Multichipanordnung und entsprechendes Herstellungsverfahren

Die vorliegende Erfindung schafft eine Multichipanordnung und ein entsprechendes Herstellungsverfahren. Die Multichipanordnung ist ausgestattet mit einem Umverdrahtungssubstrat (UV; UV'; UV''; UV'''; UV'''') mit einer Chipanbringungsseite (O; O'; O''; O'''; O''''), einem ersten Chip (C1; C1'; C1'') mit einer ersten Vorderseite (V1; V1'; V1'') und einer ersten Rückseite (R1; R1'; R1''), welcher mit der ersten Rückseite (R1; R1'; R1'') auf der Chipanbringungsseite (O; O'; O''; O'''; O'''') angebracht ist und welcher eine erste elektrische Kontaktanordnung (B1; B1'; B1") aufweist, und einem zweiten Chip (C2; C2') mit einer zweiten Vorderseite (V2; V2') und einer zweiten Rückseite (R2; R2'), welcher mit der zweiten Rückseite (R2; R2') auf der Chipanbringungsseite (O; O'; O''; O'''; O'''') angebracht ist und welcher eine zweite elektrische Kontaktanordnung (B2; B2') an der zweiten Vorderseite (V2; V2') aufweist. Der zweite Chip (C2; C2') weist an der zweiten Rückseite (R2; R2') eine Aussparung ...

Mehrfach-Bonddrahtverbund und simultanes Bonden

Verbund, enthaltend eine Isolierung und einen Bonddraht, dadurch gekennzeichnet, dass die Isolierung eine den Bonddraht teilweise einbettende Rinne aufweist, so dass eine Seite des Verbunds aus Isolation besteht und eine Seite des Verbunds eine freiliegende Bonddrahtoberfläche aufweist.

Electrically isolated power semiconductor package

SIGNAL OR LIGHTING MECHANISM FOR A MOTOR VEHICLE, WITH ELECTRONICS OF HIGH INTEGRATION COMPLEXITY

LOW-PASS FILTER AND ELECTRONIC ELEMENT

Dispositif à semi-conducteur, hermétiquement fermé, et procédé de fabrication de ce dispositif

Chip and electronic equipment

Compact topological interconnection device - localises nodes and crossovers of complex circuit formed on single layer support with connections formed by metal strips

LOW PASS FILTER AND ELECTRONIC DEVICE

METHOD OF FABRICATING A PACKAGED POWER SEMICONDUCTOR DEVICE

Semiconductor device and manufacturing method for the same

To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.

Method of making stacked die package

A method of making a stacked die package (39) includes placing a first flip chip die (16) on a base carrier (12) and electrically connecting the first flip chip die (16) to the base carrier (12). A second flip chip die (18) is attached back-to-back to the first flip chip die (16) and electrically connected to the base carrier (12) with a plurality of insulated wires (20). A mold compound (36) is formed over the first and second dice and one surface of the base carrier.

Stacked mass storage flash memory package

A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.

Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip

In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.

SYSTEMS AND METHODS FOR CROSS-OVER BOND-WIRES FOR TIA INPUT

Systems and methods are provided for improving electromagnetic interference resistance in sensor-amplifier configurations. A sensor receives a stimulus and generates a current in response to the stimulus. The current is propagated to an amplifier circuit via a pair of cross-over bond-wires creating two counter rotating loop antennae where electromagnetic interference currents induced in one loop cancel interference currents induced in the second loop such that only the sensor current is propagated to the amplifier circuit. The amplifier circuit then amplifies the propagated sensor signal.

Semiconductor device

The disclosure provides a semiconductor device. The device includes first and second substrates, first mounting layers, second mounting layers, power supply terminals, an output terminal, electroconductive coupling members and switching elements. The first substrate has first obverse and reverse surfaces facing in a thickness direction. The second substrate has a second obverse surface facing as the first obverse surface faces in the thickness direction and a second reverse surface facing away from the second obverse surface. The second substrate is spaced from the first substrate in a first direction crossing the thickness direction. The first mounting layers are electrically conductive and disposed on the first obverse surface. The second mounting layers are electrically conductive and disposed on the second obverse surface. The power supply terminals are electrically connected to the first mounting layers. The output terminal is connected to one of the second mounting layers. The electroconductive ...

RECEIVER OPTICAL MODULE AND PROCESS OF ASSEMBLING THE SAME

A receiver optical module that receives an optical signal and generating an electrical signal corresponding to the optical signal is disclosed. The module includes a photodiode (PD), a sub-mount, a pre-amplifier, and a stem. The sub-mount, which is made of insulating material, mounts the PD thereon. The pre-amplifier, which receives the photocurrent generated by the PD, mounts the PD through the sub-mount with an adhesive. The pre-amplifier generates an electrical signal corresponding to the photocurrent and has signal pads and other pads. The stem, which mounts the pre-amplifier, provides lead terminals wire-bonded with the signal pads of the pre-amplifier. The signal pads make distances against the sub-mount that are greater than distances from the other pads to the sub-mount.

Меthоd fоr idеntifуing sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, mеthоd fоr mаnufасturing sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе аnd sеmiсоnduсtоr сhip

In thе mаnufасturing prосеss оf а sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, а plurаlitу оf idеntifiсаtiоn еlеmеnts hаving thе sаmе аrrаngеmеnt аrе fоrmеd аnd thе rеlаtiоn оf mаgnitudе in а phуsiсаl аmоunt соrrеspоnding tо vаriаtiоns in thе prосеss оf thе plurаlitу оf idеntifiсаtiоn еlеmеnts is еmplоуеd аs idеntifiсаtiоn infоrmаtiоn uniquе tо thе sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе.

半導体装置及び半導体装置の製造方法

Hermetisch eingeschlossene Halbleiteranordnung

Semi-conductor structure fabrication

... 958,241. Semi-conductor devices. TEXAS INSTRUMENTS Inc. May 6, 1960 [May 6, 1959], No. 16070/60. Heading H1K. A semi-conductor body, e.g. of germanium, silicon or intermetallic alloys is attached to an insulating, e.g. ceramic base by a cement, the thermal expansion coefficient of which matches those of the ceramic and semi-conductor. The wafer is then processed and a sealed enclosure, of which the substrate forms an external wall, formed around it. In one embodiment a semiconductor wafer in ohmic contact with metal strip or silver paste electrodes 3-6 (Fig. 1), on a ceramic base 1 is stuck to the base with a thermosetting cement, containing finely-divided glass, and is subsequently formed into a junction diode combined with a centre-tapped resistor, constituted by the semi-conductor wafer itself. A metal ring 11 (Fig. 2), coated with non-conductive glaze 12, or a ceramic ring metallized on its upper surface, is mounted on a low-melting glaze ring 13 applied over electrodes 3-7 and sealed ...

Semiconductor devices

... 958,248. Semi-conductor devices. TEXAS INSTRUMENTS Inc. May 6, 1960 [May 6, 1959], No. 46089/63. Divided out of 958,242. Heading H1K. The subject-matter of this Specification is contained in Specification 958,242, but the claims are to a device comprising a plurality of semi-conductor wafers or layers on or in one surface of a substrate which provides electrical isolation between them, each wafer including a region with the electrical properties of at least part of a circuit element. An electrical interconnection, including a conductive lead attached to a wafer or layer surface remote from the substrate, is provided between two of the circuit elements. Specifications 945,734, 958,244, 958,245, 958,246, 958,247 and 958,249 also are referred to.

Low inductive wire bond chip packaging

COATED BOND WIRES FOR DIE PACKAGES AND METHODS OF MANUFACTURING SAID COATED BOND WIRES

The present invention relates to a bond wire having a metal core (202), a dielectric layer (200, 204), and a ground connectable metallization (206), wherein the bond wire has one or more vapor barrier coatings. Further, the present invention relates to a die package with at least one bond wire according to the invention.

SEMICONDUCTOR DEVICE

Leadframe, leadframe type package and lead lane

A lead lane is adapted to a leadframe of a leadframe type package. The lead lane includes a pair of first differential signal leads, a pair of second differential signal leads, a pair of third differential signal leads, a first power lead, a second power lead, and a third power lead. The pair of second differential signal leads is arranged between the pairs of first and third differential signal leads. The first power lead is arranged between the pairs of first and second differential signal leads. The second power lead is arranged between the pairs of second and third differential signal leads. The pair of third differential signal leads is arranged between the second and third power leads. The voltage provided by the first power lead is smaller than the voltage provided by the second power lead. The voltage provided by the second power lead is substantially equal to the voltage provided by the second power lead.

Stacked mass storage flash memory package

A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.

Chip package structure and method of making the same

Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame.

SEMICONDUCTOR DEVICE HAVING CONDUCTIVE WIRE WITH INCREASED ATTACHMENT ANGLE AND METHOD

A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

Semiconductor device and manufacturing method for the same

To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21 A arranged on its surface; and a first semiconductor element 11 A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10 , wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11 A (i.e., at least one of the electrodes 21 and 22 ), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.

Amplifier die with elongated side pads, and amplifier modules that incorporate such amplifier die

An embodiment of a Doherty amplifier module includes a substrate, a first amplifier die, and a second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. The first and second amplifier die each also include an elongated output pad that is configured to enable a pluralities of wirebonds to be connected in parallel along the length of the elongated output pad so that the pluralities of wirebonds extend in perpendicular directions to the first and second signal paths.

Semiconductor package having optimized wire bond positioning

Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least 50 percent of the length of the shorter of the two adjacent wires. In one embodiment, the separation distance D is at most two times a diameter of the wire having the larger diameter of the two adjacent wires. In another embodiment, the separation distance D is at most three times a wire-to-wire pitch between the two adjacent wires. Each wire grouping may include two of more closely-spaced wires. Wire groupings of closely-spaced bonding wires may be used to form, for example, power-signal-ground triplets, signal-ground pairs, signal-power pairs, or differential signal pairs or triplets.

Receiver optical module and process of assembling the same

A receiver optical module that receives an optical signal and generating an electrical signal corresponding to the optical signal is disclosed. The module includes a photodiode (PD), a sub-mount, a pre-amplifier, and a stem. The sub-mount, which is made of insulating material, mounts the PD thereon. The pre-amplifier, which receives the photocurrent generated by the PD, mounts the PD through the sub-mount with an adhesive. The pre-amplifier generates an electrical signal corresponding to the photocurrent and has signal pads and other pads. The stem, which mounts the pre-amplifier, provides lead terminals wire-bonded with the signal pads of the pre-amplifier. The signal pads make distances against the sub-mount that are greater than distances from the other pads to the sub-mount.

Semiconductor device

A semiconductor device having a plurality of pads P 11 , P 12 , P 21 , P 22 , P 31 , and P 32 on the same plane of a semiconductor chip with wires W 1 , W 2 , and W 3 connected between the pads P 11 and P 12 , P 21 and P 22 , and P 31 and P 32 , respectively, so as to be electrically isolated from each other or without contacting each other. For the crossing and electrically isolated wires W 1 and W 2 respectively having pads P 11 and P 22 that are adjacently located very close, the wires are connected so that one pad P 11 is set to be a first bonding point where a rising portion 12 of one wire W 1 is bonded, and the other pad P 22 is set to be a second bonding point to which a downwardly inclined end of the other wire W 2 opposite from its cubic interchanging crossing and electrically isolated is bonded.

Electrically isolated power semiconductor package

A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper ("DBC") substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE PROVIDED WITH SAME

It is an object of the present invention to provide a semiconductor device which allows an increase in the number of semiconductor elements mounted in parallel and prevents a shape of an insulating substrate onto which the semiconductor elements are mounted, from being laterally long, and provide a semiconductor module including such semiconductor device. A semiconductor device according to the present invention includes an insulating substrate, a metal pattern which is a continuous piece and is bonded to one main surface of the insulating substrate, and a plurality of switching elements which are bonded to a surface opposite to the insulating substrate on the metal pattern, and the plurality of switching elements are arranged in a matrix of two or more rows and two or more columns on the metal pattern.

Semiconductor device reducing risks of a wire short-circuit and a wire flow

A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.

COMPACT IMPEDANCE TRANSFORMATION CIRCUIT

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE: To prevent the failures caused by contact among bonding wires and to enable a crossing wiring and a tightly-contact wiring by using the bonding wires which are insulation-coated. CONSTITUTION: The bonding wire 5 which is insulation-coated 4 contacts an electrode 2, 2' on semiconductor chip 1, 1' to an electrode 6 of container. The bonding wire 5 insulated, for example, with a resin coating 4 is used to connected the chip 1, 1' of an integrated circuit device to the base ribbon 6. As a result, even if the bonding wires 5 come in contact with one another because of crossing of the wires or the tightly-contact wiring in which the electrode pads 2' are composed into two rows on the chip 1' in order to obtain much more electrode pads 2' and intervals among the bonding wires 5 are extremely narrow, the resin coating 4 ensures insulation among the wires and function of the wires are not lost. COPYRIGHT: (C)1986,JPO&Japio ...

CORRECTING METHOD OF WIRING OF SEMICONDUCTOR DEVICE

PURPOSE: To realize the partial correction of an internal wiring formed onto an LSI chip easily without having an adverse effect on a semiconductor element. CONSTITUTION: Opening sections 6a, 6b are formed to an insulating film 4 shaped onto a surface including aluminum wirings 5a, 5b formed onto a semiconductor substrate 1, and a metallic small-gage wire 7 composed of a conductor wire 7b, a surface of which is coated with an insulating film 7a, is stretched between the opening sections 6a, 6b, and the metallic small-gage wire 7 on the opening sections 6a, 6b is irradiated with laser beams, thus joining the metallic small-gage wire 7 with each of the aluminum wirings 5a, 5b of the opening sections 6a, 6b, then correcting the wirings. Accordingly, the connection of a long-sized correction section can easily be formed in a short time, and the lowering of the resistance of the wirings for correction, the simplification of wiring paths by the realization of crossed wirings, the avoidance of ...

Elektronikbauelement mit einem Halbleiterchip und mehreren Zuleitungen

Bauelement (100900), umfassend: einen Halbleiterchip (10) mit einer Steuerelektrode (11) und einer ersten Lastelektrode (12) auf einer ersten Oberfläche (13) und einer zweiten Lastelektrode (14) auf einer zweiten Oberfläche (15) gegenüber der ersten Oberfläche (13); einen Träger (22), über dem der Halbleiterchip (10) platziert ist, wobei die zweite Oberfläche (15) des Halbleiterchips (10) dem Träger (22) zugewandt ist; eine elektrisch an die Steuerelektrode (11) gekoppelte erste Zuleitung (16); eine elektrisch an die erste Lastelektrode (12) gekoppelte zweite Zuleitung (17); eine elektrisch an die erste Lastelektrode (12) gekoppelte dritte Zuleitung (18), wobei die dritte Zuleitung (18) von der zweiten Zuleitung (17) getrennt ist; und eine elektrisch an die zweite Lastelektrode (14) gekoppelte vierte Zuleitung (19), wobei die vierte Zuleitung (19) mit dem Träger (22) zusammenhängt, mindestens eine der zweiten und dritten Zuleitung (17, 18) zwischen der ersten und vierten Zuleitung (16, ...

Halbleitermodul

Es wird ein Halbleitermodul (100) mit einer Vielzahl von Halbleiterelementen (31, 32) angegeben, wobei die Verdrahtungslängen der nebeneinander angeordneten Halbleiterelemente (31, 32) etwa gleich sind. Der Halbleitermodul weist ein unteres Schichtsubstrat (10) und ein oberes Schichtsubstrat (20) auf, wobei eine erste und eine zweite Elektroden-Anschlußfläche, die in einer vorderen Oberfläche des unteren Schichtsubstrats ausgebildet sind, mit einem ersten und einem zweiten Leiter (12) durch einen ersten und einen zweiten Überbrückungsleiter (22) verbunden sind, die in einer rückwärtigen Oberfläche des oberen Schichtsubstrats (20) ausgebildet sind.

Interference suppression circuit for integrated circuit

The circuit has a microswitch (4) in an IC package (3). At least one supply voltage boding pad (1) is provided for connection to the supply voltage. At least one ground bonding pad (2) is provided for connection to ground potential. A supply voltage pin pair (6,7) extends out of the IC package for connection of the supply voltage and ground. A low inductance capacitor (12) is provided in the IC package. The capacitor includes capacitor connections (10,11) connected in a star-shape to the bonding pads (1,2) and the supply voltage pin pair. At least one reference potential connection (14) is connected to a earth-isolated ground plane (16).

Semiconductor devices

... 958,245. Semi-conductor devices. TEXAS INSTRUMENTS Inc. May 6, 1960 [May 6, 1959], No. 46086/63. Divided out of 958,242. Heading H1K. The subject-matter of this Specification is included in Specification 958,242, but the claims relate to a device comprising a monocrystalline semi-conductor body including a first N(P)- type region extending to one surface, a second region of P(N)-type forming a PN-junction with it extending to said surface and there defining an enclosed area, and a plurality of third regions of P(N) type forming with the first region PN-junctions, each extending to said surface and there defining enclosed areas within the first enclosed area. Ohmic contacts are provided on the first, second and third regions. Specifications 958,244, 958,246, 958,247, 958,248 and 958,249 also are referred to.

Transistors and methods of making same

... 958,246. Transistors. TEXAS INSTRUMENTS Inc. May 6, 1960 [May 6, 1959], No. 46087/63. Divided out of 958,242. Heading H1K. The subject-matter of this Specification is included in Specification 958,242, but the claims relate to a transistor comprising a semiconductor substrate forming an integral part of or bonded to a monocrystalline semi-conductor body. A collector region of P(N)-type in the body forms with an N(P)-type base region a PN-junction extending to one surface of the body and there defining a first enclosed area and an emitter region forms a second PN- junction with the base which extends to said surface and there defines a second enclosed area within the first. The base and emitter regions are formed by diffusion and ohmic contacts are provided on all three regions. Specifications 958,244, 958,245, 958,247, 958,248 and 958,249 also are referred to.

OPTO-ELECTRONIC RECEIVER

Power module

This power module has a first electrode to which a first switching element is joined on a surface, a second electrode to which a second switching element is joined on a surface, and a third electrode, which are disposed in the direction of lamination in the order of the first electrode, first switching element, second electrode, second switching element, and third electrode. The power module is characterized by having first through third electrode pieces which are electrically connected to the first through third electrodes, respectively, and first and second signal lines which are electrically connected to the first and second switch elements, respectively, and the first through third electrode pieces and first and second signal lines extending to the outside in the same plane as the second electrode.

Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops

INTERCONNECT DEVICE FOR ELECTRONIC CIRCUITS WIRE PARALLEL COUPLED, AND RELATED TOOLING AND METHOD

METHOD FOR REALIZATION Of a HYBRID CIRCUIT AND LOGICAL OR ANALOGICAL HYBRID CIRCUIT

COMPOSANT D'INTERCONNEXION TOPOLOGIQUE

L'INVENTION CONCERNE UN COMPOSANT PASSIF QUI, DANS UN CIRCUIT ELECTRONIQUE COMPLEXE, PERMET DE REALISER TOUTES LES INTERCONNEXIONS SUR UN SEUL NIVEAU DU SUPPORT DU CIRCUIT. LE COMPOSANT SELON L'INVENTION EST UN CIRCUIT MULTICOUCHES, DE PETITES DIMENSIONS PAR RAPPORT A CELLES DU SUPPORT DU CIRCUIT COMPLEXE, DANS LEQUEL SONT REGROUPES LES NOEUDS ET CROISEMENTS DU RESEAU D'INTERCONNEXION. IL EST REALISE SELON LA TECHNIQUE DES SEMI-CONDUCTEURS SUR UNE PASTILLE DE SILICIUM, OU SELON LA TECHNIQUE DE SERIGRAPHIE, PAR ALTERNANCE DE COUCHES CONDUCTRICES ET ISOLANTES. LE CIRCUIT MULTICOUCHES EST REUNI AUX CONNEXIONS EXTERNES DU BOITIER D'ENCAPSULATION PAR FILS OU BANDES METALLIQUES. APPLICATION AU REMPLACEMENT DES SUPPORTS MULTICOUCHES DES CIRCUITS COMPLEXES PAR DES SUPPORTS MONOCOUCHES ASSOCIES AU COMPOSANT TOPOLOGIQUE.

Multi-row wire bonding structure for high frequency integrated circuit

The present invention provides a multi-row wire bonding structure for high frequency integrated circuit, which includes a first electronic device, a second electronic device, a chip pad, and multiple metal lead; wherein the first electronic device is attached on the second electronic device by the chip pad, and the overlap of the first electronic device, the chip pad and the second electronic device is formed as a step. The surface of the first electronic device opposite to the chip pad is configured with the wire bonding pad at the periphery, and the coplanar wire bonding pad surrounding the wire bonding pad. The portion of the chip pad facing and exposing in the whole circle to the outside of the first electronic device is formed as a wire-like wire-bonding pad. The periphery of the second electronic device facing the chip pad and exposing in whole circle to the outside of the chip pad is configured with a plurality of pins at the positions opposite to the wire bonding pad and the coplanar ...

COMPACT IMPEDANCE TRANSFORMATION CIRCUIT

The present invention relates to an impedance transformation circuit (I10; 11 a; 11 b; 12) with a first contact pad (51) and a second contact pad (52) being spaced-apart and formed on a substrate (20). The impedance transformation circuit comprises at least first circuit element (40) providing a contact area (41) formed on the substrate (20) which is arranged adjacent and between the first (51) and the second (52) contact pad. A first 'Wire element (31) extends over the substrate (20) connecting the first contact pad (51) and a first end portion (41 a) of the contact area of the first circuit element (40), whilst at least a second wire element (32) extends over the substrate (20) connecting the second contact pad (52) and a second end portion (41b) of the contact area of the first circuit element (40). The contact area of the first circuit element (40) is shaped such that it is provided a capacitive connection with a predetermined capacitance between the contact area and a fixed reference ...

Semiconductor device for battery power voltage control

A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.

Меthоd fоr idеntifуing sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, mеthоd fоr mаnufасturing sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе аnd sеmiсоnduсtоr сhip

In thе mаnufасturing prосеss оf а sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, а plurаlitу оf idеntifiсаtiоn еlеmеnts hаving thе sаmе аrrаngеmеnt аrе fоrmеd аnd thе rеlаtiоn оf mаgnitudе in а phуsiсаl аmоunt соrrеspоnding tо vаriаtiоns in thе prосеss оf thе plurаlitу оf idеntifiсаtiоn еlеmеnts is еmplоуеd аs idеntifiсаtiоn infоrmаtiоn uniquе tо thе sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе.

Fin piece structure for heat dissipater

The present invention includes a die pad; signal leads, ground connection leads connected to the die pad; a semiconductor chip including electrode pads for grounding; metal thin wires, and an encapsulating resin for encapsulating the die pad and the semiconductor chip and encapsulating the signal leads and the ground connection lead such that lower portions of the signal leads and the ground connection lead are exposed as external terminals. The ground connection lead is connected to the electrode pad for grounding, so that the resin-encapsulated semiconductor device is electrically stabilized. Furthermore, interference between high frequency signals passing through the signal leads can be suppressed by the die pad and the ground connection leads.

СИЛОВОЙ ПОЛУПРОВОДНИКОВЫЙ МОДУЛЬ С УЛУЧШЕННОЙ СТРУКТУРОЙ КОНТАКТНЫХ СОЕДИНИТЕЛЕЙ ДЛЯ ПРИВАРИВАНИЯ

Использование: для изготовления силового полупроводникового модуля. Сущность изобретения заключается в том, что силовой модуль имеет: по меньшей мере одну подложку; по меньшей мере один размещенный на подложке силовой полупроводник, который на своей обращенной от подложки стороне имеет контактную площадку; размещенную на подложке , рядом с силовым полупроводником, при необходимости сегментированную площадку потенциала нагрузки; множество контактных соединителей для параллельного электропроводного соединения контактной площадки с площадкой потенциала нагрузки, причем каждый контактный соединитель имеет по меньшей мере одну первую контактную ножку на площадке потенциала нагрузки и имеет множество вторых контактных ножек на контактной площадке, и причем каждый контактный соединитель имеет на контактной площадке по меньшей мере один конец, причем множество контактных соединителей подразделены по меньшей мере на две группы из множества контактных соединителей с одинаковым числом контактных ножек ...

Electrically isolated power semiconductor package

COMPACT IMPEDANCE TRANSFORMATION CIRCUIT

Semiconductor device and measurement device

Semiconductor device

The invention provides a semiconductor device. The invention provides a technique of supplying a voltage generated in any of a plurality of semiconductor chips to the other chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. In an example of the main technique, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.

ELEMENT DE CONSTRUCTION ELECTRIQUE, MUNI D'UN ORGANE INDICATEUR DE DEFAUT

... a. Elément de construction électrique, muni d'un organe indicateur de défaut. b. Elément caractérisé en ce qu'un second conducteur électrique est fixé sur la même couche et sert à contrôler le fonctionnement de l'élément de construction électrique. c. L'invention trouve son application dans le domaine des éléments de construction électrique, muni d'un organe indicateur de défaut.

ELECTRIC STRUCTURAL COMPONENT, PROVIDED With an INDICATING BODY OF DEFECT

Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip

LEAD FRAME, METHOD FOR MANUFACTURING THE SAME, RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

PACKAGING LOGIC AND MEMORY INTEGRATED CIRCUITS

Logic and memory may be packaged together in a single integrated circuit package that, in some embodiments, has high input/output pin count and low stack height. In some embodiments, the logic may be stacked on top of the memory which may be stacked on a flex substrate. Such a substrate may accommodate a multilayer interconnection system which facilitates high pin count and low package height. In some embodiments, the package may be wired so that the memory may only be accessed through the logic. © KIPO & WIPO 2008 ...

High performance IC package and method

A novel wire-based intercoimect IC package is described as well as the method of designing and the method of producing the IC package. The IC package includes one or more signal carrying wires as well as ground return wires associated with each signal carrying wire to electrically couple a chip to a carrier substrate. Both the signal carrying wire and its associated ground return wires may be insulated, however at least the signal carrying wire or the ground wires are insulated. The inductance of the signal carrying wires can be kept low by keeping the wirebonds as short as possible and by positioning a number of ground wires symmetrically about and in close proximity to the signal carrying wire. The signal carrying wires and the ground return wires are connected to bond pads on the chip and to bond fingers on the carrier substrate to couple the chip to the substrate. Further, the bond pads may be staggered such that the effective pitch of the bond pads is less than the diameter of the ...

PACKAGING LOGIC AND MEMORY INTEGRATED CIRCUITS

Logic and memory may be packaged together in a single integrated circuit package that, in some embodiments, has high input/output pin count and low stack height. In some embodiments, the logic may be stacked on top of the memory which may be stacked on a flex substrate. Such a substrate may accommodate a multilayer interconnection system which facilitates high pin count and low package height. In some embodiments, the package may be wired so that the memory may only be accessed through the logic.

Packaging for high speed integrated circuits

An integrated circuit package comprises an integrated circuit die comprising N adjacent pads, where N is an integer greater than three. A substrate comprises a first pair of traces including first and second traces and a second pair of traces including third and fourth traces. The first, second, third and fourth traces include first ends spaced from the integrated circuit die and second ends adjacent to the integrated circuit die. The first and second pairs of traces carry differential signals. The third trace of the second pair of traces has a first polarity and the fourth trace of the second pair of traces has a second polarity. The third trace is located on one side of the fourth trace at the first end and is located on an opposite side of the fourth trace at the second end. N connections independently connect the second ends to N pads.

System and method for wiring electronic components in a three-dimensional manner

A system and method for wiring electronic components in a three-dimensional manner. The wiring system includes a means for temporarily placing components on a substrate, a means for directly or indirectly connecting electrodes of the components together with wires, a means for removing the temporarily-placed components from the substrate, and a means for rearranging the components in a three-dimensional manner. The movable section permits the means for bonding to bond the wires to the components from any direction in the three-dimensional space. The means for directly or indirectly connecting the electrodes of the components together with wires includes a means for placing a wiring-branch pad in a space between the electrodes of the components to be indirectly connected together, and a means for bonding the electrodes of the components to the wiring-branch pad. The means for bonding the electrodes of the components to the wiring-branch pad includes a bonding head having a capillary, and ...

Integrated circuit package having bond fingers with alternate bonding areas

A leadframe having individual bond fingers incorporating two or more alternate bonding areas. In one embodiment, conventional bond fingers having bonding areas in an outer row are augmented to include an additional conductive trace or intermediate portion terminating in a bonding area that is in general alignment with an inner row of bonding areas. Likewise, bond fingers having bonding areas in an inner row are enlarged to include an alternate bonding area that is in general alignment with the outer row of bonding areas. In another embodiment, bond fingers are arranged to provide multiple rows of closely-spaced staggered bonding areas to reduce bonding pitches. By providing alternate bonding areas in individual bond fingers, the manufacturing rules addressing staggered bond wire placement can be followed more readily, while simultaneously permitting the most convenient bond fingers to be utilized. The invention thereby adds significant flexibility to current staggered bonding techniques ...

LASER DIODE

A laser diode which can be easily assembled at low material cost is provided. A first light emitting device having a laser structure on a substrate, a second light emitting device having laser structures on a substrate, and a support base are provided. The first light emitting device and the second light emitting device are layered in this order on the support base in a manner that the respective laser structures of the first light emitting device and the second light emitting device are opposed to each other. A substrate side of the first light emitting device and a laser structure side of the second light emitting device are electrically connected to the support base.

Methods of Forming Conductive Jumper Traces

Methods of forming conductive jumper traces for semiconductor devices and packages. Substrate is provided having first, second and third trace lines formed thereon, where the first trace line is between the second and third trace lines. The first trace line can be isolated with a covering layer. A conductive layer can be formed between the second and third trace lines and over the first trace line by a depositing process followed by a heating process to alter the chemical properties of the conductive layer. The resulting conductive layer is able to conform to the covering layer and serve to provide electrical connection between the second and third trace lines.

Меthоd fоr idеntifуing sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, mеthоd fоr mаnufасturing sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе аnd sеmiсоnduсtоr сhip

In thе mаnufасturing prосеss оf а sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, а plurаlitу оf idеntifiсаtiоn еlеmеnts hаving thе sаmе аrrаngеmеnt аrе fоrmеd аnd thе rеlаtiоn оf mаgnitudе in а phуsiсаl аmоunt соrrеspоnding tо vаriаtiоns in thе prосеss оf thе plurаlitу оf idеntifiсаtiоn еlеmеnts is еmplоуеd аs idеntifiсаtiоn infоrmаtiоn uniquе tо thе sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе.

Меthоd fоr idеntifуing sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, mеthоd fоr mаnufасturing sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе аnd sеmiсоnduсtоr сhip

In thе mаnufасturing prосеss оf а sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе, а plurаlitу оf idеntifiсаtiоn еlеmеnts hаving thе sаmе аrrаngеmеnt аrе fоrmеd аnd thе rеlаtiоn оf mаgnitudе in а phуsiсаl аmоunt соrrеspоnding tо vаriаtiоns in thе prосеss оf thе plurаlitу оf idеntifiсаtiоn еlеmеnts is еmplоуеd аs idеntifiсаtiоn infоrmаtiоn uniquе tо thе sеmiсоnduсtоr intеgrаtеd сirсuit dеviсе.

Optoelectronic receiver

A light-sensitive semiconductor component (LSSC) (11) and little connection legs (LCL) (25) are cast in a casing (29) so that the LCL protrude out of the casing with each free end. A light entry surface (LES) (31) in the LSSC has a rectangular shape. The side edges of the LES assume a 45 deg. angle regarding the direction of span for the free ends of the LCL.

Semiconductor chip having external terminals connected tSemiconductor chip having external terminals connected to corresponding leads by wireso corresponding leads by wires

Bridge module

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device which can contribute to downsizing of a module substrate with respect to interconnection between electrode pads which may be directly connected with one another from a function viewpoint. SOLUTION: In the semiconductor device, a first semiconductor chip 1 and a second semiconductor chip 2 are stacked and are mounted on a module substrate 3 with their center positions laterally being deviated with respect to the module substrate 3. Electrode pads 105 on the first semiconductor chip 1, and electrode pads 205 on the semiconductor chip 2 which correspond to one another, are directly connected with one another through wires 500 where the distance is short between the end edges of the deviated semiconductor chips 1 and 2 and the end edge of the module substrate 3. Electrode pads 101 on the first semiconductor chip 1 and electrode pads 201 on the semiconductor chip 2 are directly connected with corresponding bonding leads 302, 302 on the ...

SEMICONDUCTOR MOUNTING SUBSTRATE

PURPOSE: To make it possible to obtain a wiring at the mounting process on a bonding device using an insulation-coated bonding wire as a microwiring. CONSTITUTION: A circuit is wired using an insulated wire 21, instead of a printed wiring between the electrode pads 14 on a printed wiring board 15 and the like, with which electric insulation can be obtained even when it is brought into contact with another material. As a result, by conducting a wiring operation on the printed board using the insulated wire 21 instead of the printed wiring, the wire can be used on the small mounting region on the bonding device, the problem in the manufacture of a wiring circuit using a narrow pitched and fine-line printed wiring can be solved. Also, it can realize not only a decrease in the occupation space of the wiring, but also a high-speed operation of the device by the reduction in wiring length. COPYRIGHT: (C)1994,JPO ...

Verfahren zum Verbinden mindestens zweier auf einem Halbleiterkristall eines Halbleiterbauelements in einigem Abstand nebeneinander angeordneter kleinflaechiger Elektroden mit Anschlussdraehten durch Kaltschweissen oder Thermokompression

TIEFPASSFILTER UND ELEKTRONISCHES BAUELEMENT

Multichip-Modul mit verbessertem Systemträger

Leistungshalbleiterbauteil mit einem ersten Chipträgerteil (11) und einem zweiten Chipträgerteil (12), wobei der erste Chipträgerteil (11) und der zweite Chipträgerteil (12) zueinander beabstandet sind und jeweils elektrisch leitend sind. Ein erster Chip mit einem Leistungstransistor ist auf dem ersten Chipträgerteil (11) und ein zweiter Chip (14) ist auf dem zweiten Chipträgerteil (12) aufgebracht. Der Anschluss für ein erstes Potenzial (DC-) einer Versorgungsspannung ist mit dem ersten Chip (13) über den ersten Chipträgerteil und der Anschluss für das zweite Potenzial einer Versorgungsspannung (DC+) ist mit dem zweiten Chip (14) über den zweiten Chipträgerteil elektrisch verbunden.

Electrically isolated power semiconductor package

A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper ("DBC") substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.

Integrated circuit wire formed for welding

A process for welding a wire 100 to sheet material 130 of a printed circuit board, where the wire is deformed before welding. The end 102 of the wire 100 may form: a general wedge shape; a flat side 104 which contacts the sheet material during welding; or, a shape which is complimentary to the shape of the sheet material it contacts. A transition area 108 may be formed between the end 102 and a generally round portion 112 of the wire 100, the transition area 108 being modeled based on at least one of: the amount of deformation; an amount of remaining section; and, the stress concentration near the transition area 108. Both the wire 100 and the sheet material 130 may be formed from a range of metals or alloys. The wire 100 may be annealed with heat treatment.

Semiconductor circuits

... 958,249. Semi-conductor circuits. TEXAS INSTRUMENTS Inc. May 6, 1960 [May 6, 1959], No. 46090/63. Divided out of 958,242. Heading H1K. The subject-matter of the Specification is included in Specification 958,242. The claims relate to a circuit comprising a monocrystalline semi-conductor wafer containing a plurality of first regions, each of which overlies a second region with which it forms a PN-junction extending to a major wafer face and there defining an enclosed area. The wafer includes an elongated portion providing a current path parallel to said face with one end connected to a bias potential and the other ohmically connected to said second regions. Input connections are provided on the first regions. Specifications 945,734, 945,737, 958,244, 958,245, 958,246, 958,247 and 958,248 also are referred to.

Semiconductor device

A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads A, B and C are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires A, B and C, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.

Semiconductor device and manufacturing method thereof

Bistable multivibrator of a miniature network with semiconductor

METHOD OF DETERMINING ORDER OF WIRE BONDING

엇갈린 다이 및 와이어 본딩을 포함하는 다이 스택 배열을 갖는 반도체 디바이스

... 반도체 다이 패키지가 설명된다. 반도체 패키지의 예시는 반도체 다이의 제2 그룹과 배치되는 반도체 다이의 제1 그룹을 포함한다. 제1 및 제2 그룹에서 다이는 제1 축을 따라 서로로부터 오프셋되고, 제1 축에 직교하는 제2 축을 따라 서로에 대해 엇갈린다. 반도체 패키지의 제2 예시는 불규칙한 형상의 에지 및 패키지에서 최하위 반도체 다이보다 위의 반도체 다이로부터 기판으로 와이어 본드를 포함한다.

Semiconductor device and capsule type semiconductor package

An interposer substrate having electrodes on the front surface and on the rear surface thereof, respectively, is prepared, and at least one memory chip having electrodes connected to an internal circuit is prepared. Then, the rear surface of the memory chip is bonded to the front surface of the interposer substrate, and the memory chip is sealed to the front surface of the interposer substrate to constitute an encapsulated capsule type semiconductor package. On the other hand, a logic chip is prepared. Further, a main substrate is prepared in which electrodes are formed on the front surface and on the rear surface, respectively, and desired internal connections are provided between these electrodes. Then, the capsule type semiconductor package and the logic chip are laminated on the main substrate, and desired connections are provided between the electrodes on the rear surface of the interposer substrate of the capsule type semiconductor package, the electrodes of the logic chip and the ...

Stacked mass storage flash memory package

A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of a stacked mass storage flash memory package.

Semiconductor integrated circuit device

A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.

Doherty amplifiers and amplifier modules with shunt inductance circuits that affect transmission line length between carrier and peaking amplifier outputs

A Doherty amplifier module includes first and second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. A phase shift and impedance inversion element is coupled between the outputs of the first and second amplifier die. A shunt inductance circuit is coupled to the output of either or both of the first and/or second amplifier die. Each shunt inductance circuit at least partially resonates out the output capacitance of the amplifier die to which it is connected to enable the electrical length of the phase shift and impedance inversion element to be increased.

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Resin-Encapsulated Semiconductor Device

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Integrated circuit packaging system with die paddle and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

Systems and Methods for Heat Dissipation Using Thermal Conduits

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

Semiconductor device with less power supply noise

A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Semiconductor device

A semiconductor device includes a first semiconductor chip 1 , a second semiconductor chip 4 , a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4 . A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.

Multi-chip package with offset die stacking

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Control device of semiconductor device

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

Semiconductor device and manufacturing method of the same

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Method of making a semiconductor chip assembly with a post/base heat spreader and a substrate using grinding

A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Integrated Power Converter Package With Die Stacking

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

Milli-meter-wave-wireless-interconnect (m2w2 - interconnect) method for short-range communications with ultra-high data capability

A millimeter wave wireless (M2W2) interconnect is used for transmitting and receiving signals at millimeter-wave frequencies for short-range wireless communication with high data rate capability. The transmitter and receiver antennae may comprise an on-chip differential dipole antenna or a bond wire differential dipole antenna. The bond wire differential dipole antenna is comprised of a pair of bond wires connecting between a pair of pads on an integrated circuit (IC) die and a pair of floating pads on a printed circuit board (PCB).

Pressure sensor

A pressure sensor has a sensor body at least partly formed with an electrically insulating material, particularly a ceramic material, defining a cavity facing on which is a diaphragm provided with an electric detector element, configured for detecting a bending of the diaphragm. The sensor body supports a circuit arrangement, including, a plurality of circuit components, among which is an integrated circuit, for treating a signal generated by the detection element. The circuit arrangement includes tracks made of electrically conductive material directly deposited on a surface of the sensor body made of electrically insulating material. The integrated circuit is made up of a die made of semiconductor material directly bonded onto the surface of the sensor body and the die is connected to respective tracks by means of wire bonding, i.e. by means of thin connecting wires made of electrically conductive material.

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Magnetic shielding for multi-chip module packaging

A system comprises a plurality of stacked integrated circuit dice, each integrated circuit die comprising at least one circuit, a package enclosing the plurality of dice, and at least two magnetic shields configured to magnetically shield the at least one circuit of each of the plurality of integrate circuit dice. At least one of the magnetic shields is within the package, and at least two of the plurality of stacked integrated circuit dice are positioned between the at least two magnetic shields.

Method for semiconductor leadframes in low volume and rapid turnaround

A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

Module housing and method for manufacturing a module housing

A module housing having an inner housing, an outer housing and a connection element is provided, the inner housing having at least one component and being completely enclosed by the outer housing in a form-locking manner, and the connection element being enclosed in a first subsection by the inner housing in a form-locking manner, wherein the connection element has electrical plug contacts in a third subsection.

Radiofrequency amplifier

An integrated radiofrequency amplifier with an operational frequency includes first and second Doherty amplifiers each having a main device, and a peak device connected at respective inputs and outputs by respective phase shift elements configured to provide a 90 degree phase shift at the operational frequency. An input of the amplifier is connected to the input of the main device of the first Doherty amplifier, an output of the amplifier is connected to the outputs of the peak devices of the first and second Doherty amplifiers and the input of the peak device of the first Doherty amplifier is connected to the input of the main device of the second Doherty amplifier by a phase shift element providing a 90 degree phase shift at the operational frequency.

Semiconductor Device

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Printed circuit board

A power source terminal and a ground terminal for a semiconductor integrated circuit are connected to a conductor pattern through a capacitor. The conductor pattern is connected, through a filter, to a plane conductor connected to neither a ground plane nor a power source plane. Thus, a common mode noise arising from between the power source and the ground is caused to flow into the plane conductor. This reduces the common mode noise flowing in the ground and the power source of the printed wiring board, which relatively act as antennas.

Semiconductor package and method of fabricating the same

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

Method for manufacturing semiconductor device

A method of manufacturing a semiconductor device comprises: preparing a lead frame including a package external region and a package internal region, a burred surface being provided at a top end of a side of the lead frame, and a fracture surface being provided in the vicinity of the top end of the side; chamfering the top end of the side in the package external region; mounting a semiconductor element on the lead frame and sealing the semiconductor element with mold resin in the package internal region; and removing resin burr provided on the side of the lead frame in the package external region after the chamfering and the sealing.

Charging and Communication System for a Battery-Powered Microstimulator

A system and method are provided for both recharging and communicating with a stimulator having a rechargeable battery, which stimulator is implanted deeply in the body, in particular where the stimulator is a microstimulator, the system includes a base station and an external device, for instance a chair pad. The chair pad may contain an antenna/charging coil and a booster coil. The antenna/charging coil can be used for charging the rechargeable battery and also for communicating with the stimulator using frequency shift keying and on-off keying. The booster coil can be used to recharge a battery depleted to zero volts. The base station connected to the chair pad may be used to power the antenna/charging coil and the booster coil.

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Integrated circuit package including miniature antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

Semiconductor device

Miniaturization and acceleration of the operating speed of a System In Package (SIP) type semiconductor device in which a memory chip and a microcomputer chip are mounted over a wiring board are promoted. When mounting a microcomputer chip and a memory chip over an upper surface of a wiring board, the memory chip is disposed such that second conductive pads of the wiring board arranged along a first chip side (a side along which data system electrode pads are arranged) of the memory chip are positioned, in the plan view, in a region between an extended line of a third chip side of the microcomputer chip and an extended line of a fourth chip side of the microcomputer chip. Thus, a length of a data system wiring for coupling a data system electrode pad of the microcomputer chip with the data system electrode pad of the memory chip is minimized.

Systems and methods for three-axis sensor chip packages

Systems and methods for three-axis sensor chip packages are provided. In one embodiment, a directional sensor package comprises: a base; a first sensor die mounted to the base, the first sensor die having a first active sensor circuit and a first plurality of metal pads electrically coupled to the first active sensor circuit; a second sensor die mounted to the base, the second sensor die having a second active sensor circuit located on a first surface, and a second plurality of metal pads electrically coupled to the second active sensor circuit located on a second surface. The second sensor die is positioned such that the second active sensor circuit is oriented orthogonally with respect to the first active sensor circuit region and is perpendicular to the base. The second surface is adjacent to the first surface and angled with respect to a plane of the first surface.

Solar cell assembly ii

The present invention relates to a solar cell assembly that includes a solar cell attached to a bonding pad and a cooling substrate, wherein the bonding pad is attached to a surface of the cooling substrate by a thermally conductive adhesive and electrically contacted to the bonding pad and cooling substrate by a bonding wire. Alternatively, the bonding pad is attached to a surface of the cooling substrate by a thermally and electrically conductive adhesive.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Apparatus and methods for electronic amplification

Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved.

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Method of manufacturing semiconductor device

Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow.

Impedence controlled packages with metal sheet or 2-layer rdl

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

System and Method for Wafer Level Packaging

In an embodiment, a semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first cavity disposed through it, and conductive material covers at least the bottom portion of the first cavity. An integrated circuit is disposed on the top surface of the conductive material. The device further includes a cap disposed on the top surface of the substrate, such that a cavity disposed on a surface of the cap overlies the first cavity in the substrate.

Substrate For Integrated Modules

A method of fabricating a plurality of components using wafer-level processing can include bonding first and second wafer-level substrates together to form a substrate assembly, such that first surfaces of the first and second substrates confront one another, the first substrate having first electrically conductive elements exposed at the first surface thereof, forming second electrically conductive elements contacting the first conductive elements, and processing the second substrate into individual substrate elements. The second conductive elements can extend through a thickness of the first substrate and can be exposed at a second surface thereof opposite the first surface. The processing can include trimming material to produce the substrate elements at least some of which have respective different controlled thicknesses between first surfaces adjacent the first substrate and second surfaces opposite therefrom.

Direct conversion x-ray detector with radiation protection for electronics

The present invention relates to an X-ray detector having an X-ray sensor (first X-ray sensor) converting X-radiation directly into electric charge carriers, having signal evaluation electronics electrically connected to the X-ray sensor and preferably formed as integrated circuit(s), having an X-ray absorber formed for protecting the signal evaluation electronics, and having a sensor carrier (first sensor carrier) formed and arranged for positioning the X-ray sensor relative to the X-ray absorber, wherein, viewed in the direction of incidence of the X-radiation, both the signal evaluation electronics are arranged behind the X-ray absorber and in the X-radiation shadow thereof and the X-ray sensor is admittedly likewise positioned by means of the sensor carrier preferably arranged between the X-ray absorber and the signal evaluation electronics at least sectionally behind the X-ray absorber, but outside the X-radiation shadow thereof.

Bonded wire semiconductor device

A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.

Disguising test pads in a semiconductor package

A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.

Multiple die in a face down package

A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Semiconductor device

A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

Semiconductor device and connection checking method for semiconductor device

A semiconductor device includes a substrate, a first land formed in a first surface of the substrate, a second land formed in a second surface of the substrate, a first terminal coupled to the second land, a line coupled to the first land and the second land, a second terminal formed in the second surface of the substrate and a branch line coupled to the line and the second terminal. The second terminal is coupled to the first land and the second land and is not coupled to other lands in the first surface. The second surface is different surface from the first surface.

Multiple die stacking for two or more die

A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.

Methods of manufacturing semiconductor device assemblies including face-to-face semiconductor dice

Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. Conductive structures are structurally and electrically coupled to bond pads of a second semiconductor die. At least some of the conductive structures are aligned with at least some of the bond pads of the first semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. At least some of the conductive structures are structurally and electrically coupled to at least some of the bond pads of the first semiconductor die.

Semiconductor device and manufacturing method therefor

A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip.

Structure for High-Speed Signal Integrity in Semiconductor Package with Single-Metal-Layer Substrate

A semiconductor chip ( 101 ) with bond pads ( 110 ) on a substrate ( 103 ) with rows and columns of regularly pitched metal contact pads ( 131 ). A zone comprises a first pair ( 131 a, 131 b ) and a parallel second pair ( 131 c, 131 d ) of contact pads, and a single contact pad ( 131 e ) for ground potential; staggered pairs of stitch pads ( 133 ) connected to respective pairs of adjacent contact pads by parallel and equal-length traces ( 132 a, 132 b , etc.). Parallel and equal-length bonding wires ( 120 a, 120 b , etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

Doped 4n copper wires for bonding in microelectronics devices

A doped 4N copper wire for bonding in microelectronics contains one or more corrosion resistance dopant materials selected from Ag, Ni, Pd, Au, Pt, and Cr. A total concentration of the corrosion resistance dopant materials is between about 10 wt. ppm and about 80 wt. ppm.

Semiconductor device

A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Method of forming a semiconductor device and leadframe therefor

In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

Semiconductor device

A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

Manufacturing method for electronic device and electronic device manufacturing apparatus

An electronic device manufacturing apparatus is disclosed. The electronic device manufacturing apparatus includes a vacuum chamber, a support part, a moving part, and a heating part. The support part is located in the vacuum chamber and has a first placement surface on which a first member is to be placed. The moving part is located in the vacuum chamber and has a second placement surface on which a second member is to be placed. The moving part is movable between a first position where the first placement surface and the second placement surface do not face each other when seen in plan view and a second position where the first placement surface and the second placement surface face each other when seen in plan view. The heating part heats the first member and the second member.

Processes and structures for IC fabrication

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Complex Semiconductor Packages and Methods of Fabricating the Same

Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips.

Semiconductor package, and information processing apparatus and storage device including the semiconductor packages

According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer.

Semiconductor devices including electromagnetic interference shield

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

Semiconductor packages

A semiconductor package includes a master chip and a slave chip stacked on a substrate. The master chip and the slave chip are connected to one another by a bonding wire. The master chip and the slave chip are connected in series with an external circuit. The semiconductor package may have a low loading factor and excellent performance, and may be mass produced at low costs.

Device

A semiconductor device includes a wiring board, a first semiconductor chip mounted on the wiring board via a first adhesive member, and second semiconductor chip stacked on the first semiconductor chip via a second adhesive member. The first adhesive member is a die attach film having an adhesive layer formed on both surfaces of an insulating base, and the second adhesive member is an adhesive paste.

Monolithic Power Converter Package

According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip.

Power recovery circuit based on partial standing waves

A power recovery system includes a transmission line that is coupled to transfer an RF signal received via an antenna. The RF signal generates a partial standing wave in the transmission line and the transmission line has at least one standing wave anti-node. A power recovery circuit converts an anti-node signal from the at least one standing wave anti-node to a power signal.

Semiconductor device

A semiconductor device according to an embodiment includes: first and second semiconductor chips, each including a first electrode and a second electrode opposite to each other in a predetermined direction; a chip-mount substrate on which the first and second semiconductor chips are mounted; and a first wiring terminal to which the second electrodes of the first and second semiconductor chips are connected. The second semiconductor chip lies over the first semiconductor chip in the predetermined direction such that the second electrode of the first semiconductor chip and the second electrode of the second semiconductor chip face each other across the first wiring terminal, and the chip-mount substrate is bent such that the first electrode of the first semiconductor chip is connected to the first electrode of the second semiconductor chip.

System on Chip for Power Inverter

According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.

Semiconductor device

A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

Semiconductor device and production method of the same

A semiconductor device capable of performing sufficient power supply while suppressing an increase in a manufacturing cost. The semiconductor device has a semiconductor substrate, a multilayer interconnection layer provided over the semiconductor substrate, an Al wiring layer that is provided over the multilayer interconnection layer and has pad parts, and a redistribution layer that is provided over the Al wiring layer and is coupled with the Al wiring layer, in which the redistribution layer is comprised of a metal material whose electric resistivity is lower than that of Al and is not formed over the pad parts.

Circuit device

A circuit device having superior voltage resistance is provided. A structure is achieved that omits the resin layer that is normally provided to the top surface of a circuit board. Specifically, a ceramic substrate ( 22 ) is disposed on the top surface of a circuit board ( 12 ) comprising a metal, and a transistor ( 34 ) such as an IGBT is mounted to the top surface of the ceramic substrate ( 22 ). As a result, the transistor ( 34 ) and the circuit board ( 12 ) are insulated from each other by the ceramic substrate ( 22 ). The ceramic substrate ( 22 ), which comprises an inorganic material, has an extremely high voltage resistance compared to the conventionally used insulating layer comprising resin, and so even if a high voltage on the order of 1000V is applied to the transistor ( 34 ), short circuiting between the transistor ( 34 ) and the circuit board ( 12 ) is prevented.

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Semiconductor power module and method of manufacturing the same

A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Thermally Enhanced Semiconductor Package with Conductive Clip

One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.

Sgs or gsgsg pattern for signal transmitting channel, and pcb assembly, chip package using such sgs or gsgsg pattern

A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.

Supply voltage or ground connections including bond pad interconnects for integrated circuit device

Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond pads on an integrated circuit die may be connected together via one or more electrically conductive interconnects.

Thin Leadframe QFN Package Design of RF Front-Ends for Mobile Wireless Communication

Systems and methods are disclosed herein for a low cost, compact size, and thin half-etched leadframe quad-flat no-leads (QFN) package that integrates RF passive elements in the QFN leadframe for linearized PA design and RF FEMs. The integrated RF passive elements in the QFN leadframe may include RF inductors (e.g., meanders lines or spirals) for amplifier bias or RF matching, extension bar of the ground paddle for inter-stage matching or jumper pads for connection. The integrated RF passive elements may also include transmission lines for output power matching, coupled line structures such as RF couplers, RF divider or combiner realized using transmission lines with proper impedance and length, jumper pads for adjusting the bond wire length, etc. The RF parameters of the integrated passive elements are adjustable using different length and number of wire bond for fine tuning the performance of the PAM or the RF FEM.

Method of manufacturing semiconductor device

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

Die-to-die electrical isolation in a semiconductor package

Some of the embodiments of the present disclosure provide a semiconductor package comprising a first die; a second die; and an inductor arrangement configured to inductively couple the first die and the second die while maintaining electrical isolation between active circuit components of the first die and active circuit components of the second die. Other embodiments are also described and claimed.

Stacked die power converter

A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Method for manufacturing optical image stabilizer employing scratch drive actuator

A method for an optical image stabilizer including: providing an SOI wafer substrate which has a plurality of cells, the SOI wafer substrate including an insulating layer, and first and second silicon layers disposed on both sides of the insulating layer; forming scratch drive arrays and supporting members on each of the cells by etching the first silicon layer; forming the table through cells' separation by etching the second silicon layer and the insulating layer; removing the insulating layer interposed between the scratch drive arrays and the table; mounting the image sensor on the table; forming the substrate which has an electrode layer corresponding to the scratch drive arrays; and assembling the table with the image sensor and the scratch drive arrays on the substrate having the electrode layer in such a manner that the scratch drive arrays face the electrode layer each other.

Semiconductor device including semiconductor chip mounted on lead frame

A semiconductor device includes a lead frame, a semiconductor chip, a substrate, a plurality of chip parts, a plurality of wires, and a resin member. The lead frame includes a chip mounted section and a plurality of lead sections. The semiconductor chip is mounted on the chip mounted section. The substrate is mounted on the chip mounted section. The chip parts are mounted on the substrate. Each of the chip parts has a first end portion and a second end portion in one direction, and each of the chip parts has a first electrode at the first end portion and a second electrode at the second end portion. Each of the wires couples the second electrode of one of the chip parts and one of the lead sections. The resin member covers the lead frame, the semiconductor chip, the substrate, the chip parts, and the wires.

Efficient Linear Integrated Power Amplifier Incorporating Low And High Power Operating Modes

A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Systems and methods related to ablation during manufacture of radio-frequency modules

Disclosed are systems and methods related to removal of materials by techniques such as ablation during manufacture of radio-frequency (RF) modules. Such modules can be manufactured in an array on a panel, and an overmold structure can be formed on the panel. In some situations, it can be desirable to remove a portion of an upper surface of the overmold to, for example, better expose upper portions of shielding wirebonds. In some embodiments, an ablation system can include a blasting apparatus configured to provide a stream of ablating particles to a blasting region. A first transport section that moves a panel through the blasting region can be separate from a second transport section that feeds or removes the panel to or from the first transport section. Such a configuration can substantially isolate the second transport section from the stream of ablating particles.

Solid-state image pickup element and solid-state image pickup element mounting structure

A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.

Integrated circuit package

An integrated circuit package and a manufacturing method thereof are provided. The integrated circuit package can include a substrate provided with a circuit pattern, a first set of bonding fingers and a second set of bonding fingers, a first chip stack mounted on the substrate and having a plurality of first semiconductor chips stacked in a first direction in a stepped manner, each of the first semiconductor chips being provided with a first bonding pad at an end thereof on one side, a second chip stack mounted on the first chip stack and having a plurality of second semiconductor chips stacked in a second direction opposite to the first direction in a stepped manner.

Power semiconductor module

A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

Semiconductor package having wire bond wall to reduce coupling

A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

Transceiver and interface for ic package

An interconnect system includes a first circuit board, first and second connectors connected to the first circuit board, and a transceiver including an optical engine and arranged to receive and transmit electrical and optical signals through a cable, to convert optical signals received from the cable into electrical signals, and to convert electrical signals received from the first connector into optical signals to be transmitted through the cable. The transceiver is arranged to mate with the first and second connectors so that at least some converted electrical signals are transmitted to the first connector and so that at least some electrical signals received from the cable are transmitted to the second connector.

Semiconductor device

A semiconductor device according to an embodiment includes a normally off transistor having a first source, a first drain, a first gate connected to a common gate terminal, and a body diode, a normally on transistor having a second source connected to the first drain, a second drain, and a second gate, a capacitor provided between the common gate terminal and the second gate, a first diode having a first anode connected to between the capacitor and the second gate and a first cathode connected to the first source, and a second diode having a second anode connected to the first source and a second cathode connected to the second drain.

SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented. 1. A semiconductor device comprising:a substrate with a surface;a first circuit on the substrate and comprising a plurality of electrical components, including a first transistor, and a first wire bond array electrically coupled between the first transistor and a first lead;a second circuit on the substrate and comprising a plurality of electrical components, including a second transistor, and a second wire bond array electrically coupled between the second transistor and a second lead; andan isolation wall formed of electrically conductive material and located between the first circuit and the second circuit in an air cavity above the surface of the substrate, the isolation wall formed of a body of material that is oriented perpendicular to the surface of the substrate and extending above a height of the first and second wire bond arrays, the isolation wall being configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit, wherein the isolation wall is formed by a section of a lead frame for the semiconductor device, and wherein the lead frame also includes the first lead and the second lead.2. The semiconductor device as recited in claim 1 , wherein the lead frame is formed by an electrically conductive sheet claim 1 , and the isolation wall is formed by a section of the lead frame that is ...

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate. 1. A packaged microelectronic device , comprising:an interposer substrate having a first side with a plurality of interposer contacts and a second side opposite the first side, the second side including a plurality of interposer pads arranged in an array corresponding to a standard JEDEC pinout;a microelectronic die attached and electrically coupled to the interposer substrate;a casing covering the die and at least a portion of the interposer substrate, wherein the casing has a thickness and a top facing away from the interposer substrate; anda plurality of electrically conductive through-casing interconnects in contact with and projecting from corresponding interposer contacts, wherein the through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing, and wherein the through-casing interconnects are at least partially encapsulated in the casing,wherein the through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a lead frame comprising a first terminal and a second terminal for grounding, a sealing resin which covers the lead frame, an exposed part which is a part of the second terminal and is exposed from the sealing resin and a conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part. 1. A semiconductor device comprising:a lead frame comprising a first terminal and a second terminal for grounding;a sealing resin which covers the lead frame;an exposed part which is a part of the second terminal and is exposed from the sealing resin; anda conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part.2. The semiconductor device according to claim 1 ,wherein the first terminal and the second terminal are arranged at an end of the semiconductor device,the second terminal is higher than the first terminal at the end, andthe sealing resin comprises a thin wall part at the end, whose height is equal to that of the second terminal at the end.3. The semiconductor device according to claim 2 ,wherein the second terminal comprises:a third terminal which is comprised by the lead frame and has the same height as the first terminal; anda conductive piece which is disposed on the surface of the third terminal.4. The semiconductor device according to claim 2 ,wherein the lead frame comprises a die pad for mounting a semiconductor chip, andthe second terminal is electrically conducted with the die pad.5. The semiconductor device according to claim 2 ,wherein the exposed part and the thin wall part are formed so as to enclose the semiconductor chip, andthe conductive material covers the surfaces of the exposed part and the thin wall part which enclose the semiconductor chip.6. The semiconductor device according to claim 1 ,wherein the second terminal is higher than the first terminal,the second terminal is aligned with the sealing resin in ...

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode. 1. A semiconductor component having at least first and second terminals , comprising:a leadframe having first and second opposing sides, a device receiving area, and a first lead integrally formed with the leadframe;an insulated metal substrate having a first surface and a second surface, the second surface coupled to the leadframe;a first semiconductor chip mounted to the insulated metal substrate, the first semiconductor chip having first and second surfaces, a first gate bond pad, a first source bond pad, and a first drain bond pad, the first semiconductor chip configured from a III-N semiconductor material, wherein the second surface of the first semiconductor chip is coupled to the insulated metal substrate; anda second semiconductor chip mounted to the first semiconductor chip and having first and second surfaces, an anode formed from the first surface and a cathode formed from the second surface, wherein the cathode is coupled to the first source bond pad.2. The semiconductor component of claim 1 , further including a second lead that is electrically isolated from the leadframe and wherein the first gate bond pad is electrically coupled to ...

Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops

A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

MAGNETIC MEMORY DEVICE

According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces. 1. A magnetic memory device comprising:a magnetic memory chip having a magnetoresistive element;a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip;a circuit board on which the magnetic layer is mounted; anda bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces,wherein the first portion is nearer the circuit board than the second portion,each of the first and second portions has a size larger than a size of the magnetic memory chip in the first direction, andone of the first and second portions covers side surfaces of the magnetic memory chip in a second direction parallel to the first and second main surfaces and orthogonal to the first direction.2. The device of claim 1 , whereinthe first and second portions have first and second ends respectively in the second direction, and a space between the first and second portions is narrowest in the first and second ends.3. The device of claim 1 , whereinthe second portion covers the side surfaces of the magnetic memory chip.4. The device of claim 3 , further comprising:a spacer between the magnetic memory chip and the second portion.5. The device ...