Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Power/ground layout for chips

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Chip scale surface mounted semiconductor device package and process of manufacture

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND POWER CONVERSION APPARATUS

A semiconductor module includes a substrate, a semiconductor element, and a wire. The semiconductor element is joined onto the substrate and has a surface electrode. Both ends of the wire are bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element. The wire is electrically connected to the surface electrode. 1: A semiconductor module comprising:a substrate;a semiconductor element joined onto the substrate and having a surface electrode;a wire, both ends of the wire being bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element;a conductor joined onto the surface electrode; anda joining member arranged on the conductor and having electrical conductivity,the wire being electrically connected to the surface electrode by the conductor and the joining member, the wire being separated from the conductor and embedded in the joining member.2: The semiconductor module according to claim 1 , whereinthe substrate includes an insulating layer and a conductor pattern provided on the insulating layer,the conductor pattern includes a first conductor portion and a second conductor portion,the semiconductor element is arranged between the first conductor portion and the second conductor portion, anda first end of the both ends of the wire is bonded to the first conductor portion, and a second end of the both ends of the wire is bonded to the second conductor portion.3. (canceled)4: A semiconductor module comprising:a substrate;a semiconductor element joined onto the substrate and having a surface electrode;a wire, both ends of the wire being bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element, the wire being electrically connected to the surface electrode;a conductor joined onto the surface electrode; anda joining member arranged on the conductor and having electrical conductivity,the wire being joined by the conductor and the ...

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. 113-. (canceled)14. A manufacturing method of a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer equipped with a plurality of device formation regions,each device formation region having a semiconductor circuit, a pad electrically coupled to the semiconductor circuit, a first insulating film formed over the pad such that a surface portion of the pad is exposed from an opening of the first insulating film, and a second insulating film formed over the first insulating film such that the surface portion of the pad is exposed from the second insulating film;(b) contacting a probe needle to a first region of the surface portion of the pad of each device formation region; and(c) after the step (b), forming an interconnect layer over a second region of the surface portion of each pad adjacent to the first region by plating, such that the interconnect layer is electrically coupled to the pad at the second region.15. The manufacturing method of a semiconductor device according to claim 14 , further comprising the steps of:(d) after the step (c), coupling a conductive member to one end portion of the ...

SEMICONDUCTOR DEVICE HAVING LOW ON RESISTANCE

A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad. 1. A semiconductor device , comprising:a semiconductor chip including a field effect transistor, having a main surface over which a source electrode and a gate electrode of the field effect transistor are formed, and having a second main surface on which a drain electrode of the field effect transistor is formed, the second main surface being opposed to the first main surface;a metal-made support board having a top surface and a bottom surface opposite the top surface, the semiconductor chip being mounted over the top surface such that the drain is fixed to the top surface of the metal-made support board via a conductive adhesive material;a source lead electrically connected with the source electrode of the semiconductor chip via a plurality of source conductors;a gate lead electrically connected with the gate electrode of the semiconductor chip via a gate conductor;a drain lead formed contiguously with the metal-made support board; anda sealing body sealing the semiconductor chip, andwherein, in plan view, the metal-made support board has a first side and a second side opposite the first side,wherein, in plan view, the sealing body having a third side that is extended along the first side of the metal-made support board,wherein, in plan view, ...

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first package;a second pad on a second surface of a second package;a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , wherein the first package comprises a first substrate and a first integrated circuit die attached to the first substrate claim 1 , wherein the second package comprises a second substrate and a second integrated circuit die attached to the second substrate.3. The device of claim 2 , wherein the metallic element is laterally adjacent the first integrated circuit die with the first integrated circuit die and the metallic element being interposed between the first substrate and the second substrate.4. The device of claim 3 , wherein the metallic element extends closer to the second substrate than the first integrated circuit die.5. The device of claim 1 , wherein a height of the metallic element is between about 20 micrometers and about 200 ...

PACKAGE STRUCTURE INTEGRATING A START-UP COMPONENT, A CONTROLLER, AND A POWER SWITCH

A package structure integrating a start-up component, a controller, and a power switch for a power converter, wherein the power converter has a coil having a first end and a second end, and the first end is coupled to a rectifier, the package structure including: a first die pad for carrying a chip of the controller; a second die pad for carrying a chip of the start-up component and a chip of the power switch, wherein the chip of the start-up component has a bottom surface providing a first drain contact; and the chip of the power switch has a bottom surface providing a second drain contact; and a plurality of external connection leads, of which one is connected with the second die pad via a wire and is used to couple with the second end of the coil. 1. A package structure integrating a start-up component , a controller , and a power switch for a power converter , wherein said power converter has a coil for transferring power , said coil has a first end and a second end , and said first end is coupled to a rectifier , said package structure comprising:a first die pad made of a conductor, used for carrying a chip of said controller;a second die pad made of said conductor, used for carrying a chip of said start-up component and a chip of said power switch, wherein said chip of said start-up component has a top surface providing a first gate contact and a first source contact, and a bottom surface providing a first drain contact which is electrically connected with said second die pad; and said chip of said power switch has a top surface providing a second gate contact and a second source contact, and a bottom surface providing a second drain contact which is electrically connected with said second die pad;a plurality of external connection leads, wherein one of said plurality of external connection leads is connected with said second die pad via a wire and is used to couple with said second end of said coil; anda resin material, used to enclose said chip of said ...

Semiconductor package having a multi-channel and a related electronic system

A substrate including internal interconnections, first and second finger electrodes, and having first to fourth quadrants. External terminals are formed on the substrate and connected to the first and second finger electrodes via the internal interconnections. A first tower including first semiconductor chips is formed on the substrate. First conductive wires are formed between the first semiconductor chips and the first finger electrodes. A second tower including second semiconductor chips is formed on the substrate. Second conductive wires are formed between the second semiconductor chips and the second finger electrodes. The external terminals include a first group connected to the first finger electrodes and configuring a channel, and a second group connected to the second finger electrodes, and configuring another channel. The first finger electrodes are formed on the third quadrant, and the second finger electrodes are formed on the first quadrant.

Semiconductor Device, Electronic Component and Method

In an embodiment, a semiconductor device includes a galvanically isolated signal transfer coupler having a contact pad. The contact pad includes a metallic base layer, a metallic diffusion barrier layer arranged on the metallic base layer, and a metallic wire bondable layer arranged on the metallic diffusion barrier layer. The metallic diffusion barrier layer includes a first portion and a second portion. The first portion has a first surface and a second surface opposing the first surface. The first surface has a curved surface at the periphery. The first portion extends in a transverse plane and has a width. The second portion protrudes from the second surface intermediate the width of the first portion.

Stack type semiconductor package

A stack type semiconductor package includes a lower semiconductor package including a lower package substrate and at least one lower semiconductor chip disposed on the lower package substrate; an upper semiconductor package including an upper package substrate larger than the lower package substrate and at least one upper semiconductor chip disposed on the upper package substrate; an inter-package connector connecting an upper surface of the lower package substrate to a lower surface of the upper package substrate; and a filler filling in between the lower package substrate and the upper package substrate while substantially surrounding the inter-package connector.

Laser ablation for wire bonding on organic solderability preservative surface

A printed circuit board is disclosed. The printed circuit board includes: a substrate layer; a copper layer disposed on the substrate layer; and an organic solderability preservative (OSP) layer disposed on the copper layer. The OSP layer defines one or more laser treated OSP surfaces.

SEMICONDUCTOR MODULE

A semiconductor modules includes insulating substrates having first and second patterns thereon. One terminal plate connects the first patterns and another terminal plate connects the second patterns. A first and a second switching chip are provided on the first pattern. Bonding wires connect the first ans second chips to the second pattern. An insulating plate with an auxillary conductor theron is disposed on the first pattern between the second pattern and both the first and second chips. A first auxiliary connection connect the auxiliary conductor and the second chip and a second auxilliary connection connect thes auxiliary conductor and the second pattern. The auxiliary connections may be, for example, bonding wires or solder connections. 1. A semiconductor module , comprising:a plurality of insulating substrates each having a first conductive pattern and a second conductive pattern on a surface thereof;a positive electrode terminal plate that electrically connects first conductive patterns on a pair of neighboring insulating substrates of the plurality of insulating substrates;a negative electrode terminal plate that electrically connects second conductive patterns on the pair of neighboring insulating substrates, the negative electrode terminal plate being connected to a negative electrode terminal connection portion of each second conductive pattern on the pair of neighboring insulating substrates;a first switching chip on a first conductive pattern of one of the pair of neighboring insulating substrate and having a front surface electrode on a side of the first switching chip facing away from the first conductive pattern;a second switching chip on the first conductive pattern, the first switching chip being between the negative electrode terminal connection portion and the second switching chip, the second switching chip having a front surface electrode;a first bonding wire that connects the front surface electrode of the first switching chip and the second ...

Semiconductor device

A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

SEMICONDUCTOR DEVICE AND INSPECTION DEVICE

A semiconductor device includes a pair of electrodes and a conductive connection member electrically bonded to the pair of electrodes At least a portion of a perimeter of a bonding surface of at least one of the pair of electrodes and the conductive connection member includes an electromigration reducing area 1. A semiconductor device comprising:a pair of electrodes; anda conductive connection member electrically bonded to the pair of electrodes, whereinat least a portion of a perimeter of a bonding surface of at least one of the pair of electrodes and the conductive connection member comprises an electromigration reducing area.2. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an area of the perimeter of the bonding surface.3. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an end area on an upstream side in a current direction of the perimeter of the bonding surface of the conductive connection member.4. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an area of at least a portion of the perimeter of the bonding surface of at least either of the pair of electrodes and the conductive connection member.5. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an additive containing area containing an additive for reducing diffusion of the electromigration or reducing electrical conductivity of a base material of the bonding surface.6. The semiconductor device according to claim 5 , wherein a content of the additive contained in the electromigration reducing area is 0.1% or greater by mass and 20.0% or lower by mass.7. The semiconductor device according to claim 5 , wherein the additive is at least one type selected from a group comprising Al claim 5 , Cu claim 5 , Si claim 5 , Ni claim 5 , Cr claim 5 , Mg claim 5 , Au claim 5 , Ag claim 5 , Ta claim 5 , Fe claim 5 , a molybdenum-tungsten ...

Leadless integrated circuit package having standoff contacts and die attach pad

A leadless integrated circuit (IC) package comprising an IC chip mounted on a die attach pad and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die attach pad are all covered with a molding material, with portions of the electrical contacts and die attach pad protruding from a bottom surface of the molding material.

Integrated Circuit Assembly and Method of Making

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

Semiconductor device

The semiconductor device includes a supporting member, a conductive member, and a semiconductor element. The supporting member has a supporting surface facing in a thickness direction. The conductive member has an obverse surface facing the same side as the supporting surface faces in the thickness direction, and a reverse surface opposite to the obverse surface. The conductive member is bonded to the supporting member such that the reverse surface faces the supporting surface. The semiconductor element is bonded to the obverse surface. The semiconductor device further includes a first metal layer and a second metal layer. The first metal layer covers at least a part of the supporting surface. The second metal layer covers the reverse surface. The first metal layer and the second layer are bonded to each other by solid phase diffusion.

Module Comprising a Semiconductor Chip

A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

ADDING CAP TO COPPER PASSIVATION FLOW FOR ELECTROLESS PLATING

An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening. 1. An integrated circuit , comprising:an interconnect region;a top interconnect level disposed in said interconnect region;a metal element of said top interconnect level;a metal seed layer disposed over said metal element and making electrical connection to said metal element;a copper pad of electroplated copper disposed over said seed layer, said copper pad making electrical connection to said seed layer;a metal cap layer of plated metal free of copper disposed on a top surface of said copper pad;an upper protective overcoat disposed over said integrated circuit, said upper protective overcoat overlapping a top surface of said metal cap layer and covering said lateral surface of said copper pad, said upper protective overcoat having a bond pad opening which exposes said top surface of said metal cap layer; anda bond pad of electroless plated metal disposed in said bond pad opening, said bond pad making electrical connection to said metal cap layer.2. The integrated circuit of claim 1 , in which said metal cap layer includes nickel between 1 to 3 microns thick;3. The integrated circuit of claim 1 , in which said metal cap layer includes a metal selected from the group consisting of: nickel claim 1 , palladium claim 1 , gold and any combination thereof.4. The integrated circuit of claim 1 , in which said metal cap layer includes electroplated metal.5. The integrated circuit of claim 1 , in which said metal cap layer includes electroless plated metal.6. The integrated circuit of claim 1 , in which said upper protective overcoat ...

SILICON SHIELD FOR PACKAGE STRESS SENSITIVE DEVICES

A surface mount semiconductor package, semiconductor device, and method for fabrication of the surface mount semiconductor package and electrical device are described that include a leadframe assembly, an integrated circuit device disposed on the leadframe assembly, a silicon shield disposed on the integrated circuit device, where the silicon shield is configured to mitigate packaging stress to the integrated circuit device, and a molding layer that encapsulates the integrated circuit device, the silicon shield, and at least a portion of the leadframe assembly. 1. A surface mount semiconductor package , comprising:a leadframe assembly;an integrated circuit device disposed on the leadframe assembly;a silicon shield disposed on the integrated circuit device, where the silicon shield is configured to mitigate packaging stress to the integrated circuit device; anda molding layer that encapsulates the integrated circuit device, the silicon shield, and at least a portion of the leadframe assembly.2. The surface mount semiconductor package of claim 1 , where the leadframe assembly includes copper.3. The surface mount semiconductor package of claim 1 , where the integrated circuit device includes a small-outline transistor.4. The surface mount semiconductor package of claim 1 , where the integrated circuit device includes a flip-chip die.5. The surface mount semiconductor package of claim 1 , where the integrated circuit device includes an active die.6. The surface mount semiconductor package of claim 1 , where the integrated circuit device includes a passive device.7. The surface mount semiconductor package of claim 1 , where the silicon shield includes silicon with a thickness of approximately 5 mm.8. The surface mount semiconductor package of claim 1 , where the molding layer includes epoxy.9. The surface mount semiconductor package of claim 1 , further comprising:at least one wirebond that provides electrical communication between the leadframe assembly and the ...

METHOD FOR PROTECTING BOND PADS FROM CORROSION

Methods, systems, and apparatuses for preventing corrosion between dissimilar bonded metals. The method includes providing a wafer having a plurality of circuits, each of the plurality of circuits having a plurality of bond pads including a first metal; applying a coating onto at least the plurality of bond pads; etching a hole in the coating on each of the plurality of bond pads to provide an exposed portion of the plurality of bond pads; dicing the wafer to separate each of the plurality of circuits; die bonding each of the plurality of circuits to a respective packaging substrate; and performing a bonding process to bond a second, dissimilar metal to the exposed portion of each of the plurality of bond pads such that the second, dissimilar metal encloses the hole in the coating of each of the plurality of bond pads, thereby enclosing the exposed portion.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. 113-. (canceled)14. A method of manufacturing a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer including a plurality of device formation regions, each device formation region having a semiconductor circuit, a pad electrically coupled to the semiconductor circuit, and a first insulating film formed on the pad such that a surface portion of the pad is exposed from the first insulating film at a first opening of the first insulating film;(b) after the step (a), forming a second insulating film on the first insulating film such that the surface portion of the pad is exposed from the second insulating film at a second opening of the second insulating film;(c) after the step (b), bringing a probe needle into contact with the surface potion of the pad; and(d) after the step (c), forming an interconnect layer on the second insulating film, and electrically coupling the interconnect layer to the pad at the surface portion,wherein in the step (b), the second insulating film is formed with application of a heat load to the semiconductor wafer.15. The method according to claim 14 , wherein in the step (a) ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling a back surface electrode of the semiconductor chip with an upper surface of the chip mounting part; a plurality of inner lead parts and a plurality of outer lead parts electrically coupled with an electrode pad of the semiconductor chip through wires; and a sealing body for sealing the semiconductor chip and the wires. Further, a recess is formed in a peripheral region of the back surface of the semiconductor chip. The recess has a first surface extending to join the back surface and a second surface extending to join the first surface. Also, a metal film is formed over the first surface and the second surface of the recess. 1. A method of manufacturing a semiconductor device , comprising the steps of:(a) forming a concave in a first back surface on the side opposite to a first main surface along dicing lines formed over the first main surface of a semiconductor wafer;(b) after the step (a), forming a metal film over the first back surface of the semiconductor wafer so as to enclose the concave;(c) after the step (b), dicing the semiconductor wafer along the dicing lines and forming a plurality of semiconductor chips each having a recess in a peripheral region of a second back surface located on the side opposite to a second main surface; and(d) after the step (c), mounting the semiconductor chip over a chip mounting part of a lead frame through a bonding material,wherein, in the step (d), the semiconductor chip is mounted over the chip mounting part through the bonding material such that the recess in the second back surface of the semiconductor chip comes in contact with the bonding material.2. The method of manufacturing a semiconductor device according to claim 1 , wherein a solder material is used as the bonding material.3. The method of manufacturing a semiconductor device according to claim 1 , wherein ...

ELECTRONIC DEVICE

A electronic device includes a substrate, a first metal film, an insulating film, a second metal film, and a third metal film. The substrate has one surface. The first metal film is disposed on the one surface. The insulating film is disposed on the one surface in a state covering the first metal film. The insulating film has a contact hole exposing the first metal film. The second metal film is disposed on a portion of the first metal film exposed from the contact hole and a periphery of the contact hole. The third metal film is made of gold and disposed on the second metal film. The first metal film, the second metal film, and the third metal film are stacked as a pad portion. 1. An electronic device comprising:a substrate having one surface;a first metal film disposed on the one surface;an insulating film disposed on the one surface in a state covering the first metal film, and having a contact hole exposing the first metal film;a second metal film disposed on a portion of the first metal film exposed from the contact hole and a periphery of the contact hole; anda third metal film made of gold and disposed on the second metal film, wherein:the first metal film, the second metal film, and the third metal film are stacked as a pad portion;the second metal film is covered by the third metal film without being exposed from the third metal film; and{'b': 0', '4, 'the third metal film has a film thickness of equal to or more than . pm.'}2. An electronic device comprising:a substrate having one surface;a first metal film disposed on the one surface;an insulating film disposed on the one surface in a state covering the first metal film, and having a contact hole exposing the first metal film;a second metal film disposed on a portion of the first metal film exposed from the contact hole and a periphery of the contact hole; anda third metal film made of gold and disposed on the second metal film, wherein:the insulating film includes a stress reduction structure;the first ...

Printed circuit boards

A printed circuit board to which a localised solder connection is to be made, the surface of said printed circuit board having a continuous or non-continuous coating of a composition comprising a halo-hydrocarbon polymer at a thickness of from 1 nm to 10 μm.

Method for manufacturing printed circuit boards

A method including: attaching a plurality of conductive tracks to at least one surface of a substrate, depositing a coating comprising at least one halo-hydrocarbon polymer on the at least one surface of the substrate, and soldering through the coating.

Magneto-electric converting element

내용 없음. No content.

Semiconductor device

반도체 장치 및 그 제조 방법

본 발명의 목적은 더머신 프로세스에 의한 디바이스의 본딩 불량을 없애기 위한 것이다. 본딩 패드(21)는 격자 모양으로 형성되어 있다. 패시베이션층(22)의 바로 아래에는 에칭 스토퍼층이 배치되어 있다. 패시베이션층(22) 및 에칭 스토퍼층에는 본딩 패드(21) 상에 개구(23)가 설치되어 있다. 격자 모양의 본딩 패드(21)의 사이에는 절연층(27)이 충전되어 있다. 본딩 와이어는 격자 모양의 본딩 패드(21)에 결합되어 있다.

콤포넌트 패키지용 장치 및 방법

콤포넌트 패키지 및 그 형성 방법이 제공된다. 제1 콤포넌트 패키지는 제1 반도체 기판의 대향 면 상에서 제1 반도체 소자에 부착되는 인터포저 쌍을 갖는 제1 반도체 소자를 포함할 수 있다. 각각의 인터포저는 그 내에 형성된 도전 트레이스를 포함하여 각 인터포저의 표면 상에 형성된 도전 특징부로의 전기적 결합을 제공한다. 복수의 스루 비어는 인터포저를 서로 전기적으로 접속할 수 있다. 제1 인터포저는 인쇄 회로 기판 또는 후속의 반도체 소자로의 전기적 접속을 제공할 수 있다. 제2 인터포저는 제2 반도체 소자 및 제2 콤포넌트 패키지로의 전기적 접속을 제공할 수 있다. 제1 및 제2 콤포넌트 패키지는 결합되어 패키지 온 패키지(PoP) 구조물을 형성할 수 있다.

半導体装置

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

包括散热器的半导体器件

本发明涉及包括散热器的半导体器件。半导体器件包括：包括背面金属的半导体芯片；衬底；以及直接接触背面金属的导电散热器。所述半导体芯片包括直接接触散热器且将散热器与衬底电耦合的烧结接头。

Bonding method of insulating wire

내용 없음. No content.

Semiconductor device and method for fabricating the same

본 발명은 구리 금속배선을 사용하는 반도체 소자에서, 스크라이브 레인 영역에서 구리 금속배선이 노출되는 것을 방지하여 반도체 소자의 수율 증가 및 신뢰성 향상을 확보할 수 있는 반도체 소자의 제조방법을 제공한다. The present invention provides a method of manufacturing a semiconductor device in which a semiconductor device using a copper metal wiring is prevented from exposing the copper metal wiring in a scribe lane region, thereby increasing yield and improving reliability of the semiconductor device. 본 발명에 따르면, 먼저 스크라이브 레인 영역에는 제1 금속으로 이루어진 제1 패드 및 연결배선을 형성하고, 칩 영역에는 제1 금속으로 이루어진 제2 패드를 형성한다. 다음에, 제1 패드, 연결배선 및 제2 패드 상에 식각정지막 및 제1 절연막을 순차로 형성한다. 그리고 식각정지막 및 제1 절연막을 패터닝하여 제1 및 제2 패드를 노출시키고, 제1 및 제2 패드 상에 제2 금속으로 이루어진 제3 및 제4 패드를 형성한다. 그런 후에 제3 및 제4 패드와 패터닝된 제1 절연막 상에 제2 및 제3 절연막을 순차적으로 형성하고, 제3 절연막 상에 형성되어 패터닝된 감광막을 이용하여 제3 및 제4 패드가 노출되도록 제1, 제2 및 제3 절연막을 식각한다. According to the present invention, first, a first pad made of a first metal and a connection wiring are formed in the scribe lane region, and a second pad made of the first metal is formed in the chip region. Next, an etch stop film and a first insulating film are sequentially formed on the first pad, the connection wiring, and the second pad. The etch stop layer and the first insulating layer are patterned to expose the first and second pads, and third and fourth pads made of a second metal are formed on the first and second pads. Thereafter, second and third insulating layers are sequentially formed on the third and fourth pads and the patterned first insulating layer, and the third and fourth pads are exposed on the third insulating layer by using the patterned photosensitive layer. The first, second and third insulating films are etched. 구리, 부식, 스크라이브 레인, 식각정지막 Copper, Corrosion, Scribe Lane, Etch Stop

Semiconductor device and manufacturing method thereof

Method for manufacturing resin-encapsulated semiconductor device

다이패드가 그 주면에 탑재되는 반도체 칩의 면적에 비교해서 작은 면적으로 형성되고, 상기 반도체 칩 및 다이패드가 수지밀봉체로 밀봉되는 수지밀봉형 반도체장치의 제조방법에 있어서, 상기 몰드금형의 공동내에 상기 다이패드의 이면에서 그것과 대향하는 상기 공동의 내벽 면까지의 간극이 상기 방도체 칩의 주면에서 그것과 대향하는 상기 공동의 내벽 면까지의 간극보다도 상기 다이패드의 두께에 상당하는 분만큼 좁게되도록, 상기 반도체 칩 및 다이패드를 배치하고, 센터·게이트에서 상기 공동내에 수지를 동시에 주입해서 수지밀봉체를 형성하는 것에 의해, 반도체 칩의 이면측의 충전영역에 충전된 수지에 의해서, 반도체 칩이 그 상방에 밀어 올려지지는 않는다. 이 결과, 반도체 칩, 본딩와이어 등이 수지밀봉체에서 노출하는 문제를 방지할 수 있기 때문에 수지밀봉형 반도체장치의 수율을 높일 수 있다. A method of manufacturing a resin-sealed semiconductor device in which a die pad is formed with a small area compared to the area of a semiconductor chip mounted on its main surface, and the semiconductor chip and the die pad are sealed with a resin sealing body, wherein the die mold is formed in a cavity of the mold mold. The gap from the back surface of the die pad to the inner wall surface of the cavity facing it is narrower than the gap from the main surface of the insulator chip to the inner wall surface of the cavity facing it by an amount corresponding to the thickness of the die pad. By disposing the semiconductor chip and the die pad as much as possible, and injecting the resin into the cavity at the center gate at the same time to form a resin sealing body, the resin is filled with the resin filled in the filling region on the back side of the semiconductor chip. It is not pushed upwards. As a result, since the problem which a semiconductor chip, a bonding wire, etc. expose to a resin sealing body can be prevented, the yield of a resin sealing semiconductor device can be improved.

Semiconductor device and manufacturing method thereof

Component And Method For The Production Thereof

회로 기판(1)에 주로 구리로 구성된 층(2)이 제공된다. 와이어(3)가 주로 구리로 된 층(2)에 와이어 본딩과 금속간 화합물 형성에 의하여 연결되므로, 주로 구리층(2)에 적층되는 단단한 층(5)은 본딩 영역에서 깨진다. 단단한 층(5)은 80℃ 이상의 온도에서 안정하다. 이 온도에서 상기 층은 산소 확산 장벽으로 작용하며, 정상적인 환경하에서 형성되는 알루미늄 산화물 층과 유사한 방식으로 알루미늄에 작용한다. 회로 기판, 와이어, 본딩 영역, 산소 확산 장벽, 산화물 The circuit board 1 is provided with a layer 2 consisting mainly of copper. Since the wire 3 is connected to the layer 2 mainly made of copper by wire bonding and intermetallic compound formation, the rigid layer 5 mainly laminated to the copper layer 2 is broken in the bonding region. The rigid layer 5 is stable at temperatures of at least 80 ° C. At this temperature the layer acts as an oxygen diffusion barrier and acts on aluminum in a manner similar to the aluminum oxide layer formed under normal circumstances. Circuit board, wire, bonding area, oxygen diffusion barrier, oxide

Printed-circuit boards

FIELD: physics, computer engineering. SUBSTANCE: invention relates to articles having printed-circuit boards with a halohydrocarbon polymer coating. The result is achieved due to that the surface of the printed-circuit board, having a localised soldered connection, has a continuous or discontinuous coating from a composition which includes more than one fluorohydrocarbon polymer with thickness of 1 nm to 10 mcm. EFFECT: preventing oxidation of current-conducting tracks of the printed-circuit board workpiece and (or) other damages under the effect of the environment, for example, corrosion. 5 cl, 15 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 563 978 C2 (51) МПК H05K 1/18 (2006.01) H05K 3/28 (2006.01) H05K 3/34 (2006.01) H05K 3/26 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ (21)(22) Заявка: ИЗОБРЕТЕНИЯ К ПАТЕНТУ 2009130670/07, 18.02.2008 (24) Дата начала отсчета срока действия патента: 18.02.2008 Приоритет(ы): (30) Конвенционный приоритет: (72) Автор(ы): ФЕРДИНАНДИ Фрэнк (GB), СМИТ Родни Эдвард (GB), ХАМФРИЗ Марк Робсон (GB) 19.02.2007 GB 0703172.7 (43) Дата публикации заявки: 10.04.2011 Бюл. № 10 R U (73) Патентообладатель(и): СЕМБЛАНТ ЛИМИТЕД (GB) (45) Опубликовано: 27.09.2015 Бюл. № 27 2 5 6 3 9 7 8 (56) Список документов, цитированных в отчете о поиске: WO 97/39610 A1, 23.10.1997. US 2006/ 0001700 A1, 05.01.2006. US 3931454 A, 06.01.1976. WO 01/14612A1, 01.03.2001. US 2006/0292354 A1, 28.12.2006. RU 2177934 C2, 10.01.2002. RU 2104263 C1, 10.02.1998 (85) Дата начала рассмотрения заявки PCT на национальной фазе: 21.09.2009 GB 2008/000552 (18.02.2008) C 2 C 2 (86) Заявка PCT: (87) Публикация заявки PCT: R U 2 5 6 3 9 7 8 WO 2008/102113 (28.08.2008) Адрес для переписки: 105215, Москва, а/я 26, Рыбиной Н.А. (54) ПЕЧАТНЫЕ ПЛАТЫ (57) Реферат: Изобретение относится к изделиям, включающим печатные платы с нанесенным на них галогенуглеводородным полимерным покрытием. Технический результат предотвращение окисления токопроводящих дорожек ...

Semiconductor components having encapsulated through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Method and apparatus for enabling conventional wire bonding to copper-based bond pad features

본 발명에 따른 방법은 표면에서 산화물을 제거하는 단계와, 그 후에, 산화물제거의 5초이내에 표면에서 부동화층의 도포를 개시하는 단계를 포함하는 바, 상기 표면은 구리표면으로 될 수 있으며, 본드패드표면을 추가로 구비하고, 산화물의 제거는 구연산 혹은 염산을 함유한 용매를 도포하는 단계를 추가로 포함하며, 부동화층의 도포는 아졸계 화합물을 포함한 용매를 도포하는 단계를 추가로 포함하되, BTA를 추가로 포함할 수 있는 한편, 상기 방법은 도포가 개시된 후에 35초내에 부동화층을 완전히 도포하는 단계를 추가로 포함할 수 있다.

Sensor device

Package and semiconductor device using the package

An electronic device has a substrate that has first and second peripheral portions. The first peripheral portion provides a shearing position for separation. The electronic device has a plurality of wiring layers one of which forms a functional surface wiring on the substrate, an electronic element mounted on the substrate, and an encapsulation member formed over the substrate and the electronic element. The surface wiring is selectively disposed under the encapsulation member and in an area adjacent to the second peripheral portion.

Semiconductor Package Having Spin Stacked Structure

기판과 기판에 적층되는 제 1 반도체 칩 및 제 1 반도체 칩에 적층되는 제 2 반도체 칩을 갖는 반도체 패키지들을 제공한다. 여기서, 제 2 반도체 칩은 회전되어 제 1 반도체 칩 상에 적층되는 반도체 패키지를 제공한다. 나아가, 그러한 반도체 패키지들을 구비하는 각종 전자 시스템들을 제공한다.

Bonding wire directly to contact face - after laser removal of contact face oxide and impurities

(A) In prodn. of a connection between a bond wire (20) and a metallic contact face (12), esp. for circuit board components (pref. discrete or integrated semiconductor devices), the novelty is that the contact face (12) is freed from oxide (13) and other impurities (13@) before bonding the wire (20). Pref. a laser (esp. an excimer laser) is used to remove the oxide and impurities. (B) Equipment for carrying out the process consists of a commercial bonding device combined with a laser (pref. excimer laser) system. (C) Also claimed is an electronic assembly (esp. a semiconductor component) produced by the process. Pref. the laser has a 180-350 (esp. 193) nm. wavelength and is pulse-operated pref. in the nanosec. range. The process is suitable for use in the bonding of aluminium bond wire directly to copper contact faces of unpackaged semiconductor devices. ADVANTAGE - The process allows direct bonding on a metallic contact face of non-precious metal (e.g. Cu or Ni), thus avoiding expensive special metallising e.g. with Au and Ni.

Semiconductor device and manufacturing method thereof

Semiconductor radiation emitter package

A semiconductor optical radiation package includes a leadframe, at least one semiconductor optical radiation emitter and an encapsulant. The leadframe has a heat extraction member, which supports the semiconductor optical emitter and provides one or more thermal paths for removing heat generated within the emitter to the ambient environment, as well as at least two electrical leads for providing electrical coupling to the semiconductor optical radiation emitter. The encapsulant covers and protects the emitter and optional wire bonds from damage and allows radiation to be emitted from the emitter into the ambient environment. The semiconductor optical radiation package provides high emitted flux and is preferably compatible with automated processing techniques.

Plate-shaped body and method for manufacturing semiconductor device

Semiconductor device

本发明揭示一种半导体器件，通过加厚层间膜(22)，并将电极焊盘(11)的一部分或全部引出到有源区(16)且形成于该区，能使输入输出区(15)缩小，因而能缩小半导体器件的面积。

Electronic device having contact elements with a specified cross section and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Manufacturing electronic device having contact elements with a specified cross section

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

A semiconductor device and its manufacture method

내용 없음. No content.

Universal Serial Bus memory package and manufacturing method the same

본 발명은 ＵＳＢ 메모리 패키지 및 그 제조 방법에 관한 것으로서, 해결하고자 하는 기술적 과제는 ＵＳＢ 규격과 일치하면서도 경박단소화가 가능하고, 또한 다양한 응용과 메모리 용량의 확장이 간편한 ＵＳＢ 메모리 패키지 및 그 제조 방법을 제공하는데 있다. The present invention relates to a USB memory package and a method for manufacturing the same, the technical problem to be solved in accordance with the USB standard, and can be reduced in size and light, and also provides a USB memory package and a method of manufacturing the memory is easy to expand the memory capacity It is. 이를 위해 본 발명은 상면에 다수의 배선 패턴이 형성된 서브스트레이트와, 서브스트레이트의 배선 패턴에 접속된 적어도 하나의 수동 소자와, 서브스트레이트의 배선 패턴에 접속된 적어도 하나의 컨트롤러와, 서브스트레이트의 배선 패턴에 접속된 적어도 하나의 플래시 메모리와, 서브스트레이트 위의 수동 소자, 컨트롤러 및 플래시 메모리를 밀봉하는 봉지부를 포함하고, 서브스트레이트의 일측 하면에 배선 패턴과 도전성 비아로 연결된 적어도 하나의 ＵＳＢ 랜드가 형성된 ＵＳＢ 메모리 패키지가 개시된다. To this end, the present invention provides a substrate having a plurality of wiring patterns formed thereon, at least one passive element connected to the wiring pattern of the substrate, at least one controller connected to the wiring pattern of the substrate, and the wiring of the substrate. At least one flash memory connected to the pattern, and an encapsulant sealing the passive element, the controller, and the flash memory on the substrate, and at least one USB land connected to the wiring pattern and the conductive via is formed on one lower surface of the substrate. A USB memory package is disclosed. ＵＳＢ 메모리, ＵＳＢ 랜드, 서브스트레이트, 컨트롤러, 플래시 메모리 USB memory, USB land, substrate, controller, flash memory

Printed circuit boards

本发明涉及一种其上将进行局部焊接的印刷电路板，所述印刷电路板的表面具有厚度为1nm至10μm的连续或不连续的组合物涂层，所述组合物包括卤代烃聚合物。

Electronic device having metallurgies containing copper-semiconductor compounds

본 발명의 실리콘 및 게르마늄 함유 재료는 전자 장치에서 도체의 표면에 사용된다. 본 발명에 의하면, 이들 표면에 땜납이 용제없이 접합될 수 있고 와이어가 와이어 접합될 수 있다. 이들 재료는 집적 회로 칩을 패키징하기 위한 리드프레임용 표면 피막으로 사용된다. 이들 재료는 도체 표면상으로 전사(傳寫)되거나, 무전해 또는 전기분해 증착될 수 있다. The silicon and germanium containing materials of the present invention are used on the surface of conductors in electronic devices. According to the present invention, solder can be bonded to these surfaces without solvent and wires can be wire bonded. These materials are used as surface coatings for leadframes for packaging integrated circuit chips. These materials may be transferred onto the conductor surface, or may be electrolessly or electrolytically deposited.

A semiconductor device having a suspended isolating interconnect

Semiconductor device and method of manufacturing a semiconductor device

반도체 소자는 하부 구조물, 절연막, 메탈 콘택들, 브리지, 금속 패드를 포함한다. 하부 구조물은 금속 배선을 가지며, 절연막은 하부 구조물 상에 형성된다. 메탈 콘택들은 절연막을 관통하여 금속 배선과 연결되며, 브리지는 절연막 내부에 구비되며, 메탈 콘택들을 연결한다. 브리지의 폭은 메탈 콘택들의 폭과 다르다. 금속 패드는 절연막 상에 구비되며, 메탈 콘택들과 접촉한다. The semiconductor device includes a lower structure, an insulating film, metal contacts, a bridge, and a metal pad. The lower structure has a metal wiring, and an insulating film is formed on the lower structure. The metal contacts pass through the insulating film and are connected to the metal wires, and a bridge is provided inside the insulating film and connect the metal contacts. The width of the bridge is different from the width of the metal contacts. The metal pad is provided on the insulating film and in contact with the metal contacts.

Semiconductor module for power semiconductor

The module includes power semiconductor components (101,102) which are wired by a metal film (103) deposited on a substrate (106). These components form asymmetric unit arrangements contg. semiconductor components. Each unit is located on the substrate in the same direction. One unit is coupled to electrode terminals (108,110), which are coupled to coupling terminals. The electrode terminals are fitted in given spacing intervals. Pref. the asymmetric unit arrangement is of left-right and/or top-bottom asymmetric direction type.

Leadless integrated circuit package having standoff contacts and die attach pad

本发明提供了一种具有支架触点以及管芯附垫的无引脚集成电路封装，该无引脚集成电路(IC)封装包括：安装到管芯连接焊盘上的IC芯片以及电气地连接到IC芯片的多个电触点。IC芯片、电触点和管芯连接焊盘都由模塑材料所覆盖，并且电触点和管芯连接焊盘的一部分从模塑材料的底面凸出。

Copper pad for copper wire bonding

An integrated circuit package comprising an integrated circuit that includes transistors coupled to copper interconnect structures. The integrated circuit package also comprises copper pads located on the integrated circuit and directly contacting uppermost ones of the copper interconnect structures. Each of copper pads has a thickness of at least about 2 microns. The integrated circuit package further comprises copper wires pressure-welded directly to the copper pads.

Flip-chip solder bump formation using a wirebonder apparatus

A method for forming solder bumps on a flip-chip semiconductor die using a wirebonder apparatus and a flip-chip die bumped according to the method disclosed. An embodiment of the invention includes feeding a solder wire through a wirebonder capillary, where the solder wire forms a solder sphere upon exiting the wirebonder capillary. The solder sphere may then be attached to a solder pad on a flip-chip die, compressing the solder sphere into a solder stud bond. The solder stud bond may then be severed from the solder wire and reflowed into a more spherical solder bump in an oven-reflow process.

Semiconductor package and method for manufacturing the same

A semiconductor package and a method for manufacturing the same are provided to perform a wire bonding process on a fine finger by bonding a wire at an upper surface and a lateral surface of the finger. A substrate has a finger(111). One or more semiconductor chip having a chip pad is laminated on the substrate. A wire(160) is formed to connect electrically the finger and the chip pad to each other. One end of the wire is bonded with the finger at an upper surface of the finger and a lateral surface of the finger. A protrusion(162) is formed at one end of the wire. In a vertical projection of the substrate, a maximum width of an upper surface of the finger is smaller than a width of the protrusion. In the vertical projection of the substrate, the upper surface of the finger is positioned within a lower surface of the finger.

SEMICONDUCTOR DEVICE WITH DIODE AND MANUFACTURING METHOD

Un dispositif à semiconducteur comprend un circuit électronique (112) formé sur un substrat semiconducteur (13); une borne (121) reliée au circuit électronique; et un élément de connexion en métal (3) connecté à la fois à la borne et à une région d'une surface du substrat qui est à nu en position adjacente à la borne. Avec cette structure, une diode dont l'une des électrodes est constituée par la surface du substrat, est formée entre l'élément de connexion (3) et le substrat, de façon à écouler des surtensions susceptibles d'être appliquées au circuit électronique (112). A semiconductor device includes an electronic circuit (112) formed on a semiconductor substrate (13); a terminal (121) connected to the electronic circuit; and a metal connection element (3) connected both to the terminal and to a region of a surface of the substrate which is exposed in position adjacent to the terminal. With this structure, a diode, one of the electrodes of which is formed by the surface of the substrate, is formed between the connection element (3) and the substrate, so as to pass overvoltages which can be applied to the electronic circuit ( 112).

METHOD FOR MANUFACTURING A HIGH TEMPERATURE RESISTANT GOLD WIRE BOND FOR AN ELECTRONIC COMPONENT

The method involves arranging a catalyst layer (6) on connection points (2) of a chip (1). A diffusion blocking layer (7) is arranged on the catalyst layer, and a gold layer (8) is applied on the blocking layer. A gold wire is connected to the gold layer by a welding process. The gold layer has a thickness of 30 to 500 nanometer and the blocking layer has a thickness of 0.8 to 5 micrometer. - An INDEPENDENT CLAIM is also included for a gold wire connection for semi-conductor component.

Semiconductor arrangement with an electrode spot.

SEMICONDUCTOR DEVICE WITH DIODE AND MANUFACTURING METHOD

SEMICONDUCTOR DEVICE COMPRISING A POWER DEVICE AND A CONTROL DEVICE FORMED ON MOUNTING FRAMES

L'invention consiste en un dispositif à semiconducteurs qui utilise un moulage par transfert pour simplifier une étape d'enrobage dans une résine, qui réduit le coût de fabrication en n'utilisant pas d'éléments coûteux et qui a une meilleure efficacité de dissipation de la chaleur produite par un dispositif de puissance. Le dispositif de puissance (101) et un dispositif de commande (102) sont placés dans des positions prédéterminées sur des cadres de montage respectifs (103a, 103b). Une couche isolante (105) de résine époxy ou autre est formée sur une surface principale d'un radiateur (104), et une couche de motif de circuit (106) sur une surface principale de la couche isolante (105) se conforme à un motif de circuit prédéterminé. Les cadres de montage (103a, 103b) sont disposés sur la couche de motif de circuit (106). The invention consists of a semiconductor device which uses transfer molding to simplify a step of coating in a resin, which reduces the manufacturing cost by not using expensive elements and which has a better dissipation efficiency. the heat produced by a power device. The power device (101) and a control device (102) are placed in predetermined positions on respective mounting frames (103a, 103b). An insulating layer (105) of epoxy resin or the like is formed on a main surface of a radiator (104), and a circuit pattern layer (106) on a main surface of the insulating layer (105) conforms to a predetermined circuit pattern. The mounting frames (103a, 103b) are disposed on the circuit pattern layer (106).

Component and method for the production thereof

A substrate (1) is provided with a mainly copper layer (2). A wire (3) is joined to the copper layer (2) by means of bonding and by formation of an intermetallic compound, whereby a hard layer (5) which is applied to the mainly copper layer (2) is broken up in the bond area. The hard layer is stable at a temperature of at least 80 ~C. At this temperature said layer acts as an oxygen diffusion barrier, acting upon aluminium in a manner similar to an aluminium oxide layer which is formed in a normal environment.

FBEOL process for Cu metallizations free from Al-wirebond pads

A process of making an interconnection structure of Cu FBEOL semiconductor devices that does not rely upon Al-wirebond pads which require additional patterning steps (for Al-via to Cu, Al-pad), including: a) providing a substrate having Cu wires and Cu pads embedded therein; b) selectively depositing a first metallic passivation layer on the top copper surfaces sufficient to prevent Cu oxidation and/or Cu out diffusion; c) depositing a final passivation layer; d) employing lithography and etching of the final passivation layer to cause pad opening of the fuses by exposing the passivated Cu in the bond pad area and in the fuse area; and e) causing additional passivation of open pad and open fuse areas by selective immersion deposition of Au.

Bond pad structure for integrated circuit chip

An integrated circuit chip is provided, which includes a bond pad structure. The bond pad structure includes a bond pad, a first metal plate, and a second metal plate. The first metal plate is located under the bond pad. The first metal plate has a first outer profile area. The second metal plate is located under the first metal plate. A cumulative top view outer profile area of the first metal plate and the second metal plate is larger than the first outer profile area of the first metal plate. The second metal plate may have a second outer profile area that is substantially equal to or larger than the first outer profile area. A first vertical axis may extend through a centroid of the first metal plate, and a centroid of the second metal plate may be laterally offset relative to the first vertical axis.

Power semiconductor module method

A method for assembling a power module includes providing a casing with a plurality of receiving elements. At least one substrate carrying at least one semiconductor chip is provided within the casing. At least one support element is provided. An elastically stressed cover is arranged over the at least one support element, and the cover is released so that the elastically stressed cover is restrained by the at least one support element and the plurality of receiving elements.

Bonding pad and support structure and method for their fabrication

A copper bonding pad is directly supported by a copper via pad structure, the copper via pad structure having substantially the same geometry and dimensions as the copper bonding pad. The combination of the copper bonding pad and the copper via pad structure results in an increase in effective thickness of the copper bonding pad. Due to this effective increase in the bonding pad thickness, the bonding pad is more tolerant to the potential dishing problem caused by the CMP process. Additional metal pad structures and via pad structures are used below the bonding pad. The additional metal pad structures and via pad structures comprise alternating segments of interconnect metal and dielectric fillers, and alternating segments of via metal and dielectric fillers, respectively. The alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers prevent or reduce the potential dishing problem that otherwise exists in damascene and CMP processing. The alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers are arranged such that there are a number of columns of solid metal support under the bonding pad. The columns of solid metal support significantly improve the poor mechanical support otherwise provided by the low dielectric constant materials that are presently used in fabrication of modern copper integrated circuits. The columns of solid metal support also improve thermal conductivity of the bonding pad.

Metal base circuit board and its production process

A metal base circuit board is provided. The circuit board includes circuits provided on a metal plate via an insulating layer. A dent portion is provided on one side of the metal plate in such a state that the circumferential portion thereof is not opened, and insulating layers made of the same material are provided both on the space of the dent portion and on the metal plate on which the dent portion is present. The maximum depth of the dent portion may range from 10% to 50% of the thickness of the metal plate. The size of the dent portion as viewed from the vertical direction may be at least 50% of the area of the metal plate, and in a shape of the dent portion as viewed from the vertical direction, the corner may have a curvature radius of at least 2.5mm.

Semiconductor device e.g. schottky diode, has schottky electrode formed on n-type silicon carbide substrate which is electrically connected to bonding wire above P-type well region

A P-type well region (7) with a predetermined depth is formed on a N-type silicon carbide substrate (1). A schottky electrode (2) with schottky junction is formed on the substrate and electrically connected to a bonding wire (6) selectively above the well region. An Independent claim is also included for method of manufacturing semiconductor device.

Bond pad structure for integrated circuit chip

Semiconductor device and method of manufacturing the same

Semiconductor device having a wire bond pad and method therefor

An integrated circuit ( 50 ) has a wire bond pad ( 53 ). The wire bond pad ( 53 ) is formed on a passivation layer ( 18 ) over active circuitry ( 26 ) and/or electrical interconnect layers ( 24 ) of the integrated circuit ( 50 ). The wire bond pad ( 53 ) is connected to a plurality of final metal layer portions ( 51, 52 ). The plurality of final metal layer portions ( 51, 52 ) are formed in a final interconnect layer of the interconnect layers ( 24 ). In one embodiment, the bond pad ( 53 ) is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad ( 53 ) allows routing of conductors in a final metal layer ( 21 ) directly underlying the bond pad ( 53 ), thus allowing the surface area of the semiconductor die to be reduced.

Method for manufacturing resin-encapsulated semiconductor device

다이패드가 그 주면에 탑재되는 반도체 칩의 면적에 비교해서 작은 면적으로 형성되고, 상기 반도체 칩 및 다이패드가 수지밀봉체로 밀봉되는 수지밀봉형 반도체장치의 제조방법에 있어서, 상기 몰드금형의 공동내에 상기 다이패드의 이면에서 그것과 대향하는 상기 공동의 내벽 면까지의 간극이 상기 방도체 칩의 주면에서 그것과 대향하는 상기 공동의 내벽 면까지의 간극보다도 상기 다이패드의 두께에 상당하는 분만큼 좁게되도록, 상기 반도체 칩 및 다이패드를 배치하고, 센터·게이트에서 상기 공동내에 수지를 동시에 주입해서 수지밀봉체를 형성하는 것에 의해, 반도체 칩의 이면측의 충전영역에 충전된 수지에 의해서, 반도체 칩이 그 상방에 밀어 올려지지는 않는다. 이 결과, 반도체 칩, 본딩와이어 등이 수지밀봉체에서 노출하는 문제를 방지할 수 있기 때문에 수지밀봉형 반도체장치의 수율을 높일 수 있다. A method of manufacturing a resin-sealed semiconductor device in which a die pad is formed with a small area compared to the area of a semiconductor chip mounted on its main surface, and the semiconductor chip and the die pad are sealed with a resin sealing body, wherein the die mold is formed in a cavity of the mold mold. The gap from the back surface of the die pad to the inner wall surface of the cavity facing it is narrower than the gap from the main surface of the insulator chip to the inner wall surface of the cavity facing it by an amount corresponding to the thickness of the die pad. By disposing the semiconductor chip and the die pad as much as possible, and injecting the resin into the cavity at the center gate at the same time to form a resin sealing body, the resin is filled with the resin filled in the filling region on the back side of the semiconductor chip. It is not pushed upwards. As a result, since the problem which a semiconductor chip, a bonding wire, etc. expose to a resin sealing body can be prevented, the yield of a resin sealing semiconductor device can be improved. 반도체 칩, 본딩와이어, 수지밀봉형 Semiconductor Chip, Bonding Wire, Resin Sealed Type

Semiconductor device

Power Semiconductor Device Packaging

A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity.

Semiconductor device

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

METHOD OF FABRICATING A WIRE BOND PAD WITH Ni/Au METALLIZATION

A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.

Semiconductor component having increased stability relative to thermomechanical influences, and method for contacting a semiconductor

The invention relates to a semiconductor component, wherein the surface of a semiconductor (11) is contacted by means of a wiring (15), wherein an electrically conductive layer (12) is disposed between the surface of the semiconductor (11) and the wiring, the thermal coefficient of expansion thereof being between that of the semiconductor (11) and that of the material of the wiring. The invention further relates to a method for contacting a semiconductor (11), wherein an electrically conductive layer is at least partially disposed on the surface of the semiconductor (11), and wherein wiring takes place subsequently, wherein the thermal coefficient of expansion of the electrically conductive layer is between that of the semiconductor (11) and that of the material for the wiring.

Wire bonding structure and method for forming same

Provided is a bonding structure of a bonding wire and a method for forming the same which can solve problems of conventional technologies in practical application of a multilayer copper wire, improve the formability and bonding characteristic of a ball portion, improve the bonding strength of wedge connection, and have a superior industrial productivity. A bonding wire mainly composed of copper, and a concentrated layer where the concentration of a conductive metal other than copper is high is formed at a ball bonded portion. The concentrated layer is formed in the vicinity of the ball bonded portion or at the interface thereof. An area where the concentration of the conductive metal is 0.05 to 20 mol % has a thickness greater than or equal to 0.1 μm, and it is preferable that the concentration of the conductive metal in the concentrated layer should be five times as much as the average concentration of the conductive metal at the ball bonded portion other than the concentrated layer.

Heat dissipation board and manufacturing method thereof

Circuit board with self-supporting connection between sides

A copper supporting sheet (5) has holes (9) for connecting semiconductor chips (3) to surface mount components (27). A laminate of polyimide (7) has holes (13) corresponding to the supporting layer holes (9) with copper 15 covering those holes (13). In addition to crossing those holes (13), the copper 15 forms conventional circuit patterns. The side having circuit patterns is populated by surface mount techniques with components (27). The opposite side has silicon chips (3) attached to the copper sheet (5) adjacent to holes (9). Wires (17) are ultrasonically bonded to the chips (3) and extended to the inside of the holes (13) in the polyimide layer (7), where they are ultrasonically bonded to copper (15). Crossover connection of the circuit patterns (17a) are achieved using the same technique. The circuit board is densely populated and cost-effective, with good heat dissipation characteristics.

Plastic encapsulation for integrated circuits having plated copper top surface level interconnect

A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art. In one embodiment, the copper surface level interconnect layer (35) is coated with a thin barrier layer of material (37) which may receive a bond wire. The entire structure is then encapsulated in a plastic package (22) such that the plastic is in physical contact with the copper interconnect metal (35). The use of the plastic packaging (22) in physical contact with the copper interconnect metal (35) eliminates the need for the passivation layers of the prior art. Other devices and methods are described.

Integrated circuit and manufacture thereof

(57)【要約】 【課題】 プラスチックパッケージ内にカプセルされた めっきされた銅相互接続表面層を有する集積回路を提供 する。 【解決手段】 基板２３を覆って第１および第２の金属 被覆層２７，３１が形成され、デバイスのうちの選択さ れた１つに接触し、ビアを通じて互いに接触し得る。そ の上を覆う銅の厚い表面レベル金属層３５は、デバイス の相互接続金属被覆の抵抗を実質的に下げる。銅表面レ ベル相互接続層３５は、ボンドワイヤ４１を受け入れ可 能な物質の薄いバリヤ層３７でコートされる。銅相互接 続金属と物理的に接触したプラスチックパッケージ２２ を使用することにより、不活性化層の必要をなくした。

Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer

A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the substrate in a BOC configuration, wire bonding wires through the opening to the conductors and the bumps, and forming a die encapsulant on the die.

Semiconductor device and manufacturing method for the same

A semiconductor device and a manufacturing method of the same are provided to reduce a size thereof and to enhance performance thereof by increasing density of wires. A first electrode(21) is arranged on a surface of a substrate(10). A second electrode(22) is installed on a surface of a first semiconductor element(11A). The first semiconductor element is supported by the substrate. A first wire(41) is connected through a first bump to at least one electrode which is installed on one of the substrate and the first semiconductor element. A second wire(42) is connected through a second bump(32) to a connecting target part of the first wire. The first wire and the second wire are bonded with the first bump and the second bump, respectively by using a stitch bonding method.