Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

COPPER ALLOYS FOR SUPPRESSING GROWTH OF CU-AL INTERMETALLIC COMPOUNDS

METAL BASE CIRCUIT BOARD AND ITS PRODUCTION PROCESS

A metal base circuit board to be used for a hybrid integrated circuit is provided. The circuit board comprises a metal plate and an insulating layer provided on the metal plate. Circuits are provided on the insulating layer and a plurality of semiconductors are mounted on the circuits. A low dielectric constant portion is provided on the metal plate under a part of the circuits on which no semiconductor is mounted. The low dielectric constant portion may be formed by providing a dent portion on the surface of the metal plate and filling the dent portion with a resin containing an inorganic filler. The side wall of the dent portion may have a gradient from 35 to 65°.

Mit mindestens einer Anschlusselektrode kontaktiertes elektronisches Bauelement

The semiconductor device comprises a base

Copper interconnection with conductive polymer layer and method of forming the same

A conductive polymer between two metallic layers, acts as a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection structure to prevent copper diffusion into any overlying layers and improve adhesive characteristics between the copper and any overlying layers.

Thin NiB or CoB capping layer for non-noble metallic bonding landing pads

The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

SEMICONDUCTOR COMPONENT HAVING INCREASED STABILITY RELATIVE TO THERMOMECHANICAL INFLUENCES, AND METHOD FOR CONTACTING A SEMICONDUCTOR

The invention relates to a semiconductor component, wherein the surface of a semiconductor (11) is contacted by means of a wiring (15), wherein an electrically conductive layer (12) is disposed between the surface of the semiconductor (11) and the wiring, the thermal coefficient of expansion thereof being between that of the semiconductor (11) and that of the material of the wiring. The invention further relates to a method for contacting a semiconductor (11), wherein an electrically conductive layer is at least partially disposed on the surface of the semiconductor (11), and wherein wiring takes place subsequently, wherein the thermal coefficient of expansion of the electrically conductive layer is between that of the semiconductor (11) and that of the material for the wiring.

Semiconductor device and method for producing a semiconductor device

A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.

Wire bonding structure and method for forming same

Provided is a bonding structure of a bonding wire and a method for forming the same which can solve problems of conventional technologies in practical application of a multilayer copper wire, improve the formability and bonding characteristic of a ball portion, improve the bonding strength of wedge connection, and have a superior industrial productivity. A bonding wire mainly composed of copper, and a concentrated layer where the concentration of a conductive metal other than copper is high is formed at a ball bonded portion. The concentrated layer is formed in the vicinity of the ball bonded portion or at the interface thereof. An area where the concentration of the conductive metal is 0.05 to 20 mol % has a thickness greater than or equal to 0.1 μm, and it is preferable that the concentration of the conductive metal in the concentrated layer should be five times as much as the average concentration of the conductive metal at the ball bonded portion other than the concentrated layer.

Method of fabricating stacked wire bonded semiconductor package with low profile bond line

A method of fabricating a low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.

METHOD OF MANUFACTURING DIFFERENT BOND PADS ON THE SAME SUBSTRATE OF AN INTEGRATED CIRCUIT PACKAGE

A method for manufacturng an integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is formed over the substrate. A second metallurgy layer is formed over the first metallurgy layer. The first metallurgy layer is removed while leaving a portion thereof over the second contact pad. The second metallurgy layer is removed while leaving a portion thereof over the second contact pad. A protective layer is formed over the first contact pad while removing the first metallurgy layer.

SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME

A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Method for fabricating semiconductor package with circuit side polymer layer

A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Micro universal serial bus memory package and manufacturing method the same

The present invention relates to a micro USB memory package and a method for manufacturing the same. The object of the present invention is to provide a micro USB memory package and a method for manufacturing the same, which can meet the USB standard specification, can have light, thin, short and small configuration, can have various applications, and can simply expand the memory capacity thereof. In order to accomplish the object of the present invention, there is disclosed a micro USB memory package, which comprises a substrate with a plurality of circuit patterns formed on the top surface thereof, at least one of passive elements connected with the circuit patterns of the substrate, at least one of controllers connected with the circuit patterns of the substrate, at least one of flash memories connected with the circuit patterns of the substrate, and an encapsulation part encapsulating the passive elements, the controllers and the flash memories on the substrate, and at least one of ...

Semiconductor component with front side metallization, includes thick intermediate layer comprising nickel and copper, which is free of noble metals

The intermediate layer (7) comprises nickel and is free of noble metals. It is at least 10 times thicker than the adhesion layer (6). The intermediate layer contains copper in addition to nickel, the copper content being much higher. The intermediate layer is divided into copper and nickel regions. It is at least 100 times thicker than the adhesion layer. The adhesion layer thickness is between 1 nm and 1 mu m. An enhancement layer of nickel phosphide is included on the intermediate layer. Further structural refinements are detailed. An independent claim IS INCLUDED FOR the method of manufacture.

Halbleitervorrichtung mit Grundplatte

Eine Halbleitervorrichtung umfasst einen Halbleiterchip (136) und eine Grundplatte (102), die mit dem Halbleiterchip (136) gekoppelt ist. Die Grundplatte (102) umfasst einen oberen und einen unteren Abschnitt (112, 114). Der obere Abschnitt (112) weist eine Bodenfläche (106) auf, die sich mit einer Seitenwand (108) des unteren Abschnitts (114) trifft. Die Halbleitervorrichtung umfasst ein Kühlelement (160), das mit der Grundplatte (102) gekoppelt ist. Das Kühlelement (160) weist eine erste Fläche (166) auf, die direkt mit der Bodenfläche (106) des oberen Abschnitts (112) der Grundplatte (102) in Berührung ist, eine zweite Fläche (170), die die Seitenwand (108) des unteren Abschnitts (114) der Grundplatte (102) direkt berührt, und eine dritte Fläche (168), die parallel zu der ersten Fläche (166) verläuft und die bündig zu einer Bodenfläche (110) des unteren Abschnitts (114) der Grundplatte (102) angeordnet ist.

COPPER ALLOYS FOR SUPPRESSING GROWTH OF CU-AL INTERMETALLIC COMPOUNDS

Copper alloys are disclosed which may be bonded to aluminum containing members with reduced formation of undesirable copper-aluminum intermetallic compounds. The copper alloys consist essentially of about 15% to about 30% nickel and the balance essentially copper and have particular utility in integrated circuit assemblies as lead frames, lead wires and beam lead tapes. The nickel addition in the alloys suppresses the nucleation rate and the subsequent growth rate of copper-aluminum intermetallic compounds.

METAL BASE CIRCUIT BOARD AND ITS PRODUCTION PROCESS

A process for producing a metal base circuit board to be used for a hybrid integrated circuit is provided, in which the integrated circuit includes a metal plate, an insulating layer on the metal plate, circuits provided on the insulating layer, a power semiconductor mounted on the circuit and a control semiconductor to control the power conductor. The method comprises forming concave portions on a principal plane at a side where the insulating layer is provided on the metal plate, applying an insulating adhesive to the concave portions and the metal plate at a portion other than the concave portions to the same level, providing a metal foil on the surface of the insulating adhesive and curing the adhesive to form a metal assembly, and processing the metal foil of the metal assembly to form circuits.

Semiconductor apparatus, method for manufacturing the same and electric device

METHOD OF MAKING RADIO FREQUENCY IDENTIFICATION TAGS

와이어 결합(wire bonding)을 이용하여 무선 주파수 태그(radio frequency tag)및 그 안테나 구조(antenna structure)가 제조된다. 반도체 칩은 유기체막 기판(organic film substrate)상에 위치되어 부착된다. 하나 이상의 얇은 와이어(one or more thin wires)로 구성되는 안테나는 기판 상에서 생성되고 와이어 결합 머쉰(a wirebonding machine)을 이용하여 칩 상의 접점에 접속된다. 기판의 조각(a strip of substrate)상에서 다수의 반도체(a plurality of semiconductors)를 이용하는 다른 실시예가 또한 개시된다. 이 칩은 캡슐 재료(encapsulant)로 보호될 수도 있고, 칩 및 안테나 결합은 유기체막으로 된 층 사이에 밀봉(seal)될 수 있다. A radio frequency tag and its antenna structure are fabricated using wire bonding. The semiconductor chip is positioned and attached on an organic film substrate. Antennas consisting of one or more thin wires are created on a substrate and connected to contacts on a chip using a wirebonding machine. Another embodiment is also disclosed that uses a plurality of semiconductors on a strip of substrate. The chip may be protected with an encapsulant, and the chip and antenna coupling may be sealed between layers of organic film.

ARRANGEMENT FOR ELECTRICALLY CONNECTING SEMICONDUCTOR CIRCUIT ARRANGEMENTS TO AN EXTERNAL CONTACT DEVICE AND METHOD FOR PRODUCING THE SAME

An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.

Semiconductor package having optimized wire bond positioning

Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least 50 percent of the length of the shorter of the two adjacent wires. In one embodiment, the separation distance D is at most two times a diameter of the wire having the larger diameter of the two adjacent wires. In another embodiment, the separation distance D is at most three times a wire-to-wire pitch between the two adjacent wires. Each wire grouping may include two of more closely-spaced wires. Wire groupings of closely-spaced bonding wires may be used to form, for example, power-signal-ground triplets, signal-ground pairs, signal-power pairs, or differential signal pairs or triplets.

CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE

A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.

Method of improving copper interconnect of semiconductor devices for bonding

An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Lead frame, lead frame fabrication, and semiconductor device

Lead frames and their fabricating method which reduce generation of defects in the process of fabricating semiconductor devices, in particular connection defects in wire bonding, thereby improving the product yield and reliability, and semiconductor devices using the lead frames and their fabricating method are provided. A method for fabricating a lead frame is characterized in including a process of forming a substrate equipped with a convex portion, and a metal layer having a first portion that overlaps a first surface included in the convex portion and a second portion that extends from the first portion and does not overlap the first surface, and a process of bending the metal layer such that the second portion of the metal layer overlaps a second surface included in the convex portion that intersects the first surface.

METAL-BASE CIRCUIT BOARD AND ITS MANUFACTURING METHOD

To provide a metal base circuit board excellent in heat dissipation properties, which remarkably reduces malfunction time of a semiconductor which occurs when a hybrid integrated circuit is operated at a high frequency. A metal base circuit board to be use for a hybrid integrated circuit, comprising circuits provided on a metal plate via an insulating layer (A, B), a power semiconductor mounted on the circuit and a control semiconductor to control the power semiconductor, provided on the circuit, wherein a low capacitance portion is embedded under a circuit portion (pad portion) on which the control semiconductor is mounted, preferably, the low capacitance portion is made of a resin containing an inorganic filler and has a dielectric constant of from 2 to 9.

Contact arrangement for semiconductor component e.g. integrated circuit (IC) has reinforcement layer formed on contact surface and protrudes above insulating layer

An insulating layer (1) is formed such that a contact surface (3) on a semiconductor chip (7) is enclosed. A reinforcement layer (9) formed on the contact surface has a thickness such that the reinforcement layer protrudes above the insulating layer. A contact wire (4) is connected to the reinforcement layer. An independent claim is also included for a contact arrangement manufacturing method.

CONTACTING STRUCTURE OF AN INTEGRATED ACHIEVEMENT CIRCUIT

METAL BASE CIRCUIT BOARD AND ITS PRODUCTION PROCESS

... ²² To provide a metal base circuit board excellent in ²heat dissipation properties, which remarkably reduces ²malfunction time of a semiconductor which occurs when a ²hybrid integrated circuit is operated at a high ²frequency.²A metal base circuit board to be use for a hybrid ²integrated circuit, comprising circuits provided on a ²metal plate via an insulating layer (A, B), a power ²semiconductor mounted on the circuit and a control ²semiconductor to control the power semiconductor, ²provided on the circuit, wherein a low capacitance ²portion is embedded under a circuit portion (pad portion) ²on which the control semiconductor is mounted, ²preferably, the low capacitance portion is made of a ²resin containing an inorganic filler and has a dielectric ²constant of from 2 to 9.² ...

SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING COMMON VOLTAGE BUS AND WIRE BONDABLE REDISTRIBUTION

SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING COMMON VOLTAGE BUS AND WIRE BONDABLE REDISTRIBUTION A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer. (Fig. 5b) ...

Package structure

SEMICONDUCTOR ELEMENT AND ELECTRIC DEVICE

A semiconductor element (20) is provided with a plurality of field effect transistors (90) and Schottky electrodes (9a). The Schottky electrodes (9a) are arranged along an outer circumference of a region wherein the field effect transistors (90) are formed.

Wire bonding process for copper-metallized integrated circuits

A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of barrier metal that resists copper diffusion, deposited on the non-oxidized copper surface in a thickness such that the barrier layer reduces the diffusion of copper at 250° C. by more than 80% compared with the absence of the barrier metal. The structure further comprises an outermost bondable layer which reduces the diffusion of the barrier metal at 250° C. by more than 80% compared with the absence of the bondable metal. Finally, a metal wire is bonded to the outermost layer for metallurgical connection. The barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The outermost bondable metal layer is selected from a group consisting of gold, platinum, and silver.

Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion

A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a polymer layer (306, preferably benzocyclobutene) on the first inorganic layer (303), and finally an outermost second inorganic layer (310, preferably silicon dioxide) on the polymer layer (303). A window (301a) in the stack of layers exposes the metallization (301) of the IC. A patterned seed metal layer (307, preferably copper) is on the metallization (301) in the window and on the second inorganic layer (310) around the window. A buffer metal layer (308, preferably copper) is positioned on the seed metal layer (307). A metal reflow element (309) is attached to the buffer metal (308).

Nickel bonding cap over copper metalized bondpads

A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.

Vertical power MOSFET having thick metal layer to reduce distributed resistance and method of fabricating the same

The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer. ...

Vertikaler Leistungs-MOSFET mit dicker Metallschicht zur Verminderung des verteilten Widerstandes und Verfahren zur Herstellung

Kontaktierungsstruktur einer integrierten Leistungsschaltung

Anschlussflächen mit Seitenwandabstandshaltern und Verfahren zum Herstellen von Anschlussflächen mit Seitenwandabstandshaltern

Es werden eine Chip-Anschlussfläche (215) und ein Verfahren zum Herstellen einer Chip-Anschlussfläche (215) offenbart. Eine Ausführungsform der vorliegenden Erfindung enthält das Bilden mehrerer Anschlussflächen (215) auf einem Werkstück, wobei jede Anschlussfläche (215) untere Seitenwände und obere Seitenwände besitzt, und das Verringern einer unteren Breite jeder Anschlussfläche (215), so dass eine obere Breite jeder (215) Anschlussfläche größer ist als die untere Breite. Das Verfahren enthält ferner das Bilden eines Photoresists über den mehreren Anschlussflächen (215) und das Entfernen von Abschnitten des Photoresists, um dadurch längs der unteren Seitenwände Seitenwandabstandshalter (217) zu bilden. A die pad (215) and a method of making a die pad (215) are disclosed. One embodiment of the present invention includes forming a plurality of pads (215) on a workpiece, each pad (215) having lower sidewalls and upper sidewalls, and decreasing a lower width of each pad (215) so that an upper width of each (215 ) The connection area is larger than the lower width. The method further includes forming a photoresist over the plurality of pads (215) and removing portions of the photoresist to thereby form sidewall spacers (217) along the lower sidewalls.

Electrical connection arrangement, for e.g. integrated circuit, has metallic layer arranged on surfaces of internal contact terminal and wire, where terminal is connected to external terminal of contact device by wire

The arrangement has a metallic layer (7) applied before producing an electrical connection between a semiconductor circuit arrangement (1) and an external contact device (3). The metallic layer is arranged on a surface of an internal contact terminal (4) and on a surface of a wire (6). A bottom of the semiconductor circuit arrangement and a top side of the external contact device are placed opposite to one another. The internal contact terminal is connected to an external contact terminal (5) of the external contact device by the wire. An independent claim is also included for a method for producing a connection arrangement.

ULTRASONIC WIRE BONDER

Ultrasonic wire bonder and method of manufacturing a semiconductor therewith

The bonder is provided with a single bonding head 10 which has two bonding wedges and grooves for location of wires W1, W2 under the wedges and two guides through a tongue 10A at the rear of the bonding head. It is used to perform the simultaneous bonding of two connecting wires on the contact area 2 of a semiconductor device 3 and on a conductor 5 associated with the contact area. The bonding time required for two wires of a given diameter is the same as that required to bond a single wire of the same diameter, thus twin connecting wires may be provided in half the bonding cycle time and the wire spacing is accurately determined without operator intervention. The bonder is of particular use in the manufacture of triac devices where the wires can be accurately spaced one over a first sector, the other over a second sector of the triac structure, on a contact area common to both sectors of the triac. ...

DEVICE AND PROCEDURE FOR THE THERMO-COMPRESSION BONDING

INTERMEDIATE CONNECTIONS TO COPPER IN INTEGRATED CIRCUITS

Semiconductor device and manufacturing method of semiconductor device

Nickel bonding cap over copper metalized bondpads

A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is suitably determined such that oxidation is inhibited. The resulting nickel cap may be wire-bonded directly, without the deposition of a gold cap layer.

Bonded system with coated copper conductor

A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on the semiconductor device region, and at least one additional metal layer on the aluminum-containing metal layer which is harder than the aluminum-containing metal layer. The copper-containing electrical conductor is bonded to the at least one additional metal layer of the semiconductor die via an electrically conductive coating of the copper-containing electrical conductor which is softer than the copper of the copper-containing electrical conductor.

Metal foil interconnection of electrical devices

An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1). A third foil element may be installed to electrically interconnect the discrete ...

A semiconductor device having a suspended isolating interconnect

A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

Device and method for thermo-compression bonding

Arrangement for thermo-compression bonding The arrangement has a wedge (10) which can be applied to a bonding point (14) and an associated optical conductor (19). The conductor is coupled to a laser light (23) source and directed towards a section of bonding wire (13) beneath the wedge between it and the bonding position. The conductor is fed through the wedge to near the bonded wire section so that only this section is heated for thermo-compression bonding when laser energy is coupled in. An Independent claim is also included for a method of thermo-compression bonding.

Device and method for thermo-compression bonding

Verfahren zum Drahtbonden

Anordnung zur elektrischen Verbindung einer Halbleiter-Schaltungsanordnung mit einer äusseren Kontakteinrichtung

Verbindungsanordnung zwischen einer Halbleiter-Schaltungsanordnung (1) und einer äusseren Kontakteinrichtung (3), bei der die Unterseite (12) der Halbleiter-Schaltungsanordnung (1) und die Oberseite (31) der äusseren Kontakteinrichtung (3) gegenüber zueinander vorgesehen sind und eine elektrische Verbindung zwischen einem inneren Kontaktanschluss (4) auf der zur Unterseite gegenüberliegenden Oberseite (11) der Halbleiter-Schaltungsanordnung (1) und einem äusseren Kontaktanschluss (5) auf der Oberfläche der äusseren Kontakteinrichtung (3) aus einem elektrisch leitenden Draht (6) besteht, wobei auf der Oberfläche mindestens des inneren Kontaktanschlusses (4) und auf der Oberfläche des Drahtes (6) eine zusätzliche metallische Schicht (7, 72) angeordnet ist, dadurch gekennzeichnet, dass die metallische Schicht (7) aus Zn-Keimen (71), einer Ni-Legierungsschicht (72), einer Pd-Schicht (73) und einer Au-Schicht (74) besteht.

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

Method of manufacturing semiconductor apparatus, the semiconductor apparatus, and ignitor using the semiconductor apparatus

A method of manufacturing a semiconductor apparatus according to aspects of the invention can include the steps of coating solder on an predetermined area in the upper surface of a lead frame, mounting a chip on solder and melting solder with a hot plate for bonding the chip to the lead frame. The method can also include wiring with bonding wires, turning lead frame upside down, placing lead frame turned upside down on heating cradle, coating solder, the melting point of which is lower than the solder melting point and mounting electronic part on solder; and melting solder with heating cradle for bonding electronic part to lead frame. The bonding with solder can be conducted at a high ambient temperature. Aspects of the semiconductor apparatus can facilitate mounting semiconductor devices and electronic parts on both surfaces of a lead frame divided to form wiring circuits without through complicated manufacturing steps.

SYSTEM FOR DIFFERENT BOND PADS IN AN INTEGRATED CIRCUIT PACKAGE

An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad.

SEMICONDUCTOR ELEMENT AND ELECTRICAL APPARATUS

A semiconductor element (20) of the present invention includes a plurality of field effect transistors (90) and a schottky electrode (9a), and the schottky electrode (9a) is formed along an outer periphery of a region where the plurality of field effect transistors (90) are formed.

SUBMOUNT, ENCAPSULATED SEMICONDUCTOR ELEMENT, AND METHODS OF MANUFACTURING THE SAME

The present invention provides a submount which includes a semiconductor element and which can be easily connected to an IC on a main substrate. The submount in one embodiment of the present invention includes: a substrate; electrodes; the semiconductor element; Au wires; and gold bumps. The electrodes, the semiconductor element, the Au wires, and the gold bumps are encapsulated on the substrate by a resin. The gold bumps are formed on the electrodes and the Au wires by ball bonding and are cut by dicing such that side surfaces of the gold bumps are exposed. The exposed surfaces function as side surface electrodes of the submount.

Self-aligned corrosion stop for copper C4 and wirebond

A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. Examples of a relevant interconnect include a wirebond interconnect and a controlled collapse chip connection (C4) interconnect. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The metallic layer includes an alloy or an unalloyed metal. The metal layer may include copper. The process may be accomplished by providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a ...

Solder material and electronic part using the same

This invention provides a lead-free high temperature solder material comprising 0.005-3.0 wt % of palladium (Pd) and 97.0-99.995 wt % of tin (Sn) whose liquidus temperature is 200-350° C. The solder material is environmentally-friendly, improved in thermal fatigue property, and it can improve the reliability of electronic apparatuses. A predetermined amount of Sn material and Pd is mixed, vacuum-melted and cast to prepare an ingot. The ingot is rolled to be a tape that is later pressed to obtain a solder pellet. In a preferable composition, at least 95 wt % of Sn and 0.005-3.0 wt 5 of Pd are contained, and 0.1-5.0 wt % of metallic (e.g. Cu, Ni) or alloy particles are added. The average particle diameter is about 40 mum. A substrate and an IC chip (electronic element) are die-bonded substantially in parallel by a solder material provided between an Ni plating on the lower side of an IC chip (semiconductor) and an Ni plating on a die.

Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion

A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer ( 303 , preferably silicon nitride) on the chip surface, followed by a polymer layer ( 306 , preferably benzocyclobutene) on the first inorganic layer ( 303 ), and finally an outermost second inorganic layer ( 310 , preferably silicon dioxide) on the polymer layer ( 303 ). A window ( 301 a) in the stack of layers exposes the metallization ( 301 ) of the IC. A patterned seed metal layer ( 307 , preferably copper) is on the metallization ( 301 ) in the window and on the second inorganic layer ( 310 ) around the window. A buffer metal layer ( 308 , preferably copper) is positioned on the seed metal layer ( 307 ). A metal reflow element ( 309 ) is attached to the buffer metal ( 308 ).

A semiconductor device having a suspended isolating interconnect

A semiconductor device (200) configured to provide current and voltage isolation inside an integrated circuit package, the semiconductor device comprising: a lead frame (210) including a first set of leads (220,222,224,226) and a second set of leads (230,232,234,236), the first set of leads being isolated from the second set of leads; a semiconductor die (240) positioned on the lead frame (210); an isolating block (250) positioned on the semiconductor die; a first interconnect coil (202) formed by a first set of wires (260,262,264,266), the semiconductor die, and the first set of leads; and a second interconnect coil (204) isolated from the first interconnect coil and formed by a second set of wires (280,282,284,286), the isolating block, and the second set of leads.

A semiconductor device using a lead frame and its manufacturing method

Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

Verfahren zum Drahtbonden

Halbleitervorrichtung und Verfahren zum Fertigen einer Halbleitervorrichtung

Eine Elementelektrode (103) ist auf einer Oberfläche eines Halbleiterelements (101) angeordnet. Eine Metallschicht (105) ist auf der Elementelektrode (103) angeordnet und umfasst eine innere Region (105a) und eine äußere Region (105b1), die um die innere Region (105a) herum angeordnet ist. Die Metallschicht (105) weist eine Öffnung (TR) auf, welche die Elementelektrode (103) zwischen der inneren Region (105a) und der äußeren Region (105b1) freilegt. Die Elementelektrode (103) weist eine Lotbenetzbarkeit auf, die niedriger als eine Lotbenetzbarkeit der Metallschicht (105) ist. Eine externe Elektrode (117) ist an die innere Region (105a) der Metallschicht (105) angelötet.

Semiconductor device, electronic component and method

METAL BASE CIRCUIT BOARD AND ITS PRODUCTION PROCESS

A metal base circuit board is provided. The circuit board includes circuits provided on a metal plate via an insulating layer. A dent portion is provided on one side of the metal plate in such a state that the circumferential portion thereof is not opened, and insulating layers made of the same material are provided both on the space of the dent portion and on the metal plate on which the dent portion is present. The maximum depth of the dent portion may range from 10% to 50% of the thickness of the metal plate. The size of the dent portion as viewed from the vertical direction may be at least 50% of the area of the metal plate, and in a shape of the dent portion as viewed from the vertical direction, the corner may have a curvature radius of at least 2.5mm.

Interconnections to copper ICs

Connecting a Plurality of Bond Pads and/or Inner Leads With a Single Bond Wire

An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Semiconductor device

According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.

Stacked semiconductor package with circuit side polymer layer

A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.

Elektronische Anordnung und ihre Herstellung

Die Erfindung bezieht sich auf eine elektronische Anordnung (100) und ihre Herstellung. Eine Ausführungsform stellt einen Träger (11) und mehrere Kontaktelemente (12, 13) bereit. Der Träger (11) definiert eine erste Ebene (14). An dem Träger (11) ist ein Leistungs-Halbleiterchip (15) angebracht. Aus einem elektrisch isolierenden Material ist ein Körper (16) gebildet, der den Leistungs-Halbleiterchip (15) überdeckt. Der Körper (16) definiert eine zu der ersten Ebene (14) parallele zweite Ebene (17) und sich von der ersten Ebene (14) zu der zweiten Ebene (17) erstreckende Seitenflächen. Mindestens eines der mehreren Kontaktelemente (12) besitzt in einer zu der ersten Ebene (14) orthogonalen Richtung einen Querschnitt, der länger als 60% des Abstands zwischen der ersten Ebene (14) und der zweiten Ebene (17) ist.

Bondverbindung zwischen einem Bonddraht und einem Leistungshalbleiterchip

Leistungshalbleiteranordnung mit einer Bondverbindung zwischen einem Bonddraht und einem Leistungshalbleiterchip umfassend einen Leistungshalbleiterchip (10) mit einem Halbleiterkörper (1), in dem ein aktiver Zellbereich (12) mit einer Vielzahl von Zellen (15) angeordnet ist, die in einer lateralen Richtung (r) aufeinanderfolgend angeordnet und elektrisch parallel geschaltet sind, wobei- der Halbleiterkörper (1) einen Oberflächenabschnitt (11') aufweist, der in einer zur lateralen Richtung (r) senkrechten vertikalen Richtung (v) oberhalb des aktiven Zellbereichs (12) angeordnet ist;- auf den Oberflächenabschnitt (11') eine Metallisierungsschicht (20) aufgebracht ist, auf die ein Bonddraht (9) gebondet ist;- der Bonddraht (9) einen Durchmesser von größer gleich 300 µm aufweist und aus einer Legierung besteht, die wenigstens 99 Gew.% Aluminium (91) enthält, sowie wenigstens einen weiteren Legierungsbestandteil (92);- das Aluminium (91) eine Kornstruktur mit einer mittleren Korngröße ( Подробнее

Anschlusselektrode zum Kontaktieren von elektronischen,vorzugsweise Halbleiterbauelementen

METHOD FOR OBTAINING METAL TO METAL CONTACT BETWEEN A METAL SURFACE AND A BONDING PAD.

In the DCB substrate comprises a discrete device on the module and manufacturing method of the module of

PACKAGE-ON-PACKAGE (POP) STRUCTURE AND METHOD

METHOD FOR OBTAINING METAL TO METAL CONTACT BETWEEN A METAL SURFACE AND A BONDING PAD.

A method for obtaining metal-to-metal contact between a bonding surface of a metallic bonding area and a second metal surface is disclosed. The method comprises the steps of : - coating said bonding surface of said metallic bonding area with a chemical composition that forms a self-assembled monolayer on said bonding surface of said metallic bonding area, and - bonding said second metal surface on said coated bonding surface through said self–assembled monolayer. The combination of the coating step and the bonding step result in a metal to metal contact between the bonding surface of he metallic bonding area and the second metal surface. The metallic bonding area can be a semiconductor bond pad, e.g. of a semiconductor device.

Arrangement for wire bonding and method for producing a bonding connection

The invention relates to a wire-bonding process and to a process for producing a bonded joint. A bonding location is heated by means of a laser beam originating from a laser, the arrangement comprising an ultrasonic wedge-wedge bonding unit with a bonding needle, a copper or aluminum bonding wire guide, and a copper or aluminum wire for an ultrasonic wedge-wedge bonding process, and at least one of the bonding locations having a hard-metal coating.

Copper-metallized integrated circuits having electroless thick copper bond pads

A metal structure ( 100 ) for a contact pad of a semiconductor device, which has interconnecting traces of a first copper layer ( 102 ). The substrate is protected by an insulating overcoat ( 104 ). In the structure, the first copper layer of first thickness and first crystallite size is selectively exposed by a window ( 110 ) in the insulating overcoat. A layer of second copper ( 105 ) of second thickness covers conformally the exposed first copper layer. The second layer is deposited by an electroless process and consists of a transition zone, adjoining the first layer and having copper crystallites of a second size, and a main zone having crystallites of the first size. The second thickness is selected so that the distance a void from the second layer can migrate during the life expectancy of the structure is smaller than the combined thicknesses of the first and second layers. A layer of nickel ( 106 ) is on the second copper layer, and a layer of noble metal ( 107 ) is on the nickel ...

Double solid metal pad with reduced area

An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions.

Copper-metallized integrated circuits having electroless thick copper bond pads

A metal structure ( 100 ) for a contact pad of a semiconductor, which has interconnecting traces of a first copper layer ( 102 ). The substrate is protected by an insulating overcoat ( 104 ). The first copper layer of first thickness and first crystallite size is selectively exposed by a window ( 110 ) in the insulating overcoat. A second copper layer ( 105 ) of second thickness covers conformably the exposed first copper layer. The second layer is deposited by an electroless process and consists of a transition zone, adjoining the first layer and having copper crystallites of a second size, and a main zone having crystallites of the first size. The distance a void can migrate from the second layer is smaller than the combined thicknesses of the first and second layers. A nickel layer ( 106 ) is on the second copper layer, and a noble metal layer ( 107 ) is on the nickel layer.

Terminal arrangement

The terminal or connector arrangement has a metallic conductor frame (1) with several contact surfaces (5) which connect gold terminal wires (12) by bonds which lead to signal and/or control terminal contacts (14) of an electronic component (8). The contact surfaces (5) are coated with a material (10) which is suitable both for bonding gold connector wires (12) and also for bonding aluminium connector wires (12'). At least one connection wire leading to an active connector contact is an aluminium terminal wire. Preferably the contact surfaces (5) are coated with aluminium and a nickel containing compound. The aluminium (10) may be applied to the contact surfaces by roller plating.

ULTRASONIC WIRE BONDER AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE THEREWITH

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Sealing and protecting integrated circuit bonding pads

A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer (104) positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud (301) is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer (501) and an outermost bondable metal layer (502).

METHODS OF STRESS BALANCING IN GALLIUM ARSENIDE WAFER PROCESSING

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

SEMICONDUCTOR DEVICE PACKAGE HAVING FEATURES FORMED BY STAMPING

Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body.

ELECTRONIC DEVICE AND MANUFACTURING THEREOF

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Power Semiconductor Chip Having Two Metal Layers on One Face

A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Each stitch part of a plurality of leads of a package has a first region having the most outer surface on which Ag plating is applied and a second region having the most outer surface on which Ni plating is applied. Further, the second region is arranged on a die pad side, and the first region is arranged on a periphery side of a sealer. Therefore, in each stitch part, types of plating applied on the most outer surfaces of the first region and the second region can be differentiated from each other, a thick Al wire can be connected to the second region of the second lead, and a thin Au wire can be connected to the first region of the first lead. As a result, usage of only Au plating can be avoided, so that the cost of the package is reduced.

Solderless Die Attach to a Direct Bonded Aluminum Substrate

A DBA-based power device includes a DBA (Direct Bonded Aluminum) substrate. An amount of silver nanoparticle paste of a desired shape and size is deposited (for example by micro-jet deposition) onto a metal plate of the DBA. The paste is then sintered, thereby forming a sintered silver feature that is in electrical contact with an aluminum plate of the DBA. The DBA is bonded (for example, is ultrasonically welded) to a lead of a leadframe. Silver is deposited onto the wafer back side and the wafer is singulated into dice. In a solderless silver-to-silver die attach process, the silvered back side of a die is pressed down onto the sintered silver feature on the top side of the DBA. At an appropriate temperature and pressure, the silver of the die fuses to the sintered silver of the DBA. After wirebonding, encapsulation and lead trimming, the DBA-based power device is completed.

A process of assembling a connector electrode to electronic, preferably semiconductor, components

... 1,139,035. Welding by pressure. BROWN, BOVERI & CO. Ltd. 29 July, 1966 [31 July, 1965], No. 34268/66. Heading B3R. [Also in Division H1] As shown, an electrode 2 having an enlarged head 3 is ultrasonically welded to a semiconductor wafer 1 by means of a hollow sonotrode 4. The electrode 2 is produced by passing an aluminium wire through the sonotrode 4 and forming the head 3 by melting or by cold deformation. Wafer 1 may be of N-type or P- type silicon, the resulting contacts being rectifying or ohmic respectively. The electrode may be welded to or through a thin metal coating of, for example, nickel or gold on the wafer, or through a coat of protective paint.

Semiconductor device, electronic component and method

A contact pad 22 is disclosed which may be part of a semiconductor device 20 comprising a galvanically isolated signal transfer coupler 21. The contact pad may include a metallic base layer 25 having a metallic diffusion barrier layer 26 and metallic wire bondable layer 27 arranged on top. The diffusion barrier layer has a mushroom or pinhead shape, and includes a first portion 28 which is wider than a second portion 33. A surface 29 of the first portion may be curved at the periphery to prevent faults due to voltage spikes. The diffusion barrier layer and wire bondable layer may be replaced by a metallic anchoring layer (140, Fig 6a) not having a barrier function. The contact pad may be formed by depositing the diffusion barrier layer onto a surface of the base layer exposed in an opening of an isolation layer (50, Fig 2), annealing the diffusion barrier layer, and depositing the wire bondable layer on top. The galvanically isolated signal transfer coupler 21 may comprise an inductive ...

Semiconductor package having a stacked structure

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Chip scale surface mounted semiconductor device package and process of manufacture

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first package;a second pad on a second surface of a second package;a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , wherein the first package comprises a first substrate and a first integrated circuit die attached to the first substrate claim 1 , wherein the second package comprises a second substrate and a second integrated circuit die attached to the second substrate.3. The device of claim 2 , wherein the metallic element is laterally adjacent the first integrated circuit die with the first integrated circuit die and the metallic element being interposed between the first substrate and the second substrate.4. The device of claim 3 , wherein the metallic element extends closer to the second substrate than the first integrated circuit die.5. The device of claim 1 , wherein a height of the metallic element is between about 20 micrometers and about 200 ...

Semiconductor package having a multi-channel and a related electronic system

A substrate including internal interconnections, first and second finger electrodes, and having first to fourth quadrants. External terminals are formed on the substrate and connected to the first and second finger electrodes via the internal interconnections. A first tower including first semiconductor chips is formed on the substrate. First conductive wires are formed between the first semiconductor chips and the first finger electrodes. A second tower including second semiconductor chips is formed on the substrate. Second conductive wires are formed between the second semiconductor chips and the second finger electrodes. The external terminals include a first group connected to the first finger electrodes and configuring a channel, and a second group connected to the second finger electrodes, and configuring another channel. The first finger electrodes are formed on the third quadrant, and the second finger electrodes are formed on the first quadrant.

Semiconductor Device, Electronic Component and Method

In an embodiment, a semiconductor device includes a galvanically isolated signal transfer coupler having a contact pad. The contact pad includes a metallic base layer, a metallic diffusion barrier layer arranged on the metallic base layer, and a metallic wire bondable layer arranged on the metallic diffusion barrier layer. The metallic diffusion barrier layer includes a first portion and a second portion. The first portion has a first surface and a second surface opposing the first surface. The first surface has a curved surface at the periphery. The first portion extends in a transverse plane and has a width. The second portion protrudes from the second surface intermediate the width of the first portion.

Stack type semiconductor package

A stack type semiconductor package includes a lower semiconductor package including a lower package substrate and at least one lower semiconductor chip disposed on the lower package substrate; an upper semiconductor package including an upper package substrate larger than the lower package substrate and at least one upper semiconductor chip disposed on the upper package substrate; an inter-package connector connecting an upper surface of the lower package substrate to a lower surface of the upper package substrate; and a filler filling in between the lower package substrate and the upper package substrate while substantially surrounding the inter-package connector.

SEMICONDUCTOR DEVICE AND INSPECTION DEVICE

A semiconductor device includes a pair of electrodes and a conductive connection member electrically bonded to the pair of electrodes At least a portion of a perimeter of a bonding surface of at least one of the pair of electrodes and the conductive connection member includes an electromigration reducing area 1. A semiconductor device comprising:a pair of electrodes; anda conductive connection member electrically bonded to the pair of electrodes, whereinat least a portion of a perimeter of a bonding surface of at least one of the pair of electrodes and the conductive connection member comprises an electromigration reducing area.2. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an area of the perimeter of the bonding surface.3. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an end area on an upstream side in a current direction of the perimeter of the bonding surface of the conductive connection member.4. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an area of at least a portion of the perimeter of the bonding surface of at least either of the pair of electrodes and the conductive connection member.5. The semiconductor device according to claim 1 , wherein the electromigration reducing area is an additive containing area containing an additive for reducing diffusion of the electromigration or reducing electrical conductivity of a base material of the bonding surface.6. The semiconductor device according to claim 5 , wherein a content of the additive contained in the electromigration reducing area is 0.1% or greater by mass and 20.0% or lower by mass.7. The semiconductor device according to claim 5 , wherein the additive is at least one type selected from a group comprising Al claim 5 , Cu claim 5 , Si claim 5 , Ni claim 5 , Cr claim 5 , Mg claim 5 , Au claim 5 , Ag claim 5 , Ta claim 5 , Fe claim 5 , a molybdenum-tungsten ...

Leadless integrated circuit package having standoff contacts and die attach pad

A leadless integrated circuit (IC) package comprising an IC chip mounted on a die attach pad and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die attach pad are all covered with a molding material, with portions of the electrical contacts and die attach pad protruding from a bottom surface of the molding material.

ADDING CAP TO COPPER PASSIVATION FLOW FOR ELECTROLESS PLATING

An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening. 1. An integrated circuit , comprising:an interconnect region;a top interconnect level disposed in said interconnect region;a metal element of said top interconnect level;a metal seed layer disposed over said metal element and making electrical connection to said metal element;a copper pad of electroplated copper disposed over said seed layer, said copper pad making electrical connection to said seed layer;a metal cap layer of plated metal free of copper disposed on a top surface of said copper pad;an upper protective overcoat disposed over said integrated circuit, said upper protective overcoat overlapping a top surface of said metal cap layer and covering said lateral surface of said copper pad, said upper protective overcoat having a bond pad opening which exposes said top surface of said metal cap layer; anda bond pad of electroless plated metal disposed in said bond pad opening, said bond pad making electrical connection to said metal cap layer.2. The integrated circuit of claim 1 , in which said metal cap layer includes nickel between 1 to 3 microns thick;3. The integrated circuit of claim 1 , in which said metal cap layer includes a metal selected from the group consisting of: nickel claim 1 , palladium claim 1 , gold and any combination thereof.4. The integrated circuit of claim 1 , in which said metal cap layer includes electroplated metal.5. The integrated circuit of claim 1 , in which said metal cap layer includes electroless plated metal.6. The integrated circuit of claim 1 , in which said upper protective overcoat ...

混成集積回路のリ−ド線の接続方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Ultrasonic welding method

Semiconductor Package Having Spin Stacked Structure

기판과 기판에 적층되는 제 1 반도체 칩 및 제 1 반도체 칩에 적층되는 제 2 반도체 칩을 갖는 반도체 패키지들을 제공한다. 여기서, 제 2 반도체 칩은 회전되어 제 1 반도체 칩 상에 적층되는 반도체 패키지를 제공한다. 나아가, 그러한 반도체 패키지들을 구비하는 각종 전자 시스템들을 제공한다.

Plate-shaped body and method for manufacturing semiconductor device

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Electronic device having contact elements with a specified cross section and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Manufacturing electronic device having contact elements with a specified cross section

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

A semiconductor device and its manufacture method

내용 없음. No content.

Universal Serial Bus memory package and manufacturing method the same

본 발명은 ＵＳＢ 메모리 패키지 및 그 제조 방법에 관한 것으로서, 해결하고자 하는 기술적 과제는 ＵＳＢ 규격과 일치하면서도 경박단소화가 가능하고, 또한 다양한 응용과 메모리 용량의 확장이 간편한 ＵＳＢ 메모리 패키지 및 그 제조 방법을 제공하는데 있다. The present invention relates to a USB memory package and a method for manufacturing the same, the technical problem to be solved in accordance with the USB standard, and can be reduced in size and light, and also provides a USB memory package and a method of manufacturing the memory is easy to expand the memory capacity It is. 이를 위해 본 발명은 상면에 다수의 배선 패턴이 형성된 서브스트레이트와, 서브스트레이트의 배선 패턴에 접속된 적어도 하나의 수동 소자와, 서브스트레이트의 배선 패턴에 접속된 적어도 하나의 컨트롤러와, 서브스트레이트의 배선 패턴에 접속된 적어도 하나의 플래시 메모리와, 서브스트레이트 위의 수동 소자, 컨트롤러 및 플래시 메모리를 밀봉하는 봉지부를 포함하고, 서브스트레이트의 일측 하면에 배선 패턴과 도전성 비아로 연결된 적어도 하나의 ＵＳＢ 랜드가 형성된 ＵＳＢ 메모리 패키지가 개시된다. To this end, the present invention provides a substrate having a plurality of wiring patterns formed thereon, at least one passive element connected to the wiring pattern of the substrate, at least one controller connected to the wiring pattern of the substrate, and the wiring of the substrate. At least one flash memory connected to the pattern, and an encapsulant sealing the passive element, the controller, and the flash memory on the substrate, and at least one USB land connected to the wiring pattern and the conductive via is formed on one lower surface of the substrate. A USB memory package is disclosed. ＵＳＢ 메모리, ＵＳＢ 랜드, 서브스트레이트, 컨트롤러, 플래시 메모리 USB memory, USB land, substrate, controller, flash memory

Semiconductor device and preparation there of and bonding wire used there of

내용 없음. No content.

A semiconductor device having a suspended isolating interconnect

Aluminum wire for power semiconductor, semiconductor device using the aluminum wire, and method for searching for aluminum wire

Semiconductor device

半導体チップ（１）と回路パターン（４）とがワイヤ（７）によって電気的に接続されたモジュール構造の半導体装置であって、半導体チップ（１）のおもて面電極の表面にはおもて面金属膜が形成され、このおもて面金属膜にワイヤボンディングによってワイヤ（７）が接合されている。半導体チップ（１）は、Ｓｉ基板またはＳｉＣ基板のおもて面におもて面電極を有し、裏面に裏面電極を有する。おもて面金属膜は、例えば３μｍ以上７μｍ以下の厚さのＮｉ膜またはＮｉ合金である。ワイヤ（７）は、ワイヤボンディング前の結晶粒径を例えば１μｍ以上２０μｍ以下の範囲内に制御することにより再結晶温度を高め、かつ強度を向上させたＡｌワイヤである。これにより、大電流導通および高温動作を実現した信頼性の高い半導体装置を提供することができる。 A semiconductor device having a module structure in which a semiconductor chip (1) and a circuit pattern (4) are electrically connected by a wire (7), and a front surface electrode surface of the semiconductor chip (1) A face metal film is formed, and a wire (7) is bonded to the face metal film by wire bonding. The semiconductor chip (1) has a front electrode on the front surface of the Si substrate or the SiC substrate, and a back electrode on the back surface. The front metal film is, for example, a Ni film or a Ni alloy having a thickness of 3 μm or more and 7 μm or less. The wire (7) is an Al wire in which the recrystallization temperature is increased and the strength is improved by controlling the crystal grain size before wire bonding within a range of 1 μm to 20 μm, for example. Thus, a highly reliable semiconductor device that realizes large current conduction and high-temperature operation can be provided.

Leadless integrated circuit package having standoff contacts and die attach pad

本发明提供了一种具有支架触点以及管芯附垫的无引脚集成电路封装，该无引脚集成电路(IC)封装包括：安装到管芯连接焊盘上的IC芯片以及电气地连接到IC芯片的多个电触点。IC芯片、电触点和管芯连接焊盘都由模塑材料所覆盖，并且电触点和管芯连接焊盘的一部分从模塑材料的底面凸出。

Semiconductor package and method for manufacturing the same

A semiconductor package and a method for manufacturing the same are provided to perform a wire bonding process on a fine finger by bonding a wire at an upper surface and a lateral surface of the finger. A substrate has a finger(111). One or more semiconductor chip having a chip pad is laminated on the substrate. A wire(160) is formed to connect electrically the finger and the chip pad to each other. One end of the wire is bonded with the finger at an upper surface of the finger and a lateral surface of the finger. A protrusion(162) is formed at one end of the wire. In a vertical projection of the substrate, a maximum width of an upper surface of the finger is smaller than a width of the protrusion. In the vertical projection of the substrate, the upper surface of the finger is positioned within a lower surface of the finger.

Lead frame

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

METHOD FOR MANUFACTURING A HIGH TEMPERATURE RESISTANT GOLD WIRE BOND FOR AN ELECTRONIC COMPONENT

The method involves arranging a catalyst layer (6) on connection points (2) of a chip (1). A diffusion blocking layer (7) is arranged on the catalyst layer, and a gold layer (8) is applied on the blocking layer. A gold wire is connected to the gold layer by a welding process. The gold layer has a thickness of 30 to 500 nanometer and the blocking layer has a thickness of 0.8 to 5 micrometer. - An INDEPENDENT CLAIM is also included for a gold wire connection for semi-conductor component.

Electric apparatus and preparation thereof and bonding wire used thereto and preparation thereof

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor device manufacturing method, semiconductor device, and igniter device

Semiconductor device

Semiconductor device

Vertical power MOSFET having thick metal layer to reduce distributed resistance

The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.

Plastic encapsulation for integrated circuits having plated copper top surface level interconnect

A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art. In one embodiment, the copper surface level interconnect layer (35) is coated with a thin barrier layer of material (37) which may receive a bond wire. The entire structure is then encapsulated in a plastic package (22) such that the plastic is in physical contact with the copper interconnect metal (35). The use of the plastic packaging (22) in physical contact with the copper interconnect metal (35) eliminates the need for the passivation layers of the prior art. Other devices and methods are described.

Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer

A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing a substrate having a plurality of conductors and an opening. The method also includes the steps of attaching the die to the substrate in a BOC configuration, wire bonding wires through the opening to the conductors and the bumps, and forming a die encapsulant on the die.

Stacked die semiconductor package

A stacked die semiconductor package includes: a substrate, having a first surface and an opposite surface thereto; a plurality of dice, structured for being stacked one on top of the other on the first surface of the substrate, including at least a first die which is mounted closest to the first surface, a second die mounted thereupon and having a larger footprint area than the first die, and a top die having a smaller footprint area than the underlying die thereof, and each having a plurality of contact pads and a plurality of wires for electrically connecting the dice to the first surface of the substrate; at least one interposer between the plurality of dice; advantageously, said top die is electrically directly connected to one of the underlying dice. A method for the assembly of a stacked die semiconductor package is provided.

Metal-base circuit board and its manufacturing method

Metal-base circuit board and its manufacturing method

혼성 집적 회로의 고주파 동작시에 발생하는 반도체의 오동작시를 대폭 저감시켜, 열 방산성이 우수한 금속 베이스 회로 기판을 제공한다. 금속판 상에 절연층 (A, B) 을 개재시켜 형성된 회로와, 상기 회로 상에 실장되는 출력용 반도체와, 상기 출력용 반도체를 제어하고, 상기 회로 상에 형성되는 제어용 반도체로 이루어지는 혼성 집적 회로에 사용되는 금속 베이스 회로 기판으로서, 상기 제어용 반도체를 탑재하는 회로 부분 (패드 부분) 의 하부에 저정전 용량 부분을 매설하고 있는 것을 특징으로 하는 금속 베이스 회로 기판으로서, 바람직하게는 저정전 용량 부분이, 무기질 충전재를 함유하여 이루어진 수지로 이루어지며, 또한 유전율이 2～9 인 것을 특징으로 하는 상기의 금속 베이스 회로 기판. A metal base circuit board excellent in heat dissipation is provided by significantly reducing malfunction of a semiconductor generated during high frequency operation of a hybrid integrated circuit. Used in a hybrid integrated circuit comprising a circuit formed on the metal plate via insulating layers A and B, an output semiconductor mounted on the circuit, and a control semiconductor formed on the circuit by controlling the output semiconductor. A metal base circuit board, wherein a low capacitance portion is embedded below a circuit portion (pad portion) on which the control semiconductor is mounted. Preferably, the low capacitance portion is an inorganic filler. Said metal base circuit board | substrate, Comprising: It consists of resin which contains and the dielectric constant is 2-9.

High density sim card package module and producing method thereof

A high density subscriber identity module(SIM) card package module includes: a substrate, IC chips(3,5,7), bonding wires(12,13,14) and a plastic package(15), the substrate is an organic laminated substrate(1) with two, four, six or eight layers high density interconnected package made by a back-etch process, passive devices(8,9,10) and a crystal oscillator (11) are disposed on the organic laminated substrate(1), two IC chips are disposed side by side. A producing method is also provided.

Method of manufacturing semiconductor apparatus, the semiconductor apparatus, and ignitor using the semiconductor apparatus

A method of manufacturing a semiconductor apparatus according to the invention includes the steps of: coating solder 31 on an predetermined area in the upper surface of lead frame 30; mounting chip 32 on solder 31; melting solder 31 with hot plate 33 for bonding chip 32 to lead frame 30; wiring with bonding wires 34; turning lead frame 30 upside down; placing lead frame 30 turned upside down on heating cradle 35; coating solder 36, the melting point of which is lower than the solder 31 melting point; mounting electronic part 37 on solder 36; and melting solder 36 with heating cradle 35 for bonding electronic part 37 to lead frame 30. The bonding with solder 36 is conducted at a high ambient temperature. The semiconductor apparatus and the manufacturing method thereof facilitate mounting semiconductor devices and electronic parts on both surfaces of a lead frame divided to form wiring circuits without through complicated manufacturing steps.

Method to achieve continuous hydrogen saturation in sparingly used electroless nickel plating process

An improved wire bonding process for copper-metallized integrated circuits is provided by a nickel layer that acts as a barrier against up-diffusing copper. In accordance with the present invention the nickel bath is placed and remains in hydrogen saturation by providing a piece of metal that remains in the nickel plating tank before and during the plating process.

Gate contact and runners for high density trench MOSFET

A trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a buried trench-poly gate runner electrically contacting to a trench gate of the trenched MOSFET. The buried trench-poly gate runner for functioning as a gate runner to increase gate transmission area and a contact area to a gate contact metal for reducing a gate resistance.

Semiconductor component

本发明提供一种半导体元件，其包括：一具有开口的介电层；一铜基第一金属层，填满该介电层的该开口并具有一上表面；以及一第一导电性高分子，覆盖该铜基第一金属层的该上表面。本发明还提供一种半导体元件，其包括：一铜基金属层，埋设于一介电层并具有一上表面；一导电性高分子，覆盖该铜基金属层的该上表面；以及一铝基金属垫，设置于该导电性高分子上。该导电性高分子夹置于两金属层间，可作为粘着层，阻挡层或活化晶种层。该导电性高分子可包覆铜连线结构以避免铜扩散至其上层，以及增加铜与其上层的附着力。

Semiconductor device

A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 μm to 7 μm. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 μm to 20 μm.

Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation

A method of bumping a wafer for facilitating bonding of bond wires to elevate the bond location above the passivation layer. The wafer is bumped by disposing the wafer in at least one electroless bath having a nickel-containing solution therein, wherein bumps having a nickel-containing material are formed simultaneously on the exposed bond pads to an elevation sufficient to prevent damage to a passivation layer surrounding the bond pads by contact of a wire bonding capillary. A gold or palladium cap may optionally be formed over the nickel-containing material of the bumps. A method of forming a semiconductor device assembly is also disclosed.

Semiconductor device package having features formed by stamping

本发明的实施例涉及使用冲压工艺在半导体器件封装的引线框架上形成特征。在一个实施例中，引线框架的一部分诸如管脚通过冲压移动至管芯焊盘的水平平面之外。在某些实施例中，通过冲压可以使得管脚和/或管芯焊盘的一部分具有凹部或者复杂横截面轮廓，例如带倒角的轮廓。通过这种冲压形成的横截面轮廓所提供的复杂度可以用来提高引线框架在封装体的塑料模制体内的机械结合。其它技术(例如选择性地电镀和/或形成棕色氧化保护带以限制在管芯装配时粘附材料的扩展)可以单独和组合使用以便于生产具有这种冲压特征的封装。

Method of improving copper interconnects of semiconductor devices for bonding

An improved wire bond with the pond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Semiconductor devices, electronic building brick and method

本发明公开了半导体器件、电子组件及方法。在一个实施例中，一种半导体器件包括包含接触衬垫的电流隔离信号传输耦合器。所述接触衬垫包括金属基底层，布置在金属基底层上的金属扩散屏障层，以及布置在金属扩散屏障层上的金属线可接合层。金属扩散屏障层包括第一部分和第二部分。第一部分具有第一表面以及与第一表面相对的第二表面。第一表面在外围处包括弯曲表面。第一部分在横向平面中延伸并且具有宽度。第二部分在第一部分的宽度的中间处从第二表面伸出。

Semiconductor package

반도체 패키지의 부피를 최소화할 수 있는 고용량화된 반도체 패키지를 제공한다. 본 발명에 따른 반도체 패키지는 본딩 패드를 가지는 패키지 베이스 기판, 서로 반대되는 활성면 및 비활성면을 가지는 반도체 기판, 반도체 기판의 활성면에 형성되는 반도체 소자, 반도체 소자와 전기적으로 연결되는 제1 패드, 반도체 기판에 대하여 제1 패드와 동일 레벨을 가지며 제1 패드보다 반도체 기판의 가장자리에 인접하는 도전 패턴 및 제1 패드 상에 연결되고 도전 패턴과 이격되면서 도전 패턴 상으로 연장되는 제2 패드를 각각 포함하되, 제2 패드가 적어도 일부 노출되도록 제1 방향으로 소정거리만큼 쉬프트(shift)되며 패키지 베이스 기판 상에 적층되는 복수의 반도체 칩, 및 복수의 반도체 칩들 각각의 제2 패드와 본딩 패드를 연결하는 본딩 와이어를 포함한다.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). The invention of the present application provides a semiconductor integrated circuit device (semiconductor device or electron circuit device) which includes a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board or the like (wiring substrate).

Power semiconductor chip having two metal layers on one face

本发明涉及在一个面上具有两层金属层的功率半导体芯片。该半导体芯片包括具有多个有源晶体管元件的功率晶体管电路。第一负载电极和控制电极布置在半导体芯片的第一面上，其中，第一负载电极包括第一金属层。第二负载电极布置在半导体芯片的第二面上。第二金属层布置在第一金属层上方，其中第二金属层与功率晶体管电路电绝缘，第二金属层布置在功率晶体管电路的包括多个有源晶体管元件中的至少一个的区域的上方。

Solderless die attach to a direct bonded aluminum substrate

A DBA-based power device includes a DBA (Direct Bonded Aluminum) substrate. An amount of silver nanoparticle paste of a desired shape and size is deposited (for example by micro-jet deposition) onto a metal plate of the DBA. The paste is then sintered, thereby forming a sintered silver feature that is in electrical contact with an aluminum plate of the DBA. The DBA is bonded (for example, is ultrasonically welded) to a lead of a leadframe. Silver is deposited onto the wafer back side and the wafer is singulated into dice. In a solderless silver-to-silver die attach process, the silvered back side of a die is pressed down onto the sintered silver feature on the top side of the DBA. At an appropriate temperature and pressure, the silver of the die fuses to the sintered silver of the DBA. After wirebonding, encapsulation and lead trimming, the DBA-based power device is completed.

Self-aligned corrosion stop for copper C4 and wirebond

A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. Examples of a relevant interconnect include a wirebond interconnect and a controlled collapse chip connection (C4) interconnect. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The metallic layer includes an alloy or an unalloyed metal. The metal layer may include copper. The process may be accomplished by providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer. An alternative process may be accomplished by providing a metal layer on the substrate, and electroless plating a corrosion-resistant metal or a corrosion- resistant alloy on the metal layer. The preceding alternative process may additionally include electroless plating a second corrosion-resistant metal on the corrosion-resistant metal or corrosion-resistant alloy. After the corrosion-resistant conductive pad is formed, the interconnect is attached to the conductive pad.

The joint structure of the joining wire and its forming method

Semiconductor device, electronic component and method

In an embodiment, a semiconductor device includes a galvanically isolated signal transfer coupler having a contact pad. The contact pad includes a metallic base layer, a metallic diffusion barrier layer arranged on the metallic base layer, and a metallic wire bondable layer arranged on the metallic diffusion barrier layer. The metallic diffusion barrier layer includes a first portion and a second portion. The first portion has a first surface and a second surface opposing the first surface. The first surface has a curved surface at the periphery. The first portion extends in a transverse plane and has a width. The second portion protrudes from the second surface intermediate the width of the first portion.

Device including a semiconductor chip and wires

Ein Bauelement beinhaltet einen Träger, einen ersten Halbleiterchip, der über dem Träger angeordnet ist, und ein erstes elektrisch leitendes Element, das über dem Träger angeordnet ist. Das Bauelement beinhaltet weiter einen ersten Draht, der elektrisch an das erste elektrisch leitende Element gekoppelt ist, und einen zweiten Draht, der elektrisch an das erste elektrisch leitende Element und an den ersten Halbleiterchip gekoppelt ist. Das erste elektrisch leitende Element ist ausgestaltet, um ein elektrisches Signal zwischen dem ersten Draht und dem zweiten Draht weiterzuleiten. A device includes a carrier, a first semiconductor chip disposed over the carrier, and a first electrically conductive element disposed over the carrier. The device further includes a first wire electrically coupled to the first electrically conductive element and a second wire electrically coupled to the first electrically conductive element and the first semiconductor chip. The first electrically conductive element is configured to pass an electrical signal between the first wire and the second wire.

Semiconductor device including a power device with first metal layer and second metal layer laterally spaced apart

A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

Semiconductor device having improved contact interface reliability and method therefor

A semiconductor package assembly has a first semiconductor package. A plurality of first solder balls is attached to the first semiconductor package. A circuit board is provided having a plurality of mounting pads that is electrically connected to the plurality of first solder balls. A first underfill is disposed on each of the plurality of first solder balls. The first underfill is disposed on interfaces between each of the plurality of first solder balls and the first semiconductor package and each of the plurality of first solder balls and the circuit board. The first underfill is removed from an area between adjacent first solder balls.

Semiconductor device with a contact clip with projections and manufacture thereof

Halbleiter-Bauelement, das Folgendes umfasst: einen Systemträger (10), der ein Die-Pad (11) und eine erste Zuleitung (12) umfasst; einen Halbleiterchip (15), der eine erste Elektrode (16) umfasst, wobei der Halbleiterchip (15) über dem Die-Pad (11) platziert ist; einen Kontaktclip (25), der einen ersten Kontaktbereich (26) und einen zweiten Kontaktbereich (27) umfasst, wobei der erste Kontaktbereich (26) über der ersten Zuleitung (12) platziert ist und der zweite Kontaktbereich (27) über der ersten Elektrode (16) des Halbleiterchips (15) platziert ist, wobei mehrere Vorsprünge (28) sich von dem ersten Kontaktbereich (26) und dem zweiten Kontaktbereich (27) erstrecken und jeder der Vorsprünge (28) eine Höhe von mindestens 5 μm aufweist; und eine erste Schicht aus Lotmaterial (32) zwischen dem ersten Kontaktbereich (26) des Kontaktclips (25) und der ersten Zuleitung (12), wobei Abschnitte der ersten Schicht aus Lotmaterial (32) intermetallische Phasen (50) aufweisen, die nur in Bereichen zwischen den Vorsprüngen (28) des Kontaktclips (25) und der ersten Zuleitung (12) angeordnet sind und wobei die intermetallischen Phasen (50) eine höhere Schmelztemperatur aufweisen als die Bereiche des Lotmaterials (32) zwischen den Vorsprüngen (28) des Kontaktclips (25), in denen das Lotmaterial (32) keine intermetallische Phasen aufweist. A semiconductor device comprising: a leadframe (10) including a die pad (11) and a first lead (12); a semiconductor chip (15) including a first electrode (16), the semiconductor chip (15) being placed over the die pad (11); a contact clip (25) comprising a first contact region (26) and a second contact region (27), wherein the first contact region (26) is placed over the first lead (12) and the second contact region (27) over the first electrode (27) 16) of the semiconductor chip (15), wherein a plurality of protrusions (28) extend from the first contact region (26) and the second contact region (27) and each of the protrusions (28) has a height ...

Semiconductor packages

一种半导体器件封装(10)，包含至少部分被模塑化合物(18)覆盖的半导体器件(20)和导电的引线框架(22)。导电的引线框架(22)包含邻近封装(10)的周边设置的多根引线(23)和设置在由多根引线(23)形成的中心区域中的裸片焊盘(30)。半导体器件(20)被固定到裸片焊盘(30)上，并且从裸片(20)向外延伸的裸片焊盘(23)的一部分被粗糙化以改善与模塑化合物(18)的粘接性。在其它的方面中，沟槽(50、52)被设置在裸片焊盘(30)表面上以进一步促进与裸片焊盘(30)的粘接性并防止水分渗入半导体器件(20)的附近。

Double Solid Metal Pad with Reduced Area

An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions.

Semiconductor package with optimized wire bond positioning

Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least 50 percent of the length of the shorter of the two adjacent wires. In one embodiment, the separation distance D is at most two times a diameter of the wire having the larger diameter of the two adjacent wires. In another embodiment, the separation distance D is at most three times a wire-to-wire pitch between the two adjacent wires. Each wire grouping may include two of more closely-spaced wires. Wire groupings of closely-spaced bonding wires may be used to form, for example, power-signal-ground triplets, signal-ground pairs, signal-power pairs, or differential signal pairs or triplets.

Semiconductor device with front side metallization and method for its production and power diode

Halbleiterbauteil (2) mit einem Halbleiterchip (16) mit einer Vorderseite (1) und einer Rückseite, wobei die Vorderseite (1) integrierte Schaltungselemente und eine elektrisch leitende Metallisierungsstruktur (3) mit Chipkontaktflächen (9) aufweist, wobei die Metallisierungsstruktur (3) die folgenden Schichten aufweist, – eine elektrisch leitende strukturierte Adhäsionsschicht (6), wobei die Adhäsionsschicht (6) auf der Oberfläche der Vorderseite (1) des Halbleiterchips (16) angeordnet ist und einen niederohmigen Kontakt mit Silizium vorsieht, – eine elektrisch leitende strukturierte Zwischenschicht (7), die auf der Adhäsionsschicht (6) angeordnet ist und eine verbindbare Oberfläche vorsieht, – eine Passivierungsschicht (8), die unter Freilassung der Chipkontaktfläche (9) die Oberseite und die Randseiten der Zwischenschicht (7) abdeckt, wobei die Zwischenschicht (7) Ni aufweist und frei von Edelmetallen ist, und wobei die Zwischenschicht (7) mindestens 10-fach dicker als die Adhäsionsschicht (6) ist, und wobei die Zwischenschicht (7) die Randseiten sowie die Oberseite der Adhäsionsschicht (6) abdeckt. Semiconductor component (2) having a semiconductor chip (16) with a front side (1) and a back side, wherein the front side (1) has integrated circuit elements and an electrically conductive metallization structure (3) with chip contact surfaces (9), wherein the metallization structure (3) having the following layers, An electrically conductive structured adhesion layer (6), wherein the adhesion layer (6) is arranged on the surface of the front side (1) of the semiconductor chip (16) and provides a low-resistance contact with silicon, An electrically conductive structured intermediate layer (7) which is arranged on the adhesion layer (6) and provides a connectable surface, - A passivation layer (8) covering the top and the edge sides of the intermediate layer (7), leaving the chip contact surface (9), wherein the intermediate layer (7) comprises Ni and is free of noble ...

Board for manufacturing a BGA and method of manufacturing semiconductor device using thereof

Package-on-package (PoP) structure and method

本发明涉及堆叠封装(PoP)的结构和形成PoP结构的方法。根据一个实施例，结构包括第一衬底、螺柱球、管芯、第二衬底和电连接件。螺柱球与第一衬底的第一表面相接合。管芯附接至第一衬底的第一表面。电连接件与第二衬底连接，以及对应的电连接件与对应的螺柱球相连。

Contact pads with sidewall spacers and method of making contact pads with sidewall spacers

A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

Seedless wirebond pad plating

An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. The platable metal layer may be copper and the noble metal plated layer may be of gold, platinum, palladium, rhodium, ruthenium, osmium, iridium or indium.

Semiconductor package and method of manufacturing the same

Provided are a semiconductor package and a method of manufacturing the semiconductor package, and more particularly, a semiconductor package with bonding wires and a method of manufacturing the semiconductor package. The semiconductor package includes a substrate including a finger, at least one semiconductor chip stacked on the substrate, the semiconductor chip including a chip pad, and a wire which electrically connects the finger with the chip pad, wherein one end of the wire bonds with an upper surface and lateral surfaces of the finger.

Sequentially etched and plated lead frame structure with island prepacked plastic sealed material and producing method thereof

本发明涉及一种有基岛预填塑封料先镀后刻引线框结构及其生产方法，所述结构包括基岛（1）和引脚（2），所述基岛（1）和引脚（2）正面镀有第一金属层（5），基岛（1）和引脚（2）背面镀有第二金属层（6），所述基岛（1）与引脚（2）之间以及引脚（2）与引脚（2）之间的蚀刻区域均填充有塑封料（4），所述塑封料（4）与第一金属层（5）和第二金属层（6）齐平。本发明的有益效果是：引线框底部不需要再贴附一层昂贵的抗高温软性有机物胶膜，也没有背景中所述的装片、打线、包封会产生的各种问题，成品良率得到大大提升，而且引线框采用正背面同时蚀刻，在工序上可减少50%的复杂度，降低了成本，又可以减少因为二次对位造成的错位风险。

Semiconductor device with front side metallization and method for the production thereof

A semiconductor device ( 2 ) has a semiconductor chip ( 16 ) the front side ( 1 ) of which has integrated circuit elements and an electrically conductive metallization structure ( 3 ) with chip contact areas ( 9 ). The metallization structure ( 3 ) has an electrically conductive patterned adhesion layer ( 6 ), which provides a low-resistance contact with silicon, and an electrically conductive patterned intermediate layer ( 7 ), which provides a connectable surface. Furthermore, a passivation layer ( 8 ) is provided, which covers the top side and the edge sides of the intermediate layer ( 7 ) whilst leaving the chip contact area ( 9 ) free. The intermediate layer ( 7 ) comprises Ni and is free of noble metals. The intermediate layer ( 7 ) is at least 10 times thicker than the adhesion layer ( 6 ).

Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion

A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer ( 303, preferably silicon nitride) on the chip surface, followed by a polymer layer ( 306 , preferably benzocyclobutene) on the first inorganic layer ( 303 ), and finally an outermost second inorganic layer ( 310 , preferably silicon dioxide) on the polymer layer ( 303 ). A window ( 301 a ) in the stack of layers exposes the metallization ( 301 ) of the IC. A patterned seed metal layer ( 307 , preferably copper) is on the metallization ( 301 ) in the window and on the second inorganic layer ( 310 ) around the window. A buffer metal layer ( 308 , preferably copper) is positioned on the seed metal layer ( 307 ). A metal reflow element ( 309 ) is attached to the buffer metal ( 308 ).

Semiconductor device and method of manufacturing the same

Terminals ( 2 b, 2 c ) are divided into two along a common boundary, coatings ( 10, 11 ) most suitable for two conductive bonding materials ( 5, 6 ) to be used are exposed on the terminals ( 2 b, 2 c ), the most suitable one of the coatings ( 10, 11 ) is selected, and the corresponding conductive bonding material ( 5, 6 ) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.

Bond pad structure for integrated circuit chip

An integrated circuit chip is provided, which includes a bond pad structure, a low-k dielectric layer, and active circuits. The bond pad structure includes a conductive bond pad, an M top solid conductive plate, and an M top−1 solid conductive plate. The M top solid conductive plate is located under the bond pad. The M top plate is electrically coupled to the bond pad. The M top−1 solid conductive plate is located under the M top plate. A low-k dielectric layer is located under the bond pad of the bond pad structure. At least part of an active circuit is located under the bond pad of the bond pad structure.

Copper interconnect

An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Method of fabricating stacked wire bonded semiconductor package with low profile bond line

A method of fabricating a low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.

Metal ring techniques and configurations

Embodiments of the present disclosure provide an apparatus comprising a substrate layer, a metal ring structure disposed on the substrate layer, the metal ring structure having an opening defined therein, and a solder mask layer coupled to (i) the metal ring structure and (ii) the substrate layer through the opening defined in the metal ring structure, the solder mask layer having a solder mask opening defined therein, wherein an edge of solder mask material defining the solder mask opening overlaps a portion of the opening defined in the metal ring structure. Other embodiments may be described and/or claimed.

Patent JPS6057221B2

PURPOSE:To improve bonding by mounting a semiconductor element, an upper surface thereof has an Al electrode, to an element disposed base material coated with a Ni or Ni alloy layer, and connecting the Al electrode and the base material by a wire made of Al or an Al alloy. CONSTITUTION:The surface of the lead frame 101 is coated with the Ni or Ni alloy layer 102, the semiconductor element, the upper surface thereof has the Al electrodes 111a, 111b, is mounted to an island section 103 of the lead frame 101, and the lead sections 104a, 104b of the lead frame 101 and the Al electrodes 111a, 111b are connected by the wires 112a, 112b consisting of Al or the Al alloy. Accordingly, both pellet bonding and post bonding can be improved, and the semiconductor device having high reliability can be obtained at low cost.

Device including semiconductor chip and wire

本发明的各实施方式总体上涉及包括半导体芯片和接线的器件。具体地，涉及一种器件，包括载体、布置在所述载体之上的第一半导体芯片和布置在所述载体之上的第一导电元件。该器件进一步包括电耦合至所述第一导电元件的第一接线以及电耦合至所述第一导电元件和所述第一半导体芯片的第二接线。所述第一导电元件被配置为在所述第一接线与所述第二接线之间转发电信号。

Semiconductor device

According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.

Trenched MOSFET termination with tungsten plug structures

A metal oxide semiconductor field effect transistor (MOSFET) device includes a termination area. The termination area has a trenched gate runner electrically connected to a trenched gate of said MOSFET. The MOSFET further includes a gate runner contact trench opened through an insulation layer covering the gate runner and into a gate dielectric filling in the trenched gate runner and the gate runner contact trench filled with a gate runner contact plug. The gate runner contact plug further includes a tungsten contact plug. The gate runner contact plug further includes a tungsten contact plug surrounded by a TiN/Ti barrier layer. The gate runner has a width narrower than one micrometer. The MOSFET further includes a field plate in electric contact with the gate runner contact plug. The gate dielectric filling in the trenched gate runner includes a gate polysilicon filling in the trenched gate runner in the termination area. The gate runner contact plug has a bottom portion extends through the insulation layer into the gate dielectric whereby contact areas are increased with the contact plug contacting the gate dielectric to reduce a gate contact resistance.

Semiconductor device, electronic component and method

Semiconductor device and method of manufacturing the same

【課題】半導体装置の信頼性を向上させる。 【解決手段】ダイパッド６と、ダイパッド６に搭載されたＳｉＣチップ１と、ダイパッド６とＳｉＣチップ１とを接合する多孔質の第１焼結Ａｇ層１６と、第１焼結Ａｇ層１６の表面を覆い、かつフィレット状に形成された補強樹脂部１７とを有している。さらにＳｉＣチップ１のソース電極２と電気的に接続するソースリード９と、ゲート電極３と電気的に接続するゲートリードと、ドレイン電極４と電気的に接続するドレインリードと、ＳｉＣチップ１、第１焼結Ａｇ層１６およびダイパッド６の一部を覆う封止体１４とを有しており、補強樹脂部１７は、ＳｉＣチップ１の側面１ｃの一部を覆っている。 【選択図】図２

Semiconductor element and electrical apparatus

A semiconductor element ( 20 ) of the present invention includes a plurality of field effect transistors ( 90 ) and a schottky electrode ( 9 a ), and the schottky electrode ( 9 a ) is formed along an outer periphery of a region where the plurality of field effect transistors ( 90 ) are formed.

Soft solder and electronic component using the same

无铅高温软钎焊材料,并且液相线温度是200—350℃。将以Sn为基体金属,配入规定量的Pd,真空熔炼后锻造成合金锭,轧制成带材,经冲压加工制成软钎料小圆片。优选的成分是含95.0%(重量)以上的Sn和0.005—3.0%(重量)的Pd,再添加0.1—5.0%(重量)平均粒径40μm左右的Ni、Cu等金属或合金粒子。通过IC芯片下面的镀Ni层和管芯表面的镀Ni层,用软钎料将基板与芯片状的电子元件半导体IC芯片大致平行地连接(芯片焊接)。

Method of making a metal wire for use in integrated circuits.

A metal wire for use in connection to integrated circuits has a ball at its tip. The wire has a diameter of 20 to 100 µm and a maximum elongation of not more than 60% at room temperature (20°C) and is an Al wire or a Cu wire. The wire has been annealed at a temperature higher than the recrystallization temperature of the metal material in a non-oxidizing atmosphere. The ball is spherical in shape and has a hardness substantially equal to that of the metal wire. When used, this wire avoids local deformation.

Semiconductor device

A semiconductor device includes a substrate, a semiconductor element, a connection pad, a plated layer, a wire, and an encapsulation resin. The substrate includes a main surface. The semiconductor element is mounted on the main surface and includes a main surface electrode. The connection pad is formed of Cu, arranged with respect to the substrate, separated from the substrate, and includes a connection surface. The plated layer is formed of Ni and partially covers the connection surface. The wire is formed of Al and bonded to the main surface electrode and the plated layer. The encapsulation resin encapsulates the semiconductor element, the connection pad, the plated layer, and the wire.

Die pad for semiconductor packages

A semiconductor device package (10) includes a semiconductor device (20) and an electrically conductive lead frame (22) at least partially covered by a molding compound (18). The electrically conductive lead frame (22) includes a plurality of leads (23) disposed proximate a perimeter of the package (10) and a die pad (30) disposed in a central region formed by the plurality of leads (23). The semiconductor device (20) is attached to the die pad (30), and a portion of the die pad (30) extending outward from the die (20) is roughened to improve adhesion to the molding compound (18). In other aspects, grooves (50, 52) are disposed in die pad (30) surfaces to further promote adhesion of the die pad (30) and to prevent moisture from permeating into the vicinity of the semiconductor chip (20). (Drawing Figure 2)

Semiconductor device with an electromigration reducing area

According to an arrangement, a semiconductor device (10) includes a pair of electrodes (16) and a conductive connection member (21) electrically bonded to the pair of electrodes (16). At least a portion of a perimeter of a bonding surface (24) of at least one of the pair of electrodes (16) and the conductive connection member (21) includes an electromigration reducing area (22).

Method of manufacturing semiconductor apparatus, the semiconductor apparatus, and ignitor using the semiconductor apparatus

A method of manufacturing a semiconductor apparatus according to the invention includes the steps of: coating solder 31 on an predetermined area in the upper surface of lead frame 30; mounting chip 32 on solder 31; melting solder 31 with hot plate 33 for bonding chip 32 to lead frame 30; wiring with bonding wires 34; turning lead frame 30 upside down; placing lead frame 30 turned upside down on heating cradle 35; coating solder 36, the melting point of which is lower than the solder 31 melting point; mounting electronic part 37 on solder 36; and melting solder 36 with heating cradle 35 for bonding electronic part 37 to lead frame 30. The bonding with solder 36 is conducted at a high ambient temperature. The semiconductor apparatus and the manufacturing method thereof facilitate mounting semiconductor devices and electronic parts on both surfaces of a lead frame divided to form wiring circuits without through complicated manufacturing steps.

Connecting a Plurality of Bond Pads and/or Inner Leads With a Single Bond Wire

An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Gold wire connection manufacturing method for semiconductor component, involves applying gold layer on diffusion blocking layers arranged on catalyst layer, and connecting gold wire to gold layer by welding process

Procédé de fabrication d'une liaison de fil d'or résistant à une température élevée pour des composants semi-conducteurs.On dépose une couche de catalyseur (6) sur des points de liaison (2) d'une pastille (1), on dépose une barrière de diffusion métallique (7) sur la couche de catalyseur (6) et ensuite on applique une couche d'or (8) et on relie le fil d'or (9) à la couche d'or (8) par un procédé d'assemblage par une liaison par matière.