Verfahren zur Abschätzung der Lebensdauer eines Leistungshalbleiter-Bauelements

Gestapelte Mehrchip-Module und Verfahren zur Herstellung

Mikrominiaturisierte, integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung

Leistungsmodul

Ein Leistungsmodul ist so aufgebaut, dass ein Leistungsvorrichtungschip (5) innerhalb eines äußeren Gehäuses (1) angeordnet ist und eine Elektrode des Leistungsvorrichtungschips (5) mit einer externen Elektrode (10a) verbunden ist, die in dem äußeren Gehäuse (1) integriert ist. Das Leistungsmodul enthält: einen Wärmeverteiler (3), der in dem äußeren Gehäuse (1) befestigt ist, den Leistungsvorrichtungschip (5), der mit Lot auf den Wärmeverteiler (3) gebondet ist, einen isolierenden Damm (4), der auf dem Wärmeverteiler (3) so gebildet ist, dass er den Leistungsvorrichtungschip (5) umgibt, und eine interne Hauptelektrode (7), deren eines Ende mit Lot auf die Elektrode des Leistungsvorrichtungschips (5) gebondet ist und deren anderes Ende an einer oberen Oberfläche des Dammes befestigt ist. Die externe Elektrode (10a) und das andere Ende der internen Hauptelektrode (7) sind durch Drahtbonden elektrisch miteinander verbunden.

Integrierte Vorrichtung in Halbleiterscheibengrösse.

HALBLEITEREINHEIT UND VERFAHREN ZUR HERSTELLUNG DERSELBEN

Eine Elektrode (1) ist auf einer Halbleiterschicht (11) angeordnet. Eine Polyimid-Schicht (12) weist eine Öffnung auf, die auf der Elektrode (1) angeordnet ist, bedeckt den Rand der Elektrode (1) und erstreckt sich bis auf die Elektrode (1). Eine Kupfer-Schicht (13) ist innerhalb der Öffnung (OP) auf der Elektrode (1) angeordnet und befindet sich entfernt von der Polyimid-Schicht (12) auf der Elektrode (1). Das eine Ende eines Kupfer-Drahts (14) ist mit der Oberfläche der Kupfer-Schicht (13) verbunden.

Verfahren zum Herstellen eines gestapelten Chip-Paketes

Verfahren zum Herstellen eines gestapelten Chip-Paketes, mit den Schritten: Anbringen eines ersten Substrates einschließlich eines ersten zentralen Fensters auf einem ersten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer ersten Verbindungsleitung, die den ersten Halbleiter-Chip und das erste Substrat verbindet; Anbringen eines zweiten ein zweites zentrales Fenster aufweisenden Substrates auf einem zweiten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer zweiten Verbindungsleitung, die den zweiten Halbleiter-Chip und das zweite Substrat verbindet; Zusammenführen der Rückseiten des sich ergebenden ersten und des sich ergebenden zweiten Halbleiter-Chips; Bilden einer dritten Verbindungsleitung, die das erste und das zweite Substrat verbindet; Bilden eines Gusskörpers, welcher die erste, die zweite und die dritte Verbindungsleitung überdeckt; und Anbringen einer leitenden ...

Halbleitereinrichtung

Halbleitereinrichtung, aufweisend:eine Radiatorplatte (1);eine auf der Radiatorplatte (1) angeordnete Harzisolierungsschicht (2);ein Gehäuse (8); undein Versiegelungsmaterial (10), das in ein Inneres des Gehäuses (8) gefüllt ist,gekennzeichnet durch einen Harzblock (11), der aus Harz besteht und ringförmig angeordnet ist, um einen Endteil der Radiatorplatte (1) und einen Endteil der Harzisolierungsschicht (2) zu bedecken;wobei das Gehäuse (8) angeordnet ist, um den Harzblock (11) zu bedecken;wobei das Gehäuse (8) über ein Haftmaterial (6) an den Harzblock (11) oder die Harzisolierungsschicht (2) gebondet ist; undwobei das Versiegelungsmaterial (10) und der Harzblock (11) durch das Haftmaterial (6) voneinander getrennt sind.

Leistungshalbleitermodul

Es wird ein Leistungshalbleitermodul offenbart. Eine Ausführungsform enthält ein Mehrschichtsubstrat mit mehreren Metallschichten und mehreren Keramikschichten, wobei die Keramikschichten zwischen den Metallschichten liegen.

Microwave circuit package

MICROWAVE OSCILLATOR DEVICES

Miniature semiconductor device

... 945,741. Semi-conductor devices. TEXAS INSTRUMENTS Inc. Feb. 2, 1960 [Feb. 6, 1959; Feb. 12, 1959], No. 27197/63. Divided out of 945,734. Heading H1K. The subject matter of this Specification is included in Specification 745,734 from which the Specification is divided but the claims relate to a device comprising a monocrystalline semiconductor wafer containing two elongated portions, electrically isolated from each other through the wafer, each having a surface lying on a major face of the wafer and forming a resistive current path substantially parallel to said face between a pair of ohmic contacts attached to opposite ends of said surfaces. Specifications 945,737,945,738,945,739,945,740, 945,742, 945,743, 945,744, 945,745, 945,746, 945,747, 945,748 and 945,749 also are referred to.

SEMICONDUCTOR MICROWAVE DEVICE OF THE KIND UTILIZING THE TRANSIT-TIME EFFECTS

... 1516945 Oscillators and amplifiers using negative resistance semi-conductor devices THOMSON CSF 25 March 1976 [28 March 1975] 12148/76 Heading H3T A transit time oscillator or amplifier comprises a transistor type semiconductor capable of oscillating at high frequency when a direct voltage is applied to across its collector and emitter and a transmission line connected to the base and collector electrodes of the semiconductor and having a short circuit termination which is adjustable along the line to neutralize the damping effect of the collector-base capacitance on the high frequency oscillations. In one embodiment, Fig. 4, the collector of the transistor is soldered to a microstrip base 41 and the base is connected to the transmission line 45 by a lead 150 and the microstrip circuit. The movable h.f. short circuit comprises a cylinder 46 in the line. The output is taken from the emitter via lead 160 and a further coaxial line 44. In a modification, Fig. 5 (not shown) the lines 44 and ...

METAL BASE CIRCUIT BOARD AND ITS PRODUCTION PROCESS

A metal base circuit board to be used for a hybrid integrated circuit is provided. The circuit board comprises a metal plate and an insulating layer provided on the metal plate. Circuits are provided on the insulating layer and a plurality of semiconductors are mounted on the circuits. A low dielectric constant portion is provided on the metal plate under a part of the circuits on which no semiconductor is mounted. The low dielectric constant portion may be formed by providing a dent portion on the surface of the metal plate and filling the dent portion with a resin containing an inorganic filler. The side wall of the dent portion may have a gradient from 35 to 65°.

Condensateur

Dispositif semi-conducteur

Circuit semi-conducteur microminiature intégré

Circuit microminiature intégré et procédé de fabrication dudit circuit

Dispositif à semi-conducteur, hermétiquement fermé, et procédé de fabrication de ce dispositif

Dispositif semi-conducteur

Circuit semi-conducteur microminiature intégré

Circuit semi-conducteur microminiature intégré

Circuit semi-conducteur microminiature intégré

Semiconductor device and manufacture thereof, circuit board and electronic machine

A high power integrated RF amplifier

An integrated HF-amplifier structure comprises in a first direction (FD) in the order mentioned: an input bond pad (IBP), a plurality of cells (CE1, CE2) being displaced with respect to each other in the first direction (FD), and an output bond pad (OBP). Each one of the cells (CE1, CE2) comprises an amplifier having an input pad (GP1, GP2), an active area (A1, A2), and an output pad (DP1, DP2). The active area (A1, A2) is arranged in- between the input pad (GP1, GP2) and the output pad (DP1, DP2), and the input pad (GP1, GP2), the active area (A1, A2), and the output pad (DP1, DP2) are displaced with respect to each other in a second direction (SD) substantially perpendicular to the first direction (FD). A first network (Nl) comprises first interconnecting means (Li, Ci; Li1, Li2, Ci1) to interconnect input pads (GP1, GP2) of adjacent ones of the plurality of cells (CE1, CE2), and extends in the first direction (FD). A second network (N2) comprises second interconnecting means (Lo, Co; ...

RF-coupled digital isolator

An RF-coupled digital isolator includes a first leadframe portion and a second leadframe portion, electrically isolated from one another. The first leadframe portion includes a first main body and a first finger. The second leadframe portion includes a second main body and a second finger. The first main body is connected to a first ground, and the second main body is connected to a second groundthat is electrically isolated from the first ground. The first finger and the second finger are electrically isolated from one another, e.g., by a plastic molding compound that forms a package for the digital isolator. The first finger acts as a primary of a transformer, and the second finger acts as a secondary of a transformer, when an RF signal drives to the first finger. The first finger and the second finger can be substantially parallel or anti-parallel to one another.

降低相邻信号的串音效应的基板布局方法及其结构

... 降低相邻信号间的串音效应的球栅阵列的基板布局方法及其结构，基板包含形成在晶片上的数个信号端焊垫、形成在晶片外围的环状结构及形成在环状结构外围的数个信号端指状接点。二个信号端焊垫之间形成一防护焊垫；二个信号端指状接点之间形成一防护指状接点；形成一结合线以连结防护焊垫至一环状结构；形成另一结合线以连结环状结构至防护指状接点；形成一防护走线以连结防护指状接点至基板边缘的通路孔，经由通路孔连结防护走线至一信号短路处。 ...

Semiconductor device

A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.

DEVICE ULTRA HIGH FREQUENCY HAS SEMICONDUCTOR, OF THE TYPE USING THE TIME OF TRANSIT, AND APPARATUSES GENERATING OR AMPLIFIERS USING THIS DEVICE

INTEGRATED CIRCUIT IN ULTRA HIGH FREQUENCIES INCLUDING/UNDERSTANDING A PASTILLE SEMICONDUCTRICE

L'invention concerne un circuit intégré. Elle se rapporte à un circuit intégré en hyperfréquences qui comprend un substrat diélectrique (35) ayant une ligne de signaux (38a, 38b) et une plage de montage (36), une pastille semi-conductrice (21) ayant une électrode supérieure et une électrode inférieure placées aux faces opposées de la pastille semi-conductrice, l'électrode inférieure étant montée sur la plage de montage, un bloc de liaison (25, 26) connectant une surface inférieure du bloc de liaison à l'extrémité en direction longitudinale de la ligne de signaux, et un organe de câblage convenant à la liaison de l'électrode supérieure de la pastille à une surface supérieure du bloc de liaison. Application aux circuits intégrés en hyperfréquences.

Multi-chip package

Ultra-Thin Semiconductor Package Device Using a Support Tape

적층가능 마이크로전자 패키지 구조

... 마이크로전자 어셈블리(8)는 제 1 면(14) 및 제 2 면(16) 및 기판 콘택(24)이 있는 기판(12)을 가지는 제 1 마이크로전자 패키지(10A)를 포함한다. 제 1 패키지는 기판 콘택과 전기적으로 접속되고 제 1 면 상에서 서로로부터 이격되어 제 1 및 제 2 마이크로전자 소자 사이에 상호접속 영역을 제공하는 소자 콘택(24)을 가지는 제 1 및 제 2 마이크로전자 소자(40)를 더 포함한다. 제 2 면에서의 복수 개의 패키지 단자(26)는 패키지를 외부 컴포넌트와 접속시키기 위하여 기판 콘택과 상호접속된다. 복수 개의 스택 단자(58)는 패키지를 기판의 제 1 면에 상재하는 컴포넌트와 접속시키기 위하여 상호접속 영역 내의 제 1 면에서 노출된다. 어셈블리는 제 1 마이크로전자 패키지에 상재하며 제 1 마이크로전자 패키지의 스택 단자에 결합되는 단자(26)를 가지는 제 2 마이크로전자 패키지(10B)를 더 포함한다.

SEMICONDUCTOR PACKAGE, CAPABLE OF SHIELDING AN ELECTROMAGNETIC WAVE

PURPOSE: A semiconductor package is provided to reduce an impedance of a whole semiconductor package by shielding an electromagnetic wave. CONSTITUTION: A semiconductor package includes a printed circuit board, a semiconductor chip(106), a first metal wire(110), a metal plate(108), a second metal wire(112), and an encapsulation agent(116). The printed circuit board has an electrode terminal on a side. The semiconductor chip is arranged on a plane of the printed circuit board. The first metal wire couples a bonding pad of the semiconductor bonding pad to the electrode terminal of the printed circuit board electrically. The metal plate is arranged on an upper part of the semiconductor chip. The second metal wire connects the metal plate to the electrode terminal of the printed circuit board electrically. The encapsulation agent encapsulates a plane of the printed circuit board having the metal plate and the first and second metal wires. © KIPO 2008 ...

SEMICONDUCTOR DEVICE

PURPOSE: To facilitate wire bonding process and reduce costs regarding a semiconductor device comprising a structure in which a plurality of semiconductor elements are mounted. CONSTITUTION: The semiconductor device is provided with a circuit board 33 on which leads 49 are arranged and a semiconductor element 21 arranged on the other side which is bonded on an upper surface 33A of the circuit board 33 by face-down bonding, a first and a second laminated semiconductor elements 22 and 23 which are mounted on a lower surface 33B of the circuit board 33 and are connected to the circuit board 33 with wires 30 and 31. In addition, the circuit board 33 is provided with a via 60 and a first and a second trailing wirings 59 and 62 which connect the electrodes having the equal electric characteristics (equal characteristic electrodes) with one another among an electrode 21A formed on the semiconductor element 21 on the other side and electrodes 27 and 28 formed on the first and second semiconductor ...

BALL GRID ARRAY PACKAGE USING TAPE TRACE SUBSTRATE

PURPOSE: A ball grid array package using a tape trace substrate is provided to prevent deformation of a tape trace substrate from an external force by using a tape trace substrate having a cooper wire formed on a polyimide tape. CONSTITUTION: A tape trace substrate(110) is formed with a copper wire including a plurality of solder ball pad(116) formed on one side of a polyimide tape(112) and a connection hole(118) for exposing the solder ball pads(116). An insulating adhesive(164) is applied on a center portion of one side of the tape trace substrate(110). A power plate(170) is adhered to a center portion of the insulating adhesive(164). A ground plate(180) is adhered to the insulating adhesive(164) around the power plate(170). A semiconductor chip(120) is adhered to the power plate(170). A bonding wire(130) is used for connecting the semiconductor chip(120) with the power plate(170) or the semiconductor chip(120) with the ground plate(180) or the semiconductor chip(120) with the cooper ...

METHOD FOR FABRICATING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE OF A SINGLE CHIP WITH A MASK ROM, A PROGRAM DEBUGGING METHOD, AND A METHOD FOR FABRICATING A MICRO CONTROLLER

PURPOSE: A method for fabricating a semiconductor integrated circuit device of a single chip is provided to produce a semiconductor integrated circuit device of a single chip including a mask ROM(read only memory) by memorizing a final program determined by using a programmable ROM in a second mask ROM of a second semiconductor integrated circuit substrate having substantially the same structure as a second semiconductor integrated circuit substrate. CONSTITUTION: A first mask ROM in which a program is not memorized is prepared. A first semiconductor integrated circuit substrate(10) having a first inner bus to which the first mask ROM is to be connected as a metal interconnection is prepared. While the first mask ROM is electrically insulated from the first inner bus, a programmable ROM(15) independent of the first semiconductor integrated circuit substrate is electrically connected to the first inner bus. The first semiconductor integrated circuit substrate and the programmable ROM are ...

Copper interconnects having a titanium-platinum-titanium assembly between copper and compound semiconductor

Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd).

Liquid adhesive for an electronic component and adhesive tape

A liquid adhesive for an electronic component; wherein a component (a) which is an acrylonitrile-butadiene copolymer, a component (b) which is a phenolic resin, and a component (c) which is a compound having two or more maleimide groups are dissolved in an organic solvent, and the component (c) comprises a compound represented by the general formula (1) and a compound represented by the general formula (2).

Semiconductor device and method of manufacturing the same

The invention provide a semiconductor device in which disconnection of a wire wire-bonded to an island due to thermal shock in mounting or a temperature cycle can be positively prevented and a remarkable increase in a manufacturing process time can be prevented. The semiconductor device is characterized to be formed in such a way that a semiconductor chip is die-bonded on the surface of an island and one end of first wire is wire-bonded on an electrode formed on the surface of the semiconductor chip to form a first bonding portion, the other end of the first wire is wire-bonded on the island to form a second bonding portion, and the semiconductor device is sealed with a resin. In this semiconductor device, a double bonding portion formed by wire-bonding the second wire is provided on the second bonding portion of the first wire wire-bonded on the island.

INTEGRATED CIRCUIT DIE WITH LOGICALLY EQUIVALENT BONDING PADS

An integrated circuit (IC) die includes two bonding pads, that share a common logical function, such as signal input or signal output, separated by the width of the die, and preferably on opposite sides of the die. System-in-package devices are produced by steps including directly electrically connecting one or the other bonding pad to bonding pads of other, functionally different IC dies, with the bonding pads of the other IC dies, to which are connected bonding pads of common logical function of the IC dies of the present invention, being functionally identical but geometrically different. Multchip package devices are produced by stacking the IC dies of the present invention with other IC dies and directly electrically connecting one or the other bonding pad to different bonding pads of the other IC dies.

STACKABLE MOLDED MICROELECTRONIC PACKAGES WITH AREA ARRAY UNIT CONNECTORS

A microelectronic package (290) having a (substrate 230), a microelectronic element (170), e.g., a chip, and terminals (240) can have conductive elements (238) electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant (201) can overlie the first surface (136) of the substrate and at least a portion of a face (672) of the microelectronic element remote from the substrate, and may have a major surface (200) above the microelectronic element. A plurality of package contacts (120, 220, 408, 410, 427) can overlie a face (672) of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses (410), substantially rigid posts (120, 220), can be electrically interconnected with terminals (240) of the substrate (230), such as through the conductive elements. The package contacts can have top ...

SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD

A semiconductor device (2) includes: a (65) that is disposed on a field limiting ring (FLR) semiconductor substrate so as to divide the semiconductor substrate into an inner region and an outer region; a first bonding pad (24a to 24d) that is disposed in the inner region and is connected to an external circuit by a wire (14a to 14d) whose one end is connected to the external circuit; and a second bonding pad (26a to 26d) that is disposed in the outer region and on which the other end of the wire is bonded.

EDGE CONNECTABLE METAL PACKAGE

There is provided an edge connectable electronic package (90). The package (90) has a metallic base (92) at least partially coated with a dielectric layer. An interconnection means (96) taking the form of either a leadframe or a circuit trace is electrically interconnected to an encased semiconductor device (94). The opposing end of the interconnection means (96) extends to the package perimeter for interconnection to a socket or brazing to external leads.

Multi-chip package including at least one semiconductor device enclosed therein

A multi-chip package, a semiconductor device used therein, and manufacturing method thereof are provided. The multi-chip package may include a substrate having a plurality of substrate bonding pads formed on an upper surface thereof, at least one first semiconductor chip mounted on the substrate, and at least one second semiconductor chip mounted on the substrate where the at least one first semiconductor chip may be mounted. The at least one second semiconductor chip may include at least one three-dimensional space so as to allow the at least one first semiconductor chip to be enclosed within the at least one three-dimensional space. The at least one three-dimensional space may be a cavity, a groove, or a combination thereof.

Semiconductor device and manufacturing method for the same

To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.

Microelectronic assemblies incorporating inductors

Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Resin mold package structure of integrated circuit

A hybrid integrated circuit is provided having a substrate with at least one active and passive element disposed thereon. A lead frame has a plurality of leads and a support plate. The support plate supports the substrate. The support plate and inner leads are encapsulated in a resin mold package. An opening is formed in the support plate to thermally connect the bottom surface of the substrate to the resin mold package, and a plurality of devoid portions are formed in the substrate causing the amount of edge area contacting the resin mold package to be increased and adhesion between the substrate and the resin mold package improved.

Metal matrix composite semiconductor power switch assembly

A power semiconductor assembly, particularly a semiconductor switch assembly which has a number of discrete emitter connection pads, comprised of a metal matrix composite housing and a copper or aluminum post with a cross-sectional area sufficiently large to carry the rated current providing a single-point, external connection to all emitter pads. The post passes through and is supported by an insulating ceramic insert such as aluminum oxide in the wall of the metal matrix composite housing. The post is hollowed out in the region where it passes through the ceramic insert in order to reduce the mechanical stress between the post and the insulating insert as a result of the mismatch in their thermal expansion coefficients. Buses on either side of the semiconductor die provide surfaces for connection from the post to the discrete emitter connection pads on the die.

Wafer scale integration device with dummy chips and relay pads

A wafer scale integration device comprises a plurality of real chips formed in the center portion of a wafer and a plurality of dummy chips formed in the circumference of the wafer. The dummy chips only include relay pads, some of the relay pads are used for relaying bonding wires of power supply lines. Consequently, the power supply lines do not short-circuit at edge portions of the wafer, since a length of the bonding wire at the edge portion of the wafer becomes short due to the relay pad connected to the bonding wire.

Resin encapsulated BGA-type semiconductor device

A method for fabricating a resin-encapsulated semiconductor device includes the steps of consecutively forming a first interconnect pattern, a dielectric film and a second interconnect pattern on a metallic plate, mounting a semiconductor chip on the dielectric film, connecting chip electrodes of the semiconductor chip to the second interconnect pattern, encapsulating the semiconductor chip on the first dielectric film, removing the metallic plate selectively from the first interconnect pattern, and forming a plurality of metallic bumps on the exposed bottom surface of the first interconnect pattern.

Die positioning in integrated circuit packaging

An integrated circuit die or chip may be positioned within an integrated circuit package by providing a spacer connected to the die and extending upwardly therefrom. When the die is overmolded, the spacer contacts the mold and spaces the die with respect to the mold. By forming the spacer using conventional wire bonding techniques, no additional process steps are necessary in forming the spacer and no additional parts are needed. The spacer wire bonds may be formed with wires which extend upwardly above the remaining wires, protecting the remaining wires from being contacted by the mold or from being positioned too close to the upper surface of the resulting molded package.

Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages

An apparatus and method for enhancing thermal performance and electromagnetic interference (EMI) shielding in die-up array integrated circuit (IC) device packages is presented. A die-up array package includes an IC die mounted to a first stiffener surface. The package further includes a cap body having first and second surfaces. A first portion of the second surface has a cavity formed therein, and a planar second portion of the second surface is coupled to the first stiffener surface. The package further includes a substrate having a first surface coupled to a second stiffener surface. A plurality of contact pads on the first substrate surface are electrically connected to an array of electrically conductive terminals on a second substrate surface. The stiffener and cap body form a die enclosure that dissipates heat during operation of the IC die, and shields EMI emanating from and radiating toward the IC die.

Semiconductor package

A semiconductor package (10) forms an impedance matching capacitor by utilizing an insulator (12), a conductor (19) on the dielectric, and a substrate (11) as elements of the capacitor. The capacitor is electrically connected, as part of an impedance matching network to shunt the inductance of the bonding wires (21) that connect the semiconductor die (18) an input lead (17).

Semiconductor device having an interconnecting circuit board

A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.

POWER SEMICONDUCTOR DEVICE

A power semiconductor device includes power semiconductor elements joined to wiring patterns of a circuit substrate, cylindrical external terminal communication sections, and wiring means for forming electrical connection between, for example, the power semiconductor elements and the cylindrical external terminal communication sections. The power semiconductor elements, the cylindrical external terminal communication sections, and the wiring means are sealed with transfer molding resin. The cylindrical external terminal communication sections are arranged on the wiring patterns so as to be substantially perpendicular to the wiring patterns, such that external terminals are insertable and connectable to the cylindrical external terminal communication sections, and such that a plurality of cylindrical external terminal communication sections among the cylindrical external terminal communication sections are arranged two-dimensionally on each of wiring patterns that act as main circuits.

Substrate for semiconductor package and method of making same

The present invention provides a substrate for a semiconductor and the semiconductor package, wherein with the setup that the conductive fingers around the chip of enclosure structure superposes with the electrical connecting element, the distance between the conductive fingers and the chip will be shortened, so as to effectively shorten the wires from the chip to the conductive fingers and reduce the materials and the processing time, in favor of cutting down the cost of production.

Packaged semiconductor device

A semiconductor device includes: a transistor including a main terminal and a sense terminal; a main output electrode connected to the main terminal via a first wire; a sense output electrode connected to the sense terminal via a second wire; and a package sealing the transistor, the first and second wires, part of the main output electrode and part of the sense output electrode, wherein a wiring inductance from the main terminal to the main output electrode is larger than a wiring inductance from the sense terminal to the sense output electrode.

Semiconductor device having a heat spreader exposed from a seal resin

A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.

SEMICONDUCTOR CHIP PACKAGE

A semiconductor chip package is provided. The semiconductor chip package includes a lead frame having a chip carrier. A semiconductor chip is mounted on the chip carrier, having a plurality of bonding pads thereon. A package substrate has a cavity therein to accommodate the chip carrier and the semiconductor chip, wherein at least one of the bonding pads of the semiconductor chip is electrically coupled to the package substrate.

Semiconductor package including multiple chips and separate groups of leads

Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.

HIGH VOLTAGE POLYMER DIELECTRIC CAPACITOR ISOLATION DEVICE

An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Inductive relayed coupling circuit between substrates

An electronic circuit carries out communication by inductive coupling between chips which are stacked and mounted. The electronic circuit relays an inter-chip communication signal by a repeater which receives a signal from a transmitter to recognize a transmission source and a receiving destination, and relays a received signal when the repeater itself exists between the transmission source and the receiving destination, and does not relay the received signal when the repeater itself does not exist between the transmission source and the receiving destination. Accordingly, data can be transferred at high speed up to a chip farther than the dimensions of a coil through communications by inductive coupling between the stacked and mounted chips.

Semiconductor device and manufacturing method thereof

In a semiconductor device having a semiconductor chip mounted on a printed circuit board, the semiconductor chip has a plurality of electrodes and the printed circuit board has a plurality of conductive patterns. Metallic plated layers are formed on the electrodes of the semiconductor chip. The metallic plated layers on the electrodes of the semiconductor chip are electrically connected with the conductive patterns of the printed circuit board by metallic wires.

ELECTRONIC COMPONENT STRUCTURE AND METHOD OF MAKING

An external component, typically a surface mount passive, is attached to a semiconductor die. In some embodiments the passive is placed directly over exposed pads on the semiconductor die and attached using conductive tape or conductive epoxy. In some embodiments the passive is attached to the semiconductor die using non-conductive adhesive and wire bonded to bond pads on the semiconductor die and/or to pads on a substrate to which the semiconductor die is attached.

Laser diode arrangement

A laser diode arrangement has a joint electrically insulating substrate, a plurality of laser diodes arranged in the joint electrically insulated substrate, conductor structures provided on the substrate so that, the laser diodes are connected with one another through the conductor structures, and a joint control of the laser diodes.

SEMICONDUCTOR PACKAGE

A semiconductor package comprising a substrate including substrate pads on a top surface thereof, a first upper semiconductor chip on the substrate and including conductive chip pads, and bonding wires coupled to the substrate pads and the first upper semiconductor chip. The bonding wires include first and second bonding wires. The substrate has a first region between the conductive chip pads and the substrate pads, and a second region between the first region and the substrate pads. The second bonding wire has a maximum vertical level on the first region of the substrate. On the first region of the substrate, the first bonding wire is at a level higher than that of the second bonding wire. On the second region of the substrate, the second bonding wire is at a level higher than that of the first bonding wire.

Microwave circuit package

A microwave circuit package having a ball grid array, BGA, soldered on to a planar major surface of a metal housing of the package for the electrical connection of the ports of the microwave circuit through RF signal paths to an adjacent electrical device. Each of the RF signal paths comprises a pin electrically connected to a respective port of the microwave circuit package, projecting normally through an opening in the said major surface from which it is electrically insulated, and soldered to a ball of the BGA; the pin and the surrounding balls of the BGA, which are soldered to the metal housing, constituting a coaxial RF signal path.

Method for making wire connections

ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE

An integrated-circuit package assembly includes a separate silicon substrate (34) to which an integrated-circuit die (32) is fixed. The separate silicon substrate (34) serves as a heat spreader for the integrated-circuit die (32). The separate silicon substrate (34) to which the integrated-circuit die (32) is fixed is packaged in either a molded package body (80) or a cavity-type package body (120). For the molded package body (80), the package body is molded around a leadframe (42), the integrated-circuit die (32), and the separate silicon substrate (34) to which the integrated-circuit die (32) is fixed. For a molded package body (80), the leadframe (42) has bonding fingers formed at the inward ends thereof which are attached to the separate silicon substrate (34) or the leadframe may have a die-attach pad (20) to which is fixed the separate silicon substrate (34). For the cavity-type package (120), the package body includes a mounting surface formed adjacent to a cavity formed therein ...

COMPOUND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To solve the problem that pad electrodes are disposed in an L shape along chip corners so as to reduce the cost by shrinking the chip size in a GaAs FET adopted for a high-frequency device. SOLUTION: In order to realize a further shrinkage of the chip size and improve high-frequency characteristics of a compound semiconductor device, the pad electrodes are disposed at respective corners of the chip, and the FET is disposed at the center with inclination of 45° to the side of the chip. Thus, the chip size can be further reduced, and a lower cost GaAs FET than that of a silicon semiconductor of an ultra-high frequency can be realized. COPYRIGHT: (C)2003,JPO ...

GALLIUM ARSENIDE INTEGRATED CIRCUIT

PURPOSE:To improve an integrated circuit of this design in a heat dissipating property by a method wherein a main body of a gallium arsenide integrated circuit is mounted on a silicon substrate in one piece with a capacitor formed on the silicon substrate and a power terminal of the gallium arsenide circuit main body is connected with an electrode. CONSTITUTION:A gallium arsenide integrated circuit 10 is mounted on the central section of a silicon substrate 11 mounted on a ceramic substrate 13 and a capacitor 12 is formed on the peripheral section of the silicon substrate 11. The power terminal of the gallium arsenide integrated circuit 10 is connected with the upper and the lower electrode of the capacitor 12 through bonding wires 14 and 15 and also with a terminal of the ceramic substrate 13. The gallium.arsenic integrated circuit 10 is mounted on the central section of the silicon substrate 11 and the capacitor 12 is mounted on the peripheral section of it. A silicon oxide film 16 is ...

HIGH TEMPERATURE SOLDER, HIGH TEMPERATURE SOLDER PASTE MATERIAL AND POWER SEMICONDUCTOR EQUIPMENT USING THE SAME

PROBLEM TO BE SOLVED: To provide power semiconductor equipment using a high temperature lead-free solder material having excellent heat resistance at ≥280°C, joinability at ≤400°C, solder feedability and wettability, high temperature holding reliability and temperature cycle reliability. SOLUTION: The power semiconductor equipment is obtained by joining a semiconductor device and a metal electrode member with a high temperature solder material having a composition comprising Sn, Sb, Ag and Cu as the main constituting elements and satisfying 42 wt.%≤Sb/(Sn+Sb)≤48 wt.%, 5 wt.%≤Ag<20 wt.%, 3 wt.%≤Cu<10 wt.% and 5 wt.%≤Ag+Cu≤25 wt.%, and the balance other inevitable impurity elements. COPYRIGHT: (C)2007,JPO&INPIT ...

INFRARED IMAGE PICKUP DEVICE

PURPOSE: To obtain a vacuum vessel for infrared image pickup devices which has a high cooling efficiency and in which numerous wires are fixed and the occurrence of disconnection and fault connection of the wires are prevented even when the vessel is subjected to shocks and vibrations. CONSTITUTION: A cold head 4 for mounting an infrared image pickup element 5 is put on the top of the inner cylindrical body 1 of a vacuum vessel 3 constituted in a double-pipe structure of the inner and an outer cylindrical bodies 1 and 2. A cylindrical body 11 formed of a porous sintered member is put around the cylindrical body 1 and wires 6 lead out from the element 5 are buried in the cylindrical body 11 or passed through a through hole formed through the cylindrical body 11. COPYRIGHT: (C)1993,JPO&Japio ...

SEMICONDUCTOR POWER MODULE AND ITS MANUFACTURE

PURPOSE: To make the manufacture of a semiconductor power module easier without deteriorating the heat radiating efficiency of its main circuit so that the manufacturing cost can be reduced by fixing each of a plurality of terminals which inputs and outputs a main current or electric signals to a frame body by burying part of the terminals in the frame body. CONSTITUTION: Terminals 14a and 14b are formed in plate-like states bent in L-shapes and their upright sections are buried in the side wall section of a frame body 102 except head parts which are protruded from the upper end face of the side wall section of the frame body 102. The other horizontal sections are buried in the bottom face section of the frame body 102 so that their upper surfaces can be exposed and can be flush with the upper surface of the bottom face section of the frame body 102 and a control circuit board 101 is fixed to the upper surface of the bottom face section of the frame body 102 with adhesive 7. In addition ...

Hermetisch eingeschlossene Halbleiteranordnung

Mikrominiaturisierte, integrierte Halbleiterschaltungsanordnung

Verfahren zur Herstellung einer mikrominiaturisierten, integrierten Halbleiterschaltungsanordnung

Semi-conductor structure fabrication

... 958,241. Semi-conductor devices. TEXAS INSTRUMENTS Inc. May 6, 1960 [May 6, 1959], No. 16070/60. Heading H1K. A semi-conductor body, e.g. of germanium, silicon or intermetallic alloys is attached to an insulating, e.g. ceramic base by a cement, the thermal expansion coefficient of which matches those of the ceramic and semi-conductor. The wafer is then processed and a sealed enclosure, of which the substrate forms an external wall, formed around it. In one embodiment a semiconductor wafer in ohmic contact with metal strip or silver paste electrodes 3-6 (Fig. 1), on a ceramic base 1 is stuck to the base with a thermosetting cement, containing finely-divided glass, and is subsequently formed into a junction diode combined with a centre-tapped resistor, constituted by the semi-conductor wafer itself. A metal ring 11 (Fig. 2), coated with non-conductive glaze 12, or a ceramic ring metallized on its upper surface, is mounted on a low-melting glaze ring 13 applied over electrodes 3-7 and sealed ...

Miniature semiconductor devices and methods of producing same

... 945,734. Semi-conductor arrangements. TEXAS INSTRUMENTS Inc. Feb. 2, 1960 [Feb. 6, 1959; Feb. 12, 1959], No. 3633/60. Heading H1K. A semi-conductor arrangement comprises a monocrystalline semi-conductor wafer containing a layer of one conductivity type forming part of one major wafer face, and a layer of opposite type conductivity both layers being spaced from the other major wafer face and forming a PN junction extending to said one major face. The wafer includes discrete areas providing the electrical properties of at least two different kinds of circuit elements. A multivibrator (Fig. 6a), the circuit of which is shown in Fig. 6b, comprises such an arrangement and may be formed from a monocrystalline wafer of silicon or germanium. In a typical case antimony is first diffused into one lapped and polished face of a 3 ohm cm. P-type germanium wafer to form a 0.7 mil. thick N-type layer. The unpolished face of the wafer is then lapped to give a wafer thickness of 0.0025 in. and gold plated ...

Microwave integrated circuit

Lead frame structure and semiconductor package

A lead frame structure and semiconductor package using the same comprise a paddle (21) for mounting a chip, connection leads (23) radiating outwardly away from the paddle, upper and lower dielectric adhesive layers (24, 34) sandwiching the leads (23) therebetween, upper and lower dielectric layers (25, 35) attached on an upper surface of the upper dielectric adhesive layer (24) and a lower surface of the lower dielectric adhesive layer (34), and upper and lower metallic polar plates (26, 36) formed on an upper surface of the upper dielectric layer (25) and a lower surface of the lower dielectric layer (35). The semiconductor package decreases noise such as electromagnetic noise, reflection noise and delta-I noise by providing appropriate characteristic impedances for the leads (23) which act as signal lines and at the same time decreasing the characteristic impedances for the leads (23) which act as power lines or ground lines. The metallic plates are divided into portions (26-1 to 26-4 ...

HIGH-FREQUENCY HIGHY-POWER TRANSISTOR

Method of forming substrates

A substrate is formed by moulding a composition comprising a particulate material (e.g. alumina) and a binder to provide a planar mounting area for a heat producing element (2) (e.g. an integrated circuit chip) and a heat sink aperture (9) directly below the mounting area. The binder is then at least partly removed and the substrate sintered. A fluid may be circulated through the heat sink aperture (9) or a heat pipe system may be utilised. Conductive tracks (24) may be provided by moulding grooves in the substrate which are further filled with a conductive ink before firing. The grooves enable connecting wires (3) to cross the tracks (24) without the risk of short circuiting. A method of making a mould of reduced size from a master is described in which the uniform shrinkage of a ceramic when fired is used in a sequence of replicating steps. ...

POWER TRANSISTOR WITH INTERNALLY COMBINED LOW-PASS AND BAND-PASS FILTER ADAPTOR STAGES

SEMICONDUCTOR COMPONENT

SEMICONDUCTOR DEVICE HAVING A BOND PAD AND METHOD FOR ITS FABRICATION

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

METAL BASE CIRCUIT BOARD AND ITS PRODUCTION PROCESS

A process for producing a metal base circuit board to be used for a hybrid integrated circuit is provided, in which the integrated circuit includes a metal plate, an insulating layer on the metal plate, circuits provided on the insulating layer, a power semiconductor mounted on the circuit and a control semiconductor to control the power conductor. The method comprises forming concave portions on a principal plane at a side where the insulating layer is provided on the metal plate, applying an insulating adhesive to the concave portions and the metal plate at a portion other than the concave portions to the same level, providing a metal foil on the surface of the insulating adhesive and curing the adhesive to form a metal assembly, and processing the metal foil of the metal assembly to form circuits.

Lead frame, semiconductor device, and method for manufacturing lead frame

The present invention provides a lead frame which can reduce oxidization of the lead frame, a semiconductor device and a method for manufacturing the lead frame. The lead frame includes a plurality of leads defined by an opening extending in a thickness direction, and an insulating resin layer which fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

Insulating member, metal base substrate, and semiconductor module, and manufacturing methods thereof

Semiconductor device

Encapsulating structure for T0220F outline triode product

ELECTRONIC DEVICE, IN PARTICULAR FOR MOTOR VEHICLE ALTERNATOR

Dispositif de connexion pour circuits integres numeriques ultra-rapides

Dispositif de connexion pour circuit integre numerique ultrarapide a N entrees-sorties, destine a etre introduit dans un boitier sans broche standard a M plots tel que M ‗ N, comprenant un substrat tres mince de surface apte a occuper le logement interne du boitier, ce substrat presentant un evidement en son centre approprie a recevoir au plus juste la pastille de circuit integre, une face arriere munie d'une couche metallique pour former un plan de masse et un radiateur thermique, une face avant munie d'au moins N lignes de connexion formees par la technique dite micro-ruban d'au moins une couche metallique serigraphiee dirigee radialement du bord de l'evidement vers la peripherie du substrat en vis-a-vis de plots du boitier.

Wiring substrate and solid-state imaging apparatus using thereof

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Stacked semiconductor package and method of fabricating the same

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

Integrated circuit packaging system with die paddle and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK 1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK 2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK 1 +TK 2 ; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Packaging Integrated Circuits

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Power amplifier circuit

There is provided a power amplifier circuit capable of improving cross isolation between a high frequency band power coupler and a low frequency band power coupler, by directly transmitting power to the high frequency band power coupler and the low frequency band power coupler from a power amplifier, and forming a predetermined inductance circuit or an LC resonance circuit in a line transmitting the power to the high frequency band power coupler. The power amplifier circuit may include a power amplifying unit supplied with power from the outside and amplifying an input signal, a coupling unit having a high frequency band power coupler and a low frequency band power coupler, and an isolation unit including a first power line and a second power line, wherein the first power line has an inductor blocking signal interference generated in a predetermined frequency band.

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Semiconductor module

A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

Light emitting devices and methods

Light emitting devices and methods such as light emitting diodes (LEDs) are disclosed for use in higher voltage applications. Variable arrangements of LEDs are disclosed herein. Arrangements can include one or more LED chips connected in series, parallel, and/or a combination thereof. LED chips can be disposed in a package body having at least one thermal element and one or more electrical components.

semiconductor package and a method for selecting a chip in the semiconductor package

A semiconductor package includes a first semiconductor chip formed with a first through-silicon via; a second semiconductor chip stacked over the first semiconductor chip and formed with a second through-silicon via; and a cantilever formed over the first semiconductor chip and electrically connected to the first through-silicon via or the second through-silicon via according to an electrical signal.

Semiconductor Device

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Microelectronic package and method of manufacturing same

A microelectronic package includes a substrate ( 110, 210 ), an interposer ( 120, 220 ) having a first surface ( 121 ) and an opposing second surface ( 122 ), a microelectronic die ( 130, 230 ) attached to the substrate, and a mold compound ( 140 ) over the substrate. The interposer is electrically connected to the substrate using a wirebond ( 150 ). The first surface of the interposer is physically connected to the substrate with an adhesive ( 160 ), and the second surface has an electrically conductive contact ( 126 ) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.

Semiconductor device

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Light emitting device and display device including the same

A light emitting device package is disclosed. The light emitting device package includes a body, first and second reflection cups spaced apart from each other in a top surface of the body, a first connection pad disposed in the top surface of the body, spaced apart from the first and second reflection cups, a first light emitting diode mounted in the first reflection cup, a second light emitting diode mounted in the second reflection cup, and a partition wall disposed between the first reflection cup and the second reflection cup, the partition wall extended from the top surface of the body upwardly.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Apparatus and methods for electronic amplification

Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved.

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

Semiconductor device, manufacturing method thereof, and mobile telephone

Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

System and Method for Packaging of High-Voltage Semiconductor Devices

A method and an electronic device structure comprising at least one access lead to adapted to be connected to an electrical circuit; at least one substrate region; at least one semiconductor die positioned on the substrate; the at least one semiconductor die being operatively connected to the at least one access lead; a dielectric region extending below the at least one semiconductor die; the dielectric region being formed by creating a cavity in the at least one substrate region; whereby the dielectric region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown. The method of making an electronic device structure comprises providing at least one substrate region; providing at least one semiconductor die located on the at least one substrate region; removing a portion of the at least one substrate region to provide a dielectric region within the substrate extending below the at least one semiconductor die; whereby the dielectric region within the at least one substrate region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown.

Light emitting module

Disclosed herein is a light emitting module. The light emitting module according to an exemplary embodiment includes a circuit board having a cavity and including a circuit pattern at a region which does not have the cavity, an insulation substrate disposed in the cavity while being formed, at an upper portion thereof, with at least one pad, and at least one light emitting device disposed on the pad, wherein a joining structure is disposed between a bottom surface of the cavity and a bottom surface of the insulation substrate.

Semiconductor device

A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

Power semiconductor module with wireless saw temperature sensor

A power semiconductor module includes a housing, a base plate disposed in the housing, a plurality of substrates mounted to the base plate, a plurality of power transistor die mounted to the substrates and a plurality of terminals mounted to the substrates and protruding through the housing. The terminals are in electrical connection with the power transistor die. The power semiconductor module further includes a wireless surface acoustic wave (SAW) temperature sensor disposed in the housing of the power semiconductor module.

Light emitting device and light unit having the same

A light emitting device includes a body having a first recess; a barrier section having a second recess and a third recess, protruding upward over a bottom surface of the first recess, and dividing the bottom surface of the first recess into a first region and a second region; a first light emitting diode disposed in the first region; a second light emitting diode disposed in the second region; a first lead electrode disposed in the first region; a second lead electrode disposed in the second region; a first wire electrically connecting the first lead electrode to the second light emitting diode through the second recess; and a second wire electrically connecting the second lead electrode to the first light emitting diode through the third recess.

Multi-Die LED Package

A light-emitting device comprising (a) a submount having front and back sides and including a ceramic layer; (b) an array of light-emitting diodes (LEDs) on the front side; and (c) a lens overmolded on the submount and covering the LED array. In some embodiments, the submount comprises at least two electrically-conductive contact pads on the front side, and each LED in the array is secured with respect to one of the contact pads.

Integrated circuit including a differential power amplifier with a single ended output and an integrated balun

An integrated circuit, including, a die with an electronic circuit embedded thereon; wherein the electronic circuit includes a differential power amplifier and pads to electronically interface with the electronic circuit; a packaging encasing the die with contact pins to connect between the integrated circuit and external elements; wires connecting between the pads and the contact pins; a converter that includes capacitors and inductors to combine the outputs from the differential power amplifier to form a single ended output at one of the contact pins; wherein inherent inductance of some of the wires serve as the inductors of the converter.

Temperature compensation attenuator

In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change.

Structure for High-Speed Signal Integrity in Semiconductor Package with Single-Metal-Layer Substrate

A semiconductor chip ( 101 ) with bond pads ( 110 ) on a substrate ( 103 ) with rows and columns of regularly pitched metal contact pads ( 131 ). A zone comprises a first pair ( 131 a, 131 b ) and a parallel second pair ( 131 c, 131 d ) of contact pads, and a single contact pad ( 131 e ) for ground potential; staggered pairs of stitch pads ( 133 ) connected to respective pairs of adjacent contact pads by parallel and equal-length traces ( 132 a, 132 b , etc.). Parallel and equal-length bonding wires ( 120 a, 120 b , etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

Lighting device including light-emitting element

In accordance with a first aspect of the present inventive subject matter, a lighting device includes light-emitting elements arranged in lines that are extended in parallel with one another, the light-emitting elements being divided into groups each including the same number of light-emitting elements, a first connecting electrode is disposed adjacent to one end portion of the lines extended, a second connecting electrode is disposed adjacent to another end portion of the lines extended, and the light-emitting elements within each group are electrically connected in series with one another by metallic wires and electrically connected in series to the first connecting electrode and to the second connecting electrode. The groups each include the same number of light-emitting elements that are electrically connected in parallel between the first connecting electrode and the second connecting electrode.

Semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Method of forming a semiconductor device and leadframe therefor

In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

Discrete power transistor package having solderless dbc to leadframe attach

A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

Complex Semiconductor Packages and Methods of Fabricating the Same

Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips.

Power semiconductor apparatus

A power semiconductor apparatus which is provided with a first power semiconductor device using Si as a base substance and a second power semiconductor device using a semiconductor having an energy bandgap wider than the energy bandgap of Si as a base substance, and includes a first insulated metal substrate on which the first power semiconductor device is mounted, a first heat dissipation metal base on which the first insulated metal substrate is mounted, a second insulated metal substrate on which the second power semiconductor device is mounted, and a second heat dissipation metal base on which the second insulated metal substrate is mounted.

Lead frame, semiconductor device, and method for manufacturing lead frame

A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

Dual Power Converter Package Using External Driver IC

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively.

Semiconductor packages

A semiconductor package includes a master chip and a slave chip stacked on a substrate. The master chip and the slave chip are connected to one another by a bonding wire. The master chip and the slave chip are connected in series with an external circuit. The semiconductor package may have a low loading factor and excellent performance, and may be mass produced at low costs.

Light emitting lamp

Disclosed is a light emitting lamp including a light source module including at least one light source and a light guide layer disposed on a substrate burying the at least one light source, and a housing accommodating the light source module, and the at least one light source includes a body having a cavity, a first lead frame including one end exposed to the cavity and the other end passing through the body and exposed to one surface of the body, a second lead frame including one end exposed to one portion of the surface of the body, the other end exposed to the another portion of the surface of the body, and an intermediate part exposed to the cavity, and at least one light emitting chip including a first semiconductor layer, an active layer and a second semiconductor layer, and disposed on the first lead frame.

Semiconductor device

A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

Circuit device

A circuit device having superior voltage resistance is provided. A structure is achieved that omits the resin layer that is normally provided to the top surface of a circuit board. Specifically, a ceramic substrate ( 22 ) is disposed on the top surface of a circuit board ( 12 ) comprising a metal, and a transistor ( 34 ) such as an IGBT is mounted to the top surface of the ceramic substrate ( 22 ). As a result, the transistor ( 34 ) and the circuit board ( 12 ) are insulated from each other by the ceramic substrate ( 22 ). The ceramic substrate ( 22 ), which comprises an inorganic material, has an extremely high voltage resistance compared to the conventionally used insulating layer comprising resin, and so even if a high voltage on the order of 1000V is applied to the transistor ( 34 ), short circuiting between the transistor ( 34 ) and the circuit board ( 12 ) is prevented.

Rf power amplifier

A reduction is achieved in the primary-side input impedance of a transformer (voltage transformer) as an output matching circuit without involving a reduction in Q-factor. An RF power amplifier includes transistors, and a transformer as the output matching circuit. The transformer has a primary coil and a secondary coil which are magnetically coupled to each other. To the input terminals of the transistors, respective input signals are supplied. The primary coil is coupled to each of the output terminals of the transistors. From the secondary coil, an output signal is generated. The primary coil includes a first coil and a second coil which are coupled in parallel between the respective output terminals of the transistors, and each magnetically coupled to the secondary coil. By the parallel coupling of the first and second coils of the primary coil, the input impedance of the primary coil is reduced.

Multichip package structure for generating a symmetrical and uniform light-blending source

A multichip package structure for generating a symmetrical and uniform light-blending source includes a substrate unit, a light-emitting unit and a package unit. The substrate unit includes a substrate body and at least one bridging conductive layer disposed on the top surface of the substrate body. The light-emitting unit includes at least two first light-emitting elements diagonally disposed on the substrate body and electrically connected to the substrate body and at least two second light-emitting elements diagonally disposed on the substrate body and electrically connected to the substrate body. The package unit includes at least two first light-transmitting package bodies respectively covering the at least two first light-emitting elements and at least two second light-transmitting package bodies respectively covering the at least two second light-emitting elements.

Semiconductor device and system using the same

There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Manufacturing method of semiconductor device and semiconductor device

To enhance the reliability of a semiconductor device. The semiconductor device includes die pads, over which a first semiconductor chip and a second semiconductor chip are mounted respectively, a plurality of support pins that support each of the die pads, a plurality of inner leads and outer leads arranged around the die pads, a plurality of wires that electrically couple the semiconductor chips to the inner leads, and a sealing body that seals the semiconductor chips, the inner leads, and the wires. Each of the die pads is supported by three support pins integrally formed together with the die pad, and each of second support pins of each pair of the three support pins is arranged between the inner leads adjacent to each other.

Semiconductor device and method of detecting wire open failure thereof

In a semiconductor device, two series connections are arranged to be connected between respective split emitter electrodes and a gate electrode with Zener diode units connected in series to respective resistors, with the cathode sides thereof directed to the gate electrode side. The numbers of the Zener diodes in the Zener diode units in the respective series connections are different between the respective Zener diode units. Thus, a semiconductor device can be provided which is capable of detecting an open failure of a bonding wire regardless of the number of a plurality of the bonding wires connected in parallel, by a simple electrical test to make it possible to reliably sort out a semiconductor device with a wire open failure at an early stage.

Semiconductor device including semiconductor chip mounted on lead frame

A semiconductor device includes a lead frame, a semiconductor chip, a substrate, a plurality of chip parts, a plurality of wires, and a resin member. The lead frame includes a chip mounted section and a plurality of lead sections. The semiconductor chip is mounted on the chip mounted section. The substrate is mounted on the chip mounted section. The chip parts are mounted on the substrate. Each of the chip parts has a first end portion and a second end portion in one direction, and each of the chip parts has a first electrode at the first end portion and a second electrode at the second end portion. Each of the wires couples the second electrode of one of the chip parts and one of the lead sections. The resin member covers the lead frame, the semiconductor chip, the substrate, the chip parts, and the wires.

Semiconductor package

Provided are a semiconductor die and a semiconductor package. The semiconductor package includes: a monolithic die; a driving circuit, a low-side output power device, and a high-side output power device disposed in the monolithic die; and an upper electrode and a lower electrode disposed above and below the monolithic die.

Power semiconductor module

A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate. 1. A packaged microelectronic device , comprising:an interposer substrate having a first side with a plurality of interposer contacts and a second side opposite the first side, the second side including a plurality of interposer pads arranged in an array corresponding to a standard JEDEC pinout;a microelectronic die attached and electrically coupled to the interposer substrate;a casing covering the die and at least a portion of the interposer substrate, wherein the casing has a thickness and a top facing away from the interposer substrate; anda plurality of electrically conductive through-casing interconnects in contact with and projecting from corresponding interposer contacts, wherein the through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing, and wherein the through-casing interconnects are at least partially encapsulated in the casing,wherein the through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to ...

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode. 1. A semiconductor component having at least first and second terminals , comprising:a leadframe having first and second opposing sides, a device receiving area, and a first lead integrally formed with the leadframe;an insulated metal substrate having a first surface and a second surface, the second surface coupled to the leadframe;a first semiconductor chip mounted to the insulated metal substrate, the first semiconductor chip having first and second surfaces, a first gate bond pad, a first source bond pad, and a first drain bond pad, the first semiconductor chip configured from a III-N semiconductor material, wherein the second surface of the first semiconductor chip is coupled to the insulated metal substrate; anda second semiconductor chip mounted to the first semiconductor chip and having first and second surfaces, an anode formed from the first surface and a cathode formed from the second surface, wherein the cathode is coupled to the first source bond pad.2. The semiconductor component of claim 1 , further including a second lead that is electrically isolated from the leadframe and wherein the first gate bond pad is electrically coupled to ...

Electronic Circuit and Substrate with Identification Pattern for Separate Electronic Circuits and Method for Producing Thereof

The present invention relates to an improved electronic circuit, as well as an improved substrate with electronic circuits, with an identification pattern. The invention makes it possible to make them identifiable and amongst other things to retrace the circuit(s) in this way through the production process. Furthermore, the invention relates to an improved production method for circuits and substrates according to the invention.

Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops

A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.

Semiconductor Device and Power Conversion Apparatus

Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced. The semiconductor device according to the present invention is characterized by: being provided with a semiconductor chip having a gate structure represented by an IGBT; including first gate wiring and second gate wiring formed on the surface of the semiconductor chip; and including an emitter electrode disposed so as to cover the first gate wiring and a sintered layer disposed above the emitter electrode, wherein a multilayer structure formed by including at least the emitter electrode and the sintered layer on the surface of the semiconductor chip continuously exists over a range including an emitter electrode connecting contact and gate wiring regions. 110.-. (canceled)11. A semiconductor device comprising:a semiconductor chip;a first gate wiring and a second gate wiring formed on a front surface of the semiconductor chip;an emitter electrode arranged so as to cover the first gate wiring; anda sintered layer arranged above the emitter electrode,wherein a multilayer structure consisting of at least the emitter electrode and the sintered layer is continuously present over a range including an emitter electrode connecting contact and a gate wiring region on the front surface of the semiconductor chip.12. The semiconductor device according to claim 11 , whereinthe semiconductor chip is joined to a collector wiring on a common ceramic substrate together with a diode chip by another sintered layer separated from the sintered layer.13. The semiconductor device according to claim 11 , whereinthe multilayer structure is configured to include an electrode layer, which contains nickel (Ni) as a ...

Method of manufacturing a semiconductor device

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

GUARD BOND WIRES IN AN INTEGRATED CIRCUIT PACKAGE

An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first and second end coupled to ground. The second guard bond wire has a first and second end coupled to ground. The integrated circuit package further comprises a die. The die is mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die. 1. An integrated circuit package , comprising:a first guard bond wire having a first and second end coupled to ground;a second guard bond wire having a first and second end coupled to ground;a die mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die, wherein the die has a surface area with a first side and a second side that is opposite to the first side and at least a portion of the first guard bond wire is aligned with the first side of the die and at least a portion of the second guard bond wire is aligned with the second side of the die; anda flange on which the die is mounted;wherein the at least a portion of the first guard bond wire is aligned with the first side such that the at least a portion of the first bond wire runs parallel to the first side of the die, and wherein the at least a portion of the second guard bond wire is aligned with the second side such that the at least a portion of the second guard bond wire runs parallel to the second side of the die,wherein the first and/or second end of the first guard bond wire is/are coupled to ground through a flange mounted first and/or second capacitor, respectively, and the first and/or second end of the second guard bond wire is/are coupled to ground through a flange mounted third and/or fourth capacitor, respectively.215-. (canceled)16. The ...

Mounting component, semiconductor device using same, and manufacturing method thereof

A mounting component includes a main body and a metal layer. The main body has a first main surface and a second main surface. The metal layer is arranged on the first main sur face of the main body. The metal layer includes at least one concave recognition mark having an inclined surface that is inclined with respect to a main surface of the metal layer.

MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME

An integrated circuit package includes a lead frame and an encapsulation that substantially encloses the lead frame. The lead frame further includes a first conductor comprising a first conductive loop and a second conductor galvanically isolated from the first conductor, proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductor. The second conductor includes a first conductive portion, a second conductive portion, and a wire coupling together the first conductive portion and the second conductive portion. 1. An integrated circuit package , comprising:an encapsulation; and a first conductive loop disposed substantially within the encapsulation;', 'a second conductive loop disposed substantially within the encapsulation and substantially all of the second conductive loop is outside of the first conductive loop; and', 'wherein the first and second conductive loops are configured to form a magnetically coupled communication link.', 'a galvanic isolator coupled to the first conductive loop such that there is galvanic isolation between the first and the second conductive loops,'}], 'a lead frame, a portion of the lead frame disposed within the encapsulation, the lead frame comprising2. The integrated circuit package of claim 1 , further comprising:a first circuit coupled to the first conductive loop; and wherein one of the first and second circuits is configured to control properties of a transmitter current to produce a changing magnetic field in proximity to a corresponding one of the first and second conductive loops, thereby inducing a voltage that is generated across an other one of the first and second conductive loops that is subjected to the changing magnetic field and results in a current flow in the other one of the inner and outer conductive loops, and', 'wherein the other one of the first and second circuits is configured to receive an electrical parameter induced by the one of ...

Heterojunction Semiconductor Device for Reducing Parasitic Capacitance

A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer. 1. A semiconductor device , comprising:an active layer made of III-V group semiconductor materials;a source electrode disposed on the active layer;a drain electrode disposed on the active layer;a gate electrode disposed above the active layer and between the source electrode and the drain electrode;a gate field plate disposed above the active layer;an interlayer dielectric covering the source electrode, the drain electrode, the gate field plate, and the gate electrode, the interlayer dielectric having a plurality of inter-gate via holes;an inter-source layer disposed on the interlayer dielectric and electrically connected to the source electrode;an inter-drain layer disposed on the interlayer dielectric and electrically connected to the drain electrode;an inter-gate layer disposed on the interlayer dielectric, wherein the gate field plate is separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer; anda plurality of inter-gate plugs filled into the inter-gate via holes;wherein at least one of the inter-gate via holes positioned on the gate field ...

III-Nitride Device and FET in a Package

One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces. 132-. (canceled)33. A semiconductor device comprising:a first lead frame formed integral with first two terminals respectively extending from the first lead frame, the first two terminals including respective curved portions curved so that edges of the first two terminals are placed in line with other lead terminals than the first two terminals in a plain view, each of the respective curved portions having two mutually opposing and continuously curved edges each having a center of curvature located on a same side of said each edge in plan view as proceeding along said each edge;a first elongated semiconductor chip mounted on the first lead frame and having a first edge and a second edge in plan view, the first edge being parallel to a longitudinal direction of the first elongated semiconductor chip and greater in length than the second edge, the second edge being perpendicular to the first edge;an isolator chip mounted on the first lead frame;a second lead frame formed with second two terminals respectively extending from the second lead frame, the second two terminals are curved so that edges of the second ...

Multi-chip package structure

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

Multichip package manufacturing process

Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

APPARATUS FOR MEASURE OF QUANTITY AND ASSOCIATED METHOD OF MANUFACTURING

An integrated device provides a measure of a quantity dependent on current through an electrical conductor, having: a sensing and processing sub-system; an electrical conductor conducting current; an insulating material encapsulates the sensing and processing sub-system and maintains the electrical conductor in a fixed and spaced relationship to the sensing and processing sub-system. The insulating material insulates the electrical conductor from the sensing and processing sub-system. Sensing and processing sub-system sensing circuitry includes magnetic field sensing elements adjacent the electrical conductor. The sensing circuitry provides a measure of the quantity as a weighted sum and/or difference of magnetic field sensing elements outputs caused by current through the electrical conductor adjacent the magnetic field sensing elements. A voltage sensing input senses a measure of voltage associated with the current conductor. Sensing and processing sub-system output circuitry provides an output measure of the quantity from the sensed measure of current and voltage. 1. An integrated device for providing a measure of at least one quantity dependent on the current through an electrical conductor , the device comprising:a sensing and processing sub-system comprising at least a sensing face arranged to be placed in proximity to an electrical conductor conducting a current, the sensing face comprising sensing circuitry, the sensing circuitry comprising at least one magnetic field sensing element and configured to measure the quantity as a combination of outputs of the at least one magnetic field sensing element caused by the current flowing through the electrical conductor;a voltage sensing input for sensing a measure of a voltage; andinput-output circuitry arranged to provide an output measure of at least one quantity from the sensed current and the sensed voltage,wherein one or more of the at least one magnetic field sensing element is arranged to be biased by a ...

Semiconductor module

A semiconductor module according to the present disclosure includes: an insulating substrate; a first conductor disposed on the insulating substrate; a second conductor disposed on the insulating substrate; a first semiconductor element disposed on the first conductor; a second semiconductor element disposed on the second conductor; a first busbar connected to the first conductor in a region between the first semiconductor element and the second semiconductor element; a second busbar connected to the second semiconductor element; and an output busbar connecting the first semiconductor element to the second conductor and connected to the second conductor in the region between the first semiconductor element and the second semiconductor element. The output busbar is disposed at least partially overlapping the first busbar, and in an overlap region between the output busbar and the first busbar, the output busbar is located above the first busbar.

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

SEMICONDUCTOR DEVICE

The disclosure provides a semiconductor device. The device includes first and second substrates, first mounting layers, second mounting layers, power supply terminals, an output terminal, electroconductive coupling members and switching elements. The first substrate has first obverse and reverse surfaces facing in a thickness direction. The second substrate has a second obverse surface facing as the first obverse surface faces in the thickness direction and a second reverse surface facing away from the second obverse surface. The second substrate is spaced from the first substrate in a first direction crossing the thickness direction. The first mounting layers are electrically conductive and disposed on the first obverse surface. The second mounting layers are electrically conductive and disposed on the second obverse surface. The power supply terminals are electrically connected to the first mounting layers. The output terminal is connected to one of the second mounting layers. The electroconductive coupling members are connected to the first and second mounting layers. The switching elements are mounted on the first and second mounting layers. Each of the electroconductive coupling members has strip sections and a connecting section. The strip sections extend in the first direction and are spaced in a second direction crossing the thickness direction and the first direction. The connecting section extends in the second direction to interconnect the strip sections. The strip sections are connected at one end to the first mounting layer and connected at another end to the second mounting layer. 1. A semiconductor device comprising:a first substrate having a first obverse surface and a first reverse surface each facing in a thickness direction;a second substrate spaced apart from the first substrate in a first direction perpendicular to the thickness direction, the second substrate having a second obverse surface facing in a direction in which the first obverse ...

Doherty amplifier

A package ( 1 ) includes first and second input terminals ( 2,3 ) which are adjacent to each other, and first and second output terminals ( 4,5 ) which are adjacent to each other. A first input matching circuit ( 6 ), a first delay circuit ( 7 ), a second input matching circuit ( 8 ), a first amplifier ( 9 ), and a first output matching circuit ( 10 ) are sequentially connected between the first input terminal ( 2 ) and the first output terminal ( 4 ) inside the package ( 1 ). A third input matching circuit ( 11 ), a second amplifier ( 12 ), a second output matching circuit ( 13 ), a second delay circuit ( 14 ), and a third output matching circuit ( 15 ) are sequentially connected between the second input terminal ( 3 ) and the second output terminal ( 5 ) inside the package ( 1 ). First to fourth matching circuits ( 16 - 19 ) are respectively connected to the first input terminal ( 2 ), the second input terminal ( 3 ), the first output terminal ( 4 ) and the second output terminal ( 5 ) outside the package ( 1 ).

Lighting Device

A lighting device according to an embodiment includes a body section; a substrate that is provided in the body section; a wiring pattern that is provided on a surface of the substrate and has a plurality of wiring pads; a plurality of light emitting elements that are provided on the wiring pattern and have electrodes in the vicinity of a the circumference edge of a surface opposite to a side on which the wiring pattern is provided; a plurality of wirings that respectively connect the plurality of wiring pads and a plurality of electrodes; a surrounding wall member that is provided so as to surround the plurality of light emitting elements and has an annular shape; and a sealing section that is provided so as to cover the inside of the surrounding wall member. Then, at least a part of the plurality of light emitting elements is connected in series. The plurality of electrodes are respectively positioned on or inside a circumference passing through centers of the plurality of light emitting elements which are connected in series centered on a first position in electric connection between the light emitting element and the light emitting element in the plurality of light emitting elements connected in series.

Multi-path amplifier circuit or system and methods of implementation thereof

Power amplifiers such as multi-path power amplifiers, systems employing such amplifiers, and methods of implementing amplifiers and amplifier systems are disclosed herein. In one example embodiment, a multi-path power amplifier includes a first semiconductor die with an integrated first transistor having a first source-to-drain pitch, and a second semiconductor die with an integrated second transistor having a second source-to-drain pitch, where the second source-to-drain pitch is smaller than the first source-to-drain pitch by at least 30 percent. In another example embodiment, a Doherty amplifier system includes a first semiconductor die with a first physical die area to total gate periphery ratio, and a second semiconductor die with a second physical die area to total gate periphery ratio, where the second physical die area to total gate periphery ratio is smaller than the first physical die area to total gate periphery ratio by at least 30 percent.

ELECTRONIC CIRCUIT

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode. 1. A semiconductor device comprising:a MOSFET including a PN junction diode;a unipolar device connected in parallel to the MOSFET and having two terminals;an output line;a first wire that connects an anode of the PN junction diode to one of the two terminals of the unipolar device; anda second wire that connects the one of the two terminals of the unipolar device to the output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire,wherein the first wire and the second wire are continuous with each other.2. The semiconductor device according to claim 1 , wherein an operating voltage of the unipolar device is lower than an operating voltage of the PN junction diode.3. The semiconductor device according to claim 1 , wherein the MOSFET is an SiC semiconductor device made of a semiconducting material that chiefly includes SiC.4. The semiconductor device according to claim 1 , wherein a counter electromotive force generated by an inductance between the unipolar device and the output line is 2.0 V or more.5. The semiconductor device according to claim 1 , wherein the unipolar device includes a Schottky barrier diode.6. The semiconductor device according to claim 5 , whereinthe first wire connects the anode of the PN junction diode to an anode of the Schottky barrier diode, andthe second wire connects the anode of the Schottky ...

Light emitting device and method for manufacturing the same

Provided is a light emitting device that reduces color unevenness between a plurality of light emitting elements. A light emitting device 1 includes a base substrate 10, a first frame body 11 disposed at an upper surface 10 a of the base substrate 10, and a second frame body 12 disposed at the upper surface 10 a of the base substrate 10 and surrounding the first frame body 11 while being spaced away from the first frame body 11 . A plurality of light emitting elements 2 is disposed within a region surrounded by the first frame body 11 . A first sealing resin 21 is disposed within the region surrounded by the first frame body 11 to cover the light emitting elements 2 . The first sealing resin 21 includes a wavelength conversion member that converts a wavelength of light emitted from the light emitting elements 2 . A second sealing resin 22 is disposed within the region surrounded by the second frame body 12 to cover the first sealing resin 21 . The second sealing resin 22 has a light diffusion material layer 221 having a convex upper surface over the first sealing resin 21.

Multi-chip package

A multi-chip package may include a package substrate including a first substrate pad and a second substrate pad, first semiconductor chips stacked on the package substrate in a steplike shape along a first direction, second semiconductor chips stacked on the first semiconductor chips in a steplike shape along a second direction opposite the first direction, first pad wires electrically connecting first bonding pads of the first semiconductor chips with each other, second pad wires electrically connecting second bonding pads of the second semiconductor chips with each other, a first substrate wire electrically connecting the first substrate pad with a first bonding pad of any one among the first semiconductor chips except for a lowermost first semiconductor chip, and a second substrate wire electrically connecting the second substrate pad with a second bonding pad of any one among the second semiconductor chips except for a lowermost second semiconductor chip.

Polymer battery cell and electronic device comprising same

Disclosed are a polymer battery cell capable of increasing cell capacity due to efficient use of space by efficiently placing a protection circuit device, and thus of effectively protecting the protection circuit device from an external environment, and an electronic device including the polymer battery cell. The polymer battery cell includes an electrode body including a positive plate, a negative plate, and a separator provided between the positive and negative plates, cell taps including a positive tap connected to and protruding from the positive plate, and a negative tap connected to and protruding from the negative plate, and a battery protection circuit module electrically connected to the cell taps. The polymer battery cell further includes a pouch receiving the electrode body, the cell taps, and the battery protection circuit module therein, and being made of a flexible material.

BIPOLAR TRANSISTOR ON HIGH-RESISTIVITY SUBSTRATE

Systems and methods are disclosed for fabricating a semiconductor die that includes one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference. 1. A method of fabricating a semiconductor die comprising:forming a bulk silicon substrate having a high-resistivity portion;forming a silicon-germanium bipolar transistor on the bulk silicon substrate, the silicon-germanium bipolar transistor configured as a power amplifier, the bulk silicon substrate including a low-resistivity well at least partially surrounding the silicon-germanium bipolar transistor, the bulk silicon substrate further including a trench disposed adjacent to the low-resistivity well;integrating a front-end module on the high-resistivity bulk silicon substrate, the front-end module including the power amplifier, a switch, and a plurality of filters; andforming a complementary metal oxide semiconductor field-effect transistor device on the bulk silicon substrate.2. The method of further comprising implanting a low-resistivity substrate on a top surface of the substrate and disposing one or more digital circuit devices on the low-resistivity substrate.3. The method of wherein the low-resistivity substrate is implanted so as to at least partially surround a radio frequency element of the front-end module.4. The method of wherein the bulk silicon substrate is grown using a silicon seed.5. The method of wherein the silicon-germanium bipolar transistor conditions or creates electronic signals.6. The method of further comprising forming a low-resistivity epitaxial layer adjacent to a first ...

SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE SHINGLED STACKS OF SEMICONDUCTOR DIES

A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack. 1. A method of making a memory device , comprising:providing a substrate;stacking a first plurality of semiconductor dies on the substrate in a first shingled stack;stacking a second plurality of semiconductor dies on the substrate in a second shingled stack;wirebonding, subsequent to stacking the first and second shingled stacks, the first and second pluralities of semiconductor dies to the substrate; andproviding an encapsulant to at least partially encapsulate the substrate, the first shingled stack and the second shingled stack.2. The method of claim 1 , wherein the wirebonding is performed in a single operation uninterrupted by any stacking.3. The method of claim 2 , wherein:the first plurality of semiconductor dies is stacked directly over a first location on the substrate, andthe second plurality of semiconductor dies is stacked directly over a second location on the substrate.4. The method of claim 2 , further comprising:stacking a third plurality of semiconductor dies in a third shingled stack;stacking a fourth plurality of semiconductor dies in a fourth shingled stack; andwirebonding, subsequent to stacking the third and fourth shingled stacks, the third and fourth pluralities of semiconductor dies to the substrate.5. The method of claim 4 , wherein wirebonding the first and second pluralities of semiconductor dies to ...

Heterojunction Semiconductor Device for Reducing Parasitic Capacitance

A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer. 1an active layer;at least one source electrode disposed on the active layer, an orthogonal projection of the source electrode on the active layer forming a source region;at least one drain electrode disposed on the active layer, the drain electrode being separate from the source electrode, and an orthogonal projection of the drain electrode on the active layer forming a drain region;at least one gate electrode disposed above the active layer and between the source electrode and the drain electrode;a gate field plate disposed above the active layer and adjacent to the gate electrode;an interlayer dielectric covering the source electrode, the drain electrode, the gate field plate, and the gate electrode, the interlayer dielectric having at least one first inter-source via hole above the source electrode, at least one first inter-drain via hole above the drain electrode, and at least one inter-gate via hole above the gate field plate;an inter-source layer disposed on the interlayer dielectric and electrically connected to the source electrode through an inter-source plug disposed in the inter-source via ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD

A semiconductor device, including a semiconductor element, and a first wiring member and a second wiring member bonded to each other and being electrically connected to the semiconductor element. The first wiring member has an irradiation area for receiving irradiation of a laser beam. The semiconductor device also includes a protection member disposed on an area of the second wiring member opposite the irradiation area of the first wiring member, the protection member having a melting point higher than a melting point of at least one of the first wiring member and the second wiring member including the area on which the protection member is disposed. 1. A semiconductor device comprising:a semiconductor element;a first wiring member and a second wiring member bonded to each other and being electrically connected to the semiconductor element, the first wiring member having an irradiation area for receiving irradiation of a laser beam; anda protection member disposed on an area of the second wiring member opposite the irradiation area of the first wiring member, the protection member having a melting point higher than a melting point of at least one of the first wiring member and the second wiring member including the area on which the protection member is disposed.2. The semiconductor device according to claim 1 , wherein:the second wiring member is bonded to the first wiring member at a bonding plane;the irradiation area is on a first principal plane of the first wiring member opposite the bonding plane; andthe area on which the protection member is disposed is on a second principal plane of the second wiring member opposite the bonding plane.3. The semiconductor device according to claim 2 , wherein one or more wiring members are laminated between the first wiring member and the second wiring member.4. The semiconductor device according to claim 1 , wherein:the second wiring member is bonded to the first wiring member at a bonding plane;the irradiation area of the ...

Semiconductor device manufacturing method

This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.

Semiconductor component and method of manufacture

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

SOLID STATE DRIVE PACKAGE AND DATA STORAGE SYSTEM INCLUDING THE SAME

A solid state drive (SSD) package type has a lower package including a lower package substrate, a controller chip mounted on the lower package substrate, and a plurality of upper packages disposed on the lower package as spaced apart from each other. The plurality of upper packages includes at least one non-volatile memory and at least one first individual electronic component. The upper packages are electrically connected to the lower package such that the package type is a package-on-package (PoP) type. The height of the first individual electronic component is greater than the spacing between the lower package and each of the upper packages. 1. A solid state drive (SSD) package-on-package (PoP) , comprising:a lower package comprising a lower package substrate, a controller chip disposed on and mounted to the lower package substrate, and a lower mold layer on an upper surface of the lower package substrate and covering the controller chip; anda plurality of upper packages disposed on the lower package as spaced laterally apart from each other, and including a non-volatile memory package comprising a non-volatile memory and an individual component package comprising an individual electronic component, the non-volatile memory and the individual electronic component being electrically connected to the lower package,wherein the height of the first individual electronic component is greater than a thickness of the lower mold layer at the controller chip as measured from the upper surface of the lower package substrate.2. The SSD package-on-package of claim 1 , wherein the lower package further comprises a semiconductor memory chip mounted on the lower package substrate as laterally spaced apart from the controller chip claim 1 , and the non-volatile memory package spans the semiconductor memory chip as viewed in plan.3. The SSD package-on-package of claim 2 , wherein the semiconductor memory chip comprises a non-volatile memory.4. The SSD package-on-package of claim 1 ...

Semiconductor device

Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

SEMICONDUCTOR DEVICE

A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a source pad, a drain pad, and a source external connecting element. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The source pad is electrically connected to the source electrode and includes a body portion, a plurality of branch portions, and a current diffusion portion. The body portion is at least partially disposed on the active region of the active layer. The current diffusion portion interconnects the body portion and the branch portions. A width of the current diffusion portion is greater than a width of the branch portion and less than a half of a width of the body portion. The source external connecting element is disposed on the body portion and spaced from the current diffusion portion. 1. A semiconductor device , comprising:an active layer having an active region;a source electrode, a drain electrode, and a gate electrode disposed on the active region of the active layer; a body portion at least partially disposed on the active region of the active layer, wherein the body portion of the source pad extends along a first direction;', 'a plurality of branch portions extending along a second direction different from the first direction; and', 'at least one current diffusion portion interconnecting the body portion of the source pad and the branch portions of the source pad and extending along the first direction, wherein a width of the current diffusion portion of the source pad is greater than a width of one of the branch portions of the source pad and less than a half of a width of the body portion of the source pad;, 'a source pad electrically connected to the source electrode, wherein the source pad comprisesa drain pad electrically connected to the drain electrode; andat least one source external connecting element disposed on the body portion of the source pad and spaced ...

SWITCHING DEVICE AND ELECTRONIC CIRCUIT

A switching device includes a SiC semiconductor chip which has a gate pad , a source pad and a drain pad and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal electrically connected to the source pad for applying the drive voltage, and an external resistance (source wire ) that is interposed in a current path between the sense source terminal and the source pad , is separated from sense source terminal , and has a predetermined size. 18-. (canceled)9. A switching device including:a switching element having a gate electrode, a first output electrode, and a second output electrode;a second output terminal electrically connected to the second output electrode and having an island on which the switching element is mounted;a gate terminal electrically connected to the gate electrode;a first output terminal electrically connected to the first output electrode;a third output terminal electrically connected to the first output electrode and spaced apart from the first output terminal, anda resin package sealing the switching element, a part of the gate terminal, a part of the first output terminal, a part of the third output terminal and a part of the second output terminal; whereinthe gate terminal, the first output terminal, the third output terminal and the second output terminal each include a sealing portion sealed in the resin package and a terminal portion protruding in the same direction with respect to the resin package and protruding therefrom,the distance between the terminal portion of the first output terminal and the terminal portion of the second output terminal is greater than the distance between the terminal portion of the third output terminal and the terminal portion of the gate terminal.10. The switching device according to claim 9 , wherein the first output electrode ...

Load balancing in discrete devices

In a general aspect, an apparatus can include a temperature measurement circuit configured to produce a first signal indicating a first operating temperature of a first semiconductor device and a temperature comparison circuit operationally coupled with the temperature measurement circuit. The temperature comparison circuit can be configured to compare the first signal with a second signal indicating a second operating temperature of at least a second semiconductor device and produce a comparison signal indicating whether the indicated first operating temperature is higher, lower or equal to the indicated second operating temperature. The apparatus can also include an adjustment circuit configured to adjust operation of the first semiconductor device based on the comparison signal.

Stack package

A stack package includes a substrate, a stack of semiconductor chips mounted to the substrate, a side semiconductor chip disposed on one side of the stack, and adhesive interposed between the lower surface of the side semiconductor chip and the stack of semiconductor chips and which attaches the side semiconductor chip to the stack.

Low Inductance Flex Bond with Low Thermal Resistance

A electronic circuit with low inductance connections is disclosed. The electronic circuit includes a ground plane and a flex circuit. The flex circuit having a first surface generally facing the ground plane and a second surface opposite to the first surface. The flex circuit also having a flexible bridge defined thereof. The electronic circuit further includes a first electronic device communicatively coupled to the second surface of the flex circuit, a second electronic device communicatively coupled to the second surface of the flex circuit, and at least one conductive trace defined on the second surface of the flex circuit and extending along the flexible bridge. One end of the at least one conductive trace is configured for receiving an outbound current from the first electronic device and another end of the at least one conductive trace is communicatively coupled to the second electronic device through a vertical interconnect access.

Electronic device including a hemt

An electronic device can include a bidirectional HEMT. In an aspect, the electronic device can include a pair of switch gate and blocking gate electrodes, wherein the switch gate electrodes are not electrically connected to the blocking gate electrodes, and the first blocking, first switch, second blocking, and second switch gate electrodes are on the same die. In another aspect, the electronic device can include shielding structures having different numbers of laterally extending portions. In a further aspect, the electronic device can include a gate electrode and a shielding structure, wherein a portion of the shielding structure defines an opening overlying the gate electrode.

Capacitor component for an electric motor or generator

A capacitor component comprising a first busbar, a second busbar, one or more capacitor elements and a housing, the housing having a first portion and a second portion, wherein the first portion and the second portion are arranged to extend around an aperture, the first portion includes a section for housing the one or more capacitor elements, with the second portion extending between a first end and a second end of the first portion, wherein the first busbar and the second busbar are arranged to extend around the first portion and the second portion of the housing, a first power supply terminal is formed at the first end of the first portion and a second power supply terminal is formed at the second end of the first portion, wherein the first power supply terminal is coupled to the first busbar and the second power supply terminal is coupled to the second busbar, wherein a first conductive layer of the one or more capacitor elements is coupled to the first busbar and a second conductive layer of the one or more capacitor elements is coupled to the second busbar.

SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND POWER CONVERSION APPARATUS

A semiconductor module includes a substrate, a semiconductor element, and a wire. The semiconductor element is joined onto the substrate and has a surface electrode. Both ends of the wire are bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element. The wire is electrically connected to the surface electrode. 1: A semiconductor module comprising:a substrate;a semiconductor element joined onto the substrate and having a surface electrode;a wire, both ends of the wire being bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element;a conductor joined onto the surface electrode; anda joining member arranged on the conductor and having electrical conductivity,the wire being electrically connected to the surface electrode by the conductor and the joining member, the wire being separated from the conductor and embedded in the joining member.2: The semiconductor module according to claim 1 , whereinthe substrate includes an insulating layer and a conductor pattern provided on the insulating layer,the conductor pattern includes a first conductor portion and a second conductor portion,the semiconductor element is arranged between the first conductor portion and the second conductor portion, anda first end of the both ends of the wire is bonded to the first conductor portion, and a second end of the both ends of the wire is bonded to the second conductor portion.3. (canceled)4: A semiconductor module comprising:a substrate;a semiconductor element joined onto the substrate and having a surface electrode;a wire, both ends of the wire being bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element, the wire being electrically connected to the surface electrode;a conductor joined onto the surface electrode; anda joining member arranged on the conductor and having electrical conductivity,the wire being joined by the conductor and the ...

Power Converter Package Using Driver IC

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control FETs and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively.

Semiconductor device with an isolation structure coupled to a cover of the semiconductor device

A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.

Display device and light-emitting array module thereof

A light-emitting array module includes a circuit substrate, a light-emitting unit, and an encapsulation body. The light-emitting unit includes a plurality of light-emitting groups arranged in matrix on the circuit substrate. The encapsulation body disposed on the circuit substrate for encapsulating the light-emitting groups. The encapsulation body includes a plurality of encapsulation portions and a plurality of thin connection portions. Therefore, light beams generated by the light-emitting group is transformed into an obvious single point light source without halation due to the design of “each thin connection portion connected between the two adjacent encapsulation portions to separate the two adjacent encapsulation portions from each other by a predetermined distance”, so that the color resolution of the light-emitting array module is increased. In addition, the present disclosure further provides a display device including the light-emitting array module.

Ceramic substrate and method for producing a ceramic substrate

The present invention relates to a ceramic substrate ( 100 ) comprising: a front side ( 100 - 1 ), which comprises: i) a power semiconductor ( 102 - 1, . . . , 102 -n); and ii) a first metallic layer ( 104 ) comprising at least one first metallic plane contact ( 104 - 1, . . . , 104 -n), which is configured to connect the power semiconductor ( 102 - 1, . . . , 102 -n) to a first terminal ( 105 - 1, . . . , 105 -n) on an edge ( 100 - 3 ) of the ceramic substrate ( 100 ); a back side ( 100 - 2 ), which comprises: i) a capacitor ( 103 ) which is attached to a ii) second metallic layer ( 108 ) comprising at least one second metallic plane contact ( 108 - 1, . . . , 108 -n), which is configured to connect the capacitor ( 103 ) to a second terminal ( 107 - 1, . . . , 107 -n) on the edge ( 100 - 3 ) of the ceramic substrate ( 100 ); and a metallic frame ( 110 ), which is configured to connect the first metallic layer ( 104 ) to the second metallic layer ( 108 ).

METHOD OF FORMING PACKAGE STRUCTURE

A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer. 1. A package structure comprising:a first semiconductor package comprising a dielectric structure, a semiconductor device on the dielectric structure and an under bump metallization (UBM) structure in the dielectric structure, the UBM structure comprising a seed layer and a conductive feature thicker than the seed layer, wherein the seed layer is on a bottom surface of the conductive feature facing away from the semiconductor device;a conductive bump below the UBM structure;a second semiconductor package over the first semiconductor package;an electrical connector electrically connecting the second semiconductor package to the first semiconductor package; andan epoxy material encapsulating the electrical connector.2. The package structure of claim 1 , wherein the seed layer is absent between the conductive feature of the UBM structure and the conductive bump.3. The package structure of claim 1 , wherein the first semiconductor package further comprises a redistribution line claim 1 , the redistribution line has a linear portion extending in parallel with a bottom surface of the dielectric structure claim 1 , and a protruding portion protruding from the linear portion to the UBM structure claim 1 , wherein the protruding portion has a width decreasing in a first direction claim 1 , and the UBM structure has a width decreasing in a second direction opposite the first direction.4. The package structure of claim 1 , wherein the first semiconductor package further comprises a redistribution line over the UBM structure claim 1 , the redistribution line comprises a seed layer ...

Semiconductor device and power converter

A semiconductor device improved in deterioration detection accuracy by using an inductance of a bonding wire. The semiconductor device includes a first conductor pattern formed on the insulating substrate, the main current of the semiconductor die device flowing through the first conductor pattern; a second conductor pattern formed on the insulating substrate for sensing the potential of the surface electrode of the semiconductor die device; a first bonding wire for connecting the surface electrode and the first conductor pattern; and a second bonding wire. Further, there is a voltage sensing unit which is connected to the first conductor pattern and the second conductor pattern to sense a potential difference between the first conductor pattern and the second conductor pattern at the time of switching of the semiconductor die device; and a deterioration detection unit for detecting deterioration of the first bonding wire by using the sensed potential difference.