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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 3881. Отображено 100.
12-01-2012 дата публикации

Method for molecular adhesion bonding with compensation for radial misalignment

Номер: US20120006463A1
Автор: Gweltaz Gaudin
Принадлежит: Soitec SA

A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.

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Номер записи: 1
01-03-2012 дата публикации

Bumpless build-up layer package with pre-stacked microelectronic devices

Номер: US20120049382A1
Автор: Pramod Malatkar
Принадлежит: Intel Corp

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

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Номер записи: 2
28-06-2012 дата публикации

Trap Rich Layer for Semiconductor Devices

Номер: US20120161310A1
Автор: Chris BRINDLE, Michael A. Stuber, Stuart B. Molin
Принадлежит: IO Semiconductor Inc

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

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Номер записи: 3
03-10-2013 дата публикации

Bonded processed semiconductor structures and carriers

Номер: US20130256907A1
Автор: Ionut Radu, Mariam Sadaka
Принадлежит: Soitec SA

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

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Номер записи: 4
06-03-2014 дата публикации

Prevention of thru-substrate via pistoning using highly doped copper alloy seed layer

Номер: US20140061915A1
Автор: Andrew H. Simon, Christopher N. Collins, Daniel C. Edelstein, Mukta G. Farooq, Richard P. Volant, Troy L. Graves-Abe
Принадлежит: International Business Machines Corp

A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device.

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Номер записи: 5
04-01-2018 дата публикации

Bumped land grid array

Номер: US20180005971A1
Автор: Ah Ron Lee, Deog Soon Choi, Hyon Mo Ku
Принадлежит: Avago Technologies General IP Singapore Pte Ltd

A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of solderable surfaces formed on the first face of the substrate, a first solderable surface in the plurality of solderable surfaces having a pattern plating structure on an outward facing surface of the first solderable surface. There may also be an amount of solder bonded to the outward facing surface of the first solderable surface, where the pattern plating structure on the outward facing surface of the first solderable surface causes the amount of solder to have a first thickness at its ends, a second thickness at its center, and a discrete transition between the first thickness and the second thickness.

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Номер записи: 6
07-01-2021 дата публикации

Semiconductor Device and Method of Manufacturing

Номер: US20210005561A1
Автор: Chen Ming-Fa, Hu Chih-Chia, Jan Sen-Bor, Yeh Sung-Feng, Yuan Ching-Pin
Принадлежит:

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads. 1. A semiconductor device , comprising: a first passivation layer disposed over a first substrate; and', 'first bond pads disposed in the first passivation layer; and, 'a first die, comprising a second passivation layer, the second passivation layer being bonded to the first passivation layer; and', 'second bond pads disposed in the second passivation layer, each of the second bond pads being bonded to one of the first bond pads, the second bond pads comprising inner bond pads and outer bond pads, the outer bond pads having a greater diameter than the inner bond pads., 'a second die, comprising2. The semiconductor device of further comprising third bond pads disposed in the second passivation layer claim 1 , wherein the third bond pads are closer than the outer bond pads to an outer edge of the second passivation layer claim 1 , and wherein the third bond pads have a greater diameter than the outer bond pads.3. The semiconductor device of claim 1 , wherein:a center of one of the first bond pads is located a first distance from a center of the first passivation layer, the one of the first bond pads having a first diameter;a center of one of the second bond pads is located a second distance from a center of the second passivation layer, the one of the second bond pads being bonded to the one of the first bond pads, the one of the second bond pads having a second diameter; andthe second distance being ...

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Номер записи: 7
02-01-2020 дата публикации

Semiconductor Device Package and Method

Номер: US20200006164A1
Автор: Chen-Hua Yu, Ching-Pin Yuan, Hsien-Wei Chen, Hui-Wen Liu, Ming-Fa Chen, Sung-Feng Yeh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

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Номер записи: 8
03-01-2019 дата публикации

3D SEMICONDUCTOR DEVICE AND STRUCTURE

Номер: US20190006222A1
Автор: Cronquist Brian, OR-BACH Zvi, Sekar Deepak C., Wurman Zeev
Принадлежит: MonolithIC 3D Inc.

A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written. 1. A 3D semiconductor device , the device comprising: 'wherein connections between said first transistors and first metal layer comprise said first contact plugs;', 'a first level comprising a single crystal layer, a plurality of first transistors, a plurality of first contact plugs and a first metal layer,'}memory control circuits comprising a portion of said connections and said plurality of first transistors;a second level overlaying said single crystal layer, said second level comprising a plurality of second transistors;a third level overlaying said second level, said third level comprising a plurality of third transistors;a second metal layer overlaying said third level; and wherein said second transistors are aligned to said first transistors with less than 40 nm alignment error,', 'wherein said third metal layer comprises bit lines,', 'wherein said second level comprises a plurality of first memory cells,', 'wherein said third level comprises a plurality of second memory cells,', 'wherein one of said second transistors is at least partially self-aligned to at least one of said third ...

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Номер записи: 9
02-01-2020 дата публикации

Methods and devices for fabricating and assembling printable semiconductor elements

Номер: US20200006540A1
Автор: Dahl-Young Khang, Etienne Menard, John A. Rogers, Keon Jae Lee, Matthew Meitl, Ralph G. Nuzzo, Yugang Sun, Zhengtao Zhu
Принадлежит: University of Illinois

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

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Номер записи: 10
11-01-2018 дата публикации

PRE-PLATED SUBSTRATE FOR DIE ATTACHMENT

Номер: US20180012855A1
Автор: ABDO DAVID F., Sathiapalan Sivanesan A/L
Принадлежит:

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die. 19-. (canceled)10. A method of preparing a substrate for attachment to a semiconductor die , the method comprising:providing a substrate;selectively forming an attachment layer on a surface of the substrate at one or more die attachment locations, the attachment layer having a reflow temperature; andcovering the attachment layer with a protective flash plating layer, the protective flash plating layer having a reflow temperature that is less than or equal to the reflow temperature of the attachment layer.11. The method of claim 10 , wherein the formation of the attachment layer includes selectively plating one or more attachment stacks to the surface of the substrate at the one or more die attachment locations.12. The method of claim 10 , wherein the formation of the attachment layer includes selectively stamping one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations.13. The method of claim 10 , wherein the formation of the attachment layer includes spot welding one or more attachment preforms at diagonal corners of each of the one or more die attachment locations.14. The method of claim 10 , wherein the formation of the attachment layer includes hot rolling one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations.15. The method of claim 10 , wherein the protective flash ...

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Номер записи: 11
14-01-2021 дата публикации

3D Integrated Circuit and Methods of Forming the Same

Номер: US20210013098A1
Автор: Chao Lan-Lin, Chen Xiaomeng, Chu Yen-Chang, Hsiao Cheng-Tai, Kuang Hsun-Chung, Liu Ping-Yin, Tsai Chia-Shiung, Tu Yeur-Luen
Принадлежит:

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A semiconductor device comprising:a first contact extending away from a planar surface of a substrate, the first contact having straight sidewalls;a first dielectric layer surrounding a first portion of the first contact, the first dielectric layer being separated from the planar surface;a second dielectric layer surrounding a second portion of the first contact, wherein the second dielectric layer has a larger porosity than the first dielectric layer and wherein the first dielectric layer is located between the second dielectric layer and the substrate; anda dielectric barrier layer surrounding a third portion of the first contact, the dielectric barrier layer sharing a planar surface with the first contact.2. The semiconductor device of claim 1 , wherein the straight sidewalls are perpendicular to a major surface of the substrate.3. The semiconductor device of claim 1 , wherein the straight sidewalls are tilted with respect to a major surface of the substrate.4. The semiconductor device of claim 1 , wherein the first dielectric layer has a porosity of less than about 5%.5. The semiconductor device of claim 4 , wherein the first dielectric layer comprises un-doped silicate glass (USG).6. The semiconductor device of claim 1 , wherein the second dielectric layer ...

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Номер записи: 12
14-01-2021 дата публикации

METHOD OF TRANSFERRING MICRO DEVICE

Номер: US20210013172A1
Автор: CHEN Li-Yi
Принадлежит:

A method of transferring a micro device is provided. The method includes: aligning a transfer plate with the micro device thereon with a receiving substrate having a contact pad thereon such that the micro device is above or in contact with the contact pad; moving a combination of the transfer plate with the micro device thereon and the receiving substrate into a confined space with a relative humidity greater than or equal to about 85% so as to condense some water between the micro device and the contact pad; and attaching the micro device to the contact pad. 1. A method of transferring a micro device , comprising:aligning a transfer plate with the micro device thereon with a receiving substrate having a contact pad thereon such that the micro device is above or in contact with the contact pad;moving a combination of the transfer plate with the micro device thereon and the receiving substrate into a confined space with a relative humidity greater than or equal to about 85% so as to condense some water between the micro device and the contact pad; andattaching the micro device to the contact pad.2. The method of claim 1 , wherein attaching the micro device to the contact pad comprises:moving the combination out of the confined space to an environment with a relative humidity smaller than about 80% such that the water is evaporated and the micro device is stuck to and in contact with the contact pad.3. The method of claim 2 , wherein attaching the micro device to the contact pad further comprises:applying an external pressure to press the micro device and the contact pad during evaporating the water.4. The method of claim 1 , wherein attaching the micro device to the contact pad comprises:increasing a temperature within the confined space such that the water is evaporated and the micro device is stuck to and in contact with the contact pad.5. The method of claim 4 , wherein the temperature within the confined space is increased to a temperature point such that the ...

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Номер записи: 13
14-01-2021 дата публикации

STRUCTURE AND METHOD FOR FORMING CAPACITORS FOR A THREE-DIMENSIONAL NAND

Номер: US20210013303A1
Автор: Chen Liang, CHEN Shunfu, GAN Cheng, Liu Wei
Принадлежит: Yangtze Memory Technologies Co., Ltd.

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches. 1. A method for forming a three-dimensional capacitor for a memory device , comprising:forming, on a first side of a first substrate, a peripheral circuitry comprising a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode, wherein the first capacitor electrode is electrically connected with the deep well;forming, on a second substrate, a memory array comprising a plurality of memory cells and a second interconnect layer;bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array, such that at least one peripheral device of the peripheral circuitry is electrically connected with at least one memory cell of the memory array;forming, on a second side of the first substrate, one or more trenches inside the deep well, wherein the first and second sides are opposite sides of the first substrate;disposing a capacitor dielectric layer on sidewalls of the one or more trenches; andforming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.2. The ...

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Номер записи: 14
03-02-2022 дата публикации

Semiconductor device with recessed pad layer and method for fabricating the same

Номер: US20220037287A1
Автор: Shing-Yih Shih
Принадлежит: Nanya Technology Corp

The present application discloses a semiconductor device with a recessed pad layer and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a second die positioned on the first die, a pad layer positioned in the first die, a filler layer including an upper portion and a recessed portion, and a barrier layer positioned between the second die and the upper portion of the filler layer, between the first die and the upper portion of the filler layer, and between the pad layer and the recessed portion of the filler layer. The upper portion of the filler layer is positioned along the second die and the first die, and the recessed portion of the filler layer is extending from the upper portion and positioned in the pad layer.

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Номер записи: 15
18-01-2018 дата публикации

METAL-METAL DIRECT BONDING METHOD

Номер: US20180019124A1
Автор: GONDCHARTON Paul, Imbert Bruno, Moriceau Hubert
Принадлежит:

A method for assembling a first substrate and a second substrate by metal-metal direct bonding, includes providing a first layer of a metal at the surface of the first substrate and a second layer of the metal at the surface of the second substrate, the first and second metal layers having a tensile stress (σ) between 30% and 100% of the tensile yield strength (σ) of the metal; assembling the first and second substrates at a bonding interface by directly contacting the first and second tensile stressed metal layers; and subjecting the assembly of the first and second substrates to a stabilization annealing at a temperature lower than or equal to a temperature threshold beyond which the first and second tensile stressed metal layers are plastically compressively deformed. 1. A method for assembling a first substrate and a second substrate by a metal-metal direct bonding , comprising:providing a first layer of a metal at a surface of the first substrate and a second layer of said metal at a surface of the second substrate, the first and second metal layers having a tensile stress comprised between 30% and 100% of the tensile yield strength of said metal;assembling the first and second substrates at a bonding interface by directly contacting the first and second metal layers;subjecting the assembly of the first and second substrates to a stabilization annealing at a temperature lower than or equal to a temperature threshold beyond which the first and second tensile stressed metal layers are plastically compressively deformed.2. The method according to claim 1 , comprising calculating said temperature threshold from the tensile stress of the first and second metal layers and the thermo-elastic coefficient of said metal.3. The method according to claim 1 , wherein the providing comprises depositing the first metal layer onto a face of the first substrate and the second metal layer onto a face of the second substrate.4. The method according to claim 3 , wherein the ...

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Номер записи: 16
18-01-2018 дата публикации

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

Номер: US20180019279A1
Автор: Horiike Machiko, Itonaga Kazuichiroh
Принадлежит:

A semiconductor device, which is configured as a backside illuminated solid-state imaging device, includes a stacked semiconductor chip which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit; a semiconductor-removed region in which a semiconductor section of a part of the first semiconductor chip unit is completely removed; and a plurality of connection wirings which is formed in the semiconductor-removed region and connects the first and second semiconductor chip units to each other. 119-. (canceled)20. A semiconductor device , comprising:a first substrate including a pixel array and first connection pads;a second substrate bonded to the first substrate, the second substrate including second connection pads and a logic circuit for driving the pixel array, wherein the first connection pads are located at a different level in the semiconductor device than the second connection pads; andconnection wirings that electrically connect the first connection pads to the second connection pads,wherein, in a plan view, pairs including one of the first connection pads and one of the second connection pads form a connection pad array, andwherein, in the plan view, at least one of the first connection pads partially overlaps at least one of the second connection pads.21. The semiconductor device of claim 20 , wherein claim 20 , in the plan view claim 20 , the first connection pads and the second connection pads have a same shape.22. The semiconductor device of claim 21 , wherein the same shape is an octagonal shape.23. The semiconductor device of claim 20 , wherein claim 20 , in the plan view claim 20 , each pair is a stage in which the first connection pad and the second connection pad are adjacent to one another in a horizontal direction claim 20 ...

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Номер записи: 17
17-01-2019 дата публикации

System on integrated chips and methods of forming the same

Номер: US20190019756A1
Автор: Chen-Hua Yu, Chuei-Tang Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device and methods of forming are provided. The method includes bonding a second die to a surface of a first die. The method includes encapsulating the second die in an isolation material, and forming a through via extending through the isolation material. The method also includes forming a first passive device in the isolation material.

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Номер записи: 18
26-01-2017 дата публикации

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

Номер: US20170025327A1
Автор: Liu Chun-Li, Padmanabhan Balaji, Salih Ali, Venkatraman Prasad
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support. 1. A semiconductor component having at least first and second terminals , comprising:a support having first and second device receiving portions, a first lead extending from the first device receiving portion and a second lead extending from the first die receiving portion, wherein the first and second leads are integral with the first device receiving portion;a third lead adjacent to and electrically isolated from the first and second device receiving portions; anda first semiconductor device having a first surface and a second surface, wherein a first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface and a third bond pad extends from a third portion of the first surface, the first semiconductor device mounted to the support in a flip chip configuration, wherein the first bond pad is coupled to the first device receiving portion, the second bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead, wherein the first semiconductor device is configured from a III-N semiconductor material.2. The semiconductor ...

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Номер записи: 19
10-02-2022 дата публикации

SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS OF THE SAME

Номер: US20220045035A1
Автор: PARK Hyun Mog
Принадлежит:

A semiconductor device includes a first substrate structure and a second substrate structure. The first substrate structure includes a base substrate, circuit elements disposed on the base substrate, a first substrate disposed on the circuit elements, first memory cells disposed on the first substrate and electrically connected to the circuit elements, first bit lines disposed on the first memory cells and connected to the first memory cells, and first bonding pads disposed on the first bit lines to be connected to the first bit lines, respectively. The second substrate structure is connected to the first substrate structure on the first substrate structure, and includes a second substrate, second memory cells disposed on the second substrate, second bit lines disposed on the second memory cells and connected to the second memory cells, and second bonding pads disposed on the second bit lines to be connected to the second bit lines, respectively. The first substrate structure and the second substrate structure are connected to each other by bonding the first bonding pads to the second bonding pads, and the first bonding pads and second bonding pads are vertically between the first bit lines and the second bit lines, without the first substrate or second substrate disposed vertically between the first bit lines and the second bit lines. 1. A method for manufacturing a semiconductor device , comprising:forming a first substrate structure by forming first gate electrodes stacked and spaced apart from each other in a direction perpendicular to a first surface of a first substrate, first channels extending perpendicular to the first substrate while passing through the first gate electrodes, first bit lines connected to the first channels, and first bonding pads disposed on the first bit lines to be electrically connected to the first bit lines, respectively, on the first substrate;forming a second substrate structure by forming second gate electrodes stacked and spaced ...

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Номер записи: 20
10-02-2022 дата публикации

Method for Manufacturing Display Device and Display Device Manufacturing Apparatus

Номер: US20220045039A1
Автор: Kusunoki Koji, Nonaka Taiki, TSUKAMOTO Yosuke, Yamazaki Shunpei, Yoshizumi Kensuke
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

To reduce the manufacturing cost of a display device using a micro LED as a display element. To manufacture a display device using a micro LED as a display element in a high yield. Employed is a method for manufacturing a display device, including: forming a plurality of transistors in a matrix over a substrate (), forming conductors () electrically connected to the transistors over the substrate (), and forming a plurality of light-emitting elements () in a matrix over a film (). Each of the light-emitting elements () includes electrodes () on one surface and the other surface is in contact with the film (). The conductors () and the electrodes () are opposed to each other. An extrusion mechanism () is pushed out from the film () side to the substrate () side so that the conductors () and the electrodes () are in contact with each other, whereby the conductors () and the electrodes () are electrically connected to each other. 1. A method for manufacturing a display device , comprising:forming a first plurality of transistors in a matrix over a substrate,forming a conductor electrically connected to the first plurality of transistors over the substrate after forming the first plurality of transistors;forming a first plurality of light-emitting elements comprising an electrode in a matrix over a first film;arranging the substrate and the first film so that the conductor and the electrode face each other:electrically connecting the conductor and the electrode by pushing out the one of the first plurality of light-emitting elements after arranging the substrate and the first film,wherein one of the first plurality of light-emitting elements includes the electrode on one surface and is in contact with the first film on the other surface.2. The method for manufacturing a display device claim 1 , according to claim 1 , further comprising:after electrically connecting the conductor and the electrode, applying an ultrasonic wave to the conductor and the electrode, whereby ...

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Номер записи: 21
24-01-2019 дата публикации

A 3d semiconductor device and system

Номер: US20190027409A1
Автор: Brian Cronquist, Deepak C. Sekar, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A 3D semiconductor device, the device including: a first crystalline silicon layer including a plurality of first transistors; a first metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of first logic gates; a first array of memory cells including second transistors; a second metal layer overlying the first and second transistors; a second crystalline silicon layer overlaying the second metal layer and the second crystalline silicon layer including a plurality of third transistors; a third metal layer interconnecting the third transistors, a portion of the third transistors forming a plurality of second logic gates; a second array of memory cells including fourth transistors and overlaying the second crystalline silicon layer; a fourth metal layer overlying the third and fourth transistors, where at least one of the fourth transistors is overlaying at least another one of the fourth transistors such that they are self-aligned, having been processed following the same lithography step, where the second array of memory cells include NAND flash type memory cells.

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Номер записи: 22
24-01-2019 дата публикации

SUBSTRATE BONDING APPARATUS AND SUBSTRATE BONDING METHOD

Номер: US20190027462A1
Автор: FUKUDA MINORU, Sugaya Isao
Принадлежит: NIKON CORPORATION

A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact in a state where a temperature difference is generated therebetween, to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate, wherein enlargement of the contact regions starts before positional misalignment between the first substrate and the second substrate exceeds a threshold, and the threshold is set such that positional misalignment after the first substrate and the second substrate are bonded does not exceed a tolerated value. 1. A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact in a state where a temperature difference is generated therebetween , to form contact regions at the parts , and then enlarges the contact regions to bond the first substrate and the second substrate , whereinenlargement of the contact regions starts before positional misalignment between the first substrate and the second substrate exceeds a threshold, andthe threshold is set such that positional misalignment after the first substrate and the second substrate are bonded does not exceed a tolerated value.2. The substrate bonding apparatus according to claim 1 , wherein enlargement of the contact regions starts before a temperature difference between non-contact regions of the respective surfaces of the first substrate and the second substrate that are yet to contact becomes a temperature difference out of a predetermined range.3. The substrate bonding apparatus according to claim 1 , wherein enlargement of the contact regions starts after the first substrate and the second substrate are coupled to each other at a predetermined coupling force in the contact regions formed at the parts.4. The substrate bonding apparatus according to claim 3 , comprising:a judging unit that judges ...

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Номер записи: 23
24-01-2019 дата публикации

System on Integrated Chips and Methods of Forming Same

Номер: US20190027465A1
Автор: Chen Ming-Fa, Yeh Sung-Feng, Yu Chen-Hua
Принадлежит:

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die. 1. A package comprising:a first semiconductor die;a second semiconductor die bonded to the first semiconductor die, wherein a first dielectric layer of the first semiconductor die is directly bonded to a second dielectric layer of the second semiconductor die;a third semiconductor die bonded to the first semiconductor die, wherein the first dielectric layer of the first semiconductor die is directly bonded to a third dielectrics layer of the third semiconductor die;a first isolation material disposed around the second semiconductor die and the third semiconductor die, wherein the second semiconductor die is physically separated from the third semiconductor die by the first isolation material; anda redistribution structure electrically connected to the first semiconductor die, the second semiconductor die, and the third semiconductor die.2. The package of claim 1 , wherein the redistribution structure is disposed on an opposing side of the first semiconductor die as the second semiconductor die and the third semiconductor die.3. The package of claim 1 , wherein the redistribution structure is electrically connected to the second semiconductor die by a conductive via extending through a second isolation material claim 1 , and wherein the first semiconductor die is physically separated from the conductive via by the second isolation material.4. The package of claim 3 , wherein the second ...

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Номер записи: 24
23-01-2020 дата публикации

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

Номер: US20200027868A1
Автор: Lin Jing-Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer. 1. A semiconductor device structure , comprising:a first polymer layer formed between a first substrate and a second substrate;a first conductive layer formed over the first polymer; anda first through substrate via (TSV) formed over the first conductive layer, wherein the conductive layer is in direct contact with the first TSV and the first polymer.2. The semiconductor device structure as claimed in claim 1 , further comprising:an interconnect structure formed over the first substrate, wherein the interconnect structure is in direct contact with the first TSV.3. The semiconductor device structure as claimed in claim 1 , further comprising:a first transistor formed in the first substrate; anda first contact plug formed below the first transistor, wherein a bottom surface of the first contact plug is level with a bottom surface of the first TSV.4. The semiconductor device structure as claimed in claim 3 , wherein a sidewall of the first contact plug is aligned with a sidewall of the first conductive layer.5. The semiconductor device structure as claimed in claim 1 , further comprising:a second TSV formed in the second substrate, wherein a first width of the first TSV is smaller than a second width of the second TSV.6. The semiconductor device structure as claimed in claim 5 , further comprising:a second polymer layer formed between the first substrate and the second substrate; anda second conductive layer formed below the second polymer layer, wherein the second conductive layer is in direct contact with the second polymer layer and the second TSV ...

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Номер записи: 25
28-01-2021 дата публикации

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

Номер: US20210028135A1
Автор: Raghuveer S. Makala, Ramy Nashed Bassely SAID, Senaka Kanakamedala
Принадлежит: SanDisk Technologies LLC

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

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Номер записи: 26
28-01-2021 дата публикации

BONDED ASSEMBLY CONTAINING OXIDATION BARRIERS AND/OR ADHESION ENHANCERS AND METHODS OF FORMING THE SAME

Номер: US20210028149A1
Автор: Alsmeier Johann, Makala Raghuveer S.
Принадлежит:

A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads, providing a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, and bonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads. 1. A method of forming a bonded assembly , comprising:providing a first semiconductor die comprising a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices;forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads;providing a second semiconductor die comprising a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices; andbonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads.2. The method of claim 1 , wherein:the first bonding pads are located within a first bonding dielectric layer;the second bonding pads are located within a second bonding dielectric layer; andthe oxidation barrier layer is selectively formed on physically exposed surfaces of the first bonding pads without forming the first oxidation barrier layer on physically exposed surfaces of the first bonding dielectric layer.3. The method of claim 2 , wherein:the first bonding dielectric layer and the second bonding dielectric ...

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Номер записи: 27
04-02-2016 дата публикации

TRAP RICH LAYER FOR SEMICONDUCTOR DEVICES

Номер: US20160035833A1
Автор: Brindle Christopher N., Molin Stuart B., Stuber Michael A.
Принадлежит:

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer. 130.-. (canceled)31. A method of fabricating an integrated circuit , comprising:forming a first active layer in a first semiconductor wafer, wherein the first active layer comprises a first active device layer and a first metallization layer;creating a trap rich layer in a second semiconductor wafer;bonding the second semiconductor wafer to the first semiconductor wafer to form a bonded structure;forming a second active layer in the second semiconductor wafer, wherein the second active layer comprises a second active device layer and a second metallization layer; andelectrically interconnecting the first and second metallization layers.32. The method of claim 31 , wherein the trap rich layer is between the first active device layer and the second active device layer in the bonded structure.33. The method of claim 31 , further comprising removing a portion of the second semiconductor wafer before the trap rich layer is created in the second semiconductor wafer.33. The method of claim 31 , wherein the forming of the second active layer is performed after the bonding.34. The method of claim 31 , wherein the forming of the second active layer is performed before the bonding.35. The method of claim 31 , wherein the forming comprises forming the first active device layer above an insulator layer in the first semiconductor wafer.36. The method of claim 31 , wherein the forming of the second active layer comprises forming the second active device layer above an insulator layer in the second semiconductor wafer.37. The method of claim 31 , further comprising providing a bonding layer on a bottom surface of the second ...

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Номер записи: 28
17-02-2022 дата публикации

Semiconductor Die Package and Method of Manufacture

Номер: US20220052009A1
Автор: Kuan-Yu Huang, Shang-Yun Hou, Shu Chia Hsu, Sung-Hui Huang, Wen-Yao Chang, Yu-Jen Cheng, Yu-Yun Huang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

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Номер записи: 29
17-02-2022 дата публикации

Hybrid bonded interconnect bridging

Номер: US20220052023A1
Автор: Brett P. Wilkerson, Lei Fu, Rahul Agarwal
Принадлежит: Advanced Micro Devices Inc

A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

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Номер записи: 30
17-02-2022 дата публикации

SEMICONDUCTOR ELEMENT

Номер: US20220052099A1
Автор: HAYASHI TOSHIKO, Ito Daisuke, Murata Kenichi
Принадлежит:

A first semiconductor element according to one embodiment of the present disclosure includes: an element substrate including an element region in which a wiring layer and a first semiconductor layer including a compound semiconductor material are provided as a stack, and a peripheral region outside the element region; a readout circuit substrate opposed to the first semiconductor layer with the wiring layer interposed therebetween, and electrically coupled to the first semiconductor layer with the wiring layer interposed therebetween; a first electrode provided in the wiring layer and electrically coupled to the first semiconductor layer; a second electrode opposed to the first electrode with the first semiconductor layer interposed therebetween; and an insulating layer provided on the second electrode and having a non-reducing property. 1. A semiconductor element comprising:an element substrate including an element region in which a wiring layer and a first semiconductor layer including a compound semiconductor material are provided as a stack, and a peripheral region outside the element region;a readout circuit substrate opposed to the first semiconductor layer with the wiring layer interposed therebetween, and electrically coupled to the first semiconductor layer with the wiring layer interposed therebetween;a first electrode provided in the wiring layer and electrically coupled to the first semiconductor layer;a second electrode opposed to the first electrode with the first semiconductor layer interposed therebetween; andan insulating layer provided on the second electrode and having a non-reducing property.2. The semiconductor element according to claim 1 , wherein the insulating layer includes any one of an oxide (MO) claim 1 , a nitride (MN) claim 1 , and an oxynitride (MON)(M is any one of silicon (Si), titanium (Ti), hafnium (Hf), zirconium (Zr), and yttrium (Y); x, y, and z are integers of 1 or greater).3. The semiconductor element according to claim 1 , ...

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Номер записи: 31
31-01-2019 дата публикации

3D Integrated Circuit and Methods of Forming the Same

Номер: US20190035681A1
Автор: Chao Lan-Lin, Chen Xiaomeng, Chu Yen-Chang, Hsiao Cheng-Tai, Kuang Hsun-Chung, Liu Ping-Yin, Tsai Chia-Shiung, Tu Yeur-Luen
Принадлежит:

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A method of manufacturing a semiconductor device , the method comprising:pre-bonding a first dielectric barrier layer and a second dielectric barrier layer at room temperature for a time of less than about one minute, wherein the first dielectric barrier layer is adjacent to a first high porosity dielectric layer and the second dielectric barrier layer is adjacent to a second high porosity dielectric layer, wherein the first high porosity dielectric layer is adjacent to a first low porosity dielectric layer and the second high porosity dielectric layer is adjacent to a second low porosity dielectric layer, and wherein a first contact extends through the first low porosity dielectric layer, the first high porosity dielectric layer, and the first dielectric barrier layer to make contact with a second contact, the second contact extending through the second dielectric barrier layer, the second high porosity dielectric layer, and the second low porosity dielectric layer; andannealing the first dielectric barrier layer and the second dielectric barrier layer at a temperature of between about 300° C. and about 400° C.2. The method of claim 1 , further comprising curing the first dielectric barrier layer and the second dielectric barrier layer.3. The method of claim 1 ...

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Номер записи: 32
30-01-2020 дата публикации

SEMICONDUCTOR DEVICE PRODUCTION METHOD

Номер: US20200035636A1
Автор: GAWASE Akifumi, Kawasaki Takahiro, MATSUI Yukiteru
Принадлежит: Toshiba Memory Corporation

A semiconductor device production method includes forming a first recess portion in a first insulating film formed on a first substrate and a first conductive layer on the front surface of the first insulating film located inside and outside the first recess portion. In the first recess portion, a first pad is formed having a width of 3 μm or less and including the first conductive layer by performing a first polishing the first conductive layer at a first polishing rate and, after the first polishing, a second polishing the first conductive layer at a second polishing rate lower than the first polishing rate. The first pad of the first substrate and a second pad of a second substrate are joined together by annealing the first substrate and the second substrate. The selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4. 1. A semiconductor device production method comprising:forming a first recess portion in a first insulating film formed on a first substrate;forming a first conductive layer on a front surface of the first insulating film located both inside and outside the first recess portion;forming, in the first recess portion, a first pad having a width of 3 μm or less and including the first conductive layer by performing a first process of polishing the first conductive layer at a first polishing rate and, after the first process, a second process of polishing the first conductive layer at a second polishing rate which is lower than the first polishing rate, wherein the second process is performed such that a selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4; andjoining the first pad of the first substrate and a second pad of a second substrate together by annealing the first substrate and the second substrate.2. The semiconductor device production method according to claim 1 , wherein the first conductive layer contains copper.3. The semiconductor device production method according to ...

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Номер записи: 33
30-01-2020 дата публикации

POST CMP PROCESSING FOR HYBRID BONDING

Номер: US20200035641A1
Автор: FOUNTAIN, Gao Guilian, JR. Gaius Gillman, MANDALAPU Chandrasekhar
Принадлежит:

Devices and techniques include process steps for forming openings through stacked and bonded structures. The openings are formed by pre-etching through one or more layers of prepared dies after planarization of the bonding layer (by chemical-mechanical polishing (CMP) or the like) and prior to bonding. For instance, the openings are etched through one or more layers of dies to be bonded prior to bonding the dies to form an assembly. 1. A microelectronic assembly , comprising:a first substrate having a bonding surface, the bonding surface of the first substrate having a planarized topography;a first plurality of electrically conductive features at the bonding surface of the first substrate;a second substrate having a bonding surface, the bonding surface of the second substrate having a planarized topography and bonded to the bonding surface of the first substrate;a second plurality of electrically conductive features at the bonding surface of the second substrate and bonded to the first plurality of electrically conductive features; andone or more electrically conductive contact pads disposed within an insulating layer of the second substrate and below the bonding surface of the second substrate, the one or more electrically conductive contact pads disposed in an area different from the first plurality of electrically conductive features and the second plurality of electrically conductive features.2. The microelectronic assembly of claim 1 , further comprising one or more secondary openings in the insulating layer of the second substrate aligned to the one or more electrically conductive contact pads claim 1 , the one or more secondary openings extending from the bonding surface of the second substrate to the one or more electrically conductive contact pads claim 1 , providing access to the one or more electrically conductive contact pads.3. The microelectronic assembly of claim 2 , further comprising one or more primary openings in an insulating layer of the first ...

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Номер записи: 34
30-01-2020 дата публикации

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, AND SOLID-STATE IMAGING DEVICE

Номер: US20200035643A1
Автор: Hiramatsu Katsunori, HIRATA AKIKO, KIMURA TADAYUKI, Miyoshi Yasufumi
Принадлежит:

The present technology relates to a semiconductor device, a manufacturing method, and a solid-state imaging device which are capable of suppressing a decrease in bonding strength and preventing a poor electrical connection or peeling when two substrates are bonded to each other. Provided is a semiconductor device, including: a first substrate including a first electrode including a metal; and a second substrate bonded to the first substrate and including a second electrode including a metal. An acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed. The present technology can be, for example, applied to a solid-state imaging device such as a CMOS image sensor. 1. A semiconductor device , comprising:a first substrate including a first electrode including a metal; anda second substrate bonded to the first substrate and including a second electrode including a metal,wherein an acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed.2. The semiconductor device according to claim 1 , wherein side roughness is formed in a part of the side surface of the groove claim 1 , anda metal seed corresponding to a shape of the groove, part of which has the side roughness, is formed between the groove and the metal.3. The semiconductor device according to claim 1 , wherein a part of the side surface of the groove has an acute-angled concavo-convex shape claim 1 , anda metal seed corresponding to the shape of the groove is formed between the groove and the metal.4. A semiconductor device manufacturing method claim 1 , comprising:forming side roughness in a part of a side surface of a groove in which an electrode including a metal is formed;forming a metal ...

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Номер записи: 35
30-01-2020 дата публикации

THROUGH SILICON VIA DESIGN FOR STACKING INTEGRATED CIRCUITS

Номер: US20200035672A1
Автор: Chen Yi-Sheng, Fan Fu-Jier, Kalnitsky Alexander, LIN Hsing-Chih, Liu Jen-Cheng, Thei Kong-Beng, TUAN Hsiao-Chin, Yaung Dun-Nian
Принадлежит:

A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias. 1. A method for manufacturing a three-dimensional (3D) integrated circuit (IC) , comprising:providing a first IC die comprising a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, a first bonding structure over the first interconnect structure, and a first plurality of TSV wiring layers and inter-wire vias;providing a second IC die comprising a second semiconductor substrate, a second bonding structure, a second interconnect structure between the second semiconductor substrate and the second bonding structure, and a second plurality of TSV wiring layers and inter-wire vias;bonding the second IC die to the first IC die through the second bonding structure and the first bonding structure at a bonding interface, the bonding enclosing a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies, wherein the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate; andwherein the bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by ...

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Номер записи: 36
04-02-2021 дата публикации

BONDED THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MAKING THE SAME BY REPLACING CARRIER SUBSTRATE WITH SOURCE LAYER

Номер: US20210035965A1
Автор: Higashitani Masaaki, Kai James, MIZUTANI Yuki
Принадлежит:

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer. 1. A semiconductor structure comprising a memory die bonded to a logic die , the memory die comprising:an alternating stack of insulating layers and electrically conductive layers;memory openings extending through the alternating stack;memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film;a source layer having a front side electrically connected to first end portions of the vertical semiconductor channels that are distal from an interface between the logic die and the memory die;an electrically conductive layer connected to a back side of the source layer; andbackside bonding pads electrically connected to the electrically conductive layer.2. The semiconductor structure of claim 1 , wherein electrically conductive layer comprises a source power supply network.3. The semiconductor structure of claim 2 , wherein the source power supply network comprises backside metal interconnect structures embedded in a backside isolation dielectric layer and contacting the source layer at multiple locations.4. The semiconductor structure of claim 3 , wherein the source power supply network comprises:a network of metal lines; ...

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Номер записи: 37
04-02-2021 дата публикации

THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF

Номер: US20210036006A1
Автор: Chen Liang, Huang Shi Qi, Liu Wei, Xue Lei
Принадлежит: Yangtze Memory Technologies Co., Ltd.

A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming an array wafer comprises forming an alternating dielectric etch stop structure on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure. The method further comprises forming a CMOS wafer and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact. 1. A method for forming a three-dimensional (3D) memory device , comprising: forming an alternating dielectric etch stop structure on a first substrate in the periphery region,', 'forming an array device on the first substrate in the staircase and array region, and', 'forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure;, 'forming an array wafer including a periphery region and a staircase and array region, comprisingforming a CMOS wafer;bonding the array wafer and the CMOS wafer; andforming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact.2. The method of claim 1 , wherein forming the array wafer further comprises:forming an array well structure in the first substrate in the periphery region; andforming at least one second vertical through contact in contact with the array well structure.3. The method of claim 2 , wherein forming the array wafer further comprises:forming ...

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Номер записи: 38
04-02-2021 дата публикации

SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210036007A1
Автор: CHOI Chang Woon, JUNG Soo Nam, Kim Jin Ho, OH Sung Lae, Park Sang Woo, SUNG Sang Hyun
Принадлежит:

A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction. 1. A semiconductor memory device comprising:an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction;a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; anda plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively,wherein the plurality of opening holes are distributed in a plurality of rows arranged in a second direction.2. The semiconductor memory device according to claim 1 ,wherein opening holes disposed in the same coupling area and in the same row comprise a hole group, andwherein the opening holes in the hole group are disposed in the first direction.3. The semiconductor memory device according to claim 2 ,wherein the plurality of contact holes disposed under the plurality of opening holes of the same hole group are sequentially deepened by a first depth, andwherein the first depth is the same as a vertical pitch of the plurality of electrode layers.4. The semiconductor ...

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Номер записи: 39
08-02-2018 дата публикации

Interposer device including at least one transistor and at least one through-substrate via

Номер: US20180040547A1
Автор: Changhan Hobie Yun, Chengjie Zuo, David Francis Berdy, Jonghae Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Shiqun Gu
Принадлежит: Qualcomm Inc

In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure.

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Номер записи: 40
18-02-2021 дата публикации

Support structure for mems device with particle filter

Номер: US20210047176A1
Автор: Chia-Hua Chu, Chun-Wen Cheng, Wen Cheng Kuo
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Various embodiments of the present disclosure are directed towards a microphone including a support structure layer disposed between a particle filter and a microelectromechanical systems (MEMS) structure. A carrier substrate is disposed below the particle filter and has opposing sidewalls that define a carrier substrate opening. The MEMS structure overlies the carrier substrate and includes a diaphragm having opposing sidewalls that define a diaphragm opening overlying the carrier substrate opening. The particle filter is disposed between the carrier substrate and the MEMS structure. A plurality of filter openings extend through the particle filter. The support structure layer includes a support structure having one or more segments spaced laterally between the opposing sidewalls of the carrier substrate. The one or more segments of the support structure are spaced laterally between the plurality of filter openings.

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Номер записи: 41
24-02-2022 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING HYBRID BONDING INTERFACE

Номер: US20220059372A1
Автор: CHIU Hsih-Yang
Принадлежит:

The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases. 1. A method of manufacturing a semiconductor device , comprising:forming a dielectric layer on a substrate;etching the dielectric layer to create a plurality of openings in the dielectric layer;applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer;forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed;removing the sacrificial layer to form at least one air gap in the dielectric layer; andforming a plurality of protrusions on the bases.2. The method of claim 1 , wherein in a pair of openings claim 1 , only a portion of the dielectric layer is covered by the sacrificial layer.3. The method of claim 1 , wherein the first conductive feature and the bases are arranged in an interleaved configuration.4. The method of claim 1 , wherein the first conductive feature and the bases are formed using a plating process.5. The method of claim 4 , wherein the first conductive feature claim 4 , the bases and the protrusions have the same material.6. The method of claim 1 , wherein the formation of the protrusions comprises:applying a patterned mask comprising a plurality of through holes on the dielectric layer, the ...

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Номер записи: 42
24-02-2022 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE WITH AIR GAP

Номер: US20220059468A1
Автор: Huang Tse-Yao
Принадлежит:

The present application provides a method for manufacturing a semiconductor package with air gaps for reducing capacitive coupling between conductive features. The method comprises: providing a first substrate with an integrated circuit; forming a first stack of insulating layers with first protruding portions on the integrated circuit; removing a topmost insulating layer in the first stack of insulating layers; forming through holes in the first stack to form a first semiconductor structure; providing a second substrate with an integrated circuit; forming a second stack of insulating layers with second protruding portions on the integrated circuit; forming a recess portion in the first stack to form a second semiconductor structure; and bonding the first semiconductor structure with the second semiconductor structure, with an air gap formed from the recess portion. 1. A method for manufacturing a semiconductor package , comprising:providing a first substrate with an integrated circuit;forming a first stack of insulating layers with first protruding portions on the integrated circuit;removing a topmost insulating layer in the first stack of insulating layersforming through holes in the first stack to form a first semiconductor structureproviding a second substrate with an integrated circuit; forming a second stack of insulating layers with second protruding portions on the integrated circuit;forming a recess portion in the first stack to form a second semiconductor structure; andbonding the first semiconductor structure with the second semiconductor structure, with an air gap formed from the recess portion.2. The method for manufacturing a semiconductor package according to claim 1 , wherein the second protruding portions are inserted into the through holes claim 1 , and the first protruding portions are inserted into the recess portion.3. The semiconductor package according to claim 1 , wherein forming a second stack of insulating layers with second protruding ...

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Номер записи: 43
07-02-2019 дата публикации

SUBSTRATE BONDING APPARATUS AND SUBSTRATE BONDING METHOD

Номер: US20190043826A1
Автор: FUKUDA MINORU, MITSUISHI Hajime, Sugaya Isao
Принадлежит: NIKON CORPORATION

A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate includes: a temperature adjusting unit that adjusts a temperature of at least one of the first substrate and the second substrate such that positional misalignment between the first substrate and the second substrate does not exceed a threshold at least in a course of enlargement of the contact regions. 1. A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact to form contact regions at the parts , and then enlarges the contact regions to bond the first substrate and the second substrate , the substrate bonding apparatus comprising:a temperature adjusting unit that adjusts a temperature of at least one of the first substrate and the second substrate such that positional misalignment between the first substrate and the second substrate does not exceed a threshold at least in a course of enlargement of the contact regions.2. The substrate bonding apparatus according to claim 1 , wherein the temperature adjusting unit adjusts a temperature of at least one of non-contact regions of the first substrate and the second substrate such that positional misalignment which is equal to or larger than the threshold does not occur between the non-contact regions claim 1 , the non-contact regions being regions in which the surface of the first substrate and the surface of the second substrate are not in contact yet.3. The substrate bonding apparatus according to claim 2 , wherein the temperature adjusting unit keeps a temperature difference between the non-contact regions within a predetermined range until the non-contact regions come into contact.4. The substrate bonding apparatus according to claim 1 , wherein the temperature ...

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Номер записи: 44
18-02-2021 дата публикации

BONDING SYSTEM AND BONDING METHOD

Номер: US20210050243A1
Автор: Otsuka Yoshitaka
Принадлежит:

A bonding system includes a first holder and a second holder arranged to be spaced apart from each other in a vertical direction; a position adjuster configured to move the first holder and the second holder relatively to perform a position adjustment in a horizontal direction between a first substrate held by the first holder and a second substrate held by the second holder; a pressing unit configured to press the first substrate and the second substrate against each other; a measuring unit configured to measure a position deviation between an alignment mark on the first substrate and an alignment mark on the second substrate, the first substrate and the second substrate being bonded by the pressing unit; and a position adjustment controller configured to control the position adjustment in the horizontal direction in a currently-performed bonding processing based on the position deviation generated in a previously-performed bonding processing. 1. A bonding system , comprising:a first holder and a second holder arranged to be spaced apart from each other in a vertical direction, the first holder having, on a surface thereof facing the second holder, an attraction surface configured to attract and hold a first substrate, and the second holder having, on a surface thereof facing the first holder, an attraction surface configured to attract and hold a second substrate;a position adjuster configured to move the first holder and the second holder relatively to perform a position adjustment in a horizontal direction between the first substrate held by the first holder and the second substrate held by the second holder;a pressing unit configured to press the first substrate held by the first holder and the second substrate held by the second holder against each other;a measuring unit configured to measure a position deviation between an alignment mark formed on the first substrate and an alignment mark formed on the second substrate, the first substrate and the second ...

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Номер записи: 45
16-02-2017 дата публикации

Apparatus And Method For Verification Of Bonding Alignment

Номер: US20170047260A1
Автор: Chao Lan-Lin, Huang Xin-Hua, Liu Ping-Yin
Принадлежит:

Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node. 1. A device comprising:a common node disposed in a first wafer;a test node disposed in the first wafer and having a plurality of test pads exposed at a first surface of the first wafer, the test node further having a plurality of test node lines separated by a first spacing and exposed at a second surface of the first wafer and each connected to a respective one of the plurality of test pads; anda comb disposed in a second wafer and having a plurality of comb lines having a second spacing different from the first spacing, each of the comb lines having a first surface exposed at a first side of the second wafer.2. The device of claim 1 , wherein the common node includes a common node pad exposed at the first surface of the first wafer and further includes a plurality of common node lines exposed at the second surface of the first wafer claim 1 , the common node lines being separated by the first spacing.3. The device of claim 1 , wherein respective test node lines of the plurality of test node lines comprises substantially straight conductive line segments extending from the first surface of the first wafer to the second surface of the first wafer.4. The device of claim 1 , wherein at ...

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Номер записи: 46
15-02-2018 дата публикации

BUMPLESS BUILD-UP LAYER PACKAGE WITH A PRE-STACKED MICROELECTRONIC DEVICES

Номер: US20180047702A1
Автор: Malatkar Pramod
Принадлежит:

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package. 1. A microelectronic package , comprising:a substrate;a plurality of stacked microelectronic dies above the substrate, the plurality of stacked microelectronic dies having a bottommost microelectronic die proximate the substrate, and a next bottommost microelectronic die above the bottommost microelectronic die, wherein the bottommost microelectronic die has a plurality of front side lands on an active portion facing the substrate and a plurality of backside lands facing the next bottommost microelectronic die with a plurality of through silicon vias (TSVs) electrically coupling the backside lands and the front side lands of the bottommost microelectronic die, wherein the next bottommost microelectronic die has a plurality of front side lands facing the bottommost microelectronic die, wherein the plurality of backside lands of the bottommost microelectronic die is directly coupled to the plurality of front side lands of the next bottommost microelectronic die by a solder layer, and wherein the plurality of front side lands of the bottommost microelectronic die electrically couples the bottommost microelectronic die to the substrate, wherein the TSVs of the bottommost microelectronic die are in direct contact with the backside lands of the bottommost microelectronic die but are not in direct contact with the front side lands of the bottommost microelectronic die;an underfill material layer between the bottommost microelectronic die and the next bottommost microelectronic die; andan encapsulation material over the substrate and laterally ...

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Номер записи: 47
03-03-2022 дата публикации

Integrated Circuit Package and Method

Номер: US20220068856A1
Автор: Chen-Hua Yu, Shih Ting Lin, Szu-Wei Lu, Wen-Chih Chiou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

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Номер записи: 48
03-03-2022 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20220069093A1
Автор: Katsuyuki KITAMOTO, Ken Komiya, Masayoshi Tagami
Принадлежит: Kioxia Corp

A semiconductor device includes: a plurality of first electrode films stacked in a state of being insulated from each other; a plurality of semiconductor members extending in a stacked direction of the plurality of first electrode films in a stacked body of the plurality of first electrode films; a plurality of charge storage members provided between the plurality of first electrode films and the plurality of semiconductor members; a first conductive film having a first surface, and commonly connected to the plurality of semiconductor members on the first surface; a first insulating film provided on a second surface of the first conductive film on the side opposite to the first surface; a contact provided in the first insulating film and connected to the first conductive film; and a second conductive film provided on the first insulating film and connected to the contact.

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Номер записи: 49
14-02-2019 дата публикации

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Номер: US20190051628A1
Автор: Chao Lan-Lin, Huang Xin-Hua, LIN SHIH-WEI, Liu Ping-Yin, Tsai Chia-Shiung
Принадлежит:

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together. 1. A method comprising:depositing a first protection layer on a first bonding surface of a first semiconductor wafer;removing the first protection layer from the first bonding surface of the first semiconductor wafer to expose the first bonding surface of the first semiconductor wafer;applying a plasma process to the first bonding surface of the first semiconductor wafer;performing a cleaning process on the first bonding surface of the first semiconductor wafer;coupling the first semiconductor wafer to a second semiconductor wafer; andannealing the first semiconductor wafer and the second semiconductor wafer to bond the first bonding surface of the first semiconductor wafer to a second bonding surface of the second semiconductor wafer, wherein bonding the first bonding surface of the first semiconductor wafer to the second bonding surface of the second semiconductor wafer comprises:forming a first bond between a first insulating layer of the first bonding surface and a second insulating layer of the second bonding surface; andforming a second bond between a first conductive pad of the first bonding ...

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Номер записи: 50
22-02-2018 дата публикации

METHOD FOR TRANSFERRING SEMICONDUCTOR STRUCTURE

Номер: US20180053684A1
Автор: CHEN Li-Yi, Lin Shih-Chyn
Принадлежит:

A method for transferring a semiconductor structure is provided. The method includes: coating an adhesive layer onto a carrier substrate; disposing the semiconductor structure onto the adhesive layer, in which the adhesive layer includes an adhesive component and an surfactant component after the disposing, the semiconductor structure includes a body and a bottom electrode, and the bottom electrode is disposed between the body and the adhesive layer after the disposing; irradiating a first electromagnetic wave to the adhesive layer to reduce adhesion pressure of the adhesive layer to the semiconductor structure while the semiconductor structure remains on the adhesive layer, in which the carrier substrate, the semiconductor structure, and the bottom electrode have a pass band in between ultraviolet to infrared; and transferring the semiconductor structure from the adhesive layer to a receiving substrate after the adhesion pressure of the adhesive layer is reduced. 1. A method for transferring at least one semiconductor structure , the method comprising:coating an adhesive layer onto a carrier substrate;disposing the semiconductor structure onto the adhesive layer, such that the adhesive layer temporarily adheres the semiconductor structure thereto, wherein the adhesive layer comprises at least one adhesive component and at least one surfactant component at least after the disposing, the semiconductor structure comprises a body and a bottom electrode, and the bottom electrode is disposed between the body and the adhesive layer after the disposing;irradiating at least one first electromagnetic wave to the adhesive layer to reduce adhesion pressure of the adhesive layer to the semiconductor structure while the semiconductor structure remains within a predictable position on the adhesive layer, wherein at least one of the carrier substrate and a combination of the body and the bottom electrode has a pass band in between ultraviolet to infrared; andtransferring the ...

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Номер записи: 51
25-02-2021 дата публикации

PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20210057362A1
Автор: Chen Hsien-Wei, Chen Ming-Fa, Yeh Sung-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a second bonding structure. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. The first dielectric layer is hybrid bonded to the second dielectric layer. The first connectors are hybrid bonded to the second connectors. The encapsulant laterally encapsulates the second die. The TIVs penetrate through the encapsulant and are connected to the first bonding structure. 1. A package , comprising:a first die having a first bonding structure, wherein the first bonding structure comprises a first dielectric layer and first connectors embedded in the first dielectric layer;a second die having a second bonding structure, wherein the second bonding structure comprises a second dielectric layer and second connectors embedded in the second dielectric layer, the first dielectric layer is hybrid bonded to the second dielectric layer, and the first connectors are hybrid bonded to the second connectors;an encapsulant laterally encapsulating the second die; andthrough insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs are connected to the first bonding structure.2. The package according to claim 1 , wherein the first dielectric layer is attached to the encapsulant and the second dielectric layer is laterally covered by the encapsulant.3. The package according to claim 1 , wherein each first connector of the first connectors has a via portion and a trench portion stacked on the via portion claim 1 , each second connector of the second connectors has a via portion and a trench portion stacked on the via portion claim 1 , and the trench portion of the second connector is hybrid bonded to the trench portion of ...

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Номер записи: 52
25-02-2021 дата публикации

SUBSTRATE BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME

Номер: US20210057373A1
Автор: Han Ilyoung, KIM HOECHUL, Kim Taeyeong
Принадлежит:

A substrate bonding method and apparatus are described. The substrate bonding apparatus is used to bond a first substrate to a second substrate. The bonding apparatus includes a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck; a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck; a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate; and a process gas supply device configured to supply a process gas to a bonding space surrounded by the seal. 1. A substrate bonding apparatus for bonding a first substrate to a second substrate , a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck;', 'a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck;', 'a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate, and configured to enclose a bonding space; and', 'a process gas supply device configured to supply a process gas to the bonding space enclosed by the seal., 'the substrate bonding apparatus comprising2. The substrate bonding apparatus of claim 1 , whereina first portion of the seal is detachably coupled to the first bonding chuck, anda second portion of the seal is coupled to the second bonding chuck, the second portion of the seal being opposite the first portion of the seal.3. The substrate bonding apparatus of claim 2 , whereinthe first bonding chuck comprises a vacuum groove, andthe substrate bonding apparatus further comprises a vacuum pump configured to provide ...

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Номер записи: 53
10-03-2022 дата публикации

BONDED STRUCTURE WITH INTERCONNECT STRUCTURE

Номер: US20220077063A1
Автор: Haba Belgacem
Принадлежит:

A bonded structure is disclosed. The bonded structure can include an interconnect structure that has a first side and a second side opposite the first side. The bonded structure can also include a first die that is mounted to the first side of the interconnect structure. The first die can be directly bonded to the interconnect structure without an intervening adhesive. The bonded structure can also include a second die that is mounted to the first side of the interconnect structure. The bonded structure can further include an element that is mounted to the second side of the interconnect structure. The first die and the second die are electrically connected by way of at least the interconnect structure and the element. 1. A bonded structure comprising:an interconnect structure having a first side and a second side opposite the first side, the first side comprising a first conductive pad, a second conductive pad, and a non-conductive region;a first die mounted and directly bonded to the first side of the interconnect structure, the first die electrically connected to the first conductive pad of the interconnect structure;a second die mounted to the first side of the interconnect structure, the second die electrically connected to the second conductive pad of the interconnect structure, the second die spaced apart from the first die laterally along the first side of the interconnect structure; andan element mounted to the second side of the interconnect structure,wherein the first die and the second die are electrically connected by way of at least the interconnect structure and the element.2. The bonded structure of claim 1 , wherein the first die comprises a bonding surface claim 1 , the bonding surface comprising a first conductive bond pad and a first non-conductive material claim 1 , the first conductive bond pad directly bonded to the first conductive pad without an intervening adhesive claim 1 , and the first non-conductive material directly bonded to a first ...

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Номер записи: 54
10-03-2022 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20220077072A1
Автор: LU Chun-Lin, Wu Kai-Chiang, Yu Chen-Hua
Принадлежит:

A method of manufacturing a semiconductor structure includes following operations. A first die is provided. A first molding is formed to encapsulate the first die. A second die is disposed over the first molding. A mold chase is disposed over the second die and the first molding. The mold chase includes a protrusion protruded from the mold chase towards the first molding. A molding material is disposed between the mold chase and the first molding. A second molding is formed to surround the second die. The second die is at least partially covered by the second molding. The disposing of the mold chase includes surrounding the protrusion of the mold chase by the molding material. 1. A method of manufacturing a semiconductor structure , comprising:providing a first die;forming a first molding to encapsulate the first die;disposing a second die over the first molding;disposing a mold chase over the second die and the first molding, wherein the mold chase includes a protrusion protruded from the mold chase towards the first molding;disposing a molding material between the mold chase and the first molding; andforming a second molding to surround the second die,wherein the second die is at least partially covered by the second molding, and the disposing the molding material includes surrounding the protrusion of the mold chase by the molding material.2. The method of claim 1 , further comprising:forming a recess extended through the second molding; anddisposing a third die within the recess.3. The method of claim 2 , wherein a sidewall of the recess of the second molding is conformal to an outer surface of the protrusion of the mold chase.4. The method of claim 1 , wherein the second molding is formed by transfer molding claim 1 , compression molding or print molding operations.5. The method of claim 1 , further comprising:inserting the protrusion of the mold chase into the molding material; anddisposing the protrusion of the mold chase over a surface of the second die.6. ...

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Номер записи: 55
10-03-2022 дата публикации

Bonded structure with interconnect structure

Номер: US20220077087A1
Автор: Belgacem Haba
Принадлежит: Invensas Bonding Technologies Inc

A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

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Номер записи: 56
10-03-2022 дата публикации

Semiconductor package with air gap

Номер: US20220077091A1
Автор: Tse-Yao Huang
Принадлежит: Nanya Technology Corp

The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

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Номер записи: 57
10-03-2022 дата публикации

METHODS OF FORMING STACKED INTEGRATED CIRCUITS USING SELECTIVE THERMAL ATOMIC LAYER DEPOSITION ON CONDUCTIVE CONTACTS AND STRUCTURES FORMED USING THE SAME

Номер: US20220077104A1
Автор: Bakir Muhannad, Breeden Mike, Hollin Jonathan, Kummel Andrew, LI Ming-Jui, LINN Nyi Myat Khine, Wang Victor, Winter Charles H.
Принадлежит:

Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact. 1. A method of bonding , the method comprising:providing a first substrate with a first electrical contact;providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; anddepositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact in the gap by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.2. The method of claim 1 , wherein the thermal ALD process does not require compression or mechanical force applied between the first and second electrical contacts.3. The method of claim 1 , wherein a spacing from the first substrate and the second substrate is substantially constant during the thermal ALD process.4. The method of claim 1 , wherein thermal ALD process creates a diffusion reaction between a precursor gas carrying a constituent of the selective metal and the surfaces of both the first and second electrical contacts.5. The method of claim 1 , wherein the first substrate is a wafer.6. The method of claim 1 ...

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Номер записи: 58
10-03-2022 дата публикации

Manufacturing method of semiconductor device and semiconductor device

Номер: US20220077106A1
Автор: Gen Toyota
Принадлежит: Kioxia Corp

According to one embodiment, a manufacturing method of a semiconductor device is provided. The manufacturing method includes removing a portion of an edge region from a front surface of a first substrate to form a notch in the edge region; bonding the front surface of the first substrate and a front surface of a second substrate together to forma stacked substrate, wherein the stack substrate includes an opening at a position corresponding to the notch; and filling the opening with an embedding member.

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Номер записи: 59
10-03-2022 дата публикации

STACKED DIE INTEGRATED WITH PACKAGE VOLTAGE REGULATORS

Номер: US20220077109A1
Автор: Chava Bharani, Kim Jonghae, ROY Abinash, SONG Stanley Seungchul
Принадлежит:

An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package. 1. An integrated circuit (IC) package , comprising:a first die having a first power delivery network on the first die;a second die having a second power delivery network on the second die, in which the first die is stacked on the second die; anda plurality of package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.2. The IC package of claim 1 , in which a front-side surface of the first die is directly bonded to a front-side surface of the second die.3. The IC package of claim 1 , in which a backside surface of the first die is directly bonded to a back-side surface of the second die.4. The IC package of claim 1 , further comprising a plurality of passive devices integrated with the plurality of package voltage regulators within the package core placed around a perimeter of the first die and the second die.5. The IC package of claim 1 ,in which the first die includes a front-side surface and a backside surface, opposite the front-side surface, the backside surface of the first die on a front-side surface of the first power delivery network; andin which the second die includes a front-side surface on the front-side surface of the first die and a backside surface on a front-side surface of the second power delivery network, the second power delivery network being distal from the first power delivery network.6. The IC package of claim 5 , further comprising:a first redistribution layer (RDL) coupled to a backside ...

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Номер записи: 60
05-03-2015 дата публикации

STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20150064843A1
Автор: CHOI Hyeong Seok
Принадлежит:

A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip. 1. A method for manufacturing a stacked semiconductor package , comprising:forming first through electrodes in a first wafer which is formed with a plurality of first semiconductor chips each having first bonding pads, to pass through first surfaces of the first semiconductor chips on which the first bonding pads are disposed;forming a first molding part on the first wafer to cover the first surfaces of the first semiconductor chips;exposing the first through electrodes on second surfaces of the first semiconductor chips which face away from the first surfaces;stacking a second wafer including a plurality of second semiconductor chips each having second bonding pads and formed with second through electrodes to a depth that passes through third surfaces on which the second bonding pads are disposed and does not reach fourth surfaces which face away from the third surfaces, over the first wafer such that the second through electrodes are electrically connected with the first through electrodes;exposing the second through electrodes on the fourth ...

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Номер записи: 61
01-03-2018 дата публикации

METAL BONDING PADS FOR PACKAGING APPLICATIONS

Номер: US20180061804A1
Автор: Yang Chih-Chao
Принадлежит:

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices. 1. A method for bonding a first semiconductor device to a second semiconductor device , comprising:providing a first semiconductor device comprising a first metal pad, wherein the first metal pad has a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface;providing a second semiconductor device comprising a second metal pad, wherein the second metal pad has a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface;contacting the second metal pad to the first metal pad; andbonding the first semiconductor device to the second semiconductor device at a temperature of less than 250° C. to greater than 100° C. and at a pressure of less than 250 psi to greater than 50 psi.2. The method of claim 1 , wherein the first and second metal pad comprise copper claim 1 , aluminum claim 1 , tungsten claim 1 , nitrides thereof claim 1 , or combinations comprising at less one of the foregoing.3. The method of claim 1 , wherein bonding the first semiconductor device to the second semiconductor device at a temperature of less than 200° C. to greater than 100° C. and at a pressure of less than 200 psi to greater than 100 psi.4. The method of claim 1 , wherein bonding the first semiconductor device to the second semiconductor device at a temperature of less than 175° C. to greater than 125° C. and at a pressure of less than 150 ...

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Номер записи: 62
20-02-2020 дата публикации

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20200058614A1
Автор: CHANG Geng-Ming, Shao Tung-Liang, Tung Chih-Hang, Yang Su-Chun, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated. 1. A method for forming a chip package structure , comprising:partially removing a first redistribution layer to form an alignment trench in the first redistribution layer, wherein the alignment trench surrounds a first bonding portion of the first redistribution layer;forming a liquid layer over the first bonding portion;disposing a chip structure over the liquid layer, wherein a first width of the first bonding portion is substantially equal to a second width of the chip structure; andevaporating the liquid layer, wherein the chip structure is bonded to the first bonding portion after the liquid layer is evaporated.2. The method for forming the chip structure package structure as claimed in claim 1 , wherein the liquid layer is made of water.3. The method for forming the chip package structure as claimed in claim 1 , further comprising:before partially removing the first redistribution layer to form the alignment trench in the first redistribution layer, forming the first redistribution layer over a substrate.4. The method for forming the chip package structure as claimed in claim 1 , wherein a first length of the first bonding portion is substantially equal to a second length of the chip structure.5. The method for forming the chip package structure as claimed in claim 1 , wherein the chip structure ...

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Номер записи: 63
04-03-2021 дата публикации

CHEMICAL MECHANICAL POLISHING FOR HYBRID BONDING

Номер: US20210066233A1
Автор: FOUNTAIN, JR. Gaius Gillman, MANDALAPU Chandrasekhar, THEIL Jeremy Alfred, Uzoh Cyprian Emeka
Принадлежит:

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer. 1. (canceled)2. A method comprising:forming one or more openings in a dielectric layer of a substrate, the one or more openings extending at least partially through the dielectric layer from a surface of the dielectric layer, a width of at least one of the one or more openings being at least 5 microns;forming a barrier layer over the surface of the dielectric layer and surfaces of the openings;forming a conductive structure disposed over the barrier layer and in the openings;polishing at least a portion of the conductive structure to reveal a surface of the barrier layer; andpolishing the barrier layer to reveal a planar dielectric bonding surface with a surface roughness of less than 1 nm root mean square (RMS), the conductive structure is recessed less than 25 nm from the dielectric bonding surface.3. A method according to claim 2 , wherein the substrate is a first substrate claim 2 , the method further comprising directly bonding the planar dielectric bonding surface of the first substrate to a prepared planar bonding surface of a second substrate.4. ...

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Номер записи: 64
04-03-2021 дата публикации

PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20210066248A1
Автор: Chen Ming-Fa, Hong Jian-Wei, Yeh Sung-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs. 1. A package , comprising:a first die;a second die stacked on the first die;a first encapsulant laterally encapsulating the first die;first through insulating vias (TIV) aside the first die, wherein the first TIVs penetrate through the first encapsulant and are electrically floating;a second encapsulant laterally encapsulating the second die; andsecond TIVs aside the second die, wherein the second TIVs penetrate through the second encapsulant and are electrically floating, and the second TIVs are substantially aligned with the first TIVs.2. The package of claim 1 , further comprising:a first bonding layer over the first die, the first encapsulant, and the first TIVs, wherein the first bonding layer comprises first bonding pads and connecting pads, and the first TIVs are connected to the connecting pads; anda second bonding layer sandwiched between the first bonding layer and the second die, wherein the second bonding layer comprises second bonding pads, and the first bonding pads are hybrid bonded to the second bonding pads.3. The package of claim 1 , further comprising:a carrier substrate over the second die and the second encapsulant.4. The package of claim 1 , wherein the first die comprises:a first semiconductor substrate;first through semiconductor vias (TSV) penetrating through the first semiconductor substrate;a first interconnection structure ...

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Номер записи: 65
04-03-2021 дата публикации

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Номер: US20210066250A1
Автор: Hong Yikoan, Jang Joohee, Kang Pilkyu, Kim Seokho, Lee Kyuha, Moon Kwangjin, Na Hoonjoo, PARK Jaehyung
Принадлежит:

A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer. 1. A method of manufacturing a semiconductor device , the method comprising:sequentially forming first through third insulating layers on a substrate;forming an opening by etching the first through third insulating layers;forming a conductive layer in the opening;forming a fourth insulating layer in the opening after the forming of the conductive layer; andremoving a portion of an edge region of the substrate after the forming of the fourth insulating layer.2. The method of claim 1 , further comprising cleaning the substrate by using an acid-base solution after the removing of the portion of the edge region of the substrate claim 1 ,wherein the conductive layer comprises a first of a plurality of conductive regions that are horizontally spaced apart from each other in the first through third insulating layers, andwherein, during the cleaning, the fourth insulating layer extends continuously from the first conductive region to a second and a third of the plurality of conductive regions.3. The method of claim 2 , wherein the cleaning of the substrate comprises removing a portion of the fourth insulating layer without exposing the first claim 2 , second claim 2 , and third of the plurality of conductive regions.4. The method of claim 1 , wherein the forming of the fourth insulating layer comprises forming a lowermost point of a top surface of the fourth insulating layer farther apart from the substrate than a top surface of the third insulating layer.5. The method of claim 1 , wherein ...

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Номер записи: 66
10-03-2016 дата публикации

MULTICHIP MODULES AND METHODS OF FABRICATION

Номер: US20160071818A1
Автор: Katkar Rajesh, Shen Hong, Wang Liang
Принадлежит:

In a multi-chip module (MCM), a “super” chip (N) is attached to multiple “plain” chips (F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties. 1. An assembly comprising:a wiring board comprising circuitry comprising a plurality of contact pads at a top side of the wiring board; one or more first contact pads at a bottom side of the first chip; and', 'one or more second contact pads at the bottom side of the first chip that are directly connected to one or more of the contact pads of the wiring board;, 'a plurality of first chips, each first chip comprising circuitry which comprisesa second chip overlying the wiring board and comprising circuitry comprising a plurality of first contact pads at a top side of the second chip, wherein at least one first contact pad of each first chip is attached to at least one first contact pad of the second chip;wherein at least one direct connection of at least one second contact pad of at least one first chip to at least one of the contact pads of the wiring board lies between the first chip and the wiring board and is longer than a thickness of the second chip.2. The assembly of wherein at least one direct connection between at least one second contact pad of at least one first chip and at least one contact pad of the wiring board lies entirely below the first chip.3. The ...

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Номер записи: 67
28-02-2019 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20190067244A1
Автор: Chen Ming-Fa, Chiou Wen-Chih, Yeh Sung-Feng
Принадлежит:

A semiconductor structure includes a substrate; a first die disposed over the substrate; a second die disposed over the substrate; a molding disposed over the substrate and surrounding the first die and the second die; an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed over the first die, the second die and the molding, and the conductive member is surrounded by the dielectric layer; and a via extended within the second die and between the dielectric layer and the substrate. 1. A semiconductor structure , comprising:a substrate;a first die disposed over the substrate;a second die disposed over the substrate;a molding disposed over the substrate and surrounding the first die and the second die;an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed over the first die, the second die and the molding, and the conductive member is surrounded by the dielectric layer; anda via disposed between the dielectric layer and the substrate, the via extended within the second die.2. The semiconductor structure of claim 1 , wherein the substrate is electrically connected with the conductive member through the via.3. The semiconductor structure of claim 1 , wherein a thickness of the first die is substantially different from or same as a thickness of the second die.4. The semiconductor structure of claim 1 , wherein the molding is disposed between the first die and the dielectric layer.5. The semiconductor structure of claim 1 , wherein the second die is a functional or dummy die.6. The semiconductor structure of claim 1 , wherein the first die is electrically connected with the conductive member through the substrate and the via.7. The semiconductor structure of claim 1 , further comprising a conductive bump disposed over the dielectric layer and electrically connected with the conductive member.8. A semiconductor structure claim 1 , comprising:a ...

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Номер записи: 68
08-03-2018 дата публикации

Conductive Pad Structure for Hybrid Bonding and Methods of Forming Same

Номер: US20180068965A1
Автор: Chen Sheng-Chau, Chou Cheng-Hsien, Chou Shih Pei, Chu Yen-Chang, HUANG Chih-Hui, Tu Yeur-Luen
Принадлежит:

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material. 1. A device comprising:a first substrate;a first redistribution structure over the first substrate;a first dielectric layer over the first redistribution structure; and a first portion extending through the first dielectric layer, the first portion having a first width; and', 'a second portion extending through the first redistribution structure, the second portion having a second width, the second width being different from the first width., 'a first conductive pad extending through the first dielectric layer and the first redistribution structure, a bottommost surface of the first conductive pad being below a bottommost surface of the first redistribution structure, wherein the first conductive pad comprises2. The device of claim 1 , wherein the second width is less than the first width.3. The device of claim 1 , further comprising:a second substrate;a second redistribution structure interposed between the second substrate and the first dielectric layer;a second dielectric layer interposed between the second redistribution structure and the first dielectric layer, the second dielectric layer being in physical contact with first dielectric layer; anda second conductive pad extending through the second dielectric layer and the second redistribution structure, the second conductive pad being in physical contact with the first conductive pad.4. The device of claim 3 , wherein a topmost surface of the second conductive pad is above a topmost surface of the second redistribution structure.5. The device of claim 3 , wherein the second conductive pad comprises:a third portion extending through the second ...

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Номер записи: 69
27-02-2020 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Номер: US20200066682A1
Автор: KIM Hyoju, KIM TAESEONG, Lee Hakseung, MIN Junhong, Moon Kwangjin
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Disclosed are semiconductor packages and methods of manufacturing the same. The semiconductor package comprises a substrate, a first unit structure attached to the substrate, and a second unit structure attached to the first unit structure. Each of the first and second unit structures comprises an adhesive layer, a lower semiconductor chip on the adhesive layer, an upper semiconductor chip on and in contact with the lower semiconductor chip, and a plurality of vias penetrating the upper semiconductor chip and connecting with the lower and upper semiconductor chips. 1. A semiconductor package , comprising:a substrate;a first unit structure attached to the substrate; anda second unit structure attached to the first unit structure, an adhesive layer;', 'a lower semiconductor chip on the adhesive layer;', 'an upper semiconductor chip on and in contact with the lower semiconductor chip; and', 'a plurality of vias penetrating the upper semiconductor chip and connecting with the lower and upper semiconductor chips., 'wherein each of the first and second unit structures comprises2. The semiconductor package of claim 1 , wherein a lower chip pad on a front side of the lower semiconductor chip; and', 'a lower insulating layer surrounding the lower chip pad on the front side of the lower semiconductor chip, and, 'the lower semiconductor chip comprises an upper chip pad on a front side of the upper semiconductor chip; and', 'an upper insulating layer surrounding the upper chip pad on the front side of the upper semiconductor chip., 'the upper semiconductor chip comprises3. The semiconductor package of claim 2 , wherein the lower semiconductor chip and the upper semiconductor chip are arranged to allow the front side of the lower semiconductor chip to face the front side of the upper semiconductor chip claim 2 ,wherein the lower insulating layer of the lower semiconductor chip and the upper insulating layer of the upper semiconductor chip are in contact with each other.4. The ...

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Номер записи: 70
11-03-2021 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20210074672A1
Автор: MATSUO Mie, Miyajima Hideshi
Принадлежит: Kioxia Corporation

In a manufacturing method of a semiconductor device according to an embodiment, a first substrate having a first elastic modulus is joined onto a second substrate having a second elastic modulus higher than the first elastic modulus. A first semiconductor element is formed on the first substrate. The first substrate is detached from the second substrate. 1. A manufacturing method of a semiconductor device , the method comprising:joining a first substrate having a first elastic modulus onto a second substrate having a second elastic modulus higher than the first elastic modulus;forming a first semiconductor element on the first substrate; anddetaching the first substrate from the second substrate.2. The method of claim 1 , further comprisingafter joining the first substrate to the second substrate,thinning the first substrate.3. The method of claim 1 , further comprisingbefore joining the first substrate to the second substrate,providing a first separable layer on the second substrate, the first separable layer joining the first substrate to the second substrate.4. The method of claim 2 , further comprisingbefore joining the first substrate to the second substrate,providing a first separable layer on the second substrate, the first separable layer joining the first substrate to the second substrate.5. The method of claim 1 , whereinthe first substrate is a silicon single crystal, and{'sub': 2', '3, 'the second substrate is a single crystal or a polycrystal of SiC, AlN, SiN, or AlO, or a composite thereof.'}6. The method of claim 2 , whereinthe first substrate is a silicon single crystal, and{'sub': 2', '3, 'the second substrate is a single crystal or a polycrystal of SiC, AlN, SiN, or AlO, or a composite thereof.'}7. The method of claim 3 , whereinthe first substrate is a silicon single crystal, and{'sub': 2', '3, 'the second substrate is a single crystal or a polycrystal of SiC, AlN, SiN, or AlO, or a composite thereof.'}8. The method of claim 3 , wherein the first ...

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Номер записи: 71
05-06-2014 дата публикации

Conductive compositions and methods of using them

Номер: US20140153167A1
Автор: Deborah Makita, James Hurley, Jose Quinones, Martin Sobczak, Rajan Hariharan, Senthil Kanagavel
Принадлежит: Alpha Metals Inc

A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.

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Номер записи: 72
07-03-2019 дата публикации

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

Номер: US20190074319A1
Автор: Horiike Machiko, Itonaga Kazuichiroh
Принадлежит: SONY CORPORATION

A semiconductor device, which is configured as a backside illuminated solid-state imaging device, includes a stacked semiconductor chip which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit; a semiconductor-removed region in which a semiconductor section of a part of the first semiconductor chip unit is completely removed; and a plurality of connection wirings which is formed in the semiconductor-removed region and connects the first and second semiconductor chip units to each other. 119-. (canceled)20. A semiconductor device , comprising:a first substrate including a pixel array and first connection pads;a second substrate bonded to the first substrate, the second substrate including second connection pads and a logic circuit for driving the pixel array; andconnection wirings that electrically connect the first connection pads to the second connection pads,wherein, in a plan view, pairs including one of the first connection pads and one of the second connection pads form a connection pad array, andwherein, in the plan view, at least one of the first connection pads partially overlaps at least one of the second connection pads.21. The semiconductor device of claim 20 , wherein claim 20 , in the plan view claim 20 , the first connection pads and the second connection pads have a same shape.22. The semiconductor device of claim 21 , wherein the same shape is an octagonal shape.23. The semiconductor device of claim 20 , wherein claim 20 , in the plan view claim 20 , each pair is a stage in which the first connection pad and the second connection pad are adjacent to one another in a first direction claim 20 , and wherein the connection pad array includes two stages in the first direction and four stages in a second direction.24. The ...

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Номер записи: 73
24-03-2022 дата публикации

BONDED ASSEMBLY INCLUDING INTERCONNECT-LEVEL BONDING PADS AND METHODS OF FORMING THE SAME

Номер: US20220093555A1
Автор: Chen Yangyin, Higashitani Masaaki, HOU Lin, Rabkin Peter, SHARANGPANI Rahul
Принадлежит:

A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures. 1. A method of forming a bonded assembly , comprising:providing a first semiconductor die, wherein the first semiconductor die comprises first semiconductor devices, first interconnect-level dielectric material layers embedding first metal interconnect structures and first metallic bonding structures, and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures;providing a second semiconductor die, wherein the second semiconductor die comprises second semiconductor devices, second interconnect-level dielectric material layers embedding second metal interconnect structures, and second metallic bonding structures;disposing the second semiconductor die in contact with the first semiconductor die; andannealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding ...

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Номер записи: 74
05-03-2020 дата публикации

BOND ENHANCEMENT IN MICROELECTRONICS BY TRAPPING CONTAMINANTS AND ARRESTING CRACKS DURING DIRECT-BONDING PROCESSES

Номер: US20200075520A1
Автор: Delacruz Javier A., FOUNTAIN, Gao Guilian, Huang Shaowu, JR. Gaius Gillman, Katkar Rajesh, Uzoh Cyprian Emeka, Wang Liang
Принадлежит:

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process. 1. A method , comprising:planarizing a bonding surface of a die or wafer to a flatness sufficient for direct bonding or for direct hybrid bonding at a bonding interface;providing a recess in the bonding surface before, during, or after the planarizing step, the recess configured to capture particles, contaminants, or bonding reaction byproducts or annealing reaction byproducts; andjoining the bonding surface with another bonding surface in a direct-bonding process or a direct hybrid bonding process.2. The method of claim 1 , further comprising determining a location at which the particles collect during the direct bonding or the direct hybrid bonding claim 1 , wherein a propagation of a bonding wave front mobilizes and moves the particles; andproviding the recess at the determined location.3. The method of claim 1 , further comprising vertically aligning a first recess in a first bonding ...

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Номер записи: 75
05-03-2020 дата публикации

BOND ENHANCEMENT IN MICROELECTRONICS BY TRAPPING CONTAMINANTS AND ARRESTING CRACKS DURING DIRECT-BONDING PROCESSES

Номер: US20200075533A1
Автор: Delacruz Javier A., FOUNTAIN, Gao Guilian, Huang Shaowu, JR. Gaius Gillman, Katkar Rajesh, Uzoh Cyprian Emeka, Wang Liang
Принадлежит:

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process. 1. A method , comprising:planarizing a bonding surface of a die or a wafer to a flatness sufficient for direct bonding or for direct hybrid bonding at a bonding interface; andproviding a recess in the bonding surface before, during, or after the planarizing step, the recess configured to arrest propagation of cracking, chipping, or delamination in the bonding surface, in a bonding layer, or in a completed bond of the bonding surface.2. The method of claim 1 , further comprising joining the bonding surface with another bonding surface in a direct-bonding process or a direct hybrid bonding process.3. The method of claim 2 , further comprising providing the recess in the bonding surface at or near the location of a stress point or a stress area to arrest the cracking or chipping.4. The method of claim 1 , further comprising vertically aligning a first recess in a first bonding surface with a ...

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Номер записи: 76
05-03-2020 дата публикации

WAFER LEVEL PACKAGE STRUCTURE AND WAFER LEVEL PACKAGING METHOD

Номер: US20200075539A1
Автор: DROWLEY Clifford Ian, LUO Hailong
Принадлежит:

Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process. 1. A wafer level packaging method , comprising:providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated on the first front surface of the device wafer;forming a first oxide layer on the first front surface of the device wafer;providing at least one second chip having a to-be-bonded surface;forming a second oxide layer on the to-be-bonded surface of each second chip;providing a carrier wafer;temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer;forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second chip, the encapsulation layer exposing a top of the second oxide layer; andbonding the device wafer and the second chip by bonding the first oxide layer and the second oxide layer using a low-temperature fusion bonding process.2. The method according to claim 1 , wherein the low-temperature fusion bonding process comprises:sequentially performing a plasma activation process, a deionized water ...

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Номер записи: 77
14-03-2019 дата публикации

Three-dimensional memory devices and methods for forming the same

Номер: US20190081069A1
Автор: Jifeng Zhu, Jun Chen, Qian Tao, Simon Shi-ning Yang, Steve Weiyi Yang, Yushi Hu, Zhenyu Lu
Принадлежит: Yangtze Memory Technologies Co Ltd

Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.

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Номер записи: 78
31-03-2022 дата публикации

Photonic package and method of manufacture

Номер: US20220099887A1
Автор: Chen-Hua Yu, Hsing-Kuo Hsia, Hung-Yi Kuo, Jiun Yi Wu, Kuo-Chiang Ting, Shang-Yun Hou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

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Номер записи: 79
31-03-2022 дата публикации

Method of manufacturing semiconductor structure

Номер: US20220102490A1
Автор: Hsih-Yang Chiu, Ting-Cih Kang
Принадлежит: Nanya Technology Corp

A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

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Номер записи: 80
25-03-2021 дата публикации

THREE-DIMENSIONAL INTEGRATED CIRCUIT TEST AND IMPROVED THERMAL DISSIPATION

Номер: US20210091041A1
Автор: IRBY Joel Thornton, Jeloka Supreet, SINHA Saurabh Pijuskumar
Принадлежит:

A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs. 1. A three-dimensional (3D) integrated circuit (IC) comprising:a bottom tier comprising first circuitry and first backside TSVs coupled to a substrate;a top tier coupled to the first tier at a front side, the top tier comprising second circuitry and second backside TSVs; anda heat conductor on the second backside TSVs of the top tier.2. The 3D IC of claim 1 , wherein the second backside TSVs are arranged in an array covering at least a portion of the second circuitry of the top tier.3. The 3D IC of claim 1 , wherein the heat conductor comprises a passivation material layer on the second backside TSVs claim 1 , a thermal interface material on the passivation material layer claim 1 , and a heat spreader on the thermal interface material.4. The 3D IC of claim 1 , wherein the substrate is a package substrate.5. The 3D IC of claim 1 , wherein the substrate is a board.6. The 3D IC of claim 1 , wherein the substrate is an organic substrate.7. The 3D IC of claim 1 , wherein the substrate is an interposer.8. The 3D IC of claim 1 , wherein the substrate is a system interface.9. A method of pre-bond testing a 3D IC comprising at least two tiers claim 1 , the method comprising:testing a top tier of the 3D IC at speed using TSVs on a backside of the top tier.10. The method of claim 9 , wherein the TSVs on the backside of the top tier are arranged in an array covering at least a portion of circuitry of the top tier.11. The method of claim 9 , further comprising: ...

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Номер записи: 81
25-03-2021 дата публикации

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Номер: US20210091064A1
Автор: Chen Hsien-Wei, Chen Jie, Chen Ming-Fa
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A method is provided. A bottom tier package structure is bonded to a support substrate through a first bonding structure, wherein the bottom tier package structure includes a first semiconductor die encapsulated by a first insulating encapsulation, and the first bonding structure includes stacked first dielectric layers and at least one stacked first conductive features penetrating through the stacked first dielectric layers. The support substrate is placed on a grounded stage such that the first semiconductor die is grounded through the at least one first stacked conductive features, the support substrate and the grounded stage. A second semiconductor die is bonded to the bottom tier package structure through a second bonding structure, wherein the second bonding structure includes stacked second dielectric layers and at least one stacked second conductive features penetrating through the stacked second dielectric layers. The second semiconductor die is encapsulated with a second insulating encapsulation. 1. A method , comprising:bonding a first package structure to a support substrate through a first bonding structure disposed between the first package structure and the support substrate, wherein the first package structure comprises a first semiconductor die encapsulated by a first insulating encapsulation, and the first bonding structure comprises stacked first dielectric layers and at least one stacked first conductive feature penetrating through the stacked first dielectric layers;placing the support substrate on a grounded stage such that the first semiconductor die is grounded through the at least one first stacked conductive feature, the support substrate and the grounded stage;after the first semiconductor die is grounded, bonding a second semiconductor die to the first package structure through a second bonding structure between the second semiconductor die and the first package structure, the second bonding structure comprising stacked second dielectric ...

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Номер записи: 82
31-03-2016 дата публикации

WAFER LEVEL INTEGRATION OF PASSIVE DEVICES

Номер: US20160093592A1
Автор: Zhai Jun
Принадлежит:

A semiconductor device is described that includes an integrated circuit coupled to a first semiconductor substrate with a first set of passive devices (e.g., inductors) on the first substrate. A second semiconductor substrate with a second set of passive devices (e.g., capacitors) may be coupled to the first substrate. Interconnects in the substrates may allow interconnection between the substrates and the integrated circuit. The passive devices may be used to provide voltage regulation for the integrated circuit. The substrates and integrated circuit may be coupled using metallization. 1. A semiconductor device , comprising:an integrated circuit;a first semiconductor substrate coupled to an active surface of the integrated circuit with a first metallization, wherein the first semiconductor substrate comprises a first set of passive devices and a first set of interconnects through the first semiconductor substrate; anda second semiconductor substrate coupled to the first semiconductor substrate with a second metallization, wherein the second semiconductor substrate comprises a second set of passive devices and a second set of interconnects through the second semiconductor substrate.2. The device of claim 1 , wherein the first set of passive devices comprise inductors and the second set of passive devices comprise capacitors.3. The device of claim 1 , further comprising an electrically insulating material filling a space around the first metallization and between the first semiconductor substrate and the integrated circuit.4. The device of claim 1 , further comprising an electrically insulating material filling a space around the second metallization and between the second semiconductor substrate and the first semiconductor substrate.5. The device of claim 1 , further comprising one or more pillars coupled to the active surface of the integrated circuit on a periphery of the first semiconductor substrate and the second semiconductor substrate claim 1 , wherein the ...

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Номер записи: 83
21-03-2019 дата публикации

Integrated Thermal Management for Surface Treatment with Atmospheric Plasma

Номер: US20190088451A1
Автор: Hughlett Robert Emmett, Pascual Daniel Nicholas, Penelon Joel Alfred, Phillips Matthew Sheldon, Schulte Eric Frank, Stead Michael Dow
Принадлежит: ONTOS Equipment Systems, Inc.

Methods and systems for thermal management methods to control the rates of chemical reaction at the surface of a substrate being treated by atmospheric plasma. Integrated thermal management includes static heating and cooling of the plasma head and the substrate, as well as dynamic heating and cooling of the substrate surface, before and after the substrate passes the linear aperture of the atmospheric plasma head. 1. A method of treating surfaces , comprising: while maintaining a glow discharge plasma inside the plasma head, and', 'while also moving the surface being treated and/or the plasma head with respect to each other; and, 'flowing a process gas stream, at approximately atmospheric pressure, through a plasma head and thence out an aperture to directly impinge on a surface being treated,'}passing the process gas stream, downstream of the aperture, through an open channel in the surface of the plasma head, and thence into an exhaust manifold; wherein the open channel faces the surface being treated.2. The method of claim 1 , further comprising heating the plasma head to a controlled temperature.3. The method of claim 1 , further comprising heating portions of the surface claim 1 , by scanning a laser claim 1 , just before they pass under the plasma head.4. The method of claim 1 , further comprising heating the plasma head to a controlled temperature.5. The method of claim 1 , further comprising uniformly heating the entire surface being treated.6. The method of claim 1 , further comprising uniformly cooling the entire surface being treated.7. The method of claim 1 , wherein the process gas stream comprises nitrogen.8. The method of claim 1 , wherein the process gas stream comprises N2 gas.9. The method of claim 1 , wherein the process gas stream comprises argon.10. A method of treating surfaces claim 1 , comprising: while maintaining a glow discharge plasma inside the plasma head, and', 'while also moving the surface being treated and/or the plasma head with ...

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Номер записи: 84
21-03-2019 дата публикации

METHOD AND APPARATUS FOR STACKING DEVICES IN AN INTEGRATED CIRCUIT ASSEMBLY

Номер: US20190088527A1
Автор: Uzoh Cyprian Emeka
Принадлежит: INVENSAS CORPORATION

Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both top side processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that top sides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks. 1. A method , comprising:placing a die in a die tray comprising at least one through-hole allowing processing on both a top side and a bottom side of the die;preparing both the top side and the bottom side of the die for direct bonding to a substrate or to another die without flipping the die;direct bonding the top side to a respective substrate or to another die; anddirect bonding the bottom side to a respective substrate or to another die.2. The method of claim 1 , further comprising removing the direct bonded die from the die tray or removing the die tray from the direct bonded die.3. The method of claim 1 , wherein the die comprises an ultrathin die.4. The method of claim 1 , further comprising simultaneously direct bonding the top side of the die and the bottom side of the die to respective substrates or dies.5. The method of claim 4 , further comprising placing multiple dies in multiple respective instances of the die tray and simultaneously direct bonding respective top sides and bottom sides of the ...

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Номер записи: 85
21-03-2019 дата публикации

Multichip modules and methods of fabrication

Номер: US20190088607A1
Автор: HONG Shen, Liang Wang, Rajesh Katkar
Принадлежит: Invensas LLC

In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

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Номер записи: 86
21-03-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20190088618A1
Автор: Higashi Kazuyuki, TSUMURA Kazumichi
Принадлежит:

A method of manufacturing a semiconductor device includes forming a first metal film on a first insulating region and a first metal region directly adjacent to the first insulating region, wherein the first metal film comprises a metal other than the metal of the first metal region, forming a second metal film on a second insulating region and a second metal region directly adjacent to the second insulating region, wherein the second metal film comprises a metal other than the metal of the second metal region, bringing the first metal film and the second metal film into contact with each other, and heat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second metal region to each other and simultaneously forming an insulating interface film between the first insulating region and the second insulating region. 1. A method of manufacturing a semiconductor device comprising:providing a first substrate comprising a first surface including a first insulating region and at least one first metal region directly adjacent to the first insulating region;forming a first metal film on the first insulating region and the first metal region, wherein the first metal film comprises a metal other than the metal of the first metal region;providing a second substrate comprising a second surface including a second insulating region and at least one second metal region directly adjacent to the second insulating region;forming a second metal film on the second insulating region and the second metal region, wherein the second metal film comprises a metal other than the metal of the second metal region;bringing the first metal film and the second metal film into contact with each other so that the first surface of the first substrate faces the second surface of the second substrate; andheat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second ...

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Номер записи: 87
05-05-2022 дата публикации

Semiconductor structure and method for forming the same

Номер: US20220139771A1
Автор: Jen-Yuan Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure includes a first die, a second die over the first die, and a positioning member disposed within a bonding dielectric and configured to align the second die with the first die. A method for forming a semiconductor structure includes receiving a first die having a first bonding layer; forming a recess on the first bonding layer; forming a positioning member on a second die; bonding the second die over the first die using the first bonding layer; and disposing the positioning member into the recess.

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Номер записи: 88
05-05-2022 дата публикации

Direct bonding methods and structures

Номер: US20220139867A1
Автор: Cyprian Emeka Uzoh
Принадлежит: Invensas Bonding Technologies Inc

A bonding method can include polishing a first bonding layer of a first element for direct bonding, the first bonding layer comprises a first conductive pad and a first non-conductive bonding region. After the polishing, a last chemical treatment can be performed on the polished first bonding layer. After performing the last chemical treatment, the first bonding layer of the first element can be directly bonded to a second bonding layer of a second element without an intervening adhesive, including directly bonding the first conductive pad to a second conductive pad of the second bonding layer and directly bonding the first non-conductive bonding region to a second nonconductive bonding region of the second bonding layer. No treatment or rinse is performed on the first bonding layer between performing the last chemical treatment and directly bonding.

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Номер записи: 89
05-05-2022 дата публикации

DIRECT BONDING METHODS AND STRUCTURES

Номер: US20220139869A1
Автор: FOUNTAIN, Gao Guilian, JR. Gaius Gillman, Mirkarimi Laura Wills, Uzoh Cyprian Emeka
Принадлежит:

A bonding method can include activating a first bonding layer of a first element for direct bonding to a second bonding layer of a second element. The bonding method can include, after the activating, providing a protective layer over the activated first bonding layer of the first element.

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Номер записи: 90
05-05-2022 дата публикации

Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same

Номер: US20220139878A1
Автор: Hiroyuki Ogawa, Ken Oowada, Mitsuteru Mushiga
Принадлежит: SanDisk Technologies LLC

A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.

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Номер записи: 91
05-05-2022 дата публикации

Semiconductor device and data storage system including the same

Номер: US20220139944A1
Автор: Jiyoung Kim, Jungtae Sung, Junyoung Choi, Yoonjo Hwang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.

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Номер записи: 92
28-03-2019 дата публикации

a method for manufacturing a mems device by first hybrid bonding a cmos wafer to a mems wafer

Номер: US20190092627A1
Автор: LIN Hung-Hua, Liu Ping-Yin, Peng Jung-Huei, Wu Chang-Ming, Yu Chung-Yi
Принадлежит:

A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis. 1. A method for packaging a microelectromechanical system (MEMS) , the method comprising:forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, wherein the first metallization structure comprises a first sacrificial oxide layer and a first metal contact pad;forming a second metallization structure over a MEMS wafer, wherein the second metallization structure comprises a second sacrificial oxide layer and a second metal contact pad;bonding the first metallization structure to the second metallization structure, wherein an upper surface of the first sacrificial oxide layer is bonded to an upper surface of the second sacrificial oxide layer and an upper surface of the first metal contact pad is bonded to an upper surface of the second metal contact pad;after the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer; andafter the first metallization structure and second metallization structure are bonded together, removing ...

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Номер записи: 93
19-03-2020 дата публикации

Semiconductor Oxide or Glass Based Connection Body with Wiring Structure

Номер: US20200091058A1
Автор: Fachmann Christian, Kutschak Matteo-Alessandro, Riegler Andreas, von Koblinski Carsten, Weber Hans
Принадлежит:

A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension. 120-. (canceled)21. A semiconductor device , comprisinga chip carrier comprising a substantially planar mounting surface;an electronic device that comprises an upper main surface with a conductive pad and a rear surface opposite the upper main surface;a connection body that comprises a glass base structure and an electrically conductive wiring structure,wherein the connection body is mounted on the chip carrier with the glass base structure facing and adhered to the mounting surface,wherein an enclosed cavity is disposed between the connection body and the chip carrier,wherein the electronic chip is disposed within the enclosed cavity,wherein the electrically conductive wiring structure is connected to the conductive pad of the electronic chip,wherein the electronic chip is mounted on the chip carrier such that the rear surface is flush against the mounting surface.22. The semiconductor device of claim 21 , wherein the wiring structure comprises a conductive track that is electrically connected to the conductive pad claim 21 , and wherein the conductive track laterally extends across an outer edge side of the electronic device.23. The semiconductor device of claim 22 , further comprising an electrically conductive lead that is spaced apart from the chip carrier claim 22 , wherein the conductive track laterally extends across a gap between the ...

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Номер записи: 94
05-04-2018 дата публикации

Substrate attachment for attaching a substrate thereto

Номер: US20180096962A1
Автор: Andreas Fehkührer
Принадлежит: EV Group E Thallner GmbH

A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

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Номер записи: 95
01-04-2021 дата публикации

Integrated Circuit Package and Method

Номер: US20210098323A1
Автор: Chen-Hua Yu, Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng LIU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

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Номер записи: 96
28-03-2019 дата публикации

Method for aligning chip components relative to substrate by using liquid

Номер: US20190096697A1
Автор: Kangwook Lee, Mitsumasa Koyanagi, Satohiko Hoshino, Shinya KIKUTA, Takafumi Fukushima
Принадлежит: Tohoku University NUC, Tokyo Electron Ltd

A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.

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Номер записи: 97
12-05-2022 дата публикации

Semiconductor device structure with bottle-shaped through silicon via and method for forming the same

Номер: US20220148995A1
Автор: Shing-Yih Shih, Tse-Yao Huang
Принадлежит: Nanya Technology Corp

A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

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Номер записи: 98
12-05-2022 дата публикации

Bonded assembly formed by hybrid wafer bonding using selectively deposited metal liners

Номер: US20220149002A1
Автор: Lin Hou, Masaaki Higashitani, Peter Rabkin, Yangyin Chen
Принадлежит: SanDisk Technologies LLC

A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.

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Номер записи: 99
28-03-2019 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20190096830A1
Автор: CHEN Hsin-Chi, Huang Hsun-Ying, LEE Kuo-Cheng, LI Cheng-Yuan, Lin Yen-Liang, WEI Chia-Yu
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via. 1. A semiconductor structure , comprising: a first conductive layer formed over a first substrate;', 'a first etching stop layer formed over the first conductive layer, wherein the first etching stop layer is in direct contact with the first conductive layer;', 'a first bonding layer formed over the first etching stop layer;', 'a first bonding via formed through the first bonding layer and the first etching stop layer, wherein the first bonding via is electrically connected to the first conductive layer;, 'a first semiconductor device, wherein the first semiconductor device comprises a second conductive layer formed over a second substrate;', 'a second etching stop layer formed over the second conductive layer, wherein the second etching stop layer is in direct contact with the second conductive layer;', 'a second bonding layer formed over the second etching stop layer;', 'a second bonding via formed through the second bonding layer and the second etching stop layer, wherein the second bonding via is electrically connected to the second conductive layer; and, 'a second semiconductor device, ...

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Номер записи: 100