Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Joining method and device therefor

Semiconductor device and method for manufacturing the same

JOINING METHOD AND DEVICE THEREFOR

A joining method, which comprises an initial washing step (S1) of washing the surface of articles (1b, 2a) to be joined, to remove a material (G) interfering with joining, such as an oxide or an adsorbed material, a surface roughness controlling step (S3) of forming an uneven surface having a prescribed roughness on one joining face (1b), a surface treatment step (S5) of removing a re-adsorbed material (F) attached to joining faces (1b, 2a), and then pressing a joining face (1b) having the uneven surface formed above to another joining face (2a), to thereby join the articles. The above joining method allows the metal joining at an ordinary temperature under a condition of an atmospheric pressure.

Package structure

Method For Producing And Cleaning Surface-Mountable Bases With External Contacts

In a method for producing bases with external contacts for surface mounting on circuit mounts, bases with external contacts are electrodeposited on semiconductor wafers or semiconductor chips. Subsequently, electrodeposited bases with external contacts are heat treated on the semiconductor wafers or the semiconductor chips at temperatures below the melting temperature of the deposited contact base material. Thereafter, a so-called RTP process is carried out in the form of a high-temperature interval in which the melting temperature is reached. Subsequently, the surfaces of the bases with external contacts are wet etched, the overall method being terminated by a cooling and drying operation. The bases with external contacts thus produced can be reliably surface mounted on circuit mounts.

MANUFACTURING OF FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.

METHOD FOR MANUFACTURING ELECTRONIC DEVICE BY USING FLIP-CHIP BONDING

An electronic device is manufactured by providing a substrate on which a pad including an organic solderability preservative (OSP) film is formed, mounting a die on the substrate such that the die is electrically connected to the pad, performing a molding process on the die mounted on the substrate, and thereafter, forming an oxide film on the substrate by using an oxidation process on the substrate.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

CHIP PACKAGING METHOD AND CHIP PACKAGE USING HYDROPHOBIC SURFACE

소수성 표면(hydrophobic surface)을 이용한 칩 패키징 방법은 제1 칩 또는 제1 보드 중 어느 하나 및 제2 칩 또는 제2 보드 중 어느 하나 각각의 표면에 미리 설정된 크기의 초소수성 표면을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 초소수성 표면 상의 미리 설정된 위치에 친수성 표면(hydrophilic surface)을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 친수성 표면에 액체 금속 볼(liquid metal ball)을 생성하는 단계; 및 상기 제1 칩 또는 상기 제1 보드 중 어느 하나의 액체 금속 볼 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나의 액체 금속 볼을 결합시킴으로써, 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나를 패키징 하는 단계를 포함한다. A method of chip packaging using a hydrophobic surface includes forming a super-hydrophobic surface of a predetermined size on a surface of either the first chip or the first board and the second chip or the second board, respectively; Forming a hydrophilic surface at a predetermined position on a super-hydrophobic surface formed on either the first chip or the first board and on either the second chip or the second board; Forming a liquid metal ball on a hydrophilic surface formed on either the first chip or the first board and on either the second chip or the second board; And either one of the liquid metal ball of the first chip or the first board and the liquid metal ball of either the second chip or the second board, And packaging either the second chip or the second board.

ELECTRODE BONDING METHOD AND PART MOUNTING APPARATUS

An electrode bonding method according to the present invention includes: a plasma cleaning step of irradiating an electrode surface (3) to be cleaned of at least either one of a part (1), such as a semiconductor device, and a substrate (10) with atmospheric pressure plasma (8) for cleaning; an inert gas atmosphere maintaining step of covering the electrode surface (3) to be cleaned and its vicinity with a first inert gas (4) before the irradiation of the atmospheric pressure plasma (8) is ended, and maintaining that state even thereafter; and a bonding step of bonding an electrode of the part (1) and an electrode on the substrate (10) before the inert gas atmosphere maintaining step is ended. The electrode surface (3) is thereby plasma-cleaned without the possibility of damaging the part (1) to be bonded to the substrate (10), and the cleaned state is maintained while bonding the electrodes to provide an electrode bonding state of high bonding force and high reliability.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To improve reliability of a flip chip connected semiconductor device. SOLUTION: In assembly of a flip chip connected BGA, when a semiconductor chip 1 is solder-connected by flip chip connection, a solder precoat 3 is formed on a surface of a land 2j on a lower surface 2b side of a wiring board 2, and the land 2j and a solder ball as an external terminal are solder-connected, and thereby, shock resistance of a connection portion between the land 2j and the solder ball can be enhanced, and reliability of the BGA can be improved. COPYRIGHT: (C)2011,JPO&INPIT ...

JOINING APPARATUS

PACKAGE-ON-PACKAGE (POP) STRUCTURE AND METHOD

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a chip package structure is provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer over the first pad. The method includes forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer. The method includes bonding a chip to the wiring substrate through a conductive bump and a flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the flux layer while the conductive protection layer covers the nickel-containing layer.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

A solution relating to electronic devices of flip-chip type is proposed. Particularly, an electronic device (200,300;400;700;800) of flip-chip type comprises at least one chip carrier (110;805) having a carrier surface (135;835), the carrier comprising one or more contact elements (140s,140p;740s,740p;840s,840p) of electrically conductive material on the carrier surface, at least one integrated circuit chip (105;705) having a chip surface (120;720), the chip comprising one or more terminals (125s,125p;725s,725p) of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material (150;750) soldering each terminal to the corresponding contact element, and restrain means (210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p) around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements (205s,205p;785s,785p;885s ...

BONDING APPARATUS CAPABLE OF PERFORMING EFFECTIVELY SURFACE TREATMENT

PURPOSE: A bonding apparatus is provided to perform effectively a surface treatment on a bonding object under a micro plasma condition and a bonding process on the bonding object. CONSTITUTION: A bonding apparatus includes a bonding treatment unit and a micro plasma generating unit. The bonding treatment unit is used for performing a bonding process on a bonding object by using a bonding tool. The micro plasma generating unit includes a plasma capillary(40) with an RF(Radio Frequency) coil. Predetermined plasma is generated in the plasma capillary by supplying power to the RF coil. The micro plasma generating unit is used for performing a surface treatment on the bonding object by spraying the predetermined plasma through a front end portion of the plasma capillary. © KIPO 2007 ...

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

An electronic device 200 of flip-chip type comprises at least one chip carrier 110 having a carrier surface 135, the carrier comprising one or more contact elements 140s,140p of electrically conductive material on the carrier surface, at least one integrated circuit chip 105 having a chip surface 120, the chip comprising one or more terminals 125s,125p of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material 150 soldering each terminal to the corresponding contact element, and restrain means 210s,210p around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements 205s,205p of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. The restrain means 210s,210p may have a surface phobic to solder ...

JOINING APPARATUS

Joining apparatus comprising a cleaning chamber; cleaning means for irradiating junction surfaces with energy waves in vacuum in the cleaning chamber; joining means for joining in air metal junction portions of items to be joined taken out from the cleaning chamber; and carrying means for, with respect to at least one member of the objects to be joined, carrying a foregoing object and an ensuing object substantially simultaneously in at least the carrying in direction to the cleaning chamber and the carrying out direction from the cleaning chamber. At the time of taking out objects to be joined after the cleaning into air and joining them to each other, the carrying in, carrying out and delivery of objects to be joined especially around the cleaning chamber can be accomplished smoothly within a short period of time, and mass production of desired joined products can be realized at high throughput. As a result, it becomes feasible to shorten the tact time through the entire joining process ...

Joining apparatus

A bonding apparatus comprising a cleaning chamber; cleaning means for irradiating energy waves to bonding surfaces in the cleaning chamber under a reduced pressure condition; bonding means for bonding metal bonding portions of objects to be bonded in an atmospheric air which have been taken out from the cleaning chamber; and carrying means for, with respect to at least one member of the objects to be bonded, carrying a foregoing object and an ensuing object substantially simultaneously in at least the carrying-in direction to the cleaning chamber and the carrying-out direction from the cleaning chamber. At the time of taking out the objects after cleaning into an atmospheric air and bonding them to each other, the carrying in, carrying out and delivery of objects to be bonded especially around the cleaning chamber can be performed smoothly within a short period of time, and mass production of desired bonded products can be realized at high throughput. As a result, it becomes possible to ...

Methods of producing and cleaning external contacts for surface-mounted chips and producing such chips tempers galvanically deposited layer followed by rapid thermal processing and moistening

A method of producing and cleaning external contacts of surface-mounted chips comprises galvanic deposition, tempering below the melting temperature performing high-temperature rapid thermal processing intervals during which the melting temperature is reached and moistening the surface. An independent claim is also included for a production method for surface-mounted chips as above.

PACKAGE-ON-PACKAGE (POP) STRUCTURE AND METHOD

Package on-package (PoP) structure including stud bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Joining method and device produced by this method and joining unit

A practical bonding technique is provided for solid-phase room-temperature bonding which does not require a profile irregularity of the order of several nanometers, in which a high-vacuum energy wave treatment and continuous high-vacuum bonding are not required. Since an adhering substance layer is thin immediately after a surface activating treatment using an energy wave, a bonding interface is spread by crushing the adhering substance layer to perform bonding, so that a new surface appears on a bonding surface, and objects to be bonded are bonded together. In order to crush the adhering substance layer more easily, a bonding metal of a bonding portion of the object to be bonded needs to have a low hardness. According to the results of various experiments conducted by the present inventors, it was found that the hardness of the bonding portion which is a Vickers hardness of 200 Hv or less is particularly effective for room-temperature bonding.

Package on-Package (PoP) structure including stud bulbs and method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

ELECTRODE BONDING METHOD AND PART MOUNTING APPARATUS

An electrode bonding method according to the present invention includes: a plasma cleaning step of irradiating an electrode surface (3) to be cleaned of at least either one of a part (1), such as a semiconductor device, and a substrate (10) with atmospheric pressure plasma (8) for cleaning; an inert gas atmosphere maintaining step of covering the electrode surface (3) to be cleaned and its vicinity with a first inert gas (4) before the irradiation of the atmospheric pressure plasma (8) is ended, and maintaining that state even thereafter; and a bonding step of bonding an electrode of the part (1) and an electrode on the substrate (10) before the inert gas atmosphere maintaining step is ended. The electrode surface (3) is thereby plasma-cleaned without the possibility of damaging the part (1) to be bonded to the substrate (10), and the cleaned state is maintained while bonding the electrodes to provide an electrode bonding state of high bonding force and high reliability. © KIPO & WIPO 2009 ...

Method of manufacturing an electronic package

一種電子封裝件之製法，係將電子元件藉由導電凸塊及形成於該導電凸塊上之銲錫端結合於承載結構上，其中，該銲錫端不經回銲作業而接觸該承載結構，使該導電凸塊上能形成足量的銲錫端，以避免該銲錫端發生破裂或銲錫崩塌之問題。

Electrode bonding method and part mounting apparatus

An electrode bonding method according to the present invention includes: a plasma cleaning step of irradiating an electrode surface (3) to be cleaned of at least either one of a part (1), such as a semiconductor device, and a substrate (10) with atmospheric pressure plasma (8) for cleaning; an inert gas atmosphere maintaining step of covering the electrode surface (3) to be cleaned and its vicinity with a first inert gas (4) before the irradiation of the atmospheric pressure plasma (8) is ended, and maintaining that state even thereafter; and a bonding step of bonding an electrode of the part (1) and an electrode on the substrate (10) before the inert gas atmosphere maintaining step is ended. The electrode surface (3) is thereby plasma-cleaned without the possibility of damaging the part (1) to be bonded to the substrate (10), and the cleaned state is maintained while bonding the electrodes to provide an electrode bonding state of high bonding force and high reliability.

Contoured package-on-package joint

Protecting flip-chip package using pre-applied fillet

JOINING METHOD AND DEVICE PRODUCED BY THIS METHOD AND JOINING UNIT

A joining technique capable of cold-joining at a practical solid layer without requiring energy wave processing under high vacuum, continuous joining under high vacuum, and an area accuracy on the order of several nanometers. When a deposition layer, still thin immediately after surface activating by energy wave, is crushed to make joining, the joint interface is spread and a regenerated surface appears on the joint surfaces to allow relative members to be joined. For the deposition layer to be easily crushed, the hardness of a joining metal at the joint portions of the relative members must be low. Various experiments conducted by this inventor have found that Vicker’s hardness at joint portions of up to 200 Hv is especially effective for cold joining.

ELECTRODE BONDING METHOD AND PART MOUNTING APPARATUS

An electrode bonding method according to the present invention includes: a plasma cleaning step of irradiating an electrode surface (3) to be cleaned of at least either one of a part (1), such as a semiconductor device, and a substrate (10) with atmospheric pressure plasma (8) for cleaning; an inert gas atmosphere maintaining step of covering the electrode surface (3) to be cleaned and its vicinity with a first inert gas (4) before the irradiation of the atmospheric pressure plasma (8) is ended, and maintaining that state even thereafter; and a bonding step of bonding an electrode of the part (1) and an electrode on the substrate (10) before the inert gas atmosphere maintaining step is ended. The electrode surface (3) is thereby plasma-cleaned without the possibility of damaging the part (1) to be bonded to the substrate (10), and the cleaned state is maintained while bonding the electrodes to provide an electrode bonding state of high bonding force and high reliability.

Contoured package-on-package joint

A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.

HYBRID INTERCONNECT FOR LASER BONDING USING NANOPOROUS METAL TIPS

Embodiments relate to using nanoporous metal tips to establish connections between a first body and a second body. The first body is positioned relative to the second body to align contacts protruding from a first surface of the first body with electrodes protruding from a second surface of the second body. The second surface faces the first surface. The contacts, the electrodes, or both comprise nanoporous metal tips. A relative movement is made between the first body and the second body after positioning the first body to approach the first body to the second body. The contacts and the electrodes are bonded by melting and solidifying the nanoporous metal tips after approaching the first body and the second body.

JOINING APPARATUS

Joining apparatus comprising a cleaning chamber; cleaning means for irradiating junction surfaces with energy waves in vacuum in the cleaning chamber; joining means for joining in air metal junction portions of items to be joined taken out from the cleaning chamber; and carrying means for, with respect to at least one member of the objects to be joined, carrying a foregoing object and an ensuing object substantially simultaneously in at least the carrying in direction to the cleaning chamber and the carrying out direction from the cleaning chamber. At the time of taking out objects to be joined after the cleaning into air and joining them to each other, the carrying in, carrying out and delivery of objects to be joined especially around the cleaning chamber can be accomplished smoothly within a short period of time, and mass production of desired joined products can be realized at high throughput. As a result, it becomes feasible to shorten the tact time through the entire joining process ...

Verfahren zum Herstellen und Reinigen von oberflächenmontierbaren Außenkontaktsockeln

Verfahren zum Herstellen und Reinigen von Außenkontaktsockeln für eine Oberflächenmontage auf Schaltungsträgern, wobei das Verfahren folgende Verfahrensschritte aufweist: galvanisches Abscheiden von Außenkontaktsockeln auf Halbleiterwafern oder Halbleiterchips; Ausdiffusion flüchtiger Substanzen aus den galvanisch abgeschiedenen Außenkontaktsockeln durch Tempern der galvanisch abgeschiedenen Außenkontaktsockel bei Temperaturen unterhalb einer Schmelztemperatur von abgeschiedenem Kontaktsockelmaterial mit einer Temperdauer tD im Bereich von 0,5 h tD 5,0 h; Durchführen eines RTP Hochtemperatur-Intervalls, bei dem mindestens die Schmelztemperatur erreicht wird, Nassätzen von Oberflächen der Außenkontaktsockel.

Method of manufacturing an electronic package

PRESSING DEVICE AND PRESSING METHOD

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.

The curved contour of the stacked package joint

Method of manufacturing semiconductor device

To aim at improvement of reliability of a semiconductor device of flip chip connection type. In assembling a BGA of flip chip connection type, when a semiconductor chip is solder-connected by a flip chip connection, because solder precoat is formed on the surface of a land on the side of an undersurface of a wiring substrate, the connection between the land and a solder ball, which is an external terminal, is solder-connection, and therefore, it is possible to increase impact resistance of a connection part between the land and the solder ball and to aim at improvement of reliability of the BGA.

JOINING METHOD AND DEVICE PRODUCED BY THIS METHOD AND JOINING UNIT

A practical bonding technique is provided for solid-phase room-temperature bonding which does not require a profile irregularity of the order of several nanometers, in which a high-vacuum energy wave treatment and continuous high-vacuum bonding are not required. Since an adhering substance layer is thin immediately after a surface activating treatment using an energy wave, a bonding interface is spread by crushing the adhering substance layer to perform bonding, so that a new surface appears on a bonding surface, and objects to be bonded are bonded together. In order to crush the adhering substance layer more easily, a bonding metal of a bonding portion of the object to be bonded needs to have a low hardness. According to the results of various experiments conducted by the present inventors, it was found that the hardness of the bonding portion which is a Vickers hardness of 200 Hv or less is particularly effective for room-temperature bonding.

FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. 1. An electronic device of a flip-chip type comprising:at least one chip carrier having a carrier surface, the at least one chip carrier comprising one or more contact elements of electrically conductive material on the carrier surface;at least one integrated circuit chip having a chip surface, the at least one integrated circuit chip comprising one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element;solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements; andwherein the at least one chip carrier comprises one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.2. The electronic device according to claim 1 , wherein the contact elements and the dissipation elements are portions of a ...

Joining apparatus

A bonding apparatus comprising a cleaning chamber; cleaning means for irradiating energy waves to bonding surfaces in the cleaning chamber under a reduced pressure condition; bonding means for bonding metal bonding portions of objects to be bonded in an atmospheric air which have been taken out from the cleaning chamber; and carrying means for, with respect to at least one member of the objects to be bonded, carrying a foregoing object and an ensuing object substantially simultaneously in at least the carrying-in direction to the cleaning chamber and the carrying-out direction from the cleaning chamber. At the time of taking out the objects after cleaning into an atmospheric air and bonding them to each other, the carrying in, carrying out and delivery of objects to be bonded especially around the cleaning chamber can be performed smoothly within a short period of time, and mass production of desired bonded products can be realized at high throughput. As a result, it becomes possible to ...

BONDING DEVICE

Protecting Flip-Chip Package using Pre-Applied Fillet

A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.

Elektrodenbondierungsverfahren und Teilmontageeinrichtung

Elektrodenbondierungsverfahren, bei welchem vorgesehen sind: ein Plasmareinigungsschritt der Behandlung einer Elektrodenoberfläche (3), die gereinigt werden soll, von zumindest entweder einem Teil (1) oder einem Substrat (10), durch Atmosphärendruckplasma (8) zum Reinigen; ein Schritt der Aufrechterhaltung einer Inertgasatmosphäre mit Abdecken der zu reinigenden Elektrodenoberfläche (3) und deren Umgebung mit einem ersten Inertgas (4), bevor die Behandlung mit dem Atmosphärendruckplasma (8) beendet ist, und Aufrechterhaltung dieses Zustands auch danach; und ein Bondierungsschritt mit Sondieren einer Elektrode des Teils (1) und einer Elektrode auf dem Substrat (10), bevor der Schritt der Aufrechterhaltung der Inertgasatmosphäre beendet ist.

Bonding method and apparatus

A bonding method and an apparatus that enable metal bonding under the atmospheric pressure and at room temperature, wherein the surfaces of objects (1b, 2a) to be bonded together are cleaned in an initial cleaning step (S1) to remove bonding inhibitor substances (G) such as oxides and adhered substances; one (1b) of the bonding surfaces is provided with an uneven profile with a predetermined roughness in a surface roughness control step (S3); a surface treatment step (S5) is performed to remove the substances (F) that have been removed but adhered to the bonding surfaces (1b, 2a) again; and the uneven bonding surface (1b) is pressed against the other bonding surface (2a) to bond them together.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Electrostatic discharge protection apparatus and process

In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.

Joining method and device produced by this method and joining unit

A practical bonding technique is provided for solid-phase room-temperature bonding not requiring a profile irregularity of the order of several nanometers, in which a high-vacuum energy wave treatment and continuous high-vacuum bonding are not required. Since an adhering substance layer is thin immediately after a surface activating treatment using an energy wave, a bonding interface is spread by crushing the adhering substance layer to perform bonding, so that a new surface appears on a bonding surface, and objects to be bonded are bonded together. In order to crush the adhering substance layer more easily, a bonding metal of a bonding portion of the object to be bonded requires a low hardness. According to the results of various experiments conducted by the present inventors, it was found that the hardness of the bonding portion which is a Vickers hardness of 200 Hv or less is particularly effective for room-temperature bonding.

Contoured package-on-package joint

本發明提供一種疊合式封裝裝置，包括：一封裝體連接盤(land)，位於一基板之一第一側上；一安裝釘柱(mounting stud)，位於封裝體連接盤(land)上且與封裝體連接盤(land)電性接觸，安裝釘柱具有一輪廓化的(contoured)釘柱表面，其表面型態與一連接件之一表面的一部分的一表面型態互補；以及一模塑底部填充(molded underfill；MUF)，位於基板之第一側上，且覆蓋安裝釘柱的至少一部分。本發明也提供一種疊合式封裝裝置的製造方法。

ELECTRODE BONDING METHOD AND PART MOUNTING APPARATUS

An electrode bonding method according to the present invention includes: a plasma cleaning step of irradiating an electrode surface to be cleaned of at least either one of a part, such as a semiconductor device, and a substrate with atmospheric pressure plasma for cleaning; an inert gas atmosphere maintaining step of covering the electrode surface to be cleaned and its vicinity with a first inert gas before the irradiation of the atmospheric pressure plasma is ended, and maintaining that state even thereafter; and a bonding step of bonding an electrode of the part and an electrode on the substrate before the inert gas atmosphere maintaining step is ended. The electrode surface is thereby plasma-cleaned without the possibility of damaging the part to be bonded to the substrate, and the cleaned state is maintained while bonding the electrodes to provide an electrode bonding state of high bonding force and high reliability.

METHOD FOR MANUFACTURING ELECTRONIC PACKAGE

The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

Protecting flip-chip package using pre-applied fillet

A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.

BONDING APPARATUS

PROBLEM TO BE SOLVED: To efficiently carry out the surface treatment and the bonding treatment for a target to be bonded by micro-plasma in a bonding apparatus. SOLUTION: The wire bonding apparatus 10 includes: a bonding-use XYZ-drive mechanism 20 for movably driving a bonding arm 21 having a bonding capillary 24 at the tip thereof; a surface-treatment-use XYZ-drive mechanism 30 for driving a plasma arm 31 provided with a plasma capillary 40 having a high-frequency coil wound about the tip thereof; a gas supply 60 for supplying a gas to the plasma capillary 40; and a high-frequency power supply 80 for supplying high-frequency power to the high-frequency coil. The gas is changed into plasma in the plasma capillary 40 by the supply of the high-frequency power, and the surface treatment is carried out by jetting it to the target 8 to be bonded. The bonding is carried out using the bonding capillary 24 in interlock with the surface treatment. COPYRIGHT: (C)2007,JPO&INPIT ...

Method For Producing And Cleaning Surface-Mountable Bases With External Contacts

In a method for producing bases with external contacts for surface mounting on circuit mounts, bases with external contacts are electrodeposited on semiconductor wafers or semiconductor chips. Subsequently, electrodeposited bases with external contacts are heat treated on the semiconductor wafers or the semiconductor chips at temperatures below the melting temperature of the deposited contact base material. Thereafter, a so-called RTP process is carried out in the form of a high-temperature interval in which the melting temperature is reached. Subsequently, the surfaces of the bases with external contacts are wet etched, the overall method being terminated by a cooling and drying operation. The bases with external contacts thus produced can be reliably surface mounted on circuit mounts.

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first package;a second pad on a second surface of a second package;a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , wherein the first package comprises a first substrate and a first integrated circuit die attached to the first substrate claim 1 , wherein the second package comprises a second substrate and a second integrated circuit die attached to the second substrate.3. The device of claim 2 , wherein the metallic element is laterally adjacent the first integrated circuit die with the first integrated circuit die and the metallic element being interposed between the first substrate and the second substrate.4. The device of claim 3 , wherein the metallic element extends closer to the second substrate than the first integrated circuit die.5. The device of claim 1 , wherein a height of the metallic element is between about 20 micrometers and about 200 ...

PRESSING DEVICE AND PRESSING METHOD

A pressure application technique is provided that enables two objects to be pressurized (e.g., objects to be bonded) to be positioned with greater accuracy before having pressure applied thereto. The objects to be pressurized are moved relative to each other in a Z direction such that the objects are brought into contact with each other (step S13). Then, a horizontal positional shift ΔD between the objects to be pressurized is measured in the contact state of the objects to be pressurized (step S14). Thereafter, positioning of the objects to be pressurized is again performed by moving the objects to be pressurized relative to each other in the horizontal direction, as a result of which the positional shift ΔD is corrected (step S17).

Method of manufacturing semiconductor device

The invention provides a method of manufacturing semiconductor device to aim at improvement of reliability of a semiconductor device of flip chip connection type. In assembling a BGA of flip chip connection type, when a semiconductor chip is solder-connected by a flip chip connection, because solder precoat is formed on the surface of a land on the side of an undersurface of a wiring substrate, the connection between the land and a solder ball, which is an external terminal, is solder-connection, and therefore, it is possible to increase impact resistance of a connection part between the land and the solder ball and to aim at improvement of reliability of the BGA.

Semiconductor substrate, semiconductor deviceimage pickup device, and imaging device

No clean flux composition and methods for use thereof

A flux formulation includes an activator and a protic solvent. The activator may be glutaric acid, levulinic acid, 2-ketobutyric acid, 2-oxovaleric acid, or mixtures thereof. Suitable protic solvents include alkanediol, alkoxy propanol and alkoxy ethanol. The flux formulation may be a no-clean flux formulation that may be used in the soldering of electronic circuit board assemblies, for example, in conjunction with a support fixture having a planar back surface that minimizes vibrations during processing that might otherwise cause misalignment between a chip and a substrate prior to solder reflow.

Method of manufacturing semiconductor device

To aim at improvement of reliability of a semiconductor device of flip chip connection type. In assembling a BGA of flip chip connection type, when a semiconductor chip is solder-connected by a flip chip connection, because solder precoat is formed on the surface of a land on the side of an undersurface of a wiring substrate, the connection between the land and a solder ball, which is an external terminal, is solder-connection, and therefore, it is possible to increase impact resistance of a connection part between the land and the solder ball and to aim at improvement of reliability of the BGA.

Method of manufacturing semiconductor device

FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

A solution relating to electronic devices of flip-chip type is proposed. Particularly, an electronic device () of flip-chip type comprises at least one chip carrier () having a carrier surface (), the carrier comprising one or more contact elements () of electrically conductive material on the carrier surface, at least one integrated circuit chip () having a chip surface (), the chip comprising one or more terminals () of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material () soldering each terminal to the corresponding contact element, and restrain means () around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements () of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. 1. An electronic device of a flip-chip type comprising:at least one chip carrier having a carrier surface, the at least one chip carrier comprising one or more contact elements of electrically conductive material on the carrier surface;at least one integrated circuit chip having a chip surface, the at least one integrated circuit chip comprising one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element;solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements; andwherein the at least one chip carrier comprises one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.2. The electronic device according to claim 1 , ...

Package structure

Package-On-Package (PoP) structures and methods of forming PoP structures are disclosed. According to an embodiment, a structure comprises a first substrate, stud bulbs, a die, a second substrate, and electric connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

JOINING METHOD AND DEVICE PRODUCED BY THIS METHOD AND JOINING UNIT

A practical bonding technique is provided for solid-phase room-temperature bonding not requiring a profile irregularity of the order of several nanometers, in which a high-vacuum energy wave treatment and continuous high-vacuum bonding are not required. Since an adhering substance layer is thin immediately after a surface activating treatment using an energy wave, a bonding interface is spread by crushing the adhering substance layer to perform bonding, so that a new surface appears on a bonding surface, and objects to be bonded are bonded together. In order to crush the adhering substance layer more easily, a bonding metal of a bonding portion of the object to be bonded requires a low hardness. According to the results of various experiments conducted by the present inventors, it was found that the hardness of the bonding portion which is a Vickers hardness of 200 Hv or less is particularly effective for room-temperature bonding.

Protecting flip-chip package using pre-applied fillet

ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND PROCESS

In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer. 1. A method forming a semiconductor device , comprising:forming at least one circuit element in each die of a plurality of dies in a substrate, where an outer region of the substrate surrounds each die of the plurality of dies;forming a conductive layer over the substrate, wherein the conductive layer is over and vertically aligned with at least one die of the plurality of dies and over and vertically aligned with a portion of the outer region, the conductive layer in electrical contact with the at least one circuit element in the at least one die;discharging electrostatic charges from the substrate via the conductive layer, wherein the discharging includes directly contacting a grounded electrode to a top surface of the conductive layer; andafter the discharging electrostatic charges removing a portion of the conductive layer.2. The method of claim 1 , whereindischarging the electrostatic charges comprises causing the grounded electrode to temporarily contact the conductive layer over the outer region.3. The method of claim 2 , whereinthe outer region comprises at least one scribe line,said discharging the electrostatic charges comprises causing the grounded electrode to temporarily contact the conductive layer over the at least one scribe line.4. The method of claim 1 , wherein the plurality of dies includes at least one interposer.5. The method of claim 1 , further comprising:forming a conductive bump over the substrate prior to the discharging electrostatic charges.6. The method of claim 1 , wherein the conductive layer includes an under-bump metal (UBM) structure.7. The method of claim 1 , wherein the removing the portion of the conductive layer includes performing photolithographic masking and etching ...

Semiconductor device and method for manufacturing the same

The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a first metal contact and a second electronic component including a second metal contact, changing a lattice of the first metal contact, and bonding the first metal contact to the second metal contact under a predetermined pressure and a predetermined temperature.

Method for manufacturing electronic package

The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

Contoured Package-on-Package Joint

A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.

Electrode bonding method and part mounting apparatus

根据本发明的电极结合方法包括：等离子体清洁步骤，用大气压等离子体(8)辐射诸如半导体器件之类的元件(1)和基底(10)中的至少一个的被清洁的电极表面(3)从而进行清洁；惰性气体氛围保持步骤，在大气压等离子体(8)的辐射结束之前，用第一惰性气体(4)覆盖被清洁的电极表面(3)及其附近，并在此后还保持该状态；以及结合步骤，在惰性气体氛围保持步骤结束之前，结合元件(1)的电极和基底(10)上的电极。电极表面(3)由此进行等离子体清洁，而没有损坏待结合到基底(10)上的元件(1)的可能性，在结合电极时保持该清洁状态，以提供高结合力和高可能性的结合状态。

Package-on-package (PoP) structure including stud bulbs and method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Flip chip electronic device with carrier free of heat dissipation element without solder mask

提出了一种涉及倒装芯片类型的电子装置的技术方案。特别是，一种倒装芯片类型的电子装置(200,300；400；700；800)，包括：具有载体表面(135；835)的至少一个芯片载体(110；805)，该载体包括在该载体表面上的导电材料的一个或多个接触元件(140s,140p；740s,740p；840s,840p)，具有芯片表面(120；720)的至少一个集成电路芯片(105；705)，该芯片包括在该芯片表面上的导电材料的一个或多个端子(125s,125p；725s,725p)，每个芯片端子面对对应的接触元件，将每个端子焊接到该对应的接触元件的焊料材料(150；750)，以及围绕该接触元件的限制装置(210s,210p,310；410sl,410sd,410p；790s,790p；890s,890p)，用于在将该端子焊接到该接触元件期间限制该焊料材料，其中，该载体包括在该载体表面上的导热材料的一个或多个热消散元件(205s,205p；785s,785p；885s,885p)，一个或多个热消散元件从该端子移位，该载体表面面对该芯片表面，该消散元件不含任何焊接掩模。

Package-On-Package (PoP) Structure Including Stud Bulbs and Method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Package-on-package (PoP) structure including stud bulbs

Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures are provided. A structure may include a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

ELECTRODE CONNECTING METHOD AND PART MOUNTING DEVICE

PROBLEM TO BE SOLVED: To provide an electrode connecting method which is used for connecting the electrodes of a part to those of a board, capable of subjecting the surface of the electrode to a plasma cleaning step without causing any damage to the part connected to the board, joining the electrodes together while the electrodes are kept in a cleaned state, and resultantly obtaining an electrode connection state that is high in bonding strength and reliability. SOLUTION: The electrode connecting method includes a plasma cleaning step of cleaning the cleaning object electrode surface 3 of, at least, either a semiconductor device 1 as a component or a board 10 by irradiating it with an atmospheric-pressure plasma 8; an inert gas atmosphere retaining step of covering the cleaning object electrode surface 3 and its surroundings with a first inert gas 4, until a point of time that irradiation with the atmospheric pressure plasma 8 is finished, and maintaining the above state thereafter; and ...

Protecting flip-chip package using pre-applied fillet

一种管芯具有第一表面，位于第一表面对面的第二表面，和包括第一部分和第二部分的侧壁，其中相比于第二部分，第一部分更接近于第一表面。填角接触管芯的侧壁的第一部分并且包围管芯。工件通过焊料凸块与管芯接合，其中第二表面面向工件。第一底部填充胶填充管芯和工件之间的间隙，其中第一底部填充胶接触填角，并且其中第一底部填充胶和填角由不同的材料形成。

ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND PROCESS

In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.

NO CLEAN FLUX COMPOSITION AND METHODS FOR USE THEREOF

A flux formulation includes an activator and a protic solvent. The activator may be glutaric acid, levulinic acid, 2-ketobutyric acid, 2-oxovaleric acid, or mixtures thereof. Suitable protic solvents include alkanediol, alkoxy propanol and alkoxy ethanol. The flux formulation may be a no-clean flux formulation that may be used in the soldering of electronic circuit board assemblies, for example, in conjunction with a support fixture having a planar back surface that minimizes vibrations during processing that might otherwise cause misalignment between a chip and a substrate prior to solder reflow.

PRESSURE APPLICATION APPARATUS AND PRESSURE APPLICATION METHOD

A pressure application technique is provided that enables two objects to be pressurized (e.g., objects to be bonded) to be positioned with greater accuracy before having pressure applied thereto. The objects to be pressurized are moved relative to each other in a Z direction such that the objects are brought into contact with each other (step S13). Then, a horizontal positional shift D between the objects to be pressurized is measured in the contact state of the objects to be pressurized (step S14). Thereafter, positioning of the objects to be pressurized is again performed by moving the objects to be pressurized relative to each other in the horizontal direction, as a result of which the positional shift D is corrected (step S17).

Pressure application apparatus and pressure application method

A pressure application technique is provided that enables two objects to be pressurized (e.g., objects to be bonded) to be positioned with greater accuracy before having pressure applied thereto. The objects to be pressurized are moved relative to each other in a Z direction such that the objects are brought into contact with each other (step S13). Then, a horizontal positional shift D between the objects to be pressurized is measured in the contact state of the objects to be pressurized (step S14). Thereafter, positioning of the objects to be pressurized is again performed by moving the objects to be pressurized relative to each other in the horizontal direction, as a result of which the positional shift D is corrected (step S17).

ELECTRONIC MEMBER, ELECTRONIC COMPONENT, AND MANUFACTURING METHOD THEREFOR

PROBLEM TO BE SOLVED: To provide electronic members which can be electrically connected by supplying a bonding material at fine pitches. SOLUTION: When a silver oxide is reduced to silver, many cores of metallic silver are formed in the silver oxide, and the silver oxide is hollowed out while maintaining its original outer configuration, and a curvature of generated silver is increased. By utilizing this microparticulation mechanism, bonding is possible even when the silver oxide is provided not as particles but as compact layers. The electronic member includes an electrode for input/output of an electric signal or a connection terminal for connection of an electric signal and has an oxide silver layer 205 formed on the outermost surface of the electrode or the connection terminal. COPYRIGHT: (C)2010,JPO&INPIT ...

Protecting Flip-Chip Package using Pre-Applied Fillet

A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.

Contoured Package-on-Package Joint

A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.

Electrode bonding method and component mounting apparatus

Joining device

Manufacturing of flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.

接合装置および接合方法

Joining apparatus

一种接合装置，具有：清洗室；清洗单元，在该清洗室内在减压情况下对所说金属接合部的接合面照射能量波；接合单元，在大气中将从所说清洗室内取出的被接合物的金属接合部彼此接合；输送单元，将至少就一方被接合物而言在前的被接合物和后续的被接合物实质上同时至少沿着向所说清洗室内送入的方向和从清洗室内送出的方向进行输送。在将清洗后的被接合物取出至大气中进行接合时，特别是围绕清洗室进行的被接合物的送入和送出以及传递能够圆滑且以较短时间完成，能够以高处理量批量生产既定的接合制品。其结果，可缩短整个接合工序的生产节拍时间、降低接合工序所需要的成本。

Joining apparatus

METHOD FOR MANUFACTURING ELECTRONIC PACKAGE

The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

Protecting flip-chip package using pre-applied fillet

A die has a first surface, a second surface opposite the first surface, and sidewalls including a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of differentmaterial.

Package-On-Package (PoP) Structure Including Stud Bulbs and Method

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

Bonding apparatus and method

A wire bonding apparatus 10 including an XYZ drive mechanism 20 for moving a bonding arm 21 that has a bonding capillary 24 at its tip end, an XYZ drive mechanism 30 for driving a plasma arm 31 that has a plasma capillary 40 having a high-frequency coil wound at its tip end portion end, a gas supply unit 60 for supplying gas to the plasma capillary, and a high-frequency power supply unit 80 for supplying high-frequency electric power to the high-frequency coil. With a supply of high-frequency electric power to the high-frequency coil, gas is being a plasma inside the plasma capillary and is ejected from its tip end against a bonding subject 8, thus performing surface treatment on the bonding subject; and using the bonding capillary, bonding is performed interconnectedly with this surface treatment.

Contoured Package-on-Package Joint

A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.

No clean flux composition and methods for use thereof

A flux formulation includes an activator and a protic solvent. The activator may be glutaric acid, levulinic acid, 2-ketobutyric acid, 2-oxovaleric acid, or mixtures thereof. Suitable protic solvents include alkanediol, alkoxy propanol and alkoxy ethanol. The flux formulation may be a no-clean flux formulation that may be used in the soldering of electronic circuit board assemblies, for example, in conjunction with a support fixture having a planar back surface that minimizes vibrations during processing that might otherwise cause misalignment between a chip and a substrate prior to solder reflow.

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

Semiconductor packaging method and semiconductor structure

本申请提出一种半导体封装方法及半导体结构。半导体封装方法包括：提供基底；在所述基底上形成金属焊盘，其中所述金属焊盘的侧壁与所述基底之间存在间隙；将多个所述基底的所述金属焊盘相连。本申请提出的半导体封装方法能够使间隙的形成工艺具备更佳的可控性，减少不同基底之间的金属焊盘在接合过程中因为热膨胀造成周围结构的损害，实现更优的封装效果。

Chip set and method for manufacturing the same

本发明提供一种芯片组及其制造方法。芯片组包括多个逻辑核心以及存储器芯片。多个逻辑核心分别具有第一装置层以及第一基板层，并且分别包括多个第一键合组件以及第一输入输出电路。多个第一键合组件设置在第一装置层。第一输入输出电路设置在第一装置层。存储器芯片具有第二装置层以及第二基板层，并且包括多个第二键合组件以及多个第二输入输出电路。多个第二键合组件设置在第二装置层。多个第二输入输出电路设置在第二装置层，且分别连接多个逻辑核心的第一输入输出电路。多个逻辑核心的多个第一键合组件的多个第一键合面分别与存储器芯片的多个第二键合组件的多个第二键合面以接垫对接垫的方式直接接合。

Bonding equipment

Electrode bonding method and part mounting apparatus

An electrode bonding method according to the present invention includes: a plasma cleaning step of irradiating an electrode surface to be cleaned of at least either one of a part, such as a semiconductor device, and a substrate with atmospheric pressure plasma for cleaning; an inert gas atmosphere maintaining step of covering the electrode surface to be cleaned and its vicinity with a first inert gas before the irradiation of the atmospheric pressure plasma is ended, and maintaining that state even thereafter; and a bonding step of bonding an electrode of the part and an electrode on the substrate before the inert gas atmosphere maintaining step is ended. The electrode surface is thereby plasma-cleaned without the possibility of damaging the part to be bonded to the substrate, and the cleaned state is maintained while bonding the electrodes to provide an electrode bonding state of high bonding force and high reliability.

Chip set and method for manufacturing the same

本发明提供一种芯片组及其制造方法。芯片组包括多个逻辑核心以及存储器芯片。多个逻辑核心分别具有第一装置层以及第一基板层，并且分别包括多个第一键合组件以及第一输入输出电路。多个第一键合组件设置在第一装置层。第一输入输出电路设置在第一装置层。存储器芯片具有第二装置层以及第二基板层，并且包括多个第二键合组件以及多个第二输入输出电路。多个第二键合组件设置在第二装置层。多个第二输入输出电路设置在第二装置层，且分别连接多个逻辑核心的第一输入输出电路。多个逻辑核心的多个第一键合组件的多个第一键合面分别与存储器芯片的多个第二键合组件的多个第二键合面以接垫对接垫的方式直接接合。

Electrostatic discharge protection apparatus and process

In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.

Electronic member, electronic part and manufacturing method therefor

When silver oxide is reduced to silver, a large number of cores of metallic silver are formed inside the silver oxide. Then, the silver oxide is reduced in a manner of being hollowed out while its original outer configuration is being maintained. As a result, the curvature of the silver generated becomes larger. The utilization of this microscopic-particle implementation mechanism allows accomplishment of the bonding even if the silver oxide is supplied not in a particle-like configuration, but in a closely-packed layer-like configuration. In the present invention, there is provided an electronic member including an electrode for inputting/outputting an electrical signal, or a connection terminal for establishing a connection with the electrical signal, wherein the uppermost surface of the electrode or the connection terminal is a silver-oxide layer.

Chip package structure and method for forming the same

A method for forming a chip package structure is provided. The method includes providing a wiring substrate. The method includes sequentially forming a nickel-containing layer and a gold-containing layer over the first pad. The method includes forming a conductive protection layer covering the gold-containing layer over the nickel-containing layer. The method includes bonding a chip to the wiring substrate through a conductive bump and a flux layer surrounding the conductive bump. The conductive bump is between the second pad and the chip. The method includes removing the flux layer while the conductive protection layer covers the nickel-containing layer.

Package-on-package (PoP) structure and method

本发明涉及堆叠封装(PoP)的结构和形成PoP结构的方法。根据一个实施例，结构包括第一衬底、螺柱球、管芯、第二衬底和电连接件。螺柱球与第一衬底的第一表面相接合。管芯附接至第一衬底的第一表面。电连接件与第二衬底连接，以及对应的电连接件与对应的螺柱球相连。

Semiconductor substrate, semiconductor deviceimage pickup device, and imaging device

Pressure application apparatus and pressure application method

A pressure application technique is provided that enables two objects to be pressurized (e.g., objects to be bonded) to be positioned with greater accuracy before having pressure applied thereto. The objects to be pressurized are moved relative to each other in a Z direction such that the objects are brought into contact with each other (step S 13 ). Then, a horizontal positional shift ΔD between the objects to be pressurized is measured in the contact state of the objects to be pressurized (step S 14 ). Thereafter, positioning of the objects to be pressurized is again performed by moving the objects to be pressurized relative to each other in the horizontal direction, as a result of which the positional shift ΔD is corrected (step S 17 ).

Chip packaging method and chip package using hydrophobic surface

소수성 표면(hydrophobic surface)을 이용한 칩 패키징 방법은 제1 칩 또는 제1 보드 중 어느 하나 및 제2 칩 또는 제2 보드 중 어느 하나 각각의 표면에 미리 설정된 크기의 초소수성 표면을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 초소수성 표면 상의 미리 설정된 위치에 친수성 표면(hydrophilic surface)을 형성하는 단계; 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나 각각에 형성된 친수성 표면에 액체 금속 볼(liquid metal ball)을 생성하는 단계; 및 상기 제1 칩 또는 상기 제1 보드 중 어느 하나의 액체 금속 볼 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나의 액체 금속 볼을 결합시킴으로써, 상기 제1 칩 또는 상기 제1 보드 중 어느 하나 및 상기 제2 칩 또는 상기 제2 보드 중 어느 하나를 패키징 하는 단계를 포함한다.

Flip-chip type electronic device and method for manufacturing flip-chip type electronic device

Interconnection structure for integrated circuit package and the method thereof

An interconnection structure for IC package onto the external device is discussed. The IC package has a voltage regulator contained therein; and the external device has a load assembled thereupon. A plurality of connection devices with elasticity are attached to the IC package, so that when a perpendicular force is applied to the connection devices, the IC package is electrically coupled to the external device to provide power supply to the load with ease replacement.

封装结构及其制法

本发明涉及一种封装结构及其制法，包括将多个具有导电柱的硅中介板相互堆叠，且于任两硅中介板之间以覆晶方式配置有至少一电子元件，使该电子元件位于两硅中介板所夹置的空间中，以经由低成本的TSV制程制作该硅中介板，且以技术成熟性高的覆晶方式进行该些硅中介板与电子元件的堆叠封装，以利于提升良率，同时大幅降低该封装结构的制作成本。

전자 디바이스를 제조하기 위한 방법

OSP(Organic Solderability Preservative)막을 갖는 패드가 형성된 기판을 제공하는 공정과, 다이를 기판에 전기적으로 연결되도록 실장하는 공정과, 기판에 실장된 다이를 몰딩 처리하는 공정과, 기판에 산화처리를 수행함으로써 기판에 산화막을 형성하는 고정에 의해 전자 디바이스를 제조한다. 이 때, 산화막을 형성하는 공정은, 몰딩 처리 공정 이후에 수행된다.

半导体存储装置及其制造方法

实施方式提供一种能够减少金属焊盘彼此的接合不良的半导体存储装置及其制造方法。一实施方式的半导体存储装置具备：阵列芯片，具有存储单元阵列；电路芯片，具有与存储单元电连接的电路；及金属焊盘，将阵列芯片与电路芯片接合。金属焊盘含有杂质。杂质的浓度在金属焊盘的厚度方向上，随着从表面向深度方向离开而变低。

焊料凸块形成用部件、焊料凸块形成用部件的制造方法及带焊料凸块的电极基板的制造方法

一种焊料凸块形成用部件，其具备：具有多个凹部的基体；以及凹部内的焊料粒子及流化剂，焊料粒子的平均粒径为1～35μm，C.V.值为20％以下。

集成电路封装互联结构及其与外部装置之间的互联方法

本申请公开了一种集成电路封装互联结构和方法。所述集成电路封装互联结构包括：内含稳压器的集成电路封装和一系列具有弹性的连接器。所述连接器附着于集成电路封装，当所述连接器被压缩时，集成电路封装通过连接器电耦接至外部装置，以使稳压器给装配在外部装置上的负载供电。所述集成电路封装互联结构和方法为电源供应器/电源供应模块提供了便捷的替换。

Semiconductor device package and method of fabricating the same

Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.

一种键合封装体及其制备方法

本发明涉及一种键合封装体及其制备方法，通过在第一半导体管芯的四周分别形成第一、第二、第三、第四键合部，并在第一半导体管芯中形成第一凹槽，所述第一凹槽露出硅通孔，并在相应的键合部上均形成多个凸柱，接着在第二半导体管芯的四周分别形成第五、第六、第七、第八键合部，并在相应的键合部上分别形成沟槽，接着将第二半导体管芯键合至所述第一半导体管芯，使得多个所述凸柱分别嵌入到相应的沟槽中。上述结构的设置，可以提高第一、第二半导体管芯的键合强度，有效防止其剥离倒塌，且为硅通孔的电连接提供安装空间，进而可以提高电连接的稳定性。

半导体存储装置及其制造方法

实施方式提供一种能够减少金属焊盘彼此的接合不良的半导体存储装置及其制造方法。一实施方式的半导体存储装置具备：阵列芯片，具有存储单元阵列；电路芯片，具有与存储单元电连接的电路；及金属焊盘，将阵列芯片与电路芯片接合。金属焊盘含有杂质。杂质的浓度在金属焊盘的厚度方向上，随着从表面向深度方向离开而变低。

半導體記憶裝置及其製造方法

實施形態提供一種可減少金屬焊墊彼此之接合不良之半導體記憶裝置及其製造方法。 一實施形態之半導體記憶裝置具備：陣列晶片，其具有記憶胞陣列；電路晶片，其具有與記憶胞電性連接之電路；及金屬焊墊，其將陣列晶片與電路晶片接合。金屬焊墊含有雜質。雜質之濃度於金屬焊墊之厚度方向上，隨著自表面向深度方向離開而變低。

Semiconductor storage device and manufacturing method of the same

A semiconductor storage device according to an embodiment includes: an array chip having a memory cell array; a circuit chip having a circuit electrically connected to a memory cell; and a metal pad bonding the array chip and the circuit chip together. The metal pad includes an impurity. A concentration of the impurity is lowered as separating in a depth direction apart from a surface in a thickness direction of the metal pad.

Chip package structure with metal-containing layer

A chip package structure is provided. The chip package structure includes a first wiring substrate including a substrate, a first pad, a second pad, and an insulating layer. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer includes tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad. The chip package structure includes a chip over the second surface of the substrate. The chip package structure includes a conductive bump between the second pad and the chip.

倒装方法

一种倒装方法，包括：提供半导体芯片和导电连接柱，所述导电连接柱具有相对的第一面和第二面；将所述导电连接柱固定在所述半导体芯片表面，第一面朝向所述半导体芯片；在所述导电连接柱的侧壁形成第一阻挡层，且所述第一阻挡层暴露出导电连接柱的第二面；提供载板；在所述载板的表面形成焊料柱；形成第二阻挡层，所述第二阻挡层位于焊料柱周围的载板表面；形成第一阻挡层和第二阻挡层后，将所述焊料柱与所述第二面接触，所述导电连接柱位于所述焊料柱上；将所述焊料柱与所述第二面接触后，进行回流焊，且使焊料柱形成焊料层。所述方法提高焊料层的质量，且避免相邻的焊料层连接在一起。

Electrical connection method for electronic element, and related apparatus thereof

Disclosed are an electrical connection method for an electronic element, and a backlight module, a display panel, and a display apparatus which include an electronic element to which the electrical connection method is applied. The electrical connection method comprises: providing a driving back plane, wherein the driving back plane comprises multiple contact electrodes; forming an anti-oxidation protection film on the contact electrodes; coating a position of the anti-oxidation protection film corresponding to each contact electrode with a binding material; and transferring multiple electronic elements to the positions of the corresponding contact electrodes, binding each electronic element to the corresponding contact electrode, and removing the anti-oxidation protection film at the position of each contact electrode before completing the binding of each electronic element to the corresponding contact electrode.

Chipset and manufacturing method thereof

The disclosure provides a chipset and a manufacturing method thereof. The chipset includes multiple logic cores and a memory chip. The logic cores respectively have a first device layer and a first substrate layer, and respectively include multiple first bonding elements and a first input/output circuit. The first bonding elements are provided in the first device layer. The first input/output circuit is provided in the first device layer. The memory chip has a second device layer and a second substrate layer, and includes second bonding elements and second input/output circuits. The second bonding elements are arranged in the second device layer. The second input/output circuits are arranged in the second device layer, and are respectively connected to the first input/output circuits of the logic cores.

半导体器件封装和制造其的方法

提供了一种半导体器件封装和/或制造该半导体器件封装的方法。该半导体器件封装可以包括：半导体器件，包括在半导体器件的上表面上的多个电极焊盘；引线框架，包括接合到所述多个电极焊盘的多个导电构件；以及模制件，在所述多个导电构件之间。

Semiconductor device package and method of fabricating the same

Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.

显示模组及其制作方法

本申请提供了一种显示模组及其制作方法。该显示模组的制作方法通过对显示面板上的多个第一绑定端子的表面进行粗糙化处理，并对覆晶薄膜或柔性电路板上的多个第二绑定端子的表面进行粗糙化处理。第一绑定端子和第二绑定端子均为金属材料，后续将多个第二绑定端子分别与多个第一绑定端子对位热压，通过振动发生器使第一绑定端子和第二绑定端子之间产生高频率摩擦，会使第一绑定端子和第二绑定端子之间粗糙的接触界面融化，而连接第一绑定端子和第二绑定端子，则第一绑定端子与第二绑定端子之间连接的力为金属共晶键合力，可以增加覆晶薄膜或柔性电路板与第一绑定端子之间的拉拔力，以提高覆晶薄膜或柔性电路板与第一绑定端子之间的连接稳定性。

电子元件的电连接方法及其相关装置

一种电子元件的电连接方法及包括应用该电连接方法的电子元件的背光模组、显示面板和显示装置，该电连接方法包括：提供一驱动背板(20)；驱动背板包括多个接触电极(201)；在接触电极之上形成防氧化保护膜(21)；在防氧化保护膜对应于各接触电极的位置处涂覆绑定材料(22)；将多个电子元件(23)转移到对应的接触电极的位置处，将各电子元件与对应的接触电极进行绑定，并且，在将各电子元件与对应的接触电极完成绑定之前，去除各接触电极位置处的防氧化保护膜。通过在接触电极之上形成防氧化保护膜，可以使接触电极在很长时间内不被氧化，确保接触电极与绑定材料之间能够良好的连接，并且可以省去化镍金工艺，简化工艺。

电子元件的电连接方法及其相关装置

一种电子元件的电连接方法及包括应用该电连接方法的电子元件的背光模组、显示面板和显示装置，该电连接方法包括：提供一驱动背板(20)；驱动背板包括多个接触电极(201)；在接触电极之上形成防氧化保护膜(21)；在防氧化保护膜对应于各接触电极的位置处涂覆绑定材料(22)；将多个电子元件(23)转移到对应的接触电极的位置处，将各电子元件与对应的接触电极进行绑定，并且，在将各电子元件与对应的接触电极完成绑定之前，去除各接触电极位置处的防氧化保护膜。通过在接触电极之上形成防氧化保护膜，可以使接触电极在很长时间内不被氧化，确保接触电极与绑定材料之间能够良好的连接，并且可以省去化镍金工艺，简化工艺。

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

A solution relating to electronic devices of flip-chip type is proposed. Particularly, an electronic device (200,300;400;700;800) of flip-chip type comprises at least one chip carrier (110;805) having a carrier surface (135;835), the carrier comprising one or more contact elements (140s,140p;740s,740p;840s,840p) of electrically conductive material on the carrier surface, at least one integrated circuit chip (105;705) having a chip surface (120;720), the chip comprising one or more terminals (125s,125p;725s,725p) of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material (150;750) soldering each terminal to the corresponding contact element, and restrain means (210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p) around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements (205s,205p;785s,785p;885s,885p) of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.

フリップチップ・タイプの電子デバイス、およびフリップチップ・タイプの電子デバイスを製造するための方法

【課題】フリップチップ・タイプの電子デバイスに関する解決策を提供する。【解決手段】詳細には、フリップチップ・タイプの電子デバイス（２００、３００、４００、７００、８００）が、キャリア面（１３５、８３５）を有する少なくとも１つのチップ・キャリア（１１０、８０５）であって、キャリア面上に導電性材料の１つまたは複数の接点要素（１４０ｓ、１４０ｐ、７４０ｓ、７４０ｐ、８４０ｓ、８４０ｐ）を備えるチップ・キャリア（１１０、８０５）と、チップ面（１２０、７２０）を有する少なくとも１つの集積回路チップ（１０５、７０５）であって、対応する接点要素に各々が向く、チップ面上の導電性材料の１つまたは複数の端子（１２５ｓ、１２５ｐ、７２５ｓ、７２５ｐ）を備える集積回路チップ（１０５、７０５）と、各端子を対応する接点要素にはんだ付けするはんだ材料（１５０、７５０）と、接点要素への端子のはんだ付けの期間にはんだ材料を制限するための接点要素の周りの制限手段（２１０ｓ、２１０ｐ、３１０、４１０ｓｌ、４１０ｓｄ、４１０ｐ、７９０ｓ、７９０ｐ、８９０ｓ、８９０ｐ）とを備え、キャリアが、端子からずれたチップ面に向くキャリア面上の熱的に伝導性の材料の１つまたは複数の熱放散要素（２０５ｓ、２０５ｐ、７８５ｓ、７８５ｐ、８８５ｓ、８８５ｐ）を備え、放散要素には何らはんだマスクがない。【選択図】図２

显示模组及其制作方法

本申请提供了一种显示模组及其制作方法。该显示模组的制作方法通过对显示面板上的多个第一绑定端子的表面进行粗糙化处理，并对覆晶薄膜或柔性电路板上的多个第二绑定端子的表面进行粗糙化处理。第一绑定端子和第二绑定端子均为金属材料，后续将多个第二绑定端子分别与多个第一绑定端子对位热压，通过振动发生器使第一绑定端子和第二绑定端子之间产生高频率摩擦，会使第一绑定端子和第二绑定端子之间粗糙的接触界面融化，而连接第一绑定端子和第二绑定端子，则第一绑定端子与第二绑定端子之间连接的力为金属共晶键合力，可以增加覆晶薄膜或柔性电路板与第一绑定端子之间的拉拔力，以提高覆晶薄膜或柔性电路板与第一绑定端子之间的连接稳定性。

땜납 범프 형성용 부재, 땜납 범프 형성용 부재의 제조 방법, 및 땜납 범프 부착 전극 기판의 제조 방법

복수의 오목부를 갖는 기체와, 오목부 내에 땜납 입자 및 유동화제를 구비하고, 땜납 입자의 평균 입자경이 1~35μm, C.V.값이 20% 이하인, 땜납 범프 형성용 부재.

Interconnection structure for integrated circuit package

An interconnection structure for IC package onto the external device is discussed. The IC package has a voltage regulator contained therein; and the external device has a load assembled thereupon. A plurality of connection devices with elasticity are attached to the IC package, so that when a perpendicular force is applied to the connection devices, the IC package is electrically coupled to the external device to provide power supply to the load with ease replacement.

接合装置

一种接合装置，具有：清洗室；清洗单元，在该清洗室内在减压情况下对所说金属接合部的接合面照射能量波；接合单元，在大气中将从所说清洗室内取出的被接合物的金属接合部彼此接合；输送单元，将至少就一方被接合物而言在前的被接合物和后续的被接合物实质上同时至少沿着向所说清洗室内送入的方向和从清洗室内送出的方向进行输送。在将清洗后的被接合物取出至大气中进行接合时，特别是围绕清洗室进行的被接合物的送入和送出以及传递能够圆滑且以较短时间完成，能够以高处理量批量生产既定的接合制品。其结果，可缩短整个接合工序的生产节拍时间、降低接合工序所需要的成本。

封装结构及其制法

本发明涉及一种封装结构及其制法，包括将多个具有导电柱的硅中介板相互堆叠，且于任两硅中介板之间以覆晶方式配置有至少一电子元件，使该电子元件位于两硅中介板所夹置的空间中，以经由低成本的TSV制程制作该硅中介板，且以技术成熟性高的覆晶方式进行该些硅中介板与电子元件的堆叠封装，以利于提升良率，同时大幅降低该封装结构的制作成本。

半导体结构及其形成方法

一种半导体结构及其形成方法，所述半导体结构的形成方法，提供半导体芯片和基板后；在所述基板上形成覆盖所述金属焊盘和基板表面的第一覆膜，所述第一覆膜中形成有若干上窄下宽的开口，每一个上窄下宽的开口的底部暴露出的相应的金属焊盘的表面；将所述半导体芯片倒装在所述基板上，使每一个所述金属柱上的焊料凸块位于对应的上窄下宽的开口内，并使得所述焊料凸块填充满所述上窄下宽的开口。由于第一覆膜中形成有若干上窄下宽的开口，从而在将半导体芯片倒装在基板上时能防止半导体芯片的偏移或倾斜，从而防止焊接不良的产生。

集成电路封装互联结构及其与外部装置之间的互联方法

本申请公开了一种集成电路封装互联结构和方法。所述集成电路封装互联结构包括：内含稳压器的集成电路封装和一系列具有弹性的连接器。所述连接器附着于集成电路封装，当所述连接器被压缩时，集成电路封装通过连接器电耦接至外部装置，以使稳压器给装配在外部装置上的负载供电。所述集成电路封装互联结构和方法为电源供应器/电源供应模块提供了便捷的替换。

包含焊料芯连接器的设备及其制造方法

本公开涉及一种包含焊料芯连接器的设备及其制造方法。本文中公开了包含连续芯连接器的半导体装置以及相关联的系统和方法。所述连续芯连接器各自包含围绕内芯的外围壁，所述内芯配置成使用均匀材料提供电路径。

焊料凸块形成用部件、焊料凸块形成用部件的制造方法及带焊料凸块的电极基板的制造方法

一种焊料凸块形成用部件，其具备：具有多个凹部的基体；以及凹部内的焊料粒子及流化剂，焊料粒子的平均粒径为1～35μm，C.V.值为20％以下。

半导体器件封装和制造其的方法

提供了一种半导体器件封装和/或制造该半导体器件封装的方法。该半导体器件封装可以包括：半导体器件，包括在半导体器件的上表面上的多个电极焊盘；引线框架，包括接合到所述多个电极焊盘的多个导电构件；以及模制件，在所述多个导电构件之间。

半导体封装方法及半导体结构

本申请提出一种半导体封装方法及半导体结构。半导体封装方法包括：提供基底；在所述基底上形成金属焊盘，其中所述金属焊盘的侧壁与所述基底之间存在间隙；将多个所述基底的所述金属焊盘相连。本申请提出的半导体封装方法能够使间隙的形成工艺具备更佳的可控性，减少不同基底之间的金属焊盘在接合过程中因为热膨胀造成周围结构的损害，实现更优的封装效果。

显示模组及其制作方法

本申请提供了一种显示模组及其制作方法。该显示模组的制作方法通过对显示面板上的多个第一绑定端子的表面进行粗糙化处理，并对覆晶薄膜或柔性电路板上的多个第二绑定端子的表面进行粗糙化处理。第一绑定端子和第二绑定端子均为金属材料，后续将多个第二绑定端子分别与多个第一绑定端子对位热压，通过振动发生器使第一绑定端子和第二绑定端子之间产生高频率摩擦，会使第一绑定端子和第二绑定端子之间粗糙的接触界面融化，而连接第一绑定端子和第二绑定端子，则第一绑定端子与第二绑定端子之间连接的力为金属共晶键合力，可以增加覆晶薄膜或柔性电路板与第一绑定端子之间的拉拔力，以提高覆晶薄膜或柔性电路板与第一绑定端子之间的连接稳定性。

电子元件的电连接方法及其相关装置

一种电子元件的电连接方法及包括应用该电连接方法的电子元件的背光模组、显示面板和显示装置，该电连接方法包括：提供一驱动背板(20)；驱动背板包括多个接触电极(201)；在接触电极之上形成防氧化保护膜(21)；在防氧化保护膜对应于各接触电极的位置处涂覆绑定材料(22)；将多个电子元件(23)转移到对应的接触电极的位置处，将各电子元件与对应的接触电极进行绑定，并且，在将各电子元件与对应的接触电极完成绑定之前，去除各接触电极位置处的防氧化保护膜。通过在接触电极之上形成防氧化保护膜，可以使接触电极在很长时间内不被氧化，确保接触电极与绑定材料之间能够良好的连接，并且可以省去化镍金工艺，简化工艺。

一种键合封装体及其制备方法

本发明涉及一种键合封装体及其制备方法，通过在第一半导体管芯的四周分别形成第一、第二、第三、第四键合部，并在第一半导体管芯中形成第一凹槽，所述第一凹槽露出硅通孔，并在相应的键合部上均形成多个凸柱，接着在第二半导体管芯的四周分别形成第五、第六、第七、第八键合部，并在相应的键合部上分别形成沟槽，接着将第二半导体管芯键合至所述第一半导体管芯，使得多个所述凸柱分别嵌入到相应的沟槽中。上述结构的设置，可以提高第一、第二半导体管芯的键合强度，有效防止其剥离倒塌，且为硅通孔的电连接提供安装空间，进而可以提高电连接的稳定性。

一种半导体堆叠封装结构及其制备方法

本发明涉及一种半导体堆叠封装结构及其制备方法，通过在所述第一半导体芯片的四个侧面分别形成多个平行排列的第一凸起，并在每个所述第一凸起的上表面均形成一第一键合槽。并在所述第二半导体芯片的四个侧面分别形成多个平行排列的第二凸起，接着在每个所述第二凸起的上表面均形成一第一键合凸起，将所述第二半导体芯片接合至所述第一半导体芯片，使得所述第一键合凸起嵌入到相应的所述第一键合槽。上述结构的设置可以提高第一半导体芯片和第二半导体芯片的键合强度，进而可以提高半导体堆叠封装结构的稳固性。

半导体存储装置及其制造方法

实施方式提供一种能够减少金属焊盘彼此的接合不良的半导体存储装置及其制造方法。一实施方式的半导体存储装置具备：阵列芯片，具有存储单元阵列；电路芯片，具有与存储单元电连接的电路；及金属焊盘，将阵列芯片与电路芯片接合。金属焊盘含有杂质。杂质的浓度在金属焊盘的厚度方向上，随着从表面向深度方向离开而变低。

芯片组及其制造方法

本发明提供一种芯片组及其制造方法。芯片组包括多个逻辑核心以及存储器芯片。多个逻辑核心分别具有第一装置层以及第一基板层，并且分别包括多个第一键合组件以及第一输入输出电路。多个第一键合组件设置在第一装置层。第一输入输出电路设置在第一装置层。存储器芯片具有第二装置层以及第二基板层，并且包括多个第二键合组件以及多个第二输入输出电路。多个第二键合组件设置在第二装置层。多个第二输入输出电路设置在第二装置层，且分别连接多个逻辑核心的第一输入输出电路。多个逻辑核心的多个第一键合组件的多个第一键合面分别与存储器芯片的多个第二键合组件的多个第二键合面以接垫对接垫的方式直接接合。

一种用于三维芯片堆叠的低应力表面钝化结构

本发明公开了一种用于三维芯片堆叠的低应力表面钝化结构，包括：芯片主体；介质层，所述介质层设置在所述芯片主体的上表面；金属层，所述金属层电连接至所述芯片主体，贯穿并露出所述介质层；凸点，所述凸点设置在露出所述介质层的所述金属层的上方；以及表面钝化层，所述表面钝化层成分立状设置在所述介质层上方。

芯片封装结构及其形成方法

提供芯片封装结构及其形成方法。此方法包含提供布线基底。此方法包含在第一焊垫上方依序形成含镍层和含金层。此方法包含形成导电保护层覆盖含镍层上方的含金层。此方法包含经由导电凸块和围绕导电凸块的助焊剂层将芯片接合至布线基底。导电凸块在第二焊垫和芯片之间。此方法包含在导电保护层覆盖含镍层的同时移除助焊剂层。

宽带射频板级互连集成方法、结构及装置

本发明公开了一种宽带射频板级互连集成方法、结构及装置，包括：步骤1，制作金属屏蔽结构；步骤2，在射频单元封装基板表面制作图形化焊盘，将所述金属屏蔽结构焊接至射频单元封装基板对应的焊盘图形区域，并预置焊点；步骤3，在射频母板表面制作图形化焊盘，该图形化焊盘与射频单元封装基板上的焊盘图形对应；步骤4，将载有金属屏蔽结构、焊点的所述射频单元封装基板与所述射频母板焊接，完成板级互连等；本发明完成宽带射频单元封装基板与射频母板的板级互连，可以改善驻波、降低传输损耗，缓解热失配，提升板级互连可靠性，满足射频、数字、接地等信号的灵活传输。

功率器件埋入式基板封装结构及制备方法

本发明公开了功率器件埋入式基板封装结构，其特征在于，包括功率半导体管芯和基板，所述功率半导体管芯通过流胶层压在所述基板上；在所述流胶内开设有若干盲孔和若干通孔，并对这些盲孔和通孔金属化，使得所述功率半导体管芯的电极与外层线路铜箔连接；对所述外层线路铜箔进行图形化处理后，进行植球和切割，形成功率器件埋入式基板封装结构。本发明还公开了上述率器件埋入式基板封装结构的制备方法。本发明解决了现有技术所存在的技术问题。本发明采用激光开孔在功率半导体管芯中的上电极的导电柱上作业，加工的冗余要比之前压焊盘Al层大很多，能极大地提高加工良率；另外，压焊盘Al层同导电柱联接非常好，这也有助于可靠性的提高。

半导体键合封装方法

本申请公开一种半导体键合封装方法，包括：提供基板，所述基板具有相背的第一面和第二面，所述第一面上设有多个金属凸块，所述第二面上设有多个焊料凸块；在所述第一面上形成图案化的第一光刻胶层，所述第一光刻胶层具有裸露出所述金属凸块顶端的第一开口部；提供芯片，在所述第一光刻胶层上倒装芯片，通过热压键合法将所述芯片的功能凸点与所述基板的金属凸块键合连接。具有第一开口部的第一光刻胶层可有效避免芯片的功能凸点与功能凸点之间出现焊料桥接的问题，避免芯片底部的填充出现空洞问题，不会出现多胶使芯片背部被粘污的问题；有效提高良品率和封装效率。

重布线层的制造方法、封装方法及半导体结构

本发明提供了一种重布线层的制造方法、封装方法及半导体结构，包括在基底上形成第一介质层，然后在所述第一介质层中形成第一开口和第二开口，在第一开口和第二开口分别形成顶层金属及支撑结构，接着形成第二介质层，并在所述第二介质层中形成第三开口和第四开口，再形成重布线层。由于第二开口形成有支撑结构，在后续的压焊工艺中，所述支撑结构可以缓解焊丝对第二介质层的应力，避免了在封装工艺中第二介质层破裂，导致封装产生缺陷，提高了产品的良率和可靠性，并且所述第二开口可以设置在基底上的任意位置(不局限于边缘部分)，使压焊形式的封装工艺也可以进行自由布线。

电子封装件的制法

一种电子封装件的制法，用于将电子元件借由导电凸块及形成于该导电凸块上的焊锡端结合于承载结构上，其中，该焊锡端不经回焊作业而接触该承载结构，使该导电凸块上能形成足量的焊锡端，以避免该焊锡端发生破裂或焊锡崩塌的问题。

一种半导体堆叠封装结构及其制备方法

本发明涉及一种半导体堆叠封装结构及其制备方法，通过在所述第一半导体芯片的四个侧面分别形成多个平行排列的第一凸起，并在每个所述第一凸起的上表面均形成一第一键合槽。并在所述第二半导体芯片的四个侧面分别形成多个平行排列的第二凸起，接着在每个所述第二凸起的上表面均形成一第一键合凸起，将所述第二半导体芯片接合至所述第一半导体芯片，使得所述第一键合凸起嵌入到相应的所述第一键合槽。上述结构的设置可以提高第一半导体芯片和第二半导体芯片的键合强度，进而可以提高半导体堆叠封装结构的稳固性。

Protecting flip-chip package using pre-applied fillet

A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.

Chip packaging method and chip package using hydrophobic surface

A chip packaging method using a hydrophobic surface includes forming superhydrophobic surfaces forming hydrophilic surfaces on predetermined positions of the superhydrophobic surfaces formed on the one of a first chip or the first board and the one of a second chip or a second board, respectively, generating liquid metal balls on the hydrophilic surfaces formed on the one of the first chip or the first board and the one of the second chip or the second board, respectively, and packaging the one of the first chip or the first board and the one of the second chip or the second board by combing the liquid metal ball of the one of the first chip or the first board and the liquid metal ball of the one of the second chip or the second board with each other.