Wafer Backside Interconnect Structure Connected to TSVs

An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line. 1. A method for forming an integrated circuit structure , the method comprising:forming a conductive via in a semiconductor substrate having an active device at a front surface, the semiconductor substrate further having a back surface opposite the front surface;patterning an opening extending from the back surface of the semiconductor substrate into the semiconductor substrate;forming a first metal feature in the opening and contacting the conductive via; andforming a bump overlying and electrically connected to the first metal feature relative the back surface of the semiconductor substrate.2. The method of claim 1 , wherein patterning the opening comprises exposing the conductive via claim 1 , wherein the opening has a greater horizontal dimension than the conductive via claim 1 , and wherein forming the first metal feature comprises:forming a dielectric isolation layer on sidewalls and a lateral surface of the opening;forming a conductive barrier layer on the dielectric isolation layer; andfilling remaining portions of the opening with a metal.3. The method of claim 2 , further comprising claim 2 , prior to forming the conductive barrier layer claim 2 , removing a portion of the dielectric isolation layer contacting the conductive via.4. The method of claim 1 , wherein patterning the opening comprises recessing the conductive via so that the back surface of the semiconductor substrate is higher than a surface of the conductive via claim 1 , and wherein the opening ...

FAN-OUT POP STACKING PROCESS

Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations. 1. A method of forming a semiconductor device package comprising:forming an array of trenches partially through a fan-out substrate that includes an array of embedded bottom die such that the trenches do not extend completely through the fan out substrate; andbonding an array of top packages to the fan-out substrate after forming the array of trenches partially through the fan-out substrate, wherein the array of top packages are directly over the array of embedded bottom die.2. The method of claim 1 , further comprising:forming the array of trenches in an active side of the fan-out substrate; andprior to bonding the array of top packages to the fan-out substrate, mounting the active side of the fan-out substrate to a temporary adhesive layer and removing a carrier substrate from the fan-out substrate; andbonding the array of top packages to a surface of the fan-out substrate opposite the active side of the fan-out substrate.3. The method of claim 2 , further comprising applying an underfill material to the array of top packages.4. The method of claim 2 , further comprising dispensing a plurality of laterally separate locations of a thermal interface material onto the array of embedded bottom die prior to bonding the array of top packages to the fan-out substrate.5. The method of claim 4 , further comprising applying an underfill material to the array of ...

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

Method and apparatus for die-to-die pad contact

A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die. The second semiconductor die comprises a first and second side, and includes at least a second contact pad located on the first side of the second semiconductor die, wherein the first semiconductor die is stacked on the second semiconductor die and wherein the first side of the first semiconductor die faces the first side of the second semiconductor die. At least one voltage-guided conductive filament is created between the first contact pad and the second contact pad.

Bump Structure for Yield Improvement

A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components. 1. A method of forming a device , the method comprising:forming a first non-flat portion on a first bump;covering the first bump with a first material;forming a second non-flat portion on a second bump, the first non-flat portion having a same number of recesses as the second non-flat portion has projections;covering the second non-flat portion with a second material;aligning the recesses of the first non-flat portion with the projections of the second non-flat portion; andreflowing the first material and the second material, thereby forming a bond between the first non-flat portion and the second non-flat portion.2. The method of claim 1 , wherein the first material is solder and the second material is electroless nickel electroless palladium immersion gold.3. The method of claim 1 , wherein the second non-flat portion comprises a flat shoulder along a periphery.4. The method of claim 1 , wherein forming the second non-flat portion on the second bump comprises:forming a first patterned mask over a passivation layer, the passivation layer having a first opening, the first opening exposing a contact pad, the first patterned mask having a second opening, the contact pad being exposed in the second opening;forming a first conductive element in the second opening, the first conductive element extending above an upper surface of the passivation layer;removing the first patterned mask;forming a second patterned mask over the passivation layer, the second patterned ...

Systems and methods for package on package through mold interconnects

Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.

System for Low-Force Thermocompression Bonding

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1. A system for bonding microelectronic elements , comprising:a bonding platform for flip-chip bonding, configured to bond elements by compressing them together, without any conductive liquid phase material, thereby deforming contacting metallizations by no more than 40% of their initial height;an atmospheric plasma applicator, integrated into said bonding platform, which is configured to apply reducing and passivating agents to said contacting metallizations on each said element, by use of plasma-activated radical-enriched gas flow at substantially atmospheric pressure;wherein said reducing and passivating agents reduce native oxides from said contacting metallizations and passivate said contacting metallizations against re-oxidation prior to bonding said element;wherein elements are loaded into said bonding platform and aligned for bonding, said atmospheric plasma applicator applies reducing and passivation agents to the contacting metallizations on said elements, ...

Thermocompression Bonding Using Metastable Gas Atoms

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1. A method for bonding microelectronic elements , comprising the steps of:a) directing plasma-activated radical-enriched gas flow at substantially atmospheric pressure both to first contacting metallizations on a first element and also to second contacting metallizations on a second element, both to reduce native oxides from said contacting metallizations and also to passivate said contacting metallizations against re-oxidation;b) compressing said first and second contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;c) repeating said steps a) and b), to thereby bond contacting metallizations on subsequent elements to contacting metallizations on the previous element;wherein said plasma-activated radical-enriched gas flow includes a population of helium metastable states.2. The method of claim 1 , further comprising the step of bonding an additional element to the previous elements ...

Thermocompression Bonding with Passivated Indium-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Thermocompression Bonding with Passivated Copper-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Thermocompression Bonding with Passivated Gold Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Thermocompression Bonding with Passivated Silver-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Thermocompression Bonding with Passivated Nickel-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Proximity coupling of interconnect packaging systems and methods

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

Proximity coupling of interconnect packaging systems and methods

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

NANOWIRES FOR PILLAR INTERCONNECTS

An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate. 1. A method of forming a semiconductor structure comprising:forming a plurality of first conductive pillars on a first substrate;forming a plurality of conductive nanowires only on a first surface of the plurality of first conductive pillars, wherein the first surface is substantially parallel to a top surface of the first substrate, and wherein a material of the plurality of conductive nanowires is the same as a material of the first conductive pillars;forming a plurality of second conductive pillars on a second substrate;forming a solder bump on a second surface of the plurality of second conductive pillars; andforming an electrical connection between the first pillar and the second pillar by joining the plurality of conductive nanowires with the solder bump.2. The method of claim 1 , wherein forming a plurality of first conductive pillars comprises:forming a masking layer on a masked region of a first substrate, and wherein an unmasked region of the first substrate comprises a plurality of electrical connections;forming a conductive material in the unmasked region, forming the plurality of first conductive pillars on the first substrate; andremoving the masking layer.3. The method of claim 1 , wherein forming a plurality of conductive nanowires comprises:forming a porous layer on a surface of the plurality of first conductive pillars, wherein the porous layer comprises a plurality of pores extending from an exposed surface of the porous layer to the ...

Semiconductor package and fabrication method thereof

A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.

Thermocompression Bonding Using Metastable Gas Atoms

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Thermocompression Bonding with Passivated Nickel-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Thermocompression Bonding with Passivated Tin-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1195-. (canceled)196. A method of bonding microelectronic elements , comprising the steps of:a) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from contact metallizations on a first element; and to passivate said contact metallizations against re-oxidation;b) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from tin-based bumps on a second element; and to passivate said tin-based bumps against re-oxidation;c) compressing said tin-based bumps and said contact metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;d) repeating said steps a), b), and c), to thereby bond the tin-based bumps on subsequent elements to the contact metallizations on the previous element;wherein said tin-based bumps are comprised of at least 90% atomic tin.197. A method of bonding ...

Thermocompression Bonding with Passivated Copper-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1217-. (canceled)218. A method for bonding microelectronic elements , comprising the steps of:a) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from the surfaces of first copper-based contacting metallizations on a first side of a first element; and to passivate the surfaces of said first copper-based contact metallizations against re-oxidation;b) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from the surfaces of second copper-based contacting metallizations on a second element; and to passivate the surfaces of said second copper-based contacting metallizations against re-oxidation;c) compressing said first and second copper-based contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;d) repeating said steps a), b), and c), to thereby bond copper-based ...

Thermocompression Bonding with Passivated Gold Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1229-. (canceled)230. A method for bonding microelectronic elements , comprising the steps of:a) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from first gold contacting metallizations on a first element; and to passivate said first gold contacting metallizations against re-oxidation;b) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from second gold contacting metallizations on a first side of a second element; and to passivate said second gold contacting metallizations against re-oxidation;c) compressing said first and second gold contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;d) repeating said steps a), b), and c), to thereby bond gold contacting metallizations on subsequent elements to gold contacting metallizations on the previous element.231. ...

THERMOCOMPRESSION BONDING WITH PASSIVATED SILVER-BASED CONTACTING METAL

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 123-. (canceled)24. A method for bonding microelectronic elements , comprising the steps of:a) directing plasma-activated radical-enriched gas flow at substantially atmospheric pressure both to first contacting metallizations on a first element and also to second contacting metallizations on a second element, both to reduce native oxides from said contacting metallizations and also to passivate said contacting metallizations against re-oxidation;b) compressing said first and second contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;c) repeating said steps a) and b), to thereby bond contacting metallizations on subsequent elements to contacting metallizations on the previous element;wherein said first contacting metallizations are made essentially of silver.2546-. (canceled)47. A method for bonding microelectronic elements , comprising the steps of:a) using plasma-activated ...

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A method of manufacturing a multi-layer wafer is provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

Wafer Backside Interconnect Structure Connected to TSVs

An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

Ball Height Control in Bonding Process

A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component. 1. A method comprising:aligning a first package component to a second package component, wherein a solder region in the first package component is aligned to, and is in contact with, a surface conductive feature in the second package component; andreflowing the solder region to bond the first package component to the second package component, wherein during the reflow, a ball-height control stud is located between, and is in contact with, the first package component and the second package component to define a standoff distance between the first package component and the second package component.2. The method of further comprising forming the ball-height control stud and a surface dielectric layer of the second package component in a common process claim 1 , wherein the ball-height control stud and the surface dielectric layer are formed of a same dielectric material claim 1 , and no distinguishable interface is between the ball-height control stud and the surface dielectric layer.3. The method of claim 2 , wherein the ball-height control stud forms a step with a top surface and an edge of the surface dielectric layer.4. The method of claim 2 , wherein the common process comprises stencil stamping.5. The method of claim 1 , wherein the ball-height control stud is pre-formed as an integrated part of the second package component before the aligning.6. The method of further comprising claim 1 , before the aligning claim 1 , adhering the ball-height control stud to the second package component.7. The method of claim 1 , wherein the first package ...

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE

An integrated circuit package system includes: providing a mountable structure having a contact pad and an inner pad; mounting an integrated circuit device having a linear through channel over the mountable structure with the linear through channel traversing between an integrated circuit device first side and an integrated circuit device second side; and connecting the linear through channel exposed on the integrated circuit device second side to the inner pad. 1. An integrated circuit package system comprising:providing a mountable structure having a contact pad and an inner pad;mounting an integrated circuit device having a linear through channel over the mountable structure with the linear through channel traversing between an integrated circuit device first side and an integrated circuit device second side; andconnecting the linear through channel exposed on the integrated circuit device second side to the inner pad.2. The system as claimed in wherein providing the mountable structure includes providing an insulation layer or a semiconductor die3. The system as claimed in further comprising forming the integrated circuit device includes:providing a first integrated circuit; andmounting a second integrated circuit over the first integrated circuit.4. The system as claimed in further comprising:mounting the mountable structure over a carrier; andconnecting the contact pad and the carrier; andencapsulating the carrier and the mountable structure with the linear through channel exposed.5. The system as claimed in further comprising forming an encapsulation over the mountable structure with the linear through channel exposed and with the encapsulation planar with the integrated circuit device first side.6. An integrated circuit package system comprising:providing a mountable structure having a contact pad and an inner pad;mounting an integrated circuit device having a linear through channel over the mountable structure with the contact pad exposed and with the ...

MICRO-LED MODULE AND METHOD FOR FABRICATING THE SAME

A method for fabricating a micro-LED module is disclosed. The method includes: preparing a micro-LED including a plurality of electrode pads and a plurality of LED cells; preparing a submount substrate including a plurality of electrodes corresponding to the plurality of electrode pads; and flip-bonding the micro-LED to the submount substrate through a plurality of solders located between the plurality of electrode pads and the plurality of electrodes. The flip-bonding includes heating the plurality of solders by a laser. 1. A method for flip-bonding a micro-LED to a submount substrate , comprising:forming a plurality of LED cells on an LED substrate to prepare the micro-LED;preparing the submount substrate having a coefficient of thermal expansion different from that of the micro-LED; andflip-bonding the micro-LED to the submount substrate through solders located therebetween,wherein the submount substrate and the micro-LED are controlled to different temperatures corresponding to different heating-cooling curves during the flip-bonding such that a difference in strain caused by the different coefficients of thermal expansion of the LED substrate and the submount substrate is suppressed.2. The method according to claim 1 , wherein the submount substrate and the micro-LED are controlled to different temperatures in a heating zone claim 1 , a holding zone claim 1 , and a cooling zone during the flip-bonding.3. The method according to claim 2 , wherein claim 2 , in the heating zone claim 2 , the LED substrate is heated from room temperature to a first holding temperature along a first heating slope and the submount substrate is heated from room temperature to a second holding temperature higher than the first holding temperature along a second heating slope steeper than the first heating slope.4. The method according to claim 2 , wherein claim 2 , in the holding zone claim 2 , the LED substrate is maintained at the first holding temperature for an indicated time and ...

Ball Height Control in Bonding Process

A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.

PROXIMITY COUPLING INTERCONNECT PACKAGING SYSTEMS AND METHODS

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad. 1. A method for manufacturing a semiconductor package assembly , the method comprising:disposing a first semiconductor die adjacent to a substrate having bond pads, the first semiconductor die having a first coupling face that faces away from the substrate;disposing a second semiconductor die adjacent to the substrate and spaced laterally apart from the first semiconductor die, the second semiconductor die having a second coupling face that faces away from the substrate; andstacking a third semiconductor die on the first semiconductor die and the second semiconductor die, the third semiconductor die having a third coupling face and bond pads at the third coupling face, the third coupling face facing the first coupling face and the second coupling face;wherein stacking the third semiconductor die includes aligning a third conductive pad on the third coupling face with a first conductive pad on the first coupling face to form a first proximity coupling interconnect, wherein the ...

PROXIMITY COUPLING INTERCONNECT PACKAGING SYSTEMS AND METHODS

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad. 1. A semiconductor package assembly comprising:a substrate having bond pads;a first semiconductor die disposed adjacent the substrate, the first semiconductor die having a first coupling face that faces away from the substrate;a second semiconductor die disposed adjacent the substrate and spaced laterally apart from the first semiconductor die, the second semiconductor die having a second coupling face that faces away from the substrate;a third semiconductor die having a third coupling face and bond pads at the third coupling face, the third semiconductor die stacked on the first semiconductor die and the second semiconductor die such that the third coupling face faces the first coupling face and the second coupling face;a first proximity coupling interconnect between the first semiconductor die and the third semiconductor die, the first proximity coupling interconnect comprising a first conductive pad on the first coupling face and a third conductive pad on the third coupling ...

Micro-LED chip, preparation method thereof and display device

本申请公开一种Micro‑LED芯片及其制备方法、显示装置，该Micro‑LED芯片包括：驱动背板和发光芯片，驱动背板和发光芯片均包括电极，其中：驱动背板的电极上方形成有凹槽，凹槽的底部露出驱动背板的电极；凹槽内填充有导电材料，驱动背板的电极通过凹槽内的导电材料与发光芯片的电极连接，凹槽内的导电材料由导电材料对应的导电墨水固化得到，导电墨水通过喷墨打印的方法打印到凹槽内。发光芯片的电极通过固化后的导电墨水与驱动背板的电极连接，相较于直接将发光芯片的电极与驱动背板的电极焊接而言，由于电极与固化后的导电墨水之间的接触性较好，因此，可以有效改善发光芯片的电极与驱动背板的电极之间的接触性能，提高电极之间连接的可靠性。

??? for fine pitch solder ball and flip-chip package method using the UBM

미세 솔더볼 구현을 위한 UBM(Under Bump Metal) 및 이를 이용한 플립칩 패키지 방법이 개시된다. 본 발명에 의한 미세 솔더볼 구현을 위한 UBM은, 제1 기판 및 제2 기판 상에 형성된 대응되는 적어도 하나 이상의 제1 및 제2 전극단자를 플립칩 본딩시 이용되는 미세 솔더볼 구현을 위한 UBM에 있어서, 제1 전극단자 및 솔더볼 사이에 배치되어 전기적으로 연결되며, 돌출부의 주변에 측면이 소정 경사를 이루는 함몰부를 구비하는 제1 기판의 돌출부에 형성되는 금속막 및 돌출부에 접하는 경사 측면 위에 형성된 금속막을 포함한다. 본 발명에 의하면, 프립칩 패키지에 있어서 UBM를 양각 패턴 구조로 구성함으로서 미세 솔더볼 구현할 수 있을 뿐만아니라 패키지의 신뢰성을 높일 수 있다. An under bump metal (UBM) and a flip chip package method using the same are disclosed. In the UBM for implementing the fine solder ball according to the present invention, in the UBM for implementing the fine solder ball used for flip chip bonding at least one or more first and second electrode terminals corresponding to the first substrate and the second substrate, A metal film formed between the first electrode terminal and the solder ball and electrically connected to the first electrode terminal and the solder ball, the metal film formed on the protruding portion of the first substrate having a depression having a predetermined inclined side surface around the protruding portion, and a metal film formed on the inclined side contacting the protruding portion; do. According to the present invention, by configuring the UBM in an embossed pattern structure in the chip package, it is possible not only to implement fine solder balls but also to increase the reliability of the package. 마이크로 접합, 플립칩 본딩, 솔더볼, UBM Micro Bonding, Flip Chip Bonding, Solder Balls, UBM

Wafer Backside Interconnect Structure Connected To TSVs

본 발명의 일 실시예에 따른, 집적 회로 구조는 앞 표면 및 뒤 표면; 반도체 기판을 관통하는 도전성 비아; 및 반도체 기판 후면의 금속 구조를 가지는 반도체 기판을 포함한다. 금속 구조는 도전성 비아에 오버라잉되어 접촉하는 금속 패드 및 도전성 비아 상의 금속 라인을 포함한다. 금속 라인은 듀얼 다마신(dual damascene) 구조를 포함한다. 집적회로 구조는 금속 라인을 오버라잉하는 범프(bump)를 더 포함한다. According to one embodiment of the invention, an integrated circuit structure comprises a front surface and a back surface; Conductive vias penetrating the semiconductor substrate; And a semiconductor substrate having a metal structure on the back side of the semiconductor substrate. The metal structure includes metal pads overlying and contacting the conductive vias and metal lines on the conductive vias. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

ELECTRIC CONNECTORS WITH HIGH DENSITY

Semiconductor device manufacturing method and semiconductor device

Semiconductor device with at least one voltage-guided conductive filament

A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die. The second semiconductor die comprises a first and second side, and includes at least a second contact pad located on the first side of the second semiconductor die, wherein the first semiconductor die is stacked on the second semiconductor die and wherein the first side of the first semiconductor die faces the first side of the second semiconductor die. At least one voltage-guided conductive filament is created between the first contact pad and the second contact pad.

METHOD OF ASSEMBLING TWO ELECTRONIC COMPONENTS OF FLIP-CHIP TYPE BY UV-COATING, ASSEMBLY OBTAINED

L'invention concerne un procédé d'assemblage de type Flip-Chip, entre un premier (1) et un deuxième (2) composants comportant chacun des plots de connexion (11, 21) sur une de leurs faces, dites faces d'assemblage, selon lequel on reporte les composants l'un sur l'autre par leurs faces d'assemblage de sorte à réaliser des interconnexions électriques entre les plots du premier et ceux du deuxième composant. Selon l'invention, on réalise une transformation de l'oxyde de cuivre en cuivre par recuit UV, très localement dans l'espacement entre composants au moins autour des zones au droit des plots de connexion. Le procédé selon l'invention peut être utilisé pour n'importe quel composant transparent aux UV, y compris pour des substrats en matière plastique tels que des substrats en PEN ou en PET. The invention relates to a method of assembly of Flip-Chip type, between a first (1) and a second (2) components each having connection pads (11, 21) on one of their faces, said assembly faces , according to which the components are reported to one another by their assembly faces so as to achieve electrical interconnections between the pads of the first and those of the second component. According to the invention, a conversion of copper oxide to copper is carried out by UV annealing, very locally in the spacing between components at least around the zones to the right of the connection pads. The process according to the invention can be used for any UV-transparent component, including for plastic substrates such as PEN or PET substrates.

Semiconductor device and method for producing semiconductor device

本发明提供一种在两个半导体晶片的接合时使接合材料不易在水平方向上扩展的半导体装置的制造方法以及半导体装置。所述半导体装置具备互补型金属氧化膜半导体晶片与另外的半导体晶片，所述半导体装置的制作方法包括开口部形成工序、导通孔形成工序、配置工序、接合工序。在开口部形成工序中，在遍及作为互补型金属氧化膜半导体晶片的一部分的第一部分和作为半导体晶片的一部分的第二部分中的至少一个部分的内侧及外侧的范围内形成非贯穿的开口部。在导通孔形成工序中，在第一部分的内侧形成导通孔。在配置工序中，将第一接合材料配置在导通孔内及第一部分上，将第二接合材料配置在第二部分上。在接合工序中，将第一接合材料与第二接合材料接合。

Compressive bump-and-socket interconnection scheme for integrated circuits

A electrically interconnected assembly includes an electronic component, such as an integrated circuit chip, having a first pattern of contact sites and includes a substrate having a second pattern of contact sites corresponding to the first pattern. The electronic component is demountably connected to the substrate by a bump-and-socket arrangement at each pair of contact sites. One of the contact sites has a raised bump that is received within a depressed area of the other contact site. The raised bumps are pressed into the depressed areas, forming a ring of contact to electrically and mechanically connect the electronic component to the substrate. Preferably, the depressed areas are formed in a compliant material that allows some deformation but not so much as to allow the raised bumps to bottom out against the depressed areas. The assembly may be used in forming multi-chip modules having demountable integrated circuit chips.

Semiconductor package and manufacturing method thereof

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.

High density electrical connectors

The present invention relates to self-aligned, flexible high density and impedance adjusted electrical connectors used in microelectronic systems. This invention solves the problem of having electrical connection and alignment at the same time. One connector (200) having a first part (204) consists of two metal layer structures, a first signal path (212) and a first ground path (210), covering the V-groove (202). The connector also has a second part (208) consisting of corresponding metal layers, a second signal path (224) covering the elastic bump (206) and a second signal ground plane (226), which fits into the V-groove (202). The first and the second signal path (212, 224) are in contact with each other when the first and the second part (204, 208) are brought together. The contact is self-aligned when put together. The electrical contact will remain even if displaced due to the thermal expansion.

Semiconductor device

In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

Method of flip-chip assembly of two electronic components by uv annealing, and assembly obtained

Semiconductor package and method of manufacturing the same

半导体封装及其制造方法。本发明提供一种半导体封装和一种制造半导体封装的方法。作为非限制性实例，本发明的各个方面提供一种半导体封装及其制造方法，所述半导体封装包括：衬底，其具有第一表面和与所述第一表面相对的第二表面，且包括形成于从所述第一表面朝向所述第二表面的方向中的至少一个第一凹口部分、形成于所述第一凹口部分中的多个第一凹口导电图案以及第一无源元件，所述第一无源元件插入到所述衬底的所述第一凹口部分中且具有电连接到所述多个第一凹口导电图案的第一电极和第二电极。

Multi-strike process for bonding

A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.

Two-way integrated embedded type POP encapsulating structure and preparation method thereof

本发明涉及一种双向集成埋入式POP封装结构及其制作方法，所述结构包括第一封装体和第二封装体，所述第一封装体包括第一线路层（1），第一线路层（1）正面设置有第一连接铜柱（2），第一线路层（1）外围包封有第一绝缘材料（3），第一绝缘材料（3）正面设置有第二线路层（4），第二线路层（4）正面设置有第二连接铜柱（5）和第一元器件（7），第二线路层（4）外围包封有第二绝缘材料（6），第一绝缘材料（3）背面设置有第三连接铜柱（8）和第二元器件（9），所述第三连接铜柱（8）外围包封有第三绝缘材料（10）。本发明能够多层双向埋入，无源器件贴装个数更多，有效地节约了基板空间提高了封装工艺的集成度。

Method of flip-chip assembly of two electronic components by uv annealing, and assembly obtained

The invention concerns a method of flip-chip assembly between first (1) and second (2) components each comprising connection pads (11, 21) on one of the faces of same, referred to as assembly faces, which involves transferring the components onto each other via the assembly faces of same in such a way as to create electrical interconnections between the pads of the first and second components. The invention involves transforming the copper oxide into copper by UV annealing, very locally, in the gap between the components, at least around the areas adjacent to the connection pads. The method according to the invention can be used for any component that is transparent to UV rays, including for substrates made from a plastic material such as substrates made from PEN or PET. The invention also concerns the assembly of two components obtained by the method.

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

METHOD OF ASSEMBLING TWO ELECTRONIC COMPONENTS OF FLIP-CHIP TYPE BY UV-COATING, ASSEMBLY OBTAINED

Inverter power system and manufacturing method thereof

本发明提供了一种逆变器电力系统及其制造方法，其包括散热基板、陶瓷基板、多个逆变器芯片、多个导电桥和多个引出端子，所通过在陶瓷基板上设置多个环形凹陷，其中，俯视观察时，所述多个环形凹陷的每一个一对一环绕所述多个逆变器芯片的每一个，且所述陶瓷基板通过焊料层焊接于所述散热基板上，其中所述焊料层至少部分填充所述多个环形凹陷。本发明可以抑制陶瓷基板的翘曲、减小其内部应力。

Nanowires for pillar interconnects

An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

Semiconductor component having an opening for optical monitoring

The invention relates to a semiconductor component. The semiconductor component comprises electrical connections which are each designed for soldering to a circuit carrier. The semiconductor component has a semiconductor, in particular a semiconductor chip. The semiconductor component also has a connection surface, wherein a plurality of electrical connections are formed on the connection surface. The connections each have a contact surface designed for soldering, in particular reflow soldering. According to the invention, the semiconductor component has at least one opening, which extends between the contact surface and a surface of the semiconductor component opposite the connection surface. The opening is designed in such a way that a soldering joint in the region of the connection can be optically recorded from outside through the opening.

Electrical interconnect structure for a semiconductor device and an assembly using the same

An electrical interconnect structure for a semiconductor device is provided herein. The electrical interconnect structure includes a conductive pillar (114) electrically coupled to a conductive contact (112) positioned on a emiconductor die (110) and a trace receiver (140) on a distal end of the pillar (114). The trace receiver (140) has a body (145) electrically coupled to the distal end, and may include a first leg(147a) projecting from a first side of the body (145) away from the distal end and a second leg (147b) projecting from a second side of the body (145) away from the distal end, such that the body (145), the first leg (147a), and the second leg (147b) together form a cavity. During assembly of the semiconductor device, the cavity is configured to at least partially surround a portion of a trace (122) positioned in an insulated substrate (120). To form the electrical connection, a solder material (142) may be disposed between the trace receiver (140) and the trace (122).

Display device

A display device includes a substrate including an active area having pixels and a non-active area including a pad region. A pad electrode is disposed in the pad region and includes a first pad electrode and a second pad electrode disposed on the first pad electrode. A first insulating pattern is interposed between the first and second pad electrodes. In a plan view, the first insulating pattern is positioned inside the first pad electrode, and a portion of the second pad electrode overlapping the first insulating pattern protrudes further from the substrate in a thickness direction than a portion of the second pad electrode not overlapping the first insulating pattern. The second pad electrode directly contacts a portion of the upper surface of the first pad electrode. In a plan view, an area of the second pad electrode is greater than an area of the first pad electrode.

Methods of manufacturing semiconductor packages

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

半導體封裝及其製造方法

本發明提供一種半導體封裝和一種製造半導體封裝的方法。作為非限制性實例，本發明的各個態樣提供一種半導體封裝及其製造方法，所述半導體封裝包括：基板，其具有第一表面和與所述第一表面相對的第二表面，且包括形成於從所述第一表面朝向所述第二表面的方向中的至少一個第一凹口部分、形成於所述第一凹口部分中的多個第一凹口導電圖案以及第一被動元件，所述第一被動元件插入到所述基板的所述第一凹口部分中且具有電連接到所述多個第一凹口導電圖案的第一電極和第二電極。

Ball height control in bonding process

A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.

半導體封裝及其製造方法

本發明提供一種半導體封裝和一種製造半導體封裝的方法。作為非限制性實例，本發明的各個態樣提供一種半導體封裝及其製造方法，所述半導體封裝包括：基板，其具有第一表面和與所述第一表面相對的第二表面，且包括形成於從所述第一表面朝向所述第二表面的方向中的至少一個第一凹口部分、形成於所述第一凹口部分中的多個第一凹口導電圖案以及第一被動元件，所述第一被動元件插入到所述基板的所述第一凹口部分中且具有電連接到所述多個第一凹口導電圖案的第一電極和第二電極。

显示设备

本申请提供了一种显示设备，该显示设备包括衬底，衬底包括具有像素的有效区域和包括焊盘区域的非有效区域。焊盘电极设置在焊盘区域中并且包括第一焊盘电极和设置在第一焊盘电极上的第二焊盘电极。第一绝缘图案插置在第一焊盘电极和第二焊盘电极之间。在平面图中，第一绝缘图案位于第一焊盘电极内部，并且相比于第二焊盘电极的不与第一绝缘图案重叠的部分，第二焊盘电极的与第一绝缘图案重叠的部分在厚度方向上从衬底进一步突出。第二焊盘电极直接接触第一焊盘电极的上表面的其上没有设置第一绝缘图案的部分。在平面图中，第二焊盘电极的面积大于第一焊盘电极的面积。

互連結構及相關聯系統及方法

本文中提供一種用於一半導體裝置之互連結構。該互連結構通常包括電耦接至定位於一半導體晶粒上之一導電觸點之一導電柱及位於該柱之一遠端上之一跡線收納器。該跡線收納器具有電耦接至該遠端之一本體，且可包括自該本體之一第一側遠離該遠端突出的一第一支腳及自該本體之一第二側遠離該遠端突出的一第二支腳，使得該本體、該第一支腳及該第二支腳一起形成一空腔。在該半導體裝置之組裝期間，該空腔經組態以至少部分地環繞定位於一絕緣基板中之一半導體跡線之一部分。為了形成電連接，可將一焊料材料安置於該跡線收納器與該跡線之間。

互連結構及相關聯系統及方法

本文中提供一種用於一半導體裝置之互連結構。該互連結構通常包括電耦接至定位於一半導體晶粒上之一導電觸點之一導電柱及位於該柱之一遠端上之一跡線收納器。該跡線收納器具有電耦接至該遠端之一本體，且可包括自該本體之一第一側遠離該遠端突出的一第一支腳及自該本體之一第二側遠離該遠端突出的一第二支腳，使得該本體、該第一支腳及該第二支腳一起形成一空腔。在該半導體裝置之組裝期間，該空腔經組態以至少部分地環繞定位於一絕緣基板中之一半導體跡線之一部分。為了形成電連接，可將一焊料材料安置於該跡線收納器與該跡線之間。

Elektrische zwischenverbindungsstruktur für eine halbleitervorrichtung und anordnung zu deren verwendung

Eine Zwischenverbindungsstruktur für eine Halbleitervorrichtung wird hier bereitgestellt. Die Zwischenverbindungsstruktur umfasst eine leitende Säule (114), die elektrisch mit einem leitenden Kontakt (112) gekoppelt ist, der sich auf einem Halbleiterchip (110) befindet, und einen Leiterbahnempfänger (140) an einem distalen Ende der Säule (114). Der Leiterbahnempfänger (140) hat einen Körper (145), der elektrisch mit dem distalen Ende gekoppelt ist, und kann einen ersten Schenkel (147a), der von einer ersten Seite des Körpers (145) und weg von dem distalen Ende vorsteht, und einen zweiten Schenkel (147b), der von einer zweiten Seite des Körpers (145) und weg von dem distalen Ende vorsteht, umfassen, so dass der Körper (145), der erste Schenkel (147a) und der zweite Schenkel (147b) zusammen eine Kavität bilden. Während des Zusammenbaus der Halbleitervorrichtung ist die Kavität konfiguriert, um einen Bereich einer Leiterbahn (122), die sich in einem isolierten Substrat befindet, zumindest teilweise zu umgeben. Um die elektrische Verbindung herzustellen, kann ein Lötmaterial (142) zwischen dem Leiterbahnempfänger (140) und der Leiterbahn (122) angeordnet werden.

用于半导体装置的电互连结构及使用电互连结构的组合件

本文中提供一种用于半导体装置的电互连结构。所述电互连结构包含电耦合到定位于半导体裸片(110)上的导电触点(112)的导电柱(114)及位于所述柱(114)的远端上的迹线收纳器(140)。所述迹线收纳器(140)具有电耦合到所述远端的主体(145)，且可包含从所述主体(145)的第一侧远离所述远端突出的第一支脚(147a)及从所述主体(145)的第二侧远离所述远端突出的第二支脚(147b)，使得所述主体(145)、所述第一支脚(147a)及所述第二支脚(147b)一起形成空腔。在所述半导体装置的组装期间，所述空腔经配置以至少部分地环绕定位于绝缘衬底(120)中的迹线(122)的一部分。为了形成电连接，可将焊料材料(142)安置于所述迹线收纳器(140)与所述迹线(122)之间。

半导体存储装置及其制造方法

一种半导体存储装置及其制造方法，所述半导体存储装置包括：第一存储芯片，所述第一存储芯片内形成有第一存储阵列和外围电路，所述外围电路包括第一电路、至少部分第二电路以及共用电路，所述第一电路用于控制所述第一存储阵列，所述第二电路用于控制所述的第二存储阵列，所述第一电路与所述第一存储阵列连接，所述第二电路与所述第二存储阵列连接，所述共用电路连接所述第一电路和第二电路；第二存储芯片，所述第二存储芯片内形成有第二存储阵列；所述第二存储芯片的正面堆叠于所述第一存储芯片表面，所述第二存储芯片的正面形成有第二导电凸块；通过所述第二导电凸块与第一存储芯片之间形成电连接；所述半导体存储装置的数据传输效率提高。

마이크로 엘이디 모듈 및 그 제조방법

마이크로 엘이디 모듈 제조방법이 개시된다. 이 마이크로 엘이디 모듈 제조방법은, 다수의 전극패드와 다수의 엘이디 셀을 포함하는 마이크로 엘이디를 준비하는 단계; 상기 다수의 전극패드에 상응하는 다수의 전극을 포함하는 서브마운트 기판을 준비하는 단계; 및 상기 다수의 전극패드와 상기 다수의 전극 사이에 위치하는 다수의 솔더를 이용하여, 상기 마이크로 엘이디를 상기 서브마운트 기판에 플립본딩하는 단계를 포함하되, 상기 플립본딩하는 단계는 상기 다수의 솔더를 레이저빔으로 가열하는 것을 포함한다.

Device and method of fluidic assembly of microchips on a substrate

A cell of fluidic assembly of microchips on a substrate, including: a base having its upper surface intended to receive the substrate; a body laterally delimiting a fluidic chamber above the substrate; and a cover closing the fluidic chamber from its upper surface, wherein the body comprises first and second nozzles respectively emerging onto opposite first and second lateral edges of the fluidic chamber, each of the first and second nozzles being adapted to injecting and/or sucking in a liquid suspension of microchips into and/or from the fluidic chamber, in a direction parallel to the mean plane of the substrate.

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

스루-실리콘 비어들을 위한 관통 구조물들을 포함하는 적층 다이용 상호접속 구조물

스루-실리콘 비어들을 위한 관통 구조물들을 포함하는 적층 다이용 상호접속 구조물들, 관련 시스템 및 방법들이 설명되어 있다. 특별한 실시예에 따른 시스템은 제1 기판 재료를 갖는 제1 반도체 기판과, 상기 제1 반도체 기판에 의해 지지된 관통 구조물을 포함한다. 또한 시스템은 프리폼형 리세스를 갖는 제2 기판 재료를 구비하는 제2 반도체 기판을 포함한다. 제1 반도체 기판의 관통 구조물은 제2 반도체 기판의 리세스내에 수용되어, 상기 리세스와 기계적으로 결합되며, 제2 반도체 기판에 고정된다.

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

包含用于穿硅通孔的穿透结构的堆叠式裸片互连结构

本发明揭示包含用于穿硅通孔的穿透结构的堆叠式裸片互连结构以及相关联的系统及方法。根据特定实施例，一种系统包含具有第一衬底材料的第一半导体衬底及由所述第一半导体衬底承载的穿透结构。所述系统进一步包含具有带有预形成的凹部的第二衬底材料的第二半导体衬底。所述第一半导体衬底的所述穿透结构接纳于所述第二半导体衬底的所述凹部中且与所述凹部机械啮合并紧固到所述第二半导体衬底。

스루-실리콘 비어들을 위한 관통 구조물들을 포함하는 적층 다이용 상호접속 구조물

스루-실리콘 비어들을 위한 관통 구조물들을 포함하는 적층 다이용 상호접속 구조물들, 관련 시스템 및 방법들이 설명되어 있다. 특별한 실시예에 따른 시스템은 제1 기판 재료를 갖는 제1 반도체 기판과, 상기 제1 반도체 기판에 의해 지지된 관통 구조물을 포함한다. 또한 시스템은 프리폼형 리세스를 갖는 제2 기판 재료를 구비하는 제2 반도체 기판을 포함한다. 제1 반도체 기판의 관통 구조물은 제2 반도체 기판의 리세스내에 수용되어, 상기 리세스와 기계적으로 결합되며, 제2 반도체 기판에 고정된다.

Semiconductor package and manufacturing method thereof

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.

Adapter board and method for forming same, packaging method, and package structure

Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure. In the embodiments and implementations of the present disclosure, the capacitor is further formed in the adapter board, so that a process of forming the capacitor and a process of forming the adapter board are integrated, and an additional step of forming the capacitor is omitted, which is beneficial to reduce processes and improve the process integration, and is further beneficial to reduce process costs and shorten the production cycle. Moreover, the functional diversity of the adapter board is further improved, so that an application scenario of the adapter board is diversified.

用於透過模具互連的堆疊式封裝的裝置及方法

在本文中大體上討論用於更可靠的透過模具互連(TMI)的堆疊式封裝(PoP)之方法及裝置。一裝置可包含：一第一晶粒封裝，其包含在該第一晶粒封裝上或至少部分地在該第一晶粒封裝中之第一導電襯墊；在該第一晶粒封裝上之一介電質模具材料，該模具材料包含貫穿其以至少部分地曝露該襯墊之一孔；一第二晶粒封裝，其包含在該第二晶粒封裝上或至少部分地在該第二晶粒封裝中之一第二導電襯墊，該第二晶粒封裝在該模具材料上使得該第二導電襯墊透過該孔而面向該第一導電襯墊；以及一形狀記憶結構，其位在該孔中且形成該第一晶粒封裝與該第二晶粒封裝之間之一焊料柱電連接的一部分。

マイクロｌｅｄモジュールのフリップチップボンディング方法

半导体部件背侧上用于减轻堆叠封装中的分层的孔结构

本发明题为“半导体部件背侧上用于减轻堆叠封装中的分层的孔结构”。本发明公开了一种工艺，所述工艺包括在部件背侧上形成一个或多个孔，在模具套中形成真空，并且使所述部件背侧与所述模具套中的模具化合物接合。所述一个或多个孔形成孔结构。所述孔结构可包括彼此平行或正交的多个孔。所述孔具有孔宽度、孔深度和孔间距。可改变这些特性以使在所述模具套中形成所述真空之后捕捉的空气保留的可能性最小化。

マイクロｌｅｄモジュールのフリップチップボンディング方法及びそれを用いたフリップチップボンディングモジュール

【課題】マイクロＬＥＤモジュールのフリップチップボンディング方法及びそれを用いたフリップチップボンディングモジュールを提供する。 【解決手段】本発明のフリップチップボンディング方法は、ＬＥＤ基板、及びＬＥＤ基板上に形成された多数のＬＥＤセルを含むマイクロＬＥＤを準備する段階と、ＬＥＤ基板とは熱膨張係数が異なるサブマウント基板を準備する段階と、マイクロＬＥＤとサブマウント基板との間に位置するソルダーを用いてマイクロＬＥＤとサブマウント基板とをフリップチップボンディングする段階と、を有し、フリップチップボンディングする段階は、ＬＥＤ基板とサブマウント基板との熱膨張係数の差による変形量の差を抑制するように、サブマウント基板の温度とＬＥＤ基板の温度とを互いに異なる加熱−冷却曲線で制御する。 【選択図】図９

Metal clip with solder volume balancing reservoir

A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.

Semiconductor device and semiconductor device manufacturing method

A semiconductor device includes: a redistribution line provided on a main face of a first semiconductor chip; an insulating film covering a front face of the redistribution line, the insulating film including a first opening and a second opening that each partially expose the redistribution line; a first electrode provided on the insulating film, and is connected to the redistribution line at the first opening, the first electrode formed of the same material as the redistribution line; and a second electrode provided on the insulating film, and is connected to the redistribution line at the second opening, the second electrode formed of a material that differ from a material of the first electrode.

Adapter board and method for forming same, packaging method, and package structure

Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

转接板及其形成方法、封装方法以及封装结构

一种转接板及其形成方法、封装方法以及封装结构，转接板的形成方法包括：提供基底，包括互连区和电容区，基底包括相背的正面和背面；对基底的正面进行刻蚀，在互连区的基底中形成第一沟槽、以及在电容区的基底中形成第二沟槽；在第二沟槽中形成电容器；刻蚀第一沟槽下方的部分厚度基底，形成导电通孔；在导电通孔中形成通孔互连结构；对基底的背面进行减薄处理，露出通孔互连结构。本发明实施例还在转接板中形成电容器，从而将形成电容器和形成转接板的工艺相整合，省去了额外进行形成电容器的步骤，有利于节约工序、提高工艺整合度，进而降低工艺成本、缩短生产周期，而且还提高转接板的功能多样性，从而使转接板的应用场景多样化。

Adapter board and method for forming same, packaging method, and package structure

Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure. In the embodiments and implementations of the present disclosure, the capacitor is further formed in the adapter board, so that a process of forming the capacitor and a process of forming the adapter board are integrated, and an additional step of forming the capacitor is omitted, which is beneficial to reduce processes and improve the process integration, and is further beneficial to reduce process costs and shorten the production cycle. Moreover, the functional diversity of the adapter board is further improved, so that an application scenario of the adapter board is diversified.

用於透過模具互連的堆疊式封裝的系統及方法

在本文中大體上討論用於更可靠的透過模具互連(TMI)的堆疊式封裝(PoP)之方法及裝置。一裝置可包含：一第一晶粒封裝，其包含在該第一晶粒封裝上或至少部分地在該第一晶粒封裝中之第一導電襯墊；在該第一晶粒封裝上之一介電質模具材料，該模具材料包含貫穿其以至少部分地曝露該襯墊之一孔；一第二晶粒封裝，其包含在該第二晶粒封裝上或至少部分地在該第二晶粒封裝中之一第二導電襯墊，該第二晶粒封裝在該模具材料上使得該第二導電襯墊透過該孔而面向該第一導電襯墊；以及一形狀記憶結構，其位在該孔中且形成該第一晶粒封裝與該第二晶粒封裝之間之一焊料柱電連接的一部分。

凸塊結構及其製造方法

Aperture structure on semiconductor component backside to alleviate delamination in stacked packaging

A process includes forming one or more apertures on a component backside, creating a vacuum in a mold chase, and engaging the component backside with a mold compound in the mold chase. The one or more apertures form an aperture structure. The aperture structure may include multiple apertures parallel or orthogonal to each other. The apertures have an aperture width, aperture depth, and aperture pitch. These characteristics may be altered to minimize the likelihood of trapped air remaining after creating the vacuum in the mold chase.

Fan-out pop stacking process

Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

Semiconductor module and method of fabricating same

A semiconductor module having a first metal wiring board, a second metal wiring board, a third metal wiring board, and a first semiconductor element and a second semiconductor element that each include an emitter electrode and a collector electrode. The second metal wiring board is disposed over a principal surface of the first metal wiring board with an insulation material therebetween. The third metal wiring board has a principal surface thereof facing the first metal wiring board. The first and second semiconductor elements are disposed to face directions opposite to each other. The collector electrodes of the first and second semiconductor elements respectively face the principal surfaces of the first and third metal wiring boards. The emitter electrodes of the first and second semiconductor elements are respectively connected to the principal surfaces of the third and second metal wiring boards.

Metallclip mit lotvolumenausgleichendem reservoir

Ein Halbleiterbauelement umfasst ein auf einem Substrat befestigtes Halbleiter-Die und einen an einer vom Substrat abgewandten Seite des Halbleiter-Dies mittels einer Lötstelle befestigten Metallclip. Der Metallclip weist mehrere Schlitze auf, die dahingehend bemessen sind, wenigstens 10 % einer zum Ausbilden der Lötstelle aufgeschmolzenen Lotpaste aufzunehmen. Es werden auch entsprechende Fertigungsverfahren beschrieben.

Semiconductor device having a metal clip with a solder volume balancing reservoir

A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste that reflowed to form the soldered joint. Corresponding methods of production are also described.