ПРИВЕДЕНИЕ В КОНТАКТ УСТРОЙСТВА С ПРОВОДНИКОМ

Изобретение относится к области приведения в контакт ОСИД с проводником. В способе для приведения в контакт ОСИД с проводником, ОСИД содержит подложку, по меньшей мере, с одной ячейкой, область контакта и инкапсулирующую оболочку, содержащую тонкую пленку, которая содержит нитрид кремния, карбид кремния или оксид алюминия, причем инкапсулирующая оболочка инкапсулирует, по меньшей мере, область контакта, а способ содержит этапы компоновки проводника на инкапсулирующей оболочке и взаимного соединения проводника с областью контакта, без предварительного удаления инкапсулирующей оболочки между проводником и областью контакта. Это изобретение обладает преимуществом в том, что инкапсулирующую оболочку между проводником и областью контакта не надо предварительно удалять. 2 н. и 7 з.п. ф-лы, 4 ил.

Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

Verfahren zur Bildung einer Drahtbondelektrode auf einer Dickschichtleiterplatte

Verfahren zum Herstellen einer Drahtbondelektrode auf einer Dickschichtleiterplatte, bei welcher eine Kupfer-Dickschicht (2) als Verdrahtungsschicht auf einem isolierenden Substrat (1) gebildet ist und ein auf dem isolierenden Substrat angebrachtes Teil (7) elektrisch mit der Kupfer-Dickschicht (2) über einen Golddraht (8) verbunden ist, mit: einem Schritt des Druckens der Kupfer-Dickschicht (2) auf das isolierende Substrat und des Sinterns der Kupfer-Dickschicht zur Bildung der Verdrahtungsschicht; und einem Schritt des Druckens einer Gold-Dickschicht, welcher vor dem Drucken Kupfer hinzugefügt worden ist, auf das isolierende Substrat und des Sinterns der Gold-Dickschicht als Drahtbondelektrode, um wenigstens partiell die Kupfer-Dickschicht zu überlappen, welche auf dem isolierenden Substrat gebildet ist.

Chip size semiconductor component

The semiconductor chip (21) carries several beads (22) bonded to the inner ends of the conductive wires (16), in a vertical manner. The entire chip is embedded in synthetic resin (23) such that the outer ends of the conductive wires protrude outwards. Preferably the inner end of the bonded wires, in contact with the chip beads, are shaped as irregular, oval; bonding spheres (25). Typically the outer ends of the protruding conductive vires are bent, directed against the middle of the chip, such as to form L-shaped external conductors.

Semiconductor module, has bonding wire bonded at load terminal and connected with upper contact piece, and explosion protection unit arranged between load terminals and upper contact piece and embedded in bonding wire at specific length

The module (100) has an electrically conductive lower contact piece (31) and an electrically conductive upper contact piece (32) spaced in a vertical direction (v). Multiple semiconductor chips comprise load terminals. One of the load terminals is electrical conductively connected with the lower contact piece. A bonding wire (4) is bonded at the load terminal and connected with the upper contact piece. An explosion protection unit is arranged between the load terminals and the upper contact piece and embedded in the bonding wire over 80% or 90% of length. The semiconductor chips are designed as unipolar and bipolar transistors such as IGBTs and MOSFETs. The bonding wire is designed as a flat small strip.

Wire bonding method for semiconductor device manufacture

The method involves using a capillary driven by a wire bonding apparatus, the capillary having an opening. A distal end of a bonding wire which enters a bonding circuit through the capillary is ultrasonically bonded. The opening forms a substantial part of a nail head bonding point during nail-head bonding.

Halbleitervorrichtung, Substrat zum Herstellen einer Halbleitervorrichtung und Verfahren zum Herstellen derselben

Halbleitervorrichtung, umfassend: eine Chipkontaktstelle; ein Halbleiterelement, das auf die Chipkontaktstelle geladen ist, das Elektroden aufweist; eine Mehrzahl von elektrisch leitfähigen bzw. leitenden Abschnitten, die um die Chipkontaktstelle angeordnet sind; Drähte zum Verbinden der Elektroden des Halbleiterelements und der elektrisch leitfähigen Abschnitte; und ein Dichtharz zum Dichten von wenigstens dem Halbleiterelement, den elektrisch leitfähigen Abschnitten und Drähten; wobei jeder der elektrisch leitfähigen Abschnitte eine Metallfolie enthält, wobei den elektrisch leitfähigen Abschnitt plattierende Schichten bzw. Lagen sowohl am oberen als auch unteren Ende der Metallfolie zur Verfügung gestellt sind; wobei die Chipkontaktstelle eine Chipkontaktstellen-Plattierschicht beinhaltet, die in derselben Ebene wie untere, den elektrisch leitfähigen Abschnitt plattierende Schichten der elektrisch leitfähigen Abschnitte vorgesehen ist; und wobei die unteren, den elektrisch leitfähigen ...

KAPAZITIVE VORRICHTUNG.

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Bondkopf für dicken Draht

Ultraschall-Drahtbonder, welcher umfasst: einen Bondkopf (10), welcher so verbunden ist, dass er in der Z-Achse über einem elektrischen oder elektronischen Bauteil, an das ein Draht gebondet werden soll, bewegbar ist; einen Ultraschall-Transducer (72) mit einem mit ihm verbundenen Bondwerkzeug (278) zum Bonden eines Drahtes; und eine flexible Halterung zur Halterung des Bondwerkzeugs (278), welche von mindestens einem bogenförmigen Arm (106, 108, 110, 124, 126, 128) gebildet ist, der mit dem Bondwerkzeug (278) so verbunden ist, dass das Bondwerkzeug (278) in Richtung der Z-Achse flexibel bewegbar ist.

Elektronisches Bauteil mit Halbleiterchip und Halbleiterwafer mit Kontaktflecken, sowie Verfahren zur Herstellung derselben

Die Erfindung betrifft ein elektronisches Bauteil mit Halbleiterchips (1) und einen Halbleiterwafer mit Kontaktflecken (2) sowie Verfahren zur Herstellung derselben. Dazu weisen die Kontaktflecken (2) auf dem Halbleiterchip (1) Mesastrukturen (6) auf, die derart dimensioniert sind, dass sie an die Größen von Kompressionsköpfen (7) von Bondverbindungen (4) angepasst sind und eine druckverteilende Wirkung auf die Oberseite (10) der Kontaktflecken (2) ausüben.

Verfahren zum elektrischen Verbinden eines Kontaktfeldes eines Halbleiterchips mit zumindest einer Kontaktfläche sowie danach hergestellte Chipkarte

Vorrichtung zum Anschweissen von duennen Draehten an Halbleiterbauteile mit Hilfe der Pressschweissung (Kalt- und Warmschweissung), mit einer Zufuhr fuer den Draht an einem den Pressdruck auf den Draht uebertragenden Schweisskopf

Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung

Leistungshalbleiterchip mit einem Halbleiterbauelementkörper (2) und mit einer auf dem Halbleiterbauelementkörper (2) angeordneten mehrschichtigen Metallisierung (10), die eine über dem Halbleiterbauelementkörper (2) angeordnete Nickelschicht (6) aufweist, wobei die Metallisierung (10) eine auf dem Halbleiterbauelementkörper (2) angeordnete, Aluminium aufweisende erste Metallschicht (3) aufweist, wobei die Nickelschicht (6) über der ersten Metallschicht (3) angeordnet ist, wobei die Metallisierung (10) eine zweite Metallschicht (4), die als Chromschicht ausgebildet ist und eine auf der zweiten Metallschicht (4) angeordnete Zwischenschicht (13), die aus Nickel besteht und eine auf der Zwischenschicht (13) angeordnete dritte Metallschicht (5), die als Silberschicht ausgebildet ist, aufweist, wobei die zweite Metallschicht (4) auf der ersten Metallschicht (3) angeordnet ist, wobei die Nickelschicht (6) auf der dritten Metallschicht (5) angeordnet ist, wobei die Nickelschicht (6) eine Dicke ...

KUPFERLEGIERUNGEN MIT VERBESSERTER LOETFAEHIGKEITS-HALTBARKEIT

Wire Bonder

Ein Wire Bonder enthält einen Bondkopf (1) und eine auf dem Bondkopf (1) angeordnete Wippe (8), die um eine horizontale Achse drehbar ist. An der Wippe (8) ist ein mit einem Flansch (18) versehenes Horn (9) befestigt, in dem eine Kapillare (10) eingespannt ist. Am Bondkopf (1) ist mindestens ein Sensor (22) befestigt, der Schwingungen des Bondkopfs (1) detektiert und zwischen dem Flansch (18) und der Wippe (8) ist mindestens ein Aktuator (13; 14; 15) angeordnet, der eine Bewegung des Horns (9) relativ zur Wippe (8) ermöglicht. Eine Steuereinrichtung (26) berechnet aus einem von dem mindestens einen Sensor (22) gelieferten Ausgangssignal ein Steuersignal für den mindestens einen Aktuator (13; 14; 15) und steuert den mindestens einen Aktuator (13; 14; 15) an, um Schwingungen des Horns (9) zu eliminieren oder mindestens zu reduzieren. Der mindestens eine Sensor (22) ist bevorzugt auf der Wippe (8) angeordnet und ist bevorzugt ein Beschleunigungssensor.

Laminierte Leistungselektronikbaugruppe

Halbleiterbaugruppe für die Leistungselektronik umfassend ein mindestens teilweise metallisiertes Substrat mit wenigstens einem darauf angeordneten, an der Unterseite elektrisch kontaktierten Halbleiterbauelement, gekennzeichnet durch eine das Halbleiterbauelement unter Druckbeaufschlagung dicht umschließende, elektrisch isolierende Polymerfolie aus einem unter Druck fließfähigen Polymer, wobei die Folie an vorbestimmten Stellen Schlitzungen aufweist, durch welche wenigstens ein Metallband als Kontaktelement mindestens einmal von der einen Folienseite auf die andere Folienseite geführt ist und die Oberseite des Halbleiterbauelements elektrisch kontaktiert.

Bondvorrichtung und Verfahren zur Herstellung elektrisch leitfähiger Verbindungen

Die vorliegende Erfindung betrifft eine Bondvorrichtung, aufweisend zumindest ein Bondwerkzeug und aufweisend eine Schneideinrichtung zum teilweisen oder vollständigen Zertrennen des Leiterquerschnittes und schlägt zur vorteilhaften Weiterbildung vor, dass auf der Schneideinrichtung (9) zumindest ein Piezoelement (17) montiert ist, da es bei Erregung mittels elektrischer Wechselspannung, vorzugsweise im Ultraschall-Frequenzbereich, zumindest einen Teilbereich der Schneideinrichtung (9), vorzugsweise zumindest eine Schneide (10) der Schneideinrichtung (9), in Schwingungen versetzt. Die Erfindung betrifft weiterhin ein Verfahren zur Herstellung elektrisch leitfähiger Verbindungen zwischen Verbindungspartnern mittels Befestigung von elektrischem Leiter an den miteinander elektrisch leitfähig zu verbindenden Verbindungspartnern durch Bondverbindungen, vorzugsweise Ultraschall-Bondverbindungen, wobei nach dem Herstellen einer gewünschten Anzahl von Bondverbindungen zum Abtrennen eines Längenabschnittes ...

Leistungshalbleitermodul

Es wird ein Leistungshalbleitermodul offenbart. Eine Ausführungsform enthält ein Mehrschichtsubstrat mit mehreren Metallschichten und mehreren Keramikschichten, wobei die Keramikschichten zwischen den Metallschichten liegen.

METHOD FOR BONDING A WIRE TO A METAL LAYER

... 1294770 Soldering HITACHI Ltd 22 Dec 1970 [29 Dec 1969] 60892/70 Heading B3R [Also in Division H1] In connecting a wire to a metal layer on a substrate the wire is guided through the passage of a capillary tube and a portion of the wire extending from the tube is pressed against the layer by the tube, the tube is heated to a temperature not lower than the melting point of the layer but lower than the melting point of the wire whereby the portion of the wire is pressed into the metal layer while metal of the layer is melted and the layer is then cooled to bond the wire to the layer, the tool being then moved away. An electrode 2, Fig. la, printed on a ceramic substrate 1 of a semi-conductor device carries a lead-tin solder layer 3 and a silver wire 5 is guided through the passage of a capillary tube 4. A head 6 is formed on the wire by burning in a hydrogen flame. The tube 4 is heated by resistance means to a temperature not lower than the melting point of the solder 3, e.g. to 300‹ C. and ...

Method of producing a semiconductor device

Electrical connection to an A1 electrode of a semiconductor is made by the attachment of a copper wire. A copper ball 8a formed by flaming out one end of a copper wire 8 is moved downward to an A1 electrode pad 5 on a semiconductor chip and brought into contact for less than 150 ms. Plastic deformation then occurs so that the copper ball is pressed to the aluminium electrode pad in such a manner that the height of the copper ball (h, Fig. 8) is 25 mu m or less. It is therefore possible to decrease the work hardening property of the Cu ball and prevent A1 exclusion when the Cu ball is bonded to the A1 electrode pad. ...

WIRE BONDING APPARATUS

PROVISION OF WIRE CONNECTIONS FOR SEMICONDUCTOR DEVICES

... 1502965 Welding by pressure; welding electrical contact PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 16 May 1975 [21 May 1974] 20840/75 Headings B3R and B3A In a method of welding a wire 9 (e.g. gold) to a semi-conductor body 1, an electric spark discharge between an electrode 10 and the end of the wire 9 melts the wire to form a ball 11 below a recess 8 in the welding surface 6 of a welding tool 5, preferably an ultrasonic sonotrode, whereupon the tool 5 presses the ball 11 on to a contact place 2 of the semi-conductor body 1 to produce the weld. The welding tool 5 also produces a weld between the wire 9 and a supply conductor, without the formation of a ball 11 (Fig. 6, not shown). The electric spark discharge may be provided by way of a transformer fed by a discharge capacitor, the discharge time being less than 5 msec. and the energy of the discharge (hence the size of the ball) determined by the capacitor voltage. The recess 8 can either be a groove transverse to the wire 9, which ...

PROCEDURE FOR THE WIRE BONDING OF A MICROELECTRONIC SEMICONDUCTOR CHIP

PROCEDURE AND DEVICE FOR THE EXAMINATION OF A WIRE BOND

CONTROL SYSTEM

PROCEDURE FOR ATTACHING A DUENNEN ELECTRICAL OF LEADING WIRE AT ELECTRONIC CONSTRUCTION UNITS, IN PARTICULAR SEMICONDUCTOR COMPONENTS.

WEAK POINT OF A WIRE PRODUCES BY A WIRE LINK.

BALL BOND PROCEDURE AND DEVICE FOR THE EXECUTION OF THE SAME

MONITORING OF BOND PARAMETERS DURING THE BOND PROCEDURE.

DEVICE FOR THE EXAMINATION OF WIRE FEED AND - CONSUMPTION

EFFICIENT ENERGY-TRANSFERRING CAPILLARY

Laying device, contacting device, advancing system, laying and contacting unit, production system, method for the production and a transponder unit

Manufacturing process for hybrid circuit modules including e lectronic chip devices

Method for the wafer-level integration of shape memory alloy wires

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

WIRE BONDED INTEGRATED CIRCUIT DEVICES

Improved integrated circuit structures and methods to facilitate accurate measurement of the ic devices

LAYING DEVICE, CONTACTING DEVICE, ADVANCING SYSTEM, LAYING AND CONTACTING UNIT, PRODUCTION SYSTEM, METHOD FOR THE PRODUCTION AND A TRANSPONDER UNIT

CORROSION-RESISTANT ALUMINUM ELECTRONIC MATERIAL

A corrosion-resistant aluminum electronic material comprising an alloy containing aluminum as the principal component and, in addition, a small amount of a noble metal, the content of said noble metal being equal to or less than that at the eutectic point having the primary crystal of aluminum. As the noble metal, there is contained at least one metal selected from Pt, Pd, Rh, Ir, Os, Ru, Au and Ag. Said electronic material is used for ball-bonding wire and distributing film in a semiconductor device, and the like.

METHOD OF PROVIDING RAISED CONTACT PORTIONS ON CONTACT AREAS OF AN ELECTRONIC MICROCIRCUIT

... : "Method of providing raised contact portions on contact areas of an electronic microcircuit". A method of providing raised contact portions on contact areas of an electronic microcircuit in which a ball is formed at one end of a metal wire by means of thermal energy, the ball is pressed against a contact area of the electronic microcircuit and is connected to said contact area, a weakening being provided in the wire near the ball and the wire being severed at the area of the weakening.

METHOD OF WELDING OF CONNECTION WIRES TO MICROCIRCUIT CONTACTS

PHN.9872 10 27.4.81 "Method of forming a wire bond" A method of forming a wire bond between a contact place on an electronic microcircuit (17) and a connection conductor (18), in which a wire (6) of aluminium or an aluminium alloy is used which is passed through a capillary (5) in which a ball is formed at the end of the wire by means of a spark discharge between the wire (6) and an electrode (11), which spark discharge takes place in a protective gas atmosphere in which a first electric spark discharge is produced between two auxiliary electrodes (12, 13) as a result of which the protective gas is ionised and a plasma is formed, after which due to the low resistance in the plasma an electric spark discharge takes place between the electrode (11) and the wire (6) at a voltage between 25 V and 200 V, by which spark discharge a ball is formed at the end of the wire, while the wire is then bonded to a contact place on the electronic microcircuit and then to the connection conductor by means ...

WIRE BONDING TECHNIQUE FOR INTEGRATED CIRCUIT CHIPS

Title of the Invention LEAD FRAME WIRE BONDING BY PREHEATING In a method for welding a lead wire or bonding wire from a microcircuit chip mounted on a lead frame to a lead frame finger, the lead frame finger is preheated prior to any substantial electrical or thermal coupling between the lead frame finger and chip. Intense but controlled energy is applied to the lead frame finger at levels which might otherwise damage the IC chip. In one embodiment the lead frame finger is preheated to a temperature below the melting point of the metal comprising the lead frame. Enhanced bonding is thereafter effected by thermocompression bonding or the like. In another embodiment the preheating step comprises melting a portion of the surface of the lead frame finger and forming a molten pool or puddle in the surface. Bonding of the lead wire is affected by immersing a section of the wire in the molten pool or puddle. In order to preheat the lead frame finger a controlled pulse train is delivered for arc ...

LEAD WIRE BOND ATTEMPT DETECTION

Title of the Invention LEAD WIRE BOND ATTEMPT DETECTION A method and circuits are described for sensing and detecting bond attempts and weld attempts during bonding and welding-of lead wire. The method and circuitry are particularly applicable for detecting missed ball bonds and missed wedge bonds during bonding of lead wire between the die pad of a microcircuit chip and the lead frame on which the chip is mounted. A sensor (30) or sensing circuit (42) senses the different characteristic electrical condition of the lead wire (11) following a ball bond attempt and following a wedge bond attempt. A bond attempt indicator (45). indicates high resistance in the lead wire following a missed ball bond while weld attempt indicator (46) indicates low resistance in the lead wire (11) following a missed wedge bond. The lead wire (11) is isolated from uncontrolled contacts with ground potential while the lead wire is held in the bonding tool and bonding machine. Switching circuit (38) electrically ...

SEMICONDUCTOR PACKAGE

PULSE-WIDTH CONTROL OF BONDING BALL FORMATION

PACKAGE FOR INTEGRATED CIRCUIT DIE

A circuit package for housing semiconductor or other integrated circuit devices ("die") includes a high-copper flange, one or more high-copper leads and a liquid crystal polymer frame molded to the flange and the leads. The flange includes a dovetail-shaped groove or other frame retention feature that mechanically interlocks with the molded frame. During molding, a portion of the frame forms a key that freezes in or around the frame retention feature. The leads include one or more lead retention features to mechanically interlock with the frame. During molding, a portion of the frame freezes in or adjacent these lead retention features. The frame includes compounds to prevent moisture infiltration and match its coefficient of thermal expansion (CTE) to the CTE of the leads and flange. The frame is formulated to withstand die-attach temperatures. A lid is ultrasonically welded to the frame after a die is attached to the flange.

ELECTRONIC DEVICE PACKAGING

LEAD WIRE BOND ATTEMPT DETECTION

MICROELECTRONIC CIRCUIT COATING SYSTEM

HALO-HYDROCARBON POLYMER COATING

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multilayer coating.

METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

METHOD FOR PRODUCING AN ELECTRONIC CIRCUIT ASSEMBLY

There is disclosed herein a method for producing a wirebonded electronic circuit assembly which obviates the need for soldering aluminum-copper wirebond pads to substrate mounting pads and other copper bonding surfaces.

Werkzeug zum permanenten Befestigen eines Drahtes an einer Fläche

Verfahren zum Kontaktieren von Halbleiteranordnungen oder anderen elektrischen Bauelementen mit mindestens zwei eng nebeneinanderliegenden, kleinflächigen Kontaktstellen

Träger mit mindestens einer Mikroschaltanordnung und Verfahren zu seiner Herstellung

Verfahren zur Herstellung eines Halbleiterbauelementes, wobei das Anbringen elektrischer Verbindungen zwischen Kontaktstellen des Halbleiterbauelementes einerseits und Zuführungsleitern andererseits ein Werkzeug verwendet wird

VERFAHREN ZUM FORTLAUFENDEN HERSTELLEN MINDESTENS EINER DRAHTVERBINDUNG IN HALBLEITER-BAUTEILEN UND VORRICHTUNG ZUR AUSFUEHRUNG DES VERFAHRENS.

Mit mindestens einer Anschlusselektrode kontaktiertes elektronisches Bauelement

CONTACTING MECHANISM FOR THE PRODUCTION OF A WIRE COMMUNICATION AT A MICROCIRCUIT.

USE OF A PURIFYING WIRE FOR THE PRODUCTION OF THE EXTERNAL CONNECTIONS OF SEMICONDUCTOR COMPONENTS.

PURIFYING WIRE FOR CONTACTING SEMICONDUCTOR COMPONENTS.

PROCESS FOR THE CONTINUOUS PRODUCTION OF A PRINTED CIRCUIT AND USE OF THAT CIRCUIT.

PROCEDURE FOR THE ATTACHMENT OF CONTACT CONTACTS TO CONTACT POINTS OF AN ELECTRONIC MICROCIRCUIT.

PROCEDURE FOR THE PRODUCTION OF A WIRE COMMUNICATION.

Contacting quality analyzer.

Bonding head of a wire and associated method.

PROCEDURE FOR THE ASSEMBLY OF SEMICONDUCTOR DEVICES AND MECHANISM FOR THE EXECUTION OF THE SAME.

DEVICE FOR ULTRASONIC WIRE BONDING.

DRIVE FOR A HIGH-SPEED WIRE CONTACTING MECHANISM.

Drahtklammer f�r a Wire Bonder.

Eine Drahtklammer (1) für einen Wire Bonder umfasst einen ersten Arm (2) und einen zweiten Arm (3), der um eine vorbestimmte Achse (4) drehbar am ersten Arm (2) gelagert ist. Der erste Arm (2) und der zweite Arm (3) weisen an einem von der Achse (4) entfernten Ende eine Klemmbacke (5 bzw. 6) auf. Die Drahtklammer (1) umfasst weiter ein Piezo-Biegeelement (8) zum Öffnen und Schliessen der Drahtklammer (1). Ein Ende des Piezo-Biegeelementes (8) ist am beweglichen Arm (3) befestigt und ein gegenüberliegendes Ende des Piezo-Biegeelementes (8) ist in einer am ersten Arm (2) befestigten Halterung (7) gelagert.

Procedure for the production of a Wedge Wedge cable link.

Eine Wedge Wedge Drahtbrücke (5) wird gebildet durch die Schritte:
a) Absetzen der Kapillare (11) auf einem ersten Anschlusspunkt (1) und Herstellen einer Wedge Verbindung, indem das aus der Kapillare (11) herausragende Endstück (10) des Drahts (4) durch Anlegen einer vorbestimmten Bondkraft und Ultraschalls auf dem ersten Anschlusspunkt (1) befestigt wird,
b) Anheben der Kapillare (11) um eine vorbestimmte Distanz D1 in im Wesentlichen vertikaler Richtung,
c) Bewegen der Kapillare (11) seitlich und abwärts, um den Draht (4) umzubiegen und an die Wedge Verbindung anzudrücken,
d) Anheben der Kapillare (11) und Bewegen der Kapillare (11), um eine Drahtbrücke (5) zu bilden und den Draht (4) auf dem zweiten Anschlusspunkt (7) zu befestigen, und
e) Abreissen des Drahts (4).

Capillary one for wire bonding.

Eine Kapillarenspitze 12, um einen Bonddraht, während dem Bonden des Drahtes zu einer Bonding-Oberfläche, zu deformieren, umfasst eine untere Fläche (18) entlang einem inneren Rand der Kapillarenspitze, um den Bonddraht gegen die Bonding-Oberfläche zu drücken, einen äusseren Radius entlang einem äusseren Rand (24) der Kapillarenspitze, und beinhaltet ferner eine erste geneigte Fläche (20) angrenzend zu der unteren Fläche und schiefwinklig zu der unteren Fläche erstreckend, sowie eine zweite geneigte Fläche, angrenzend an die erste geneigte Fläche und sich schiefwinklig zu der ersten geneigten Fläche erstreckend.

Semiconductor device and manufacture thereof, circuit board and electronic machine

CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

Manufacturing method for physical quantity sensor using lead frame and bonding device therefor

The light emitting element substrate, the light-emitting component and the light emitting assembly manufacturing method

The semiconductor device comprises a base

Welding device

Semiconductor equipment

Semiconductor device

A semiconductor device includes a semiconductor chip, a plurality of bonding pads which are formed on a main surface of the semiconductor chip and include first power source bonding pads, second power source bonding pads and a plurality of signal bonding pads, a plurality of leads which are arranged around the semiconductor chip and include first power source leads and a plurality of signal leads, a plurality of bonding wires which include first bonding wires for connecting the first power source bonding pads with the first power source leads, second bonding wires for connecting the first bonding pads with second bonding pads and third bonding wires for connecting the plurality of signal bonding pads with the plurality of signal leads, and a sealing body which seals the semiconductor chip, the plurality of bonding wires and some of the plurality of leads.

Semiconductor device and semiconductor device producing substrate and production method for semiconductor device producing substrate

FILS DE CONNEXION D'UNE PASTILLE SEMI-CONDUCTRICE, NOTAMMENT ENCAPSULEE SOUS RESINE

L'INVENTION CONCERNE UN DISPOSITIF A SEMI-CONDUCTEURS. DANS CE DISPOSITIF QUI COMPORTE UNE PASTILLE 3 RELIEE PAR DES CONDUCTEURS 6 A DES PARTIES EXTERIEURES CONDUCTRICES 1, CHAQUE FIL EST CONSTITUE PAR DE L'ALUMINIUM QUI CONTIENT AU MOINS UN ELEMENT CHOISI DANS LE GROUPE INCLUANT 0,05 A 3 EN POIDS DE FER ET 0,05 A 3 EN POIDS DE PALLADIUM. APPLICATION NOTAMMENT A LA FABRICATION DE DISPOSITIFS A SEMI-CONDUCTEURS ENCAPSULES DANS UNE RESINE ET FORMES MOYENNANT L'UTILISATION DE LA TECHNIQUE DU SOUDAGE A BOULE ECRASEE.

CIRCUIT IMPRIME A COMPOSANTS ELECTRONIQUES INCORPORES ET SON PROCEDE DE FABRICATION

Circuit imprimé multicouche à composants électroniques et collecteur thermique incorporée. Les cristaux semi-conducteurs 23 sont, d'une part, fixés directement sur le collecteur thermique 15 et, d'autre part, noyés dans la matière isolante 27 du stratifié 10. Le collecteur thermique 15 borde le circuit sur l'essentiel de sa surface et a sa face 22 libre pour la dissipation des calories. Application aux appareillages électroniques.

PROCEDE DE SUBSTITUTION D'UN COMPOSANT ELECTRONIQUE CONNECTE AUX PISTES CONDUCTRICES D'UN SUBSTRAT PORTEUR

L'INVENTION A POUR OBJET UN PROCEDE DE SUBSTITUTION D'UN COMPOSANT ELECTRONIQUE 1A A UN COMPOSANT 1 ANALOGUE CONNECTE AUX PISTES CONDUCTRICES 3 D'UN SUBSTRAT PORTEUR 2 PAR L'INTERMEDIAIRE DE FILS DE LIAISON 4. ON COUPE LES PISTES CONDUCTRICES EN AVAL PAR RAPPORT AU COMPOSANT 1 A METTRE HORS SERVICE, DES ZONES OU LES FILS DE LIAISON 4 SONT CONNECTES AUX PISTES, PUIS ON POSITIONNE LE COMPOSANT 1A DE REMPLACEMENT SUR LA FACE SUPERIEURE ENCOLLEE DU COMPOSANT 1, ET ON LE RELIE AUX PISTES PAR L'INTERMEDIAIRE DE FILS DE LIAISON 4A INDEPENDANTS DES PRECEDENTS. L'INVENTION S'APPLIQUE NOTAMMENT AUX CIRCUITS INTEGRES ET AUX CIRCUITS RESISTIFS A COUCHES MINCES DEPOSEES SOUS VIDE.

PROCESS AND APPARATUS OF CONDUCTING ALUMINIUM WIRE FIXING

DEVICE SEMICONDUCTOR HAS DIODE AND MANUFACTORING PROCESS

APPARATUS FOR THE WIRE FIXING BY WELDING, IN PARTICULAR FOR SOLID-STATE COMPONENTS

PROCEDE ET APPAREIL DE FIXATION DE FILS CONDUCTEURS D'ALUMINIUM

L'invention concerne la fixation de fils d'aluminium ou d'alliage d'aluminium à des composants ou petits circuits électriques, par mise en oeuvre d'une bille. Selon l'invention, une décharge disruptive est formée entre l'extrémité du fil et une électrode, en atmosphère protectrice, avec une densité de courant de crête dans le fil comprise entre 40 et 450 fois celle qui est utilisée pour la fixation d'un fil d'or suivant la même technique. L'oxydation de la bille est ainsi évitée. Application à la fixation de fils de connexion aux circuits intégrés.

Semiconductor device electrical conductor

DEVICE HAS SEMICONDUCTOR AND PROCESS OF WELDING OF WIRE FOR A DEVICE HAS SEMICONDUCTOR

Dans un dispositif à semiconducteur et un procédé de soudage de fil pour le dispositif à semiconducteur conformes à l'invention, une puce de semiconducteur (13) et un cadre de montage (14) moulé dans un boîtier (12) par moulage sur insert, sont connectés ensemble par un fil de soudage en or (15) au moyen d'un processus de soudage de fil dans lequel on accomplit une combinaison de soudage par onde ultrasonore et de soudage par thermocompression. Une partie de pré-soudage est formée initialement sur une surface de soudage du cadre de montage (14), et ensuite le fil de soudage (15) est soudé à la puce de semiconducteur et à la partie de pré-soudage par la combinaison du soudage par onde ultrasonore et du soudage par thermocompression.

CONNECTIONS FOR SEMICONDUCTOR COMPONENTS

MACHINE FOR ATTACHING THE CONNECTING WIRES TO THE CONNECTION POINTS OF A SEMICONDUCTOR COMPONENT AND OF THE HOUSING ACCOMMODATING THE SEMICONDUCTOR COMPONENT

MEANS Of DRIVE FOR an INSTALLATION OF WELDING OF WORKING WIRE HAS High speed, FOR EXAMPLE the BRANCHPOINTS FOR the FIXING OF the SEMICONDUCTOR PLATES

IMPROVEMENTS IN AND RELATING TO SEMICONDUCTOR DEVICES

Silver alloy wire

WIRE BONDING DEVICE AND WIRE BONDING METHOD

HALO-HYDROCARBON POLYMER COATING

... 일부 구체예에서, 인쇄 회로 보드(PCB)는 절연재를 포함하는 기판을 포함한다. 상기 PCB는 기판의 하나 이상의 표면에 결합된 복수의 도전성 트랙을 더 포함한다. 상기 PCB는 기판의 하나 이상의 표면상에 증착된 다중층 코팅을 더 포함한다. 상기 다중층 코팅은 (i) 복수의 도전성 트랙의 적어도 일부를 커버하고, (ii) 할로-하이드로카본 폴리머로 형성된 하나 이상의 층을 포함한다. 상기 PCB는 하나 이상의 도전성 트랙에 솔더 접합에 의해 연결된 하나 이상의 전기 소자를 더 포함하며, 상기 솔더 접합은 상기 솔더 접합이 상기 다중층 코팅에 인접하도록 상기 다중층을 통해 솔더된다.

CANTILEVER BEAMS AND MANUFACTURING METHOD OF INTERCONNECTS FACTOR USING SACRIFICIAL SUBSTRATES

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Gas delivery system for reducing oxidation in wire bonding operations

A wire bonding machine is provided. The wire bonding machine includes a bonding tool and an electrode for forming a free air ball on an end of a wire extending through the bonding tool where the free air ball is formed at a free air ball formation area of the wire bonding machine. The wire bonding machine also includes a bond site area for holding a semiconductor device during a wire bonding operation. The wire bonding machine also includes a gas delivery mechanism configured to provide a cover gas to: (1) the bond site area whereby the cover gas is ejected through at least one aperture of the gas delivery mechanism to the bond site area, and (2) the free air ball formation area.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Packaging Integrated Circuits

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Method of making a semiconductor chip assembly with a post/base heat spreader and a substrate using grinding

A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Semiconductor Device

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Method of manufacturing film for semiconductor device

The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T 2 /T 1 is 0.04 or more, wherein T 1 is the light transmittance of the portion where the dicing film and the protecting film are laminated and T 2 is the light transmittance of the portion where the dicing film, the die bond film, and the protecting film are laminated.

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Support structures and clamping systems for semiconductor devices during wire and ribbon bonding operations

A support structure for supporting a semiconductor device during a bonding operation is provided. The support structure comprises a body portion defining an upper surface configured to support a semiconductor device during a bonding operation. The upper surface defines a constraining feature for constraining at least a portion of the semiconductor device during the bonding operation.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Method of manufacturing semiconductor device

Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Low loop wire bonding

A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Power semiconductor arrangement and method for producing a power semiconductor arrangement

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Ribbon bonding tools and methods of using the same

A ribbon bonding tool including a body portion is provided. The body portion includes a tip portion. The tip portion includes a working surface between a front edge of the tip portion and a back edge of the tip portion. The working surface includes a region defining at least one of a plurality of recesses and a plurality of protrusions. The working surface also defines at least one of ( 1 ) a first planar portion between the region and the front edge of the tip portion, and ( 2 ) a second planar portion between the region and the back edge of the tip portion.

Wire loops, methods of forming wire loops, and related processes

A method of forming a wire loop is provided. The method includes the steps of: ( 1 ) forming a conductive bump on a bonding location using a wire bonding tool; ( 2 ) bonding a portion of wire to another bonding location using the wire bonding tool; ( 3 ) extending a length of wire from the bonded portion of wire toward the bonding location; ( 4 ) lowering the bonding tool toward the bonding location while detecting a height of a tip of the wire bonding tool; and ( 5 ) interrupting the lowering of the wire bonding tool during step ( 4 ) if the wire bonding tool reaches a predetermined height.

Resin Sealed Semiconductor Device And Manufacturing Method Therefor

A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.

Semiconductor device

A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Processes and structures for IC fabrication

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Wire bonding method in circuit device

A wire bonding method in a circuit device mounted on a lead frame, the wire bonding method including: counting a stop time if an operation of a capillary stops; removing a contaminated free air ball (FAB) formed on an end of the capillary if the stop time exceeds a reference time; forming a new FAB; and restarting a wire bonding process.

Manufacturing method of semiconductor device

A manufacturing yield of a semiconductor device including a power transistor is improved. When forming a tip portion LE 1 c of a first lead, a tip portion LE 2 c of a second lead, and a tip portion LE 3 c of a third lead by using a spanking die SDM 1 , the tip portion LE 1 c of the first lead, the tip portion LE 2 c of the second lead, and the tip portion LE 3 c of the third lead are pressed by an upper surface of a protrusion portion provided on a pressing surface of a lower die SD 1 and a bottom surface of a groove portion provided in a pressing surface of an upper die SU 1 , and a bent portion of the second lead and a bent portion of the third lead are pressed by a flat pressing surface of the lower die SD 1 and a flat pressing surface of the upper die SU 1.

Lead frame with grooved lead finger

A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.

Methods of adjusting ultrasonic bonding energy on wire bonding machines

A method of adjusting ultrasonic bonding energy on a wire bonding machine, the method comprising the steps of: providing a reference relationship between free air ball squash and ultrasonic bonding energy; determining an actual relationship between free air ball squash and ultrasonic bonding energy on a subject wire bonding machine; and adjusting at least one ultrasonic bonding energy setting of the subject wire bonding machine such that the actual relationship of the subject wire bonding machine is closer to the reference relationship.

Semiconductor device

A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Wedge bonder and a method of cleaning a wedge bonder

Disclosed is a wedge bonder, comprising a wedge for bonding a wire to surfaces to form an electrical interconnection therebetween, a cleaning device for cleaning the wedge, and a positioning device to which the wedge is mounted. In particular, the positioning device is operative to move the wedge to the cleaning device for cleaning. A method of cleaning a wedge of a wedge bonder is also disclosed.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Semiconductor device structures and methods for copper bond pads

A method of making a semiconductor device can comprise forming a copper bond pad on an integrated circuit device; forming a first passivation layer on the integrated circuit device and the copper bond pad; forming a second passivation layer on the first passivation layer; forming a mask over the first and second passivation layers around the copper bond pad; etching the second passivation layer over the copper bond pad; and cleaning the first passivation layer over the copper bond pad. At least a portion of the first passivation layer remains over the copper bond pad after the etching the second passivation layer. A thickness of the first passivation layer over the copper bond pad is selected to protect the copper bond pad from oxidation and to allow wire bonding to the copper bond pad through the first passivation layer.

Power semiconductor module

A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

Multi-segment wire-bond

A multifaceted capillary that can be used in a wire-bonding machine to create a multi-segment wire-bond is disclosed. The multifaceted capillary is shaped to apply added pressure and thickness to an outer segment of the multi-segment wire-bond that is closest to the wire loop. The added pressure eliminates a gap under a heel portion of the multi-segment wire-bond and the added thickness increases a mechanical strength of the heel portion. As a result, a pull test of the multi-segment wire-bond may be higher than a single-segment wire-bond and the multi-segment wire-bond may resist cracking, lifting, or breaking.

POWER MODULE WITH THE INTEGRATION OF CONTROL CIRCUIT

The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased. 1. A power module with the integration of a control circuit , comprising:a power substrate;a power device mounted on the power substrate; andat least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted;wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees.2. The power module according to claim 1 , wherein the power substrate comprises at least one conductive wiring layer on which the power device is disposed.3. The power module according to claim 1 , wherein the at least one control substrate comprises at least one conductive wiring layer and at least one insulation layer claim 1 , and a control device in the control circuit is disposed on the at least one conductive wiring layer.4. The power module according to claim 3 , wherein the at least one control substrate comprises two conductive wiring layers disposed on both sides of the at least one insulation layer claim 3 , ...

Semiconductor device

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad.

PROCESS FOR ELECTRICALLY CONNECTING CONTACT SURFACES OF ELECTRONIC COMPONENTS

A process for electrically connecting contact surfaces of electronic components by capillary wedge bonding a round wire of 8 to 80 μm to the contact surface of a first electronic component, forming a wire loop, and stitch bonding the wire to the contact surface of a second electronic component, wherein the wire comprises a wire core having a silver or silver-based wire core with a double-layered coating comprised of a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold. 1. A process for electrically connecting a contact surface of a first electronic component with a contact surface of a second electronic component comprising the subsequent steps:(1) capillary wedge bonding a wire having a circular cross-section with an average diameter in the range of 8 to 80 μm to the contact surface of the first electronic component,(2) raising the capillary wedge bonded wire to form a wire loop between the capillary wedge bond formed in step (1) and the contact surface of the second electronic component, and(3) stitch bonding the wire to the contact surface of the second electronic component,wherein the capillary wedge bonding of step (1) is carried out with a ceramic capillary having a lower face angle within the range of from zero to 4 degrees,wherein the wire comprises a wire core with a surface, the wire core having a double-layered coating superimposed on its surface,wherein the wire core consists of a material selected from the group consisting of pure silver, doped silver with a silver content of >99.5 wt.-% and silver alloys with a silver content of at least 89 wt.-%, andwherein the double-layered coating comprises a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold.2. The process of claim 1 , (a′) an ultrasonic energy in a range of 50 to 100 mA,', '(b′) a force in a range of 10 to 30 g,', '(c′) a constant velocity in a range of 0.3 to 0.7 μm/s,', '(d′) a contact ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point. 120-. (canceled)21. A method of manufacturing a semiconductor device , comprising:(a) providing a lead frame having a lead, a die pad, and a suspension lead connected to the die pad and bent along a thickness direction of the die pad;(b) after (a), mounting a semiconductor chip on a first surface of the die pad; and(c) after (b), electrically connecting the semiconductor chip with the lead via a conductive member, (c1) providing a stage having a front surface, and a first jig having a first support portion and a second support portion;', '(c2) after (c1), arranging the lead frame over the stage such that a second surface of the die pad, opposite to the first surface, faces the front surface of the stage, and such that a first part of the second surface of the die pad is spaced apart from the front surface of the stage, while a second part of the second surface is contacted with the front surface of the stage, the second part of the second surface being closer to the suspension lead than the first part of the second surface;', '(c3) after (c2), contacting the first part of the second surface of the die pad with the front surface of the stage by pressing the first jig against the first surface of the die pad; and', '(c4) after (c3), connecting the conductive member with the semiconductor chip, while contacting the first and second ...

SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device. 1. A semiconductor device comprising:a semiconductor chip on which electrodes are respectively formed on a front surface side and a back surface side of the semiconductor chip; anda high-thermal-resistant fired layer formed so as to cover at least a part of the electrode formed on the front surface side of the semiconductor chip.2. The semiconductor device according to claim 1 , whereinthe semiconductor chip is disposed on a first substrate electrode, andone end of a wire is bonded onto the high-thermal-resistant fired layer.3. The semiconductor device according to claim 2 , whereinthe wire comprising a copper wire, an aluminum wire, or a clad wire, andthe one end of the wire is bonded thereto by means of an ultrasonic wave.4. The semiconductor device according to claim 1 , whereinthe semiconductor chip is disposed on a first substrate electrode, andone end of a plate-like upper wiring is bonded onto the high-thermal-resistant fired layer by means of solder as a bonding material.5. The semiconductor device according to claim 1 , whereinthe high-thermal-resistant fired layer comprises an silver fired layer.6. The semiconductor device according to claim 1 , whereinthe high-thermal-resistant fired layer comprises a copper fired layer.7. The semiconductor device according to claim 1 , further comprising:a thin film for coating electrode surface disposed between the electrode and the fired layer, the thin film for coating electrode surface comprising one film selected from the group consisting of an gold thin film, a silver ...

PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME

The present disclosure provides a package structure, including a semiconductor chip having a magnetic device, wherein the semiconductor chip includes a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface, and a first magnetic field shielding at least partially surrounding the third surface. 1. A package structure , comprising:a mounting pad having a mounting surface;a semiconductor chip having a magnetic device, a first surface perpendicular to a thickness direction of the semiconductor chip;', 'a second surface opposite to the first surface, wherein the second surface is attached to the mounting surface of the mounting pad, a total area of the mounting surface is greater than a total area of the second surface; and', 'a third surface connecting the first surface and the second surface; and, 'wherein the semiconductor chip comprisesa first magnetic field shielding at least partially surrounding the third surface, wherein a bottom surface of the first magnetic field shielding is attached to the mounting surface of the mounting pad.2. The package structure of claim 1 , wherein the magnetic device has a magnetic component disposed between an Nmetal layer and an (N+1)metal layer.3. The package structure of claim 1 , wherein a height of the first magnetic field shielding is greater than or equal to a thickness of the magnetic device.4. The package structure of claim 1 , further comprising a bonding surface of the semiconductor chip connected to a lead frame by a bonding wire.5. The package structure of claim 4 , further comprising a second magnetic field shielding over the first surface.6. The package structure of claim 5 , wherein the bonding surface of the semiconductor chip is exposed from the second field shielding.7. The package structure of claim 4 , wherein the first magnetic field shielding is disposed between the ...

Semiconductor device manufacturing method

This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor element that is mounted on a substrate, an electrode pad that contains aluminum as a main component and is provided in the semiconductor element, a copper wire that contains copper as a main component and connects a connection terminal provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. When the semiconductor device is heated at 200° C. for 16 hours in the atmosphere, a barrier layer containing any metal selected from palladium and platinum is farmed at a junction between the copper wire and the electrode pad.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating a semiconductor device includes providing a semiconductor die, arranging an electrical connector over the semiconductor die, the electrical connector including a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die, and soldering the electrical connector onto the semiconductor die by heating the solder layer with a laser, wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer. 1. A method for fabricating a semiconductor device , the method comprising:providing a semiconductor die;arranging an electrical connector over the semiconductor die, the electrical connector comprising a conductive core, an absorbing feature arranged on a first side of the conductive core, and a solder layer arranged on a second side of the conductive core, opposite the first side and facing the semiconductor die; andsoldering the electrical connector onto the semiconductor die by heating the solder layer with a laser,wherein the laser irradiates the absorbing feature and absorbed energy is transferred from the absorbing feature through the conductive core to the solder layer.2. The method of claim 1 , wherein the material of the solder layer has a melting point that is lower than a melting point of the material of the conductive core claim 1 , and wherein the absorbed energy is sufficient to melt the material of the solder layer but insufficient to melt the material of the conductive core.3. The method of claim 1 , wherein an absorptance for the laser beam of the absorbing feature is higher than an absorptance for the laser beam of the conductive core.4. The method of claim 1 , wherein the absorbing feature comprises an absorbing layer or an antireflection layer claim 1 , and wherein the absorbing layer or ...

Fine Pitch stud POP Structure and Method

A fine pitch stud POP structure and method is disclosed. The studs are made in bonding pads on the top surface of a lower substrate, which greatly increase the height of the interconnection such as solder balls. In addition, the lower substrate and the upper substrate are connected by reflowing two solder balls on them separately. The two features make the diameter of the bonding balls greatly reduce and further make the pitch between two bonding balls on the lower substrate or the upper substrate greatly reduce, and then the fine pitch POP is achieved. 1. A fine pitch stud POP structure comprising a lower package body and an upper package body , wherein ,the lower package body comprises a lower substrate, at least one chip attached on a die pad of the top surface of the lower substrate and electrically connected with the lower substrate, studs made in bonding pads on the top surface of the lower substrate, solder balls mounted on the studs separately; wherein, the solder balls and the top surface of the lower substrate are pre-molded, and the top of the solder balls is exposed outside of the pre-molded material on the top surface of the lower substrate and is used to connected with the upper package body; wherein,the upper package body comprises an upper substrate, and solder balls mounted on bonding pads on the bottom surface of the upper substrate; wherein,the position and pitch of the solder balls on the bottom surface of the upper substrate match those of the solder balls on the top surface of the lower substrate, and the upper substrate is connected with the lower substrate by reflowing the solder balls on the bottom surface of the upper substrate and the solder balls on the top surface of the lower substrate separately.2. The structure of claim 1 , wherein claim 1 , the at least one chip is flip chip.3. The structure of claim 1 , wherein claim 1 , the lower package body further comprises: solder balls mounted on bonding pads of the bottom surface of the lower ...

Integrated Circuit Device With Wire Bond Connections

An integrated circuit assembly includes a die with a bond pad; a stud bump formed on the bond pad; and a ball bond formed on the stud bump. 1. An integrated circuit assembly comprising:a die with a bond pad;a stud bump formed on said bond pad; anda ball bond formed on said stud bump.2. The integrated circuit of further comprising:a leadframe; anda low modulus of elasticity die mounting material attaching said die to said leadframe.3. The integrated circuit of claim 2 , wherein said low modulus of elasticity die mounting material has a modulus of elasticity of less than about 100 MPa.4. The integrated circuit of further comprising a bond wire integrally formed with said ball bond.5. The integrated circuit of wherein said stud bump is made from gold.6. The integrated circuit of wherein said stud bump is made from copper.7. The integrated circuit of wherein said ball bond is made from gold.8. The integrated circuit of wherein said ball bond is made from copper.9. The integrated circuit of wherein said stud bump and said ball bond are made from the same material.10. The integrated circuit of wherein said stud bump and said ball bond are made from different material.11. A method of forming an integrated circuit assembly comprising:{'sup': '2', 'forming a stud bump on a bond pad on a face of a die that has a face area of less than about 1.00 mm,'}forming a ball bond on the stud bump.12. The method of claim 11 , wherein said forming a stud bump comprises forming a stud bump on a bond pad on a face of a die that has a face area of less than about 0.50 mm.13. The method of further comprising attaching the die to a leadframe with a material having a modulus of elasticity of less than about 100 MPa.14. The method of further comprising attaching the die to a leadframe with a material having a modulus of elasticity of less than about 90 MPa.15. The method of wherein said forming a ball bond comprises forming a ball bond using ultrasonic energy.16. The method of wherein said ...

SEMICONDUCTOR DEVICE

A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 μm to 7 μm. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 μm to 20 μm. 1. A semiconductor device , comprising:a conducting unit that is disposed on a surface of a semiconductor element;a metal film having a thickness ranging from 3 μm to 7 μm that is disposed on a surface of the conducting unit; anda wire having a wire diameter ranging from 500 μm or larger that is bonded to the metal film by wire-bonding using ultrasonic vibration.2. The semiconductor device according to claim 1 , wherein the semiconductor element includes:a semiconductor substrate selected from a silicon substrate and a silicon carbide substrate; andthe conducting unit having, as a major component, aluminum and being disposed on the surface of the semiconductor substrate.3. The semiconductor device according to claim 1 , wherein the metal film has a main component that is nickel.4. The semiconductor device according to claim 3 , wherein the metal film is a nickel alloy film having a main component that is nickel claim 3 , and containing at least one of phosphorus and boron.5. The semiconductor device according to claim 2 , wherein the metal film has a main component that is nickel.6. The semiconductor device according to claim 5 , wherein the metal film ...

SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device. 120-. (canceled)21. A semiconductor device comprising:a semiconductor chip on which first and second electrodes are formed on a front surface side of a semiconductor layer and a third electrode is formed on a back surface side of the semiconductor layer, the semiconductor chip configured to perform a switching operation between the first electrode and the third electrode in accordance with a signal supplied to the second electrode;an insulating film formed to cover a front surface of the semiconductor chip, the first electrode and the second electrode being disposed on a surface of the insulating film, the first electrode and the second electrode being electrically connected to a transistor formed in the semiconductor layer at a position where the first electrode is formed;a metal layer formed so as to cover at least a part of a front side surface of the first electrode; anda wire selected from the group consisting of a plate-like wire and a bonding wire, the wire being connected to the metal layer, whereinan area of the first electrode is larger than an area of the second electrode.22. The semiconductor device according to claim 21 , whereinthe metal layer covers the first electrode, except for a part of the surface of the first electrode.23. The semiconductor device according to claim 22 , whereinan area of the surface of the first electrode covered by the metal layer is larger than an area of the surface of the first electrode not covered by the metal layer.24. The semiconductor device according to claim 21 , ...

Semiconductor package with supported stacked die

Semiconductor packages with electromagnetic interference supported stacked die and a method of manufacture therefor is disclosed. The semiconductor packages may house a stack of dies in a system in a package (SiP) implementation, where one or more of the dies may be wire bonded to a semiconductor package substrate. The dies may be stacked in a partially overlapping, and staggered manner, such that portions of some dies may protrude out over an edge of a die that is below it. This dies stacking may define a cavity, and in some cases, wire bonds may be made to the protruding portions of the die. Underfill material may be provided in the cavity and cured to form an underfill support. Wire bonding of the bond pads overlying the cavity formed by the staggered stacking of the dies may be performed after the formation of the underfill support.

SEMICONDUCTOR DEVICE

A technique is provided that can prevent cracking of a protective film in the uppermost layer of a semiconductor device and improve the reliability of the semiconductor device. Bonding pads formed over a principal surface of a semiconductor chip are in a rectangular shape, and an opening is formed in a protective film over each bonding pad in such a manner that an overlapping width of the protective film in a wire bonding region of each bonding pad becomes wider than an overlapping width of the protective film in a probe region of each bonding pad. 119-. (canceled)20. A semiconductor device , comprising:a semiconductor chip having a first main surface, a second main surface opposite the first main surface, a side extending in a first direction, and a plurality of bonding pads formed on the first main surface and extending along the side,each of the bonding pads having a first side and a second side opposite the first side, extending in the first direction,wherein the first main surface of the semiconductor chip is covered by a protective film in which a plurality of openings are formed, andwherein a peripheral portion of an upper surface of each of the bonding pads is covered by the protective film and a portion other than the peripheral portion of the upper surface of each of the bonding pads is exposed from a corresponding one of the openings. The disclosure of Japanese Patent Application No. 2009-121857 filed on May 20, 2009 including the specification, drawings and abstract is incorporated herein by reference in its entirety.The present invention relates to a semiconductor device, in particular, to a technique effective to be applied to a semiconductor device with a semiconductor chip, having bonding pads, mounted thereon.Japanese Patent Laid-Open No. 1991-79055 (Patent Document 1), for example, discloses an electrode pad provided with a first portion to bond a wire or a film lead and a second portion that is integrally linked to the first portion, can be ...

NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE USING NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME

A noble metal-coated silver bonding wire suppresses corrosion at the bonding interface under severe conditions of high temperature and high humidity, and the noble metal-coated silver bonding wire can be ball-bonded in the air. The noble metal-coated silver wire for ball bonding is a noble metal-coated silver wire including a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes a palladium intermediate layer and a gold skin layer, the palladium content relative to the entire wire is 0.01 mass % or more and 5.0 mass % or less, the gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, and the sulfur group element content relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less. 1. A noble metal-coated silver wire for ball bonding comprising a noble metal coating layer on a core material made of pure silver or a silver alloy ,wherein the wire contains at least one sulfur group element,the noble metal coating layer comprises a palladium intermediate layer and a gold skin layer,a palladium content relative to an entire wire is 0.01 mass % or more and 5.0 mass % or less,a gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, anda content of the sulfur group element relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less.2. The noble metal-coated silver wire for ball bonding according to claim 1 , wherein the noble metal coating layer further comprises a gold intermediate layer on a core material surface of the palladium intermediate layer.3. The noble metal-coated silver wire for ball bonding according to claim 1 , wherein the core material further contains copper claim 1 , and a copper content relative to the entire wire is 0.005 mass % or more and 2.0 mass % or less.46-. (canceled)7. A semiconductor device comprising at least one ...

Support terminal integral with die pad in semiconductor package (as amended)

A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.

Methods to fabricate integrated circuits by assembling components

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.

WIRE BOND CONNECTION WITH INTERMEDIATE CONTACT STRUCTURE

Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag). 122.-. (canceled)23. A packaged integrated circuit (IC) device comprising:a substrate;one or more IC dies including a first IC die, wherein a first conductive pad is formed at a first side of the first IC die, wherein the substrate or an IC die other than the first IC die includes a second side, and wherein a second conductive pad is formed at the second side;a first bump disposed on one of the first conductive pad and the second conductive pad; anda first wire coupled between the first conductive pad and the second conductive pad, wherein a distal end of the first wire is bonded via the first bump to the one of the first conductive pad and the second conductive pad, wherein a first hardness of the first wire is more than a second hardness of the first bump and wherein a third hardness of the one of the first conductive pad and the second conductive pad is more than the second hardness.24. The packaged IC device of claim 23 , wherein the first wire includes copper (Cu).25. The packaged IC device of claim 24 , wherein the first bump includes gold (Au) or silver (Ag).26. The packaged IC device of claim 25 , wherein the one of the first ...

WIRE BONDING METHODS AND SYSTEMS INCORPORATING METAL NANOPARTICLES

Wire bonding operations can be facilitated through the use of metal nanoparticle compositions. Both ball bonding and wedge bonding processes can be enhanced in this respect. Wire bonding methods can include providing a wire payout at a first location from a rolled wire source via a dispensation head, contacting a first metal nanoparticle composition and a first portion of the wire payout with a bonding pad, and at least partially fusing metal nanoparticles in the first metal nanoparticle composition together to form an adhering interface between the bonding pad and the first portion of the wire payout. The adhering interface can have a nanoparticulate morphology. Wire bonding systems can include a rolled wire source, a dispensation head configured to provide a wire payout, and an applicator configured to place a metal nanoparticle composition upon at least a portion of the wire payout or upon a bonding pad. 1. A method comprising:providing a wire payout at a first location from a rolled wire source via a dispensation head;contacting a first metal nanoparticle composition and a first portion of the wire payout with a bonding pad in electrical communication with an electronic component; andat least partially fusing metal nanoparticles in the first metal nanoparticle composition together to form an adhering interface between the bonding pad and the first portion of the wire payout.2. The method of claim 1 , further comprising:applying pressure and ultrasonic energy to the first metal nanoparticle composition via the dispensation head.3. The method of claim 1 , further comprising:moving the dispensation head to a second location;contacting a second portion of the wire payout with a lead at the second location;adhering the wire payout to the lead, thereby forming a wire loop extending between the bonding pad and the lead; andsevering the wire payout from the wire loop.4. The method of claim 3 , further comprising:contacting a second metal nanoparticle composition and the ...

ELECTRONIC CHIP DEVICE WITH IMPROVED THERMAL RESISTANCE AND ASSOCIATED MANUFACTURING PROCESS

An electronic chip device with improved thermal resistance comprises at least one electrical connection pad with an electrical interconnection link, at least one thermal pad arranged on a face of the chip, at least one heat exchange element, and at least one thermal link between a thermal pad and a heat exchange element. 1. A stack of at least one electronic chip device with improved thermal resistance comprising at least one electrical connection pad with an electrical interconnection link , at least one thermal pad arranged on a face of the chip , at least one heat exchange element , and at least one thermal link between a thermal pad and a heat exchange element , wherein a portion of a heat exchange element , said portion being situated facing an electrical connection pad , with an electrical interconnection link , of an electronic chip comprises an aperture preventing contact with said electrical interconnection link.2. The stack as claimed in claim 1 , wherein said heat exchange element comprises tabs arranged facing the corners of the corresponding chip.3. The stack as claimed in claim 1 , wherein the electronic chip device(s) comprise a portion of said heat exchange element claim 1 , said portion being arranged facing a thermal pad claim 1 , comprising an aperture.4. The stack as claimed in claim 1 , wherein the thermal link(s) of the electronic chip device(s) comprise at least one thermally conductive wire.5. The stack as claimed in claim 1 , wherein the face of a chip comprising at least one thermal pad is the active face of the chip.6. The stack as claimed in claim 5 , wherein a portion of a heat exchange element claim 5 , said portion being situated facing electrical connection pads claim 5 , with an electrical interconnection link of an electronic chip is raised in such a way as to avoid contact with said electrical interconnection link.7. The stack as claimed in claim 1 , wherein the front face of a chip comprising at least one thermal pad is the ...

Method for Soldering an Insulating Substrate onto a Carrier

A method for soldering an insulating substrate onto a substrate mounting portion of a carrier by a predefined solder is provided. The insulating substrate includes a dielectric insulation carrier, a top side, and a bottom side opposite to the top side. The method includes selecting the insulating substrate based on a criterion which indicates that the insulating substrate, if it has the solidus temperature of the solder, has a positive unevenness. The insulating substrate is soldered on the bottom side to the substrate mounting portion, such that, after the soldering, the solidified solder extends continuously from the bottom side of the insulating substrate as far as the substrate mounting portion. The top side of the insulating substrate is populated with at least one semiconductor chip. 1. A method for soldering an insulating substrate onto a substrate mounting portion of a carrier by a predefined solder , wherein the insulating substrate comprises a dielectric insulation carrier , a top side , and a bottom side opposite to the top side , the method comprising:selecting the insulating substrate based on a criterion which indicates that the insulating substrate, if it has the solidus temperature of the solder, has a positive unevenness;soldering the insulating substrate on the bottom side to the substrate mounting portion, such that, after the soldering, the solidified solder extends continuously from the bottom side of the insulating substrate as far as the substrate mounting portion; andpopulating the top side of the insulating substrate with at least one semiconductor chip.2. The method of claim 1 , wherein the criterion indicates that the insulating substrate claim 1 , if it is heated proceeding from an initial temperature which is lower than the solidus temperature of the solder up to a predefined maximum temperature which is higher than the liquidus temperature of the solder claim 1 , and then cooled claim 1 , such that it reaches the solidus temperature of ...

METHOD FOR MANUFACTURING WIRE BONDING STRUCTURE, WIRE BONDING STRUCTURE, AND ELECTRONIC DEVICE

A manufacturing method for a wire bonding structure of the present invention includes a step of preparing a wire made of Cu and a step of joining the wire to a first joining target formed on an electronic device. Before the joining step, the wire has an outer circumferential surface and a withdrawn surface. The withdrawn surface is withdrawn toward a central axis of the wire from the outer circumferential surface. In the joining step, ultrasonic vibration is applied to the wire in a state in which the withdrawn surface is pressed against the first joining target. 1. A manufacturing method for a wire bonding structure , the method comprising:a step of preparing a wire made of Cu: anda step of joining the wire to a first joining target formed on an electronic device;wherein before the joining step, the wire has an outer circumferential surface and a withdrawn surface,the withdrawn surface is withdrawn toward a central axis of the wire from the outer circumferential surface, andin the joining step, ultrasonic vibration is applied to the wire in a state in which the withdrawn surface is pressed against the first joining target.2. The manufacturing method according to claim 1 , wherein the withdrawn surface is flat at a point in time of starting the joining step.3. The manufacturing method according to claims 1 , further comprising a step of forming the withdrawn surface by pressing the wire against a pressing target before the joining step.4. The manufacturing method according to claim 3 , wherein the pressing target is made of a ceramic material or a metal.5. The manufacturing method according to claim 3 , further comprising a step of preparing a wedge for pressing the wire claim 3 ,wherein in the step of forming the withdrawn surface, the wire is pressed against the pressing target by the wedge, andin the step of joining the wire to the first joining target, the wire is pressed against the first joining target by the wedge.6. The manufacturing method according to ...

Semiconductor device and production method therefor

An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.

SYSTEMS AND METHODS TO FABRICATE A RADIO FREQUENCY INTEGRATED CIRCUIT

To reduce radio frequency losses during operation of a radio frequency integrated circuit module, the radio frequency integrated circuit module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the radio frequency current to flow around the high-resistivity material, which reduces the radio frequency signal loss associated with the high resistivity plating material. 1. A radio frequency integrated circuit module comprising:a substrate;a radio frequency integrated circuit die supported by the substrate;a copper trace including at least a sidewall and formed on the substrate;a nickel layer plated over a portion of a top surface of the copper trace;a palladium layer plated over the nickel layer; anda gold layer plated over the palladium layer, the nickel, palladium, and gold layers forming a wire bonding pad that covers a plated portion of the top surface copper trace and does not cover an unplated portion of the top surface of the copper trace that is substantially parallel to the wire bonding pad, a width of the unplated portion extending from a periphery of the wire bonding pad to the sidewall, a lead of the radio frequency integrated circuit die bonded to the wire bonding pad.2. The radio frequency integrated circuit module of wherein the width of the unplated portion of the top surface of the copper trace is at least approximately 50 microns.3. The radio frequency integrated circuit module of wherein the width of the unplated portion of the top surface of the copper trace is approximately 50 microns to approximately 100 microns.4. The radio frequency integrated circuit module of wherein the width of the unplated portion of the top surface of the copper trace is approximately 20 microns to approximately 200 microns.5. The radio frequency integrated circuit module of wherein the unplated portion of the ...

Semiconductor device

A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed. 119-. (canceled)20. A method of manufacturing a semiconductor device , including the steps of:(a) providing a lead frame having a first metal plate, a plurality of leads arranged in juxtaposition with the first metal plate, and a frame portion coupled to the first metal plate and to the leads;(b) mounting a semiconductor chip over a first surface of the first metal plate of the lead frame and electrically coupling the semiconductor chip to the leads;(c) sealing the entire semiconductor chip, a portion of the first metal plate, and a portion of each of the leads with a resin to form a sealing body;(d) forming a first metal film over a portion of the lead frame which is exposed from the sealing body using an electrolytic plating method; and(e) after the step (d), cutting each of the leads to separate the leads from the frame portion,wherein the first metal plate has a second surface opposite to the first surface and a plurality of side surfaces located between the first and second surfaces,wherein the side surfaces of the first metal plate include:a first side surface provided to face ...

METHODS AND APPARATUS FOR IMPROVED BONDING

Various embodiments of the present technology may comprise a method and apparatus for improved bonding and may operate in conjunction with a main platform configured to support a substrate. Movable members may allow the substrate to be positioned on the main platform when rotated to a first position and apply a force to a predetermined area on an upward facing surface of the substrate when rotated to the second position. 1. An apparatus for securing a substrate , comprising:a main platform configured to support the substrate; allows the substrate to be positioned on the main platform when rotated to the first position; and', 'applies a force to a predetermined area on an upward facing surface of the substrate when rotated to the second position., 'a plurality of movable members positioned above the main platform and rotatable between a first position and a second position, wherein each movable member2. The apparatus of claim 1 , wherein:a first movable member from the plurality of movable members applies a first force to a first surface area of upward facing surface of the substrate when rotated to the second position; anda second movable member from the plurality of movable members applies a second force to a second surface area of the upward facing surface of the substrate when rotated to the second position.3. The apparatus of claim 2 , wherein the first surface area comprises an area substantially adjacent to and including a centerline of the substrate.4. The apparatus of claim 2 , wherein the second surface area comprises an area along an edge portion of the substrate.5. The apparatus of claim 1 , wherein a first movable member from the plurality of movable members secures the substrate at a first predetermined time and a second movable member from the plurality of movable members secures the substrate at a second predetermined time.6. The apparatus of claim 1 , wherein the main platform comprises:a plurality of openings disposed along the main platform; anda ...

Chip package, method of forming a chip package and method of forming an electrical contact

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

Electronic package for integrated circuits and related methods

Electronic packages and related methods are disclosed. An example electronic package apparatus includes a substrate and an electronic component. A protective material is positioned on a first surface, a second surface and all side surfaces of the electronic component to encase the electronic component. An enclosure is coupled to the substrate to cover the protective material and the electronic component.

Power module

A power module includes: a base plate having a first surface; electrode plate provided at the first surface; a wire connected to a semiconductor chip and the electrode plate; a metal member connected to the electrode plate; a terminal plate; a first resin layer, a connection portion of the wire and the semiconductor chip being disposed inside the first resin layer; and a second resin layer provided on the first resin layer and having a lower elastic modulus than the first resin layer. The terminal plate includes a bonding portion contacting an upper surface of the metal member, a curved portion curved upward from the bonding portion. The curved portion is disposed inside the second resin layer, and a length from the first surface of a lower surface of the bonding portion is greater than a length from the first surface of the connection portion.

FLOATING DIE PACKAGE

A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only. 1. A semiconductor package comprising:a lead frame including a die paddle and a first plurality of conductors and a second plurality of conductors;a first semiconductor die electrically connected to the first plurality of conductors through a first set of bond wires;a second semiconductor die electrically connected to the second plurality of conductors through a second set of bond wires, the second semiconductor die attached to the first semiconductor die;a molding structure covering portions of the lead frame, the first semiconductor die, the second semiconductor die, the first set of bond wires, and the second set of bond wires; anda cavity within the molding structure and covering portions of top surfaces of the first semiconductor die and attached to the second semiconductor die, wherein a portion of the cavity is in between the first semiconductor die and the die paddle, wherein one surface of each of the first plurality of conductors and two surfaces of each of the second plurality of conductors are exposed from the semiconductor package, and wherein the first semiconductor die is suspended by the first set of bond wires to float inside the cavity.2. The semiconductor package of claim 1 , wherein the second set of bond wires is below the first set of bond wires in a cross-sectional view of the semiconductor package.3. The semiconductor package of further comprising a film layer in contact with portions of the molding structure and covering a portion of the cavity.4. The semiconductor package of claim 3 , wherein the film layer includes a screen-printed film.5. The ...

Wire bonding apparatus and wire bonding method

A wire bonding apparatus according to an embodiment bonds a wire to a bonding portion by generating an ultrasonic vibration in a state of pressing the wire onto the bonding portion. The wire bonding apparatus includes a bonding tool that causes the wire to contact the bonding portion and applies a load, an ultrasonic horn that generates the ultrasonic vibration, a load sensor that continuously detects the load applied from the bonding tool to the bonding portion, and a controller that controls the operation of the bonding tool and the ultrasonic horn. The controller analyzes data of the load output from the load sensor between when the wire contacts the bonding portion and when the ultrasonic vibration is generated, and controls the operation of the bonding tool and the ultrasonic horn based on an analysis result.

Nanostructure barrier for copper wire bonding

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Wedge tool and wedge bonding method

A bonding tool includes a wedge tool that presses a bonding wire against a principal plane of a structure such as an electrode to which the bonding wire is to be bonded. A groove formed in an end portion of a wedge tool body of the wedge tool is inclined along a longitudinal direction of the bonding wire so that a heel side of the groove is closer to the principal plane of the structure than a toe side of the groove. As a result, the wedge tool is inclined at a tilt angle and the bonding wire fits the groove in the end portion of the wedge tool body along the longitudinal direction of the bonding wire. Thus, a corner portion of the wedge tool does not contact the electrode.

CAPILLARY TRANSPORT DEVICE, CAPILLARY MOUNTING DEVICE, CAPILLARY REPLACEMENT DEVICE, CAPILLARY TRANSPORT METHOD, CAPILLARY MOUNTING METHOD, AND CAPILLARY REPLACEMENT METHOD

There is provided a capillary transport device capable of inserting, without manpower, a capillary into a mounting section of an ultrasonic horn. According to an aspect of the present invention, a capillary transport device includes: a first tube for transporting a capillary ; an ultrasonic horn with a mounting section for mounting the capillary; a first movement mechanism for relatively moving the ultrasonic horn and a first end of the first tube; and a mechanism for blowing gas into a second end of the first tube. 1. A capillary transport device comprising:a first tube for transporting a capillary;an ultrasonic horn with a mounting section for mounting said capillary;a first movement mechanism for relatively moving said ultrasonic horn and a first end of said first tube; anda mechanism for blowing gas into a second end of said first tube.2. The capillary transport device according to claim 1 , wherein said mechanism for blowing gas includes a second tube for pushing said capillary into the second end of said first tube and a second movement mechanism for moving said second tube.3. The capillary transport device according to claim 2 , further comprising a block arranged at the first end of said first tube and made of a material harder than said first tube.4. A capillary mounting device comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the capillary transport device according to any one of ; and'}a mechanism for fixing said capillary to said mounting section.5. A capillary replacement device comprising:{'claim-ref': {'@idref': 'CLM-00004', 'claim 4'}, 'the capillary mounting device according to ;'}a mechanism for removing said capillary fixed to said mounting section; anda mechanism for sucking gas from the second end of said first tube.6. A capillary replacement device comprising:a fourth tube for transporting a first capillary;a first tube for transporting a second capillary;an ultrasonic horn with a mounting section for mounting said first or second ...

Resin sealing type semiconductor device and method of manufacturing the same, and lead frame

The invention is directed to firm bonding between semiconductor dies etc bonded to a lead frame and wire-bonding portions of the lead frame by ultrasonic Al wire bonding, and the prevention of shortcircuit between the semiconductor dies etc due to a remaining portion of the outer frame of the lead frame after the outer frame is cut. By extending the wire-bonding portion etc on the lead frame in a wire-bonding direction and connecting the wire-bonding portion etc to the outer frame of the lead frame through a connection lead etc, the ultrasonic vibration force in the ultrasonic Al wire bonding is prevented from dispersing and the Al wire and the wire-bonding portion etc are firmly bonded. The outer frame is cut after a resin sealing process is completed. Even when a portion of the outer frame remains on the side surface of the resin package, connection between the connection lead etc and other hanging lead etc are prevented by providing a notch etc in the outer frame between the connection lead etc and the hanging lead etc.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A method for manufacturing a semiconductor device includes: a first bonding process including bonding, at a first bonding point, a tip of a wire held by a capillary; a first lifting process including moving the capillary upward; a first reverse process including moving the capillary in a direction that includes a component in a first direction that is from a second bonding point toward the first bonding point; a second lifting process including moving the capillary upward; a second reverse process including moving the capillary in the first direction; a third lifting process including moving the capillary upward; a forward process including moving the capillary toward the second bonding point; and a second bonding process including bonding the wire at the second bonding point. A movement distance of the capillary in the first lifting process is not less than a movement distance of the capillary in the second lifting process. 1. A method for manufacturing a semiconductor device , the method comprising:a first bonding process comprising bonding, at a first bonding point, a tip of a wire held by a capillary;a first lifting process comprising moving the capillary upward;a first reverse process comprising moving the capillary in a direction that includes a component in a first direction, the first direction being from a second bonding point toward the first bonding point;a second lifting process comprising moving the capillary upward;a second reverse process comprising moving the capillary in the first direction;a third lifting process comprising moving the capillary upward;a forward process comprising moving the capillary toward the second bonding point; anda second bonding process comprising bonding the wire at the second bonding point,wherein a movement distance of the capillary in the first lifting process is not less than a movement distance of the capillary in the second lifting process.2. The method according to claim 1 , further comprising a third reverse process ...

Semiconductor device

An object of the present invention is to stabilize and strengthen the strength of a bonding part between a metal electrode on a semiconductor chip and metal wiring connected thereto using a simple structure. Provided is a semiconductor device including a metal layer 130 on a surface of a metal electrode 120 formed on a semiconductor chip 110 , the metal layer 130 consisting of a metal or an alloy different from a constituent metal of the metal electrode 120 , metal wiring 140 is connected to the metal layer 130 via a bonding part 150 , wherein the constituent metal of the metal layer 130 is a metal or an alloy different from the constituent metal of the metal electrode 120 , and the bonding part 150 has an alloy region harder than the metal wiring 140.

Gallium arsenide devices with copper backside for direct die solder attach

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Direct die solder (DDS) attach can be achieved by use of electroless nickel plating of the copper contact layer followed by a palladium flash. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Laser module and method of manufacturing the same

A laser module includes an optical fiber, a laser device, an optical system, a housing, a lead terminal, a conductive wire, and an insulation member. The laser device emits a laser beam. The optical system couples the laser beam, emitted from the laser device, to the optical fiber. The housing includes a base plate on which the laser device is fixed and a side wall that includes an opening. The lead terminal extends from an outside of the housing through the opening of the side wall into the housing. The conductive wire electrically connects a connecting portion of the lead terminal, located within the housing, to the laser device. The insulation member includes a seal portion and an extension portion.

Semiconductor device having first and second electrode layers electrically disconnected from each other by a slit

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

Ribbon bonding tools, and methods of designing ribbon bonding tools

A ribbon bonding tool is provided. The ribbon bonding tool includes a body portion including a tip portion, the tip portion defining a working surface. The ribbon bonding tool includes a group of four protrusions extending from the working surface, wherein the working surface defines four quadrants in a horizontal plane by extending an imaginary line at a midpoint along each of a length and a width of the working surface. Each of the four protrusions is arranged in one of four quadrants.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

In a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower die cavity block with which the tip-end surface of each push-up pin is contacted are inclined in such a manner that a distance to a top surface of the lower die cavity block becomes longer towards the pot side where mold resin is supplied. When the lower die cavity block is returned to the initial position, the lower die cavity block is lifted while being slightly moved towards the pot block side. No gap is formed between a side surface of the pot block and a side surface of the lower die cavity block. 1. A manufacturing method of a semiconductor device comprising the steps of:(a) preparing a mold die including an upper die having an upper die cavity block, a lower die having a lower die cavity block and push-up pins, and a pot block having a pot that supplies resin;(b) preparing a semiconductor chip mounted over an upper surface of a substrate;(c) disposing the substrate over a surface of the lower die cavity block;(d) clamping the substrate between the upper die and the lower die so that the semiconductor chip is located in an upper die cavity of the upper die cavity block;(e) supplying the resin into the upper die cavity from the pot of the pot block to seal the semiconductor chip with resin; and(f) inserting each push-up pin into a hole formed in the rear surface opposite to the surface of the lower die cavity block and pressing the same against an inner wall of the hole to return the lower die cavity block sunk in the step (d) to the initial position,wherein a part of a side surface of the hole into which each push-up pin is inserted is inclined to the direction in which the diameter of the hole becomes smaller from the rear surface side of the lower die cavity block towards the surface side.2. The manufacturing method of a semiconductor device according to claim 1 ,wherein the two or more push-up pins ...

Methods of forming wire interconnect structures

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.

Aluminum coated copper ribbon

A ribbon, preferably a bonding ribbon for bonding in microelectronics, contains a first layer containing copper, a coating layer containing aluminum superimposed over the first layer, and an intermediate layer. In a cross-sectional view of the ribbon, the area share of the first layer is from 50 to 96% and the aspect ratio between the width and the height of the ribbon in a cross-sectional view is from 0.03 to less than 0.8. The ribbon has a cross-sectional area of 25,000 μm 2 to 800,000 μm 2 . The intermediate layer contains at least one intermetallic phase containing materials of the first and coating layers. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing the wire, to a propelled device comprising said electric device and to a process of connecting two elements through the wire by wedge-bonding.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device includes a circuit board including an insulating layer having opposite front and rear surfaces, an electrode pad disposed on the front surface, a housing having an installation area for the circuit board, and a bonding material embedded in a recess within either a first area located at the rear surface of the insulating layer directly below an area of the circuit board in which the electrode pad is disposed, or at a second area located within the installation area of the housing and corresponding to the first area in a plan view. 1. A semiconductor device , comprising:a circuit board including an insulating layer having a front surface and a rear surface opposite to the front surface, and an electrode pad disposed on said front surface;a housing having an installation area within which the circuit board is disposed; anda bonding material embedded in a recess disposed in a first area or a second area, whereinthe first area is located at the rear surface of the insulating layer and is an area directly below an area of the circuit board in which the electrode pad is disposed, andthe second area is located within said installation area and at an area corresponding to the first area in a plan view of the semiconductor device.2. The semiconductor device according to claim 1 , further comprising a groove portion claim 1 , which includes the recess.3. The semiconductor device according to claim 1 , whereinthe electrode pad has a bonding area to which a bonding wire is bonded,the recess is disposed in a third area within the first area or a fourth area within the second area, andthe third area is located at the rear surface of the insulating layer, and at an area directly below the bonding area, andthe fourth area is located within said installation area of the housing and at an area corresponding to the third area in the plan view.4. The semiconductor device according to claim 3 , wherein a width of the recess is in a range of 0.8 times to 1.2 times a ...

WIRE BONDING METHODS AND SYSTEMS INCORPORATING METAL NANOPARTICLES

Wire bonding operations can be facilitated through the use of metal nanoparticle compositions. Both ball bonding and wedge bonding processes can be enhanced in this respect. Wire bonding methods can include providing a wire payout at a first location from a rolled wire source via a dispensation head, contacting a first metal nanoparticle composition and a first portion of the wire payout with a bonding pad, and at least partially fusing metal nanoparticles in the first metal nanoparticle composition together to form an adhering interface between the bonding pad and the first portion of the wire payout. The adhering interface can have a nanoparticulate morphology. Wire bonding systems can include a rolled wire source, a dispensation head configured to provide a wire payout, and an applicator configured to place a metal nanoparticle composition upon at least a portion of the wire payout or upon a bonding pad. 1. An electrical package comprising:a bonding pad in electrical communication with an electronic component;a lead;a wire loop extending between the bonding pad and the lead; andan adhering interface having a nanoparticulate structure disposed between the wire loop and at least one of the bonding pad and the lead.2. The electrical package of claim 1 , wherein the adhering interface is present between the wire loop and both the bonding pad and the lead.3. The electrical package of claim 1 , wherein the wire loop comprises a copper wire claim 1 , a gold wire claim 1 , an aluminum wire claim 1 , a silver wire claim 1 , carbon nanotube ropes claim 1 , a drawn carbon nanotube fiber claim 1 , or any combination thereof.4. The electrical package of claim 1 , wherein the adhering interface is formed from a copper nanoparticle composition.5. The electrical package of claim 1 , wherein the wire loop comprises a copper wire and the adhering interface is formed from a copper nanoparticle composition.6. The electrical package of claim 1 , wherein the lead is disposed on the ...

DETECTION OF FOREIGN PARTICLES DURING WIRE BONDING

A method of bonding wires onto surfaces, an apparatus and a computer program product are disclosed. The method of bonding wires onto surfaces, comprises the steps of: collecting operating characteristics of a bonding tool while forming a wire bond which bonds a wire to a surface; determining whether a possible bonding failure of the wire bond has occurred as indicated by the operating characteristics; and capturing an image of the wire bond to identify whether a foreign body is present on the surface if it is determined that a possible bonding failure has occurred. In this way, imaging of the wire bond is only necessary when the operating characteristics indicate a suspect bonding failure has occurred. This avoids the need to image every bond, while still imaging suspect bonds. This approach helps to significantly increase the throughput of the wire bonding apparatus whilst still identifying and classifying bonding defects due to the presence of a foreign body. 1. A method of bonding wires onto surfaces , comprising the steps of:collecting operating characteristics of a bonding tool while forming a wire bond which bonds a wire to a surface;determining whether a possible/likely/potential/suspect/suspected bonding failure of said wire bond has occurred as indicated by said operating characteristics; andcapturing an image of said wire bond to identify whether a foreign particle is present on said surface if it is determined that a possible bonding failure has occurred.2. The method of claim 1 , wherein said operating characteristics comprise at least one of energy consumed by said bonding tool and a deformation of said wire while forming said wire bond.3. The method of claim 1 , wherein said operating characteristics comprise at least one of energy consumed by said bonding tool and a deformation of said wire over a bonding period while forming said wire bond.4. The method of claim 1 , wherein said bonding tool comprises an ultrasonic transducer operable to supply ...

Power Semiconductor Chip, Method for Producing a Power Semiconductor Chip, and Power Semiconductor Device

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

Method for manufacturing a semiconductor device

After a die bonding step, a wire bonding step is performed to electrically connect the plurality of pad electrodes and the plurality of leads of the semiconductor chip via a plurality of copper wires. A plating layer is formed on a surface of the lead, and a copper wire is connected to the plating layer in the wire bonding step. The plating layer is a silver plating layer. After the die bonding step, an oxygen plasma treatment is performed on the lead frame and the semiconductor chip before the wire bonding step, and then the surface of the plating layer is reduced.

Wire bonding assembly and method

A method of wire bonding a die to a lead frame comprising mounting the die on a die attachment pad portion of a leadframe and supporting the leadframe on a support plate having a vacuum hole therein filled with porous material.

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. 1. A method of forming a semiconductor assembly , comprising:forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;attaching the support member to a die having a second bond-site;disposing an encapsulant adjacent to the pedestal;removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; andforming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.2. The method of wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal.3. The method of claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly.4. A method of forming a stacked semiconductor assembly claim 2 , comprising:singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second ...

Semiconductor device

A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.

Environmental hardened packaged integrated circuit

A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a modified extracted die, which includes one or more extended bond pads, a package comprising a base and a lid, and a plurality of new bond wires. The modified extracted die is placed into a cavity of the base. After the modified extracted die is placed into the cavity, the plurality of new bond wires are bonded between the one or more extended bond pads of the modified extracted die and package leads of the package base or downbonds. After bonding the plurality of new bond wires, the lid is sealed to the base. 1. A method for assembling a packaged integrated circuit for operating reliably at elevated temperatures , the method comprising:providing an extended bond pad over an original die pad of an extracted die to create a modified extracted die, wherein the extracted die is a functional semiconductor die that has been removed from a finished packaged integrated circuit;placing the modified extracted die into a cavity of a package base;bonding a new bond wire between the extended bond pad and a lead of the package base or a downbond; andsealing a package lid to the package base.2. The method as recited in claim 1 , the extended bond pad comprising a plurality of layers claim 1 , wherein at least one of the layers of the plurality of layers is a different conductive material than a different layer of the plurality of layers.3. The method as recited in claim 1 , the extended bond pad comprising a first portion over the original die pad and a second portion adjacent to and connected to the first portion claim 1 , wherein the first portion covers an original ball bond on the extracted die claim 1 , if an original ball bond is present.4. The method as recited in claim 3 , wherein providing the extended bond pad comprises:sputtering a redistribution layer comprising the extended bond pad on the extracted die, the redistribution layer ...

CORROSION-RESISTANT COPPER BONDS TO ALUMINUM

A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads. The packaged device is treated for at least one cycle at a temperature in the range from about 250° C. to 270° C. for a period of time in the range from about 20 s to 40 s. 16- (canceled)7. A method for fabricating a semiconductor device comprising:providing a packaged semiconductor device having copper ball bonds attached to aluminum pads; andtreating the packaged device for at least one cycle at a temperature in the range from about 250° C. to 270° C. for a period of time in the range from about 20 s to 40 s.8. The method of wherein the process of treating is repeated for two or more cycles.9. The method of wherein the process of treating is preceded by the process of a cycle at a temperature of about 125° C. for a time of about 24 h.10. The method of wherein the process of providing is preceded by the processes of:heating a semiconductor chip having an aluminum bond pad to a first temperature;forming a free air ball from the end piece of a copper wire protruding from the tip of a bonder capillary;contacting the ball to the pad and applying force and ultrasonic energy to the ball for a first period of time to squash and attach the ball to the pad; andafter cooling down, encapsulating the chip with the bond pad and the squashed ball in a packaging compound.11. The method of wherein the packaging compound is a thermoset compound and the encapsulating process is followed by a compound polymerization process at a temperature of about 175° C. for a time in the range from about 4 h to 6 h.12. The method of wherein the first temperature is between about 165 and 250° C. and the first period of time between about 10 and 20 ms claim 10 , while the pad onto which the ball is attached is at the first temperature for a time period between about 2 and 30 minutes. This application is a Divisional of and claims priority to U ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Method for manufacturing a semiconductor device includes: preparing a first subassembly in which an upper surface of the conductive spacer is soldered on the second conductive member and preliminary solder is provided on a lower surface of the conductive spacer; preparing a second subassembly in which the lower surface of the semiconductor element is soldered on the first conductive member and the bonding wire is joined on upper surface of the semiconductor element; and soldering the upper surface of the semiconductor element in the second subassembly on the lower surface of the conducive spacer in the first subassembly by melting the preliminary solder in the first subassembly 1. Method for manufacturing a semiconductor device which comprises a semiconductor element , a first conductive member joined on a lower surface of the semiconductor element , a second conductive member joined on an upper surface of the semiconductor element via a conductive spacer , and a copper bonding wire joined on the upper surface of the semiconductor element , the method comprising:preparing a first subassembly in which an upper surface of the conductive spacer is soldered on the second conductive member and preliminary solder is provided on a lower surface of the conductive spacer;preparing a second subassembly in which the lower surface of the semiconductor element is soldered on the first conductive member and the bonding wire is joined on the upper surface of the semiconductor element; andsoldering the upper surface of the semiconductor element in the second subassembly on the lower surface of the conducive spacer in the first subassembly by melting the preliminary solder in the first subassembly.2. The method according to claim 1 , wherein the conductive spacer comprises a concave portion formed along a peripheral edge of the lower surface of the conductive spacer.3. The method according to claim 1 , wherein the preparing of the first subassembly comprises soldering the conductive ...

ELECTRONIC DEVICES AND PROCESS OF FORMING THE SAME

A process of forming an electronic device includes providing a wire comprising a first ball at an end thereof, operating on the first ball to modify a surface of the first ball to form a modified surface, moving the first ball to a first location on a die, and bonding the first ball along the modified surface to the first location of the die. In an embodiment, the process further includes moving a bonding tool including the wire away from the die while the wire remains bonded to the die. In another embodiment, 1. A process of forming an electronic device comprising:providing a wire comprising a first ball at an end thereof;operating on the first ball to modify a surface of the first ball to form a modified surface;moving the first ball to a first location on a die; andbonding the first ball along the modified surface to the first location of the die,wherein the modified surface comprises a pattern including a hatching, a concentric arcuate shape, a nonconcentric arcuate shape, a concentric polygonal shape, a nonconcentric polygonal shape, a zig-zag pattern, a dot matrix, a honeycomb, or any combination thereof.2. The process of claim 1 , further comprising:moving a bonding tool including the wire away from the die while the wire remains bonded to the die.3. The process of claim 2 , further comprising:forming a second ball at a newly formed end of the wire;operating on the second ball to modify a surface of the second ball to form a modified surface;moving the second ball to a second location on the die; andbonding the second ball along the modified surface to the second location of the die.4. The process of claim 1 , wherein the die comprises a bond pad material exposed at the first location and bonding the modified surface of the first ball to the die is performed such that at least 20% of an original bond pad material thickness remains under the modified surface after bonding is complete.5. The process of claim 1 , wherein operating on the first ball is performed ...

SEMICONDUCTOR DEVICE

A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the opening region of the frame body and on which semiconductor chips are mounted, lead portions, each including an inclined portion that is at least partially exposed to the opening region formed in the frame body and extends so as to be inclined with respect to an end surface forming the opening region, and a bonding wire that is bonded between the lead portion and the semiconductor chip by ultrasonic bonding. 1. A semiconductor device comprising:a frame body having an opening region;an insulating substrate disposed in the opening region of the frame body and including a semiconductor chip;a lead portion including an inclined portion that is at least partially exposed to the opening region of the frame body and that extends so as to be inclined with respect to an end surface forming the opening region; andan ultrasonic-bonded wire connecting the lead portion and the semiconductor chip.2. The semiconductor device according to claim 1 ,wherein the inclined portion extends in a direction in which a vibration component is suppressed during ultrasonic bonding of the ultrasonic-bonded wire.3. The semiconductor device according to claim 1 ,wherein the lead portion includes a movement restriction portion formed on a side opposite to the opening region and configured to restrict the movement of the lead portion to the outside of the frame body, andthe frame body includes a receiving portion fitted to the movement restriction portion.4. The semiconductor device according to claim 1 ,wherein the lead portion includes:a parallelogram region having inclined end surfaces that intersect the end surface forming the opening region and are parallel to each other; anda terminal portion that protrudes and extends from one side of the parallelogram region, which is opposite to the opening region, to the outside of the frame body.5 ...

Wire Stitch Bond Having Strengthened Heel

A semiconductor chip () assembled on a substrate (), the chip having bond pads () and the substrate having contact pads (). Wires () form arches to connect electrically the chip and the substrate, the wires forming first bonds ( e.g. ball bonds) on the chip bond pads and second bonds ( e.g. stitch bonds) on the substrate contact pads. The second (stitch) bonds have bendings (heels) with metal bulges () near the vertex of the bending. 1. An apparatus for use in wire bonders comprising:a tube of a length having a surface and walls made of a material and surrounding a capillary bore, the material at the capillary mouth contoured by intersecting first and second planes, wherein the first plane is at right angle to the tube length and the second plane at an acute angle, the intersection at the mouth of the capillary bore;at the edge of the first plane and the tube surface, the material forming a first curved surface, and at the intersection of the first and second planes, the material forming a second curved surface; andat least one concave recess in the material of the first and the second curved surfaces.2. The apparatus of wherein the material of the tube is selected from a group including tungsten carbide claim 1 , corundum claim 1 , and sapphire.3. The apparatus of wherein the concave recesses are positioned in the center portions of the curved surfaces.4. The apparatus of wherein the concave recesses have a contour selected from a group including concave bowl claim 1 , dish claim 1 , indent claim 1 , chamfer claim 1 , groove claim 1 , wedge claim 1 , and flute.5. The apparatus of wherein the first curved surface is characterized by a front radius and the second curved surface is characterized by a back radius.6. A method for fabricating a device having wire bonds comprising:providing a device having metallic bond pads, the device assembled on a substrate;providing a tube having a capillary loaded with a metal bonding wire, at the tube end with the capillary mouth ...

SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and a wire extending between the first electrode and the second electrode. The wire includes a first conductor in contact with the first electrode and the second electrode, and a second conductor that is provided inside the first conductor and has no contact with the first electrode and the second electrode. 1. A semiconductor device comprising:a first electrode;a second electrode; anda wire extending between the first electrode and the second electrode, a first conductor in contact with the first electrode and the second electrode; and', 'a second conductor that is provided inside the first conductor and has no contact with the first electrode and the second electrode., 'wherein the wire includes2. The device of claim 1 , further comprising a semiconductor chip having an upper surface provided with the first electrode.3. The device of claim 2 , wherein the first conductor contains palladium (Pd).4. The device of claim 3 , wherein the second conductor contains at least one metal selected from copper (Cu) claim 3 , gold (Au) claim 3 , silver (Ag) claim 3 , and aluminum (Al).5. The device of claim 4 , wherein the wire has a diameter ranging from 15 micrometers (μm) to 80 micrometers (μm).6. The device of claim 5 , wherein the semiconductor chip is one of a memory device claim 5 , an integrated circuit claim 5 , a discrete semiconductor claim 5 , and a light emitting diode (LED).7. The device of claim 4 , wherein the wire has a diameter ranging from 100 micrometers (μm) to 500 micrometers (μm).8. The device of claim 7 , wherein the semiconductor chip is a power semiconductor.9. The device of claim 4 , wherein:the wire includes a first portion in contact with the first electrode, a second portion in contact with the second electrode, and a third portion between the first portion and the second portion; andthe first portion of the wire and the second portion of the wire ...

Method of manufacturing semiconductor device

As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load. In addition, the method of manufacturing a semiconductor device includes a step of, after the first step, applying the ultrasonic waves to the ball portion while pressing the ball portion with a second load larger than the first load, thereby bonding the ball portion and the first electrode.

Bond pad having a trench and method for forming

A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.