Halbleiterpackung und -modul, Herstellungsverfahren und elektronisches Bauelement

Die Erfindung bezieht sich auf eine Halbleiterpackung mit gestapelten Halbleiterchips, auf ein Halbleitermodul mit einer derartigen Packung, auf ein Verfahren zur Herstellung der Halbleiterpackung sowie auf ein elektronisches Bauelement, das ein derartiges Modul beinhaltet. Eine Halbleiterpackung gemäß der Erfindung beinhaltet ein Packungssubstrat (200) mit einem Durchkontakt (220s), wenigstens einen Halbleiterchip (100, 120), der auf dem Packungssubstrat gestapelt ist, einen thermischen Grenzflächenfilm (132), der auf dem Halbleiterchip gestapelt ist, eine Packungsabdeckung (300), die in Kontakt mit dem thermischen Grenzflächenfilm und über dem Halbleiterchip positioniert ist, und eine Packungshaftstruktur (310) zwischen dem Durchkontakt und einem Teil der Packungsabdeckung. Verwendung in der Halbleiterbauelementtechnologie.

ELECTRONIC DEVICE WITH INTEGRATED CIRCUIT

Thermal interface material layer and includes a thermal interface material layer of the stacked package device

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP-BY ANNEALING THE UV, OBTAINED ASSEMBLY

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP UV BY ANNEALING, RESULTING ASSEMBLY

L'invention concerne un procédé d'assemblage de type Flip-Chip, entre un premier (1) et un deuxième (2) composants comportant chacun des plots de connexion (11, 21) sur une de leurs faces, dites faces d'assemblage, selon lequel on reporte les composants l'un sur l'autre par leurs faces d'assemblage de sorte à réaliser des interconnexions électriques entre les plots du premier et ceux du deuxième composant. Selon l'invention, on réalise une transformation de l'oxyde de cuivre en cuivre par recuit UV, très localement dans l'espacement entre composants au moins autour des zones au droit des plots de connexion. Le procédé selon l'invention peut être utilisé pour n'importe quel composant transparent aux UV, y compris pour des substrats en matière plastique tels que des substrats en PEN ou en PET.

METHOD FOR REALIZATION Of ELEMENTS CHIP HAS PROVIDED WITH GROOVES Of INSERTION OF WIRE

L'invention concerne un procédé de réalisation d'éléments à puce (10) munis d'une rainure (14), comprenant les étapes suivantes : prévoir, sur un substrat d'interconnexion (22), une piste conductrice (26) agencée pour relier une plage de contact d'une face active d'une puce (20) à une zone correspondant à une première paroi de la rainure ; faire croître par électrodéposition un plot de contact (16) sur la piste conductrice au niveau de la zone correspondant à la première paroi de la rainure ; assembler la puce (20) sur le substrat par sa face active de manière qu'une paroi latérale de la puce forme le fond de la rainure ; usiner la puce par sa face arrière parallèlement au substrat en mesurant la distance entre la face arrière de la puce et le plot de contact ; arrêter l'usinage lorsque la distance mesurée atteint une valeur souhaitée ; et assembler par collage une plaque (24) sur la face arrière de la puce de manière à former une deuxième paroi de la rainure.

핫 스팟 열 관리 특징부를 갖춘 3ＤＩＣ 패키징

... 패키지는 전도성 층을 갖는 기판을 포함하며, 전도성 층은 노출된 부분을 포함한다. 다이 스택은 기판 위에 배치되며, 전도성 층에 전기적으로 접속된다. 고 열전도성 재료가 기판 위에 배치되며 전도성 층의 노출된 부분과 접촉한다. 패키지는 또한, 고 열전도성 재료 위에 있고 고 열전도성 재료와 접촉하는 콘투어 링을 포함한다.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

THERMAL INTERFACE MATERIAL HAVING DIFFERENT THICKNESSES IN PACKAGES

Chip package structure and manufacturing method thereof

Microelectronic assemblies with cavities, and methods of fabrication

Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer's substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

Die encapsulation in oxide bonded wafer stack

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Package and package method thereof

A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

Manufacturing method of package-on-package structure

Semiconductor device and method of manufacture

Package structure and method for manufacturing same

Vacuum assisted underfill process and apparatus for semiconductor package fabrication

A semiconductor chip fabrication assembly and method including a semiconductor package having a packaging substrate and a semiconductor die. An active circuit surface of the semiconductor die is positioned adjacent to a contact surface of the packaging substrate such that a substantially thin gap is formed therebetween. A semi-rigid shroud device is provided which defines a vacuum chamber configured to extend around the gap to hermetically seal the gap within the vacuum chamber. A dispensing device is provided having an outlet end positioned proximate the gap in the vacuum chamber which is adapted to vacuum flow the bonding material between the electrical contacts in the gap, and between the active circuit surface and the contact surface. The absence of air and any other gases forms a substantially voidless underfill layer of bonding material in the gap.

MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin. The flexible board includes a bendable flexible portion and a hard portion. The flexible portion is bent at a boundary with the hard portion, along a shape of the electronic component such that the flexible board covers the electronic component. The flexible board and the electronic component are sealed with the sealing resin. The first semiconductor device is provided vertical to the second semiconductor device such that the hard portion is provided parallel to the second semiconductor device, and a length of the hard portion in a direction perpendicular to a bend line of the flexible portion is equal to a thickness of a bottom surface of the electronic component in the direction.

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

A semiconductor device includes a rectangular lower semiconductor element; a plurality of external electrodes located in a pattern on the lower semiconductor element along sides thereof; a plurality of internal electrodes electrically connected to the plurality of external electrodes via a plurality of line patterns respectively and located on the lower semiconductor element in a pattern; dams provided in such a pattern that each of the dams encloses one or at least two external electrodes among the plurality of external electrodes; an upper semiconductor element mounted on the lower semiconductor element such that a plurality of terminals on the upper semiconductor element are electrically connected to the plurality of internal electrodes respectively; and a resin potted to flow to a space between the lower semiconductor element and the upper semiconductor element.

3-D STACKING SEMICONDUCTOR ASSEMBLY HAVING HEAT DISSIPATION CHARACTERISTICS

A semiconductor assembly having heat dissipation characteristics includes stacked semiconductor chips thermally conductible to a thermal pad of an interconnect substrate and electrically connected to the interconnect substrate through bonding wire. The bonding wires extending from a primary routing circuitry in between the stacked chips can accommodate the height difference between the stacked chips and the interconnect substrate. These wires can also effectively compensate for the thermal expansion mismatch between the stacked chips and the interconnect substrate, thereby allowing a higher manufacturing yield and better reliability. 1. A three-dimensional semiconductor assembly , comprising:a stacked semiconductor subassembly that includes a primary routing circuitry, a first device and a second device, wherein (i) the primary routing circuitry has a first surface in a first direction, a second surface in an opposite second direction, first conductive pads at the first surface, and second conductive pads at the second surface electrically connected to the first conductive pads, (ii) the first device is disposed over the first surface of the primary routing circuitry and electrically coupled to the primary routing circuitry through the first conductive pads, and (iii) the second device is disposed over the second surface of the primary routing circuitry and electrically coupled to the primary routing circuitry through the second conductive pads;an interconnect substrate that includes a thermal pad and a surrounding layer, wherein (i) the thermal pad has a front side facing in the first direction and the front side of the thermal pad is attached to the second device by a thermal conducting material, (ii) the surrounding layer has a dielectric layer and contact pads, (iii) the dielectric layer is bonded to sidewalls of the thermal pad and has a front surface facing in the first direction, and (iv) the contact pads are disposed on the front surface of the dielectric ...

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE

An electronic device includes a substrate, an electronic element mounted on the substrate, bumps that electrically connect the substrate to the electronic element, dummy bumps that are formed on the substrate to surround the electronic element, and a side fill that is formed around the electronic element and is in contact with the dummy bumps. 1. An electronic device , comprising:a substrate;an electronic element mounted on the substrate;bumps that electrically connect the substrate to the electronic element;dummy bumps that are formed on the substrate to surround the electronic element; anda side fill that is formed around the electronic element and is in contact with the dummy bumps.2. The electronic device as claimed in claim 1 , whereinthe electronic element is a light-emitting element or a light-receiving element;the substrate includes an opening that is formed in a position corresponding to a light emitter of the light-emitting element or a light receiver of the light-receiving element; andthe bumps are formed around the opening.3. A method for manufacturing an electronic device claim 1 , the method comprising:forming bumps on a substrate;connecting an electronic element via the bumps to the substrate;after connecting the electronic element to the substrate, forming dummy bumps on the substrate;applying a side fill resin onto the bumps and the dummy bumps; andcuring the side fill resin. The present application is based upon and claims the benefit of priority of Japanese Patent Application No. 2017-029990, filed on Feb. 21, 2017, the entire contents of which are incorporated herein by reference.An aspect of this disclosure relates to an electronic device and a method for manufacturing the electronic device.An electronic device including a light-emitting element and a light-receiving element is used in the field of optical communication. Such an electronic device is called an optical module and is used for high-speed optical communication performed by, for ...

High density interconnection using fanout interposer chiplet

Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

Semiconductor package with through silicon vias and method for making the same

The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.

Method of forming a dummy die of an integrated circuit having an embedded annular structure

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Method of manufacturing semiconductor devices

In the disclosed method of manufacturing semiconductor devices with a single-sided resin-sealed package structure, when resin is filled into between the chip and the substrate, the occurrence of variations in the finishing dimensions of the package or defects in the outward appearance of the package is prevented. The present invention comprises the step of using a guide plate (11) for pouring resin and bringing one end of the guide plate into contact with one face end of a substrate or with a portion of one major surface near at least one side face of a chip in filling sealing resin (5a) between the chip and the substrate after the semiconductor chip (2) has been mounted, with the face down, on one major surface of a wiring substrate (1) having the wiring (1a) containing a connection section (1b), the step of inclining the guide plate so that the guide plate may meet one major surface of the substrate at a specified angle, when or after one end of the guide plate is brought into contact ...

THERMISCHES GRENZFLÄCHENMATERIAL MIT UNTERSCHIEDLICHEN DICKEN IN PACKUNGEN

Eine Packung enthält eine Packungskomponente, einen Vorrichtungs-Die über der Packungskomponente und an diese gebunden, eine Metallkappe mit einem oberen Abschnitt über dem Vorrichtungs-Die und ein thermisches Grenzflächenmaterial zwischen und in Kontakt mit dem Vorrichtungs-Die und der Metallkappe. Das thermische Grenzflächenmaterial enthält einen ersten Abschnitt direkt über einem inneren Abschnitt des Vorrichtungs-Die und einen zweiten Abschnitt, der sich direkt über einem Eckbereich des Vorrichtungs-Die erstreckt. Der erste Abschnitt hat eine erste Dicke. Der zweite Abschnitt hat eine zweite Dicke größer als die erste Dicke.

VERFAHREN ZUM HERSTELLEN EINER ELEKTRISCHEN VERBINDUNG

Verfahren zum Herstellen einer elektrischen Verbindung zwischen einem Kontaktträger (102) und einem zugehörigen Gegenkontaktträger (104), wobei das Verfahren die folgenden Schritte aufweist:Herstellen des Kontaktträgers (102) mit mindestens einem elektrisch leitfähigen Kontaktelement (106) und mindestens einer Leiterbahn, die mit dem Kontaktelement verbunden ist,Bereitstellen des Gegenkontaktträgers (104), der mindestens ein elektrisch leitendes Gegenkontaktelement (108) aufweist und Positionieren des Kontaktträgers (102), so dass das mindestens eine Kontaktelement (106) und das mindestens eine Gegenkontaktelement (108) übereinander ausgerichtet sind,Anbringen einer Isolierlage (118) zwischen dem Kontaktträger (102) und dem Gegenkontaktträger (104), so dass das Kontaktelement (106) durch die Isolierlage (118, 154) hindurch ragt,Verbinden des mindestens einen Kontaktelements (106) und des mindestens einen Gegenkontaktelements (108) durch Einbringen eines elektrisch leitenden Verbindungsmaterials ...

SEMICONDUCTOR UNIT PACKAGE, SEMICONDUCTOR UNIT PACKAGING METHOD, AND ENCAPSULANT FOR USE IN SEMICONDUCTOR UNIT PACKAGING

An improved semiconductor unit package is disclosed. This package is implemented by a semiconductor device (1) having an electrode pad (2), a substrate (6) having a terminal electrode (5), a bump electrode (3) formed on the electrode pad (2), a conductive adhesion layer (4) with flexibility, and an encapsulating layer (7) formed by curing a composition the viscosity and thixotropy index of which are below 100 Pa.s and below 1.1, respectively. Such a composition essentially consists of (A) a resin binder that contains, for example, a polyepoxide, an acid anhydride, and a rheology modifier and (B) a filler. The rheology modifier is one capable of impeding interaction between a free acid contained in the acid anhydride and a polar group at the surface of the filler. An encapsulant with improved flowability is used, so that the encapsulant readily flows and spreads to fill a gap between the semiconductor device (1) and the substrate (6) with no air bubbles. This achieves semiconductor unit ...

Semiconductor package

SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING THE SAME

Integrated Fan-Out Package on Package Structure and Methods of Forming Same

Semiconductor assembly with built-in stiffener and integrated dual routing circuitries and method of making the same

Fan out system in package and method for forming the same

지문센서 패키지

... 본 발명은 지문센서 패키지에 관한 것으로, 해결하고자 하는 기술적 과제는 도전성 범프와 지문센싱부가 반도체 다이의 일면에 구비되고, 타면에 구비된 보호판이나 보호막에 지문이 인접할 경우, 정전용량 변화를 통해 지문을 센싱할 수 있고, 지문센싱부가 구비된 반도체 다이가 기판에 플립칩 타입으로 안착되므로, 공정을 간소화하는데 있다.

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively include an active side, a back side and a conductive pillar at the active side. The back side of the first semiconductor die is attached with the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached with the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends toward the second redistribution structure. The first and second semiconductor dies are laterally encapsulated by the encapsulant.

SEMICONDUCTOR DEVICE AND ASSOCIATED METHOD

The invention provides a semiconductor device and associated method, which includes a substrate, a first die, multiple sub-package systems surrounding the first die, and a heat spreader. The first die and the sub-package systems are installed on a same surface of the substrate, wherein projections of the first die and each sub-package system on the surface partially overlap, and have a portion not overlapping. Each of the sub-package systems includes an interposer and multiple second dice installed on the interposer by way of flip-chip. The heat spreader includes a protrusion portion and a dissipation plate; the dissipation plate covers the first die and the sub-package systems, and the protrusion portion is set between the dissipation plate and the first die.

Packages with stacked dies and methods of forming the same

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same

A thermally enhanced semiconductor assembly with three dimensional integration includes a stacked semiconductor sub-assembly electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the stacked semiconductor sub-assembly is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the sub-assembly and the wiring board for interconnecting devices assembled in the sub-assembly to terminal pads provided in the wiring board.

SEMICONDUCTOR DEVICE

The terminal pattern TP1 of the wiring substrate PB has a side T1a facing the terminal pattern TP2 and the terminal pattern TP2 of the wiring substrate PB has a side T2a facing the side T1a of the terminal pattern TP1. The side T1a and the side of T2a are exposed from the opening portion OP1 and OP2 of the solder resist layer SR1 respectively, and outer peripheries of terminal patterns TP1 and TP2 other than sides T1a and T2a are not exposed from opening portions OP1 and OP2. The opening portion OP1 and the opening portion OP2 are separated from each other. The electrode E1 of the capacitor C1 is soldered to the terminal pattern TP1 exposed from the opening portion OP1, and the electrode E2 of the capacitor C1 is soldered to the terminal pattern TP2 exposed from the opening portion OP2.

SEMICONDUCTOR DEVICE

Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

Heat sink, electronic device, and method of manufacturing electronic device

A heat sink includes a base including a first surface and a second surface facing away from each other, the base being configured to have the first surface thermally connected to a heat generator; and multiple radiation fins extending from the second surface of the base, the radiation fins being reduced in length in accordance with a decrease in the temperature of the base due to the heat conducted from the heat generator, the radiation fins being shaped to bend outward.

Method for packaging semiconductor device

The present invention provides a method for packaging semiconductor device which is using more than once reflow processes to heat the solder ball to prevent the deformation of solder ball, so that the yield of the manufacturing process can be increased and the reliability of the semiconductor device can be increased.

Methods of forming multi-chip package structures

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die disposed on a substrate, a second die disposed on the substrate, a molding compound disposed between the first die and the second die, wherein the molding compound is disposed on a top surface of the substrate. An epoxy material is disposed between a top portion of a sidewall of the first die and the molding compound, and a thermal interface material (TIM) is disposed on top surfaces of the first and second die, wherein the TIM extends over the entire length of the substrate.

Light emitting device

A light emitting device includes a substrate and a light emitting element mounted on the substrate, a light transmissive member, covering member, first and second protruding members, and a protective element. The light transmissive member is disposed on an upper surface of the light emitting element. The covering member covers an upper surface of the substrate, a lateral surface of the light emitting element, and at least a portion of a lateral surface of the light transmissive member such that an upper surface of the light transmissive member is exposed. The first protruding member and the second protruding member are provided on the substrate such that the light emitting element and the light transmissive member are positioned between the first protruding member and the second protruding member. The protective element is mounted on the substrate so as to be positioned between the light emitting element and the second protruding member.

Semiconductor unit package, semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging

DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK

Structures and methods of fabricating semiconductor water assemblies (100) that encapsulate at least one die (108, 202, 402) in a cavity (110, 204, 404) etched into an oxide bonded semiconductor wafer stack (102+104, 206+208, 406+408). The methods generally include the steps of position-ing the die (108, 202, 402) in the cavity (110, 204, 404), mechanically and electrically mounting the die (108, 202, 402) to the wafer stack (102+104, 206+208, 406+408), and encapsulating the die (108, 202, 402) within the cavity (110, 204, 404) by bonding a lid wafer (106, 210, 410) to the wafer stack (102+104, 206+208, 406+408) in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above. The cavity (110, 404) may be hermetically sealed to ...

DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK

Structures and methods of fabricating semiconductor wafer assemblies (100) that encapsulate at least one die (108, 202, 402) in a cavity (110, 204, 404) etched into an oxide bonded semiconductor wafer stack (102+104, 206+208, 406+408). The methods generally include the steps of positioning the die (108, 202, 402) in the cavity (110, 204, 404), mechanically and electrically mounting the die (108, 202, 402) to the wafer stack (102+104, 206+208, 406+408), and encapsulating the die (108, 202, 402) within the cavity (110, 204, 404) by bonding a lid wafer (106, 210, 410) to the wafer stack (102+104, 206+208, 406+408) in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above. The cavity (110, 404) may be hermetically sealed to encapsulate ...

Electronic device package structure and package manufacturing method

Provided is an electronic device package which can easily cope with diversification of electronic component configuration and is not harmful to the environment in the aspects of the number of manufacturing steps and resource consumption. A package structure in one working example is provided with a substrate (1), a wiring (2) formed on the surface of the substrate (1), an electrode pad (3), an electronic component (5), and a bonding material (4) for bonding the external electrode (6) and an external electrode (6) of the external component (5). The wiring (2), the electrode pad (3) and the bonding material (4) are all composed of the same material, and furthermore, the electrode pad (3) operates also as the bonding material (4).

STRUCTURE OF CHART OF ASSEMBLY OF LSI AND ITS MANUFACTORING PROCESS

Une puce LSI (1) est réunie à une première surface d'une carte de câblage (2) d'une manière par montage de puce nue et un remplissage inférieur (3) est rempli dans l'espace entre la puce LSI (1) et la carte de câblage (2). Un dispositif de rigidification (4) ayant les mêmes dimensions externes et le même coefficient de dilatation thermique que la puce LSI (1) est réuni à une deuxième surface de la carte de câblage (2) dans la position correspondant à la puce LSI (1) par une colle (5), supprimant ainsi l'apparition du gauchissement de la carte de montage de LSI dû à la différence de coefficient de dilatation thermique entre la puce LSI (1) et la carte de câblage (2) lorsque la température varie.

Halvledarkapsel, förfarande för kapsling av halvledare samt inneslutning för användning vid kapsling av halvledare

Semiconductor package assembly and method for forming the same

Forming folded-stack packaged device using progressive folding tool

An embodiment of the present invention includes a plunger, a heating element, and first and second arms. The plunger affixes a first unit to a second unit with adhesive. The first and second units are on a strip of a flexible tape. The strip is on a folding base unit. The folding base unit folds the first unit on top of the second unit. The heating element is attached to the plunger to cure the adhesive. The first and second arms are positioned on first and second sides of the plunger via first and second hinges, respectively, to secure the first and second units underneath the plunger. Another embodiment of the invention includes a first sub-assembly and a second subassembly. The first sub-assembly supports a first unit. The first sub-assembly, when activated, folds the first unit on top of a second unit. The first and second units are on a strip of a flexible tape. The second sub-assembly supports the second unit.

Cross-connected multi-chip modules coupled by silicon bent-bridge interconnects and methods of assembling same

A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.

HETEROGENEOUS INTEGRATED CIRCUITS WITH INTEGRATED COVERS

The system and method for a heterogeneous integrated circuit packaging method having an air-cavity lid to protect the active face of an integrated circuit, or other device, either active or passive, from the environment. The packaging is hermetic or near hermetic. In some examples, the cover provides electrical routing. In some examples, the cover also provides electromagnetic shielding. In some cases, an encapsulant and/or an overmoulding is provided to further protect the heterogeneous integrated circuit.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

Thin bonded interposer package

Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.

Method for manufacturing a semiconductor device having multiple heat sinks

A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.

Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

PROBLEM TO BE SOLVED: To prevent an unfilled part from generating on a connecting terminal reinforcing resin layer. SOLUTION: A semiconductor device 46 is provided by arranging a pellet 11 on the top plane of a substrate 21 and is connected by a plurality of connecting terminals 32 formed of solder bumps. A group of connecting terminals is arranged in a plurality of annular lines 33 at the periphery of the pellet 11, a space 40 with a low height formed between the pellet and the substrate by the connecting terminal group is filed with resin and a reinforcing resin layer 44 is formed. A vacant part 35 is formed on the connecting terminal annular line group 34 due to a vacant part provided on one side of the annular line group at the time of forming the solder bump, and the reinforcing resin layer 44 is also formed at the vacant part 35. Since the air in the space 40 is completely discharged by the operation of the vacant part 35 of the connecting terminal annular line group, an unfilled ...

Computersystem mit einer magnetische Partikel umfassenden thermischen Schnittstelle

Ausführungsformen der vorliegenden Offenbarung stellen Verfahren und Konfigurationen für ein Computersystem mit einer thermischen Schnittstelle bereit, die magnetische Partikel aufweist. In manchen Ausführungsformen kann das Computersystem einen ersten Teil, einen zweiten Teil und eine thermische Schnittstelle umfassen, um den ersten und den zweiten Teil zu verbinden. Die thermische Schnittstelle kann ein thermisches Schnittstellenmaterial mit magnetischen Partikeln umfassen, die in Bezug auf eine Oberfläche des ersten oder des zweiten Teils in eine definierte Richtung ausgerichtet sind, um eine gewünschte thermische Leitfähigkeit zwischen dem ersten und dem zweiten Teil bereitzustellen. Die definierte Ausrichtungsrichtung der magnetischen Partikel kann eine Ausrichtung der Partikel im Wesentlichen im rechten Winkel auf die Oberfläche des ersten oder des zweiten Teils umfassen. Weitere Ausführungsformen können beschrieben und/oder beansprucht werden.

Substrate employing a vent hole arrangement suitable for encapsulating an electrical component package mounted thereon and related method

Semiconductor unit package, semiconductor unit packaging method and encapsulant for use in semiconductor unit packaging

INTERPOSER FOR A PACKAGE-ON-PACKAGE STRUCTURE

A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Integrated circuit chip using top post-passivation technology and bottom structure technology

Adhesive film for a semiconductor device with a body and the back of the cut film for semiconductor

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

병렬형 반도체 패키지

... 병렬형 구성을 위한 반도체 패키지는, 캐비티를 갖는 기판, 캐비티 내부에 포지셔닝되고 제 1 다이 및 제 2 다이의 활성측들을 향하고 제 1 다이 및 제 2 다이와 부분적으로 수평 중첩되어 제 1 다이와 제 2 다이 사이에 인터커넥션을 제공하는 활성측을 갖는 브리지 인터포저, 및 제 1 다이 및 제 2 다이에 열 경로 및 열 저장소를 제공하기 위해 제 1 다이 및 제 2 다이의 후면측들에 부착되는 열 엘리먼트를 포함할 수 있다.

Semiconductor packages including heat spreaders and methods of manufacturing the same

Semiconductor package structure and method for manufacturing the same structure

A semiconductor package structure includes a first semiconductor substrate, a second semiconductor substrate, a semiconductor die electrically connected to the first semiconductor substrate, an interconnection element and an encapsulant. The first semiconductor substrate includes a first top pad, and the second semiconductor substrate includes a second bottom pad. The interconnection element connects the second bottom pad and the first top pad. The interconnection element includes a first cupped portion and a second arcuate portion, where the first portion is connected to the first top pad and the second portion is connected to the second bottom pad. The first portion and the second portion together define the interconnection element as a monolithic component. The encapsulant is disposed between the first semiconductor substrate and the second semiconductor substrate, and covers the semiconductor die and the interconnection element.

Semiconductor device and manufacturing method thereof

A semiconductor device according to an embodiment of the present invention comprises pads electrically connected to wires provided on an insulating substrate. A wiring substrate comprises a first insulant provided between the pads. A first semiconductor chip comprises metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate. A first adhesion layer is provided between the first insulant and the first semiconductor chip and adheres the wiring substrate and the first semiconductor chip to each other. An insulating resin is provided to cover peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate.

Forming folded-stack packaged device using progressive folding tool

An embodiment of the present invention includes a plunger, a heating element, and first and second arms. The plunger affixes a first unit to a second unit with adhesive. The first and second units are on a strip of a flexible tape. The strip is on a folding base unit. The folding base unit folds the first unit on top of the second unit. The heating element is attached to the plunger to cure the adhesive. The first and second arms are positioned on first and second sides of the plunger via first and second hinges, respectively, to secure the first and second units underneath the plunger. Another embodiment of the invention includes a first sub-assembly and a second sub-assembly. The first sub-assembly supports a first unit. The first sub-assembly, when activated, folds the first unit on top of a second unit. The first and second units are on a strip of a flexible tape. The second sub-assembly supports the second unit.

Method for mounting a semiconductor chip on a carrier layer and device for carrying out the method

In order to mount a semiconductor chip on a carrier layer, consolidated filler material is applied between the semiconductor chip and the carrier layer. The filler material is sucked, under the application of a partial vacuum, from at least one edge section of the semiconductor chip to at least one other edge section of the semiconductor chip. As a result, a package is provided in which the filler material is essentially free of air inclusions.

Semiconductor device and a method of manufacturing a semiconductor device

In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

METHOD AND APPARATUS FOR HEAT SINKING HIGH FREQUENCY IC WITH ABSORBING MATERIAL

A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5.

Semiconductor device

A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.

Semiconductor package having a stiffener ring

A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.

RF AMPLIFIERS HAVING SHIELDED TRANSMISSION LINE STRUCTURES

HALBLEITERVORRICHTUNG UND HERSTELLUNGSVERFAHREN

Eine Vorrichtung umfasst eine Umverteilungsstruktur, eine erste Halbleitervorrichtung, eine erste Antenne und eine erste leitfähige Säule auf der Umverteilungsstruktur, die mit der Umverteilungsstruktur elektrisch verbunden sind, eine Antennenstruktur über der ersten Halbleitervorrichtung, wobei die Antennenstruktur eine zweite Antenne umfasst, die sich von der ersten Antenne unterscheidet, wobei die Antennenstruktur einen externen Anschluss umfasst, der an die erste leitfähige Säule gebondet ist, und ein Formmaterial, das sich zwischen der Antennenstruktur und der Umverteilungsstruktur erstreckt, wobei das Formmaterial die erste Halbleitervorrichtung, die erste Antenne, den externen Anschluss und die erste leitfähige Säule umgibt.

METHOD AND DEVICE FOR SEALING IC CHIP

A method and device for sealing IC chip, by which the occurence of imperfect sealing can be eleminated by surely feeding a sealing agent onto the upper surface of a mounting substrate. In the method, prior to feeding the sealing agent (17) a first gap (h1) is provided between a feeding nozzle (15) and the substrate (13) mounted with an IC chip (12), and the IC chip (12) is sealed while the sealing agent (17) is fed by providing a second gap (h2) larger than the first gap (h1) between the nozzle (15) and the substrate (13). After the sealing agent (17) is surely brought into contact with the upper surface of the substrate (13), the IC chip (12) is sealed.

Clamp mounting bracket and be used for assembling integrated circuit package's device

패키지-온-패키지 구조를 위한 인터포저

... 패키지-온-패키지 (PoP) 구조는 제 1 다이, 제 2 다이, 및 제 1 다이와 제 2 다이 사이의 인터포저에 의해 제 1 다이 및 제 2 다이에 전기적으로 커플링된 메모리 디바이스를 포함한다. 인터포저는 몰드 내에 형성된 구리 충진형 비아들을 포함한다.

FORMING FOLDED-STACK PACKAGED DEVICE USING PROGRESSIVE FOLDING TOOL

An embodiment of the present invention includes a plunger, a heating element, and first and second arms. The plunger affixes a first unit to a second unit with adhesive. The first and second units are on a strip of a flexible tape. The strip is on a folding base unit. The folding base unit folds the first unit on top of the second unit. The heating element is attached to the plunger to cure the adhesive. The first and second arms are positioned on first and second sides of the plunger via first and second hinges, respectively, to secure the first and second units underneath the plunger. Another embodiment of the invention includes a first sub-assembly and a second sub-assembly. The first sub-assembly supports a first unit. The first sub- assembly, when activated, folds the first unit on top of a second unit. The first and second units are on a strip of a flexible tape. The second sub-assembly supports the second unit. © KIPO & WIPO 2007 ...

Semiconductor device and manufacturing of the same

A semiconductor device has a pellet at the upper surface of a substrate and connects the pellet with a plurality of connecting terminals formed of solder bumps. The connecting terminal group is arranged in the form of a plurality of annular lines in the periphery of the pellet, and a reinforcing resin layer is formed, in the connecting terminal group, of a resin filling a thinner space formed between the pellet and the substrate. At the time of forming the solder bumps, a cutout portion (a vacant area where no bumps are arranged) is formed in the connecting terminal annular line group by means of a cutout part opened at one side of the annular line group, and the reinforcing resin layer is also formed in the cutout portion. Since the air in the thinner space is perfectly exhausted by the effect of the connecting terminal annular line group cutout portion when the vacant area is filled with the reinforcing resin, the generation of an unfilled area in the reinforcing resin layer can be prevented ...

Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

METHOD FOR SELF-ALIGNED SOLDER REFLOW BONDING AND DEVICES OBTAINED THEREOF

A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein. 1. A semiconductor device comprising: a substrate top side;', 'a substrate bottom side;', 'a substrate dielectric structure between the substrate top side and the substrate bottom side;', conductive pads at the substrate bottom side; and', 'conductive paths along the substrate dielectric structure and coupled to the conductive pads; and', 'a substrate cavity through the substrate dielectric structure;, 'a substrate conductive structure comprising;'}], 'a substrate comprising inner short bumps;', 'outer short bumps bounding a perimeter around the inner short bumps; and', 'tall bumps between the outer short bumps and an edge of the base component top side; and, 'a base component top side comprising, 'a base electronic component comprisinga mounted electronic component coupled to the inner short bumps of the base electronic component; the tall bumps of the base component are coupled to the conductive pads of the substrate;', 'the mounted electronic component is in the substrate cavity; and', 'the substrate bottom side covers at least a ...

System and method for bonding package lid

Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.

Pressurized underfill encapsulation of integrated circuits

A new method and device to encapsulate integrated circuits such as flip chips and BGA packages. A special mold to surrounds the chip to be encapsulated in a cavity, and the encapsulant is injected into the cavity at an elevated pressure, and possibly at an elevated temperature. This shortens the cavity filling time by two or three orders of magnitude, compared to the conventional dispensing process. The reliability of the package is increased by increasing the adhesion of encapsulant to the package, by controlling fillet shape through in-mold curing, and by completely filling the cavity through proper mold design and, optionally, evacuation of the cavity prior to injection. The invention also allows the use of a wider range of encapsulants, including highly viscous material, fast curing materials and reworkable materials.

Control of under-fill with a packaging substrate having an integrated trench for a dual-sided ball grid array package

Described herein are methods of manufacturing dual-sided packaged electronic modules to control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include forming a trench in a packaging substrate that is configured to prevent or limit the flow of a capillary under-fill material. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using a trench in a packaging substrate.

FABRICATION OF 3D CHIP STACKS WITHOUT CARRIER PLATES

A method of fabricating a 3D chip stack uses an interposer and an electronic circuit substrate comprising a plurality of electronic circuits. The electrical contacts of the electronic circuit substrate are bonded and electrically coupled to bumps of the interposer. A molding compound is applied over the electronic circuits to form a molded structure. The molded structure is thinned to have a second molded thickness that is less than the first molded thickness, and the interposer is thinned to a second interposer thickness that is less than a first interposer thickness.

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RADOM ACCESS MEMORY CELLS

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Semiconductor unit package, semiconductor unit packaging met hod, and encapsulant for use in semiconductor unit packaging

METHOD FOR REALIZATION Of ELEMENTS CHIP HAS PROVIDED WITH GROOVES Of INSERTION OF WIRE

Semiconductor device package and method of forming the same

A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Multiple-chip package with multiple thermal interface materials

A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.

Semiconductor device and method of manufacturing the same

A method of making a semiconductor device is characterized by the step of attaching a chip-on-interposer subassembly to a heat spreader with the chip inserted into a cavity of the heat spreader and the interposer laterally extending beyond the cavity. The interposer backside process is executed after the chip-on-interposer attachment and encapsulation to form the finished interposer. The heat spreader provides thermal dissipation, and the finished interposer provides primary fan-out routing for the chip. In the method, a buildup circuitry is electrically coupled to the interposer to provide further fan-out routing.

SEMICONDUCTOR MODULE, CIRCUIT BOARD

To improve efficiency of manufacturing a semiconductor module and a circuit board on which is mounted a semiconductor element having electrodes on both the front and rear surfaces. [Solution] A semiconductor module comprises a wiring substrate on which a via and a wiring pattern are formed, a semiconductor element disposed on a first surface side of the wiring substrate, and a bonding part composed of a first bonding layer disposed on the wiring substrate side and a second bonding layer disposed on the semiconductor element side. The first bonding layer comprises: a first insulating layer in which the primary component is an inorganic material; a through-hole of the first insulating layer, formed in a region corresponding to the via; and a conductive bonding part for creating conduction between the wiring substrate and an electrode part formed on the semiconductor element, the conductive bonding part being disposed inside the through-hole; and the first bonding layer has a first bonding ...

METHOD FOR MOUNTING SEMICONDUCTOR ELEMENT TO CIRCUIT BOARD, AND SEMICONDUCTOR DEVICE

The present invention provides a method for mounting a semiconductor element to a circuit board and a semiconductor device whereby connection reliability and connection strength in bonding of the semiconductor element and circuit board are enhanced and a connection resistance value is stabilized low. An insulating adhesive (107) is applied to an opposite face (101a) of a circuit board (101). The circuit board is then connected with a semiconductor element (103) by a conductive adhesive (106) and the insulating adhesive which are interposed between an electrode (102) on the circuit board and the projecting electrode and set in the same process. The circuit board and semiconductor element are connected by the insulating adhesive in addition to the conductive adhesive, so that connection reliability and connection strength are high and a connection resistance value is stabilized low.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

Adhesive film for semiconductor device, film for backside of flip-chip semiconductor, and dicing tape-integrated film for backside of semiconductor

Provided is an adhesive film for a semiconductor device that is capable of having the same physical properties as these at the time of manufacture even after it is stored for a long time. The adhesive film for a semiconductor device of the present invention contains a thermosetting resin, and in which the amount of reaction heat generated in a temperature range of ±80° C. of a reaction heat peak temperature measured by a differential scanning calorimeter after the adhesive film is stored at 25° C. for 4 weeks is 0.8 to 1 time the amount of reaction heat generated before storage.

Electrical module for being received by automatic placement machines by means of generating a vacuum

The invention relates to an electrical module ( 100 ) for being received by automatic placement machines by means of generating a vacuum, comprising a carrier substrate ( 10 ), at least one component ( 20, 21 ) disposed on the carrier substrate ( 10 ), and a cover element ( 30 ) disposed above the at least one component ( 20, 21 ). A fixing component ( 40 ) by which the cover element ( 30 ) is attached to the at least one component ( 21 ) is disposed between the cover element ( 30 ) and the at least one component ( 21 ). The cover element can be implemented as a dimensionally stable, flat film by means of which it is possible to suction the module by means of vacuum for a placement method, and to place said module at a position on a circuit board.

Semiconductor Package, and a Method for Forming a Semiconductor Package

A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. 1. A package comprising: a first device die;', 'a first molding compound extending along sidewalls of the first device die; and', 'a first through intervia (TIV) extending through the first molding compound;, 'a first fan-out tier comprisingone or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;one or more second fan-out RDLs on an opposing side of the first fan-out tier from the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; anda plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan ...

Method for forming Board Assembly with Chemical Vapor Deposition Diamond (CVDD) Windows for Thermal Transport

A method for forming a board assembly includes identifying a location of a hot-spot on a semiconductor die and cutting an opening in a circuit board corresponding to the location of the identified hot-spot. A Chemical Vapor Deposition Diamond (CVDD) window is inserted into the opening. A layer of thermally conductive paste is applied over the CVDD window. The semiconductor die is placed over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste. 1. A method for forming a board assembly comprising:identifying a location of a hot-spot on a semiconductor die;cutting an opening in a circuit board corresponding to the location of the identified hot-spot;inserting a Chemical Vapor Deposition Diamond (CVDD) window into the opening;applying a layer of thermally conductive paste over the CVDD window; andplacing the semiconductor die over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste.2. The method of further comprising: attaching leads to the semiconductor die and the circuit board to electrically couple the die to the first circuit board.3. The method of further comprising: forming a dam around the semiconductor die and attaching an additional circuit board to the dam so as to enclose the semiconductor die within the dam and between the circuit board and the additional circuit board.4. The method of further comprising: dispensing filler material within the enclosure.5. The method of claim 4 , wherein the filler material comprises diamond paste.6. The method of claim 1 , wherein the CVDD window has a thickness that is the same as the thickness of the circuit board.7. The method of claim 1 , wherein the CVDD window has a thickness that is greater than a thickness of the ...

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64. 1. A chip package comprising:a non-volatile memory cell configured to store resulting data of a look-up table (LUT) therein;a sense amplifier configured to sense input data thereof associated with the resulting data of the look-up table (LUT) stored in the non-volatile memory cell to generate output data of the sense amplifier;a logic circuit comprising a static-random-access-memory (SRAM) cell configured to store first data therein associated with the output data of the sense amplifier, and a selection circuit comprising a first set of input points for a first input data set for input data of a logic operation and a second set of input points for a second input data set having second data associated with the first data stored in the static-random-access-memory (SRAM) cell, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data of the logic operation; anda plurality of metal bumps at a bottom of the chip package, wherein the plurality of metal bumps comprise five metal bumps arranged in a line.2. The chip package of claim 1 , wherein the sense amplifier and logic circuit are provided by a ...

Multi-metal package stiffener

A semiconductor package system includes a semiconductor package including at least one semiconductor device having a first side and a second side and a substrate having a first side and a second side. The second side of the at least one semiconductor device is positioned on the first side of the substrate. At least one stiffener element is provided on the semiconductor package. The at least one stiffener element includes at least two metal elements having different coefficients of thermal expansion joined together.

LIGHT EMITTING DEVICE

A light emitting device includes a substrate and a light emitting element mounted on the substrate, a light transmissive member, covering member, first and second protruding members, and a protective element. The light transmissive member is disposed on an upper surface of the light emitting element. The covering member covers an upper surface of the substrate, a lateral surface of the light emitting element, and at least a portion of a lateral surface of the light transmissive member such that an upper surface of the light transmissive member is exposed. The first protruding member and the second protruding member are provided on the substrate such that the light emitting element and the light transmissive member are positioned between the first protruding member and the second protruding member. The protective element is mounted on the substrate so as to be positioned between the light emitting element and the second protruding member. 1. A light emitting device comprising:a substrate;a light emitting element mounted on the substrate;a light transmissive member disposed on an upper surface of the light emitting element;a covering member covering an upper surface of the substrate, a lateral surface of the light emitting element, and at least a portion of a lateral surface of the light transmissive member such that an upper surface of the light transmissive member is exposed;a first protruding member provided on the substrate;a second protruding member provided on the substrate such that the light emitting element and the light transmissive member are positioned between the first protruding member and the second protruding member; anda protective element mounted on the substrate so as to be positioned between the light emitting element and the second protruding member.2. The light emitting device according to claim 1 , wherein the first protruding member and the second protruding member are parallel to each other.3. The light emitting device according to claim 1 , ...

Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure

An electronic device disposed in a package that includes: an interposer, fan-out interconnect (FOI), and a lid. The interposer having first size and first surface upon which die terminals (DTs) are disposed and are configured to electrically couple to integrated circuit die (IC), and second surface upon which substrate terminals (STs) are disposed and are configured to electrically couple to substrate. The IC has second size smaller than the first size, and the IC is mounted on the first surface in electrical contact with the DTs, the interposer is mounted on third surface, and the package substrate has third size, larger than the first size. The FOI establishes electrical interconnection between DTs and STs, the DTs have first pitch size and the STs have second pitch size, larger than first pitch size. The lid has first section, configured to abut fourth surface, and second section, mounted on the third surface.

SEMICONDUCTOR PACKAGE HAVING A SIDEWALL CONNECTION

A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections. 1. A device , comprising:a semiconductor die including a first surface, a second surface opposite to the first surface, a first sidewall surface transverse to the first and second surfaces; anda contact pad exposed from the first surface;a first dielectric layer on the contact pad and extending from the contact pad to the first sidewall surface, the first dielectric layer including a second sidewall surface coplanar with the first sidewall surface;a second dielectric layer on the contact pad and extending from the contact pad to the first and second sidewall surfaces, the second dielectric layer having a third sidewall surface coplanar with the first and second sidewall surfaces, the second dielectric layer having a surface facing away from the semiconductor die;a mold protection layer on and covering the first, second, and third sidewall surfaces, the mold protection layer having an end surface facing away from the semiconductor die and a fourth sidewall surface transverse to the end surface of the mold protection layer; anda redistribution layer on the contact pad and extending from the contact pad to the mold protection layer, the redistribution ...

Board Assembly with Chemical Vapor Deposition Diamond (CVDD) Windows for Thermal Transport

A method and apparatus for conducting heat away from a semiconductor die are disclosed. A board assembly is disclosed that includes a first circuit board having an opening extending through the first circuit board. A Chemical Vapor Deposition Diamond (CVDD) window extends within the opening. A layer of thermally conductive paste extends over the CVDD window. A semiconductor die extends over the layer of thermally conductive paste such that a hot-spot on the semiconductor die overlies the CVDD window. 1. A board assembly comprising:a circuit board;a semiconductor die electrically coupled to the circuit board;a Chemical Vapor Deposition Diamond (CVDD) window; anda layer of thermally conductive paste in direct contact with a first surface of the CVDD window along the full extent of the first surface of the CVDD window, and in direct contact with the semiconductor die, the layer of thermally conductive paste positioned so that it covers a hot-spot on the semiconductor die, the CVDD window having a footprint that is less than twenty percent of the footprint of the semiconductor die.2. The board assembly of further comprising an opening extending through the circuit board claim 1 , the CVDD window extending within the opening.3. The board assembly of further comprising leads that extend from the semiconductor die to the circuit board for electrically coupling the semiconductor die to the circuit board.4. The board assembly of further comprising a dam extending around the die claim 3 , and filler material that extends within the dam.5. The board assembly of further comprising an additional circuit board and a dam extending around the die claim 3 , the additional circuit board attached to the dam so as to couple the circuit board to the additional circuit board and form an enclosure within the dam and between the circuit board and the additional circuit board claim 3 , the semiconductor die and the leads extending within the enclosure.6. The board assembly of further ...

SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR DIE EMBEDDED BETWEEN AN EXTENDED SUBSTRATE AND A BOTTOM SUBSTRATE

A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive. 120-. (canceled)21. An electronic device comprising:a conductive signal distribution layer (SDL) having an upper SDL side and a lower SDL side;a semiconductor die having an upper die side, and a lower die side facing the upper SDL side;a metal contact structure having an upper contact end coupled to the lower die side, and a lower contact end coupled to the upper SDL side;an encapsulating material having an upper encapsulating material side, and a lower encapsulating material side that faces the upper SDL side, wherein the encapsulating material laterally surrounds the semiconductor die and the metal contact structure; anda dielectric layer between lower die side and the upper SDL side and between the lower encapsulating material side and the upper SDL side.22. The electronic device of claim 21 , wherein the lower contact end is coplanar with the lower encapsulating material side.23. The electronic device of claim 21 , wherein the dielectric layer comprises an adhesive layer.24. The electronic device of claim 21 , wherein the dielectric layer comprises a material ...

Method of manufacturing semiconductor devices, corresponding device and circuit

A method of manufacturing semiconductor devices includes: coupling first and the second substrates by coupling a back surface of the second substrate with a front surface of the first substrate, thereby producing a step-like structure, with an uncovered portion of the front surface of the first substrate left uncovered by the second substrate coupling a first integrated circuit with the uncovered portion of the front surface of the first substrate; and coupling a second integrated circuit with the second substrate and the first integrated circuit by arranging the second integrated circuit extending bridge—like between the second substrate and the first integrated circuit.

Semiconductor package

A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

Semiconductor package and electronic device having the same

A semiconductor package includes a substrate including an antenna; a heating element disposed on a first surface of the substrate and connected to the antenna; a heat radiating part coupled to the heating element; and a signal transfer part disposed on the first surface of the substrate and configured to electrically connect the substrate to a main substrate. The heat radiating part may include a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other.

CHIP MODULE WITH STIFFENING FRAME AND ORTHOGONAL HEAT SPREADER

An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, and a first directional heat spreader. A second directional heat spreader may further be arranged orthogonal to the first directional heat spreader. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes an opening that accepts the IC chip and may be attached to the top surface of the carrier. The IC chip is concentrically arranged within the opening of the stiffening frame. The first directional heat spreader is attached to the stiffening frame and to the IC chip and generally removes heat in a first opposing bivector direction. When included in the IC chip module, the second directional heat spreader is attached to the stiffening frame and to the first directional heat spreader and generally removes heat in a second opposing bivector direction orthogonal to the first opposing bivector direction. 1. An integrated circuit chip module comprising:a carrier comprising a top surface and a bottom surface configured to be electrically connected to a motherboard;a stiffening frame attached to the carrier top surface, the stiffening frame comprising a central opening that accepts a semiconductor chip, a base portion, and a plurality of opposing sidewalls;a semiconductor chip electrically connected to the carrier top surface and concentrically arranged within the central opening; anda first directional heat spreader thermally contacting the semiconductor chip, the first directional heat spreader comprising a directionally thermally conductive material arranged to efficiently transfer heat from the semiconductor chip in a first opposing bivector direction towards first opposing sidewalls.2. The integrated circuit chip module of claim 1 , wherein the first directional heat spreader contacts the first opposing sidewalls.3. The integrated circuit chip module of claim 1 , further comprising:a second ...

CHIP MODULE WITH STIFFENING FRAME AND ORTHOGONAL HEAT SPREADER

An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, and a first directional heat spreader. A second directional heat spreader may further be arranged orthogonal to the first directional heat spreader. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes an opening that accepts the IC chip and may be attached to the top surface of the carrier. The IC chip is concentrically arranged within the opening of the stiffening frame. The first directional heat spreader is attached to the stiffening frame and to the IC chip and generally removes heat in a first opposing bivector direction. When included in the IC chip module, the second directional heat spreader is attached to the stiffening frame and to the first directional heat spreader and generally removes heat in a second opposing bivector direction orthogonal to the first opposing bivector direction. 1. A method comprising: a carrier comprising a top surface and a bottom surface configured to be electrically connected to a motherboard;', 'a stiffening frame attached to the carrier top surface, the stiffening frame comprising a central opening that accepts a semiconductor chip;', 'a semiconductor chip electrically connected to the carrier top surface and concentrically arranged within the central opening, a base portion and a plurality of opposing sidewalls; and', 'a first directional heat spreader thermally contacting the semiconductor chip, the first directional heat spreader comprising a directionally thermally conductive material arranged to efficiently transfer heat from the semiconductor chip in a first opposing bivector direction towards first opposing sidewalls., 'electrically connecting a IC chip module to a motherboard and thermally contacting a heat sink to the IC chip module, wherein the IC chip module comprises2. The method of claim 1 , wherein the first directional heat spreader ...

Lid Structure for a Semiconductor Device Package and Method for Forming the Same

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure formed over the substrate. The semiconductor device structure also includes a lid structure formed over the die structure. The lid structure includes a top portion with a top length and a bottom portion with a bottom length, and the top length is greater than the bottom length. The semiconductor device structure also includes a package layer formed between the lid structure and the die structure, and a sidewall of the bottom portion of the lid structure is not aligned with a sidewall of the die structure. 1. A method for forming a semiconductor device structure , the method comprising:attaching a first die to a substrate;attaching a lid to the first die with an adhesive, wherein after the attaching the lid to the first die the adhesive is in physical contact with at least a portion of a sidewall of the first die; andencapsulating the first die and the lid with an encapsulant, wherein after the encapsulating the encapsulant has at least three different widths as it extends from adjacent to the first die to adjacent to the lid.2. The method of claim 1 , wherein the lid has a T-like shape.3. The method of claim 1 , further comprising attaching a ring structure at a peripheral region of the substrate prior to the attaching the first die.4. The method of claim 1 , wherein after the attaching the lid an edge of the adhesive is aligned with an edge of the lid.5. The method of claim 1 , further comprising attaching a second die to the first die.6. The method of claim 1 , wherein the lid has at least one sloped sidewall.7. The method of claim 1 , wherein the encapsulating the first die and the lid further comprises:applying a first material;curing the first material; andapplying a second material after the curing the first material.8. A method for forming a semiconductor device structure claim 1 , the method comprising: ...

Semiconductor package

A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

An electronic package includes a carrier and a semiconductor chip. In a first aspect an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. 1. A electronic package comprising:a carrier comprising a top surface and a bottom surface;a semiconductor chip electrically connected to the top surface;a interleaved seal band connecting the carrier and the lid perimeter; anda lid thermally connected to a top surface of the semiconductor chip and thermally connected with the interleaved seal band.2. The electronic package of claim 1 , wherein the interleaved seal band comprises a patterned epoxy material upon the carrier about the perimeter of the semiconductor chip.3. The electronic package of claim 1 , wherein the interleaved seal band further comprises a patterned elastomeric material upon the carrier about the perimeter of the semiconductor chip.4. The electronic package of claim 3 , wherein the patterned epoxy material is interleaved with the patterned elastomeric material.5. The electronic package of claim 4 , wherein the patterned epoxy material is located at corners of the interleaved seal band.6. The electronic package of claim 5 , wherein a top surface of the epoxy material is coplanar with a top surface of the elastomeric material.7. The electronic package of claim 5 , wherein a top surface of the epoxy material is recessed from a top surface of the elastomeric material.8. The electronic package of claim 1 , wherein the interleaved seal band fills a gap between the carrier and an underside of the lid.9. The electronic package of claim 5 , wherein the patterned epoxy material is further located at the semiconductor chip bisection points of the interleaved seal band.10. The electronic package of claim 1 , wherein the interleaved seal band comprises a high thermally compliant material upon the carrier about the perimeter of the semiconductor chip interleaved with a low thermally compliant material upon ...

LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE

In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness. 1. A electronic package comprising:a carrier comprising a top surface and a bottom surface;a frame comprising an opening upon the carrier, the frame comprising a first frame side and second frame side, the first frame side comprising a top surface coplanar with a top surface of a lid and the second frame side comprising a top surface below the top surface of the lid;a semiconductor chip electrically connected to the top surface within and concentric with the opening;the lid thermally connected to a top surface of the semiconductor chip; andjoin material that connects the lid and the frame.2. The electronic package of claim 1 , wherein the join material contacts a sidewall of the first frame side and a first sidewall of the lid.3. The electronic package of claim 1 , wherein the join material contacts a sidewall and the top surface of the second frame side and a second sidewall of the lid.4. The electronic package of claim 1 , wherein the first sidewall of the lid opposes the second sidewall of the lid.5. The electronic package of claim 1 , wherein the join material is solder.6. The electronic package of claim 1 , wherein the join material is epoxy.7. The electronic package of claim 1 , wherein the join material is elastomeric.8. The electronic package of claim 3 , wherein a top surface of the join material that contacts the top surface of the second frame side is coplanar with the top surface of the lid. Embodiments of the present invention generally relate to electronic devices and more specifically to lid attach techniques to limit warpage within an electronic device package.An electronic package may ...

Semiconductor device package

A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.

Thinned integrated circuit device and manufacturing process for the same

A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic devices, and methods of making thereof, that comprise a permanently coupled carrier that enhances reliability of the electronic devices. 120-. (canceled)21. An electronic device comprising:a substrate having a top substrate side and a bottom substrate side; a first die top side;', 'a first die bottom side coupled to the top substrate side;', 'a plurality of first die lateral sides between the first die top side and the first die bottom side; and', 'a first conductive pad on the first die bottom side;, 'a first semiconductor die coupled to the substrate, the first semiconductor die comprising a second die top side;', 'a second die bottom side coupled to the top substrate side;', 'a plurality of second die lateral sides between the second die top side and the second die bottom side; and', 'a second conductive pad on the second die bottom side; and, 'a second semiconductor die, of a different type of die than the first semiconductor die, coupled to the substrate and positioned laterally apart from the first semiconductor die, the second semiconductor die comprisingan encapsulating material that covers at least the plurality of first die lateral sides and the plurality of second die lateral sides, but does not cover the first die top side and the second die top side.22. The electronic device of claim 21 , wherein the first die top side and the second die top side are at least as high as a top side of the encapsulating material.23. The electronic device of claim 21 , wherein the first die top side claim 21 , the second die top side claim 21 , and a top side of the encapsulating material are coplanar.24. The electronic device of claim 21 , wherein each of the first die top side claim 21 , the second die top side claim 21 , and a top side of the encapsulating material comprises a ground surface.25. The electronic device ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein. 1. (canceled)2. A semiconductor device comprising: 'a base electronic component top side;', 'a base electronic component comprising a substrate top side;', 'a substrate bottom side;', 'a substrate dielectric structure between the substrate top side and the substrate bottom side;', conductive pads at the substrate bottom side; and', 'conductive paths along the substrate dielectric structure and coupled to the conductive pads;, 'a substrate conductive structure comprising, 'and', 'a substrate cavity through the substrate dielectric structure;, 'a substrate comprisingshort interconnects between the base electronic component top side and the substrate bottom side;a dam bounding a perimeter around the short interconnects; andtall interconnects adjacent to the dam between the base electronic component top side and the substrate bottom side, and coupled to the conductive pads of the substrate;anda mounted electronic component in the substrate cavity and coupled to the short interconnects; 'the substrate bottom side covers at least a portion of ...

UNDER-FILL DEFLASH FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE

Described herein methods of manufacturing dual-sided packaged electronic modules that control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include under-filling one or more components and deflashing a portion of the under-fill to remove under-fill material prior to attaching solder balls. The deflashing step removes a thin layer of under-fill material that may have coated contact pads for the ball grid array. Because the solder balls are not present during under-fill, there is little capillary action drawing material away from the components being under-filled. This can reduce the frequency of voids under the components being under-filled. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using under-fill deflash prior to attaching solder balls of the ball grid array. 1. A method of fabricating a packaged radio-frequency device , the method comprising:mounting components to a first side of a packaging substrate;mounting a lower component to a second side of the packaging substrate, the second side of the packaging substrate including a plurality of contact pads for mounting solder balls;under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent, the under-filling agent coating a portion of at least one of the plurality of contact pads;deflashing a portion of the under-filling agent; andmounting the solder balls on the contact pads of the second side of the packaging substrate after the portion of the under-filling agent has been deflashed.2. The method of wherein deflashing includes removing a thin layer of the under-filling agent.3. The method of wherein deflashing includes removing the portion of the under-filling agent that coats the portion of the at least one of the plurality of contact pads.4. The method of wherein a size of a keep out zone is reduced by deflashing a portion ...

FAN-OUT ANTENNA PACKAGING STRUCTURE AND PREPARATION THEREOF

A method for preparing fan-out antenna packaging structure, includes: providing a carrier and a release layer structure; forming a single-layer antenna structure and a redistribution layer on an upper surface of the release layer; disposing a semiconductor chip electrically connected with the redistribution layer; forming a leading-out conducting wire on the redistribution layer at least on one side of the semiconductor chip; forming a plastic packaging layer wrapping the chip and the leading-out conducting wire; removing part of the plastic packaging layer to expose the chip and the leading-out conducting wire; forming an under-bump metal layer and a solder ball bump on an upper surface of the plastic packaging layer; removing the carrier and the release layer to expose the single-layer antenna structure; soldering a substrate on the solder ball bump; and forming a layer of cooling fins on a second surface of the semiconductor chip. 1. A fan-out antenna packaging structure , comprising:a single-layer antenna structure;a redistribution layer formed on a bottom surface of the single-layer antenna structure;one semiconductor chip formed on a bottom surface of the redistribution layer, wherein the semiconductor chip comprises a first surface and a second surface opposite to the first surface, wherein the first surface of the semiconductor chip sits on and is electrically connected with the redistribution layer;a leading-out conducting wire formed on and electrically connected to the bottom surface of the redistribution layer at least on one side of the semiconductor chip;a plastic packaging layer formed on the bottom surface of the redistribution layer and wrapping around the semiconductor chip and the leading-out conducting wire;an under-bump metal layer formed on a bottom surface of the plastic packaging layer and electrically connected with the leading-out conducting wire;a solder ball bump formed on a bottom surface of the under-bump metal layer;a substrate formed ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device according to an embodiment of the present invention comprises pads electrically connected to wires provided on an insulating substrate. A wiring substrate comprises a first insulant provided between the pads. A first semiconductor chip comprises metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate. A first adhesion layer is provided between the first insulant and the first semiconductor chip and adheres the wiring substrate and the first semiconductor chip to each other. An insulating resin is provided to cover peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate. 1. A semiconductor device comprising:a wiring substrate comprising pads electrically connected to wires provided on an insulating substrate, and a first insulant provided between the pads;a first semiconductor chip comprising metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate;a first adhesion layer provided between the first insulant and the first semiconductor chip and adhering the wiring substrate and the first semiconductor chip to each other; andan insulating resin covering peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate.2. The device of claim 1 , wherein the first adhesion layer has a thermal expansion coefficient larger than those of the wiring substrate and the first semiconductor chip.3. The device of claim 1 , wherein the first adhesion layer has an elastic modulus lower than those of the first insulant and the metal bumps.4. The device of claim 2 , wherein the first adhesion layer has an elastic modulus lower than those of the first insulant and the metal bumps.5. The device of claim 1 , wherein the first adhesion layer is placed ...

Semiconductor package

A semiconductor package includes a package substrate, a logic chip on an upper surface of the package substrate and electrically connected to the package substrate, a heat sink contacting an upper surface of the logic chip to dissipate a heat generating from the logic chip, and a memory chip disposed on an upper surface of the heat sink and electrically connected to the package substrate.

Dual side cooling power module and manufacturing method of the same

A dual side cooling power module includes: a lower substrate including a recessed portion on at least one surface thereof, a semiconductor chip formed in the recessed portion, lead frames formed at both ends of the lower substrate, and an upper substrate formed on the semiconductor chip, a portion of the lead frames, and the lower substrate.

Semiconductor package

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The second redistribution structure is vertically overlapped with the first redistribution structure. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively have an active side and a back side opposite to the active side, as well as a conductive pillar at the active side. The back side of the first semiconductor die is attached to the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached to the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends to the second redistribution structure. 1. A semiconductor package , comprising:a first redistribution structure;a second redistribution structure, vertically overlapped with the first redistribution structure;a first semiconductor die and a second semiconductor die, located between the first and second redistribution structures, and respectively having an active side and a back side opposite to the active side, as well as a conductive pillar at the active side, wherein the back side of the first semiconductor die is attached to the back side of the second semiconductor die, the conductive pillar of the first semiconductor die is attached to the first redistribution structure, and the conductive pillar of the second semiconductor die extends to the second redistribution structure; andan encapsulant, laterally encapsulating the first semiconductor die and the second semiconductor die.2. The semiconductor package according to claim 1 , further comprising:an additional first semiconductor die, having an active side and a back side opposite to the active side, and having a conductive pillar at the active side, ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.

Package structure and method for manufacturing same

An exemplary package substrate includes a package substrate, a first connection substrate, a first chip, a dielectric adhesive sheet, a second chip, and a second connection substrate. The package substrate includes many first and second electrical contact pads. The first connection substrate includes many third and fourth electrical contact pads. Each fourth electrical contact pad is electrically connected to one first electrical contact pad. The first chip includes many first electrode pads. Each first electrode pad is electrically connected to the corresponding third electrical contact pad. The second chip is connected to the first chip by the dielectric adhesive sheet, and includes many second electrode pads. The second connection substrate includes many fifth and sixth electrical contact pads. Each fifth electrical contact pad is electrically connected to one second electrode pad, and each sixth electrical contact pad is electrically connected to one second electrical contact pad.

Semiconductor package and fabricating method thereof

A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure including a substrate, a semiconductor device, a heat spreader, and an adhesive layer is provided. The semiconductor device is bonded onto the substrate, wherein an angle θ is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°<θ<90°. The heat spreader is disposed over the substrate, wherein the semiconductor device is disposed between the heat spreader and the substrate. The adhesive layer is surrounding the semiconductor device and attaching the heat spreader onto the substrate, wherein the adhesive layer has a first opening misaligned with one of corners of the semiconductor device closest to the first opening. 1. A package structure comprising:a semiconductor device bonded onto a substrate, wherein an angle θ is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°<θ<90°;a heat spreader disposed over the substrate, wherein the semiconductor device is disposed between the heat spreader and the substrate; andan adhesive layer surrounding the semiconductor device and attaching the heat spreader onto the substrate, wherein the adhesive layer has a first opening misaligned with one of corners of the semiconductor device closest to the first opening.2. The package structure as claimed in claim 1 , wherein at least one of the semiconductor device and the substrate is square shape or rectangular shape.3. The package structure as claimed in claim 1 , wherein the angle θ is about 45 degrees.4. The package structure as claimed in claim 1 , wherein a width of the adhesive layer adjacent to the one of corners of the semiconductor device is greater than a width of the adhesive layer adjacent to the first opening.5. The package structure as claimed in claim 1 , wherein the heat spreader comprises:a main portion substantially covering a top surface of the semiconductor device; anda supporting portion between the main portion and the adhesive layer.6. The package structure as ...

3DIC Packaging with Hot Spot Thermal Management Features

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material. 1. A package comprising: a plurality of first dies; and', 'a second die bonded to the plurality of first dies, wherein a first portion of the second die is disposed directly under the plurality of first dies, and wherein a second portion of the second die extends laterally past sidewalls of the plurality of first dies; and, 'a die stack comprising a conductive line extending continuously from the plurality of conductive connectors to a thermal interface material (TIM) at the top surface of the package substrate; and', 'a solder resist, wherein the solder resist covers a first portion of the conductive line and does not cover a second portion of the conductive line, and wherein the TIM extends through the solder resist to contact the second portion of the conductive line., 'a package substrate, wherein the die stack is bonded to a top surface of the package substrate by a plurality of conductive connectors, and wherein the package substrate comprises2. The package of claim 1 , further comprising a heat dissipation feature adhered to the package substrate by an adhesive claim 1 , wherein the conductive line is thermally connected to the heat dissipation feature through the TIM.3. The package of claim 2 , wherein the heat dissipation feature is adhered to the package substrate by an adhesive having a lower thermal conductivity than the TIM.4. The package of claim 3 , wherein the adhesive encircles the second portion of the conductive line in a top down view.5. The package of claim 1 , wherein the conductive line is a signal line claim 1 ...

Semiconductor package, method for forming semiconductor package, and method for forming semiconductor assembly

A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.

Semiconducor device and method of manufacturing the same

The present invention relates to a method of making a semiconductor device having a chip embedded in a heat spreader and electrically connected to a hybrid substrate. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a heat spreader using an adhesive with the chip inserted into a cavity of the heat spreader. The heat spreader provides thermal dissipation and the interposer provides a CTE-matched interface and primary fan-out routing for the chip.

Embedded copper structure for microelectronics package

An electronic component and a method of manufacturing an electronic component, the method including surface mounting electronic components to a printed circuit board (PCB), applying a flip-chip die integrated circuit (IC) to the PCB and underfilling the flip-chip IC to secure the PCB. The method also includes sintering a copper block to the PCB, where the copper block is in thermal communication with the IC and acts as a thermal path for removing heat generated by the flip-chip IC.

Manufacturing method of package-on-package structure

A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.

Package structure and manufacturing method thereof

A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.

Chip package structure and manufacturing method thereof

A chip package structure including a substrate, a first chip, a frame, a plurality of first conductive connectors, a first encapsulant, and a package is provided. The first chip is disposed on the substrate. The first chip has an active surface and a back surface opposite to the active surface, and the active surface faces the substrate. The frame is disposed on the back surface of the first chip and the frame has a plurality of openings. The first conductive connectors are disposed on the substrate and the first conductive connectors are disposed in correspondence to the openings. The first encapsulant is disposed between the substrate and the frame and encapsulates the first chip. The package is disposed on the frame and is electrically connected to the substrate via the first conductive connectors.

SENSING DEVICE AND METHOD FOR FORMING THE SAME

A method for forming a sensing device includes providing a first substrate. The first substrate has a first surface and a second surface opposite thereto. A sensing region is adjacent to the first surface. A temporary cover plate is provided on the second surface to cover the sensing region. The method also includes forming a redistribution layer on the second surface and electrically connected to the sensing region. The method further includes removing the temporary cover plate after the formation of the redistribution layer. The first substrate is bonded to a second substrate and a cover plate after the removal of the temporary cover plate so that the first substrate is positioned between the second substrate and the cover plate. In addition, the method includes filling an encapsulating layer between the second substrate and the cover plate to surround the first substrate. 1. A method for forming a sensing device , comprising:providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to the first surface, and wherein a sensing region is adjacent to the first surface;providing a temporary cover plate over the second surface to cover the sensing region;forming a redistribution layer over the second surface, wherein the redistribution layer is electrically connected to the sensing region;removing the temporary cover plate after the formation of the redistribution layer;bonding the first substrate to a second substrate and a cover plate after the removal of the temporary cover plate, so that the first substrate is between the second substrate and the cover plate, wherein the redistribution layer is electrically connected to the second substrate; andfilling an encapsulating layer between the second substrate and the cover plate to surround the first substrate.2. The method for forming a sensing device as claimed in claim 1 , further comprising thinning the first substrate from the second surface before the formation of ...

Dual side die packaging for enhanced heat dissipation

An Integrated Circuit (IC) device structure is provided. The IC device structure includes a first substrate, first one or more dies coupled to a first side of the first substrate by a first plurality of interconnect structures, second one or more dies coupled to a first section of a second side of the substrate by a second plurality of interconnect structures, and a third plurality of interconnect structures to couple a second section of the second side of the substrate to a second substrate. In an example, at least a part of the second one or more dies are within a cavity in the second substrate.

Fabrication method of semiconductor package

A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Semiconductor device

A semiconductor device may include a cooling unit, the cooling unit including a circuit unit, a first flow path member comprised of an insulating material, and a second flow path member comprised of an insulating material. The circuit unit may include a heat sink layer, a wiring layer, and a semiconductor element that is disposed between the heat sink layer and the wiring layer. The circuit unit is disposed between the first flow path member and the second flow path member. The wiring layer may face the first flow path member or the second flow path member.

Semiconductor Device

A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate arranged on an upper surface of the semiconductor element with an adhesive arranged in between, and an encapsulation resin filling a gap between the heat dissipation plate and the wiring substrate. The heat dissipation plate includes a body and a projection. The body is overlapped with the semiconductor element in a plan view and has a larger planar shape than the semiconductor element. The projection is formed integrally with the body. The projection projects outward from an end of the body and is located below the body. The encapsulation resin covers upper and lower surfaces of the projection. The body includes an upper surface exposed from the encapsulation resin.

Electronics package having a multi-thickness conductor layer and method of manufacturing thereof

An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same

A semiconductor assembly with three dimensional integration includes a face-to-face semiconductor sub-assembly electrically coupled to a heat spreader by bonding wires. The face-to-face semiconductor sub-assembly includes top and bottom devices assembled on opposite sides of a first routing circuitry, and the heat spreader includes a metal plate and a second routing circuitry on the metal plate. The sub-assembly is disposed in a through opening of the second routing circuitry of the heat spreader, and the bonding wires provide electrical connections between the first and second routing circuitries for interconnecting the devices face-to-face assembled in the sub-assembly to terminal pads provided in the heat spreader

Semiconductor module, circuit board

An improvement in the manufacturing efficiency of a circuit substrate and a semiconductor module where a semiconductor device including electrodes on a front and a back surface is mounted. [Solution] A semiconductor module includes a wiring substrate where a via and a interconnecting pattern are formed, a semiconductor device disposed on a first surface side of the wiring substrate, and a bonding portion including a first bonding layer disposed on the wiring substrate side and a second bonding layer disposed on the semiconductor device side. The first bonding layer includes a first insulation layer having inorganic material as the main constituent, a through hole formed in an area of the first insulation layer corresponding to the via, and a conductive bonding portion, disposed in the through hole, for establishing electrical continuity between an electrode portion formed on the semiconductor device and the wiring substrate, and has a first bonding start temperature to start bonding to the wiring substrate, and the second bonding layer includes a second insulation layer having inorganic material as the main constituent, and an opening portion communicating with the through hole and configured to dispose the semiconductor device therein, and has a second bonding start temperature being a temperature to start bonding to the semiconductor device, the temperature being different from the first bonding start temperature.

CHIP PACKAGE WITH INTERPOSER SUBSTRATE AND METHOD FOR FORMING THE SAME

A method for forming a chip package is provided. The method includes disposing a chip over a redistribution structure. The redistribution structure includes a first insulating layer and a first wiring layer, and the first wiring layer is in the first insulating layer and electrically connected to the chip. The method includes bonding an interposer substrate to the redistribution structure through a conductive structure. The chip is between the interposer substrate and the redistribution structure. The interposer substrate has a recess adjacent to the redistribution structure. A first portion of the chip is in the recess. The interposer substrate includes a substrate and a conductive via structure, and the conductive via structure passes through the substrate and is electrically connected to the first wiring layer through the conductive structure. 1. A method for forming a chip package , comprising:disposing a chip over a redistribution structure, wherein the redistribution structure comprises a first insulating layer and a first wiring layer, and the first wiring layer is in the first insulating layer and electrically connected to the chip; andbonding an interposer substrate to the redistribution structure through a conductive structure, wherein the chip is between the interposer substrate and the redistribution structure, the interposer substrate has a recess adjacent to the redistribution structure, a first portion of the chip is in the recess, the interposer substrate comprises a substrate and a conductive via structure, and the conductive via structure passes through the substrate and is electrically connected to the first wiring layer through the conductive structure.2. The method for forming the chip package as claimed in claim 1 , further comprising:forming an underfill layer between the interposer substrate and the redistribution structure and between the interposer substrate and the chip after bonding the interposer substrate to the redistribution structure ...

Integrated device package comprising heterogeneous solder joint structure

Some features pertain to an integrated circuit device that includes a first package substrate, a first die coupled to the first package substrate, a second package substrate, and a solder joint structure coupled to the first package substrate and the second package substrate. The solder joint structure includes a solder comprising a first melting point temperature, and a conductive material comprising a second melting point temperature that is less than the first melting point temperature. In some implementations, the conductive material is one of at least a homogeneous material and/or a heterogeneous material. In some implementations, the conductive material includes a first electrically conductive material and a second material. The conductive material is an electrically conductive material.

SEMICONDUCTOR DEVICE WITH ENHANCED THERMAL DISSIPATION AND METHOD FOR MAKING THE SAME

A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK. 1. A method , comprising:forming a solder layer on a surface of one or more chips;positioning a lid over the solder layer on each of the one or more chips; andapplying heat and pressure to melt the solder layer and attach each lid to a corresponding chip via the solder layer,wherein the solder layer has a thermal conductivity of ≥50 W/mK.2. The method according to claim 1 , further comprising forming an integrated fan-out wafer on a frame claim 1 , wherein the integrated fan-out wafer includes the one or more chips claim 1 , before forming the solder layer on the surface of the one or more chips.3. The method according to claim 1 , wherein the solder layer is a patterned solder layer.4. The method according to claim 3 , wherein the patterned solder layer includes a plurality of spaced-apart solder regions.5. The method according to claim 1 , further comprising forming a plurality of bonding pads on the surface of the one or more chips before forming the solder layer.6. The method according to claim 5 , further comprising:forming a metal pillar on each of the plurality of bonding pads before forming the solder layer,wherein the solder layer comprises solder balls formed on each of the metal pillars.7. The method according to claim 6 , wherein the metal pillars are formed of copper.8. The method according to claim 1 , further comprising forming a thermal interface material between the lid and the surface of the chip.9. The method according to claim 2 , further comprising separating the one or more chips before positioning the lids.10. The method according to claim 2 , further comprising:removing the one or more chips from the frame; andattaching the one or ...

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer. 1. A method of forming a package , the method comprising:forming a metal bump on a top surface of a first package component;forming a solder region on a top surface of the metal bump;forming a protection layer extending on a sidewall of the metal bump;reflowing the solder region to bond the first package component to a second package component; anddispensing an underfill between the first package component and the second package component, wherein the underfill is in contact with the protection layer.2. The method of claim 1 , wherein the protection layer is formed through inkjet printing.3. The method of claim 2 , wherein in the inkjet printing claim 2 , the protection layer is printed to a location spaced apart from the metal bump claim 2 , and the protection layer extends to the sidewall of the metal bump through capillary action.4. The method of claim 1 , wherein the forming the protection layer comprises:spin coating the protection layer on the first package component, wherein the protection layer comprises a portion on a top surface of the solder region; andperforming a lithography process to remove the portion of the protection layer on the top surface of the solder region.5. The method of claim 1 , wherein the forming the protection layer comprises dispensing a light-sensitive polymer claim 1 , and the protection layer is free from filler particles therein.6. The method of claim 1 , wherein the protection layer is spaced apart from the solder region.7. The method of further comprising claim 1 , after ...

THERMAL INTERFACE MATERIAL LAYER AND PACKAGE-ON-PACKAGE DEVICE INCLUDING THE SAME

Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package. 120-. (canceled)21. A semiconductor package device having a package-on-package (PoP) structure , the semiconductor package device comprising:a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted on the lower package substrate;an upper semiconductor package including an upper package substrate and a first upper semiconductor chip on the upper package substrate;a connection solder bump between the upper package substrate and the lower package substrate, the connection solder bump electrically connecting the tipper semiconductor package and the lower semiconductor package;a thermal conductive material between the lower semiconductor package and the upper semiconductor package,the thermal conductive material including a resin layer and filler particles distributed in the resin layer; anda lower mold layer covering a sidewall of the lower semiconductor chip, and not covering a top surface of the lower semiconductor chip.2228-. (canceled)29. The semiconductor package device of claim 21 , wherein at least one of the filler particles comprises a metal particle coated with an insulating layer claim 21 , and the metal particle has a hardness lower than seven.3036-. (canceled)37. The semiconductor package device of claim 21 , wherein the thermal conductive material includes a thermal interface material layer.38. The semiconductor package device of claim 37 , wherein the thermal interface material layer has a modulus of elasticity of ...

Microelectronics h-frame device

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.

3DIC Packages with Heat Dissipation Structures

A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending laterally beyond a respective edge of the first die. The package further includes a first Thermal Interface Material (TIM) over and contacting a top surface of the first die, a heat dissipating lid having a first bottom surface contacting the first TIM, a second TIM over and contacting the second portion of the second die, and a heat dissipating ring having a portion over and contacting the second TIM. The heat dissipating lid and the heat dissipating ring are discrete components, and at least one of the heat dissipating lid or the heat dissipating ring has a plurality of fins and a plurality of recesses separating the plurality of fins from each other. 1. A package comprising:a first die; a first portion overlapped by the first die; and', 'a second portion extending laterally beyond a respective edge of the first die;, 'a second die underlying the first die and in a same first die stack as the first die, wherein the second die comprisesa first Thermal Interface Material (TIM) over and contacting a top surface of the first die;a heat dissipating lid comprising a first bottom surface contacting the first TIM;a second TIM over and contacting the second portion of the second die; anda heat dissipating ring comprising a portion over and contacting the second TIM, wherein the heat dissipating lid and the heat dissipating ring are discrete components, and at least one of the heat dissipating lid or the heat dissipating ring comprises a plurality of fins and a plurality of recesses separating the plurality of fins from each other.2. The package of claim 1 , wherein the heat dissipating lid comprises the plurality of fins and the plurality recesses.3. The package of further comprising an adhesive film claim 2 , wherein a bottom surface of the heat ...

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64. 1. A multi-chip package comprising:an interconnection scheme comprises a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer and a polymer layer between the first and second interconnection metal layers, wherein the first interconnection metal layer comprises a copper layer having a thickness between 0.3 and 20 micrometers and an adhesion layer at a bottom of the copper layer but not at a sidewall of the copper layer;a first semiconductor integrated-circuit (IC) chip over the interconnection scheme, wherein the first semiconductor integrated-circuit (IC) chip couples to the interconnection scheme, wherein the first semiconductor integrated-circuit (IC) chip is configured to be programmed to perform a logic operation, comprising a non-volatile memory cell configured to store a resulting data of a look-up table (LUT), a sense amplifier configured to sense an input data thereof at a first input point of the sense amplifier by comparing the input data of the sense amplifier with a voltage at a second input point of the sense amplifier to generate an output data thereof at an output point of the sense amplifier, wherein the input data of the ...

LIGHT EMITTING DEVICE

A light emitting device includes a substrate, a light emitting element, and a protective element. The substrate includes a support member and a plurality of wirings disposed on an upper surface of the support member. The substrate has a first side extending in a first direction and a second side opposite to the first side. The light emitting element is disposed on an upper surface of the substrate, and the protective element is disposed on the upper surface of the substrate. The plurality of wirings has a plurality of external connecting portions disposed adjacent to the first side and arranged in the first direction in a plan view. The protective element is disposed between the light emitting element and the second side of the substrate. 1. A light emitting device comprising:a substrate comprising a support member and a plurality of wirings disposed on an upper surface of the support member, the substrate having a first side extending in a first direction and a second side opposite to the first side;a light emitting element disposed on an upper surface of the substrate; anda protective element disposed on the upper surface of the substrate,wherein the plurality of wirings has a plurality of external connecting portions disposed adjacent to the first side and arranged in the first direction in a plan view, andwherein the protective element is disposed between the light emitting element and the second side of the substrate in the plan view.2. The light emitting device according to claim 1 , further comprising a first protruding member disposed on the upper surface of the substrate claim 1 , the first protruding member extending in the first direction claim 1 ,wherein the light emitting element and the protective element are disposed on a first side of the first protruding member and the plurality of external connecting portions is disposed on a second side of the first protruding member in the plan view, the first side of the first protruding member being opposite to ...

PACKAGE WITH ISOLATION STRUCTURE

Embodiments are provided herein for a packaged semiconductor device that includes a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and an isolation structure on the outer surface of the RDL structure around one or more contact pads of the plurality of contact pads, wherein a height of the isolation structure is at least two thirds of a height of the external connections. 1. A packaged semiconductor device comprising:a package comprising: a semiconductor die, and a redistribution layer (RDL) structure on an active side of the semiconductor die;a plurality of contact pads on an outer surface of the RDL structure;a plurality of external connections attached to the plurality of contact pads; andan isolation structure on the outer surface of the RDL structure around a set of at least two contact pads of the plurality of contact pads, wherein a height of the isolation structure is at least two thirds of a height of the external connections.2. The packaged semiconductor device of claim 1 , wherein the set of at least two contact pads are connected to radio frequency (RF) signal lines of the semiconductor die.3. The packaged semiconductor device of claim 1 , whereinthe plurality of external connections is configured to be attached to a plurality of landing pads of a printed circuit board (PCB), andan edge of the isolation structure is configured to be separated from the PCB by a stand off height.4. The packaged semiconductor device of claim 3 , whereinthe isolation structure is configured to be a barrier between a set of at least two external connections attached to the set of at least two contact pads and an adhesive material between the RDL structure and the PCB.5. The packaged semiconductor device of claim 1 , whereinthe isolation structure ...

CONTROL OF UNDER-FILL USING AN ENCAPSULANT AND A TRENCH OR DAM FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE

Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use an encapsulant on solder balls in combination with a dam or a trench to control the distribution of an under-fill material between one or more components and a packaging substrate. The encapsulant can be used in the ball attach process. The fluxing agent leaves behind a material that encapsulates the base of each solder ball. The encapsulant reduces the tendency of the under-fill material to wick around the solder balls by capillary action which can prevent or limit the capillary under-fill material from flowing onto or contacting other components. The dam or trench aids in retaining the under-fill material within a keep out zone to prevent or limit the under-fill material from contacting other components. 1. A method of fabricating a packaged radio-frequency (RF) device , the method comprising:mounting electrical components to a first side of a packaging substrate;forming a dam on a second side of the packaging substrate;attaching solder balls to the second side of the packaging substrate;encapsulating the solder balls with an encapsulant;attaching a lower electrical component to the second side of the packaging substrate; andunder-filling the lower electrical component mounted with an under-filling agent such that the under-filling agent contacts the encapsulant or contacts the dam.2. The method of wherein the encapsulant is a polymer.3. The method of wherein the encapsulant is not removed in a cleaning process following attachment of the solder balls to the packaging substrate.4. The method of wherein the encapsulant forms an obtuse angle with the packaging substrate.5. The method of wherein the encapsulant forms an obtuse angle to the solder balls.6. The method of wherein the under-filling agent contacts the encapsulant and not the solder balls.7. The method of wherein the combination of the dam and the encapsulant is configured to limit the distribution ...

Semiconductor package and method of forming the same

A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The lid is disposed over the substrate. The lid includes a cap portion and a foot portion extending from a bottom surface of the cap portion. The cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess. The adhesive includes a sidewall portion and a bottom portion. The sidewall portion contacts a sidewall of the foot portion. The bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate.

Semiconductor device, electronic device, and manufacturing method

The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.

PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A package structure includes a wiring structure, at least one electronic device, a reinforcement structure, a plurality of conductive vias and an encapsulant. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The electronic device is electrically connected to the wiring structure. The reinforcement structure is disposed on a surface of the wiring structure, and includes a thermoset material. The conductive vias is disposed in the reinforcement structure. The encapsulant covers the electronic device. 1. A package structure , comprising:a wiring structure including at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer;at least one electronic device electrically connected to the wiring structure;a reinforcement structure disposed on a surface of the wiring structure, and including a thermoset material;a plurality of conductive vias disposed in the reinforcement structure; andan encapsulant covering the at least one electronic device.2. The package structure of claim 1 , further comprising an underfill disposed between the at least one electronic device and the reinforcement structure.3. The package structure of claim 2 , wherein the underfill contacts the reinforcement structure directly.4. The package structure of claim 1 , wherein the reinforcement structure contacts the wiring structure directly.5. The package structure of claim 1 , wherein a size of the reinforcement structure substantially covers the wiring structure from a top view.6. The package structure of claim 1 , wherein a lateral surface of the reinforcement structure is substantially coplanar with the lateral surface of the wiring structure.7. The package structure of claim 1 , wherein the wiring structure has an first surface and a second surface opposite to the first surface claim 1 , the reinforcement structure is disposed on the first surface of the wiring structure claim 1 , and ...

Semiconductor package

A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

Semiconductor device

A semiconductor device includes a semiconductor chip and a package structure mounted on a wiring substrate, and a lid for covering the semiconductor chip, which is fixed to the surface of the wiring substrate, without overlapping with the package structure in plan view. The lid includes an upper surface portion overlapping with the semiconductor chip, a flange portion fixed to the surface of the wiring substrate, and a slant portion for jointing the upper surface portion and the flange portion. Then, a distance from the surface of the wiring substrate to the top surface of the upper surface portion is larger than a distance from the surface of the wiring substrate to the top surface of the flange portion.

Semiconductor package with package-on-package stacking capability and method of manufacturing the same

The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip.

SEMICONDUCTOR PACKAGE INCLUDING ORGANIC INTERPOSER

A semiconductor package including an organic interposer includes: the organic interposer including insulating layers and wiring layers formed on the insulating layers; a stiffener disposed on the interposer and having a through-hole; a first semiconductor chip disposed in the organic through-hole on the organic interposer; a second semiconductor chips disposed adjacent to the first semiconductor chip in the through-hole on the organic interposer; and an underfill resin filling at least portions of the through-hole and fixing the first semiconductor chip and the second semiconductor chip, wherein the connection pads of the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the wiring layers of the organic interposer. 118-. (canceled)19. A semiconductor package , comprising:an organic interposer including wiring layers;a first semiconductor chip disposed on the organic interposer and electrically connected to the wiring layers of the organic interposer;a plurality of second semiconductor chips disposed adjacent to the first semiconductor chip and electrically connected to the wiring layers of the organic interposer, wherein two or more plurality of second semiconductor chips among the plurality of second semiconductor chips are adjacent to one side of the first semiconductor chip and two or more plurality of second semiconductor chips among the plurality of second semiconductor chips are adjacent to the other side opposite to the one side of the first semiconductor chip;a warpage control material disposed on the organic interposer and having a surrounding portion surrounding the first semiconductor chip and the plurality of second semiconductor chips, and a plurality of protruding portions extending from the surrounding portion to between two adjacent second semiconductor chips adjacent to the same side of the first semiconductor chip among the plurality of second semiconductor chips; andan underfill resin ...

METHOD OF MANUFACTURING PACKAGE-ON-PACKAGE DEVICE AND BONDING APPARATUS USED THEREIN

A method of manufacturing a package-on-package device includes a bonding step carried out by a bonding apparatus including a pressing member and a light source that produces a laser beam. A bottom package including a lower substrate, lower solder balls alongside an edge of the lower substrate, and a lower chip on a center of the lower substrate is provided, the bottom package is bonded to an interposer substrate having upper solder balls aligned with the lower solder balls, and a top package having an upper substrate and an upper chip on the upper substrate is bonded to the interposer substrate. While the interposer substrate is disposed on the bottom package, the pressing member presses the interposer substrate against the bottom package, and the laser beam adheres the lower solder balls to the upper solder balls. 2. The apparatus of claim 1 , wherein the optical system comprises:a light source generating the laser beam; andan objective below the light source and proving the laser beam onto the interposer substrate,wherein the pressing member is disposed between the objective and the interposer substrate.3. The apparatus of claim 2 , wherein the objective comprises a concave lens.4. The apparatus of claim 1 , wherein the pressing block is disposed on a center of the pressing plate.5. The apparatus of claim 4 , wherein the center of the pressing plate is thin an edge of the pressing plate.6. The apparatus of claim 1 , wherein the pressing plate comprises a transparent quartz.7. The apparatus of claim 1 , wherein the pressing block is aligned on the semiconductor chip.8. The apparatus of claim 1 , wherein the pressing plate comprises a cavity in which the pressing block is fixed.9. The apparatus of claim 1 , wherein the pressing block has a density greater than a density of the pressing plate.10. The apparatus of claim 1 , wherein the pressing block comprises metal.12. The apparatus of claim 11 , wherein the objective comprises a concave lens.13. The apparatus of ...

System and Method for Bonding Package Lid

Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.

Semiconductor device with reduced thickness

A semiconductor device with reduced thickness is disclosed and may include forming a back end of line (BEOL) comprising a redistribution layer on a dummy substrate. A first semiconductor die may be bonded to a first surface of the BEOL and a second semiconductor die may be bonded to the first semiconductor die. The first and second semiconductor dies may be electrically coupled to the BEOL. The first and second semiconductor dies and the BEOL may be encapsulated utilizing a first encapsulant. The dummy substrate may be removed thereby exposing a second surface of the BEOL opposite to the first surface. A solder ball may be placed on the exposed second surface of the BEOL. The second semiconductor may be stacked stepwise on the first semiconductor and may be flip-chip bonded. The semiconductor dies may be electrically coupled to the BEOL utilizing a lateral plating layer or conductive wires.

Thermal management component

Thermal management technology is disclosed. A thermal management component in accordance with the present disclosure can comprise a heat spreader having a plurality of microchannels. The thermal management component can also comprise a plurality of fins directly coupled to the heat spreader to provide surface area for heat transfer. In another aspect, a thermal management component can comprise a heat spreader having a plurality of microchannels, and an inlet port and an outlet port in fluid communication with the plurality of microchannels. The thermal management component can also comprise a plurality of fins coupled to the heat spreader to provide surface area for heat transfer. Additionally, the thermal management component can comprise a fluid conduit thermally coupled to the plurality of fins and fluidly coupled to the outlet port and the inlet port to facilitate flow of a heat transfer fluid through the microchannels and the fluid conduit. Associated electronic devices, systems, and methods are also disclosed.

CHIP PACKAGE WITH REDISTRIBUTION STRUCTURE

A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer. 1. A chip package , comprising: a redistribution structure comprising a first insulating layer, a first wiring layer, a second insulating layer, and a second wiring layer, wherein the first wiring layer is over the first insulating layer, the second insulating layer covers the first insulating layer and the first wiring layer, the first wiring layer has a conductive pad, the conductive pad is exposed from the first insulating layer, a first lower portion of the conductive pad is narrower than a first upper portion of the conductive pad, and the second wiring layer protrudes from the second insulating layer;', 'a third insulating layer under the first insulating layer of the redistribution structure, and having a through hole corresponding to the conductive pad of the first wiring layer, wherein the conductive pad overlaps the third insulating layer; and', 'a fourth insulating layer disposed between the redistribution structure and the third insulating layer; and, 'a substrate structure, comprisinga chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer ...

SEMICONDUCTOR PACKAGE HAVING A SIDEWALL CONNECTION

A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections. 1. A device , comprising:a semiconductor die including a first surface and a second surface that is transverse to the first surface;a contact pad on the first surface of the semiconductor die;a redistribution layer on the first surface of the semiconductor die and the contact pad, the redistribution layer having an extended portion extending from the contact pad to the second surface of the semiconductor die, the extended portion including a first electrical contact on the second surface of the semiconductor die; anda conductive structure on the redistribution layer spaced from the contact pad, the conductive structure including a second electrical contact on the first surface of the semiconductor die.2. The device of claim 1 , wherein the second electrical contact includes an under bump metallization claim 1 , a solder ball or a solder bump.3. The device of claim 1 , wherein the first electrical contact and the second electrical contact provide distinct electrical signals from each other.4. The device of claim 1 , wherein the semiconductor die includes a third surface opposite the first surface claim 1 , and the extended portion extends past the first ...

Heterogeneous Antenna in Fan-Out Package

A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output. 1. A multi-chip package comprising:a first interconnection scheme comprising a first insulating dielectric layer, a first interconnection metal layer on the first insulating dielectric layer and a second insulating dielectric layer on the first interconnection metal layer;a chip-on-chip package over the first interconnection scheme, wherein the chip-on-chip package comprises a first semiconductor chip over the first interconnection scheme and a second semiconductor chip over the first semiconductor chip, wherein the second semiconductor chip couples to the first semiconductor chip, wherein the first semiconductor chip comprises a silicon substrate, a transistor at a surface of the silicon substrate, and a first through silicon via (TSV) in the silicon substrate, wherein the first through silicon via (TSV) vertically extends through the silicon substrate, wherein the first interconnection metal layer is under across an edge of the chip-on-chip package;a first metal interconnect between the chip-on-chip package and the first interconnection scheme, wherein the first interconnection metal layer couples to the first through silicon via (TSV) through the first metal interconnect;a polymer layer on the second insulating dielectric layer and in a space outside of the chip-on-chip package and extending in a horizontal ...

DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above. 117-. (canceled)18. A method of encapsulating a die into a semiconductor wafer assembly , the method comprising:etching a cavity into an oxide bonded semiconductor wafer stack;positioning a semiconductor die in the cavity;mechanically and electrically mounting the semiconductor die to the wafer stack; andencapsulating the semiconductor die within the cavity by bonding a lid wafer to the wafer stack.19. The method of claim 18 , wherein mechanically and electrically mounting the semiconductor die comprises a process selected from bump bonding claim 18 , wire interconnecting claim 18 , ultrasonic bonding claim 18 , and oxide bonding.20. The method of claim 18 , wherein bonding the lid wafer to the wafer stack further comprises:creating an oxide layer a first surface of the wafer stack;creating an oxide layer on a first surface of the lid wafer; andbonding the oxide layer of the first surface of the wafer stack to the oxide layer of the first surface of the lid wafer to create a wafer assembly and to form a hermetic seal around the cavity.21. The method of claim 18 , further comprising forming a conduit from the exterior of the wafer assembly through the lid wafer to the cavity.22. The method of claim 21 , further comprising delivering a sufficient amount of a ...

SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING THE SAME

A semiconductor package includes a substrate including an antenna; a heating element disposed on a first surface of the substrate and connected to the antenna; a heat radiating part coupled to the heating element; and a signal transfer part disposed on the first surface of the substrate and configured to electrically connect the substrate to a main substrate. The heat radiating part may include a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other. 1. A semiconductor package comprising:a substrate comprising a wiring layer;a heating element disposed on a first surface of the substrate and connected to the wiring layer;a heat radiating part coupled to the heating element; anda signal transfer part electrically connecting the substrate to a main substrate;a sealing part substantially enclosing the signal transfer part and the heating element,wherein the sealing part is formed of a single insulating material, andthe heat radiating part includes a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other.2. The semiconductor package of claim 1 , wherein the heat transfer part has a flat plate shape or a block shape and comprises a metal.3. The semiconductor package of claim 1 , further comprising connection terminals disposed on one side of the signal transfer part and connected to the main substrate claim 1 ,wherein the heat radiating terminal comprises a material in common with the connection terminal and has substantially the same size as the connection terminal.4. The semiconductor package of claim 1 , wherein the single insulating material is epoxy molding compound (EMC).5. The semiconductor package of claim 1 , wherein the heat transfer part is embedded in the sealing part claim 1 , andthe heat radiating terminal penetrates through the sealing part and is connected to the ...

RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE

A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates. 1. A reconstituted interposer package comprising:an interposer substrate electrically mounted to a first surface of a reconstituted die-attach substrate and straddling an integrated circuit mounted on the first surface of the reconstituted die-attach substrate;a molding compound filled within open spaces between the interposer substrate and the first surface of the reconstituted die-attach substrate, wherein singulated surfaces of the molding compound reside along edges of the interposer substrate and the reconstituted die-attach substrate; andexternal electrical connections formed in a grid array on a second surface of the reconstituted die-attach substrate.2. The reconstituted interposer package of claim 1 , wherein one or more of the reconstituted interposer packages are assembled into one of a baseband microprocessor claim 1 , a set-top-box microprocessor claim 1 , a server message block microprocessor claim 1 , or an encryption/security microprocessor.3. The reconstituted semiconductor package of claim 1 , wherein the molding compound covers side walls of the ...

Solid-state storage device

A solid-state storage device includes a housing, a wiring board and a semiconductor package unit. The housing is formed with a heat-dissipating recess thereon. The wiring board is fixed in the housing. One side of the semiconductor package unit is mounted on the wiring board, and the other side of the semiconductor package unit is embedded in the heat-dissipating recess. A top surface and lateral surfaces surrounding the top surface of the semiconductor package unit are all thermally connected to the housing in the heat-dissipating recess.

Semiconductor package and method of manufacturing the same

A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

Electronic component and method of manufacturing the same

An electronic component has a circuit board with a main surface, a chip having a sensor facing the main surface, bump electrodes disposed between the main surface and the chip so as to be placed inside of the edges of the chip in a plan view of the main surface, a dam provided between the main surface and the chip so as to extend at least from the edges of the chip to outer positions of the bump electrodes in a plan view of the main surface, and an under-fill material provided at least in a clearance between the dam and the chip. Between the main surface and the sensor, a space is formed in a region enclosed by the bump electrodes in a plan view of the main surface. The under-fill material is disposed outside of the space in a plan view of the main surface.

3DIC Packages with Heat Dissipation Structures

A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM. 1. A method comprising:bonding a device die onto a package substrate; a first portion overlapped by the die stack; and', 'a second portion extending laterally beyond an edge of the die stack;, 'bonding a die stack onto the device die, wherein the die stack comprises a plurality of dies, and the device die comprisesdispensing a first Thermal Interface Material (TIM) onto a top surface of the die stack;dispensing a second TIM onto the second portion of the device die;adhering a heat dissipating lid to the first TIM; andadhering a heat dissipating ring to the second TIM.2. The method of claim 1 , wherein the heat dissipating lid has a first top surface coplanar with a second top surface of the heat dissipating ring claim 1 , and the method further comprises:dispensing a third TIM onto top surfaces of both the heat dissipating lid and the heat dissipating ring; andattaching a heat sink to the third TIM.3. The method of further comprising dispensing an adhesive onto a top surface of the heat dissipating ring claim 1 , wherein a bottom surface of the heat dissipating lid is adhered to the top surface of the adhesive.4. The method of claim 3 , wherein the adhesive has a thermal conductivity value lower than thermal conductivity values of the first TIM and the second TIM.5. The method of claim 3 , wherein the heat dissipating lid comprises:a top portion having a bottom surface in contact with the first TIM; andprotruding portions ...

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

CHIP MODULE WITH STIFFENING FRAME AND ORTHOGONAL HEAT SPREADER

An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, and a first directional heat spreader. A second directional heat spreader may further be arranged orthogonal to the first directional heat spreader. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes an opening that accepts the IC chip and may be attached to the top surface of the carrier. The IC chip is concentrically arranged within the opening of the stiffening frame. The first directional heat spreader is attached to the stiffening frame and to the IC chip and generally removes heat in a first opposing bivector direction. When included in the IC chip module, the second directional heat spreader is attached to the stiffening frame and to the first directional heat spreader and generally removes heat in a second opposing bivector direction orthogonal to the first opposing bivector direction. 1. A method comprising:attaching a stiffening frame to a carrier, the stiffening frame comprising a central opening to accept a semiconductor chip, a base portion, a first pair of opposing sidewalls, and a second pair of opposing sidewalls;electronically coupling the semiconductor chip to the carrier concentrically arranged within the central opening;thermally contacting a first directional heat spreader to the semiconductor chip, the first directional heat spreader arranged to transfer heat from the semiconductor chip in a first opposing bivector direction towards the first pair of opposing sidewalls; andthermally contacting a second directional heat spreader to the first directional heat spreader, the second directional heat spreader arranged to transfer heat from the first directional heat spreader in a second opposing bivector direction towards the second pair of opposing sidewalls.2. The method of claim 1 , wherein the first directional heat spreader contacts the first pair of opposing sidewalls. ...

SEMICONDUCTOR ASSEMBLY WITH BUILT-IN STIFFENER AND INTEGRATED DUAL ROUTING CIRCUITRIES AND METHOD OF MAKING THE SAME

A semiconductor assembly with built-in stiffener and integrated dual routing circuitries is characterized in that a semiconductor device and a first routing circuitry are positioned within a through opening of a stiffener whereas a second routing circuitry extends to an area outside of the through opening of the stiffener. The mechanical robustness of the stiffener can prevent the assembly from warping. The first routing circuitry can enlarge the pad size and pitch of the semiconductor device, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the first routing circuitry with the stiffener. 1. A semiconductor assembly with built-in stiffener and integrated dual routing circuitries , comprising:a subassembly that includes a semiconductor device, a balance layer and a first routing circuitry having a first surface and an opposite second surface, wherein (i) the semiconductor device is electrically coupled to the first routing circuitry from the first surface of the first routing circuitry, (ii) the first routing circuitry includes at least one conductive trace laterally extending beyond peripheral edges of the semiconductor device, and (iii) the balance layer laterally surrounds the semiconductor device and covers the first surface of the first routing circuitry;a stiffener having a through opening that extends through the stiffener, wherein the subassembly is positioned within the through opening of the stiffener; anda second routing circuitry that is electrically coupled to the first routing circuitry from the second surface of the first routing circuitry and includes at least one conductive trace laterally extending beyond peripheral edges of the first routing circuitry and over a surface of the stiffener.2. The semiconductor assembly of claim 1 , wherein the subassembly further includes a heat spreader that is attached to an inactive surface of the semiconductor device using a thermally conductive ...

PACKAGE ON PACKAGE (PoP) DEVICE COMPRISING THERMAL INTERFACE MATERIAL (TIM) IN CAVITY OF AN ENCAPSULATION LAYER

A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element. 1. A semiconductor package structure , comprising:a first substrate;at least one first semiconductor element attached to the first substrate; anda second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.2. The semiconductor package structure according to claim 1 , wherein the second substrate defines a cavity claim 1 , one end of each of the thermal vias is exposed in the cavity claim 1 , and the first semiconductor element is disposed within the cavity and directly contacts the end of each of the thermal vias exposed in the cavity.3. The semiconductor package structure according to claim 1 , wherein the second substrate further includes a main body disposed between adjacent two of the thermal vias and between adjacent two of the conductive vias claim 1 , and the main body is a monolithic structure.4. The semiconductor package structure according to claim 1 , further comprising a plurality of first electrical connectors disposed between the first substrate and the second substrate and electrically connecting the first substrate and the second substrate.5. The semiconductor package structure according to claim 1 , wherein the first substrate has a first surface and a second surface opposite to the first surface claim 1 , the first semiconductor element is attached to the second surface of the first substrate claim 1 , and the semiconductor package structure further comprises at least one second semiconductor element attached to the first surface of the first substrate.6. The semiconductor package structure ...

INTEGRATED INTERPOSER SOLUTIONS FOR 2D AND 3D IC PACKAGING

An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die. 1. A method for making an integrated circuit (IC) package , the method comprising:providing a first substrate having a back side surface, a top surface and a cavity disposed in the top surface, the cavity having a floor defining a front side surface;forming electroconductive contacts on respective ones of the front and back side surfaces;forming a plurality of electroconductive elements penetrating through the first substrate and interconnecting selected ones of the electroconductive contacts respectively disposed on the front and back side surfaces to each other;disposing one or more first dies within the cavity and electroconductively coupling each first die to corresponding ones of the electroconductive contacts disposed on the front side surface, each first die containing an IC;permanently sealingly attaching a bottom surface of a second substrate to the top surface of the first substrate; andinjecting a dielectric material into the cavity so as to encapsulate each first die.2. The method of claim 1 , further comprising processing a top surface of at least one first die and the top surface of the first ...

Multi-chip package with offset 3d structure

Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

3DIC Packaging with Hot Spot Thermal Management Features

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material. 1. A package comprising:a substrate comprising a conductive layer;a first die stack over the substrate and electrically connected to the conductive layer;a second die stack over the substrate and adjacent the first die stack, wherein the first die stack extends higher than the second die stack;a thermally conductive material over the substrate and contacting an electrically conductive material of conductive layer; anda heat dissipation feature thermally connected to the electrically conductive material through the thermally conductive material, wherein a first bottom surface of the heat dissipation feature over the first die stack is higher than a second bottom surface of the heat dissipation feature over the second die stack, and wherein a portion of the heat dissipation feature extends between the first die stack and the second die stack along a line parallel to a top surface of the substrate.2. The package of claim 1 , wherein the portion of the heat dissipation feature is directly connected to the substrate by an additional thermally conductive material.3. The package of claim 1 , wherein the thermally conductive material comprises a thermal interface material claim 1 , silver paste claim 1 , solder claim 1 , or a combination thereof.4. The package of claim 1 , wherein the electrically conductive material of the conductive layer is part of a signal line claim 1 , a power line claim 1 , or a ground line.5. The package of claim 1 , wherein the electrically conductive material of the conductive layer is a dummy feature.6. The package ...

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

Interposer for a package-on-package structure

A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Semiconductor packages including heat spreaders and methods of manufacturing the same

There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.