СИЛОВОЙ ПОЛУПРОВОДНИКОВЫЙ МОДУЛЬ С БОКОВЫМИ СТЕНКАМИ СЛОИСТОЙ КОНСТРУКЦИИ

Изобретение относится к силовому полупроводниковому модулю. Технический результат - предложение силового полупроводникового модуля, обладающего высокой взрывоустойчивостью и изготавливаемого с особенно оптимальными затратами. Достигается тем, что в силовом полупроводниковом модуле (1), включающем в себя по меньшей мере два электрически соединенных друг с другом силовых полупроводниковых блока (19, 20), содержащих управляемые силовые полупроводники, корпус (2, 3, 13) модуля, в котором расположены силовые полупроводниковые блоки (19, 20), и у которого имеются электрически изолирующие боковые стенки (13), и по меньшей мере одну присоединительную шину (9, 10, 11, 12, 21), которая распространяется сквозь боковые стенки (13) и соединена по меньшей мере с одним из силовых полупроводниковых блоков (19, 20), предлагается построить изолирующие боковые стенки (13) в виде штабеля изолирующих и цельно выполненных частичных элементов (14, 15, 16), при этом частичные элементы (14, 15, 16) прилегают друг ...

СПОСОБ СОЕДИНЕНИЯ, ГЕРМЕТИЧНАЯ КОНСТРУКЦИЯ, ИЗГОТОВЛЕННАЯ ДАННЫМ СПОСОБОМ, И СИСТЕМА ГЕРМЕТИЧНЫХ КОНСТРУКЦИЙ

... 1. Способ соединения с применением взаимной диффузии металлов для формирования, на уровне пластин, герметичных корпусов для устройств на базе микроэлектромеханических систем (МЭМС), включающий следующие этапы:формирование на поверхности как первой пластины, так и второй пластины стопы из первого металла, подверженного окислению на воздухе;формирование на верхней поверхности каждой стопы из первого металла слоя второго металла, температура плавления у которого ниже, чем у первого металла, причем толщину слоя второго металла выбирают достаточной для предотвращения окисления верхней поверхности первого металла;приведение слоя второго металла на первой пластине в контакт со слоем второго металла на второй пластине, чтобы образовать зону соединения, иприложение к первой и второй пластинам давления соединения при температуре зоны соединения, которая ниже температуры плавления второго металла, чтобы инициировать соединение, причем давление соединения выбирают достаточным для деформирования слоев ...

КОРПУС БЕСПОТЕНЦИАЛЬНОГО СИЛОВОГО МОДУЛЯ

Изобретение относится к силовой электронике, в частности к преобразователям с пониженными динамическими потерями в силовых полупроводниковых ключах, полумостовым драйверам, автономным инверторам тока и т.п. В корпусе беспотенциального полумостового силового модуля, содержащем фланец из псевдосплава, к которому припаяна керамическая плата для монтажа функциональных элементов модуля, припаянный ободок для герметизации корпуса, внешние выводы припаяны к контактным площадкам, соединённым с контактными площадками, находящимися во внутренней полости корпуса, через металлизированные переходные отверстия в керамике, на фланце размещено основание из псевдосплава с внешними размерами, соответствующими размерам ободка для герметизации корпуса, в основании выполнены две прорези на противоположных сторонах для выхода из корпуса выводов, причём ширина перемычки между прорезями превышает ширину фланца, в местах прорезей высокотемпературным припоем вакуумно-плотно припаяны платы из алюмооксидной керамики ...

СИЛОВОЙ ПОЛУПРОВОДНИКОВЫЙ МОДУЛЬ С БОКОВЫМИ СТЕНКАМИ СЛОИСТОЙ КОНСТРУКЦИИ

... 1. Силовой полупроводниковый модуль (1), включающий в себя по меньшей мере два электрически соединенных друг с другом силовых полупроводниковых блока (19, 20), содержащих управляемые силовые полупроводники, корпус (2, 3, 13) модуля, в котором расположены силовые полупроводниковые блоки (19, 20), и электрически изолирующие боковые стенки (13), и по меньшей мере одну присоединительную шину (9, 10, 11, 12, 21), которая распространяется сквозь боковые стенки (13) и соединена по меньшей мере с одним из силовых полупроводниковых блоков (19, 20), отличающийся тем, что изолирующие боковые стенки (13) выполнены в виде штабеля изолирующих и цельно выполненных частичных элементов (14, 15, 16), при этом частичные элементы (14) прилегают друг к другу контактными областями.2. Силовой полупроводниковый модуль (1) по п.1, отличающийся тем, что частичные элементы (14, 15, 16) выполнены замкнутыми в окружном направлении.3. Силовой полупроводниковый модуль (1) по п.2, отличающийся тем, что частичные элементы ...

Lead frame moisture barrier for moulded plastic electronic packages.

Eletronic packages that consits of dies sealed within hollow plastic enclosures with eletrically conductive leads penetrating the enclosure walls to access the die circuitry are manufactured by applying a heat-curable adhesive to the leads at only those locations where the surfaces of the leads will interface with the enclosure material, molding the package around the leads, and curing the adhesive during the molding process or during a post-cure. The adhesive is formulated to form a gas-tight seal around the leads and to maintain the seal during the thermal cycling that the components are exposed to during the typical procedures involved in the manufacturing the packages and in making the eletrical connections to other circuitry, as well as the typical enviromental changes that the finished and installed product is exposed to during use. In particular, the adhesive is selected to accomodate differences in the coefficients of thermal expansion between the leads and the enclosure material ...

Lead frame moisture barrier for molded plastic electronic packages

VERSCHLUSSSTOPFEN

STRUCTURAL UNIT AND PROCEDURE FOR THE PRODUCTION OF A STRUCTURAL UNIT

PACKAGING FUER POLARIZED MEMS RELAY AND PROCEDURE FOR THE PACKAGING

TOTALLY ENCLOSED CHIP WITH INTERNAL INDUCTANCE

POWER SEMICONDUCTOR MODULE

METAL LIP SEAL AND WITH SUCH A POETRY EQUIPPED MACHINE

Closure stopper

Closure stopper for a borehole (6) let into a housing (2) for electrical/electronic components, comprising an insulating base member (3) and at least one connecting pin (43, 44) forming an electrically conducting connection (4, 4'), the at least one electrically conducting connection (4, 4') being fixed with its first end (41, 41') insulated in the base member (3), ...

Substrate composite, method and apparatus for bonding substrates

Die Erfindung betrifft ein Verfahren zum Bonden eines ersten Substrats (1) mit einem zweiten Substrat (7) mit folgenden Schritten, insbesondere folgendem Ablauf: - Kontaktierung einer ersten Kontaktfläche (lk) des ersten Substrats (1) mit einer parallel zur ersten Kontaktfläche (lk) ausgerichteten zweiten Kontaktfläche (18k) des zweiten Substrats (7), wodurch eine gemeinsame Kontaktfläche (22) gebildet wird, - Herstellung einer punktuellen, stoffschlüssigen Verbindung zwischen dem ersten Substrat (1) und dem zweiten Substrat (7) außerhalb der gemeinsamen Kontaktfläche (22). Weiterhin betrifft die Erfindung eine korrespondierende Vorrichtung und einen Substratverbund aus einem ersten Substrat (1) und einem zweiten Substrat (7), bei dem eine erste Kontaktfläche (lk) des ersten Substrats (1) mit einer parallel zur ersten Kontaktfläche (lk) ausgerichteten zweiten Kontaktfläche (18k) des zweiten Substrats (7) eine gemeinsame Kontaktfläche (22) bildet, wobei außerhalb der gemeinsamen Kontaktfläche ...

ELECTRICAL CIRCUIT PACKAGING STRUCTURE

PACKAGING MICROELECTROMECHANICAL STRUCTURES

Method and apparatus for providing hermetic electrical feedthrough

HERMETICALLY SEALED MICRO-DEVICE PACKAGE WITH WINDOW

METHOD FOR FORMING HOUSINGS FOR ELECTRONIC COMPONENTS AND ELECTRONIC COMPONENTS THAT ARE HERMETICALLY ENCAPSULATED THEREBY

Hollow package manufacturing method and apparatus

Semiconductor device fabrication method and semiconductor device fabrication device

Lead frames with improved adhesion

Chip scale package

GLASS/CERAMIC SEALING SYSTEM

INTEGRATED CIRCUIT CHIPS MOUNTING AND PACKAGING ASSEMBLY

USE OF DIVERSE MATERIALS IN AIR-CAVITY PACKAGING OF ELECTRONIC DEVICES

Semiconductor circuit devices (dies) are incorporated into moisture- impenetrable electronic packages by forming enclosures around the die in three separate parts--base, sidewalls, and lid. The die is first soldered or otherwise bonded to the base, followed by attachment of the sidewalls to the base, and finally the lid to the sidewalls. For procedures involving a heat- conductive base and a high soldering temperature, the die can be secured to the base at the high soldering temperature, followed by application of the sidewalls to the base at a significantly lower temperature, avoiding potential high-temperature damage to the sidewalls. Plastic sidewalls which would otherwise deteriorate or become distorted upon exposure to the high soldering temperature can thus be used. For electronic packages in general, the use of plastic sidewalls allows the use of combinations of materials for the lid and base that are otherwise incompatible, and reduces or eliminates the incidence of failure due ...

HERMETICALLY SEALED HIGH FREQUENCY FRONT END

The invention relates to a hermetically sealed RF front end (for example a transmitting/receiving module) of a multilayered structure comprising electronic components (3, 4), wherein the multilayered structure contains a number of substrates (1, 2) which are stacked one above the other and carry the components (3, 4), wherein grooves (7) are formed in the substrates (1, 2), and between the substrates (1, 2) there are sealing elements (5, 8), which engage in the grooves (7), and the substrates (1, 2) are soldered to one another.

NICKEL/INDIUM PLATED COVER FOR HERMETICALLY SEALED CONTAINER FOR ELECTRONIC DEVICE

This invention relates to a new and improved hermetically sealed container for semiconductor and other electronic devices, to a novel sealing cover for use in fabricating the above-referenced hermetically sealed container, and to novel processes for manufacturing said container and cover. The specification discloses an improved method of fabricating a hermetically sealed container consisting of a body having a cavity therein for receiving a semiconductor device and a cobalt-nickel-iron alloy sealing cover therefor comprising superimposing upon the sealing cover and in registry with the periphery thereof a preformed ring of heat-fusible material of a thickness which is a minor fraction of that of said cover; engaging said ring with at least one pair of spaced electrodes; passing a pulse of current through the electrodes, the ring, and the cover, thereby producing an effective attachment between said ring and said cover adjacent each of said electrodes; disposing a semiconductor device in ...

INTEGRATED CIRCUIT PACKAGE

An integrated circuit package cover includes a groove with a quadrangular cross-section which contains a selfsupporting sealant material of similar cross section. During assembly, the sealant material is penetrated by the lead-ins and flows around them to achieve an environmental seal for the packaged chip.

SEALING OF INTEGRATED CIRCUIT MODULES

The hermetic seal of the backside of a substrate of an integrated circuit module is provided by a composition containing about 51.4 to about 60.6% by weight of an epoxy polymer; about 39 to about 48% by weight of a hardener and flexibilizing portion; and up to about 0.6% by weight of a coloring agent.

SEAL RING COMPOSITIONS

PACKAGE FOR INTEGRATED CIRCUIT DIE

A circuit package for housing semiconductor or other integrated circuit devices ("die") includes a high-copper flange, one or more high-copper leads and a liquid crystal polymer frame molded to the flange and the leads. The flange includes a dovetail-shaped groove or other frame retention feature that mechanically interlocks with the molded frame. During molding, a portion of the frame forms a key that freezes in or around the frame retention feature. The leads include one or more lead retention features to mechanically interlock with the frame. During molding, a portion of the frame freezes in or adjacent these lead retention features. The frame includes compounds to prevent moisture infiltration and match its coefficient of thermal expansion (CTE) to the CTE of the leads and flange. The frame is formulated to withstand die-attach temperatures. A lid is ultrasonically welded to the frame after a die is attached to the flange.

NICKEL/INDIUM PLATED COVER FOR HERMETICALLY SEALED CONTAINER FOR ELECTRONIC DEVICE

GLASS MATERIAL FOR USE AT HIGH FREQUENCIES

The aim of the invention is to improve the high-frequency characteristics of high-frequency substrates or high-frequency conductor assemblies. To achieve this, the invention provides a glass material for producing insulation layers for high-frequency conductor assemblies. Said material is applied as a layer, in particular with a layer thickness ranging between 0.05 .mu.m and 5 mm, with a tangent of loss angle tan.delta. in at least one frequency range above 1 GHz of less than or equal to 70*10-4.

APPARATUS FOR HEATING AND COOLING AN ELECTRONIC DEVICE

A method and apparatus maintain the operating temperature of an electronic device within an acceptable operating range for a wide range of ambie nt temperatures. The apparatus includes a heat sink and a temperature dependent loading device which brings the heat sink into thermal contact with the electron ic device when the ambient temperature exceeds a threshold level.

HOLLOW PACKAGE MANUFACTURING METHOD AND APPARATUS

A hollow package manufacturing method includes the adhesive spreading step, the adhesive applying step, and the cap adhering step. In the adhesive spreading step, an adhesive is spread on a circular table to a uniform thickness. In the adhesive applying step, an open end face of a cylindrical cap having a bottom is urged against the circular table to apply the adhesive to the cap. In the cap adhering step, the cap applied with the adhesive is adhered to a case. A hollow package manufacturing apparatus is also disclosed.

METAL ELECTRONIC PACKAGE WITH REDUCED SEAL WIDTH

There is provided an electronic package (30) where the package components (12, 14) define a cavity (24). A semiconductor device (16) and a portion (18) of a leadframe (20) occupy part of the cavity (24). Substantially the remainder of the cavity (24) is filled with a compliant polymer (26), such as a silicone gel. Since the cavity (24) is no longer susceptible to gross leak failure, the seal width (RW) of adhesives (22) used to assemble the package (30) may be reduced, thereby increasing the area available for mounting the semiconductor device (16).

HYBRID MICROPACKAGING OF MICRODEVICES

Kristallkontakteinrichtung.

Photoelektrische Zelle.

Procédé de fabrication d'une matière à base de silicium destinée à être utilisée dans la fabrication d'éléments d'appareils électriques.

Redresseur électrique à cristal

Procédé d'établissement d'une liaison entre un conducteur métallique et un élément semi-conducteur

Verfahren zum Anbringen einer Elektrode auf einem halbleitenden Körper

Verfahren zur Oberflächenbehandlung von Halbleiterkörpern

Gehäuse für einen Halbleitergleichrichter

Halbleiteranordnung

Halbleiteranordnung

Halbleiteranordnung und Verfahren zur Herstellung einer solchen

Verfahren zur Herstellung eines lichtempfindlichen Halbleiterelements und darnach hergestellte lichtempfindliche Zelle

Verfahren zur Herstellung einer Halbleiteranordnung, insbesondere eines Transistors, mit einem einkristallinen Grundkörper aus Silizium

Flächengleichrichteranordnung mit einem Halbleiterelement mit p-n-Übergang und Verfahren zur Herstellung einer solchen Anordnung

Gehäuse für einen Halbleitergleichrichter

Transistoranordnung mit Gehäuse

Procédé pour mettre sous boîtier un composant électronique

Halbleiter-Bauelement mit einer Flächenhalbleiteranordnung

Halbleiter-Gleichrichteranordnung mit tablettenförmigen Gleichrichterelementen

Verfahren zur Herstellung einer Halbleiteranordnung mit einem Siliciumkörper und mit mindestens einem pn-Übergang

Hermetisch abgedichtete Halbleiteranordnung und Verfahren zu ihrer Herstellung

Halbleiterbauelement

Dispositif semi-conducteur photosensible et procédé de fabrication dudit dispositif

Verfahren zur Herstellung einer Halbleitervorrichtung mit wenigstens einer aluminiumhaltigen Elektrode

Verfahren zur Herstellung von Silizium-Halbleiterelementen und nach dem Verfahren hergestellter Silizium-Leistungsgleichrichter

Halbleiteranordnung mit vakuumdichter Hülle

Dispositif semi-conducteur fixé sur une embase et enfermé dans un capot

Procédé de fabrication d'un dispositif électrique enfermé dans un boîtier et dispositif sous boîtier obtenu par ce procédé

CERAMIC PACKAGE FOR A HYBRID CIRCUIT.

Ceramic element e.g. lid, for cooperating with part to e.g. form cavity for encapsulation device encapsulating microelectromechanical systems, has metal layer protected by intermetallic layer, which is covered by material part

The element e.g. lid (4), has an element body that is intended for forming a metal layer (15) for metallization, where the element is partially covered by the metallization. The metallization comprises a coating for protection against gold oxidation. The metal layer is protected by an intermetallic layer (19), which is covered by a non-diffused material part (12'), where melting point of material e.g. indium and tin, is lower than 250 degrees Celsius. The metal layer comprises a fixing layer (13) fixing against the body. Independent claims are also included for the following: (1) a method for manufacturing an element (2) an encapsulation device (3) a method for manufacturing an encapsulation device.

Hermetically sealing cap, photograph housing for an electronic component and procedure for the production of a photograph housing for an electronic component.

Es werden eine hermetisch abdichtende Kappe (10), ein Aufnahmegehäuse mit der hermetisch abdichtenden Kappe (10) und ein Verfahren zur Herstellung des Aufnahmegehäuses bereitgestellt. Durch die hermetisch abdichtende Kappe (10) wird eine Verbrauchsmenge an Au in einem Lötmaterial zum Abdichten des Aufnahmegehäuses für eine elektronische Komponente verringert. Die hermetisch abdichtende Kappe (10) wird für das Aufnahmegehäuse für eine elektronische Komponente verwendet, das ein Elektronikkomponenten-Aufnahmeelement zum Aufnehmen einer elektronischen Komponente enthält. Die hermetisch abdichtende Kappe (10) besteht aus einer Basis (1), einer Ni-haltigen Unterschicht (2), die auf der Oberfläche der Basis (1) ausgebildet ist, und einer Hartlöt-Zusatzmetallschicht (6), die auf der Ni-haltigen Unterschicht (2) ausgebildet ist, eine Dicke von 10 µm oder weniger aufweist und aus Au und Sn besteht. Der prozentuale Au-Gehalt in der Hartlöt-Zusatzmetallschicht (6) beträgt 43 Masse-% oder mehr, aber ...

Amorphous alloy bonding

Semiconductor component and method for manufacturing a semiconductor component

Semiconductor device

Encapsulation structure for wafer chip dimension of micro mechanical-electrical system and its making method

The invention relates to a wafer-level chip size encapsulation structure of micro electromechanical system and the manufacturing method. The outside of the micro electromechanical system chip is provided with a welding pad in a dense array. The front face of the chip is provided with a protection cover. An empty cavity wall is provided between the chip and the protection cover. The material of the empty cavity is polymer photoresist leakproof material which has the possibility of being pressed. The protection cover is connected with the front cover of the chip through the empty cavity wall. The micro electromechanical component is positioned in an empty cavity formed by the empty cavity wall and the chip of the micro electromechanical system. A groove and the back of the chip of the microelectromechanical system are covered by an insulating layer. An outer lead wire is deposited on the exposing surface of the horizontal side of the welding pad and the back surface of the insulating layer ...

Low profile electronic package and manufacturing method thereof

Method for forming a wafer seal ring

Ceramic package, the electronic device device and manufacturing method thereof

For the protection of the outer cover of the flat panel computer

A cooling arrangement for an integrated circuit

Chip-scale package

A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.

Process for the setting under case of devices with asymmetrical conductibility

PROCESS Of ASSEMBLY Of a CASE Of a SEMICONDUCTOR COMPONENT

HERMETIC CERAMIC PACKAGE HAVING OUTPUTS ARE SEALED USING A GLASS STRUCTURES AND INTEGRATED CIRCUITS.

CASE HAS DISSIPATION THERMAL RAISED IN PARTICULAR FOR MICRO-ELECTRONICS

Tight sealed metal enclosure

Enclosure for a rectifier with semiconductor

Capsule pour semi-conducteur.

CAPSULE POUR DISPOSITIF SEMI-CONDUCTEUR, DEPOURVUE DE COBALT ET SCELLEE HERMETIQUEMENT. DES CAPSULES, PAR EXEMPLE DU TYPE TO- 5 ET TO- 18 COMPORTANT DES SUPPORTS 11 EN ALLIAGE 42 (FE-NI) SONT SCELLEES EN COMBINAISON AVEC DES CONDUCTEURS 13 EN ALLIAGE F-15, EN UTILISANT DES ELEMENTS PREFORMES EN VERRE CORNING 7052.

Devices with semiconductors and manufacturing methods

ELECTRONIC CIRCUIT PACKAGE COVER

A METHOD FOR RECOVERING THE MICROELECTRONICS PACKAGE

A method of making a seal bead and mechanical properties between a substrate and a [...] by beads on the substrate

L'invention concerne un procédé de réalisation d'un cordon (13) d'encapsulation assurant l'étanchéité et la tenue mécanique d'une puce (1) hybridée par billes sur un substrat (5). Ce procédé consiste, parallèlement à la réalisation des billes (9) d'hybridation sur la face (1a) inférieure de la puce ou du substrat par un premier matériau fusible: (a) à déposer un cordon (13) d'un deuxième matériau fusible sur le substrat ou sur la face inférieure du composant électronique, (b) à placer la face inférieure de la puce sur le substrat de façon à réaliser les connexions entre ladite puce et ledit substrat au moyen du premier matériau fusible, et (c) à chauffer l'ensemble ainsi formé à une température au moins égale à la température de fusion la plus élevée desdits premier et second matériaux fusibles, afin de réaliser le cordon d'étanchéité au moyen de second matériau et les billes d'hybridation au moyen du premier matériau.

A DEVICE FOR DETECTING ELECTROMAGNETIC RADIATION AND METHOD FOR ITS MANUFACTURE

METHOD FOR PACKAGING A MICROELECTRONIC DEVICE COMPRISING AN INJECTION OF NOBLE GAS THROUGH A MATERIAL PERMEABLE TO THE NOBLE GAS

Using method of preparation of the devices of the layers of transition between semiconductors from the types p and N

PROCEEDED Of HERMETIC ENCAPSULATION OF ELECTRONICS COMPONENTS High frequency HAS VERY, COMPRISING the INSTALLATION OF METAL CROSSINGS, DEVICE CARRIED out BY SUCH a PROCESS

Case e.g. ball grid array case, assembling method for interconnecting e.g. semiconductor component and external circuit, involves depositing anisotropic conductive film on surface of contact between upper and lower parts of case

L'invention concerne un procédé d'assemblage de boîtiers comportant des composants électroniques. Le procédé comporte au moins : - une étape de dépôt d'un composant conducteur anisotropique sur la surface de contact d'une des deux parties du boîtier; - une étape d'assemblage de la partie inférieure et supérieure du boîtier; - une étape de modification de la structure physico-chimique du composant conducteur anisotropique qui assure alors : o l'interconnexion électrique entre les zones d'interconnexions de la partie supérieure et inférieure du boîtier, o le lien mécanique entre les surfaces de contact de la partie supérieure et inférieure du boîtier, o l'étanchéité de la structure ainsi formée. L'invention a encore pour objet un boîtier comportant des composants électroniques. En particulier, l'invention s'applique à l'assemblage de boîtiers organiques comportant des circuits hyperfréquences.

Housing for semiconductor device - has borosilicate glass seal with specified coefft. of thermal expansion for alloy leads to eyelet carrier

CASE FOR ELECTRIC AND ELECTRONIC COMPONENTS

STRUCTURE COMPRISING a GETTER LAYER AND an UNDERLAYER Of ADJUSTMENT AND MANUFACTORING PROCESS.

La structure comporte au moins un dispositif, par exemple une puce microélectronique, et au moins un getter (6) disposés dans une cavité délimitée par deux substrats (2) et un joint de scellement périphérique fermé. Le getter (6) comporte au moins une couche getter (7), de préférence métallique, et une sous-couche d'ajustement (8), en métal pur, située entre la couche getter (7) et le substrat (2), sur lequel il est formé. La sous-couche d'ajustement (8) est apte à moduler la température d'activation de la couche getter (7).

Inductive getter activation for high vacuum packaging

An approach to activating a getter within a sealed vacuum cavity is disclosed. The approach uses inductive coupling from an external coil to a magnetically permeable material deposited in the vacuum cavity. The getter material is formed over this magnetically permeable material, and heated specifically thereby, leaving the rest of the device cavity and microdevice relatively cool. Using this inductive coupling technique, the getter material can be activated after encapsulation, and delicate structures and low temperature wafer bonding mechanisms may be used.

Substrate bonding with metal germanium silicon material

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Corner structure for ic die

One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

Unitary housing for electronic device

An electronic device having a unitary housing is disclosed. The device can include a first housing component having an open cavity, an internal electronic part disposed within the cavity, a second housing component disposed across the cavity, and a support feature disposed within the cavity and arranged to support the second housing component. The first housing component can be formed from metal, while the second housing component can be formed from a plurality of laminated foil metal layers. The second housing component can be attached to the first housing component via one or more ultrasonic welds, such that a fully enclosed housing is created. The fully enclosed housing can be hermetically sealed, and the outside surfaces thereof can be machined or otherwise finished after the ultrasonic welding.

Semiconductor laser module

A semiconductor laser module includes: a semiconductor laser element which emits light; a package base having a through hole; a lead pin which passes through the through hole and supplies the current to the semiconductor laser element; a glass material which seals the through hole through which the lead pin passes; and a cap which has a window from which light emitted by the semiconductor laser element is taken out and has the semiconductor laser element in the inside thereof, the cap being joined in air sealing relation to the package base. The lead pin is an iron-nickel alloys in which the coefficient of linear expansion is not higher than a predetermined ratio in difference with the glass material, the saturation magneto-striction constant is not higher than a predetermined value, and volume resistivity is not higher than a predetermined rate.

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Chip package and manufacturing method thereof

An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

Sealed electronic housing and method for the sealed assembly of such a housing

Method for the sealed assembly of an electronic housing containing one or more electronic components, the method including: assembling the housing by bringing a support, to which the electronic components are fixed, in contact with a cover by means of a mixture including a paste and nanoparticles in suspension in said paste, the size of the nanoparticles ranging from 10 to 30 nm; and closing the housing in a sealed manner by heating the housing to a temperature T of between 150° C. and 180° C. making it possible to sinter the metal nanoparticles, while subjecting the housing to a pressure greater than 2.5×10 5 Pa.

Hermetically sealed wafer packages

Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

System and Method for Wafer Level Packaging

In an embodiment, a semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first cavity disposed through it, and conductive material covers at least the bottom portion of the first cavity. An integrated circuit is disposed on the top surface of the conductive material. The device further includes a cap disposed on the top surface of the substrate, such that a cavity disposed on a surface of the cap overlies the first cavity in the substrate.

Glass as a substrate material and a final package for mems and ic devices

This disclosure provides systems, methods and apparatus for glass packaging of integrated circuit (IC) and electromechanical systems (EMS) devices. In one aspect, a glass package may include a glass substrate, a cover glass and one or more devices encapsulated between the glass substrate and the cover glass. The cover glass may be bonded to the glass substrate with an adhesive such as an epoxy, or a metal bond ring. The glass package also may include one or more signal transmission pathways between the one or more devices and the package exterior. In some implementations, a glass package including an EMS and/or IC device is configured to be directly attached to a printed circuit board (PCB) or other integration substrate by surface mount technology.

3d integrated electronic device structure including increased thermal dissipation capabilities

A microelectronic device structure including increased thermal dissipation capabilities. The structure including a three-dimensional (3D) integrated chip assembly that is flip chip bonded to a substrate. The chip assembly including a device substrate including an active device disposed thereon. A cap layer is phsyically bonded to the device substrate to at least partially define a hermetic seal about the active device. The microelectronic device structure provides a plurality of heat dissipation paths therethrough to dissipate heat generated therein.

Miniaturized Electrical Component Comprising an MEMS and an ASIC and Production Method

The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by means of vias through the MEMS chip or the ASIC chip.

PHYSICAL QUANTITY SENSOR AND METHOD OF MAKING THE SAME

A first sealing layer having a frame-like shape and a first contact layer are formed on a back surface of a frame portion of a sensor substrate. The first contact layer is separated from the first sealing layer, extends through a functional member and an insulation layer, and is electrically connected to the functional member and a first base member. A second sealing layer and a second contact layer are formed on a surface of a wiring substrate. The second sealing layer faces the first sealing layer. The second contact layer is separated from the second sealing layer, extends through the insulation layer, and is electrically connected to the second base member. The sealing layers are eutectically bonded to each other. The contact layers are electrically connected to each other, and thereby the first and second base members and the frame portion have the same potential. 1. A physical quantity sensor comprising:an electroconductive first base member;an electroconductive second base member; a movable portion disposed between the first base member and the second base member; and', 'a frame portion surrounding the movable portion;, 'an electroconductive functional member includinga detection portion configured to detect displacement of the movable portion;a first insulation layer bonding the frame portion and the first base member to each other; a first sealing layer formed on the facing surface of the frame portion and having a frame-like shape, and', 'a first contact layer separated from the first sealing layer, extending through the functional member and the first insulation layer, and electrically connected to the frame portion and the first base member;, 'a first metal layer formed on a facing surface of the functional member facing the second base member, the first metal layer including'}a second insulation layer formed on a facing surface of the second base member facing the functional member; and a second sealing layer formed at a position at which the second ...

Device housing package and electronic apparatus employing the same

A device housing package includes a base body ( 1 ) including, at its upper surface, a placement portion ( 1 a ) of a semiconductor device ( 9 ); a frame body ( 2 ) disposed on the base body ( 1 ) surrounding the placement portion ( 1 a ), including a notch ( 2 b ) formed by cutting a side wall thereof; an input-output terminal ( 3 ) attached to the notch ( 2 b ), including a wiring conductor layer ( 3 a ) electrically connected to the semiconductor device ( 9 ); and a sealing ring ( 5 ) disposed on an upper portion of the frame body ( 2 ). Moreover, side walls of the frame body ( 2 ) have, when seen in a plan view, an outer corner ( 2 c ) of adjacent side walls having a curved surface, the outer corner ( 2 c ) lying within a region overlapping the sealing ring ( 5 ) as seen in a plan view.

Package for a Neural Stimulation Device

An implantable device, including a first electrically non-conductive substrate; a plurality of electrically conductive vias through the first electrically non-conductive substrate; a flip-chip multiplexer circuit attached to the electrically non-conductive substrate using conductive bumps and electrically connected to at least a subset of the plurality of electrically conductive vias; a flip-chip driver circuit attached to the flip-chip multiplexer circuit using conductive bumps; a second electrically non-conductive substrate attached to the flip-chip driver circuit using conductive bumps; discrete passives attached to the second electrically non-conductive substrate; and a cover bonded to the first electrically non-conductive substrate, the cover, the first electrically non-conductive substrate and the electrically conductive vias forming a hermetic package.

Method for the production of a substrate comprising embedded layers of getter material

A method for producing a substrate with buried layers of getter material, including: making a first stack including one layer of a first getter material, arranged on a first support; making a second stack including one layer of a second getter material, arranged on a second support; and bringing the first stack into contact with the second stack and performing thermocompression, the layers of the first and of the second getter material being arranged between the first and the second support, at a temperature greater than or equal to a lowest temperature among thermal activation temperatures of the first and of the second getter material, to bond the layers of the first and second getter materials together.

Electronic component element housing package

An electronic component element housing package is produced by firing a ceramic substrate for housing an electronic component element and a metal layer for bonding to the ceramic substrate to form an electrical path, simultaneously in a reducing atmosphere. The ceramic substrate comprises alumina (Al 2 O 3 ), a partially stabilized zirconia by forming solid solution with yttria (Y 2 O 3 ) and a sintering agent. The sintering agent comprises magnesia (MgO), and at least 1 type selected from silica (SiO 2 ), calcia (CaO), or manganese oxides (MnO, MnO 2 , Mn 2 O 3 , Mn 3 O 4 ).

PACKAGE-ON-PACKAGE ELECTRONIC DEVICES INCLUDING SEALING LAYERS AND RELATED METHODS OF FORMING THE SAME

A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer. 1. A package-on-package (POP) electronic device comprising:first and second packaging substrates;a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates; andfirst and second sealing layers between the first and second packaging substrates.2. The POP electronic device of wherein the first and second sealing layers comprise respective first and second epoxy sealing layers.3. The POP electronic device of wherein the second epoxy sealing layer includes a solder flux agent claim 2 , and wherein the first epoxy sealing layer has a lower concentration of the solder flux agent than the second epoxy sealing layer.4. The POP electronic device of wherein the first sealing layer comprises a mold layer on the first packaging substrate having a via therethrough claim 1 , wherein the solder interconnection extends through the via claim 1 , and wherein portions of the second sealing layer are in the via between the mold layer and the solder interconnection.56-. (canceled)7. The POP electronic device of wherein sidewalls of the via through the mold layer have a surface roughness that is greater than a surface roughness of a surface of the mold layer that is spaced apart from the first packaging substrate.8. The POP electronic device of wherein the first and second sealing layers are spaced apart between the first and second packaging ...

Optical coupling device, opticalsystem and methods of assembly

An optical coupling device comprises: a Z-reference part co-operating with a Z-reference of a first optical device, to define the location of a first optical interface of the coupling device along a direction (Z), fixation parts ( 17, 19 ), extending at different heights along this direction, adapted to be glued to the first optical device.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device has an insulation substrate formed with a conductive pattern; an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate; a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed; an opening provided on a side surface of the case; a nut glove inserted from the opening so as to be below the independent terminal, and fix the independent terminal; and a first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively. The rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening. 1. A semiconductor device , comprising:an insulation substrate formed with a conductive pattern;an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate;a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed;an opening provided on a side surface of the case;a nut glove, being inserted from the opening so as to be below the independent terminal, to fix the independent terminal; anda first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively,wherein the rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening.2. The semiconductor device according to claim 1 , wherein the sidewall surface of the opening is formed with a step which is wider on an insulation substrate side claim 1 , the stepped surface is formed with a second projection part claim 1 , and a rear end of the nut glove is pressure contacting with the second projection part.3. The semiconductor device according to claim 1 , wherein the nut glove is ...

GLASS MEMBER PROVIDED WITH SEALING MATERIAL LAYER ELECTRONIC DEVICE USING IT AND PROCESS FOR PRODUCING THE ELECTRONIC DEVICE

A glass substrate has a surface provided with a sealing region. On the sealing region of the glass substrate , a sealing material layer having a thickness of less than 7 μm is formed. The sealing material layer is made of a fired layer of a glass material for sealing which contains a sealing glass and an inorganic filler containing a laser absorbent, wherein the content of the inorganic filler is from 2 to 44 vol %. The surface area of the inorganic filler in the glass material for sealing is within a range of more than 6 m/cmand less than 14 m/cm. The difference between the thermal expansion coefficient αof the sealing material layer and the thermal expansion coefficient αof the glass substrate is within a range of from 15 to 70(×10/° C.). 1. A glass member provided with a sealing material layer , which comprises a glass substrate having a surface having a sealing region; and , formed on the sealing region of the glass substrate , a sealing material layer having a thickness of less than 7 μm and made of a material obtained by firing a glass material for sealing that contains a sealing glass and an inorganic filler containing a laser absorbent;{'sup': 2', '3', '2', '3, 'wherein the glass material for sealing contains the inorganic filler in an amount within a range of from 2 to 44 vol % based on the total amount of the sealing glass and the inorganic filler, and the surface area of the inorganic filler in the glass material for sealing is within a range of more than 6 m/cmand less than 14 m/cm; and'}{'sub': 11', '2, 'sup': '−7', 'wherein the difference between the thermal expansion coefficient αof the material of the sealing material layer and the thermal expansion coefficient αof the glass substrate is within a range of from 15 to 70(×10/° C.).'}2. The glass member provided with a sealing material layer according to claim 1 , wherein the glass material for sealing contains the laser absorbent in an amount within the range of from 2 to 40 vol % based on the total ...

Cross-linked polymer particle for epoxy resin, epoxy resin composition, and epoxy cured material

The invention discloses a cross-linked polymer particle for an epoxy resin, an epoxy resin composition containing the cross-linked polymer particle, the epoxy resin and a curing agent, and an epoxy cured material having qualities of colorless transparency and crack resistance as a result of curing the resin composition. The cross-linked polymer particle for the epoxy resin contains a (meth)acrylate monomer unit and a crosslinking monomer unit, wherein a volume average primary particle diameter is 0.5 to 10 μm, and a glass transition temperature of the monomer components excluding the crosslinking monomer is 30° C. or more by FOX formula calculation, and the refractivity at 23° C. is 1.490 to 1.510.

Electrical module for being received by automatic placement machines by means of generating a vacuum

The invention relates to an electrical module ( 100 ) for being received by automatic placement machines by means of generating a vacuum, comprising a carrier substrate ( 10 ), at least one component ( 20, 21 ) disposed on the carrier substrate ( 10 ), and a cover element ( 30 ) disposed above the at least one component ( 20, 21 ). A fixing component ( 40 ) by which the cover element ( 30 ) is attached to the at least one component ( 21 ) is disposed between the cover element ( 30 ) and the at least one component ( 21 ). The cover element can be implemented as a dimensionally stable, flat film by means of which it is possible to suction the module by means of vacuum for a placement method, and to place said module at a position on a circuit board.

Method of manufacturing light emitting device

A light emitting device is manufactured in which a cap having a frame portion is bonded to a package having a light emitting element mounted in a recess of the package to cover an opening of the recess. A method for manufacturing the light emitting device includes: partially disposing a metal bonding agent, having greater wettability to the frame portion than to the package, to one of the package and the frame portion; and bonding the package and the frame portion by extending the metal bonding agent along the frame portion so that ends of the metal bonding agent are joined to each other while defining a space at a joining portion where the ends of the metal bonding agent are joined.

WAFER LEVEL PACKAGE, CHIP SIZE PACKAGE DEVICE AND METHOD OF MANUFACTURING WAFER LEVEL PACKAGE

A wafer level package has a first wafer having a plurality of chips mounted or formed thereon in a plane, and a second wafer that is opposed to the first wafer. The first wafer and the second wafer are joined while a seal frame that seals a periphery of each chip is interposed therebetween. A gap is formed between the seal frames of the chips adjacent to each other. A partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other. 1. A wafer level package comprising:a first wafer comprising a plurality of chips mounted or formed thereon in a plane; anda second wafer that is opposed to the first wafer,wherein the first wafer and the second wafer are joined while a seal frame that seals a periphery of each chip is interposed therebetween,wherein a gap is formed between the seal frames of the chips adjacent to each other, andwherein a partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other.2. The wafer level package according to claim 1 ,wherein the plurality of chips are arrayed while mounted on or formed in the plane of the first wafer, andwherein the partial connect part is provided in opposed-side center portions of the seal frames opposed to each other.3. The wafer level package according to claim 2 , wherein a width of the partial connect part is equal to a width of the seal frame.4. The wafer level package according to claim 1 , wherein the width of the partial connect part is greater than or equal to 1 μm.5. The wafer level package according to claim 1 , wherein the partial connect part is provided in the gap only of the seal frame in each chip mounted on or formed in an outer circumferential portion of the first wafer in the chips mounted on or formed in the plane of the first wafer.6. The wafer level package according to claim 1 , wherein the partial ...

DOUBLE SEAL RING

A double seal ring for an integrated circuit, the double seal ring includes a first seal ring surrounding the integrated circuit and a second seal ring spaced from the first seal ring. The double seal ring further includes two connectors connecting the first seal ring and the second seal ring, wherein the first seal ring, the second seal ring, and the two connectors form a closed loop. A method of forming a double seal ring for an integrated circuit includes forming a first seal ring surrounding the integrated circuit and forming a second seal ring spaced from the first seal ring. The method further includes forming two connectors connecting the first seal ring and the second seal ring, wherein the first seal ring, the second seal ring, and the two connectors form a closed loop. 1. A double seal ring for an integrated circuit , comprising:a first seal ring surrounding the integrated circuit;a second seal ring spaced from the first seal ring; andtwo connectors connecting the first seal ring and the second seal ring, wherein the first seal ring, the second seal ring, and the two connectors form a closed loop.2. The double seal ring of claim 1 , wherein at least one connector of the two connectors extends perpendicular to at least one of the first seal ring or the second seal ring.3. The double seal ring of claim 1 , wherein each of the first seal ring and the second seal ring comprises a plurality of metal layers and a plurality of via layers.4. The double seal ring of claim 3 , wherein each metal layer of the plurality of metal layers comprises at least one of aluminum claim 3 , copper claim 3 , tin claim 3 , nickel claim 3 , gold or silver.5. The double seal ring of claim 3 , wherein each via layer of the plurality of via layers comprises at least one of copper claim 3 , copper alloy claim 3 , tungsten claim 3 , gold or aluminum.6. The double seal ring of claim 1 , wherein at least one of the first seal ring or the second seal ring is connected to a ground voltage.7 ...

Cased electrical component

The invention relates to a cased electrical component comprising a carrier substrate ( 10 ), a spring device ( 20 ), which is arranged on the carrier substrate ( 10 ), a chip ( 30 ), which on a first side ( 31 ) of the chip is coupled to the spring device ( 20 ), and a cover element ( 100 ), which is arranged on the carrier substrate ( 10 ). The cover element ( 100 ) is arranged over the chip ( 20 ) such that the cover element ( 100 ) is in contact with the chip ( 30 ) at least on a second side ( 32 ) of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings.

ENCAPSULATED ARRAYS OF ELECTRONIC SWITCHING DEVICES

An electronic switching device array encapsulated in an encapsulating structure; wherein said array is exposed to one or more gas pockets between said array and said encapsulating structure. 1. Apparatus comprising: an electronic switching device array encapsulated in an encapsulating structure; wherein said array is exposed to one or more gas pockets between said array and said encapsulating structure.2. Apparatus according to claim 1 , wherein said array is exposed to said one or more gas pockets via a substrate supporting the array.3. Apparatus according to claim 1 , wherein said encapsulating structure includes a support structure and a gasket sandwiched between a lower surface of at least a periphery portion of the plastic substrate and at least a periphery portion of an upper surface of the support structure claim 1 , and said one or more gas pockets are defined by said gasket claim 1 , a central portion of the substrate and a central portion of the support structure.4. Apparatus according to claim 3 , wherein one or more of said support structure and gasket define one or more inlets to said one or more gas pockets exhibiting a higher transmission for oxygen gas than for moisture.5. Apparatus according to claim 4 , wherein at least one of said one or more inlets is defined at one or more interfaces between the gasket and the support structure and/or between the gasket and the substrate.6. Apparatus according to claim 3 , wherein said gasket comprises a spacer and layers of adhesive for adhering the spacer to a surface of the plastic substrate and a surface of the support structure.7. Apparatus according to claim 3 , wherein said support structure comprises a metal support structure.8. Apparatus according to claim 1 , comprising: a display module mounted above the array and operable via the array claim 1 , which display module incorporates harmful species capable of diffusion to the array.9. Apparatus according to claim 8 , wherein the harmful species comprise ...

Leadframes, air-cavity packages, and electronic devices with offset vent holes, and methods of their manufacture

A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device includes: a plurality of semiconductor chips to be mutually bonded via a bonding resin; a sealing resin to seal the plurality of semiconductor chips; and an anchor to be disposed in a first semiconductor chip included by the plurality of semiconductor chips and to seize the bonding resin. 1. A semiconductor device comprising:a plurality of semiconductor chips to be mutually bonded via a bonding resin;a sealing resin to seal the plurality of semiconductor chips; andan anchor to be disposed in a first semiconductor chip included by the plurality of semiconductor chips and to seize the bonding resin.2. The semiconductor device according to claim 1 , wherein the anchor includes a dummy wire bonded to between a substrate mounted with the plurality of semiconductor chips and the first semiconductor chip.3. The semiconductor device according to claim 1 , wherein the anchor includes a projection provided on the first semiconductor chip.4. The semiconductor device according to claim 1 , wherein the anchor is disposed at such an edge of the first semiconductor chip as to enable an edge of the bonding resin with an interface being formed between the bonding resin and the sealing resin to be seized outside an area formed with an electronic circuit on the surface of the first semiconductor chip.5. The semiconductor device according to claim 1 , wherein the anchor is disposed at a portion claim 1 , of the first semiconductor chip claim 1 , to which a wire for electrically connecting the substrate mounted with the plurality of semiconductor chips to the first semiconductor chip is not bonded.6. A manufacturing method of a semiconductor device claim 1 , comprising:a step of bonding a plurality of semiconductor chips mutually via a bonding resin;a step of sealing the plurality of semiconductor chips by a sealing resin; anda step of disposing an anchor to seize the bonding resin in a first semiconductor chip included by the plurality of semiconductor chips.7. ...

Method for forming semiconductor die and semiconductor device thereof

A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

Semiconductor device package and semiconductor device

A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.

Repackaged integrated circuit assembly method

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die. 1. A method , comprising:extracting a die from an original packaged integrated circuit, wherein the extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die;modifying the extracted die, comprising removing the one or more ball bonds on the one or more die pads; 'adding a sequence of metallic layers to bare die pads of the modified extracted die;', 'reconditioning the modified extracted die, comprisingplacing the reconditioned die into a cavity of a hermetic package base;bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base; andsealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit.2. The method as recited in claim 1 , wherein bare die pads of the modified extracted die comprises all metallic and chemical residue claim 1 , all ball bonds claim 1 , and all bond wires removed from all die ...

CHIP ON PRINTED CIRCUIT UNIT AND DISPLAY APPARATUS COMPRISING THE SAME

Disclosed is a printed circuit unit that includes a flexible member which has an upper surface and a lower surface and includes a first end and a second end. An output pad is disposed at the first end and is implemented to be connected to a bent display panel. A connecting unit is disposed at the second end and is implemented to be connected to a system board, and a drive chip is located between the output pad and the connecting unit. 1. A display device , comprising:a printed circuit unit having at least two electrode layers, a contact pad and a connector;a system board connected to the connector;a display panel connected to the contact pad, the display panel capable of being bent; anda driving unit driving the display panel, andwherein the driving unit and the connector are integrally formed and directly mounted on the printed circuit unit.2. The display device according to claim 1 , wherein the driving unit and the connector are disposed on the same surface of the printed circuit unit.3. The display device according to claim 2 , wherein the same surface of the printed circuit unit faces a rear surface of the display panel.4. The display device according to claim 3 , wherein the driving unit and the connector are located between the printed circuit unit and the display panel to reduce a thickness of the display device.5. The display device according to claim 1 , wherein the driving unit and the connector are located on different surfaces of the printed circuit unit.6. The display device according to claim 1 , wherein the driving unit and the contact pad are disposed on the same surface of the printed circuit unit.7. The display device according to claim 6 , wherein the connector is located on the same surface where the driving unit is disposed.8. The display device according to claim 6 , wherein the connector is disposed on a surface opposite to the surface where the driving unit and the contact pad are located.9. The display device according to claim 1 , wherein ...

LID STRUCTURE AND SEMICONDUCTOR DEVICE PACKAGE INCLUDING THE SAME

The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer. 1. A semiconductor device package , comprising:a carrier;a lid disposed on the carrier and comprising a constraint structure;a conductive adhesive layer electrically connected to the lid and the carrier;a non-conductive adhesive layer between the carrier and the lid; andwherein the constraint structure is configured to prevent the conductive adhesive layer or the non-conductive adhesive layer from bleeding or extending.2. The semiconductor device package of claim 1 , wherein the conductive adhesive layer is in contact with the non-conductive adhesive layer.3. The semiconductor device package of claim 1 , wherein the lid is used for detecting variation of electricity.4. The semiconductor device package of claim 1 , wherein a portion of the conductive adhesive layer and a portion of the non-conductive adhesive layer are disposed in the constraint structure.5. The semiconductor device package of claim 1 , wherein a portion of the conductive adhesive layer is disposed in the constraint structure.6. The semiconductor device package of claim 1 , wherein a portion of the non-conductive adhesive layer is disposed in the constraint structure.7. The semiconductor device package of claim 1 , wherein the non-conductive adhesive layer surrounds the conductive adhesive layer.8. The semiconductor device package of claim 1 , wherein the lid comprises a ...

Semiconductor Package, and a Method for Forming a Semiconductor Package

A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.

Structure and Formation Method for Chip Package

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

WAFER LEVEL PACKAGE SOLDER BARRIER USED AS VACUUM GETTER

An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer. 1. A method of fabricating an electronic device comprising:providing a first substrate having at least one cavity and a surface surrounding the at least one cavity;depositing at least one layer of barrier material on the surface of the first substrate;depositing a solder barrier layer of titanium material on a first portion of the at least one layer of barrier material;forming a first seal structure on a second portion of the at least one layer of barrier material to form a ring around a perimeter of the at least one cavity, wherein the solder barrier layer of titanium material does not extend into the first seal structure;activating the solder barrier layer of titanium material in a vacuum environment to function as a getter;providing a second substrate, the second substrate comprising at least one device attached thereto and a second seal structure, the second seal structure forming a ring around a perimeter of the at least one device;aligning the first seal structure to the second seal structure, such that the at least one cavity of the first substrate is positioned over the at least one device; andbonding the first substrate to the second substrate using solder.2. The method of claim 1 , wherein activating comprises heating the solder barrier layer of titanium material to a temperature in a range of about 200° C. to ...

ELECTRONIC DEVICE

An electronic device includes an electronic element, and a wire bonded to the electronic element. The electronic element includes a bonding pad to which the wire is bonded. The main component of the bonding pad is Al. A metal is mixed in the wire, and the mixed metal is one of Pt, Pd and Au. 1. An electronic device comprising:an electronic element; anda wire bonded to the electronic element,wherein the electronic element includes a bonding pad to which the wire is bonded, a main component of the bonding pad is Al, a mixed metal is mixed in the wire, and the mixed metal is one of Pt, Pd and Au.2. The electronic device according to claim 1 , wherein a main component of the wire is Cu or Ag.3. The electronic device according to claim 1 , wherein a main component of the wire is Cu.4. The electronic device according to claim 1 , wherein a concentration of the mixed metal in the wire is 0.5 to 5 wt %.5. The electronic device according to claim 3 , wherein the bonding pad includes a metal thin film layer claim 3 , and the metal thin film layer is made of CuAl.6. The electronic device according to claim 5 , wherein the metal thin film layer contacts the wire.7. The electronic device according to claim 6 , wherein the metal thin film layer has a thickness of 5 to 20 nm.8. The electronic device according to claim 1 , wherein the wire includes a bonding portion bonded to the electronic element claim 1 , an outer surface of the bonding portion has a bottom surface claim 1 , a lateral surface claim 1 , and a pressed surface claim 1 ,the bottom surface contacts the bonding pad,the lateral surface connects the pressed surface and the bottom surface,the pressed surface has a ring-shaped bent part and is located further inward than the lateral surface as seen in a thickness direction of the bonding pad,the lateral surface has a first curved surface part, and the first curved surface part has a curved shape that, starting from a boundary between the bottom surface and the lateral ...

A SEMICONDUCTOR MODULE

A semiconductor module includes a baseplate, a cover element attached to the baseplate so that detaching the cover element from the baseplate requires material deformations, and a semiconductor element in a room defined by the baseplate and the cover element. The semiconductor element is in a heat conductive relation with the baseplate and an outer surface of the baseplate is provided with laser machined grooves suitable for conducting heat transfer fluid. The laser machining makes it possible to make the grooves after the semiconductor module has been assembled. Therefore, regular commercially available semiconductor modules can be modified, with the laser machining, to semiconductor modules as disclosed. 110-. (canceled)11. A semiconductor module comprising:a baseplate,a cover element attached to the baseplate so that detaching the cover element from the base plate requires material deformations, andat least one semiconductor element in a room limited by the baseplate and the cover element, the semiconductor element being in a heat conductive relation with the baseplate,wherein an outer surface of the baseplate facing away from the semiconductor element is provided with laser machined grooves suitable for conducting heat transfer fluid.12. A semiconductor module according to claim 11 , wherein grooves have a rounded bottom profile.13. A semiconductor module according to claim 11 , wherein widths of the grooves are on a range from 25 μm to 2000 μm and depths of the grooves are on a range from 25 μm to 2000 μm.14. A semiconductor module according to claim 11 , wherein the grooves are branching so that a sum of gross-sectional areas of the grooves increases in each branching.15. A semiconductor module according to claim 11 , wherein an area provided with the grooves on the outer surface of the baseplate has substantially a rectangular shape and the grooves are substantially parallel with longer sides of the rectangular area.16. A semiconductor module according to ...

Thermal transfer structures for semiconductor die assemblies

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.

MICROELECTRONIC PACKAGE WITH UNDERFILLED SEALANT

Embodiments may relate to a microelectronic package comprising an integrated heat spreader (IHS) coupled with a package substrate. A sealant may be positioned between, and physically coupled to, the IHS and the package substrate. The sealant may at least partially extend from a footprint of the IHS. Other embodiments may be described or claimed. 1. A microelectronic package comprising:a package substrate;an integrated heat spreader (IHS) coupled with the package substrate; anda sealant positioned between, and physically coupled to, the IHS and the package substrate, wherein the sealant at least partially extends from a footprint of the IHS.2. The microelectronic package of claim 1 , wherein the microelectronic package further includes a die positioned between the package substrate and the IHS.3. The microelectronic package of claim 2 , wherein the microelectronic package further includes a solder thermal interface material (STIM) positioned between claim 2 , and coupled to claim 2 , the IHS and the die.4. The microelectronic package of claim 3 , wherein the STIM includes indium.5. The microelectronic package of claim 1 , wherein the sealant has a modulus range between 3 and 50 megapascals (MPas).6. The microelectronic package of claim 1 , wherein the sealant is an epoxy sealant or a silicon sealant.7. The microelectronic package of claim 1 , wherein the sealant includes a silica claim 1 , silicone claim 1 , alumina claim 1 , metal claim 1 , or organic filler.8. The microelectronic package of claim 1 , wherein the sealant includes silane claim 1 , titanate claim 1 , or zirconate.9. The microelectronic package of claim 1 , wherein the IHS includes copper.10. The microelectronic package of claim 1 , wherein the sealant extends away from the package substrate at least partially along a wall of the IHS.11. The microelectronic package of claim 1 , wherein the sealant forms a fillet around a periphery of the IHS.12. The microelectronic package of claim 1 , wherein the IHS ...

CHIP PACKAGE WITH LID

Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has a first support structure and a second support structure, and the first support structure and the second support structure are positioned at respective corner portions of the substrate. An opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure. 1. A chip package , comprising:a substrate;a semiconductor die over the substrate; anda lid covering a top surface of the semiconductor die, wherein the lid has a first support structure and a second support structure, the first support structure and the second support structure are positioned at respective corner portions of the substrate, an opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure.2. The chip package as claimed in claim 1 , wherein at least one of the first support structure and the second support structure has a sidewall surface with an L-shaped profile.3. The chip package as claimed in claim 1 , wherein one of the support structures has a base portion and a side portion claim 1 , a bottom surface of the base portion is substantially parallel to a top surface of the substrate claim 1 , and the side portion is in direct contact with the base portion and an upper plate of the lid.4. The chip package as claimed in claim 3 , wherein the side portion has a slanted sidewall extending from the base portion to the upper plate of the lid.5. The chip package as claimed in claim 1 , wherein the first support structure has a first side and a second side opposite to the ...

Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor Die

A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing an encapsulant around the first semiconductor die;forming a shielding layer over the first semiconductor die;forming a channel through the encapsulant around the first semiconductor die;depositing a conductive material in the channel around the first semiconductor die and electrically connected to the shielding layer; andforming an interconnect structure over the conductive material, encapsulant, and first semiconductor die, wherein the interconnect structure is electrically connected to the conductive material.2. The method of claim 1 , wherein the conductive material extends into the interconnect structure.3. The method of claim 1 , wherein the conductive material terminates at a boundary between the encapsulant and interconnect structure.4. The method of claim 1 , further including providing side-by-side first semiconductor die each covered by the shielding layer and surrounded by the conductive material.5. The method of claim 1 , further ...

Composite magnetic sealing material

Disclosed herein is a composite magnetic sealing material includes a resin material and a filler blended in the resin material in a blended ratio of 30 vol. % or more to 85 vol. % or less. The filler includes a magnetic filler containing Fe and 32 wt. % or more and 39 wt. % or less of a metal material contained mainly of Ni, thereby a thermal expansion coefficient of the composite magnetic sealing material is 15 ppm/° C. or less.

CHIP SCALE PACKAGE AND RELATED METHODS

Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material. 1. A method for forming a semiconductor package , the method comprising:providing a glass lid;patterning a first material on the glass lid;patterning a second material on the glass lid;coupling a wafer to the glass lid at the first material and at the second material; andforming one or more semiconductor packages from the wafer and the glass lid by singulating the wafer and the glass lid;wherein the second material forms an outer wall at the edge of the glass lid and the wafer and the first material forms an inner wall inside the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; andwherein a modulus of the first material is lower than a modulus of the second material.2. The method of claim 1 , wherein a maximum cavity wall stress on the outer wall and on the one or more inner walls is less than 40 MPa.3. The method of claim 1 , wherein the semiconductor package is capable of passing a moisture sensitivity level (MSL) 1 test.4. The method of claim 1 , wherein the first material is a dry film and the second material is a solder mask.5. A method for making a semiconductor package claim 1 , the method comprising:providing a wafer and a transparent lid;patterning a first material to form an inner wall on the wafer;patterning a second material on the transparent lid to form an outer wall; andcoupling the ...

FINGERPRINT MODULE

A fingerprint module, which relates to the field of biometric identification. The fingerprint module includes a cover plate (), a sensor package (), a circuit board (), a support frame () and an adhesive (); the cover plate () is provided with an ink layer () at a lower surface thereof, the sensor package () is located below the ink layer (), a lower surface of the ink layer () is covered with the adhesive (), and the cover plate () is fixedly connected with the sensor package () via the adhesive () below the ink layer (); the sensor package () is fixed over the circuit board (), and the support frame () is arranged on the circuit board () at both side; gaps between said constituent parts are filled with the adhesive (). 1. A fingerprint module , comprising:a cover plate, a sensor package, a circuit board, a support frame and an adhesive; whereinthe cover plate is provided with an ink layer at a lower surface thereof, the sensor package is located below the ink layer, a lower surface of the ink layer is covered with the adhesive, and the cover plate is fixedly connected with the sensor package via the adhesive below the ink layer;the sensor package is fixed over the circuit board, and the support frame is arranged on the circuit board at both side of the sensor package;the adhesive fills gaps between the cover plate, the sensor package, the circuit board and the support frame.2. The fingerprint module according to claim 1 , wherein the sensor package is a wafer level package.3. The fingerprint module according to claim 1 , wherein the fingerprint module further comprises a reinforcing plate claim 1 , and the support frame and the circuit board are fixed over the reinforcing plate claim 1 , respectively.4. The fingerprint module according to claim 3 , wherein the cover plate is located inside the support frame.5. The fingerprint module according to claim 4 , wherein the support frame has claim 4 , at a lower end connected with the reinforcing plate claim 4 , an ...

PACKAGED SEMICONDUCTOR DEVICES WITH WIRELESS CHARGING MEANS

A semiconductor device package is provided, including a semiconductor device, a magnetic flux generation unit, a molding material, and a conductive slot. The magnetic flux generation unit is surrounding an axis and configured to produce magnetic flux passes through the magnetic flux generation unit. The molding material is surrounding the semiconductor device and the magnetic flux generation unit. The conductive slot is positioned over the molding material, wherein an opening is formed on the conductive slot, and the axis passes through the opening. 1. A semiconductor device package , comprising:a semiconductor device;a molding material surrounding the semiconductor device; anda conductive slot provided within a dielectric layer that is adjacent to the molding material, wherein the conductive slot has an opening.2. The semiconductor device package as claimed in claim 1 , further comprising a coil configured to receive magnetic flux.3. The semiconductor device package as claimed in claim 2 , wherein the conductive slot and the coil are in alignment with one another.4. The semiconductor device package as claimed in claim 2 , wherein the coil surrounds an axis claim 2 , the axis extends along a direction that is perpendicular with the conductive slot.5. The semiconductor device package as claimed in claim 4 , wherein the conductive slot is formed symmetrical to the axis.6. The semiconductor device package as claimed in claim 1 , further comprising a redistribution layer electrically connected to the semiconductor device claim 1 , wherein the conductive slot and the redistribution layer are each arranged at opposite sides of the semiconductor device.7. The semiconductor device package as claimed in claim 1 , wherein a channel is formed on the conductive slot and connects the opening to an edge of the conductive slot claim 1 , wherein the edge of the conductive slot is distributed by the channel.8. The semiconductor device package as claimed in claim 1 , wherein the ...

HERMETIC LID SEAL PRINTING METHOD

A method is provided. The method includes one or more of securing a die into a cavity of a hermetic package base, providing one or more bond connections to the die, placing a hermetic package lid on the package base, and 3D printing, by a 3D printer, hermetic lid seal material to a joint between the hermetic package base and the hermetic package lid, at a temperature at or below 100 degrees Celsius. 1. A method , comprising:securing a die into a cavity of a hermetic package base;providing one or more bond connections to the die;placing a hermetic package lid on the package base; and3D printing, by a 3D printer, hermetic lid seal material to a joint between the hermetic package base and the hermetic package lid, at a temperature at or below 100 degrees Celsius.2. The method as recited in claim 1 , further comprising:clamping the hermetic package lid to the hermetic package base prior to 3D printing hermetic lid seal material.3. The method as recited in claim 1 , wherein the die comprises a device that may be damaged at temperatures over 300 degrees Celsius claim 1 , wherein the hermetic lid seal material is a hermetic compound.4. The method as recited in claim 3 , wherein the hermetic package base comprises one of ceramic claim 3 , metal claim 3 , or glass claim 3 , wherein the hermetic package lid comprises one of ceramic claim 3 , metal claim 3 , or glass.5. The method as recited in claim 4 , wherein the hermetic package base material is different than the hermetic package lid material.6. The method as recited in claim 3 , wherein the hermetic lid seal material comprises zinc oxide.7. The method as recited in claim 3 , wherein the lid seal material is 3D printed in liquid form.8. The method as recited in claim 3 , wherein the 3D printer applies the hermetic lid seal material by a selective laser sintering process claim 3 , the selective laser sintering process comprising:3D printing, by a 3D printer, the lid seal material in powder form to a joint between the ...

Package-on-Package Structure Including a Thermal Isolation Material and Method of Forming the Same

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

O-RING SEALS FOR FLUID SENSING

In some examples, a device comprises a substrate including a notch formed in a surface of the substrate and a semiconductor die positioned in the notch and including an electrochemical sensor on an active surface of the semiconductor die. The device also comprises a chemically inert member abutting the surface of the substrate and including an orifice in vertical alignment with the electrochemical sensor as a result of the semiconductor die being positioned in the notch. The device also comprises a compressed o-ring seal positioned between the chemically inert member and the active surface of the semiconductor die, the compressed o-ring seal circumscribing the electrochemical sensor. 1. A device , comprising:a substrate including a notch formed in a surface of the substrate;a semiconductor die positioned in the notch and including an electrochemical sensor on an active surface of the semiconductor die;a chemically inert member abutting the surface of the substrate and including an orifice in vertical alignment with the electrochemical sensor as a result of the semiconductor die being positioned in the notch; anda compressed o-ring seal positioned between the chemically inert member and the active surface of the semiconductor die, the compressed o-ring seal circumscribing the electrochemical sensor.2. The device of claim 1 , further comprising a mold compound abutting the chemically inert member claim 1 , the surface of the substrate claim 1 , and an outer surface of the compressed o-ring seal.3. The device of claim 1 , further comprising a bond wire coupled to the active surface of the semiconductor die and the surface of the substrate.4. The device of claim 1 , wherein the compressed o-ring seal is positioned between the chemically inert member and the active surface of the semiconductor die such that the chemically inert member does not make contact with the active surface of the semiconductor die.5. The device of claim 1 , wherein the chemically inert member ...

EPOXY RESIN COMPOSITION, CURED OBJECT AND OPTICAL SEMICONDUCTOR SEALING MATERIAL

An epoxy resin composition, a cured object thereof, and an optical semiconductor sealing material using the cured object are described. The epoxy resin composition includes an alicyclic epoxy resin (A) and a vinyl polymer particle (B). An acetone soluble part of the vinyl polymer particle (B) is 30 mass % or more. The mass average molecular weight of the acetone soluble part is 100,000 or more. The volume average primary particle diameter (Dv) is 200 nm or more. The epoxy resin composition is rapidly turned into a gel state by heating for a short time, and the transparency of the obtained cured object is good. 1. An epoxy resin composition comprising an alicyclic epoxy resin (A) and a vinyl polymer particle (B) , wherein an acetone soluble part of the vinyl polymer particle (B) is 30 mass % or more , a mass average molecular weight of the acetone soluble part is 100 ,000 or more , and a volume average primary particle diameter (Dv) of the vinyl polymer particle (B) is 200 nm or more.2. The epoxy resin composition of claim 1 , wherein the alicyclic epoxy resin (A) is selected from at least one of 3 claim 1 ,4-epoxycyclohexylmethyl 3′ claim 1 ,4′-epoxycyclohexanecarboxylate and bisphenol A-type hydrogenated alicyclic epoxy resin.3. The epoxy resin composition of claim 1 , wherein the vinyl polymer particle (B) is obtained by polymerizing a monomer material claim 1 , and the monomer material comprises 1 mass % or more of at least one monomer containing a functional group that is selected from a vinyl monomer containing a carboxyl group and a vinyl monomer containing a hydroxyl group.4. The epoxy resin composition of claim 3 , wherein the monomer material comprises 3 mass % or more of the monomer containing a functional group.5. The epoxy resin composition of claim 1 , wherein the vinyl polymer particle (B) is a pregel agent for epoxy resin.6. The epoxy resin composition of claim 1 , wherein a cured object obtained by curing the epoxy resin composition and having a ...

ELECTRONIC COMPONENT

An electronic component includes a piezoelectric substrate, a functional electrode on the piezoelectric substrate, a support layer on the piezoelectric substrate, a cover layer on the support layer, the cover layer, the support layer, and the piezoelectric substrate defining a hollow space that the functional electrode faces, and connection terminals that are electrically connected to the functional electrode, that are each made from a metal particle aggregate, and that each have a porous structure. The connection terminals are each located at a position in which the connection terminals overlap at least a portion of the hollow space in plan view. 1. An electronic component comprising:a piezoelectric substrate;a functional electrode that is disposed on the piezoelectric substrate;a support layer that is disposed on the piezoelectric substrate;a cover layer that is disposed on the support layer, the cover layer, the support layer, and the piezoelectric substrate defining a hollow space that the functional electrode faces; anda connection terminal that is electrically connected to the functional electrode, that is made from a metal particle aggregate, and that has a porous structure; whereinthe connection terminal is located at a position in which the connection terminal overlaps at least a portion of the hollow space in plan view.2. The electronic component according to claim 1 , wherein the connection terminal is disposed on the cover layer.3. The electronic component according to claim 1 , wherein the cover layer is made of a resin.4. The electronic component according to claim 1 , wherein the connection terminal has a rectangular or substantially rectangular planar shape.5. The electronic component according to claim 1 , further comprising:another functional electrode that is located above the functional electrode; andan element substrate that is located above the piezoelectric substrate; whereinthe another functional electrode is provided on the element substrate ...

PACKAGE STRUCTURE OF FINGERPRINT IDENTIFICATION CHIP

The present invention provides a package structure of a fingerprint identification chip, including: a metal substrate, having a through opening and two grooves extending from two opposite sides of the through opening; a fingerprint identification chip, disposed in the through opening and having an upper surface and a lower surface, the lower surface having a bonding pad; a cover plate, fixedly disposed on the metal substrate and covering the upper surface of the fingerprint identification chip; a flexible printed circuit (FPC), disposed on the lower surface of the fingerprint identification chip and having a first surface and a second surface, the second surface having a first metal contact; and a metal reinforcing plate, inserted into the two grooves and covering the through opening, where the bonding pad is electrically connected to the first metal contact through a wire. 1. A package structure of a fingerprint identification chip , comprising:a metal substrate, having a through opening and two grooves extending from two opposite sides of the through opening;a fingerprint identification chip, disposed in the through opening and having an upper surface and a lower surface, the lower surface having at least one bonding pad;a cover plate, fixedly disposed on the metal substrate and covering the upper surface of the fingerprint identification chip;a flexible printed circuit (FPC), disposed on the lower surface of the fingerprint identification chip and having a first surface and a second surface, the second surface having a first metal contact; anda metal reinforcing plate, inserted into the two grooves and covering the through opening;wherein the bonding pad is electrically connected to the first metal contact through a wire.2. The package structure of a fingerprint identification chip according to claim 1 , wherein a colloid is coated on the at least one bonding pad claim 1 , the wire and the first metal contact claim 1 , and the colloid is an underfill.3. The ...

HERMETIC PACKAGE FOR HIGH CTE MISMATCH

The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall. 1. A package comprising:a metal base having a top surface; and a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material;', 'the ceramic wall segments with the connecting form a ring wall, wherein the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall; and', 'the metal base is surrounded by the ring wall, and at least a portion of the top surface of the metal base is exposed through the ring wall., 'multiple ceramic wall segments discrete from each other, wherein2. The package of wherein the gap that exists between every two adjacent ceramic wall segments is between 0-50 thousandth of an inch.3. The package of wherein the metal base has a coefficient of thermal expansion (CTE)>11 μm/m·K claim 1 , and each ceramic wall segment has a CTE<9 μm/m·K.4. The package of wherein:the metal base is formed of copper, copper molybdenum, copper tungsten, a layered stack of copper and tungsten, or a layered stack of copper and moly; andeach ceramic wall segment is formed of alumina.5. The package of wherein the number of the ceramic wall segments is four claim 1 , and every two adjacent ceramic wall segments are orthogonal.6. The package of wherein the four ceramic wall segments are identical claim 5 , and the ring wall is a square ring wall.7. The package of wherein:each ceramic ...

3DIC Packaging with Hot Spot Thermal Management Features

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material. 1. A package comprising:a first die stack bonded and electrically connected to a conductive line of a substrate;a second die stack bonded to the substrate and adjacent the first die stack;a thermal interface material on a surface of the conductive line; anda conductive lid thermally connected to the substrate through the thermal interface material, wherein a first portion of the conductive lid is thicker than a second portion of the conductive lid, the first portion of the conductive lid is directly over the first die stack, the second portion of the conductive lid is directly over the second die stack, and wherein a third portion of the conductive lid extends between a sidewall of the first die stack and a sidewall of the second die stack.2. The package of claim 1 , wherein the conductive lid is adhered to the substrate by an adhesive.3. The package of claim 2 , wherein the adhesive has a lower thermal conductivity than the thermal interface material.4. The package of claim 1 , wherein the conductive line is a signal line claim 1 , a power line claim 1 , or a ground line.5. The package of claim 1 , wherein the conductive line is a dummy feature.6. The package of claim 1 , wherein the thermal interface material has a thermal conductivity in a range of 3 W/m·K to 50 W/m·K.7. The package of further comprising:a second conductive line in the substrate and electrically connected to the second die stack; anda second thermal interface material on a surface of the second conductive line, wherein the conductive lid is thermally connected to ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of insulating blocks respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements, a plurality of first set supporting pillars respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements and respectively correspondingly positioned over the plurality of insulating blocks, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars and respectively correspondingly positioned over the plurality of insulating blocks. 1. A semiconductor device , comprising:a semiconductor substrate;a plurality of first set conductive elements separately positioned above the semiconductor substrate;a plurality of insulating blocks respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements;a plurality of first set supporting pillars respectively correspondingly positioned between adjacent pairs of the plurality of first set conductive elements and respectively correspondingly positioned over the plurality of insulating blocks; anda plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars and respectively correspondingly positioned over the plurality of insulating blocks.2. The semiconductor device of claim 1 , further comprising a first sealing layer claim 1 , wherein the first sealing layer is positioned above the plurality of first set conductive elements.3. The semiconductor device of claim 1 , wherein the plurality of first set conductive elements are formed of metal claim 1 , metal alloy claim 1 , silicate claim 1 , silicide ...

Integrated Circuit (IC) Device Package Lid Attach Utilizing Nano Particle Metallic Paste

An IC device package includes a carrier, one or more IC devices and a lid. The lid includes a lid-ridge. The lid is connected to the carrier by connecting the lid-ridge to the carrier with first nano particle metallic paste, prior to connecting the IC device to the carrier. Subsequent to connecting the IC device to the carrier, the lid is connected to the lid-ridge with second nano particle metallic paste. The nano particle metallic paste may be sintered to form a metallic connection. In multi-IC device packages, the lid-ridge may be positioned between the lid and the carrier and between the IC devices. 17.-. (canceled)8. A method of fabricating an integrated circuit (IC) device carrier package comprising:connecting a lower contact of a lid-ridge to a pad of an IC device carrier with a first nano particle metallic paste;subsequently attaching an IC device to the IC device carrier;forming a contiguous underfill material instance between the IC device and the IC device carrier and between a bar of the lid-ridge and the IC device carrier;curing the underfill and sintering the first nano particle metallic paste to form a first metallic connection between the lower contact and the first pad.9. The method of claim 8 , further comprising:applying seal band material to the IC device carrier around the perimeter of the IC device and the lid-ridge.10. The method of claim 8 , further comprising:applying thermal interface material to the IC device upper surface.11. The method of claim 8 , further comprising:applying second nano particle metallic paste to the underside of a lid.12. The method of claim 11 , further comprising:attaching the lid to the lid-ridge by connecting an upper contact of the lid-ridge to the underside of the lid with the second nano particle metallic paste.13. The method of claim 12 , further comprising sintering the second nano particle metallic paste to form a second metallic connection between the upper contact and the lid.14. The method of claim 11 , ...

Semiconductor power converter and method of manufacturing the same

According to one embodiment, a semiconductor power converter includes first and second electrical conductors opposed to each other, first and second semiconductor elements joined to a first joint surface of the first electrical conductor, first and second convex electrical conductors joined to the first and second semiconductor elements, a junction joined to the first and second convex electrical conductors and a second joint surface of the second electrical conductor, power terminals, signal terminals, and an envelope sealing the constituent members. The envelope includes a flat bottom surface which extends perpendicular to the semiconductor elements and in which first and second bottom surfaces of the electrical conductors are exposed.

SEALING CAP FOR ELECTRONIC COMPONENT

An electronic component cap for producing a package having a sealed region by being bonded to a base, having a brazing material-fused surface to which a brazing material is fused and a sealing surface corresponding to the sealed region. The brazing material-fused surface has a non-flat work surface formed by plastic working, and a ratio (Sc/Sf) of a surface area (Sc) of the brazing material-fused surface per unit area to a surface area (Sf) of the sealing surface per unit area satisfies 1 Подробнее

Method for producing hermetic package

A technical object of the present invention is to devise a method by which bonding strength between an element base and a sealing material layer can be increased without thermal degradation of a member to be housed inside, to thereby improve long-term reliability of a hermetic package. A method of producing a hermetic package of the present invention includes the steps of: preparing a ceramic base and forming a sealing material layer on the ceramic base; preparing a glass substrate and arranging the ceramic base and the glass substrate so that the glass substrate is brought into contact with the sealing material layer on the ceramic base; and irradiating the sealing material layer with laser light from a glass substrate side to seal the ceramic base and the glass substrate with each other through intermediation of the sealing material layer, to thereby provide a hermetic packages.

AIR CAVITY PACKAGE WITH IMPROVED CONNECTIONS BETWEEN COMPONENTS

An air cavity package with one or more dovetail recesses configured with a first recess and a coincident second recess. The first recess has a first depth and the second recess has a second depth. The first recess has a lower width and an upper width smaller than the first lower width creating a dovetail shape. Individual dovetail recesses are created by creating a first recess in the flange at a first width and depth. A second recess with a second width and second depth and coincident with the first recess is pressed into the flange. The second width is greater than the first width and the second depth is smaller than the first depth. Pressing the second recess causes the first width at an upper portion to decrease, causing the first recess to develop a dovetail shape. 1. A method for creating an individual dovetail recess in a flange of an air cavity package , comprising the steps of:creating a first recess in the flange having a first width and first depth;pressing a second recess into the flange, the second recess being coincident with the first recess and having a second width and a second depth, wherein the second width it greater than the first width and the second depth is smaller than the first depth; andwherein pressing the second recess causes the first width at an upper portion of the first recess to decrease, causing the first recess to develop a dovetail shape.2. The method of wherein the first recess is elliptical.3. The method of wherein the second recess is elliptical.4. The method of wherein the first recess is rectangular.5. The method of wherein the second recess is rectangular.6. The method of wherein a plurality of individual dovetail recesses are created in the flange proximate the location of attachment of an air cavity package sidewall.7. An air cavity package claim 1 , comprising a flange having a plurality of individual dovetail recesses about a flange perimeter proximate the location of attachment of an air cavity package sidewall.8. The ...

Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure

An electronic device disposed in a package that includes: an interposer, fan-out interconnect (FOI), and a lid. The interposer having first size and first surface upon which die terminals (DTs) are disposed and are configured to electrically couple to integrated circuit die (IC), and second surface upon which substrate terminals (STs) are disposed and are configured to electrically couple to substrate. The IC has second size smaller than the first size, and the IC is mounted on the first surface in electrical contact with the DTs, the interposer is mounted on third surface, and the package substrate has third size, larger than the first size. The FOI establishes electrical interconnection between DTs and STs, the DTs have first pitch size and the STs have second pitch size, larger than first pitch size. The lid has first section, configured to abut fourth surface, and second section, mounted on the third surface.

ELECTRONIC COMPONENT MOUNTING BOARD, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

An electronic component mounting board includes a substrate on which an electronic component is mountable. The substrate includes a plurality of layers stacked on one another, a plurality of conductor layers located between the plurality of layers, and a recess located continuously over side surfaces of the plurality of layers. The electronic component mounting board includes an electrode located in the recess and covering an end of at least one of the plurality of conductor layers in the recess. The conductor layers contain a metal material different from a metal material contained in the electrode. The conductor layers have outer edges located inward from an outer edge of the substrate in a plan view. 1. An electronic component mounting board , comprising:a substrate on which an electronic component is mountable, the substrate including a plurality of layers stacked on one another, a plurality of conductor layers located between the plurality of layers, and a recess located continuously over side surfaces of the plurality of layers; andan electrode located in the recess and covering an end of at least one of the plurality of conductor layers in the recess,wherein the conductor layers contain a metal material different from a metal material contained in the electrode, and the conductor layers have outer edges located inward from an outer edge of the substrate in a plan view.2. The electronic component mounting board according to claim 1 , whereinthe plurality of conductor layers comprise a material having a higher copper content than a material for the electrode.3. The electronic component mounting board according to claim 1 , whereinthe electrode extends continuously from the recess onto an upper surface of the substrate.4. The electronic component mounting board according to claim 2 , whereinthe electrode extends continuously from the recess onto an upper surface of the substrate.5. The electronic component mounting board according to claim 1 , whereinthe ...

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. 1. A package comprising:a chip having a frontside and a backside, the chip comprising four corner areas;a die bonded to the frontside of the chip by a first set of conductive connectors;a molding layer on the frontside of the chip and surrounding sidewalls of the die;a dam structure in each of the four corner areas on the backside of the chip, each of the dam structures being disposed a distance from an edge of the chip, each of the dam structures being circular in a plane parallel to the backside of the chip; anda second set of conductive connectors on the backside of the chip.2. The package of claim 1 , wherein the dam structure is electrically isolated from the chip.3. The package of claim 1 , wherein a distance between the frontside of the chip and a surface of the molding layer distal the frontside of the chip is greater than a distance between the frontside of the chip and a surface of the die distal the frontside of the chip.4. The package of claim 1 , further comprising a through via extending through the chip.5. The package of claim 4 , wherein the through via comprises a metal via and a barrier layer lining sidewalls of the metal via.6. The package of claim 5 , further comprising an insulation layer between the chip and the through via claim 5 , the insulation layer comprising an oxide.7. The package of claim 1 , wherein the dam structure comprises a polymer material.8. The package of claim 1 , wherein a diameter of the dam structure is less than a diameter of each of the conductive ...

SEMICONDUCTOR DEVICE

There is provided a semiconductor device including a substrate whose surface is made of an insulation material, a semiconductor chip flip-chip connected on the substrate, and a heat sink bonded to the semiconductor chip via a thermal interface material and fixed to the substrate outside the semiconductor chip, in which the heat sink has a protrusion part protruding toward the substrate and bonded to the substrate via a conductive resin between a part bonded to semiconductor chip and a part fixed to the substrate and the heat sink has a stress absorbing part. According to the present invention, the protrusion part of the heat sink is prevented from being peeled off from the substrate at the part where the protrusion part of the heat sink is bonded to the substrate. 19-. (canceled)10. A semiconductor device , comprising:a substrate;a semiconductor chip on a top side of the substrate; and a central portion over a top side of the semiconductor chip;', 'a fixing part coupled to the top side of the substrate;', 'a protrusion part coupled to the top side of the substrate between the fixing part and the semiconductor device; and', 'a recession between the central portion and the fixing part;, 'a heatsink on a top side of the substrate, wherein the heat sink compriseswherein a thickness of the heatsink at the recession is less than a thickness of the heatsink between the protrusion part and the fixing part.11. The semiconductor device of claim 10 , further comprising a thermal interface material (TIM) contacting the central portion of the heatsink and the top side of the substrate.12. The semiconductor device of claim 10 , wherein the fixing part is attached to the top side of the substrate via an adhesive.13. The semiconductor device of claim 10 , wherein the protrusion part is coupled to the top side of the substrate via a conductive adhesive.14. The semiconductor device of claim 10 , wherein the heatsink has a lower rigidity at the recession than between the protrusion ...

Connected Plane Stiffener Within Integrated Circuit Chip Carrier

An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier. 17.-. (canceled)8. A method of fabricating an integrated circuit (IC) chip carrier comprising:forming a first plane within a first plane fabrication layer;forming a plane separation layer upon the first plane and upon the first plane fabrication layer;forming a channel via within the plane separation layer and upon the first plane;forming a second plane fabrication layer upon the channel via and upon the plane separation layer; andforming a second plane within the second plane fabrication layer and upon the channel via.9. The method of claim 8 , wherein the first plane and the second plane resist bending moments internal to the IC chip carrier.10. The method of claim 8 , wherein the channel via resists shear forces internal to the IC chip carrier.11. The method of claim 8 , wherein the first plane distributes power potential within the IC chip carrier and wherein the second plane distributes power potential within the IC chip carrier.12. The method of claim 8 , wherein the first plane distributes ground potential within the IC chip carrier and wherein the second plane distributes ground potential within the IC chip carrier.13. The method of claim 8 , wherein forming the first plane within the first plane fabrication layer ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A recess is formed in one silicon substrate. A silicon oxide film is formed in another one silicon substrate at a portion space apart from a space-to-be-formed region. The silicon oxide film has a groove surrounding the space-to-be-formed region and extending to an outer periphery of the other one silicon substrate. Further, the other one silicon substrate and the one silicon substrate are directly bonded to each other via the silicon oxide film so as to cover the groove. A gas discharge passage, a stacking structure of the silicon substrates and the silicon oxide film are formed, and the space is formed inside the stacking structure by the recess. Then, by the heat treatment, the gas inside the space is discharged to the outside of the stacking structure through the gas discharge passage. 1. A method of manufacturing a semiconductor device having a space arranged therein , comprising:preparing a plurality of silicon substrates;forming a recess in at least first one of the plurality of silicon substrates;forming a silicon oxide film in at least second one of the plurality of silicon substrates at a portion of the at least second one of the plurality of silicon substrates, which is space apart from a space-to-be-formed region of the semiconductor device, the silicon oxide film having a groove surrounding the space-to-be-formed region and extending to an outer periphery of the at least second one of the plurality of silicon substrates;directly bonding the at least second one of the plurality of silicon substrates in which the silicon oxide film is formed and the at least first one of the plurality of silicon substrates via the silicon oxide film so as to cover the groove, forming a gas discharge passage and a stacking structure of the plurality of silicon substrates and the silicon oxide film, and forming the space inside the stacking structure by the recess; anddischarging gas inside the space to an outside of the stacking structure through the gas discharge passage ...

Multi-chip package with partial integrated heat spreader

A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

INTEGRATED FILTER STACK FOR A RADIO FREQUENCY (RF) FRONT-END MODULE (FEM)

Embodiments may relate to a radio frequency (RF) front-end module (FEM) that includes a first acoustic wave resonator (AWR) die coupled with a package substrate. The RF FEM may also include a second AWR die coupled with the first AWR die. The first AWR die may be between the package substrate and the second AWR die. Other embodiments may be described or claimed. 1. A radio frequency (RF) front-end module (FEM) comprising:a first acoustic wave resonator (AWR) die coupled with a package substrate; anda second AWR die coupled with the first AWR die such that the first AWR die is between the package substrate and the second AWR die.2. The RF FEM of claim 1 , wherein the second AWR die is coupled with the first AWR die by a connective element that is coupled to the first AWR die and the second AWR die claim 1 , and the connective element hermetically seals a resonant element of the second AWR die.3. The RF FEM of claim 1 , further comprising a lid between claim 1 , and coupled to claim 1 , the package substrate and the first AWR die.4. The RF FEM of claim 3 , wherein the lid includes a terminating inductor.5. The RF FEM of claim 4 , wherein the lid includes an inductor-select switch coupled with the terminating inductor.6. The RF FEM of claim 3 , wherein the lid includes a band-select switch.7. The RF FEM of claim 3 , wherein the lid is formed of a non-organic material.8. The RF FEM of claim 1 , wherein the first AWR die is one of a surface acoustic wave (SAW) resonator and a thin-film bulk acoustic resonator (FBAR) resonator and the second AWR die is the other of the SAW resonator and the FBAR resonator.9. The RF FEM of claim 1 , wherein the RF FEM further includes an active die coupled with claim 1 , and adjacent to claim 1 , the first AWR die.10. A radio frequency (RF) front-end module (FEM) comprising:a package substrate; a first acoustic wave resonator (AWR) die related to a first frequency band; and', 'a second AWR die related to a second frequency band, wherein ...

Remapped Packaged Extracted Die with 3D Printed Bond Connections

An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.

Memory module

According to one embodiment, a memory module includes a substrate, a semiconductor memory device, a plate-form conductive member, wire, and a mold member. The substrate includes a ground terminal to which a ground potential is applied. The semiconductor memory device is provided on the substrate. The plate-form conductive member is provided on the semiconductor memory device. The wire that electrically connects the ground terminal to the plate-form conductive member. The mold member seals the semiconductor memory device on the substrate, the plate-form conductive member and the wire.

MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package. 1. A molded air cavity package , comprising:a base flange, comprising:a flange frontside having a device mount area; anda flange backside opposite the flange frontside, as taken along a centerline of the molded air cavity package;retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside;retention tabs having openings through which the retention posts are received;a molded package body bonded to the base flange and enveloping, at least in substantial part, the retention posts and the retention tabs; andpackage leads extending from the molded package body.2. The molded air cavity package of wherein the package leads and the retention tabs comprise singulated portions of a leadframe.3. The molded air cavity package of wherein the retention posts extend substantially parallel to the centerline of the air cavity package; andwherein the retentions posts comprise deformed terminal ends preventing disengagement of the retention ...

MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline. 1. A molded air cavity package having a package centerline , the molded air cavity package comprising:a molded package body having an upper peripheral edge portion;an air cavity around which the upper peripheral edge portion extends;a cover piece bonded to the upper peripheral edge portion to sealingly enclose the air cavity, the cover piece having a lower peripheral edge portion cooperating with the upper peripheral edge portion to define a cover-body interface, the cover-body interface comprising:an annular channel extending around the cover-body interface, as taken about the package centerline; andfirst and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively, the first and second hardstop features contacting to determine a vertical height of the annular channel, as taken along the package centerline.2. The molded air cavity package of wherein the first hardstop feature comprises a raised annular rim ...

INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES, AND METHODS OF MANUFACTURE

Dies () with integrated circuits are attached to a wiring substrate (), possibly an interposer, and are protected by a protective substrate () attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided. 1. (canceled)2. A structure comprising:a first semiconductor element including a cavity extending into the first semiconductor element from a first side;a second semiconductor element directly bonded to the first side of the first semiconductor element without an intervening adhesive along a bond interface, the second semiconductor element enclosing the cavity of the first semiconductor element; anda conductive via extending through the second semiconductor element, the conductive via disposed laterally offset from the bond interface.3. The structure of claim 2 , wherein the conductive via is disposed within a lateral footprint of the cavity.4. The structure of claim 2 , further comprising a first bonding layer at a first surface of the first semiconductor element and a second bonding layer at a second surface of the second semiconductor element claim 2 , the first and second bonding layers directly bonded to one another without an intervening adhesive.5. The structure of claim 4 , wherein the first and second bonding layers comprise silicon oxide.6. The structure of claim 2 , wherein the second semiconductor element comprises an interposer substrate claim 2 , the conductive via extending through the interposer substrate.7. The structure of claim 6 , ...

CONTOURED-ON-HEAT-SINK, WRAPPED PRINTED WIRING BOARDS FOR SYSTEM-IN-PACKAGE APPARATUS

A system-in-package apparatus includes a contoured heat sink that provides a first recess and a subsequent recess. The system-in-package apparatus includes a flexible printed wiring board that is wrapped onto the contoured heat sink after a manner to enclose the first semiconductive device into the first recess and a semiconductive device in the subsequent recess. 124-. (canceled)25. A system-in-package apparatus comprising:a contoured heat sink made of an integral metallic material, the contoured heat sink including a back surface and receiving surfaces of a first recess, a subsequent recess, a ledge including a precipice, and a prominence, and wherein the back surface communicates through the metallic material to each of the first recess subsequent recess, ledge, and prominence;a flexible printed wiring board (PWB), wherein a plurality of devices is disposed upon the flexible PWB, and wherein some of the plurality of devices on the flexible PWB is mated to the flexible PWB where the flexible PWB is disposed against a receiving surface of the contoured heat sink; andwherein the flexible PWB forms a contoured configuration touching each of the first recess, the subsequent recess, the ledge, and the prominence.26. The system-in-package apparatus of claim 25 , further including a lid attached to an upper ledge of the contoured heat sink claim 25 , wherein a portion of the flexible PWB is mated to the lid claim 25 , and wherein at least one device mounted on the flexible PWB is disposed on the portion of the flexible PWB mated to the lid.27. The system-in-package apparatus of claim 25 , further including:a lid attached to an upper ledge of the contoured heat sink, wherein a portion of the flexible PWB is mated to the lid, and wherein at least one device mounted on the flexible PWB is disposed on the portion of the flexible PWB mated to the lid; andat least one leg extending from the lid, wherein the at least one leg contacts the flexible PWB.28. The system-in-package ...

Thermal and stress isolation for precision circuit

Described examples include microelectronic devices and integrated circuits with an active first circuit in a first segment of a first wafer, a second circuit in a second segment of the first wafer, and second and third wafers bonded to different surfaces of the first wafer to provide first and second cavities with surfaces spaced from the first segment. An opening extends through the first wafer between the first and second cavities to separate portions of the first and second segments and to form a sealed cavity that surrounds the first segment. A bridge segment of the first wafer supports the first segment in the sealed cavity and includes one or more conductive structures to electrically connect the first and second circuits.

Module Arrangement For Power Semiconductor Devices

A module arrangement for power semiconductor devices, including one or more power semiconductor modules, wherein the one or more power semiconductor modules include a substrate with a first surface and a second surface being arranged opposite to the first surface, wherein the substrate is at least partially electrically insulating, wherein a conductive structure is arranged at the first surface of the substrate, wherein at least one power semiconductor device is arranged on the conductive structure and electrically connected thereto, wherein the one or more modules includes an inner volume for receiving the at least one power semiconductor device which volume is hermetically sealed from its surrounding by a module enclosure, wherein the module arrangement includes an arrangement enclosure at least partly defining a volume for receiving the one or more modules, and wherein the arrangement enclosure seals covers the volume.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor module having a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed, a cooler, first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler, and second insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease. 1. A semiconductor device comprising:a semiconductor module comprising a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed;a cooler;first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler; andsecond insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease.2. The semiconductor device according to claim 1 , wherein the resin has a resin through hole formed therein which communicates with the at least one radiator plate through hole.3. The semiconductor device according to claim 2 , whereinthe resin has a wide portion formed in at least part of the resin through hole, the wide portion having a larger width than the at least one radiator plate through hole, andthe wide portion has third insulating grease provided therein.4. The semiconductor device according to claim 2 , further comprising a stopper for blocking at least part of the resin through hole.5. The semiconductor device according to claim 4 , further comprising gel for fixing the stopper in place.6. The ...

LIMITING ELECTRONIC PACKAGE WARPAGE

An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed within the perimeter recess. The lid-ring exerts a reverse bending moment upon the lid to limit warpage of the electronic package. 1. A electronic package comprising:a carrier comprising a top surface and a bottom surface configured to be electrically connected to a system board;a semiconductor chip electrically connected to the top surface of the carrier;a lid attached to the top surface of the carrier that encloses semiconductor chip, the lid comprising a perimeter recess within the upper half of the lid, the perimeter recess comprising a horizontal recess and vertical recess comprising two recess sidewalls; anda lid-ring attached to the lid within the perimeter recess, the lid ring comprising a horizontal portion orthogonal and distally connected to a vertical portion, wherein the horizontal portion comprises a greater width than height, is parallel with the semiconductor chip, and is juxtaposed within the horizontal recess, wherein the vertical portion comprises a greater height than width and is juxtaposed between the two vertical recess sidewalls, wherein a perimeter sidewall of the lid-ring horizontal portion is coplanar with a perimeter sidewall of the lid, and wherein the lid-ring applies a contracting force against the upper half of the lid to exert a reverse bending moment upon the lid.2. The electronic package of claim 1 , wherein the lid is in thermal contact with the semiconductor chip.3. The electronic package of claim 1 , wherein a top surface of the lid and a top surface the lid-ring are coplanar.4. The electronic package of claim 1 , wherein the lid and the ...

Power circuit and power module using misfet having control circuit disposed between gate and source

The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q 1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q 4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG 1 ) connected between a first gate G 1 and a first source S 1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.

Electronic Component Package Structure and Electronic Device

An electronic component package structure and an electronic device where the electronic component package structure includes at least a substrate having a set attachment area for attaching an electronic component; a conductive lid having a top and a sidewall that extends toward the substrate, where one side of the sidewall close to the substrate has a bonding end, where the bonding end bonds the conductive lid to the substrate by using a non-conductive adhesive, and the conductive lid bonded to the substrate encloses the attachment area and forms a shielding space over the attachment area; and the non-conductive adhesive is located between the substrate and the bonding end, and has a dielectric constant not less than 7 and a coating thickness not greater than 0.07 millimeters (mm). With the present disclosure, an Electromagnetic Interference (EMI) shielding effect of the shielding space can be improved. 1. An electronic component package structure , comprising:a substrate;a conductive lid; anda non-conductive adhesive,wherein the substrate has a set attachment area for attaching an electronic component,wherein the conductive lid has a top and a sidewall that extend toward the substrate,wherein one side of the sidewall proximate to the substrate has a bonding end,wherein the bonding end bonds the conductive lid to the substrate using the non-conductive adhesive,wherein the conductive lid bonded to the substrate encloses the attachment area and forms a shielding space over the attachment area,wherein the non-conductive adhesive is located between the substrate and the bonding end,wherein the electronic component package structure further comprises a solder mask disposed on a surface of one side of the substrate facing the conductive lid, andwherein in the solder mask, a first open window is disposed in a position in which the non-conductive adhesive is disposed.2. The electronic component package structure according to claim 1 , wherein an air hole is disposed in the ...

Semiconductor package

A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

FINGERPRINT CHIP PACKAGE STRUCTURE, INPUT ASSEMBLY AND TERMINAL

The present disclosure provides a fingerprint chip package structure, an input assembly and a terminal. The fingerprint chip package structure includes a package body and a fingerprint identification chip. The package body includes a bottom surface and a lateral surface connected to the bottom surface, and defines a recessed portion at a junction of the bottom surface and the lateral surface. The fingerprint identification chip is received in the package body. 1. A fingerprint chip package structure , comprising:a package body having a bottom surface and a lateral surface connected to the bottom surface, wherein the package body defines a recessed portion at a junction of the bottom surface and the lateral surface; anda fingerprint identification chip received in the package body.2. The fingerprint chip package structure according to claim 1 , wherein the package body comprises a first package portion and a second package portion coupled to the first package portion claim 1 , the first package portion comprises the bottom surface claim 1 , and the second package portion comprises the lateral surface.3. The fingerprint chip package structure according to claim 2 , wherein the fingerprint identification chip is received in the first package portion.4. The fingerprint chip package structure according to claim 3 , wherein a shape and a size of the first package portion are matched with a shape and a size of the fingerprint identification chip.5. The fingerprint chip package structure according to claim 2 , wherein the first package portion has a rounded cuboid shape.6. The fingerprint chip package structure according to claim 2 , wherein the second package portion comprises a top surface connected to the lateral surface claim 2 , and the fingerprint chip package structure comprises a cover plate fixed on the top surface.7. The fingerprint chip package structure according to claim 6 , wherein the cover plate is fixed on the top surface through an adhesive.8. The ...

Integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion

An integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion of especial utility in conjunction with magnetoresistive random access memory (MRAM) and other devices requiring magnetic shielding.

MOLDED AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF

Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a base flange, retention posts integrally formed with the base flange and extending from the flange frontside in a direction opposite the flange backside, and retention tabs having openings through which the retention posts are received. A molded package body is bonded to the base flange and envelopes, at least in substantial part, the retention posts and the retention tabs. The molded air cavity package further includes package leads extending from the molded package body. In certain implementations, the package leads and the retention tabs comprise singulated portions of a leadframe. Additionally or alternatively, the retention posts may be staked or otherwise physically deformed in a manner preventing disengagement of the retention posts from the retention tabs along a centerline of the molded air cavity package. 1. A method for producing a molded air cavity package , the method comprising:providing a base flange having a flange frontside, a flange backside opposite the flange frontside as taken along a centerline of the molded air cavity package, and retention posts extending from the flange frontside in a direction opposite the flange backside;further providing a leadframe comprising retention tabs and package leads;positioning the base flange adjacent the leadframe such that the retention posts are received through openings provided in the retention tabs; andafter positioning the base flange adjacent the leadframe, forming a molded package body bonded to the base flange and enveloping, at least in substantial part, the retention posts and the retention tabs.2. The method of further comprising claim 1 , after forming the molded package body claim 1 , singulating the leadframe to electrically isolate the retention tabs and the package leads.3. The method of further comprising claim 1 , after positioning the base ...

POWER MODULE AND POWER CONVERSION SYSTEM INCLUDING SAME

A power module includes an upper substrate comprising a plurality of circuit pattern areas made of a metal and a dielectric area disposed between each of the plurality of circuit pattern areas; a lower substrate including a plurality of circuit pattern areas made of a metal and a dielectric area disposed between each of the plurality of circuit pattern areas; and a semiconductor element having an upper terminal and a lower terminal, the upper terminal and the lower terminal being bonded to a lower surface of the upper substrate and an upper surface of the lower substrate, respectively. 1. A power module comprising:an upper substrate comprising a plurality of circuit pattern areas made of a metal and a dielectric area disposed in at least one of areas between the plurality of circuit pattern areas;a lower substrate including a plurality of circuit pattern areas made of a metal and a dielectric area disposed in at least one of areas between the plurality of circuit pattern areas; anda semiconductor element having an upper terminal and a lower terminal, the upper terminal and the lower terminal being bonded to a lower surface of the upper substrate and an upper surface of the lower substrate, respectively.2. The power module of claim 1 , further comprisinga dielectric layer disposed between the upper substrate and the lower substrate, wherein the dielectric layer has an opening formed in an area in which the upper substrate and the lower substrate are electrically connected to each other or in an area in which the upper substrate and the semiconductor element are bonded.3. The power module of claim 2 , wherein the dielectric layer is coated on the upper surface of the lower substrate.4. The power module of claim 3 , wherein the dielectric layer has a conductive lead formed on the upper surface thereof and comprises at least one conductive via hole for electrically connecting the conductive lead and the semiconductor element.5. The power module of claim 1 , wherein the ...

3D Printed Hermetic Package Assembly and Method

A method is provided. The method includes one or more of removing existing ball bonds from an extracted die, placing the extracted die into a recess of a hermetic substrate, the extracted die having a centered orientation in the recess, and applying a side fill compound into the recess between the extracted die and the hermetic substrate. The method also includes 3D printing, by a 3D printer, a plurality of bond connections between die pads of the extracted die and first bond pads of the hermetic substrate in order to create a 3D printed die substrate, and 3D printing a hermetic encapsulation over the die, the side fill compound, and the 3D printed bond connections in order to create a hermetic assembly. The extracted die includes a fully functional semiconductor die removed from a previous package. The hermetic substrate includes the first bond pads coupled to second bond pads.

SEMICONDUCTOR DEVICE

This semiconductor device is provided with a device substrate in which a semiconductor circuit including two high frequency amplifiers; a cap substrate and a sealing frame of a conductor which forms and air-tightly seals space surrounding an area, in which the semiconductor circuit is formed, between the device substrate and the cap substrate, wherein the sealing frame is configured as a line of a 90-degree hybrid circuit or a line of a rat-race circuit. 1. A semiconductor device comprising a device substrate on which a semiconductor circuit including two high frequency amplifiers is formed , a cap substrate and a sealing frame of a conductor which forms and air-tightly seals space surrounding an area , in which the semiconductor circuit is formed , between the device substrate and the cap substrate ,wherein the sealing frame is configured as a line of a 90-degree hybrid circuit.25.-. (canceled)6. A semiconductor device comprising a device substrate on which a semiconductor circuit including two high frequency amplifiers , a cap substrate and a sealing frame of a conductor which forms and air-tightly seals space surrounding an area , in which the semiconductor circuit is formed , between the device substrate and the cap substrate ,wherein the sealing frame is configured as a line of a rat-race circuit.7. The semiconductor device according to wherein the sealing frame is configured as a circuit member of a divider.8. The semiconductor device according to wherein the sealing frame is configured as a circuit member of a combiner.9. The semiconductor device according to claim 1 , wherein a width of the sealing frame is not completely same.10. The semiconductor device according to claim 1 , wherein a port of a conductor constituted by a via part penetrating between a front surface and a back surface of the cap substrate is provided claim 1 , the port is electrically connected to the sealing frame and high frequency power is transmitted to the sealing frame via the port. ...

CASED ELECTRICAL COMPONENT

The invention relates to a cased electrical component comprising a carrier substrate (), a spring device (), which is arranged on the carrier substrate (), a chip (), which on a first side () of the chip is coupled to the spring device (), and a cover element (), which is arranged on the carrier substrate (). The cover element () is arranged over the chip () such that the cover element () is in contact with the chip () at least on a second side () of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings. 1. A method for producing a cased electrical component , comprising:providing a carrier substrate;arranging a spring device on the carrier substrate;arranging a chip on the spring device in such a way that a first side of the chip is coupled to the spring device; andarranging a covering element over the chip in such a way that the covering element touches the chip at least at a second side of the chip, the second side being different from the first side.2. The method according to claim 1 , wherein arranging the spring device on the carrier substrate comprises:sputtering and electrodepositing a first layer on the carrier substrate;sputtering and electrodepositing a second layer on an end section of the first layer and on a photoresist; andremoving the photoresist below the second layer.3. The method according to claim 2 , further comprising arranging a bearing element on the carrier substrate by:sputtering and electrodepositing a third layer on the carrier substrate; andmechanically post-processing the third layer in such a way that the third layer has a planar surface suitable for bearing for the chip.4. The method according to claim 3 , further comprising arranging the covering element on the carrier substrate by:laminating a film composed of a material composed of plastic over the chip and the carrier substrate; andsputtering and electrodepositing a fourth ...

Electronic element mounting substrate and electronic device

An electronic element mounting substrate according to the present disclosure includes a base body having a recessed portion including a mounting region on which an electronic element is mounted and a cutout section located on an outer periphery of the base body in a plane perspective, and a channel having an inner end portion located on an inner wall of the base body and an outer end portion located on the outer periphery of the base body. The inner end portion of the channel is open to the recessed portion, and the outer end portion of the channel is continuous with the cutout section.

POWER MODULE AND POWER CONVERSION APPARATUS

According to the present invention, a power module includes an insulating substrate, a semiconductor device provided on the insulating substrate, an internal terminal provided on the insulating substrate and electrically connected to the semiconductor device, a sealing material that seals the internal terminal, the semiconductor device and the insulating substrate so that an end portion of the internal terminal is exposed, a case that is separate from the sealing material and covers the sealing material and an elastic member that connects the case and the end portion of the internal terminal. 1. A power module comprising:an insulating substrate;a semiconductor device provided on the insulating substrate;an internal terminal provided on the insulating substrate and electrically connected to the semiconductor device;a sealing material that seals the internal terminal, the semiconductor device and the insulating substrate so that an end portion of the internal terminal is exposed;a case that is separate from the sealing material and covers the sealing material; andan elastic member that connects the case and the end portion of the internal terminal.2. The power module according to claim 1 , wherein the sealing material is in contact with the case.3. The power module according to claim 1 , wherein a concave portion into which the elastic member is inserted is provided at the end portion of the internal terminal.4. The power module according to claim 1 , wherein the elastic member is a multi-contact spring having a plurality of contacts.5. The power module according to claim 1 , further comprising an external terminal claim 1 , one end of which is electrically connected to the internal terminal via the elastic member and the other end of which is exposed from the case claim 1 ,wherein one end of a hole is provided on an inside surface of the case facing a side face of the sealing material, the other end of the hole is provided on a top surface of the case so as to ...

LIQUID COOLING OF SEMICONDUCTOR CHIPS UTILIZING SMALL SCALE STRUCTURES

A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds. 1. A semiconductor assembly including:a substrate member including a first chip and a top surface; anda cap member with a first recess formed therein, the cap member including a first recess surface and a first set of rigid small scale structure(s) extending from at least a portion of the first recess surface into the first recess, with the first recess surface and the first set of rigid small scale structure(s) defining the first recess;wherein:the first set of rigid small scale structure(s) include a structure having formed therein pores, gaps and or interstitial spaces equal to or less than 100 micrometers;the first set of rigid small scale structure(s) are sized, shaped and located to provide for appropriate fluid flow when gas and liquid are circulated through the first recess for gas-assisted direct liquid cooling; andthe cap member is attached to the top surface of the substrate member at a location such that circulation of gas and liquid through the first recess cools the first chip by gas-assisted direct liquid cooling.2. The assembly of wherein:the cap member includes an exterior surface that is generally opposite the first recess surface; andthe cap member has formed therein a first plurality of channels extending through the cap member from the first recess surface to the exterior surface of the cap member.3. The assembly of wherein:each channel of the first plurality of channels ...

Air-cavity package with enhanced package integration level and thermal performance

The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a top electronic component, and an external electronic component. The perimeter wall extends from a periphery of a lower side of the top substrate to a periphery of an upper side of the bottom substrate to form a cavity. The bottom electronic component is mounted on the upper side of the bottom substrate and exposed to the cavity. The top electronic component is mounted on the lower side of the top substrate and exposed to the cavity. And the external electronic component is mounted on an upper side of the top substrate, which is opposite the lower side of the top substrate and not exposed to the cavity.

AIR-CAVITY PACKAGE WITH DUAL SIGNAL-TRANSITION SIDES

The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, and a top electronic component. The bottom substrate includes a bottom signal via extending through the bottom substrate and the top substrate includes a top signal via extending through the top substrate. The perimeter wall extends between a periphery of the top substrate and a periphery of the bottom substrate to form a cavity. The bottom electronic component is mounted on the bottom substrate, exposed to the cavity, and electrically coupled to the bottom signal via. The top electronic component is mounted on the top substrate, exposed to the cavity, and electrically coupled to the top signal via. 1. An apparatus comprising:a bottom substrate comprising a bottom substrate body having an upper side and a lower side, at least one first bottom metal structure on the upper side of the bottom substrate body, at least one second bottom metal structure on the lower side of the bottom substrate body, and at least one bottom signal via that extends from the upper side of the bottom substrate body through the bottom substrate body to the lower side of the bottom substrate body and is electrically coupled to the at least one second bottom metal structure;a top substrate comprising a top substrate body having an upper side and a lower side, at least one first top metal structure on the upper side of the top substrate body, at least one second top metal structure on the lower side of the top substrate body, and at least one top signal via that extends from the upper side of the top substrate body through the top substrate body to the lower side of the top substrate body and is electrically coupled to the at least one first top metal structure;a perimeter wall extending from a periphery of the lower side of the top substrate body to a periphery of the upper side of the bottom substrate body such that a cavity is defined by ...

POWER ELECTRONIC SUBMODULE COMPRISING A BIPARTITE HOUSING

A submodule comprising: a substrate, a power semiconductor component, a connection device, a terminal device and an insulating body. The substrate has conductor tracks electrically insulated from one another, and the component is electrically conductively connected to a track. The connection device is a film composite with a first surface facing the component and the substrate and an opposed second surface. The insulating body has: a first partial body, connected to an edge of the substrate, a first cutout for a terminal, a second partial body, embodied as a pressure body and a second cutout, with a pressure element projecting therefrom. The second partial body is movable relative to the first partial body in the direction of the substrate to press with the pressure element onto a section of the second surface. The section is within the area of the component in projection along the direction of the normal thereto. 1. Power electronic submodule comprising:a substrate having conductor tracks electrically insulated from one another and an edge;a power semiconductor component arranged on one of said conductor tracks and electrically conductively connected thereto;a connection device internally connecting the submodule in a circuit-conforming manner said connection device being embodied as a film composite having an electrically conductive film and an electrically insulating film, and thus having a first main surface which faces said power semiconductor component and said substrate, and a second main surface opposite said first main surface, said second main surface of said film composite having a section which is arranged within an area of said power semiconductor component in projection along the direction of the normal to the power semiconductor component;a terminal device; a first partial body, which is connected to said edge of said substrate, said insulating material body also having a first cutout sized to receive said terminal device; and', 'a second partial body ...

SEMI-HERMETIC SEMICONDUCTOR PACKAGE

A method of assembling a semi-hermetic semiconductor package includes bonding a semiconductor die having bond pads to a top side of a base region of a package substrate having vertical side walls that are hollow which define an inner open volume (gap) having an adhesive or thermoplastic material therein. There are a plurality of metal terminals providing top terminal contacts on the top side of the base region and bottom terminal contacts on a bottom side or below the base region. The bond pads are coupled to the top terminal contacts. A lid is placed which provides a top for the semiconductor package, where the lid extends to vertically oriented end protrusions so that the protrusions are positioned within the adhesive or thermoplastic material to secure the protrusions within the adhesive or thermoplastic material to provide a seal for the semiconductor package. 1. A semiconductor packaged device (semiconductor package) , comprising:a package substrate comprising a dielectric material including a base region and vertical side walls that are hollow defining an inner open volume (gap);a plurality of metal terminals providing top terminal contacts on a top side of said base region and bottom terminal contacts on a bottom side of said base region;a semiconductor die having bond pads attached to said top side of said base region;wherein said bond pads are coupled to said top terminal contacts;an adhesive or thermoplastic material within said gap, anda lid providing a top for said semiconductor package extending to vertically oriented end protrusions (vertical protrusions) within said adhesive or thermoplastic material to provide a seal for said semiconductor package.2. The semiconductor package of claim 1 , wherein said lid comprises a metal or glass and said adhesive or thermoplastic material comprises an epoxy.3. The semiconductor package of claim 1 , wherein said dielectric material comprise a ceramic claim 1 , further comprising metal traces connecting said top ...