СОХРАНЕНИЕ ПЕРЕРАСПРЕДЕЛЯЮЩИХ ТОКОПРОВОДЯЩИХ ДОРОЖЕК, ИМЕЮЩИХ МЕЛКИЙ ШАГ

Один вариант воплощения изобретения включает в себя полупроводниковый аппарат, содержащий перераспределяющий слой (RDL-слой), включающий в себя рельефную токопроводящую дорожку перераспределяющего слоя, имеющую две боковые стенки перераспределяющего слоя, причем перераспределяющий слой, содержащий материал, выбранный из группы, содержащей Cu (медь) и Au (золото), защитные боковые стенки, непосредственно контактирующие с этими двумя боковыми стенками перераспределяющего слоя, затравочный слой, включающий в себя этот материал, и барьерный слой, при этом (а) токопроводящая дорожка перераспределяющего слоя имеет ширину токопроводящей дорожки перераспределяющего слоя, ортогональную по отношению к этим двум боковым стенками перераспределяющего слоя и простирающуюся между ними, и (b) затравочный и барьерный слои каждый включают в себя ширину, параллельную ширине токопроводящей дорожки перераспределяющего слоя и более широкую, чем эта ширина. Здесь же представлены и другие варианты воплощения изобретения ...

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

HALBLEITERBAUELEMENT MIT METALLKONTAKTEN AUS GOLD ODER EINER GOLDLEGIERUNG UND VERFAHREN ZU SEINER HERSTELLUNG

DIE-GEHÄUSE UND VERFAHREN ZUM BILDEN EINES DIE-GEHÄUSES

Ein Die-Gehäuse ist bereitgestellt. Das Die-Gehäuse kann Folgendes beinhalten: einen Die mit einem ersten Die-Kontakt auf einer ersten Seite des Die und einem zweiten Die-Kontakt auf einer zweiten Seite des Die, die der ersten Seite des Die gegenüberliegt, ein Isolationsmaterial, das lateral dem Die benachbart ist, eine Metallstruktur, die die gesamte Oberfläche des zweiten Die-Kontakts des Die im Wesentlichen direkt kontaktiert, wobei die Metallstruktur aus dem gleichen Material wie der zweite Die-Kontakt gefertigt ist, einen ersten Padkontakt auf der ersten Seite des Die, der den ersten Die-Kontakt elektrisch kontaktiert, und einen zweiten Padkontakt auf der ersten Seite des Die, der den zweiten Die-Kontakt über die Metallstruktur elektrisch kontaktiert, wobei das Isolationsmaterial die Metallstruktur elektrisch von dem ersten Die-Kontakt isoliert.

Electrolytically formed mask - for semi conductor contact vapour deposition

Mask for the generation of projection for contactor purposes on semiconductors or semiconductor construction elements has conical openings, the generatrix of which form an angle of 5 to 20 degrees, pref. 12 degrees, with the vertical to the plane of the mask. Also, the openings of the mask have a cross section conforming to the contact window of the semiconductor construction element. In the prefd. method the mask is made by the deposition of an electrolytic Cu, Ni or Ag film round photo chemically protruded hole section attached to a steel base plate. The mask is 115 mu thick.

Improvements in semiconductor devices

... 945,249. Semi-conductor devices. GENERAL ELECTRIC CO. Sept. 6, 1960 [Sept. 8, 1959], No. 30695/60. Heading H1K. A multi-layer semi-conductor device comprises at least two over-lapping NPN and PNP transistor units, a first ohmic electrode being connected to one terminal zone and a second ohmic electrode connected across the PN junction of the other terminal zone and its adjacent zone. Fig. 1 shows an NPNP arrangement with electrode 13 ohmically connected to P-zone 4 and electrode 12 ohmically connected to both N-zone 6 and P-zone 5 so that it shortcircuits the PN junction J E1 . The central PN junction J c between P-zone 5 and N-zone 3 behaves as a collector while the other two PN junctions J E1 and J E2 operate as emitters. If electrode 13 is biased negatively, the reversed biased junction J E2 breaks down at voltage 20, as shown, by the third quadrant characteristic in Fig. 2. If electrode 13 is biased positively, junctions J E2 and J E1 (partially) are biased forward and junction J E ...

Improvements in or relating to semiconductor amplifier

... 999,191. Semi-conductor devices. WESTINGHOUSE ELECTRIC CORPORATION. Aug. 19, 1963 [Aug. 31, 1962], No. 32675/63. Heading H1K. A semi-conductor device is formed of a semi-conductor wafer having a base region of one conductivity type and at least two groups of electrodes on one major surface thereof, each group including at least one electrode in rectifying contact with the base region and one electrode in either rectifying or non-rectifying contact with the base region, and a common electrode disposed at the opposite surface of the wafer, so as to provide the equivalent of two transistors. The two groups are symmetrically placed about the centre of the wafer to ensure identical electrical characteristics. In one embodiment a boron-doped silicon wafer 10 is placed on a gold-antimony alloy foil C and gold-boron alloy foil members, for the contacts B, E, are placed on the upper surface of the wafer. The assembly is then heated to fuse the foils to the wafer, as a result of which electrodes ...

Electric circuit devices utilizing semiconductive materials

... 694,023. Semi-conductor amplifiers. WESTERN ELECTRIC CO., Inc. Feb. 25, 1949 [Feb. 26, 1948; Feb. 26, 1948], Nos. 5203/49 and 5204/49. Class 40 (iv). An electric signal translating device comprises a thin layer of semi-conductor having spaced connections between which a current is passed longitudinally through the layer, and a control electrode, which may comprise an electrolyte, situated so as to apply an electric field to the layer to control its conductivity. Various forms of semi-conductor amplifying arrangements are described. In Fig. 1, a positively-biased source electrode 5, consisting of a rectifier point contact, is placed in contact with a surface layer 2 of N-type silicon provided on a block 1 of P-type silicon material. A high resistance barrier 3 separates the P- and N-types of material. A low resistance contact is pro. vided by a metal film 4 on the block 1, the load circuit RL being connected between electrodes 5 and 4. A control electrode 7 consisting of a metal ring is ...

Improvements in or relating to methods of providing separated metal layers side by side on a support

... 1,081,472. Etching. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. April 15, 1965 [April 21, 1964], No. 16247/65. Heading B6J. [Also in Division H1] A first metal layer is applied to a support, an etching resist mask is applied to the layer, the metal is etched away where unmasked and also to a small distance beneath the mask by undercoating, and a second metal layer is deposited on the support where unmasked, so that the two metal layers are separated by a gap at the position of the undercut. A monocrystal germanium body 1, Fig. 1, of antimony-doped N- type material 2 has formed on its upper and under sides a P-type layer 3 by diffusion of indium. The upper side is covered with a resist lacquer and the P-type layer removed from the under surface by etching. The lacquer is removed, and arsenic diffused to form an N-type layer 4 on the upper side. An N-type layer of reduced resistivity is also formed on the under side. A thin silver layer 5 is deposited on the layer 4. An etch-resist lacquer ...

IMPROVEMENTS IN OR RELATING TO BARRIER LAYER DEVICES

... 1291449 Semi-conductor devices WESTERN ELECTRIC CO Inc 21 Nov 1969 [22 Nov 1968] 56972/69 Heading H1K The disclosure of this Specification is identical to that of Specification 1,291,448 but the claims relate to a Si device including an insulating guard ring provided around and defining the periphery of a planar metal-Si or metal silicide-Si rectifying barrier, and extending into the semi-conductor substrate of the device beyond the depth of the rectifying barrier, the guard ring having been formed by chemical conversion of Si to its compound with oxygen, nitrogen or carbon or a combination thereof.

Semiconductor signal translating devices

... 1,100,708. Semi - conductor devices. WESTERN ELECTRIC CO. Inc. 17 June, 1965 [23 June, 1964], No. 25617/65. Heading HlK. In a device having a metal-to-semi -conductor rectifying junction, the metal layer consists of two different metals in contact with each other, both contacting a surface of the semi-conductor. The metal having the lower barrier potential defines the effective junction and the other metal provides a contact area for an electrode lead. In Fig. 1, an N-type silicon wafer 11 has been provided-eg. by vapour phase deposition through a surface oxide mask-with an annular deposit 12 of platinum which may, but need not, be alloyed to the silicon. The platinum serves as a mask for deposition of a circular layer 13 of tungsten inside the platinum annulus. An electrode lead 14 is attached, e.g. by thermocompression bonding, to the platinum and an ohmic contact 15 is made to the opposite face of the wafer, thus completing a diode in which the metal electrode connection is to the platinum ...

Semiconductor device

... 983,146. Semi - conductor devices. STANDARD TELEPHONES & CABLES Ltd. Aug. 25, 1961 [Aug. 30, 1960], No. 29818/60. Heading H1K. Semi-conductor devices include an effectively non - conducting support having a planar surface on which are two sideby - side semi - conductor layers of opposite conductivity type arranged in edge to edge contact to form a PN junction between them, the width of the junction being less than that of the support in the junction region. The embodiments described make use of a high resistivity intrinsic semi-conductor material such as silicon as the effectively non-conducting support but the use of ceramics and other materials is envisaged. In constructing semi-conductor diodes P and N-type layers 2 and 3 are formed on a disc 1 of high resistivity silicon (Fig. 2) either by solid state diffusion or by a deposition process such as epitoxial growth. Strips which are to form separate diodes are cut from the disc and portions of the doped layers are removed to expose parts ...

Techniques for enhancing fracture resistance of interconnects

SEMICONDUCTOR SWITCHING DEVICE HAVING A SHORTED EMITTER

... 1,242,898. Semi-conductor controlled rectifiers. GENERAL ELECTRIC CO. 7 Oct., 1968 [12 Oct., 1967], No. 47483/68. Heading H1K. In a shorted-emitter semi-conductor controlled rectifier part of the emitter region which is free of the emitter contact bears a separate control electrode. In the embodiment, Fig. 1, the emitter region 15 is apertured and the emitter electrode 17 extends over the entire region including the apertures save for a sector B of reduced thickness which carries aluminium wire control electrode 18. The emitter electrode short circuits the emitter region to adjacent region 14 via the apertures 142 and around its entire periphery. It may consist of evaporated aluminium, electroplated tungsten, or sputtered copper or gold.

METHOD OF MAKING BARRIER LAYER DEVICES AND DEVICES SO MADE

... 1291450 Semi-conductor devices WESTERN ELECTRIC CO Inc 21 Nov 1969 [22 Nov 1968] 56973/69 Heading H1K An insulating guard ring 12 defining the periphery of a planar rectifying barrier in a semiconductor device is formed by bombardment with ions to a depth beyond that of the rectifying barrier so as to convert the bombarded semi-conductor material to insulating material. Suitable ions for use with Si, Ga or III-V compounds are oxygen, nitrogen, carbon or mixtures thereof. The barrier may be a metal/ semi-conductor contact (e.g. Al on Si, Pd on Ge or Au on GaAs) or a contact between Si and a silicide of a metal such as Ni, Ti, Zr, Hf or a Pt-group metal, where the silicide is produced by heating after depositing a layer of the appropriate metal. In the latter case a localized area of the silicide (52), Fig. 5 (not shown), is then covered by a masking layer (54) of metal such as Al, Ti, Zr, Pt-Ti-Au or Cr-Au, and the entire surface is subjected to bombardment, e.g. with oxygen ions, to form ...

Semiconductor device

... 877,071. Semi-conductor devices. CLEVITE CORPORATION. Sept. 1, 1959 [Sept. 4, 1958], No. 29783/59. Class 37. A semi-conductor device comprises a body 12, Fig. 3, of semi-conductive material having at least two PN junctions 18, 20; 26, 28, arranged in pairs on each of its major surfaces, terminal connections 36, 38 for one pair of junctions 14, 22, resistances 32, 34 or resistive impedance means such as diodes, preferably semi-conductive junction diodes, Fig. 4 (not shown), interconnecting the junctions on each major surface, and a base electrode 30 making non-rectifying contact with the body 12. The semi-conductor device is symmetrical, i.e. the opposing junctions have the same area and same shape. The operation however is non-symmetrical because the resistance 32, say, causes 16 to be less effective as an emitter than 14 while the whole of 22, 24 are effective as collectors. The junctions may be annular and disc-shaped respectively, as shown, or quadrangular and rectangular respectively ...

Improvements in or relating to semiconductor devices

... 1,046,187. Semi-conductor devices. STANDARD TELEPHONES & CABLES Ltd. Aug. 6, 1965 [Sept. 2, 1964], No. 35926/64. Heading H1K. A method of manufacturing a semi-conductor junction device, such as a tunnel diode, includes the steps of providing a layer of semi-conductor material of one conductivity type on part of a face of an effectively insulating base, providing an electrically conducting layer on another part of the face spaced from the semi-conductor layer, placing a pellet of impurity material of opposite conductivity type in the space with the pellet in contact with both layers, and heating so that the impurity material is alloyed with the semiconductor layer, to form a junction therein, and also with the conducting layer, to form an ohmic connection therewith. A base 1 of semiinsulating gallium arsenide has a layer 2 of P+ germanium epitaxially deposited on one face. Part of the layer is then removed and gold layers 3a, 3b are evaporated over the stepped surface except over areas 4 ...

Procedure for manufacturing electrically isolated contact contacts consisting of aluminum

Procedure for manufacturing a well responsible layer of metal on the surface of a disk

Procedure for making a layer of metal of several metallic films on surfaces of semiconductor components

PROCEDURE FOR MANUFACTURING KLEINFLACHIGEN THYRISTORS

Gunn effect device

METHOD OF PRODUCING THICK SCHOTTKY-BARRIER CONTACTS

MILLIMETER WAVE SEMICONDUCTOR DEVICE

MILLIMETER WAVE SEMICONDUCTOR DEVICE A mesa semiconductor device, including a metal film conductor located on the upper surface of the device about the base of the mesa to reduce skin effect loss.

METHOD OF PRODUCING THICK SCHOTTKY-BARRIER CONTACTS

In einer elektrischen Schaltung angeordnetes Verstärkungselement.

Halbleiterelement zur Verstärkung elektrischer Signale.

Legierungstransistor für hohe Frequenzen

Halbleitergerät

Verfahren zur Herstellung von Halbleiterbauelementen, bei dem homogene Metallschichten auf Halbleiterkristalle aufgebracht werden

Halbleitervorrichtung

Verfahren zum Erzeugen mindestens zweier benachbarter Elektroden auf einem Halbleiterkörper

Halbleiteranordnung

Halbleiteranordnung für Schaltzwecke

Verfahren zur Herstellung einer Halbleiteranordnung

Verfahren zur Herstellung von Halbleiter-Vorrichtungen

Verfahren zur Herstellung von Halbleitervorrichtungen, insbesondere von Tunneldioden

Halbleiterbauelement mit steuerbarer Rekombination von in einem eigenleitenden Bereich vorhandenen Elektronen und Defektelektronen

Verfahren zum Herstellen von kleinflächigen Halbleiterbauelementen

Verfahren zum Herstellen von elektrisch isolierten, aus Aluminium bestehenden Anschlüssen oder Verbindungen

Verfahren zur Herstellung eines Halbleiterelementes mit pnpn-Struktur mit Kurzschlüssen in der Emitterzone

Steuerbares Gleichrichterelement mit einem im wesentlichen einkristallinen Halbleiterkörper mit pnpn-Schichtenfolge

HALBLEITERANORDNUNG.

Halbleiterbauelement mit Aluminiumkontakt

Verfahren zur gleichzeitigen Herstellung mehrerer Halbleiterschaltelemente und gemäss diesem Verfahren hergestellte Halbleiterschaltelemente

Verfahren zur Herstellung einer Halbleitervorrichtung

Dünnschichtiges aktives Festkörperelement

Verfahren zum Herstellen einer Halbleiteranordnung

Elektrisch schalterartig steuerbare Halbleiteranordnung

Verfahren zur Herstellung dünnschichtiger Gitterstrukturen

Mesa-Transistor, insbesondere Germanium-Mesa-Transistor

Procédé de fabrication d'un élément semi-conducteur à résistance inverse contrôlée et élément semi-conducteur obtenu par la mise en oeuvre de ce procédé

Flächentransistor

Transistor mit Mesa- oder Planaraufbau

Verfahren zum Herstellen von elektrischen Bauelementen oder Baugruppen

Gesteuerter Gleichrichter und Verfahren zu dessen Herstellung

Halbleitervorrichtung zum Detektieren und/oder Messen von Strahlung

Feldeffekt-Transistor und Verfahren zur Herstellung eines solchen Transistors

Halbleiteranordnung mit vier Schichten von abwechselnd gegensätzlichem Leitfähigkeitstyp

Verfahren zum Herstellen einer gut haftenden, kontaktierbaren, aus Chrom oder Molybdän bestehenden Metallisierung auf Oberflächen von elektrischen Bauelementen

Verfahren zum Herstellen eines Halbleitergleichrichters und nach diesem Verfahren hergestellter Halbleitergleichrichter

Sperrschicht-Halbleitervorrichtung

Schottkydiode mit Schutzring

Verfahren zur Herstellung von Halbleitervorrichtungen

Halbleiteranordnung mit mindestens einer Gunn-Effekt-Vorrichtung

Steuerbares Gleichrichterelement

Richtkopplungsanordnung

Verfahren zum Aufbringen von nebeneinander liegenden, durch einen Zwischenraum voneinander getrennten Metallschichten auf eine Unterlage und nach diesem Verfahren auf einer Unterlage hergestellte Metallschichten

Halbleitervorrichtung zum Nachweisen und/oder Messen von Strahlung

Verfahren zum Herstellen eines Transistors

Verfahren zur Herstellung eines Halbleiterbauelementes mit mindestens zwei pn-Übergängen

Mit einer gut lötbaren Kontaktelektrode versehene Halbleiteranordnung und Verfahren zu ihrer Herstellung

Semiconductor device

using element of active circuit of the thin films

Process for manufacture of a ordered element with semiconductor, stucture pnpn, with short-circuits in the zone of the transmitter

Process for the manufacture of a device with asymmetrical conductibility

Ordered rectifying element comprising an in theory single-crystal semiconductor with a succession of pn-pn layers

STRUCTURE D'ELECTRODES POUR DISPOSITIFS SEMI-CONDUCTEURS

L'INVENTION SE RAPPORTE A UNE STRUCTURE D'ELECTRODES A UTILISER DANS DES DISPOSITIFS SEMI-CONDUCTEURS. SELON L'INVENTION, ELLE COMPREND UNE COUCHE 20 DE SEMI-CONDUCTEUR, UNE COUCHE CONDUCTRICE 23 DISPOSEE SUR UNE SURFACE DE LA COUCHE 20, DES PREMIERES REGIONS 22 ENTRE LES COUCHES 20 ET 23 ET JOUANT LE ROLE DE PASSAGES PRINCIPAUX POUR LA TRANSMISSION DES PORTEURS MINORITAIRES DE LA COUCHE 20 A LA COUCHE 23; ET DES SECONDES REGIONS 21 ENTRE LES COUCHES 20 ET 23 ET JOUANT LE ROLE DE PASSAGES PRINCIPAUX POUR LE TRANSFERT DE PORTEURS MAJORITAIRES ENTRE ELLES, LES PREMIERES ET SECONDES REGIONS ETANT SELECTIVEMENT FORMEES SUR LA COUCHE 20, AFIN D'ETRE ADJACENTES LES UNES AUX AUTRES ET DE SE TROUVER PARALLELES AUX TRAJETS ELECTRIQUES. L'INVENTION S'APPLIQUE NOTAMMENT A LA FORMATION DE DIODES, THYRISTORS ET TRANSISTORS.

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

METHOD OF MANUFACTURING A SEMICONDUCTOR ELEMENT

MANUFACTORING PROCESS OF FIELD-EFFECT TRANSISTORS AND TRANSISTORS THUS OBTAINED

SMALL POWER DEVICE MODULE AND MANUFACTURING METHOD THEREOF

Provided are a small power module that can be more miniaturized and optimized for integration and a method of manufacturing the same. The small power module according to the present invention includes a first substrate including a first lower circuit line layer, a first insulating layer, and a first upper circuit line layer; a first power device layer comprising at least one first power device on the first substrate; a second substrate including a second lower circuit line layer on the first power device, a second insulating layer, and a second upper circuit line layer; and a second power device layer comprising at least one second power device on the second substrate. COPYRIGHT KIPO 2017 ...

ELECTRONIC COMPONENT PACKAGE AND MANUFACTURING METHOD THEREOF

The present disclosure relates to an electronic component package and a manufacturing method thereof. The electronic component package comprises: a frame having a through hole; an electronic component disposed in the through hole of the frame; and a re-distribution section disposed on one side of the frame and the electronic component, wherein at least one first wiring layer electrically connected to the electronic component is disposed inside the frame through the re-distribution section. COPYRIGHT KIPO 2016 ...

Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same

Preparation method of semiconductor device, and semiconductor device

Method of forming semiconductor structure

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Package structure and manufacture method thereof

A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps. A manufacturing method of the package structure is also provided.

Semiconductor devices and fabrication method thereof

CIRCUIT CHIP COMPRISING A SPECIFIC CONNECTION AREA CONFIGURATION

L'invention concerne une puce de connexion comprenant un substrat semi-conducteur (2) avec une face avant et une face arrière. Un circuit intégré (4) comportant une pluralité de composants est défini dans la face avant du substrat semi-conducteur (2). Le circuit intégré (4) comprend deux connexions servant à l'injection ou à l'éjection de signaux, qui sont permutables sans que cela n'altère la fonction du circuit intégré (4). La puce de connexion ne présente que deux faces de connexion (10, 12) dont une (10) se situe sur la face avant du substrat semi-conducteur (2) et l'autre (12), sur la face arrière dudit substrat. Chacune de ces surfaces de connexion est reliée à une des connexions permutables.

SEMICONDUCTOR SWITCHING DEVICE HAVING A SHORTED EMITTER

Method of manufacturing a semi-conductor target for a camera tube having a mosaic of p-n junctions covered by a perforated conductive layer

A camera employing a semi-conductor target positioned to be scanned by an electron beam. The target comprises a wafer of semi-conductive material of a particular conductivity type, e.g. n-type silicon. A plurality of islands separated by grooves project from the wafer on the side exposed to the electron beam. These islands are of opposite conductivity and form with the wafer rectifying junctions. On the exposed surface of each island is a metal layer which is separated from the semi-conductive material of the island by an insulating layer having an aperture therein.

Mold type semiconductor device and method for manufacturing the same

A mold type semiconductor device includes a semiconductor chip including a semiconductor part; a metallic layer; a solder layer; and a metallic member connecting to the semiconductor chip through the metallic layer and the solder layer. The solder layer is made of solder having yield stress smaller than that of the metallic layer. Even when the semiconductor chip is sealed with a resin mold, the metallic layer is prevented from cracking.

Supporting InFO Packages to Reduce Warpage

A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.

Semiconductor package with antenna

A semiconductor package includes a substrate, a plurality of pin pads, a radio frequency (RF) pad, a semiconductor component, at least one surface mount device (SMD) component, a mold compound, a printed circuit board (PCB) antenna and a conductive solder. The RF pad is used to receive or transmit an RF signal on the top side of the substrate. The SMD component is mounted on the RF pad. The mold compound on the top side of the substrate covers the semiconductor component and the SMD component. The PCB antenna is located on the mold compound. Wherein, the conductive solder and the SMD component are stacked between the RF pad and a feeding structure of the PCB antenna.

Formation of conductive connection tracks in package mold body using electroless plating

A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.

Halbleitervorrichtung

Control device of semiconductor device

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

Vertical electrode structure using trench and method for fabricating the vertical electrode structure

Provided is a vertical electrode structure using a trench and a method of manufacturing the vertical electrode structure. The method of forming a vertical electrode structure using a trench includes steps of: forming the trench on a predetermined region of a semiconductor substrate; and forming electrode layers in predetermined regions of inner and outer portions of the trench. In this manner, the electrode deposition in the vertical direction is established by using the trench, so that it is possible to form a deposited electrode having a size of several hundred nm or less by a short processing time and a low processing cost.

Semiconductor device

A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors.

Distributed Metal Routing

A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Ohmic connection using widened connection zones in a portable electronic object

The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects.

Thermally and dimensionally stable polyimide films and methods relating thereto

The present disclosure is directed to a polyimide film. The film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Coverlay compositions and methods relating thereto

The present disclosure is directed to a coverlay comprising a polyimide film and an adhesive layer. The polyimide film is composed of a polyimide and a sub-micron filler. The polyimide is derived from at least one aromatic dianhydride component selected from rigid rod dianhydride, non-rigid rod dianhydride and combinations thereof, and at least one aromatic diamine component selected from rigid rod diamine, non-rigid rod diamine and combinations thereof. The mole ratio of dianhydride to diamine is 48-52:52-48 and the ratio of X:Y is 20-80:80-20 where X is the mole percent of rigid rod dianhydride and rigid rod diamine, and Y is the mole percent of non-rigid rod dianhydride and non-rigid rod diamine. The sub-micron filler is less than 550 nanometers in at least one dimension; has an aspect ratio greater than 3:1; is less than the thickness of the film in all dimensions.

Magnetic integration double-ended converter

The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.

Semiconductor device

A semiconductor device includes: a main body chip; a circuit pattern on a front surface of the main body chip and including a first pad; a cap chip including a first recess in a front surface of the cap chip and a second recess in a back surface of the cap chip, the cap chip being joined to the main body chip with the first recess facing the circuit pattern; a second pad on a bottom surface of the first recess of the cap chip; a first metallic member inlaid in the second recess of the cap chip; a first through electrode electrically connecting the second pad to the first metallic member through the cap chip; and a bump electrically connecting the first pad to the second pad.

Scalable Construction for Lateral Semiconductor Components having High Current-Carrying Capacity

The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode ( 203 ), a plurality of source fields ( 201 ) and a plurality of drain fields ( 202 ). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field ( 206 ) and/or a drain contact field ( 207 ). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate. The method according to the invention for producing a transistor comprises the following steps: providing a substrate; forming a plurality of transistor cells on the substrate, each of which comprises a control electrode, a plurality of source fields and a plurality of drain fields; conductively connecting the control electrodes to each other; forming a source contact field and/or a drain contact field in each transistor cell; conductively connecting the source contact fields

Power semiconductor device

A power semiconductor device and a manufacturing method thereof are provided. The power semiconductor device includes an anode electrode including an anode electrode pad, electrode bus lines connected to a first side and a second side on the anode electrode pad, the electrode bus lines each having a decreasing width in a direction away from the anode electrode pad, and pluralities of first anode electrode fingers and second anode electrode fingers connected with a third side and a fourth side on the anode electrode pad and with both sides of the electrode bus line, a cathode electrode including a first cathode electrode pad and a second cathode electrode pad, a plurality of cathode electrode fingers connected with the first cathode electrode pad, and a plurality of second cathode electrode fingers connected with the second cathode electrode pad, and an insulation layer disposed at an external portion of the anode.

Semiconductor device and method for manufacturing the same

An element using a semiconductor layer is formed between wiring layers and, at the same time, a gate electrode is formed using a conductive material other than a material for wirings. A first wiring is embedded in a surface of a first wiring layer. A gate electrode is formed over the first wiring. The gate electrode is coupled to the first wiring. The gate electrode is formed by a process different from a process for the first wiring. Therefore, the gate electrode can be formed using a material other than a material for the first wiring. Further, a gate insulating film and a semiconductor layer are formed over the gate electrode.

Multiple die in a face down package

A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Semiconductor device and method for manufacturing the same

A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.

Semiconductor device

A semiconductor device is free from degradation of characteristics attributable to a manufacturing process thereof and its characteristics are hardly affected by changes in electric potentials of bonding pads. The semiconductor device 10 includes an active region 12 , a first insulating layer 13 covering the active region 12 , a floating conductor 14 formed on the first insulating layer 13 , a second insulating layer 15 formed on the first insulating layer 13 and the floating conductor 14 , a bonding pad 18 formed on the second insulating layer 17 and interconnection vias 19, 20 for electrically connecting the active region 12 and the bonding pad 18.

SUBSTRATE COMPRISING A TRANSPARENT CONDUCTIVE OXIDE FILM AND ITS MANUFACTURING PROCESS

The invention relates to a substrate comprising at least one scattering film made of a transparent conductive oxide (TCO) and to a process for manufacturing such a substrate. It also relates to a solar cell comprising such a substrate. The substrate according to the invention comprises a layer of spherical particles made of a material chosen from dielectric and transparent conductive oxides, the layer being coated with a TCO film and the diameters of said spherical particles belonging to at least two populations of different diameters. The invention is applicable in particular to solar cells. 1. A substrate comprising:a first TCO scattering layer of a transparent conductive oxide deposited on a surface of a support,a layer of spherical particles of a material selected from the group consisting of a dielectric material and a transparent conductive oxide,whereinthe spherical particles have at least two populations of different diameters,the layer of spherical particles is positioned under the first TCO scattering layer, andthe first TCO scattering layer has a substantially constant thickness.2. The substrate as of claim 1 , further comprising claim 1 , between the support and the layer of spherical particles claim 1 , a second TCO layer of a transparent conductive oxide that is identical to claim 1 , or different from claim 1 , the transparent conductive oxide forming the first TCO scattering layer.3. The substrate of claim 2 , wherein the first and second TCO layers coat the layer of spherical particles.4. The substrate as of claim 1 , wherein the support is made of a material selected from the group consisting of a glass claim 1 , a p-doped silicon claim 1 , a n-doped silicon claim 1 , a hydrogenated amorphous silicon (a-Si:H) claim 1 , a Cu(In claim 1 , Ga)Se claim 1 , a single-crystal silicon or polysilicon claim 1 , a CdS claim 1 , and a layer of an organic cell.5. The substrate of claim 1 , wherein the spherical particles have a diameter of between 300 nm and 10 ...

SEMICONDUCTOR DEVICE USING COMPOSITION FOR ANISOTROPIC CONDUCTIVE ADHESIVE FILM OR ANISOTROPIC CONDUCTIVE ADHESIVE FILM

A semiconductor device bonded by an anisotropic conductive adhesive composition, the anisotropic conductive adhesive composition having a solid content ratio between a polymer binder system and a curing system of about 40:60 to about 60:40, and a coefficient of thermal expansion of about 150 ppm/° C. or less at about 100° C. or less. 1. A semiconductor device bonded by an anisotropic conductive adhesive composition , the anisotropic conductive adhesive composition having:a solid content ratio between a polymer binder system and a curing system of about 40:60 to about 60:40, anda coefficient of thermal expansion of about 150 ppm/° C. or less at about 100° C. or less.2. The semiconductor device as claimed in claim 1 , wherein the polymer binder system comprises an acrylic acid ester copolymer claim 1 , and the curing system comprises a bisphenol fluorene diacrylate and an isocyanuric acid ethylene oxide modified diacrylate.3. The semiconductor device as claimed in claim 2 , wherein a total amount of the bisphenol fluorene diacrylate and the isocyanuric acid ethylene oxide modified diacrylate is about 25 to about 50 wt % based on a total amount of the anisotropic conductive adhesive composition in terms of solid content.4. A semiconductor device bonded by an anisotropic conductive adhesive composition claim 2 , the anisotropic conductive adhesive composition comprising:an acrylic acid ester copolymer;at least one selected from the group of a styrene-acrylonitrile resin, an acrylonitrile butadiene rubber, a urethane acrylate resin, an ester urethane resin, and a urethane resin other than the urethane acrylate resin and the ester urethane resin;an isocyanuric acid ethylene oxide modified diacrylate; anda bisphenol fluorene diacrylate.5. The semiconductor device as claimed in claim 4 , wherein the styrene-acrylonitrile resin claim 4 , the acrylonitrile butadiene rubber claim 4 , the urethane acrylate resin claim 4 , the ester urethane resin and the urethane resin other ...

METHOD TO FABRICATE HIGH PERFORMANCE CARBON NANOTUBE TRANSISTOR INTEGRATED CIRCUITS BY THREE-DIMENSIONAL INTEGRATION TECHNOLOGY

Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided. 1. A method for fabricating a carbon nanotube-based integrated circuit , comprising the steps of:providing a first wafer comprising carbon nanotubes which is formed by depositing the carbon nanotubes on a first substrate, depositing a first oxide layer onto the substrate covering the carbon nanotubes, and forming one or more first electrodes that extend at least part way through the first oxide layer and are in contact with one or more of the carbon nanotubes;providing a second wafer comprising one or more device elements which is formed by fabricating the device elements on a second substrate, depositing a second oxide layer over the device elements, and forming one or more second electrodes that extend at least part way through the second oxide layer connected to one or more of the device elements; andconnecting one or more of the carbon nanotubes with one or more of the device elements by bonding the first wafer and the second wafer together.2. (canceled)3. The method of claim 1 , further comprising the step of:forming one or more metal layers in the second oxide layer in contact with the device elements.4. The method of claim 1 , wherein both the first electrodes and the second electrodes comprise copper and wherein the step of connecting the carbon nanotubes with the device elements further comprises the steps of forming an oxide-to-oxide bond between the first oxide layer and the second oxide layer; andforming a copper-to-copper ...

Wafer level chip scale package

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

ANISOTROPIC CONDUCTIVE FILM AND SEMICONDUCTOR DEVICE

A semiconductor device bonded by an anisotropic conductive film, the anisotropic conductive film including a phenoxy resin including a fluorene-substituted phenoxy resin; and a radically polymerizable resin including a fluorene-substituted acrylate. 1. A semiconductor device bonded by an anisotropic conductive film , the anisotropic conductive film including:a phenoxy resin including a fluorene-substituted phenoxy resin; anda radically polymerizable resin including a fluorene-substituted acrylate.2. The semiconductor device as claimed in claim 1 , wherein the anisotropic conductive film includes:about 20 to about 60 parts by weight of the phenoxy resin including the fluorene-substituted phenoxy resin, based on 100 parts by weight of a solid content of the anisotropic conductive film, andabout 40 to about 80 parts by weight of the radically polymerizable resin including the fluorene-substituted acrylate, based on 100 parts by weight of the solid content of the anisotropic conductive film.3. The semiconductor device as claimed in claim 1 , wherein the anisotropic conductive film includes:about 5 to about 50 parts by weight of the fluorene-substituted phenoxy resin, based on 100 parts by weight of the solid content of the anisotropic conductive film andabout 5 to about 40 parts by weight of the fluorene-substituted acrylate, based on 100 parts by weight of the solid content of the anisotropic conductive film.4. The semiconductor device as claimed in claim 1 , wherein the anisotropic conductive film further includes an acrylic-modified epoxy resin.5. The semiconductor device as claimed in claim 1 , wherein the anisotropic conductive film further includes a urethane acrylate.6. The semiconductor device as claimed in claim 1 , wherein the anisotropic conductive film has an adhesive strength of about 700 gf/cm or more claim 1 , as measured after pressing at 160° C. and 3 MPa for 5 seconds.7. The semiconductor device as claimed in claim 1 , wherein the anisotropic ...

Devices Including Metal-Silicon Contacts Using Indium Arsenide Films and Apparatus and Methods

Described are apparatus and methods for forming films comprise indium and arsenic. In particular, these films may be formed in a configuration of two or more chambers under “load lock” conditions. These films may include additional components as dopants, such as aluminum and/or gallium. Such films can be used in metal/silicon contacts having low contact resistances. Also disclosed are devices including the films comprising indium arsenide. 1. A substrate processing apparatus comprising:a first processing chamber to clean a substrate to provide a cleaned substrate;a second processing chamber in communication with the first processing chamber to deposit a layer comprising indium arsenide on the cleaned substrate;a third processing chamber in communication with the second processing chamber to deposit a metal layer on the layer comprising indium arsenide; anda control system in communication with the first, second and third processing chambers,wherein the first, second and third processing chambers are in communication under load lock conditions.2. The apparatus of claim 1 , wherein the first processing chamber performs atomic hydrogen cleaning or cleaning with a fluorine-containing precursor.3. The apparatus of claim 1 , wherein the second processing chamber is an atomic layer deposition (ALD) chamber claim 1 , physical vapor deposition (PVD) chamber claim 1 , chemical vapor deposition (CVD) chamber or molecular beam epitaxy (MBE) chamber.4. The apparatus of claim 3 , wherein the second processing chamber is an ALD chamber.5. The apparatus of claim 3 , wherein the PVD chamber is a sputtering chamber.6. The apparatus of claim 1 , wherein the indium arsenide layer further comprises one or more of gallium claim 1 , aluminum claim 1 , antimony and phosphorus.7. The apparatus of claim 1 , wherein the third processing chamber is an ALD chamber.8. The apparatus of claim 1 , wherein the control system controls the second processing chamber to deposit a layer comprising indium ...

Power Device with Solderable Front Metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

Silicon/germanium nanoparticle inks, laser pyrolysis reactors for the synthesis of nanoparticles and associated methods

Laser pyrolysis reactor designs and corresponding reactant inlet nozzles are described to provide desirable particle quenching that is particularly suitable for the synthesis of elemental silicon particles. In particular, the nozzles can have a design to encourage nucleation and quenching with inert gas based on a significant flow of inert gas surrounding the reactant precursor flow and with a large inert entrainment flow effectively surrounding the reactant precursor and quench gas flows. Improved silicon nanoparticle inks are described that has silicon nanoparticles without any surface modification with organic compounds. The silicon ink properties can be engineered for particular printing applications, such as inkjet printing, gravure printing or screen printing. Appropriate processing methods are described to provide flexibility for ink designs without surface modifying the silicon nanoparticles.

Wafer with Spacer including Horizontal Member

A method of forming an insulating spacer is disclosed that includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion. A wafer is also disclosed.

Contact Test Structure and Method

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Semiconductor light emitting element

A semiconductor light emitting element has a cross-sectional structure comprising a support substrate, a semiconductor lamination located over the support substrate, and a joint layer located between the semiconductor lamination and the support substrate, containing a first jointing layer located on the semiconductor lamination side and a second jointing layer located on the support substrate side. In the plan view, the semiconductor lamination has corner portions and side portions along the periphery, the first jointing layer is encompassed by the second jointing layer, the second jointing layer is encompassed by the semiconductor lamination, and an annular region defined between outlines of the semiconductor lamination and of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths of the first portions being narrower than widths of the second portions.

CIRCUIT DEVICE

A compact circuit device wherein a semiconductor element that performs high current switching is embedded is provided. A lead () and lead () though which high current passes are disposed superimposed on the upper surface of a circuit board (). Also, a plurality of ceramic substrates (A-F) are affixed to the circuit board (), and transistors, diodes, or resistors are mounted to the upper surface of the ceramic substrates. Furthermore, the circuit elements such as the transistors or diodes are connected to the lead () or the other lead () via fine metal wires. 1. A circuit device , comprising:a circuit board;a semiconductor element disposed on an upper surface of the circuit board;a first lead electrically connected to the semiconductor element, on the upper surface of the circuit board; anda second lead electrically connected to the semiconductor element, at least a part of the second lead being superimposed on the first lead.2. The circuit device according to claim 1 , whereinthe semiconductor element includes a first transistor and a second transistor connected to each other, andthe first transistor and the second transistor are disposed in positions opposed to each other across the first lead and the second lead.3. The circuit device according to claim 1 , wherein the first transistor and the second transistor are connected to each other through a fine metal wire formed above the first lead and second lead.4. The circuit device according to claim 1 , further comprising a frame-shaped case material assembled onto the upper surface of the circuit board claim 1 , whereinthe first lead and the second lead in a state being incorporated in the case material are disposed on the upper surface of the circuit board.5. The circuit device according to claim 4 , wherein the first lead and the second lead are insulated from the circuit board by a resin material constituting the case material.6. The circuit device according to claim 1 , whereinthe circuit board is a substrate ...

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A silicon carbide semiconductor device includes: a silicon carbide layer, a reaction layer which is in contact with the silicon carbide layer, a conductive oxidation layer which is in contact with the reaction layer, and an electrode layer which is formed over the reaction layer with the conductive oxidation layer interposed therebetween. A thickness of the conductive oxidation layer falls within a range of 0.3 nm to 2.25 nm. 1. A silicon carbide semiconductor device comprising:a silicon carbide layer;a reaction layer and a conductive oxidation layer which is in contact with the reaction layer, the reaction layer and the conductive oxidation layer being formed by executing the steps in the following order: a conductive layer forming step where a conductive layer is formed on the silicon carbide layer; a heat treatment step where the silicon carbide layer and the conductive layer are made to react with each other thus forming the reaction layer which is in contact with the silicon carbide layer and a silicide layer which is present on the reaction layer; a first plasma ashing step where a carbon component which the silicide layer contains is removed; an etching step where at least a portion of the silicide layer is removed using an acid thus exposing at least a portion of a surface of the reaction layer; and a second plasma ashing step where a carbon component which remains on the reaction layer is removed and a conductive oxidation layer is formed on the reaction layer, andan electrode layer which is formed over the reaction layer with the conductive oxidation layer interposed therebetween.2. The silicon carbide semiconductor device according to claim 1 , wherein a thickness of the conductive oxidation layer falls within a range of 0.3 nm to 2.25 nm.3. The silicon carbide semiconductor device according to claim 1 , wherein the acids are a hydrochloric acid claim 1 , a nitric acid and a hydrofluoric acid.4. A method for manufacturing a silicon carbide semiconductor ...

Semiconductor device with air gap and method for fabricating the same

A method for fabricating a semiconductor device includes forming, over a substrate, a plurality of first conductive structures which are separated from one another; forming multi-layered dielectric patterns including a first dielectric layer which covers upper ends and both sidewalls of the first conductive structures; removing portions of the first dielectric layer starting from lower end portions of the first conductive structures to define air gaps, and forming second conductive structures which are filled between the first conductive structures.

SEMICONDUCTOR CONSTRUCTIONS AND METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS

Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface. 1. A semiconductor construction , comprising:a first region of a semiconductor substrate having first features, and a second region of the substrate having second features; the first features being more closely spaced than the second features;a first electrically insulative material over the second region, and having a top surface below upper surfaces of the first features;a second electrically insulative material over the first electrically insulative material and having a different composition from the first electrically insulative material;the second electrically insulative material being configured as a structure having an upwardly-extending stem joined to a horizontally-extending bench; the bench having an upper surface at about a common level as upper surfaces of the first features; the stem extending to above the upper surfaces of the first features; andan electrically conductive contact within the second region and extending through the first and second electrically insulative materials.2. The construction of wherein the first features are electrically ...

MEMORY DEVICE AND MANUFACTURING METHOD THE SAME

A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element. 1a first driver circuit;a second driver circuit; anda memory cell including a first wiring, a second wiring, a transistor, a first conductive layer, a layer, and a second conductive layer, the transistor having a semiconductor film including a channel formation region,wherein the first wiring is electrically connected to the first driver circuit,wherein the second wiring is electrically connected to the second driver circuit,wherein the semiconductor film includes a metal oxide and the metal oxide includes indium,wherein the first conductive layer is electrically connected to the transistor, wherein each of the layer and the second conductive layer is located over the transistor,wherein the first conductive layer is overlapped with the second conductive layer, andwherein the layer is interposed between the first conductive layer and the second conductive layer.. A semiconductor device comprising: 1. Field of the InventionThe present invention relates to a semiconductor device capable of transmitting and receiving data and a driving method thereof.Note that the term “semiconductor device” used in this specification refers to a device in general that can operate by utilizing semiconductor characteristics, and an electro-optical device, a ...

Integrated circuit based varactor

A varactor comprises a substrate having sets of gate units each having parallel gate strips. The gate units are located such that the gate strips of neighbouring gate units are oriented transverse to each other. An electrically conducting gate connection layer comprises gate connection units comprising parallel gate connection strips located over the gate strips, and a cathode connection frame around each of the gate connection units. A first electrically conductive anode layer comprises first layer anode strips located parallel to the gate connection strips and connected to alternate gate connection strips, and a first anode connection frame connected to the anode strips. A second electrically conductive anode layer comprises anode strips located parallel to the gate connection strips and connected to opposite alternate gate connection strips, and a second anode connection frame connected to the second layer anode strips.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Conductive bump, semiconductor chip and stacked semiconductor package using the same

A conductive bump includes a step member formed to form a step on a portion of a connection pad; and a conductive member formed on the connection pad and the step member and having an inclined surface which is inclined with respect to the connection pad.

SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a silicon substrate, a titanium layer, a nickel layer, a silver layer and a metallic adhesion layer, wherein the silicon substrate comprises a back surface, and the titanium layer comprises an upper surface. The titanium layer is formed on the back surface, the nickel layer is formed on the upper surface, the silver layer is formed on the nickel layer, and the metallic adhesion layer is formed between the nickel layer and the silver layer. 1. A semiconductor structure at least includes:a silicon substrate having an active surface and a back surface;a titanium layer formed on the back surface comprises an upper surface;a nickel layer formed on the upper surface of the titanium layer;a silver layer formed on the nickel layer; anda metallic adhesion layer formed between the nickel layer and the silver layer, wherein the metallic adhesion layer comprises a first thickness and the titanium layer comprises a second thickness such that the first thickness is not greater than the second thickness.2. The semiconductor structure in accordance with claim 1 , wherein the material of the metallic adhesive layer is titanium.3. The semiconductor structure in accordance with claim 1 , wherein the thickness of the titanium layer ranges from 100-10000 Å.4. The semiconductor structure in accordance with claim 1 , wherein the thickness of the nickel layer ranges from 100-10000 Å.5. The semiconductor structure in accordance with claim 1 , wherein the thickness of the silver layer ranges from 100-100000 Å.6. The semiconductor structure in accordance with claim 1 , wherein the thickness of the metallic adhesion layer ranges from 1-5000 Å.7. (canceled) The present invention is generally related to a semiconductor structure, which particularly relates to the semiconductor structure with low resistance.In conventional semiconductor process, a back side metal process is developed in order to improve heat dissipation of high power IC, which evaporates or ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes a process of providing two source electrodes on a substrate, a process of providing a gate electrode on one surface of the substrate between the two source electrodes, a process of providing an insulating film on the gate electrode, the substrate, and side surfaces of the two source electrodes, a process of providing an airbridge foundation resist on the insulating film, providing an airbridge on the two source electrodes and the airbridge foundation resist, and a process of removing the airbridge foundation resist, in which surfaces of the two source electrodes at sides opposite to the substrate and a front surface of the airbridge foundation resist provided in the subsequent process are substantially coplanar. 110-. (canceled)11. A semiconductor device , comprising:a substrate;a pair of source electrodes provided to be separated from each other on an upper surface of the substrate;a gate electrode provided on the upper surface of the substrate between the pair of source electrodes, the gate electrode being separated from the pair of source electrodes, an upper surface of the gate electrode being lower than upper surfaces of the pair of source electrodes; andan airbridge provided to be separated from the substrate and the gate electrode by a space, the airbridge being connected to the upper surfaces of the pair of source electrodes, a second region positioned between the pair of first regions,', 'the second region being located at a lower position than the pair of first regions., 'an upper surface of the airbridge including a pair of first regions facing the pair of source electrodes, and'}12. The semiconductor device according to claim 11 , whereinwhen viewed in top-view, connection portions of the airbridge to the source electrodes protrude further in a direction crossing a direction in which the pair of source electrodes is arranged than a portion of the airbridge overlapping the gate electrode.13. The ...

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

A display device including a substrate including: a top surface, a bottom surface, and a plurality of side surfaces connecting the top surface and the bottom surface; a signal line disposed on the top surface; a sidewall electrode in electrical contact with the signal line and disposed on a first side surface of the side surfaces; and a connection electrode in electrical contact with the sidewall electrode and disposed on the first side surface. 1. A display device comprising:a substrate comprising a top surface, a bottom surface, and a plurality of side surfaces connecting the top surface and the bottom surface;a signal line disposed on the top surface;a sidewall electrode in electrical contact with the signal line and disposed on a first side surface of the side surfaces; anda connection electrode in electrical contact with the sidewall electrode and disposed on the first side surface.2. The display device of claim 1 , wherein an overlapping area between the connection electrode and the sidewall electrode is greater than an overlapping area between the connection electrode and the signal line.3. The display device of claim 1 , wherein a thickness of the sidewall electrode is less than a thickness of the signal line.4. The display device of claim 1 , further comprising an auxiliary electrode disposed on the signal line and in electrical contact with the signal line and the connection electrode.5. The display device of claim 1 , further comprising:an upper substrate facing the substrate;an upper sidewall electrode disposed on a side surface of the upper substrate, which is aligned with the first side surface; anda sealing member disposed between the substrate and the upper substrate and electrically connecting the upper sidewall electrode to the signal line.6. The display device of claim 5 , wherein the connection electrode is in electrical contact with the sidewall electrode of the substrate and the upper sidewall electrode of the upper substrate.7. The display ...

PACKAGING DEVICE AND METHOD OF MAKING THE SAME

The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace. 1. An integrated chip packaging device , comprising:a first package component;a metal trace arranged on a surface of the first package component, wherein the metal trace comprises an undercut;a molding material that fills the undercut of the metal trace and that has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component; anda solder region arranged over the metal trace.2. The device of claim 1 , wherein a top surface of the molding material is arranged between a top surface of the metal trace and the surface of the first package component.3. The device of claim 1 , further comprising:a second metal trace arranged on the surface of the first package component and comprising a second undercut, wherein the molding material fills the second undercut but does not continuously extend over the surface between the metal trace and the second metal trace.4. The device of claim 1 , wherein the solder region surrounds a top surface of the metal trace and sidewalls of the metal trace above the molding material.5. The device of claim 4 , wherein the solder region contacts the sidewalls of the metal trace above the molding material.6. The device of claim 4 , further comprising:a metal pillar arranged between the solder region and a metal pad on a surface of a second package component, wherein the second package component is disposed over ...

SEMICONDUCTOR DEVICE

Provided is a semiconductor device in which the reliability of the gate insulating film in a trench gate is improved. The semiconductor device includes a semiconductor substrate, a plurality of trench gates, and a gate electrode. The semiconductor substrate includes an active region and a wiring region. The trench gates extend from the first active region to the wiring region. The trench gates form parts of transistors in the active region. The gate electrode is provided in the wiring region and is electrically connected to the trench gates. The end portions of the trench gates are located in the wiring region. The gate electrode is provided so as to cover gate contact portions formed at the end portions of the trench gates. The gate electrode is electrically connected to trench gates via the gate contact portions. The plurality of trench gates extend only in one direction. 1. A semiconductor device comprising:a semiconductor substrate including an active region in which a plurality of transistors are provided and a wiring region surrounding the active region in plan view;a plurality of trench gates extending from the active region to the wiring region on a front surface of the semiconductor substrate and forming a part of the plurality of transistors in the active region; anda gate electrode provided in the wiring region and electrically connected to the plurality of trench gates, whereinan end portion of each of the plurality of trench gates is located in the wiring region,the gate electrode is provided so as to cover a gate contact portion formed at the end portion of each of the plurality of trench gates, and electrically connected to each of the plurality of trench gates via the gate contact portion, andthe plurality of trench gates extend only in one direction on the front surface of the semiconductor substrate.2. The semiconductor device according to claim 1 , whereina trench width at the end portion of each of the plurality of trench gates is greater than a ...

POWER CONVERTER

To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode. 1. A power converter comprising:a plurality of semiconductor devices, a first gate electrode in an active region;', 'a gate pad in a first region different from the active region in a plan view; and', 'a first gate line electrically connecting the first gate electrode and the gate pad to each other, wherein', 'the first gate line is formed into a spiral shape,', 'the first gate line is made of a different type of material from the first gate electrode, and, 'each of the semiconductor devices includes'}the plurality of semiconductor devices are connected in parallel to each other.2. A power converter comprising:a plurality of semiconductor devices, a first gate electrode in an active region;', 'a gate pad in a first region different from the active region in a plan view; and', 'a first gate line electrically connecting the first gate electrode and the gate pad to each other, wherein', 'the first gate line is formed into a spiral shape,', 'the first gate line is arranged in the first region, and, 'each of the semiconductor devices includes'}the plurality of semiconductor devices are connected in parallel to each other.3. The power converter according to claim 1 , whereinthe first gate line surrounds the gate pad in a plan view.4. A power converter comprising:a plurality of semiconductor devices, a first gate electrode in an active region;', 'a gate pad in a first region different from the active region in a plan ...

Semiconductor Constructions

Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.

Semiconductor backmetal (bm) and over pad metallization (opm) structures and related methods

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

SEMICONDUCTOR DEVICE

In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of drain electrodes, each of the drain electrodes being disposed along one direction on the semiconductor substrate;a plurality of source electrodes, each of the source electrodes being disposed in an area between corresponding adjacent two of the drain electrodes on the semiconductor substrate, and being disposed along the one direction;a feed line being disposed on the semiconductor substrate, and having a band shape extending in the one direction; an input line disposed on the semiconductor substrate;', 'an air bridge connecting the feed line and the input line;, 'a plurality of gate fingers, each of the gate fingers having a linear shape extending from the feed line, and being disposed in an area between two adjacent electrodes on the semiconductor substrate, one of the two adjacent electrodes being a corresponding one of the drain electrodes and the other being a corresponding one of the source electrodes; and'}a plurality of open stubs being disposed on the semiconductor substrate, and having a line length that eliminates a target higher harmonic wave, and each of the open stubs passing under the air bridge and being connected directly to the feed line.2. The semiconductor device according to claim 1 , wherein the open stubs are arranged so as to correspond one-to-one to the gate fingers.3. The semiconductor device according to claim 1 , wherein the open stubs are made from a metallic material identical to that of the gate fingers.4. A semiconductor device comprising:a semiconductor substrate;a plurality of drain electrodes, each of the drain electrodes being disposed along one direction on the semiconductor substrate;a plurality of source electrodes, each of the ...

Semiconductor Package and Method of Manufacturing a Semiconductor Package

A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths. 116-. (canceled)17. A semiconductor package , comprising:a semiconductor die comprising a semiconductor device, a first contact pad arranged on a first surface of the semiconductor die and a second contact pad arranged on a second surface of the semiconductor die that opposes the first surface, the semiconductor die being embedded in a dielectric layer; andone or more first package contact pads and one or more second package contact pads arranged on a first major surface of the dielectric layer, wherein the dielectric layer has a lateral extent that is greater than the area occupied by the first and second package contact pads, the first contact pad of the semiconductor die being coupled to the one or more first package contact pads and the second contact pad of the semiconductor die being coupled to the one or more second package contact pads,wherein in operation, the semiconductor device causes a current path between the first contact pad and the second contact pad,wherein the one or more first package contact pads and the one or more second package contact pads are arranged on the first major surface of the dielectric layer to ...

Compound semiconductor device

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;a foundation layer formed on the first face of the semiconductor substrate;a first electrode formed on the foundation layer;a second electrode formed on the foundation layer;an integrated circuit comprising at least two interconnected semiconductor devices, the at least two interconnected semiconductor devices formed on the first face of the semiconductor substrate, and the integrated circuit being electrically connected to the first electrode and the second electrode;a groove portion formed through the semiconductor substrate;an insulating film formed on a side wall of the groove portion;a conductive portion formed inside the groove portion on the insulating film and electrically connected to the second electrode;a first insulation layer formed on the foundation layer;a first interconnection formed on the first insulation layer, the first interconnection being electrically connected to the first electrode;a second insulation layer formed on the first interconnection and the first insulation layer;a second interconnection formed on the second insulation layer, the second interconnection being electrically connected to the first interconnection; anda third insulation layer formed on the second interconnection and the second insulation layer; ...

BOND-OVER-ACTIVE CIRCUITY GALLIUM NITRIDE DEVICES

Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact. 1. A semiconductor device comprising:a first metal layer comprising an active area and a non-active area;a second metal layer comprising at least one drain pad, at least one source pad and at least one gate pad; andat least one gate bus;wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another;wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers;wherein the at least one drain pad is located only in the non-active area of the first metal layer; andwherein the first metal layer is electrically coupled to the second metal layer.2. The semiconductor device of claim 1 , wherein the plurality of drain fingers are coupled together at one end.3. The semiconductor device of claim 1 , further comprising a single contact between the at least one drain pad and the plurality of drain fingers.4. The semiconductor device of claim 1 , wherein the at least one source pad is located only in the active area of the first metal layer.5. The semiconductor device of claim 1 , further comprising a second source pad and wherein the at least one drain pad is located between the at least one source pad and the second source pad.6. The semiconductor device of claim 1 , further comprising a ...

Fan-Out Package with Cavity Substrate

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Method for Producing Electronic Device With Multi-Layer Contact

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

COMPOUND SEMICONDUCTOR DEVICE

A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening. 1. A semiconductor device comprising: a collector layer, base layer, and emitter layer;', 'a base electrode on the base layer; and', 'an emitter electrode on the emitter layer;, 'a heterojunction bipolar transistor including plural unit transistors, each unit transistor includingbase wires respectively electrically connecting the base electrodes of the unit transistors to an input terminal;a metallization layer electrically connecting the emitter electrode of each of the plural unit transistors to each other, and having first portions respectively over each of the emitter electrodes and second portions respectively overhanging each of the base electrodes;a dielectric layer over the metallization layer, the dielectric layer including a conductor filled via opening overlying each of the plural unit transistors; anda bump elongated in a length direction is positioned above the plural unit transistors and has a width in a width direction transverse to the length direction, and, for each of the plurality of unit transistors, the bump electrically connects the metallization layer with the conductor filled via opening therebetween, wherein the overlying via opening overlaps in a plan view a width ...

Method and Structure of Packaging Semiconductor Devices

A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly. 1. A method for fabricating packaged semiconductor devices , comprising:providing a flat carrier sheet secured in a frame to restrain warpage, the carrier having an insulating core of clear laminate material and a surface covered by a layer of a UV-releasable adhesive, the frame having lateral dimensions comparable to a semiconductor wafer;attaching the surface of a metallic window frame onto the adhesive panel surface, the frame including a plurality of rectangular windows bordered by a metal grid and sized larger than a semiconductor chip;attaching a plurality of semiconductor chips to the adhesive carrier surfaces in respective windows, the chip terminals facing the adhesive surface;compression-molding a compliant insulating material to cohesively fill gaps between chips and grid sidewalls, the material having a coefficient of thermal expansion approaching the coefficient of the semiconductor chips, thereby creating an assembly;using UV irradiation, separating the carrier sheet and frame from the assembly, thereby exposing the surfaces of the chips with terminals and the grid metals;plasma-cleaning the carrier and attached chips uniformly in ...

Chip package and manufacturing method thereof

A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

SYSTEMS AND METHODS TO ENHANCE PASSIVATION INTEGRITY

Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body. 1. A semiconductor device , comprising:a substrate;a conductive layer over the substrate, the conductive layer including a central upper surface region and a peripheral upper surface region which are spaced apart from one another by an intermediate upper surface region;a silicon-containing layer disposed over the peripheral upper surface region of the conductive layer but not covering the central upper surface region of the conductive layer, the silicon-containing layer including a plurality of bar or pillar structures over the intermediate upper surface region; andan aluminum copper body including a central portion and an intermediate portion, wherein the central portion extends through the silicon-containing layer to contact the central upper surface region of the conductive layer, and wherein the intermediate portion includes a plurality of ridges or pillars that pass between the plurality of bar or pillar structures in the silicon-containing layer to contact the intermediate upper surface region of the conductive layer.2. The semiconductor device of claim 1 , wherein the silicon-containing layer is a dielectric material.3. The semiconductor device of claim 1 , wherein the plurality of bar or pillar structures have sidewalls that are laterally spaced apart from one another claim 1 , and wherein the plurality of ridges or pillars of the intermediate portion of the aluminum copper body extend downwardly between the sidewalls of the plurality of bar or pillar structures.4. The semiconductor device of claim 1 , wherein the plurality of bar or pillar structures have upper surfaces that are ...

Low-Resistance Electrode Design

A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated.

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. 1. An apparatus comprising:a substrate having a cavity;a bridge embedded in the substrate cavity;a dielectric material laminated over the bridge in the cavity;a joint electrically coupled with the bridge, to route electrical signals beyond a surface of the substrate, a barrier layer including a second conductive material disposed directly on the joint, and', 'a solder layer that includes a third conductive material, disposed directly on the barrier layer, wherein the barrier layer and the solder layer are to route the electrical signals., 'wherein the joint includes a first conductive material;'}2. The apparatus of claim 1 , wherein the joint comprises a via.3. The apparatus of claim 1 , wherein the solder layer comprises a substantially round bump claim 1 , formed by a reflow of the solder layer.4. The apparatus of claim 1 , wherein the first conductive material comprises copper (Cu) claim 1 , the second conductive material comprises nickel (Ni) claim 1 , and the third conductive material comprises tin (Sn).5. The apparatus of claim 1 , further comprising:a first die electrically coupled with the bridge; anda second die ...

DIE BONDING TO A BOARD

An apparatus for bonding die to a board includes a circuit board having a solderable layer and a plurality of die bonded to the circuit board using at least three respective layers. Each of the at least three respective layers includes an inner layer, a first alloy of material from an outer layer and the solderable layer of the circuit board, and a second alloy of material from the outer layer and the solderable layer of the circuit board. Melting temperatures of the first alloy and the second alloy are higher than reflow temperatures of the outer layer and the solderable layer of the circuit board. 1. An apparatus , comprising:a first solderable layer on a surface of a ceramic or substrate board or a metal lead frame; a first solderable die surface on a first die comprising a first plurality of metal layers wherein an outer layer comprises a silver and tin first alloy having a silver composition that is less than 7 percent by weight and wherein an inner layer next to the outer layer comprises one of titanium, nickel or silver; and', 'a second alloy having a subsequent melting temperature that is higher than a first reflow temperature required to adhere the first die to the first solderable layer of the board, wherein the second alloy bonds the first alloy to the first solderable layer of the surface of the board to hold the first die to the board, and, 'first circuitry comprising 'a second solderable die surface on a second die comprising a third alloy,', 'second circuitry comprisingwherein the first and second circuitry are configured to control operations of the apparatus.2. The apparatus of claim 1 , wherein the second alloy has a melting temperature that will not completely melt during subsequent reflow process at the first reflow temperature used to add the second circuitry.3. The apparatus of claim 1 , wherein the first solderable layer of the ceramic or substrate board or metal lead frame comprises at least one of copper claim 1 , silver and tin.4. The ...

SEMICONDUCTOR DEVICE

In an inactive region of an active region, a gate pad, a gate poly-silicon layer, and a gate finger are provided at a front surface of a semiconductor substrate, via an insulating film. The gate poly-silicon layer is provided beneath the gate pad, sandwiching the insulating film therebetween. The gate pad, the gate poly-silicon layer, a gate finger, gate electrodes of a trench gate structure, a gate finger, and a second measurement pad are electrically connected in the order stated. As a result, the gate electrodes where parasitic resistance occurs and the gate poly-silicon layer where built-in resistance occurs are connected in series between the second measurement pad and the gate pad. A resistance value of the overall gate resistance that is a combined resistance of the built-in resistance and the parasitic resistance may be measured by the second measurement pad. 1. A semiconductor device comprising:an insulated gate structure provided on a first main surface side of a semiconductor substrate, the insulated gate structure being constituted by a 3-layer structure including a metal film, an oxide film, and a semiconductor material;a gate pad provided at a first main surface of the semiconductor substrate, via an insulating film;a gate finger provided at the first main surface of the semiconductor substrate, via the insulating film, and to which a plurality of gate electrodes constituted by the metal film of the insulated gate structure is electrically connected;a gate poly-silicon layer provided at the first main surface of the semiconductor substrate, via the insulating film, the gate poly-silicon layer electrically connecting the gate pad and the gate finger; andan electrode pad for measuring a first resistance value, the electrode pad being provided at the first main surface of the semiconductor substrate, via the insulating film, and electrically connected to the gate finger, whereinall gate electrodes of the plurality of gate electrodes are electrically ...

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. 1. A bidirectional Zener diode chip , comprising:a semiconductor substrate of a first conductivity type;an insulating film which covers a front surface of the semiconductor substrate;a first diffusion region of a second conductivity type formed in the semiconductor substrate and exposed at the front surface of the semiconductor substrate;a second diffusion region of the second conductivity type formed in the semiconductor substrate across an interval from the first diffusion region and exposed at the front surface of the semiconductor substrate;contact holes in the insulating film for selectively exposing the first diffusion region and the second diffusion region through the insulating film;a first electrode formed on the front surface of the semiconductor substrate and connected to the first diffusion region; anda second electrode formed on the front surface of the semiconductor substrate and connected to the second diffusion region,wherein the first electrode includes a plurality of first extraction electrodes which are defined to cover the first diffusion region,wherein the second electrode includes a plurality of second extraction electrodes which are defined to cover the second diffusion region along the second extraction electrodes extending parallel to the first extraction electrodes in a lengthwise direction as viewed from a plan view,wherein the plurality of first extraction electrodes and the plurality of second extraction electrodes are defined in a comb-toothed shape engaging with each other,wherein a shape of the contact holes is an elongated shape in the ...

DUAL BOND PAD STRUCTURE FOR PHOTONICS

A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads. 1. A method , comprising:forming a masking layer over a bonding layer;patterning the bonding layer to form bonding pads;attaching a laser diode to selected bonding pads using solder connections formed on the laser diode such that the laser diode is unobstructed by solder bumps and the selected bonding pads; andattaching an interposer substrate to the solder bumps which are on the bonding pads such that the interposer substrate is spaced away and disconnected from the laser diode.2. The method of claim 1 , wherein the masking layer is formed over portions of the bonding layer which are to be attached to the laser diode.3. The method of claim 1 , wherein the solder bumps are formed through a resist pattern claim 1 , after the forming of the masking layer over the bonding layer.4. The method of claim 1 , further comprising forming the solder bumps on the bonding layer.5. The method of claim 4 , wherein the patterning of the bonding layer is performed after the forming of the solder bumps such that the solder bumps and the masking layer protect underlying portions of the bonding layer during an etching process.6. The method of claim 5 , further comprising removing the masking layer and attaching the solder connections formed on the laser diode directly to the bonding pads which are formed underneath the masking layer prior to removal.7. The method of claim 6 , ...

Method for reducing cross contamination in integrated circuit manufacturing

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Various protocols can be employed during processing to avoid cross-contamination between copper-plated and non-copper-plated wafers. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Power Semiconductor Module

A power semiconductor module comprising a substrate. The power semiconductor module has first and second DC voltage load current connection elements and first and second power semiconductor components. The first and second power semiconductor components are arranged along a lateral first direction of the substrate. The power semiconductor module has a foil composite having a first metallic foil layer and a structured second metallic foil layer and an electrically insulating foil layer arranged between the first and second metallic foil layers. The first power semiconductor component and the second power semiconductor component are electrically conductively connected to the foil composite and to the substrate. The first and second power semiconductor components are arranged on a common side in relation to the first and second DC voltage load current connection elements. The invention provides a power semiconductor module having a particularly low-inductance construction. 1. A power semiconductor module comprising:a substrate having an insulating material body and an electrically conductive structured conduction layer arranged on said insulating material body, said conduction layer forming conductor tracks which are electrically insulated from one another, said substrate defining a lateral first direction;wherein a first power semiconductor component having a first and a second load current connection is arranged on a first conductor track and said first load current connection of said first power semiconductor component is electrically conductively connected to said first conductor track;wherein a second power semiconductor component having a first and a second load current connection is arranged on a second conductor track and said first load current connection of said second power semiconductor component is electrically conductively connected to said second conductor track;wherein the power semiconductor module has a first and a second DC voltage load current ...

TRANSISTOR SEMICONDUCTOR DIE WITH INCREASED ACTIVE AREA

A transistor semiconductor die includes a drift layer, a first dielectric layer, a first metallization layer, a second dielectric layer, a second metallization layer, a first plurality of electrodes, and a second plurality of electrodes. The first dielectric layer is over the drift layer. The first metallization layer is over the first dielectric layer such that at least a portion of the first metallization layer provides a first contact pad. The second dielectric layer is over the first metallization layer. The second metallization layer is over the second dielectric layer such that at least a portion of the second metallization layer provides a second contact pad and the second metallization layer at least partially overlaps the first metallization layer. The transistor semiconductor die is configured to selectively conduct current between the first contact pad and a third contact pad based on signals provided at the second contact pad. 1. A transistor semiconductor die comprising:a first contact pad, a second contact pad, and a third contact pad; and the first contact pad and the second contact pad are located on a same side of the transistor semiconductor die; and', 'a total inactive area within the device region is less than an area of the second contact pad., 'a device region comprising one or more regions coupled to one or more of the first contact pad, the second contact pad, and the third contact pad such that the transistor semiconductor die is configured to selectively conduct current between the first contact pad and the third contact pad based on signals provided at the second contact pad, wherein2. The transistor semiconductor die of claim 1 , wherein an area of the first contact pad is at least 0.4 mm.3. The transistor semiconductor die of claim 2 , wherein the area of the first contact pad is in a range from at least 0.4 mmto 1.0 mm.4. The transistor semiconductor die of claim 1 , wherein the transistor semiconductor die is configured to conduct more ...

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a substrate and an electronic component disposed on the substrate. The electronic component has an active surface facing away from the substrate. The substrate has a first conductive pad and a second conductive pad disposed thereon. The electronic component has a first electrical contact and a second electrical contact disposed on the active surface. The semiconductor device package further includes a first metal layer connecting the first electrical contact with the first conductive pad, a second metal layer connecting the second electrical contact with the second conductive pad, a first seed layer disposed below the first metal layer; and a first isolation layer disposed between the first metal layer and the second metal layer. A method of manufacturing a semiconductor device package is also disclosed.

Electronic Device with Multi-Layer Contact

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

WIRE BONDABLE SURFACE FOR MICROELECTRONIC DEVICES

The present invention concerns thin diffusion barriers in metal and metal alloy layer sequences of contact area/barrier layer/first bonding layer type for metal wire bonding applications. The diffusion barrier is selected from Co-M-P. Co-M-B and Co-M-B—P alloys wherein M is selected from Mn, Zr, Re, Mo, Ta and W having a thickness in the range 0.03 to 0.3 μm. The first bonding layer is selected from palladium and palladium alloys. 2. A semiconducting substrate according to wherein the barrier layer is selected from the group consisting of Co—Mo—P claim 1 , Co—W—P claim 1 , Co—Mo—B claim 1 , Co—W—B claim 1 , Co—Mo—B—P and Co—W—B—P alloys.3. A semiconducting substrate according to wherein the thickness of the barrier layer ranges from 0.05 to 0.15 μm.4. A semiconducting substrate according to wherein the thickness of the first bonding layer ranges from 0.1 to 0.2 μm.5. A semiconducting substrate according to wherein the stack further comprises a second bonding layer on top of the first bonding layer.6. A semiconducting substrate according to wherein the second bonding layer is selected from the group consisting of gold and gold alloys.7. A semiconducting substrate according to wherein the thickness of the second bonding layer ranges from 0.02 to 0.1 μm.8. A semiconducting substrate according to wherein the contact areas consist of a metal selected from the group consisting of copper claim 1 , copper alloys claim 1 , aluminium and aluminium alloys.9. A semiconducting substrate according to wherein the thickness of the barrier layer ranges from 0.05 to 0.15 μm.10. A semiconducting substrate according to wherein the thickness of the first bonding layer ranges from 0.1 to 0.2 μm.11. A semiconducting substrate according to wherein the thickness of the first bonding layer ranges from 0.1 to 0.2 μm.12. A semiconducting substrate according to wherein the thickness of the first bonding layer ranges from 0.1 to 0.2 μm.13. A semiconducting substrate according to wherein the ...

TRANSISTOR WITH I/O PORTS IN AN ACTIVE AREA OF THE TRANSISTOR

A semiconductor device includes an active region formed in a substrate. The active region includes input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. An input port is electrically connected to the input fingers and an output port is electrically connected to the output fingers. A common region is electrically connected to the common fingers. At least one of the input and output ports is positioned within the active region between the input, output, and common fingers. The common region is interposed between a pair of the common fingers such that the common fingers of the pair are spaced apart by a gap, and at least one of the input and output ports is position in the gap. 1. A semiconductor device comprising:an active region formed in a substrate, the active region including input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another;an input port electrically connected to the input fingers;an output port electrically connected to the output fingers; anda common region electrically connected to the common fingers, wherein at least one of the input and output ports is positioned within the active region between the input, output, and common fingers.2. The semiconductor device of wherein:the common region is interposed between a pair of the common fingers such that the common fingers of the pair are spaced apart by a gap, the common region being electrically connected to each of the common fingers of the pair; andat least one of the input and output ports is positioned in the gap.3. The semiconductor device of wherein:each of the common fingers of the pair has an intermediate region at which the common region is located, the gap is a first gap at a first side of the common region, a second gap is formed at a second side of the common region;the input port is positioned in the first gap; andthe output port is positioned ...

Method for preparing semiconductor package structure

The present disclosure provides a method for preparing a semiconductor package structure. The method includes the following steps. A first die is provided. A second die including a plurality of first conductors is bonded to the first die. A plurality of second conductors are disposed on the first die. A molding is disposed to encapsulate the first die, the second die and the plurality of second conductors. An RDL is disposed on the second die and the molding. A plurality of connecting structures are disposed on the RDL.

RADIO FREQUENCY TRANSISTOR AMPLIFIERS AND OTHER MULTI-CELL TRANSISTORS HAVING GAPS AND/OR ISOLATION STRUCTURES BETWEEN GROUPS OF UNIT CELL TRANSISTORS

A multi-cell transistor includes a semiconductor structure and a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor including a gate finger that extends in a first direction on the semiconductor structure. The gate fingers are spaced apart from each other along a second direction and arranged on the semiconductor structure in a plurality of groups. A first distance in the second direction between adjacent gate fingers in a first of the groups is less than a second distance in the second direction between a first gate finger that is at one end of the first group and a second gate finger that is in a second of the groups, where the second gate finger is adjacent the first gate finger 1. A multi-cell transistor , comprising:a semiconductor structure; anda plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure,wherein the unit cell transistors are spaced apart from each other along a second direction and arranged in a plurality of groups, wherein a first distance in the second direction between two adjacent unit cell transistors in a first of the groups is less than a second distance in the second direction between a first unit cell transistor that is at one end of the first of the groups and a second unit cell transistor that is in a second of the groups, where the second unit cell transistor is adjacent the first unit cell transistor,wherein the multi-cell transistor further comprises a metal isolation structure that extends above the semiconductor structure in the first direction between the first of the groups and the second of the groups, andwherein the metal isolation structure is electrically connected to source regions of the unit cell transistors.2. The multi-cell transistor of claim 1 , wherein the second distance is greater than the first distance by at least a factor of three.34-. (canceled)5. ...

RADIO FREQUENCY TRANSISTOR AMPLIFIERS AND OTHER MULTI-CELL TRANSISTORS HAVING ISOLATION STRUCTURES

A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure. 1. A multi-cell transistor , comprising:a semiconductor structure;a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction; andan isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors,wherein the isolation structure comprises an isolation element that extends vertically between the first group of the unit cell transistors and the second group of the unit cell transistors and is configured to reduce a mutual coupling between the first group of the unit cell transistors and the second group of the unit cell transistors.2. The multi-cell transistor of claim 1 , wherein the isolation structure is above the semiconductor structure.3. The multi-cell transistor of claim 1 , wherein a first distance in the second direction between two adjacent unit cell transistors in the first group of the unit cell transistors is less than a second distance in the second direction between a first unit cell transistor that is at one end of the first group of the unit cell transistors and a second unit cell transistor that is in the second group of the unit cell transistors claim 1 , where the second unit cell transistor is adjacent the first unit cell transistor.4. (canceled)5. The multi-cell ...

FIELD-EFFECT TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND RADIO-FREQUENCY DEVICE

There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction. 1. A field-effect transistor comprising:a semiconductor layer;a first contact plug;a second contact plug;first metals, wherein one of the first metals is stacked on the first contact plug, and wherein a second one of the first metals is stacked on the second contact plug; a first region below bottom surfaces of the first metals along a stacking direction and between the first contact plug and the second contact plug along an in-plane direction of the semiconductor layer,', 'a second region between top surfaces of the first metals and the bottom surfaces of the first metals along the stacking direction and between the first contact plug and the second contact plug along the in-plane direction of the semiconductor layer, and', 'a third region above the top surfaces of the first metals along the stacking direction and between the first contact plug and the second contact plug along the in-plane direction of the semiconductor layer; and, 'one or more insulating films provided in at least one of'}a low-dielectric constant region provided at least in the third region.2. The field-effect transistor according to claim 1 , further comprising:a gate electrode,wherein the semiconductor layer having a source region and a drain region with the gate electrode in between,wherein the first contact plug and the second contact plug are formed from a first conductive material,wherein the first contact plug is provided on the source region, andwherein the second ...

DUAL DAMASCENE STRUCTURE WITH LINER

A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a substrate. The method further includes reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The method further includes forming a liner material on the material over or within the via of the dual damascene structure. The method further includes filling any remaining portions of the via and a trench of the dual damascene structure with additional material. 1. A structure , comprising:a via interconnect in a dielectric material comprising a liner and a conductive material;an upper wiring layer in the dielectric material and in alignment with the via interconnect, the upper wiring layer comprising a liner and the conductive material; anda diffusion blocking liner embedded within the conductive material over the via interconnect and below the upper wiring layer which is located such that void formation due to electromigration or stress migration is prevented in the via interconnect.2. The structure of claim 1 , wherein the via interconnect and the upper wiring layer is a dual damascene structure.3. The structure of claim 2 , wherein the via interconnect completely fills a via of the dual damascene structure.4. The structure of claim 2 , wherein the via interconnect partially fills a via of the dual damascene structure.5. The structure of claim 2 , wherein the diffusion blocking liner is embedded between copper which is formed in the via and the trench.6. The structure of claim 1 , wherein the via interconnect comprises a seed layer of copper.7. The structure of claim 1 , wherein the diffusion blocking liner is a Cu diffusion blocking liner.8. The structure of claim 1 , wherein the diffusion blocking liner is Ta(N) claim 1 , Co(N) claim 1 , Ru(N) claim 1 , Ir claim 1 , Rh claim 1 , Pt or Pb.9. The structure of claim 1 , wherein the via interconnect is smaller in ...

Semiconductor Devices

A semiconductor device includes a first transistor cell of a plurality of transistor cells of a vertical field effect transistor arrangement, and a second transistor cell of the plurality of transistor cells. The first transistor cell and the second transistor cell are electrically connected in parallel. A gate of the first transistor cell and a gate of the second transistor cell are controllable by different gate control signals. 1. A semiconductor device , comprising:a first transistor cell of a plurality of transistor cells of a vertical field effect transistor arrangement; anda second transistor cell of the plurality of transistor cells;wherein the first transistor cell and the second transistor cell are electrically connected in parallel,wherein a gate of the first transistor cell and a gate of the second transistor cell are controllable by different gate control signals.2. The semiconductor device of claim 1 , wherein a first gate control signal generated by a controller module provides a first gate voltage to the gate of the first transistor cell claim 1 , and wherein a second gate control signal generated by the controller module provides a second gate voltage to the gate of the second transistor cell during a same time interval.3. The semiconductor device of claim 1 , wherein the different gate control signals are generated by a controller module based on a current of the first transistor cell or on a current of a subset of transistor cells of the plurality of transistors cell comprising the first transistor cell.4. The semiconductor device of claim 1 , wherein the different gate control signals are generated by a controller module based on a current of an emitter/collector or source/drain contact structure contacting the first transistor cell or a subset of transistor cells of the plurality of transistors cell comprising the first transistor cell.5. The semiconductor device of claim 4 , wherein the current of the emitter/collector or source/drain contact ...

ENCAPSULATED SEMICONDUCTOR DEVICE PACKAGE WITH HEATSINK OPENING

Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material. 1. A method of manufacturing a packaged semiconductor device , the method comprising the steps of:encapsulating a semiconductor die in encapsulant material, wherein the semiconductor die has a top die surface, a bottom die surface, and a first conductive feature coupled to the bottom die surface, wherein the first conductive feature only partially covers the bottom die surface to define a first conductor-less region that spans a first portion of the bottom die surface, and wherein encapsulating includes attaching encapsulant material to the bottom die surface wherein the encapsulant material includes a first opening that exposes the first conductive feature, and wherein the first opening has encapsulant sidewalls extending from an outer surface of the encapsulant material toward the bottom die surface;after encapsulating the semiconductor die, positioning a heatsink within the first opening, wherein the heatsink has a first heatsink surface, a second heatsink surface, and heatsink sidewalls extending between the first and second heatsink surfaces; andattaching the first heatsink surface to the first conductive feature.2. The ...

SEMICONDUCTOR DEVICE WITH GRAPHENE CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME

The present disclosure relates to a semiconductor device and a method for forming a semiconductor device with a graphene conductive structure. The semiconductor device includes a first gate structure disposed over a semiconductor substrate, and a first source/drain region disposed in the semiconductor substrate and adjacent to the first gate structure. The semiconductor device also includes a first silicide layer disposed in the semiconductor substrate and over the first source/drain region, and a graphene conductive structure disposed over the first silicide layer. The semiconductor device further includes a first dielectric layer covering the first gate structure, and a second dielectric layer disposed over the first dielectric layer. The graphene conductive structure is surrounded by the first dielectric layer and the second dielectric layer. 1. A semiconductor device , comprising:a first gate structure disposed over a semiconductor substrate;a first source/drain region disposed in the semiconductor substrate and adjacent to the first gate structure;a first silicide layer disposed in the semiconductor substrate and over the first source/drain region;a graphene conductive structure disposed over the first silicide layer;a first dielectric layer covering the first gate structure; anda second dielectric layer disposed over the first dielectric layer, wherein the graphene conductive structure is surrounded by the first dielectric layer and the second dielectric layer.2. The semiconductor device of claim 1 , further comprising:a barrier layer disposed between the graphene conductive structure and the first dielectric layer and between the graphene conductive structure and the second dielectric layer.3. The semiconductor device of claim 2 , wherein the barrier layer is in direct contact with the first silicide layer.4. The semiconductor device of claim 1 , wherein the graphene conductive structure is in direct contact with the first silicide layer.5. The semiconductor ...

Semiconductor device and method of forming a curved image sensor

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

SEMICONDUCTOR DEVICES WITH THROUGH SILICON VIAS AND PACKAGE-LEVEL CONFIGURABILITY

A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad. 1. A method of assembling a semiconductor device assembly , comprising:providing a substrate including a substrate contact; a first contact pad electrically coupled to a first circuit including at least one active circuit element,', 'a first through-silicon via (TSV) electrically coupling the first contact pad to a first backside contact pad,', 'a second contact pad electrically coupled to a second circuit including only passive circuit elements,', 'a second TSV electrically coupling the second contact pad to a second backside contact pad,', 'a third contact pad electrically coupled to a third circuit including only passive circuit elements, and', 'a third TSV electrically coupling the third contact pad to a third backside contact pad;, 'coupling first and second dies to the substrate, wherein each of the first and second die includeelectrically coupling the substrate contact to the first circuit of each of the first and second die; andelectrically coupling the substrate contact to the second circuit of the first die, the second circuit of the second ...

Bonding structure including metal nano particles and bonding method using metal nano particles

A bonding structure including metal nano particles includes a first member having a metal surface on at least one side, a second member having a metal surface on at least one side, the second member being disposed such that the metal surface of the second member faces the metal surface of the first member, and a bonding material bonding the first member and the second member by sinter-bonding the metal nano particles. At least one of the metal surfaces of the first member and the second member is formed to be a rough surface having a surface roughness within the range from 0.5 μm to 2.0 μm.

SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A GRAPHENE-BASED BARRIER METAL LAYER

An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by utilizing a graphene-based barrier metal layer to block oxygen intrusion from a dielectric layer into the interconnect structure and block copper diffusion from the interconnect structure into the dielectric layer, are disclosed. At least one opening is formed in a dielectric layer. A graphene-based barrier metal layer disposed on the dielectric layer is formed. A seed layer disposed on the graphene-based barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed. 1. An interconnect structure comprising:at least one opening in a dielectric layer;a graphene-based barrier metal layer disposed on the dielectric layer;a seed layer disposed on the graphene-based barrier metal layer;an electroplated copper layer disposed on the seed layer;a planarized surface, wherein a portion of the graphene-based barrier metal layer, the seed layer, and the electroplated copper layer are removed; anda capping layer disposed on the planarized surface.2. The interconnect structure of claim 1 , wherein the at least one opening further comprises a trench area claim 1 , a trench area with at least one via hole claim 1 , or a combination thereof.3. The interconnect structure of claim 1 , wherein:the graphene-based barrier metal layer is formed utilizing electrostatic deposition at a temperature ranging from about 15° C. to about 25° C.;{'sup': '2', 'the graphene-based barrier metal layer comprises a single atomic layer of sp-bonded carbon atoms densely packed into a hexagonal crystal lattice; and'}the graphene-based barrier metal layer has a thickness of about 0.15 nm.4. The interconnect structure of ...

Semiconductor device and method of manufacturing semiconductor device

In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.

Semiconductor package having discrete antenna device

One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

BACKSIDE CONTACT TO A FINAL SUBSTRATE

A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming an electrically-conducting connection in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate. 1. A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer , a buried insulator layer , and a handle wafer , the method comprising:forming an electrically-conducting connection in a trench;removing the handle wafer;after the handle wafer is removed, partially removing the buried insulator layer to expose the electrically-conducting connection; andafter the buried insulator layer is partially removed, coupling a final substrate to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.2. The method of claim 1 , wherein the trench extends through the device layer and partially through the buried insulator layer.3. The method of claim 2 , wherein the backside contact comprises the electrically-conducting connection.4. The method of claim 2 , wherein forming the electrically-conducting connection further comprises:filling the trench with a semiconductor material.5. The method of claim 3 , wherein forming the electrically-conducting connection further comprises:before the trench is filled with a semiconductor material, lining the trench with an etch stop layer comprised of a material that etches selective to the semiconductor material.6. The method of claim 2 , wherein:the buried insulator layer includes a first surface in direct contact with the device layer and a second surface in ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor layer laminate disposed on a semiconductor substrate, a first and a second low-side transistors, and a first and a second high-side transistors. Each of the transistors is disposed on the semiconductor layer laminate, and includes a gate electrode, a source electrode, and a drain electrode. The second low-side transistor is disposed between the first low-side transistor and the first high-side transistor, and the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor. The source electrodes of the first and the second low-side transistors are combined into one source electrode, the drain electrodes of the first and the second high-side transistors are combined into one drain electrode, and the drain electrode of the second low-side transistor and the source electrode of the first high-side transistor are combined into one first electrode. 1. A semiconductor device comprising:a semiconductor layer laminate disposed on a semiconductor substrate;a first low-side transistor disposed on the semiconductor layer laminate, and having a gate electrode, a source electrode, and a drain electrode;a second low-side transistor disposed on the semiconductor layer laminate, and having a gate electrode, a source electrode, and a drain electrode;a first high-side transistor disposed on the semiconductor layer laminate, and having a gate electrode, a source electrode, and a drain electrode; anda second high-side transistor disposed on the semiconductor layer laminate, and having a gate electrode, a source electrode, and a drain electrode,wherein the second low-side transistor is disposed between the first low-side transistor and the first high-side transistor,the first high-side transistor is disposed between the second low-side transistor and the second high-side transistor,the source electrode of the first low-side transistor and the source electrode of the second low-side ...

CMOS COMPATIBLE WAFER BONDING LAYER AND PROCESS

A wafer bonding layer and a process for using the same for bonding wafers are presented. The wafer bonding process includes providing a first wafer, providing a second type wafer and providing a water bonding layer. The wafer bonding layer is provided separately on a contact surface layer of the first or second wafer as part of a CMOS compatible processing recipe. 1. A wafer bonding process comprising:providing a first wafer,providing a second wafer; andproviding a wafer bonding layer, wherein the wafer bonding layer is provided separately on a contact surface layer of the first or second wafer as part of a CMOS compatible processing recipe.2. The wafer bonding process of wherein the wafer bonding layer is provided on the contact surface layer of the second wafer and the contact surface layer of the first wafer is an Aluminum layer.3. The wafer bonding process of wherein the wafer bonding layer comprises a bonding layer which is a CMOS foundry compatible material which forms a eutectic bond with an Aluminum contact surface layer of the first or second wafer.4. The wafer bonding process of wherein the wafer bonding layer comprises at least a Ge layer.5. The wafer bonding process of wherein the wafer bonding layer comprises a Ge layer and a barrier layer.6. The wafer bonding process of wherein the barrier layer comprises Ti claim 5 , TiN claim 5 , Ta claim 5 , TaN or alloys thereof.7. The wafer bonding process of wherein the Ge layer has a thickness of about 0.2-0.6 μm and barrier layer is preferably about 0.1-0.3 μm.8. The wafer bonding process of wherein the first and second wafers comprise wafers of the same type.9. The wafer bonding process of wherein the first and second wafers comprise a CMOS wafer.10. The wafer bonding process of wherein the first wafer comprises a CMOS wafer and the second wafer comprise a MEMS wafer.11. A wafer bonding layer comprising:a Ge layer over a barrier layer, wherein the harrier layer may be an electrical conductor or an electrical ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;an external connection terminal formed on the first face of the semiconductor substrate;a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal;a second electrode formed on the first face of the semiconductor substrate;an integrated circuit formed on the first face, the integrated circuit being electrically connected to the first electrode and the second electrode;a rear face electrode formed on the second face of the semiconductor substrate;a groove portion formed in the semiconductor substrate, the groove portion having an inner wall;an insulating film formed on side walls of the groove portion; anda conductive portion formed inside the groove portion on the insulating portion and electrically connected to the second electrode and the rear face electrode;wherein the integrated circuit and the first electrode are electrically disposed between the second electrode and the external connection terminal.2. The device of claim 1 , wherein the semiconductor substrate is silicon.3. The device of claim 2 , wherein:the second electrode comprises a second electrode rear face facing the first face of the semiconductor substrate;the rear face electrode comprises a rear face ...

CONDUCTIVE PASTE AND SOLAR CELL

An electrically conductive paste used to form an electrode used for electrical connection to a p-type semiconductor layer of a crystalline silicon solar cell, wherein the electrically conductive paste is able to fire through an antireflective film during firing and is capable of forming an electrode having low contact resistance on a p-type semiconductor layer. The electrically conductive paste contains (A) an electrically conductive powder, (B) Al powder or Al compound powder having an average particle diameter of 0.5 μm to 3.5 μm, (C) a glass frit and (D) an organic medium, and contains 0.5 parts by weight to 5 parts by weight of the Al powder or Al compound powder (B) based on 100 parts by weight of the electrically conductive powder (A). 1. An electrically conductive paste for forming an electrode of a solar cell , wherein the electrically conductive paste comprises:(A) an electrically conductive powder, (B) an Al powder or Al compound powder having an average particle diameter of 0.5 μm to 3.5 μm, (C) a glass frit and (D) an organic vehicle,wherein 0.5 parts by weight to 5 parts by weight of the Al powder or Al compound powder (B) based on 100 parts by weight of the electrically conductive powder (A).2. The electrically conductive paste according to claim 1 , wherein the electrically conductive powder (A) contains at least one of Ag powder claim 1 , Cu powder claim 1 , Ni powder and a mixture thereof.3. The electrically conductive paste according to claim 1 , wherein the Al compound powder (B) is an alloy powder containing Al.4. The electrically conductive paste according to claim 1 , wherein the glass frit (C) comprises at least one material selected from the group consisting of lead oxide (PbO) claim 1 , boron oxide (BO) claim 1 , silicon oxide (SiO) claim 1 , zinc oxide (ZnO) claim 1 , bismuth oxide (BiO) and aluminum oxide (AlO).5. The electrically conductive paste according to claim 1 , wherein the organic vehicle (D) comprises at least one material ...

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed. 1. An IC assembly , comprising:a package substrate having a cavity;a bridge embedded in the cavity of the package substrate, the bridge comprising silicon;a dielectric material over the bridge;a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;a first layer on the first joint, the first layer comprising nickel;a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;a second layer on the second joint, the second layer comprising nickel;a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge;a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge;a first die electrically coupled to the first joint and the first interconnect structure; anda second die electrically coupled to the second joint and the ...

HIGH FREQUENCY CAPACITOR WITH INDUCTANCE CANCELLATION

An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length. 1. An integrated circuit comprising: a first electrode with first electrode fingers extending in a first direction from a first bus, the first bus extending transversely to and connected to respective ends of the first electrode fingers; and', 'a second electrode with second electrode fingers extending in a second direction opposite the first direction from a second bus, the second bus extending transversely to and connected to respective ends of the second electrode fingers, wherein the first electrode fingers are interdigitated with the second electrode fingers, and the first bus is spaced from the second bus with the first electrode fingers and the second electrode fingers extending therebetween;, 'a first metallization layer comprising'}a second metallization layer below the first metallization layer and comprising a third electrode with third electrode fingers extending from a third bus in the first direction, the third bus extending transversely to and connected to respective ends of the third electrode fingers, wherein each of the third electrode fingers is ...

Semiconductor packaging device comprising a shield structure

Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component if the semiconductor packaging device was flipped vertically.

Semiconductor device including sense insulated-gate bipolar transistor

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

Semiconductor device

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 μm, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

High power transistors

High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of gate, drain, and source contacts in parallel. Thereby, the total gate width and the power rating of the high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a semiconductor substrate having opposed main and back surfaces; first and second electrodes in a device region of the substrate, and spaced apart from each other; a metal film on the main surface and joined to the second electrode; an air gap between part of the main surface and the metal film, enveloping the first electrode, and having an opening; a cured resin closing the opening; a liquid repellent film increasing contact angle of the resin, relative to contact angles on the substrate and the metal film; a first metal film joined to the metal film, covering the metal film and the cured resin, and joined to an outer peripheral region of the substrate, at a periphery of the device region; and a second metal film on the back surface and connected to the first electrode through a via hole penetrating the substrate. 16-. (canceled)7. A semiconductor device comprising:a semiconductor substrate having a main surface and a back surface opposite each other;first and second electrodes in a device region of the semiconductor substrate, on the main surface of the semiconductor substrate, and spaced apart from each other;an air gap forming metal film on the main surface of the semiconductor substrate and joined to the second electrode;an air gap between a part of the main surface of the semiconductor substrate and the air gap forming metal film, enveloping the first electrode, and having an opening;a cured resin closing the opening;a liquid repellent film on an internal surface facing the air gap and increasing contact angle of the resin, when in a liquid state, relative to contact angles on the semiconductor substrate and the air gap forming metal film;a first metal film joined to the air gap forming metal film, covering the air gap forming metal film and the cured resin, and joined to the semiconductor substrate in an outer peripheral region of the semiconductor substrate, at a periphery of the device region of the semiconductor substrate; ...

SEMICONDUCTOR STRUCTURE WITH AN AIR GAP

A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap. 1. A semiconductor structure with an air gap , comprising:a substrate;a dielectric stack comprising a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, and a third dielectric layer disposed on the second dielectric layer;a first conductive layer disposed in the dielectric stack;a second conductive layer disposed in the dielectric stack and spaced apart from the first conductive layer, wherein the first conductive layer and the second conductive layer are coplanar; anda cross-like-shaped air gap disposed in the dielectric stack between the first conductive layer and the second conductive layer, wherein the air gap has a widened middle portion in the second dielectric layer, a tapered upper portion in the third dielectric layer, and a tapered lower portion in the first dielectric layer, wherein the widened middle portion has a first width, the tapered upper portion has a second width, and the tapered lower portion has a third width, and wherein the first width is greater than the second width and the third width, and wherein the third width is smaller than or equal to the second width.2. The semiconductor structure with an air gap according to claim 1 , wherein the third dielectric layer comprises an extension portion that extends into the cross-like-shaped air gap and conformally covers a ...

RADIO FREQUENCY POWER DIES HAVING FLIP-CHIP ARCHITECTURES AND POWER AMPLIFIER MODULES CONTAINING THE SAME

Radio frequency (RF) power dies having flip-chip architectures are disclosed, as are power amplifier modules (PAMs) containing such RF power dies. Embodiment of the PAM include a module substrate and an RF power die, which is mounted to a surface of the module substrate in an inverted orientation. The RF power die includes, in turn, a die body having a frontside and an opposing backside, a transistor having active regions formed in the die body, and a frontside layer system formed over the die body frontside. The frontside layer system contains patterned metal layers defining first, second, and third branched electrode structures, which are electrically coupled to the active regions of the transistor. A frontside input/output interface is formed in an outer terminal portion of the frontside layer system and contains first, second, and third bond pads electrically coupled to the first, second, and third branched electrode structures, respectively.

POWER ELECTRONIC SWITCHING DEVICE WITH A THREE-DIMENSIONALLY PREFORMED INSULATION MOLDING AND A METHOD FOR ITS MANUFACTURE

A power electronic switching device has a substrate facing in a normal direction with a first and a second conductive track, and a power semiconductor component is arranged on the first conductive track by an electrically conductive connection. The power semiconductor component has a laterally surrounding edge and an edge region and a contact region on its first primary side facing away from the substrate, and with a three-dimensionally preformed insulation molding that has an overlap segment, a connection segment and an extension segment, wherein the overlap segment, starting from the edge partially overlaps the edge region of the power semiconductor component.

ELECTRONIC DEVICE

An electronic device has a substrate , a first electric element provided on a first conductor layer , a second electric element provided on the first electric element , and a connector having a base end part provided on a second conductor layer and a head part provided on a front surface electrode of the second electric element via a conductive adhesive . An area of the base end part placed on the second conductor layer is larger than an area of the head part placed on the second electric element . The base end part is located at a side of the substrate compared with the head part , and a gravity center position of the connector is at a side of the base end part of the connector 1. An electronic device comprising:a substrate;a conductor layer having a first conductor layer and a second conductor layer provided on the substrate;a first electric element provided on the first conductor layer;a second electric element provided on the first electric element; anda connector having a base end part provided on the second conductor layer and a head part integrally formed with the base end part and connected to a front surface electrode of the second electric element via a conductive adhesive,wherein an area of the base end part placed on the second conductor layer is larger than an area of the head part placed on the second electric element, andwherein the base end part is located at a side of the substrate compared with the head part, and a gravity center position of the connector is at a side of the base end part of the connector.2. The electronic device according towherein the first electric element and the second electric element are power semiconductor elements, andwherein a heating amount of the first electric element is larger than a heating amount of the second electric element.3. The electronic device claim 1 , according to claim 1 , further comprising one or more third electric elements provided above the first electric element and provided below the second ...

WELD JOINT WITH CONSTANT OVERLAP AREA

A packaged semiconductor device has a plurality of leads. A respective lead is to be welded to an electrical coupling that has a substantially rectangular end section. The end section has a width that is greater than a width of the respective lead. The respective lead is aligned within the width of the end section, such that the respective lead extends in a direction substantially perpendicular to the width of the end section. With the respective lead and the end section aligned, the respective lead is welded to the end section. 1. A method , comprising:providing a packaged semiconductor device having a plurality of leads; a substantially rectangular end section, the end section having a width greater than a width of a respective lead of the plurality of leads;', a side of the support is substantially parallel to a side of the end section that corresponds to the height of the end section; and', 'the support has a narrower width than the width of the end section;, 'a support to electrically couple the end section to an electrical bus, wherein the support joins the end section such that], 'providing an electrical coupling comprisingaligning the respective lead within the width of the end section, wherein the respective lead extends in a direction substantially perpendicular to the width of the end section; andwith the respective lead and the end section aligned, welding the respective lead to the end section.2. The method of claim 1 , wherein welding the respective lead to the end section comprises performing resistance spot welding.3. The method of claim 2 , wherein a single pulse of resistance spot welding is performed to weld the respective lead to the end section.4. The method of claim 1 , wherein the packaged semiconductor device is a discrete transistor.5. The method of claim 1 , wherein one or more corners of the end section are rounded.6. (canceled)7. (canceled)8. The method of claim 1 , wherein the electrical coupling is a first electrical coupling claim 1 , ...

Power transistor with distributed diodes

An electronic circuit is disclosed. The electronic circuit includes a distributed power switch. In some embodiments, the electronic circuit also includes one or more of a distributed gate driver, a distributed gate pulldown device, a distributed diode, and a low resistance gate and/or source connection structure. An electronic component comprising the circuit, and methods of manufacturing the circuit are also disclosed.