Leiterplatte, Hochfrequenzmodul und Radarvorrichtung

Die Erfindung bezieht sich auf eine Leiterplatte. Die Leiterplatte (10) umfasst ein Substrat (1), eine Wellenleiterleitung (2) und einen laminierten Wellenleiter (3). Die Wellenleiterleitung (2) ist zumindest teilweise auf einer ersten Oberfläche des Substrats (1) angeordnet. Die Wellenleiterleitung (2) überträgt ein Hochfrequenzsignal. Der laminierte Wellenleiter (3) ist innerhalb des Substrats (1) ausgebildet. Der laminierte Wellenleiter (3) ist mit der Wellenleiterleitung (2) elektromagnetisch gekoppelt und weist einen Ausleitungsabschnitt (3a) auf, der vom Inneren des Substrats (1) zu einer anderen Oberfläche als der ersten Oberfläche ausgeleitet ist. Der laminierte Wellenleiter (3) umfasst eine dielektrische Schicht (31), zwei Hauptleiterschichten (32) und eine Durchgangsleitergruppe (33). Die zwei Hauptleiterschichten (32) legt die dielektrische Schicht (31) in einer Dickenrichtung davon ein. In der Durchgangsleitergruppe (34) sind mehrere Durchgangsleiter (33) entlang einer Hochfrequenzsignal-Übertragungsrichtung ...

Schaltungsmodul

Miniaturisiertes SMD-Diodenpaket und Herstellungsverfahren dafür

Miniaturisiertes SMD-Diodenpaket (10), umfassend:einen Diodenchip (30a, 30b, 30c) mit einer TVS-Diode, einer Schottkydiode, einer Schaltdiode, einer Zenerdiode oder einer Gleichrichterdiode, der eine Bodenfläche aufweist, die mit einer positiven Elektrode (31) und einer negativen Elektrode (31) versehen ist;eine Bodenleiterplatte (50) aus einer Keramikplatte, einer Kunststoffplatte, einer Verbundplatte oder einer wärmeableitenden Platte;zwei Schaltkreiselektroden (56a, 56b), die separat auf der Bodenleiterplatte (50) aufgebracht sind und elektrisch mit der jeweiligen positiven Elektrode und negativen Elektrode (31) an der Bodenfläche des Diodenchips (30a, 30b, 30c) verbunden sind;eine Kapselung (75) aus einem Keramikmaterial oder einem Kunststoffmaterial zur Bildung einer integrierten Struktur mit der Bodenleiterplatte (50), um den Diodenchip (30a, 30b, 30c) und die zwei Schaltkreiselektroden (56a, 56b) zu kapseln, derart dass sich jeweils ein Ende der zwei Schaltkreiselektroden (56a, 56b ...

PACKAGE FOR AN ELECTRONIC ASSEMBLY

... 1,256,332. Component assemblies. NORTH AMERICAN ROCKWELL CORP. 11 June, 1970, No. 28398/70. Heading H1R. [Also in Division H2] A package for circuit boards 12 to 17 comprises a housing formed by walls 8 to 11, base 6 and cover 5, the walls having ridges 21 forming slots 20 mating with and supporting the boards, and conductive strips 30 to contact and interconnect edge contacts 31 on the boards. Preferably the walls overlap adjacent wall edges sequentially (Fig. 5, not shown) and strips 35, 36 of fusible metal are provided for bonding the assembly by heating. Conductive strips 30 may also be of fusible metal. As shown the cover 5 supports contact pins 18 connected to printed circuitry on its lower surface, and a socket shroud 3 accommodates cable plugs 4 making contact with pins 18.

INTEGRATED CIRCUIT PACKAGE

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Printed circuit board with test points

A method of manufacturing diodes with ceramic base and dice structure

Ceramic module for power semiconductor integrated packaging and preparation method thereof

CHIPTRÄGER SOWIE ANORDNUNG VON SOLCHEN CHIPTRÄGERN

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR COMPONENT, SEMICONDUCTOR BODY AND PROCEDURE FOR ITS PRODUCTION

CHIPTRÄGER SOWIE ANORDNUNG VON SOLCHEN CHIPTRÄGERN

SEMICONDUCTOR CHIP ARRANGEMENTS, MANUFACTURING METHODS AND COMPONENTS FOR THE SAME

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

Multichip module connected to flexible, film-like substrate

In-street integrated circuit wafer via

Semiconductor device fabrication method and semiconductor device fabrication device

INTEGRATED CIRCUIT CHIP CARRIER

A leadless chip carrier, comprises a base of plastics material having a sidewall of plastics material connected to a top surface of the base and extending around the periphery of the chip carrier so as to define a chip mounting cavity on the base. A metallization pattern formed on the base comprises tracks of electrically conductive material extending from first connecting points in the chip mounting cavity to second connecting points on the periphery of the chip carrier.

ELECTRONIC THICK FILM COMPONENT MULTIPLE TERMINAL AND METHODOF MAKING THE SAME

A method of making a plurality of monolithic thick film components (10) having multiple terminals (12, 14, 16, 18) comprising the steps of printing a plurality of components (10) in a wafer form forming a matrix of components, printing holes (20) in the matrix of components where two terminal ends meet thereby separating the terminals (12, 14, 16, 18) on each component, and dipping the terminal ends in a silver based thick film ink (26).

CHIP CARRIER.

Ceramic substrate and manufacturing method thereof

Multi-layer ceramic components and manufacturing thereof

Integrated circuit collector

Method for producing a ceramic matrix composite part, composite part, and electrical component

MOUNTING METHOD OF MICRO-ELECTRONIC COMPONENTS ON A SUPPORT AND METHOD IMPLEMENTED BY THE PRODUCT

DEVICE COMPRISING a PASTILLE OF INTEGRATED CIRCUIT SURMONTEE Of an INSULATING FLAGSTONE BEING USED AS CASE

Compact topological interconnection device - localises nodes and crossovers of complex circuit formed on single layer support with connections formed by metal strips

PROCESS OF ASSEMBLY OF ELECTRONIC MICROCOMPONENTS ON A SUPPORT AND PRODUCT REALIZABLE BY THE PROCESS

MICROWAVE PACKAGE WITH REDUCED SPACE IN SURFACE AND MOUNTAIN SUCH A CASING ON A CIRCUIT.

Packaging device for integrated circuits

Dispositif de conditionnement de circuits intégrés, caractérisé en ce qu'il comporte au moins une plaquette de circuit imprimé (11, 12) sur laquelle est fixée une plaquette de rehausse (15) comportant au moins une fenêtre, pour former avec la surface de la plaquette de circuit imprimé (12) se trouvant en regard de la fenêtre, le fond et les parois latérales d'un logement pour au moins un circuit intégré, connecté avec le circuit imprimé porté par la plaquette définissant le fond du logement à l'aide de fils conducteurs, le logement contenant le circuit intégré étant rempli d'une résine recouvrant totalement le circuit intégré, et en ce que ladite plaquette de circuit imprimé (11, 12) est découpée à sa périphérie selon une ligne de trous de traversée (23) pourvus d'un revêtement métallique (24) et connectés à des conducteurs imprimés de la plaquette, les rainures métallisées (23, 24) résultant du découpage constituant des bornes de connexion du dispositif.

Electronic component containing a capacitor

SUPPORT WITH SOLDER GLOBULE ELEMENTS AND A METHOD FOR ASSEMBLY OF SUBSTRATES WITH GLOBULE CONTACTS

MULTILAYERED CIRCUIT BOARD FOR SEMICONDUCTOR CHIP MODULE, AND METHOD OF MANUFACTURING THE SAME

SIDE BRAZE PACKAGE

Low profile integrated module interconnects

SEMICONDUCTOR DEVICE, STACKED SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

MULTI-LAYER WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE USING THE MULTI-LAYER WIRING SUBSTRATE

PACKAGE FOR SEMICONDUCTOR DEVICE AND PROCESS OF FABRICATING THE SAME

PURPOSE: A package for semiconductor device and process of fabricating the same is to provide a simple and low-cost manufacturing process by extending a wrap-around layer around the edge of die, and forming a partial electric connection between a position in front of the die and a terminal on the rear side of it before a wafer is cut into individual dies. CONSTITUTION: On a die strip a wrap around conductive polymer layer or a metal layer is formed. After a wafer is split into dice, a conductive wrap around layer is formed which connects the front side of a die to a device terminal on the rear side of it. The wrap around layer is extended around the edge of the die and the wafer is cut into individual dice. Thus, a surface-mounting semiconductor device package with a footprint of the same size as the die is manufactured at a lower cost. © KIPO 2002 ...

IC PACKAGE SYSTEM EQUIPPED WITH A DEVICE LAMINATE RAISING HEAT-DISSIPATION CAPACITY

PURPOSE: An IC package system equipped with a device laminate is provided to form a device within an opening of an electric wiring system so that a simplified device laminated process is provided in a reduced profile package. CONSTITUTION: An integrated circuit packaging method comprises: a step for providing an electric wiring system(108) including an inner lead - finger system(112) and outer lead - finger system(114); a step for laminating a first device(102), a second device(104) and a third device(106) in the interval and upper part of the electric wiring system; a step for connecting the first device and the second device to the inner lead - finger system; and a step for connecting the third device to the outer lead - finger system. © KIPO 2009 ...

OPTOELECTRONIC COMPONENT

INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING TO REDUCE A VERTICAL HEIGHT OF FINAL PACKAGES

PURPOSE: An IC package system for package stacking is provided to improve fatigue lifetime and reliability of package by implementing a package body in which flip chip ICs and bumps are embedded. CONSTITUTION: An area array substrate(102) is formed. Surface conductors(120) are mounted on the area array substrate. A molded package body(122) is formed on the area array substrate and the surface conductors. At this time, a first IC(Integrated Circuit)(110) is electrically connected to the area array substrate. A second IC(118) is positioned on the first IC. Molding compound is provided on the area array substrate, the surface conductors, and the first and second ICs. Then a step(124) is provided to the molded package body. The surface conductors are exposed by the step. The surface conductors are contacted with the area array substrate. © KIPO 2008 ...

Chip level emi shielding structure and manufacture method thereof

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE DEVICE

L'invention concerne un dispositif à semi-conducteur. Ce dernier comporte un premier substrat (10) qui comprend une surface supérieure, portant des réseaux de conducteurs interconnectés (31, 32, 33), des faces latérales et une surface inférieure. Un second substrat (40), portant un circuit électrique (41) et des plages de connexion (43) disposées sur la face de connexion (47), est monté sur le premier substrat (10) de façon que ladite face de connexion (47) soit tournée vers la surface supérieure (11) dudit premier substrat (10). Les plages de connexion (43) et le premier réseau de conducteurs (31) sont interconnectés par des bosses de soudure (45) disposées entre les deux substrats (40, 10).

COMPOSITE ELECTRONIC COMPONENTS

A component formed by providing a dielectric film, a solid electrolyte layer, and a collector layer on one surface of a porous valve metal sheet and by covering them with an insulating element, wherein a conductor to be respectively connected to first and second connection terminals is exposed to at least one surface of this insulating element, and connection bumps are formed on this conductor to connect an integrated circuit with other electronic components, thereby providing a thin composite electronic component excellent in high-frequency responsiveness.

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.

Method for manufacturing electronic component

A method for manufacturing an electronic component includes the steps of inserting tabs of a cover into through holes formed in a circuit board having mounting elements on the front surface thereof, disposing a print mask having openings at positions corresponding to the through holes on the back surface of the circuit board, and supplying solder cream to the through holes through the openings by placing the solder cream on the print mask and moving the solder cream in a predetermined direction with a squeegee. The print mask is provided with projections which project upstream in the moving direction of the solder cream in openings of the print mask, and the openings are shifted upstream in the moving direction of the solder cream. In addition, the tabs are inserted into the through holes such that the width direction of the tabs is along the moving direction of the solder cream.

Microelectronic packages with solder interconnections

A soldered assembly for a microelectronic element includes a microelectronic element, solder columns extending from a surface of the microelectronic element and terminals connected to distal ends of the columns. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may be inclined relative to the chip surface, and may contain long, columnar inclusions preferentially oriented along the lengthwise axes of the columns.

Method of manufacturing a semiconductor device and a fabrication apparatus for a semiconductor device

A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.

Ceramic edge connect process

A method for electrically connecting a surface conductor to an edge conductor on an intersecting side of a non-conductive substrate, includes the steps of forming a through-hole in the substrate, and metallizing the through-hole to form a conductive via. Then, the substrate through the via is cut to form an intersecting side. An electrical connection may be made between a surface conductor through the via to an edge conductor on the intersecting side of the substrate. A preferred embodiment further includes forming an insulating sealing plug in the via, prior to cutting the intersecting side. The above method provides an edge connection without the need to wrap a conductive conduit around the corner of the substrate. Such wrap-around conduits are vulnerable to damage during subsequent handling of the substrate.

Electronic component packaging structure and method for producing the same

An electronic component packaging structure, includes: circuit boards each having a wiring at least on a surface thereof; and an electronic component package secured between the circuit boards. The electronic component package includes at least one electronic component embedded within an electrical insulating encapsulation resin molded member made of an inorganic filler and a resin, the at least one electronic component being selected from an active component and a passive component, protruding electrodes are arranged on both faces of the electrical insulating encapsulation resin molded member, and the electronic component is connected electrically with at least a part of the protruding electrodes. This configuration allows circuit boards to be connected with each other and a high-density and high-performance structure.

Leadless chip carrier with frangible shorting bars

An integrated circuit semiconductor chip or the like is packaged on a leadless chip carrier. The chip carrier comprises a substrate with an integral coplanar extension frangibly connected to one or more sides. Each such extension has a metallized conductive area forming a shorting bar, interconnecting at least some of the metallized conductive traces formed on the substrate. The extensions with the shorting bars remain attached to the substrate while the chip is being installed to prevent damage to the chip from electrostatic discharges. After chip installation is completed, the extensions are separated from the substrate, thereby removing the interconnections between the traces. In a preferred embodiment, a scoring line along the peripheral edge of the substrate provides the frangible connection to the extension, and the extension is provided with holes along the scoring line to allow side metallization of the substrate.

Method of fabricating a vertically mountable IC package

A method of fabricating a vertically mountable integrated circuit (IC) package is presented. An integrated circuit is mounted on a printed circuit board (PCB) and electrically coupled to a bond pad on the PCB. The bond pad is coupled with a via that is embedded in the PCB. The IC, the bond pad, the via, and a portion of the PCB are singulated in order to create a vertically mountable IC package. The via is cut through cross-sectionally during singulation so as to expose a portion of the via and thereby provide a mountable area for the IC package. The IC package may be encapsulated or housed in a dielectric material. In addition, the via may be treated with a preservative or other s-uitable electroless metal plating deposition that prevents oxidation and promotes solderability.

Stacked chip assembly

A semiconductor chip assembly, comprises a first semiconductor chip having a front surface, a rear surface and contacts on the front surface and a second semiconductor chip having a front surface, a rear surface and contacts on the front surface. The rear surface of the second semiconductor chip is juxtaposed with the front surface of the first semiconductor chip. The assembly includes a first backing element having electrically conductive first terminals. The first backing element is juxtaposed with the rear surface of the first semiconductor chip so that at least some of the terminals overlie the rear surface of the first semiconductor chip. At least some of the contacts on the first and the second semiconductor chips are electrically connected to at least some of the terminals. The assembly includes a substrate having contact pads thereon. The first terminals are connected to the contact pads of the substrate. The substrate is adapted to connect the assembly with other elements of a ...

Stacked semiconductor memory device and semiconductor memory module containing the same

There is a trend to increase that area of a device requiring a memory of large capacity, which is occupied by a semiconductor memory. This trend obstructs reduction of the size of the device. The present invention contemplates to provide a memory which can have a high integration, a high density and a large capacity while minimizing the mounting area. In order to achieve this memory, the TAB (Tape Automated Bonding) of the prior art is mounted on an electrically conductive connector, and a plurality of structures composed of the TAB and the connector are stacked. Moreover, the connector mounting the TAB thereon is constructed such that the independent terminals of the stacked TABs may not be shorted.

LOW TEMPERATURE CO-FIRED CERAMICS SUBSTRATE AND SEMICONDUCTOR PACKAGE

A low-temperature co-fired ceramics (LTCC) substrate includes a plurality of substrate units and at least one cutting pattern. The cutting pattern is disposed between neighboring two of the substrate units. A semiconductor package including the LTCC substrate is also disclosed.

Semiconductor die package with semiconductor die having side electrical connection

A semiconductor die package is disclosed. In one embodiment, the semiconductor die package includes a circuit substrate including a conductive region. A semiconductor die is on the circuit substrate. The semiconductor die includes an edge and a recess at the edge. A solder joint couples the semiconductor die and the conductive region through the recess.

On Package Floating Metal/Stiffener Grounding to Mitigate RFI and SI Risks

An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.

HETERO-INTEGRATED STRUCTURE AND MEHOD OF FABRICATING THE SAME

A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

Microelectronic component and assembly having leads with offset portions

A microelectronic component comprising a dielectric layer having an opening and leads extending across the opening is disclosed. The leads have an offset portion. A method of making a microelectronic assembly comprises connecting each of the leads to a contact on a microelectronic element. A semiconductor chip assembly has a microelectronic component with an opening and leads extending across the opening. The leads are connected to contacts on a semiconductor chip and have at least one twisted portion.

Semiconductor device having wire studs as vertical interconnect in FO-WLP

A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Embedded electronic packaging and associated methods

An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.

3-D STACKING SEMICONDUCTOR ASSEMBLY HAVING HEAT DISSIPATION CHARACTERISTICS

A semiconductor assembly having heat dissipation characteristics includes stacked semiconductor chips thermally conductible to a thermal pad of an interconnect substrate and electrically connected to the interconnect substrate through bonding wire. The bonding wires extending from a primary routing circuitry in between the stacked chips can accommodate the height difference between the stacked chips and the interconnect substrate. These wires can also effectively compensate for the thermal expansion mismatch between the stacked chips and the interconnect substrate, thereby allowing a higher manufacturing yield and better reliability. 1. A three-dimensional semiconductor assembly , comprising:a stacked semiconductor subassembly that includes a primary routing circuitry, a first device and a second device, wherein (i) the primary routing circuitry has a first surface in a first direction, a second surface in an opposite second direction, first conductive pads at the first surface, and second conductive pads at the second surface electrically connected to the first conductive pads, (ii) the first device is disposed over the first surface of the primary routing circuitry and electrically coupled to the primary routing circuitry through the first conductive pads, and (iii) the second device is disposed over the second surface of the primary routing circuitry and electrically coupled to the primary routing circuitry through the second conductive pads;an interconnect substrate that includes a thermal pad and a surrounding layer, wherein (i) the thermal pad has a front side facing in the first direction and the front side of the thermal pad is attached to the second device by a thermal conducting material, (ii) the surrounding layer has a dielectric layer and contact pads, (iii) the dielectric layer is bonded to sidewalls of the thermal pad and has a front surface facing in the first direction, and (iv) the contact pads are disposed on the front surface of the dielectric ...

Method Of Fabricating Low Profile Leaded Semiconductor Package

In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed, in particular a method of fabricating a package including an exposed die pad. 1. A method of fabricating a semiconductor package including an exposed die pad , the method comprising:providing a metal piece, the metal piece having a thickness;thinning the metal piece at a location where a cantilever segment of a lead is to be formed while leaving the thickness of the metal piece unchanged in a location where the die pad is to be formed;thinning the metal piece at a location where a foot of the lead is to be formed; andsevering the metal piece between the location of the die pad and the location of the cantilever segment of the lead.2. The method of wherein thinning the metal piece at a location where a foot of the lead is to be formed and severing the metal piece between the location of the die pad and the location of the cantilever segment of the lead are performed in a single process step.3. The method of wherein thinning a metal piece at the location where the cantilever segment of a lead is to be formed comprises thinning the metal piece at a location of a gap between the die pad and the cantilever segment of the lead.4. The method of wherein thinning the metal piece at locations where the cantilever segment of the lead and the gap between the die pad and the cantilever segment of the lead are to be formed comprises:depositing a first mask layer on a first side of the metal piece;forming an opening in the first mask layer corresponding to the locations where the cantilever segment of the lead and the gap between the die pad and the ...

Method of manufacturing light emitting device with light-transmissive members

A light emitting device includes a light emitting element; a light-transmissive member that has a lower surface positioned inside a peripheral edge of an upper surface of the light emitting element in plan view, a first lateral surface extending from the lower surface and having at least one inclined surface that is inclined with respect to the upper surface of the light emitting element, and a second lateral surface positioned above and outside the first lateral surface; a light-transmissive adhesive member positioned inside the second lateral surface in plan view, wherein the adhesive member adheres the upper surface of the light emitting element and the lower surface of the light-transmissive member to each other and covers the first lateral surface; and a light-reflective member covering the second lateral surface.

Arrangements to supply power to semiconductor package

Arrangements are used to supply power to a semiconductor package.

SEMICONDUCTOR PACKAGES

A semiconductor package includes a semiconductor chip and a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines, opening holes located between remaining portions of the second group of conductive lines to separate the second group of conductive lines from each other.

3D electrical integration using component carrier edge connections to a 2D contact array

... 3D electrical integration is provided by connecting several component carriers to a single substrate using contacts at the edges of the component carriers making contact to a 2D contact array (e.g., a ball grid array or the like) on the substrate. The resulting integration of components on the component carriers is 3D, thereby providing much higher integration density than in 2D approaches.

Surface-mount thin-film components having terminals configured for visual inspection

A surface-mountable component is disclosed. The surface-mountable component may include a substrate having a side surface and a top surface that is perpendicular to the side surface. The component may include an element layer formed on the top surface of the substrate. The element layer may include a thin-film element and a contact pad electrically connected with the thin-film element. The contact pad may extend to the side surface of the substrate. The component may include a terminal that is electrically connected with the contact pad at a connection area. The connection area may be parallel with the top surface of the substrate. The terminal may have a visible edge surface that is approximately aligned with the side surface of the substrate. The visible edge surface may be visible for inspection when the surface-mountable component is mounted to a mounting surface.

SEMICONDUCTOR CHIP ASSEMBLIES, METHODS OF MAKING SAME AND COMPONENTS FOR SAME

Semiconductor chip assemblies incorporating flexible, sheet-like elements (42) having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals (48) on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer (42) interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with test probe assembly so as to permit reliable engagement despite tolerances.

PACKAGE FOR SEMICONDUCTOR DEVICE

PURPOSE: To assure stabilization of quality and automation of assembling operations while eliminating any step difference by a method wherein an insulator with excellent adhesive property to the backside of leadless ceramics package is formed on the part other than a leading pattern region on the backside of ceramics substrate of package. CONSTITUTION: A leading pattern 12 is provided on the backside 11 of a ceramics substrate 13 equivalent to that of package and then an insulator 15 is provided on the part corresponding to an element fixing part while a semiconductor element is mounted on the surface of substrate 13 to be wired and then sealed up with a cover 14. The thickness of insulator 15 shall equal or exceed the thickness of leading pattern 12. In such a constitution, the insulator 15 may be brought into direct contact with a heating part of assembling unit to improve the adhesive property of element fixing part to the semiconductor element so that normal vacuum adsorption may be ...

IC PACKAGE AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide an IC package for improving productivity and to provide a manufacturing method. SOLUTION: An exposed I/O terminal is installed at the side of the IC package. The IC package is provided with an IC chip loading substrate, an IC chip loaded on the IC chip loading substrate and a sealing member sealing the IC chip. A groove part where a conductor being a part of the I/O terminal is formed at the side of the chip loading substrate and the sealing member. One end of the groove part is blocked by a cover board member and the sealing member covers the IC chip and the cover board member. Ceramic material can be used as the material of the chip loading substrate and the cover board member. The chip loading substrate is constituted of the printed wiring board and the cover board member can be formed by a solder resist film. COPYRIGHT: (C)2001,JPO ...

Verfahren zum Herstellen eines Substrates mit einem Hohlraum

Verfahren zum Herstellen eines Substrates, wobei das Substrat einen Hohlraum aufweist, wobei das Verfahren Folgendes enthält: (a) Bilden einer Barriere (360) um einen vorbestimmten Bereich, in welchem der Hohlraum zu bilden ist, auf einem mit einer Kupferfolie laminierten Master (310), wobei eine innere Schaltung (320) in dem mit einer Kupferfolie laminierten Master (310) gebildet ist; (b) Auftragen eines Duroplasts (610) in dem Bereich, in welchem der Hohlraum zu bilden ist; (c) Laminieren einer dielektrischen Schicht (330) und einer Kupferfolienschicht (340) auf den mit einer Kupferfolie laminierten Master (310), auf welchem der Duroplast (610) aufgetragen ist; (d) Pressen der laminierten, dielektrischen Schicht (330) und Kupferfolienschicht (340) unter Verwendung einer Pressplatte (710, 720), auf welcher ein hervorstehendes Teil in einem Bereich gebildet ist, welcher dem Bereich entspricht, in welchem der Hohlraum zu bilden ist, wobei das dielektrische Material der dielektrischen Schicht ...

VERFAHREN ZUM AUFBRINGEN EINER GLEICHMAESSIGEN GOLDPLATTIERUNG AN KERAMISCHEN SUBSTRATEN

Surface mountable opto-electronic device e.g. LED for backlighting, has body with surface having recesses to mount device, where electrical contacts are provided on surface including portions formed on inner surface of recesses

The device has a body (402) with a surface having recesses (420,421) to mount the device. Electrical contacts (404,406) provided on the surface include portions forming a portion of one inner surface of the recesses. The recesses comprise of a diagonal portion extending diagonally away from the surface. A parallel portion extends parallel to the surface and is connected to the end of the diagonal portion.

Chipanordnungen

Chipanordnung (310), welche aufweist:eine Leiterplatte (362), welche aufweist:• ein Durchgangsloch (364), das in der Leiterplatte (362) ausgebildet ist,• und ein oder mehrere Leiterplattenkontaktgebiete (366S, 366G, 366D) , die in der Nähe des Durchgangslochs (364) angeordnet sind, undein Chipgehäuse (210, 160) mit einem Chip (104), das innerhalb des Durchgangslochs (364) angeordnet ist, wobei mindestens ein Leiterplattenkontaktgebiet (366S, 366G) elektrisch mit einem oder mit mehreren elektrisch leitenden Verbindungsstrukturen (144, 146) verbunden ist, die über einer Oberseite (152) des Chipgehäuses (210, 160) ausgebildet sind und in elektrischem Kontakt mit einer Chipoberseite (122) stehen, undwobei mindestens ein weiteres Leiterplattenkontaktgebiet (366D) elektrisch mit einer elektrisch leitenden Verbindungsstruktur (148) verbunden ist, die über einer Unterseite (154) des Chipgehäuses (210, 160) ausgebildet ist und in elektrischem Kontakt mit einer Chipunterseite (124) steht,wobei das ...

Keramisches Multilayersubstrat und Verfahren zu dessen Herstellung

Es wird ein keramisches Multilayersubstrat beschrieben, bei dem die inneren Verbindungsteile, die in den inneren Mustern ausgebildet sind, breit genug sind, um einen äußeren Anschluss zu umgeben, sowie ein Verfahren zur Herstellung des Substrats, wobei eine stabile Verbindung zwischen den inneren Mustern und dem äußeren Anschluss erzielt wird und wobei die Verbindung auch dann aufrechterhalten wird, wenn in dem Verfahrensschritt zum Ausbilden eines Durchgangslochs auf dem Substrat ein Fehler auftritt. Das keramische Multilayersubstrat umfasst eine Mehrzahl von vertikal gestapelten keramischen Substraten, jedes Substrat hat eine festgelegte Dicke; Musterschichten, die auf Flächen der keramischen Substrate ausgebildet sind, um Schaltkreiselemente zu bilden; äußere Anschlüsse, die auf Seitenflächen der gestapelten keramischen Substrate ausgebildet sind; und innere Verbindungsteile, jedes von diesen ist auf einem Teil der Musterschicht ausgebildet und an dem äußeren Anschluss angeschlossen, ...

Leadless chip carrier

A leadless chip carrier 60 comprises a thermal pad 62 for attaching to a printed circuit board (PCB) and an integrated circuit 61 electrically connected to a plurality of electrical lead frame pads 64 for connection to a plurality of corresponding pads on the PCB. The leadless chip carrier further comprises a non-collapsible conductive shim 66 bonded to a first surface of the thermal pad and each of the plurality of electrical lead frame pads is attached to a volume of solder 601, 602. The conductive shim or spacer under the chip provides a stand-off between the thermal pad and the PCB and improves the integrity of a joint between the thermal pad and the PCB. The shim can either help conduct heat away from the chip or act as a ground plane for the integrated circuit.

Ceramic multilayer substrate and method for manufacturing the same

Electrostatic discharge protection substrate for fingerprint scanner

An ESD protection substrate comprising a serrated edge surface which comprises at least one plated castellation 30 capable of conducting electrostatic discharge; a bottom surface; a top surface; and a circuit trace 34 provided on at least one of the top or bottom surface, the circuit trace 34 electrically connected to the at least one plated castellation 30. The substrate is preferably provided with a sensing circuit for receiving touch or press from a part of a living body, more preferably a finger print, where the sensing circuit is coupled to one of the top or bottom surface. A method is also disclosed, the method comprising punching holes along at least a portion of a perimeter of each of a plurality of substrates in a substrate array, plating the holes with a conductive material, and cutting each of the plurality of substrates along cut lines that bisect at least some of the holes.

Surface-mount package with side terminal

Multilayer ceramic substrate with internal connection part wider than external terminal

A ceramic multilayer substrate has internal connection parts 240 formed in the internal patterns 9 that are broad enough to surround the external terminal 220, and to stably achieve a connection between the internal patterns and the external terminal and maintain the connection even in the case of an error occurring in a step for forming a through hole on the substrate. The ceramic multilayer substrate comprises a plurality of ceramic substrates stacked vertically, pattern layers formed on surfaces of the ceramic substrates so as to form circuit elements; external terminals formed on side surfaces of the stacked ceramic substrates; and internal connection parts 240, each of which is formed on a part of the pattern layer, connected to the external terminal so as to exchange signals with the outside and being broad enough to surround the external terminal. In a modified embodiment (figs 3, 4) the internal connection part has a width greater than the terminal, but does not surround the terminal ...

Leadless chip carrier

ELECTRICAL INTERCONNECTION FOR CERAMIC ARRAYS

... 1482012 Component packages; printed circuits MINNESOTA MINING & MFG CO 3 Oct 1974 [4 Oot 1973] 42997/74 Headings H1K and H1R In a batch process for manufacturing a plurality of ceramic mounting pieces for electronic component packages, the mounting pieces are constituted by repeating units in a ceramic sheet structure, and all metallic regions to be gold-plated are electrically connected across lines of eventual severance and also to a common metallized region for supplying the plating current. Conductive regions where plating is not required may be masked. As shown, the sheet structure comprises laminated ceramic sheets 70, 72, 74 each bearing appropriate screened conductor patterns, providing in particular mounting pads 32, internal terminals 40 connected via conductors 46 to external terminals 42, and current collectors in the form of marginal metallizations 30, 48, 54. Aligned perforations 26 provide lines of severance and also electrical connection between layers because of their at ...

Method for Producing an Electrical Circuit and Electrical Circuit

A method for producing an electrical circuit includes providing a main printed circuit board having a plurality of metalized plated-through holes through the main printed circuit board along at least one separating line between adjacent printed circuit board regions of the main printed circuit board. Each printed circuit board region has electrical contact connection pads on at least the main surface of the printed circuit board region that is to be populated, electrical lines for connection between the plurality of plated-through holes and the contact connection pads, and at least one semiconductor chip electrically contact-connected by means of the contact connection pads. The main printed circuit board is covered with a potting compound across the printed circuit board regions with the semiconductor chips.

Electromagnetic interference shielding structure for integrated circuit substrate and method for fabricating the same

An electromagnetic interference (EMI) shielding structure for integrated circuit (IC) substrate includes a plurality of conductive contacts, a covering layer, and a sputtered layer. The conductive contacts are formed at the perimeter of a chip area on the IC substrate. The covering layer is formed on the conductive contacts and covers the chip area. A groove is formed on the covering layer for exposing the conductive contacts. The sputtered layer is formed on the covering layer and connected to the conductive contacts. The EMI shielding structure can restrain the interference in the chip area.

Module substrate, module-substrate manufacturing method, and terminal connection substrate

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad

An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.

Light-emitting device

A light-emitting device includes a rectangular substrate, a through-holes that is in a shape of a quarter of circle provided in two corners or four corners of the substrate, a pair of electrodes provided along short sides of the substrate and electrically connected to the through-hole(s) that is adjacently disposed to each of the electrodes. Each of the through-holes is covered by a cover that is in a shape of a quarter of circle.

Methods and Apparatus for Thinner Package on Package Structures

Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

Plated terminals with routing interconnections semiconductor device

A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate. 1. A chip package , comprising:a semiconductor substrate having an upper surface and a lower surface;a device region or sensing region defined in the semiconductor substrate;a conducting pad located on the upper surface of the semiconductor substrate;at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate;a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; andan insulating layer located between the conducting layer and the semiconductor substrate.2. The chip package as claimed in claim 1 , wherein at least a portion of the sidewall of the semiconductor substrate inclines toward the upper surface of the semiconductor substrate.3. The chip package as claimed in claim 1 , wherein the device region or sensing region is substantially and directly exposed.4. The chip package as claimed in claim 1 , further comprising a circuit board claim 1 , wherein the semiconductor substrate is disposed overlying the circuit board ...

Stacked microelectronic packages having patterened sidewall conductors and methods for the fabrication thereof

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Through-silicon via with injection molded fill

Embodiments are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming a conductive fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the conductive fill are substantially coplanar with a front surface of the substrate.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate. 1. A packaged microelectronic device , comprising:an interposer substrate having a first side with a plurality of interposer contacts and a second side opposite the first side, the second side including a plurality of interposer pads arranged in an array corresponding to a standard JEDEC pinout;a microelectronic die attached and electrically coupled to the interposer substrate;a casing covering the die and at least a portion of the interposer substrate, wherein the casing has a thickness and a top facing away from the interposer substrate; anda plurality of electrically conductive through-casing interconnects in contact with and projecting from corresponding interposer contacts, wherein the through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing, and wherein the through-casing interconnects are at least partially encapsulated in the casing,wherein the through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to ...

FAN-OUT PACKAGE STRUCTURE AND METHOD

A method includes attaching a semiconductor structure on a carrier, depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer, exposing a first photo-sensitive material layer and a second photo-sensitive material layer to light, developing the first photo-sensitive material layer and the second photo-sensitive material layer to form an opening having a first portion in the first photo-sensitive material layer and a second portion in the second photo-sensitive material layer, wherein a width of the second portion is greater than a width of the first portion, filling the opening with a conductive material to form a via in the first photo-sensitive material layer and a redistribution layer in the second photo-sensitive material layer and forming a bump over the redistribution layer. 1. A method comprising:attaching a semiconductor structure on a carrier, wherein the semiconductor structure comprises a plurality of connectors;depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer;depositing a first photo-sensitive material layer on the molding compound layer;exposing the first photo-sensitive material layer to light according to a first pattern;depositing a second photo-sensitive material layer on the first photo-sensitive material layer;exposing the second photo-sensitive material layer to light according to a second pattern;developing the first photo-sensitive material layer and the second photo-sensitive material layer to form a plurality of openings;filling the plurality of openings with a conductive material to form a first redistribution layer; andforming a plurality of bumps over the first redistribution layer.2. The method of claim 1 , further comprising:after the step of depositing the molding compound layer over the carrier, applying a grinding process to the molding compound layer until a top surface of the ...

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process. 1. A semiconductor package comprising:a redistribution layer;at least one die, disposed on the redistribution layer;a molding compound, disposed on the redistribution layer and encapsulating the at least one die;through interlayer vias, disposed on the redistribution layer and penetrating the molding compound, wherein the through interlayer vias are electrically connected to the redistribution layer and the at least one die;a protection film, disposed on the molding compound and the at least one die, wherein the protection film located on the at least one die includes a trench pattern with trenches of substantially flat bottoms;connectors, disposed on the through interlayer vias; andconductive elements, electrically connected to the redistribution layer.2. The semiconductor package as claimed in claim 1 , further comprising a dielectric material layer disposed on the molding compound claim 1 , on the at least one die and disposed between the molding compound claim 1 , the at least one die and the protection film claim 1 , wherein the dielectric material layer exposes the through interlayer vias.3. The semiconductor package as claimed in claim 2 , wherein the dielectric material layer located on the molding compound includes first openings and the connectors located within the first openings are in direct contact with the through interlayer vias.4. The semiconductor package as claimed in claim 3 ...

Integrated circuit system and packaging method therefor

An integrated circuit system and a packaging method therefor are disclosed. The method includes providing a first carrier and a second carrier oppositely, with a first device set of the first carrier and a second device set of the second carrier both located between the first and second carriers, providing a molding material between the first and second carriers to make the first and second device sets respectively in contact with the molding material, curing the material to make the first and second device sets respectively mounted at two sides of the molding material, making the first and second carriers detached from the first device set and the molding material and from the second device set and the molding material respectively; and forming connection holes in the molding material and fabricating a conductive layer which extend into the connection holes to electrically connect the first and second device sets. 1. An integrated circuit system packaging method , comprising steps of: providing a first carrier and a second carrier opposite to each other, wherein a first device set of the first carrier and a second device set of the second carrier are both located between the first carrier and the second carrier,', 'providing a molding material between the first carrier and the second carrier, wherein the first device set and the second device set are respectively in contact with the molding material, and', 'curing the molding material, so that the first device set and the second device set are respectively mounted at two sides of the molding material;, 'curing, comprising 'detaching the first carrier from the first device set and the molding material, and detaching the second carrier detached from the second device set and the molding material; and', 'detaching, comprising forming connection holes in the molding material, and', 'forming a conductive layer in such a way that the conductive layer extends into the connection holes, wherein the conductive layer enables ...

TRANSISTOR PACKAGES

In accordance with another aspect, a power switch assembly includes a transistor package including a die case, a source bus tab extending from a first side of the die case, a drain bus tab extending from a second side of the die case, a first power bus rail operatively connected to the source bus tab of the transistor package and a second power bus rail operatively connected to the drain bus tab of the transistor package. 1. A transistor package comprising:a die case having a top surface and a bottom surface opposite from the top surface;a source bus tab extending from a first side of the die case, wherein a portion of the source bus tab that extends from the first side is spaced apart from the top surface and the bottom surface in a direction perpendicular to the top surface;a drain bus tab extending from a second side of the die case opposite from the first side, wherein a portion of the drain bus tab that extends from the second side is spaced apart from the top surface and the bottom surface in the direction perpendicular to the top surface; anda gate extending from a third side of the die case, wherein the third side of the die case is perpendicular to both the first side of the die case and the second side of the die case, wherein a portion of the gate that extends from the third side is spaced apart from the top surface and the bottom surface in the direction perpendicular to the top surface, and wherein the portions of the source bus tab and the drain bus tab that extend from the die case are spaced apart from an exterior surface of the third side in a direction perpendicular to the exterior surface of the third side.2. The transistor package as recited in claim 1 , wherein the source bus tab and the drain bus tab have at least one of the same length claim 1 , the same width or the same thickness.3. (canceled)4. The transistor package as recited in claim 1 , wherein at least one of the source bus tab or the drain bus tab include a first element and a second ...

DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

Disclosed herein are a display device with a reduced bezel area and a method for fabricating the same. A wiring electrode disposed on a substrate is electrically connected to a connection electrode disposed on an inclined surface of a circuit board in contact with the substrate, and the connection electrode is electrically connected to a circuit wiring disposed on the circuit board. Therefore, an inactive area such as a pad portion for connecting the substrate with the circuit board is not required, such that the bezel area can be reduced. 1. A display device comprising:a substrate with light-emitting elements and wiring electrodes for supplying driving signals and current thereto;a circuit board disposed on the substrate and covering a part of the wiring electrodes, a plurality of circuit wirings being disposed on a first surface of the circuit board; anda plurality of connection electrodes respectively connecting the wiring electrodes to the circuit wirings,wherein the circuit board has an inclined surface and the connection electrodes extend on the inclined surface to the first surface of the circuit board.2. The display device of claim 1 , wherein the inclined surface is disposed between the first surface and the substrate and/or wherein the first surface extends in parallel to the substrate.3. The display device of claim 1 , further comprising: a buffer layer at the inclined surface of the circuit board for compensating a step difference between the circuit board and the substrate.4. The display device of claim 3 , wherein the buffer layer has a tapered shape with an inclination angle with respect to the substrate corresponding to that of the inclined surface of the circuit board.5. The display device of claim 1 , wherein a reflective layer is disposed between the circuit board and the substrate.6. The display device of claim 1 , wherein the connection electrodes and/or at least one dummy electrode extend from the substrate on the inclined surface to the first ...

SURFACE MOUNT PACKAGE FOR A SEMICONDUCTOR DEVICE

A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension. 1. A lead of a semiconductor package , comprising:a central segment having a first side and a second side;a first extension from a portion of the first side;a second extension from a portion of the second side; anda recess extending through a portion of the central segment, the first extension and the second extension.2. The lead as recited in claim 1 , wherein the first extension intersects a junction between the central segment and the recess on the first side of the central segment.3. The lead as recited in claim 1 , wherein the central segment has a thickness greater than a thickness of the first extension and the second extension.4. The lead as recited in claim 1 , wherein a thickness of the first extension is substantially equal to a thickness of the second extension.5. The lead as recited in claim 1 , wherein the recess comprises a concave shape.6. The lead as recited in claim 1 , wherein the recess comprises a step shape.7. The lead as recited in claim 1 , wherein the first extension of the lead includes an angular edge opposite the recess.8. A package claim 1 , comprising:a semiconductor die attached to a die attach pad; and a central segment having a first side and a second side;', 'a first extension from a portion of the first side;', 'a second extension from a portion of the second side; and', 'a recess extending through a portion of the central segment, the first extension and the second extension of the lead, a portion of the lead being exposed from a molding compound covering the semiconductor die., 'a lead coupled to ...

WIRING BOARD AND MEMORY SYSTEM INCLUDING THE SAME

A memory system includes a package having a memory device, and a wiring board to which the package is attached. The wiring board includes a first region and a second region separable from the first region. The first region may conform in terms of its dimensions and other physical characteristics to a first form factor of the memory system, and the first and second regions collectively may conform in the same way to a second form factor of the memory system. 1. A memory system , comprising:a package comprising a memory device of the memory system; anda wiring board to which the package is mounted, the wiring board comprising a substrate and at least one layer of a conductive pattern integral with the substrate, andwherein the memory system has a first region, a second region, and at least one boundary region including a first boundary region between the first region and the second region,the wiring board is frangible at or physically divided along the first boundary region,the at least one layer comprises a conductive pattern extending along an outer surface of the substrate in the first region, and the package is confined to the first region as attached to the conductive pattern, andthe first region conforms to a first form factor of the memory system, and a third region consisting of the first and second regions together conform to a second form factor of the memory system.2. The memory system according to claim 1 , further comprising a port in the first region and comprising a plurality of external electrical conductors claim 1 , and wherein the port conforms to the first and second form factors.3. The memory system according to claim 2 , further comprising a memory controller which controls the memory device claim 2 , the memory controller being electrically connected to the wiring board and confined to the first region of the memory system.4. The memory system according to claim 1 , wherein the second region comprises a plurality of sub-regions claim 1 , the at ...

Ceramic module for power semiconductor integrated packaging and preparation method thereof

A ceramic module for power semiconductor integrated packaging and a preparation method thereof are disclosed. The ceramic module includes a ceramic substrate and an integrated metal dam layer. By providing the integral metal dam layer on the upper surface of the ceramic substrate and forming cavities around die bonding regions, the semiconductor chip can be hermetically sealed. By providing a heat dissipation layer on the lower surface of the ceramic substrate, the heat generated by the semiconductor chip can be quickly conducted to the outside. The product has a simple production process and high product consistency.

INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME

Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation. A fabricating process of the integrated fan-out package is also provided. 1. An integrated fan-out package , comprising:a die;a first redistribution circuit structure and a second redistribution circuit structure respectively over a back surface and an active surface of the die to sandwich the die;a plurality of solder joints, aside the die and connected to the first redistribution circuit structure;a plurality of conductive posts, on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints; andan insulating encapsulation, encapsulating a plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, a plurality of sidewalls of first redistribution conductive layers of the first redistribution circuit structure, and a plurality of sidewalls of the solder joints,wherein upper surfaces of the conductive posts are partially covered by a bottommost dielectric layer of the second redistribution circuit structure.2. The integrated fan-out ...

SEMICONDUCTOR PACKAGE WITH CONFORMAL EM SHIELDING STRUCTURE AND MANUFACTURING METHOD OF SAME

A semiconductor package includes a substrate having a front side, a bottom side, and a sidewall along a perimeter of the substrate, a plurality of solder pads on the bottom side, at least one EM shielding contact structure on the bottom side and partially exposed on the sidewall, a semiconductor device mounted on the front side, a mold compound on the front side and covering the semiconductor device, and an EM shielding layer conformally covering the mold compound and the sidewall. The EM shielding layer is in direct contact with the exposed portion of the EM shielding contact structure on the sidewall. 1. A semiconductor package , comprising:a substrate having a front side, a bottom side, and a sidewall along a perimeter of the substrate;a plurality of solder pads on the bottom side;at least one electromagnetic (EM) shielding contact structure on the bottom side and partially exposed from the sidewall;a semiconductor device mounted on the front side;a mold compound on the front side and covering the semiconductor device; andan EM shielding layer conformally covering the mold compound and the sidewall, wherein the EM shielding layer is in direct contact with a portion of the EM shielding contact structure exposed from the sidewall.2. The semiconductor package according to claim 1 , wherein the substrate comprises a conductive via claim 1 , a ground pad claim 1 , and a ground layer claim 1 , wherein the conductive via electrically connects the ground pad to the ground layer.3. The semiconductor package according to claim 2 , wherein the EM shielding contact structure is electrically connected to the ground layer through the conductive via.4. The semiconductor package according to claim 2 , wherein the conductive via electrically connects the ground pad to the ground layer claim 2 , and the EM shielding contact structure and the ground pad are structurally and electrically independent and separated from each other.5. The semiconductor package according to further ...

Electronic component-use package and piezoelectric device

An electronic component-use package includes a base that holds an electronic component element, and terminal electrodes formed on a bottom surface of the base. The terminal electrodes have chamfered parts facing corner parts of the base bottom surface and having angles of chamfer ranging in ±10 degrees to a reference line. The reference line is a perpendicular line to a straight line that connects the corner parts of the base bottom surface to a central part on one side of the terminal electrode in proximity to a center point of the base bottom surface, the reference line L 8 passing through the chamfered parts.

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. 1. A package comprising:a chip having a frontside and a backside, the chip comprising four corner areas;a die bonded to the frontside of the chip by a first set of conductive connectors;a molding layer on the frontside of the chip and surrounding sidewalls of the die;a dam structure in each of the four corner areas on the backside of the chip, each of the dam structures being disposed a distance from an edge of the chip, each of the dam structures being circular in a plane parallel to the backside of the chip; anda second set of conductive connectors on the backside of the chip.2. The package of claim 1 , wherein the dam structure is electrically isolated from the chip.3. The package of claim 1 , wherein a distance between the frontside of the chip and a surface of the molding layer distal the frontside of the chip is greater than a distance between the frontside of the chip and a surface of the die distal the frontside of the chip.4. The package of claim 1 , further comprising a through via extending through the chip.5. The package of claim 4 , wherein the through via comprises a metal via and a barrier layer lining sidewalls of the metal via.6. The package of claim 5 , further comprising an insulation layer between the chip and the through via claim 5 , the insulation layer comprising an oxide.7. The package of claim 1 , wherein the dam structure comprises a polymer material.8. The package of claim 1 , wherein a diameter of the dam structure is less than a diameter of each of the conductive ...

PICTURE FRAME STIFFENERS FOR MICROELECTRONIC PACKAGES

A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package. 1. A method of fabricating a microelectronic package , comprising:forming a microelectronic die having an active surface and an opposing back surface;attaching the microelectronic die active surface to a microelectronic substrate;forming a picture frame stiffener having an opening formed therethrough;placing the picture frame stiffener on a release film;disposing a mold material over the picture frame stiffener and the release film;inserting the microelectronic die into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening;removing the release film; andremoving a portion of the mold material extending over the microelectronic die back surface.2. The method of claim 1 , wherein forming the picture frame stiffener comprises forming a layered structure having at least two material layers having differing coefficients of thermal expansion.3. The method of claim 1 , wherein forming the picture frame stiffener comprises forming a base portion and a rigidity projection extending from a first ...

Semiconductor package, semiconductor device using the same and manufacturing method thereof

A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

Multi-surface edge pads for vertical mount packages and methods of making package stacks

Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard. 1. An apparatus , comprising:a substrate;a first surface of the substrate for mounting an electronic component or an electronic circuit;a second surface of the substrate for mounting the substrate to a motherboard or to a second substrate;a notch in the substrate at an edge, a corner, or an intersection between the first surface and the second surface;a metal adhered or bonded to at least a part of the notch and electrically coupled to the electronic component or the electronic circuit; anda solder in the notch attaching the substrate to the motherboard or to the second substrate.2. The apparatus of claim 1 , wherein the notch exposes or creates at least one additional surface of the substrate; andwherein the solder attaches the at least one additional surface of the substrate to the motherboard or to the other substrate.3. The apparatus of claim 1 , wherein the first surface of the substrate is vertical with respect to a horizontal motherboard;wherein the second surface is parallel to ...

Semiconductor package including a rewiring layer with an embedded chip

A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

IC CHIP PACKAGE WITH DUMMY SOLDER STRUCTURE UNDER CORNER, AND RELATED METHOD

An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively. 1. An integrated circuit (IC) chip package comprising:a substrate comprising first mounting pads unconnected to electrical connections in the substrate; anda wafer comprising an IC chip arranged on the substrate, the wafer comprising second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.2. The IC chip package of further comprising a solder material disposed on the first mounting pads that bonds the first and second mounting pads.3. The IC chip package of further comprising an underfill disposed between the IC chip and the substrate wherein the solder material prevents the underfill from being positioned directly underneath the corners of the IC chip.4. The IC chip package of wherein the wafer comprises dicing channels along sides of the IC chip and the second mounting pads extend into the dicing channels; and wherein when the IC chip is diced claim 1 , portions of the second mounting pads are diced and remainders of the second mounting pads are coplanar with the sides of the IC chip.5. The IC chip package of wherein the first mounting pads are aligned with the second mounting pads.6. The IC chip package of wherein the first mounting pads extend laterally outwards from sides of the IC chip.7. The IC chip package of wherein each of the substrate and the IC chip comprises ...

FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. 1. An electronic device of a flip-chip type comprising:at least one chip carrier having a carrier surface, the at least one chip carrier comprising one or more contact elements of electrically conductive material on the carrier surface;at least one integrated circuit chip having a chip surface, the at least one integrated circuit chip comprising one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element;solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements; andwherein the at least one chip carrier comprises one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.2. The electronic device according to claim 1 , wherein the contact elements and the dissipation elements are portions of a ...

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process. 1. A manufacturing method , comprising:providing a carrier having a buffer layer thereon;providing sub-packages each having a die and a through interlayer via on the buffer layer and encapsulating the sub-packages with a molding compound;removing the carrier to expose the buffer layer;removing the buffer layer to at least expose the through interlayer vias;printing a protection film over the molding compound and the backsides of the dies, wherein the protection film is printed over the backsides of the dies with trenches concave into the protection film without penetrating through the protection film;forming connectors on the through interlayer vias; andperforming a dicing process cutting through the molding compound.2. The method as claimed in claim 1 , wherein removing the buffer layer comprises partially removing the buffer layer to form a dielectric pattern fully covering backsides of the dies and exposing the through interlayer vias.3. The method as claimed in claim 2 , wherein removing the buffer layer comprises laser drilling through the buffer layer to form openings exposing the through interlayer vias and to form the dielectric pattern.4. The method as claimed in claim 1 , wherein removing the buffer layer comprises completely removing the buffer layer to expose the backsides of the dies and the molding compound.5. The method as claimed in claim 1 , wherein printing a protection film ...

Method of forming a packaged semiconductor device having enhanced wettable flank and structure

A packaged electronic device includes a substrate having a lead. The lead includes an outward facing side surface having a first height, and an inward facing side surface having a second height that is less than the first height. An electronic device is electrically connected to the lead. A package body encapsulates the electronic device and portions of the lead. The outward facing side surface is exposed through a side surface of the package body, and the inward facing side surface is encapsulated by the package body. A conductive layer is disposed on the outward facing side surface to provide the packaged electronic device with an enhanced wettable flank. In one embodiment, the electronic device is electrically connected to a thick terminal portion having the outward facing side surface. In another embodiment, the electronic device is electrically connected to a thin terminal portion having the inward facing side surface.

Edge Interconnect Self-Assembly Substrate

A method of forming a quilt package nodule includes forming a trench in a microchip substrate, forming a metal layer on the bottom, the first and second sides of the trench, and on a top surface of the microchip substrate proximate the first and second sides. forming a mask layer on the metal layer, removing portions of the mask and metal layers on the bottom of the trench, etching the bottom of the trench to increase the depth of the bottom of the trench, removing remaining portions of the mask layer from the metal layer to define the quilt package nodules that protrude beyond edges of the first and second sides, and removing the remaining portion of the trench bottom thereby separating the first and second sides from each other, whereupon each side includes at least one quilt package nodule protruding from the side. 1. A method of forming a quilt package nodule on an edge of a microchip substrate comprising:(a) forming a trench in a microchip substrate, wherein the trench includes a bottom and first and second sides;(b) following step (a), forming a metal layer on the bottom, the first and second sides of the trench, and on a top surface of the microchip substrate proximate the first and second sides;(c) following step (b), forming a mask layer on the exposed surfaces of the metal layer;(d) following step (c), removing portions of the mask and metal layers on the bottom of the trench;(e) following step (d), etching the bottom of the trench to increase the depth of the bottom of the trench;(f) following step (e), removing remaining portions of the mask layer from the surfaces of the metal layer, whereupon remaining portions of the metal layers on the first and second sides define quilt package nodules that protrude beyond edges of the first and second sides; and(g) following step (f), removing the remaining portion of the trench bottom thereby separating the first and second sides from each other, whereupon each side includes at least one quilt package nodule ...

LAND GRID ARRAY (LGA) PACKAGING OF PASSIVE-ON-GLASS (POG) STRUCTURE

A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad. 1. A device comprising: a glass substrate;', 'a passive component on a first surface of the glass substrate; and', 'at least one contact pad on the first surface of the glass substrate; and, 'a passive-on-glass (POG) structure comprising at least one land grid array (LGA) pad on a third surface of the interface layer, wherein the third surface of the interface layer is opposite the second surface of the interface layer; and', 'at least one via in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad., 'an interface layer comprising a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer, wherein the interface layer comprises2. The device of further comprising a printed circuit board (PCB) claim 1 , wherein the PCB is coupled to the at least one LGA pad on the third surface of the interface layer.3. The device of claim 2 , wherein the PCB comprises a ground plane claim 2 , and wherein the passive component is separated from the ground plane by a ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a semiconductor device (SP) according to an embodiment, a solder resist film (first insulating layer, SR) which is in contact with the base material layer, and a resin body (second insulating layer, ) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (CR) of a wiring substrate and a semiconductor chip (). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved. 1. A semiconductor device comprising:a wiring substrate including a base material layer, a terminal formed on a first surface of the base material layer, and an insulating layer formed on the first surface such that the insulating film covers a first portion of the terminal, and such that the insulating film exposes a second portion of the terminal;a semiconductor chip including a front surface, a bonding pad formed on the front surface, and a projecting electrode formed on the bonding pad, and mounted over the wiring substrate such that the front surface faces the first surface of the wiring substrate via the projecting electrode;a solder material located between the second portion of the terminal and the projecting electrode; anda resin body located between the wiring substrate and the semiconductor chip, and sealing a connection part between the projecting electrode and the terminal,wherein the insulating film has an opening in which the second portion of the terminal is exposed,wherein, ...

CIRCUIT ASSEMBLY WITH THERMAL COATING IN CONTACT WITH EXPOSED METAL EDGES

Apparatus and methods are provided for providing thermal management for semiconductor packages or PCBs. In an exemplary embodiment, there is provided a circuit assembly that may comprise a plurality of metal layers each having exposed edges along peripheral sides of a respective metal layer and a thermal coating layer covering an outer surface of the circuit assembly. The thermal coating layer may be in direct contact with the exposed edges of each of the plurality of metal layers at the peripheral sides of the respective metal layer.

Packages Having Integrated Devices and Methods of Forming Same

An embodiment device package includes a discrete device, a first connector on a bottom surface of the discrete device, and a second connector on a top surface of the discrete device. The first connector bonds the discrete device to a first package component, and the second connector bonds the discrete device to a second package component. 1. A device package comprising:a discrete device;a first connector on a bottom surface of the discrete device, wherein the first connector bonds the discrete device to a first package component; anda second connector on a top surface of the discrete device, wherein the second connector bonds the discrete device to a second package component.2. The device package of claim 1 , wherein the discrete device comprises a contact pad on the top surface claim 1 , the bottom surface claim 1 , and a sidewall of the discrete device claim 1 , wherein the first connector and second connector contact the contact pad.3. The device package of claim 1 , wherein the first and the second connectors are solder balls claim 1 , wherein the first package component is a first device package comprising a first die.4. The device package of claim 3 , wherein the second package component is an interposer claim 3 , a package substrate claim 3 , or a printed circuit board.5. The device package of claim 3 , wherein the second package component is a second device package comprising a second die.6. The device package of claim 1 , further comprising:a third device die; anda molding compound extending along sidewalls of the third device die, wherein the discrete device is disposed in the molding compound.7. The device package of claim 6 , wherein at least one of the first connector or the second connector is a conductive via claim 6 , and wherein a first lateral surface of the conductive via is substantially level a second lateral surface of the molding compound.8. The device package of claim 6 , wherein the first package component is one or more redistribution ...

Semiconductor component and method of fabricating a semiconductor component

An optoelectronic semiconductor component includes a semiconductor chip having a semiconductor layer sequence including an active region that generates radiation; a radiation exit surface running parallel to the active region; a mounting side surface that fixes the semiconductor component and runs obliquely or perpendicularly to the radiation exit surface and at which at least one contact area for external electrical contacting is accessible; a molded body molded onto the semiconductor chip in places and forming the mounting side surface at least in regions; and a contact track arranged on the molded body and electrically conductively connecting the semiconductor chip to the at least one contact area.

POWER SWITCH PACKAGING WITH PRE-FORMED ELECTRICAL CONNECTIONS FOR CONNECTING INDUCTOR TO ONE OR MORE TRANSISTORS

In some examples, device includes an integrated circuit (IC) inside a first insulating layer, an inductor, and a second insulating layer arranged between the first insulating layer and the inductor. The first insulating layer shares an interface with the second insulating layer, and the inductor is attached to the second insulating layer. The device further includes a conductive path configured to conduct electricity between the IC and the inductor, wherein the conductive path is inside the second insulating layer. 1: A device comprising:a conductive path; a first electrical connection to a reference voltage,', 'a second electrical connection to an input node, and', 'a third electrical connection to the conductive path;, 'an integrated circuit (IC) inside a first insulating layer, wherein the IC includesan inductor; the first insulating layer shares an interface with the second insulating layer,', 'the inductor is attached to the second insulating layer,', 'the conductive path is configured to conduct electricity between the IC and the inductor, and', 'the conductive path is inside the second insulating layer., 'a second insulating layer arranged between the first insulating layer and the inductor, wherein2: The device of claim 1 , wherein the IC comprises at least two transistors.3: The device of claim 2 , wherein:each transistor of the at least two transistors includes a control terminal and two load terminals; andone transistor of the at least two transistors comprises a vertical transistor, wherein the vertical transistor includes at least one load terminal that is electrically connected to a top side of the IC and at least one load terminal that is electrically connected to a bottom side of the IC.4: The device of claim 2 , wherein:each transistor of the at least two transistors comprises a lateral transistor; andeach transistor of the at least two transistors includes at least two load terminals that are electrically connected to a top side of the IC or a ...

Power Semiconductor Module and Method for Fabricating a Power Semiconductor Module

A power semiconductor module includes a power semiconductor chip, an external contact electrically coupled to the power semiconductor chip, the external contact being configured to carry an alternating current and the external contact comprising an opening, and a current sensor assembly including a current sensor and being at least partially arranged in the opening, wherein the current sensor is configured to measure the alternating current.

High-frequency, high-output device unit

A high-frequency, high-output device unit includes a lead intended to be soldered to a circuit board and the lead includes concave portions only in a planar portion intended to be joined to the circuit board.

Fan-Out Package Structure and Method

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion. 1. A method comprising:embedding a semiconductor structure in a molding compound layer;depositing a first photo-sensitive material layer over the molding compound layer;exposing the first photo-sensitive material layer to light according to a first pattern;depositing a second photo-sensitive material layer over the first photo-sensitive material layer;exposing the second photo-sensitive material layer to light according to a second pattern, wherein the first pattern is different from the second pattern;developing the first and second photo-sensitive material layers after the second photo-sensitive material layer has been exposed to light according to the second pattern, wherein developing the first and second photo-sensitive material layers defines a first portion of an opening in the first photo-sensitive material layer and a second portion of the opening in the second photo-sensitive material layer; andfilling the first and second portions of the opening with a conductive material to form a first portion of a first interconnect in the first portion of the opening and a second portion of the first interconnect in the second portion of the opening, wherein a width at a top of the second portion of the first interconnect is larger than a width at a top of the first portion of the first interconnect.2. The method of claim 1 , further comprising:forming a seed layer on a ...

Method And System For A Semiconductor Device Package With A Die To Interposer Wafer First Bond

Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.

SENSOR PACKAGE AND MANUFACTURING METHOD THEREOF

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate. 120-. (canceled)21. A sensor device comprising:a substrate having a top substrate side, a bottom substrate side, and a lateral substrate side, the substrate comprising a conductive layer on the top substrate side;a semiconductor die comprising a top die side, a bottom die side coupled to the top substrate side, and a lateral die side, the semiconductor die comprising a sensing area on the top die side and a conductive pad on the top die side;a conductive interconnection structure electrically connecting the conductive pad of the semiconductor die to the conductive layer of the substrate;an encapsulating material that covers the top substrate side and laterally surrounds the semiconductor die, the encapsulating material comprising a top encapsulating material side, a bottom encapsulating material side coupled to the top substrate side, and a lateral encapsulating material side;a dielectric layer (DL) comprising a top DL side, a bottom DL side coupled to the top encapsulating material side, and a lateral DL side; anda plate positioned over the sensing area of the semiconductor die and over the conductive pad of the semiconductor die, the plate comprising a top plate side, a bottom plate side coupled to the top DL side, and a lateral plate side.22. The sensor device of claim 21 , wherein the plate is directly vertically above at a majority of the conductive interconnection structure.23. The sensor device of claim 21 , wherein the encapsulating ...

Wiring substrate, electronic device, and electronic module

A wiring substrate includes a substrate, a first metal and a second metal. The substrate has a first surface, a second surface opposite the first surface, and a side surface connected to the first surface and the second surface. The first metal film is disposed so as to extend from the first surface to the side surface. The second metal film is disposed so as to extend from the second surface to the first metal film disposed on the side surface.

SEMICONDUCTOR DEVICE

A semiconductor device of the present invention includes a resin package, a semiconductor chip sealed in the resin package, and having first and second pads on a front surface, a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and the other surface of an opposite side to the one surface of which is partially exposed from a bottom surface of the resin package as a first pad connecting terminal for electrical connection between the first pad and outside and a back connecting terminal for electrical connection between the back surface of the semiconductor chip and outside separately from each other, and a lead formed separately from the lead integrated island, sealed in the resin package, one surface of which is connected with the second pad by a wire, and the other surface of an opposite side to the one surface of which is exposed from a bottom surface of the resin package as a second pad connecting terminal for electrical connection between the second pad and outside, and the semiconductor chip is, on the one surface of the lead integrated island, disposed at a position one-sided to the first pad connecting terminal side, and the first pad and the one surface of the lead integrated island are connected by a wire. 1. A semiconductor device comprising:a resin package;a semiconductor chip sealed in the resin package, and having first and second pads on a front surface;a lead integrated island sealed in the resin package, to one surface of which a back surface of the semiconductor chip is bonded, and the other surface of an opposite side to the one surface of which is partially exposed from a bottom surface of the resin package as a first pad connecting terminal; anda lead formed separately from the lead integrated island, sealed in the resin package, one surface of which is connected with the second pad electrically, and the other surface of an opposite side to the one surface of which is ...

PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME

A package structure is provided, including a carrier, an electronic component disposed on the carrier and having a sensing area, an encapsulant formed on the carrier and encapsulating the electronic component and the sensing area, and a conductive layer formed on the encapsulant with the sensing area of the electronic component free from being covered by the conductive layer. The encapsulant prevents a user's finger from being in direct contact with the sensing area so as to protect the sensing area from being damaged and hence ensure normal operation of the electronic component. 1. A package structure , comprising:a carrier;an electronic component disposed on and electrically connected to the carrier, wherein the electronic component has a sensing area;an encapsulant formed on the carrier and encapsulating the electronic component and the sensing area of the electronic component; anda conductive layer formed on the encapsulant and electrically connected to the carrier with the sensing area of the electronic component free from being covered by the conductive layer, wherein the conductive layer is free from being electrically connected to the electronic component.2. The package structure of claim 1 , wherein the electronic component is a fingerprint identification chip.3. The package structure of claim 1 , further comprising a color layer formed on a surface of the encapsulant.4. The package structure of claim 1 , further comprising a recess formed on the encapsulant with the conductive layer formed in the recess.5. The package structure of claim 1 , wherein the conductive layer is formed of a filled conductive adhesive claim 1 , an electroplated metal material or a deposited conductive material.6. The package structure of claim 1 , wherein the conductive layer is made of a conductive adhesive or a metal material.7. The package structure of claim 1 , wherein the conductive layer is arranged within a projection area of the carrier toward the electronic component.8. ...

ELECTRONIC COMPONENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

An electronic component mounting substrate includes an insulating base having a rectangular shape in plan view and including a first main surface, a second main surface facing the first main surface, and a recess open on the first main surface, a band-shaped metal layer on a sidewall of the recess, and an electrode extending from a bottom surface of the recess into the insulating base. The electrode has an end disposed in the insulating base, and the end includes an inclined portion inclined toward the second main surface. 1. An electronic component mounting substrate comprising:an insulating base having a rectangular shape in plan view and comprising a first main surface, a second main surface facing the first main surface, and a recess open on the first main surface;a band-shaped metal layer on a sidewall of the recess; andan electrode extending from a bottom surface of the recess into the insulating base,the electrode comprising an end disposed in the insulating base, the end comprising an inclined portion inclined toward the second main surface.2. The electronic component mounting substrate according to claim 1 , wherein the sidewall of the recess and the inclined portion overlap in perspective plan view.3. The electronic component mounting substrate according to claim 1 , wherein the band-shaped metal layer and the inclined portion overlap in perspective plan view.4. The electronic component mounting substrate according to claim 1 , wherein an area of the inclined portion is included in an area of the sidewall of the recess in perspective plan view.5. The electronic component mounting substrate according to claim 1 , wherein the electrode is an outer electrode to be connected to a module substrate claim 1 ,wherein the insulating base further comprises a side surface, andwherein the recess is a solder deposit portion that is open at the side surface and in which the outer electrode is connected to the module substrate via solder.6. The electronic component ...

Light emitting device

A light emitting device includes a light emitting element; a light-transmissive member that has a lower surface positioned inside a peripheral edge of an upper surface of the light emitting element in plan view, a first lateral surface extending from the lower surface and having at least one inclined surface that is inclined with respect to the upper surface of the light emitting element, and a second lateral surface positioned above and outside the first lateral surface; a light-transmissive adhesive member positioned inside the second lateral surface in plan view, wherein the adhesive member adheres the upper surface of the light emitting element and the lower surface of the light-transmissive member to each other and covers the first lateral surface; and a light-reflective member covering the second lateral surface.

SEMICONDUCTOR PACKAGE STRUCTURES AND METHODS OF MANUFACTURE

Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags. 1. A method of forming a semiconductor package , comprising:providing a lead frame comprising a plurality of leads;attaching a tape to the lead frame;coupling one or more semiconductor die with the tape, wherein the one or more semiconductor die comprises a plurality of electrical contacts;electrically interconnecting one or more of the electrical contacts with one or more of the leads using electrical connectors;forming an encapsulated assembly, by at least partially encapsulating the one or more semiconductor die and at least partially encapsulating each of the electrical connectors, using an encapsulant;singulating the encapsulated assembly to form a semiconductor package; anddetaching the tape from one of the encapsulated assembly and the semiconductor package.2. The method of claim 1 , wherein the semiconductor package comprises one of a power converter and a power controller.3. The method of claim 1 , wherein the electrical connectors comprise wirebonds.4016871. The method of claim 1 , further ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method for forming packaged electronic devices includes providing a substrate having pads connected by conductive pad linking portions and semiconductor devices attached to the pads in different orientations. A second substrate is provided having conductive connectors each with a plate portion, a conductive member extending from a side segment of the plate portion, and a connective portion extending from the conductive member distal to the plate portion. The second substrate further has conductive linking portions physically connecting adjoining plate portions together. Each plate portion is attached to one of the semiconductor devices to provide a subassembly. The conductive linking portions are configured to maintain the adjoining plate portions in substantial alignment with the semiconductor devices and to maintain the connective portions is a desired alignment during the plate portion attachment step. A package body is provided to encapsulate the subassembly where bottom surfaces of each connective portion is exposed outside of a major surface of the package body. The method includes separating the encapsulated subassembly to provide the packaged electronic devices such that the separating step severs the conductive linking portions. 1. A method for forming packaged electronic devices , comprising:providing a first substrate comprising pads laterally spaced apart from each other, wherein at least two of the pads are connected by conductive pad linking portions; a plate portion;', 'a conductive member extending from a side segment of the plate portion; and', 'a connective portion extending from the conductive member distal to the plate portion, and', 'wherein:', 'the second substrate further comprises conductive linking portions physically connecting adjoining plate portions together;, 'providing a second substrate comprising conductive connectors, wherein each of the conductive connectors comprisesattaching electronic devices to each of the pads, wherein the ...

CIRCUIT ASSEMBLY AND METHOD FOR MANUFACTURING SAME

A circuit assembly that can be made small and a method for manufacturing the same are provided. A circuit assembly includes a substrate provided with a wiring pattern on one side, and a conductive member fixed to the other side of the substrate, and if portions (terminal portions) that are to be connected to an external electrical element are formed in the conductive member, the conductive member overlaps with the substrate, but not at the portions (terminal portions). A configuration may also be adopted in which the entire conductive member overlaps with the substrate. 2. The circuit assembly according to claim 1 ,wherein the substrate is provided with an external connection means for electrically connecting the conductive member to an external electrical element,the conductive member is provided with an electrical connection portion that is electrically connected to the external connection means, andthe entire conductive member overlaps with the substrate.3. The circuit assembly according to claim 1 ,wherein the conductive member is provided with a mechanical connection portion that is fixed to the substrate.4. A method for manufacturing a circuit assembly claim 1 , comprising:a conductive member connection step of fixing, to a substrate, a conductive member including a first conductor and a second conductor in a state in which the first conductor and the second conductor are separated from each other, the substrate being provided with a wiring pattern on one side of the substrate and being provided with an insulating layer on the other side, the conductive member being fixed to the other side of the substrate such that the conductive member overlaps with the substrate, but not at a portion that is to be connected to an external electrical element;wherein the other side of the substrate is provided with a terminal connection portion that is joined to the wiring pattern such that the terminal connection portion does not overlap with the conductive member,the method ...

Semiconductor packages including through electrodes and methods of manufacturing the same

A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided.

Anti-Plasma Adhesive Tape and Manufacturing Method

An anti-plasma adhesive tape utilized for manufacturing a semiconductor package includes a substrate; and an adhesive layer formed on the substrate, wherein the adhesive layer is selected from a group composed of acrylic adhesive, light-curable resin and photoinitiator. The anti-plasma adhesive tape is attached to a backside of a lead frame of the semiconductor package before a plasma-cleaning process and removed from the lead frame after a molding process. After the anti-plasma adhesive tape is cured by irradiating an energy ray and removed from the lead frame, there is no residual adhesive left on a molding compound of the semiconductor package. 1. An anti-plasma adhesive tape , utilized for manufacturing a semiconductor package , wherein the anti-plasma adhesive tape is attached to a backside of a lead frame of the semiconductor package before a plasma-cleaning process and removed from the lead frame after a molding process , the anti-plasma adhesive tape comprising:a substrate; andan adhesive layer, formed on the substrate, wherein the adhesive layer is selected from a group composed of acrylic adhesive, light-curable resin and photoinitiator;wherein the lead frame comprises a die pad and leads, and gaps are formed between the die pad and the leads;wherein only a first part of the adhesive layer which is directly under the gaps is cured by being irradiated an energy ray before the plasma-cleaning process, and a second part of the adhesive layer which is directly under the lead frame is not cured by the energy ray;wherein after the anti-plasma adhesive tape is removed from the lead frame, there is no residual adhesive left on a molding compound of the semiconductor package and the molding compound is formed via the molding process.2. The anti-plasma adhesive tape of claim 1 , wherein the substrate is a film made of at least one selected from a group composed of polyester (PET) claim 1 , polyimide claim 1 , polyamide and polyethylene terephthalate (PEN).3. The ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first surface), a lower surface (second surface) opposite to the upper surface, and a plurality of side surfaces located between the upper and lower surfaces and having a semiconductor chip mounted thereover. A portion of the metal plate is exposed from a sealing body sealing the semiconductor chip. The exposed portion is covered with a metal film. The side surfaces of the metal plate include a first side surface covered with the sealing body and a side surface (second side surface) provided opposite to the first side surface and exposed from the sealing body. Between the upper and side surfaces of the metal plate, an inclined surface inclined with respect to each of the upper and side surfaces and covered with the metal film is interposed. 119-. (canceled)20. A method of manufacturing a semiconductor device , including the steps of:(a) providing a lead frame having a first metal plate, a plurality of leads arranged in juxtaposition with the first metal plate, and a frame portion coupled to the first metal plate and to the leads;(b) mounting a semiconductor chip over a first surface of the first metal plate of the lead frame and electrically coupling the semiconductor chip to the leads;(c) sealing the entire semiconductor chip, a portion of the first metal plate, and a portion of each of the leads with a resin to form a sealing body;(d) forming a first metal film over a portion of the lead frame which is exposed from the sealing body using an electrolytic plating method; and(e) after the step (d), cutting each of the leads to separate the leads from the frame portion,wherein the first metal plate has a second surface opposite to the first surface and a plurality of side surfaces located between the first and second surfaces,wherein the side surfaces of the first metal plate include:a first side surface provided to face ...

WIRING SUBSTRATE

A wiring substrate includes a first insulating layer, a pad on a surface of the first insulating layer, a reinforcement wiring pattern in or on the surface of the first insulating layer, and a second insulating layer on the surface of the first insulating layer. The reinforcement wiring pattern surrounds the pad without contacting the pad in a plan view. The second insulating layer includes an opening in which the pad is exposed without contacting the second insulating layer. The second insulating layer includes an inner side surface defining the opening. The inner side surface is on the reinforcement wiring pattern. 1. A wiring substrate comprising:a first insulating layer;a pad on a surface of the first insulating layer;a reinforcement wiring pattern surrounding the pad without contacting the pad in a plan view, the reinforcement wiring pattern being in or on the surface of the first insulating layer; anda second insulating layer on the surface of the first insulating layer, the second insulating layer including an opening in which the pad is exposed without contacting the second insulating layer, the second insulating layer including an inner side surface defining the opening, the inner side surface being positioned on the reinforcement wiring pattern.2. The wiring substrate as claimed in claim 1 , wherein an end of the inner side surface toward the first insulating layer is in contact with the reinforcement wiring pattern.3. The wiring substrate as claimed in claim 1 , wherein the reinforcement wiring pattern is in a groove famed in the surface of the first insulating layer.4. The wiring substrate as claimed in claim 1 , wherein a height of the reinforcement wiring pattern is smaller than a height of the pad with reference to the surface of the first insulating layer.5. The wiring substrate as claimed in claim 1 , wherein the reinforcement wiring pattern protrudes from the surface of the first insulating layer.6. The wiring substrate as claimed in claim 1 , ...

PACKAGING SUBSTRATE, PACKAGING STRUCTURE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD

A packaging substrate, a packaging structure, an electronic device and a manufacturing method, and pertain to the field of chip packaging technologies. The packaging substrate includes a body including metal cabling. The body includes a first surface, a second surface and a side surface. The side surface is connected to the first surface and second surface. The first surface includes many first connection structures. The second surface includes second connection structures. The side surface includes third connection structures. A part of the first connection structures are connected to the second connection structures by using the metal cabling. The other part of the first connection structures are connected to the third connection structures by using the metal cabling. When the same total quantity of pins need to be disposed, a part of the pins are transferred to the side surface of the body, with less pins at the second surface. 1. A packaging substrate , comprising a metal cabling;', 'a first surface comprising a plurality of first connection structures configured to connect to a die;', 'a second surface comprising second connection structures configured to serve as pins; and', 'a side surface comprising third connection structures configured to serve as pins, wherein the side surface is connected to the first surface and the second surface, and wherein', 'a part of the plurality of first connection structures are connected to the second connection structures by using the metal cabling, and an other part of the plurality of first connection structures are connected to the third connection structures by using the metal cabling., 'a body comprising'}2. The packaging substrate according to claim 1 , wherein the side surface comprises at least two rows of third connection structures claim 1 , and wherein the at least two rows of third connection structures are distributed with a gap in a thickness direction of the body.3. The packaging substrate according to claim 1 ...

ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME

An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads. 1. An interconnect assembly for an embedded chip package , the interconnect assembly comprising:an insulating substrate;a first metal layer comprising a plurality of upper contact pads, wherein a first surface of the plurality of upper contact pads is affixed to a top surface of the insulating substrate;a second metal layer comprising a plurality of lower contact pads, wherein a first surface of the plurality of lower contact pads is affixed to a bottom surface of the insulating substrate; anda plurality of electrical connections formed through the insulating substrate and in electrical contact with the plurality of upper contact pads and the plurality of lower contact pads, wherein a portion of a bottom surface of the plurality of electrical connections is directly coupled to the top surface of the insulating substrate.2. The interconnect assembly of wherein the insulating substrate comprises a polyimide film.3. The interconnect assembly of wherein the first and second metal layers comprise copper.4. The interconnect assembly of further comprising at least one of a titanium layer and a chrome layer ...

SEMICONDUCTOR DEVICE PACKAGES AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device package includes a substrate, a semiconductor device and an encapsulant. The substrate includes a passivation layer, a first conductive layer and a barrier layer. The passivation layer has a substantially vertical sidewall. The first conductive layer is disposed on the passivation layer. The barrier layer is disposed on the passivation layer and the first conductive layer. The barrier layer includes a substantially slant sidewall. 1. A semiconductor device package , comprising: a passivation layer having a substantially vertical sidewall;', 'a first conductive layer disposed on the passivation layer;', 'a barrier layer disposed on the passivation layer and the first conductive layer, wherein the barrier layer includes a substantially slant sidewall;, 'a substrate, comprisinga semiconductor device disposed on the substrate;an encapsulant disposed on the substrate and encapsulating the semiconductor device.2. The semiconductor device package of claim 1 , further comprising a second conductive layer disposed between the first conductive layer and the barrier layer.3. The semiconductor device package of claim 2 , wherein the second conductive layer is in direct contact with the first conductive layer.4. The semiconductor device package of claim 2 , wherein the barrier layer comprising a horizontal sidewall.5. The semiconductor device package of claim 2 , wherein the second conductive layer does not continuously surround the first conductive layer.6. The semiconductor device package of claim 1 , wherein the first conductive layer includes a substantially slant sidewall.7. The semiconductor device package of claim 6 , wherein a thickness of the substantially slant sidewall of the barrier layer is greater than a thickness of a substantially vertical sidewall of the barrier layer.8. The semiconductor device package of claim 2 , wherein the first conductive layer and second conductive layer comprise a same material.9. The semiconductor device package ...

SEMICONDUCTOR DEVICE AND METHOD OF MEASURING THE SAME

A semiconductor device includes first and second contact parts that are disposed close to each other with an interval therebetween and form a screw hole (connection area) to which an external connection terminal is connected. The first contact part extends from a side of a case via a first linkage part that extends from the side, and the second contact part extends from the side via a second linkage part that extends from the side. The first and second linkage parts are disposed away from each other by at least a certain interval. In this way, the semiconductor device is allowed to have first and second semiconductor chips connected in parallel with each other and function as a semiconductor device. In addition, electrical characteristics of the first and second semiconductor chips of the semiconductor device are individually measured. 1. A semiconductor device comprising:a first semiconductor chip and a second semiconductor chip that are disposed on a metal plate;a first electrode terminal that is electrically connected to a main electrode of the first semiconductor chip; anda second electrode terminal that is electrically connected to a main electrode of the second semiconductor chip,wherein the first electrode terminal includes a first contact part, and the second electrode terminal includes a second contact part, andwherein the first contact part and the second contact part are disposed close to each other with an interval therebetween and form a connection area to which an external connection terminal is connected.2. The semiconductor device according to claim 1 , further comprising:a multi-layer substrate including the metal plate and an insulating plate having a front side on which the metal plate is formed,wherein the multi-layer substrate, the first semiconductor chip, and the second semiconductor chip are held inside a case,wherein the first contact part and the second contact part extend from a side of the case,wherein the first electrode terminal is ...

HIGH RELIABILITY WAFER LEVEL SEMICONDUCTOR PACKAGING

Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid. 1. A semiconductor package comprising:a semiconductor die comprising a first side and a second side;a first trench comprised in the first side of the semiconductor die, the trench positioned outside an active area of the die;a glass lid comprising a second trench, the glass lid fixedly coupled to a first side of the semiconductor die by an adhesive;wherein the adhesive is comprised in the first trench in the first side of the semiconductor die and comprised in the second trench positioned around a perimeter of the glass lid.2. The semiconductor package of claim 1 , wherein the adhesive is selected from the group consisting of thermal curable resin claim 1 , epoxy claim 1 , ultraviolet light curable resin and any combination thereof.3. The semiconductor package of claim 2 , wherein the adhesive is cured.4. The semiconductor package of claim 1 , wherein the adhesive is evenly distributed within the first trench and the second trench.5. The semiconductor package of claim 1 , wherein the adhesive extends out from the first trench and the second trench to further bond the glass lid and the semiconductor die.6. The semiconductor package of claim 1 , further comprising a redistribution layer coupled to the second side of the semiconductor die.7. The semiconductor package of claim 5 , further comprising a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer opposing the side of the redistribution layer ...

PRINTED CIRCUIT BOARD AND METHOD OF FABRICATING AN ELEMENT

The present invention provides a printed circuit board fabricated by a Non-Plating Process that includes at least one plating bar disposed around at least one package unit of the printed circuit board. The package unit includes at least one ground line, at least one power line and a plurality of signal lines. The ground line has a first contact pad exposed on a surface of the printed circuit board, and at least one of the ground lines is connected to the plating bar. The power line has a second contact pad exposed on the surface, and at least one of the power lines is connected to the neighboring plating bar. The signal line has a third contact pad exposed on the surface. 1. A printed circuit board , being divided into at least one package unit , comprising:at least one plating bar, being disposed around the package unit, wherein the printed circuit board is fabricated by a Non-Plating Process, and each of the package units comprises:at least one ground line, wherein the ground line has a first contact pad exposed on a surface of the printed circuit board, and at least one of the ground lines is connected to the plating bar;at least one power line, wherein the power line has a second contact pad exposed on the surface of the printed circuit board, and at least one of the power lines is connected to the plating bar; anda plurality of signal lines, wherein each of the signal lines has a third contact pad exposed on the surface of the printed circuit board and all of the signal lines of each of the package units are decoupled from the plating bars.2. The printed circuit board as claimed in claim 1 , wherein the power line of each of the package units is connected to the neighboring plating bar.3. The printed circuit board as claimed in claim 1 , wherein the plating bars are connected to ground.4. A printed circuit board claim 1 , having a plurality of edges claim 1 , comprising:at least one ground line, wherein the ground line has a first contact pad exposed on a first ...

ON-PACKAGE CONNECTOR

Conventional ways of coupling die packages to external devices include providing contacts on a separate area on a printed circuit board (PCB). These PCB contacts are configured to mate with connector contacts of a connector to enable coupling with external devices. Unfortunately, the PCB contacts take up significant amount of area of the PCB. Also, the connection can suffer from parasitic losses and signal integrity can be compromised. An on-package connection is proposed to address the short comings of the conventional ways. The on-package connection enables a die package to connect directly with the connector. This removes the need to provide a separate area for PCB contacts. Also, parasitic losses are minimized and signal integrity is enhanced. 1. A die package , comprising:a die coupled to a substrate; anda plurality of package contacts on an outer perimeter of the die package, the plurality of package contacts configured to mate with a connector,the die configured to electrically couple to the connector through the plurality of package contacts and through a plurality of connector contacts if the plurality of package contacts are mated with the plurality of connector contacts.2. The die package of claim 1 , the plurality of package contacts comprising:a plurality of first contacts on an outer perimeter of the substrate and configured to electrically couple to the die through the substrate, the plurality of first contacts configured to mate with the plurality of connector contacts.3. The die package of claim 1 , the plurality of package contacts comprising:a plurality of first contacts on an outer perimeter of the substrate and configured to electrically couple to the die through the substrate; anda plurality of second contacts around the die and configured to electrically couple to the plurality of first contacts, the plurality of second contacts configured to mate with the plurality of connector contacts.4. The die package of claim 3 , the plurality of first ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor device includes a molded body and an interconnection layer. The molded body includes a semiconductor chip, at least one terminal body disposed around the semiconductor chip and a resin member provided between the semiconductor chip and the terminal body. The molded body has a first surface, a second surface opposite to the first surface and a side surface connected to the first and second surfaces. The interconnection layer is provided on the first surface of the molded body. The interconnection layer includes an interconnect electrically connecting the semiconductor chip and the terminal body. The terminal body has first and second contact surfaces. The first contact surface is exposed at the first or second surface of the molded body. The second contact surface is connected to the first contact surface and exposed at the side surface of the molded body. 1. A semiconductor device , comprising:a molded body including a semiconductor chip, at least one terminal body and a resin member, the at least one terminal body being disposed around the semiconductor chip, the resin member provided between the semiconductor chip and the terminal body, the molded body having a first surface, a second surface opposite to the first surface and a side surface connected to the first surface and the second surface, the semiconductor chip and the terminal body being exposed at the first surface of the molded body; andan interconnection layer provided on the first surface of the molded body, the interconnection layer including an interconnect electrically connecting the semiconductor chip and the terminal body,the terminal body having a first contact surface and a second contact surface, the first contact surface being exposed at the first surface of the molded body or the second surface of the molded body, the second contact surface being connected to the first contact surface and exposed at the side surface of the molded body.2. The device according to claim 1 , ...

BACKSIDE GROUND PLANE FOR INTEGRATED CIRCUIT

An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound. 1. An integrated circuit (IC) device , comprising:a die including an integrated passive device (IPD) layer;a substrate supporting the die;a molding compound surrounding the die;a backside conductive layer on a surface of the die that is distal from the IPD layer; anda plurality of vias coupling the backside conductive layer to a ground plane through the molding compound.2. The IC device of claim 1 , in which the die comprise a glass die.3. The IC device of claim 1 , in which the IPD layer comprises inductors and capacitors.4. The IC device of claim 1 , in which the ground plane comprises a shielding layer surrounding a portion of the molding compound and the substrate.5. The IC device of claim 4 , in which the shielding layer is arranged to cover sidewalls of the substrate.6. The IC device of claim 1 , in which the ground plane is distal from the IPD layer.7. The IC device of claim 1 , further comprising solder balls on a front side of the die for electrically coupling the substrate to the die.8. The IC device of claim 1 , integrated into a radio frequency (RF) front end module claim 1 , the RF front end module incorporated into at least one of a music player claim 1 , a video player claim 1 , an entertainment unit claim 1 , a navigation device claim 1 , a communications device claim 1 , a personal digital assistant (PDA) claim 1 , a fixed location data unit claim 1 , a mobile phone claim 1 , and a portable computer.9. A method of fabricating an integrated circuit (IC) device claim 1 , ...

Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks

A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.

Laminated interposers and packages with embedded trace interconnects

Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical conductive vias in the package by depositing conductive traces on multiple wafers or panes, then laminating these substrates into a stack, thereby embedding the conductive traces. The laminated stack is sliced to dimensions of an interposer or electronic package. A side of the sliced stack is then used as the top of the interposer or package, rendering some of the horizontally laid traces into vertical conductive vias. The interposer or package can be finished or developed by adding redistribution layers on the top and bottom surfaces, and active and passive components. Electronic components can also be embedded in the laminated stack. Some of the stack layers can be active dies, such as memory controllers, memory storage arrays, and processors, to form a memory subsystem or self-contained computing device.

ORGANIC INTERPOSER INCLUDING INTRA-DIE STRUCTURAL REINFORCEMENT STRUCTURES AND METHODS OF FORMING THE SAME

An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Asic Package With Photonics And Vertical Power Delivery

The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

TAPELESS LEADFRAME PACKAGE WITH UNDERSIDE RESIN AND SOLDER CONTACT

The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array. 1. A device , comprising: a semiconductor die;', 'a leadframe having a first side and a second side opposite the first side, the leadframe having a plurality of recesses in the first side, the semiconductor die coupled to the second side of the leadframe;', 'a plurality of electrical contacts, the plurality of electrical contacts in a first group of the plurality of recesses, the plurality of electrical contacts having a first portion extending into a respective one of the plurality of recesses and a second portion extending away from the respective one of the plurality of recesses; and', 'an encapsulant on the first side of the leadframe and on the second side of the leadframe, the encapsulant around respective sides of the second portion of the electrical contacts., 'a leadframe package including2. The device of claim 1 , wherein the plurality of electrical contacts each have a surface that is coplanar with a surface of a first side of the encapsulant.3. The device of claim 2 , wherein the encapsulant has a second side opposite the first side claim 2 , the first and second sides of the encapsulant being in a parallel plane to the first side of the leadframe.4. The device of claim 3 , wherein a thickness of the encapsulant between the second side of the encapsulant and the second side of the leadframe is no more than five times ...

CHIP PACKAGES, CHIP ARRANGEMENTS, A CIRCUIT BOARD, AND METHODS FOR MANUFACTURING CHIP PACKAGES

A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material. 1. A chip arrangement comprising: a cavity formed in the circuit board;', 'and one or more circuit board contact regions arranged proximate to the cavity;, 'a circuit board comprisinga chip package arranged within the cavity,wherein at least one circuit board contact region is electrically connected to the one or more electrically conductive contact regions formed over a top side of the chip package and in electrical connection with a chip top side; andwherein at least one further circuit board contact region is electrically connected to an electrically conductive contact region formed over a bottom side of the chip package and in electrical connection with a chip bottom side.2. The chip arrangement according to claim 1 , wherein the chip package further comprises:a chip disposed over and electrically connected to a chip carrier top side;an electrically insulating material disposed over and at least partially surrounding the chip, wherein the one or more electrically conductive contact regions over the chip carrier top side comprises two or more electrically conductive contact regions formed through the electrically insulating material; anda further electrically insulating material disposed under a chip carrier bottom side wherein an electrically conductive contact region over the chip carrier bottom side is formed through the electrically insulating material. ...

Single or multi chip module package and related methods

Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame.

Circuits and methods related to radio-frequency devices with overmold structure

A method for manufacturing packaged radio-frequency devices is disclosed, including providing a packaging substrate configured to receive a plurality of components, the packaging substrate including a first side and a second side. The method further includes forming a shielded package on the first side of the packaging substrate, the shielded package including a first circuit and a first overmold structure, the shielded package configured to provide radio-frequency shielding for at least a portion of the first circuit. The method includes mounting a component on the second side of the packaging substrate, forming a second overmold structure over the component and forming a set of cavities in the second overmold structure, the set of cavities positioned relative to the component. The method includes forming a set of through-mold connections in the set of cavities in the second overmold structure.

MICROELECTRODE ARRAY AND METHODS OF FABRICATING SAME

An implantable device and methods for forming the same are provided. The device may comprise: (a) a substrate comprising a plurality of feedthroughs, wherein the plurality of feedthroughs comprises a first conductive material; and (b) an array of microwires extending from the substrate. The array of microwires may be connected or bonded to the plurality of feedthroughs using a biocompatible solder or braze material or intermediate filler material. The array of microwires may comprise a second conductive material that is different from the first conductive material. 1. An implantable device comprising:a substrate comprising a plurality of feedthroughs, wherein the plurality of feedthroughs comprises a first conductive material; andan array of microwires extending from the substrate, wherein the array of microwires is connected or bonded to the plurality of feedthroughs using a biocompatible solder or braze material or intermediate filler material, and wherein the array of microwires comprises a second conductive material that is different from the first conductive material.2. The device of claim 1 , wherein the substrate comprises ceramic.3. The device of claim 1 , wherein a thickness of the substrate is equal to or less than about 1 millimeter (mm).4. The device of claim 1 , wherein a diameter of each of the plurality of feedthroughs is from about 25 microns to about 250 microns.5. The device of claim 1 , wherein the plurality of feedthroughs is completely filled with the first conductive material.6. The device of claim 1 , wherein sidewalls of the plurality of feedthroughs are coated with the first conductive material.7. The device of claim 1 , wherein each microwire in the array of microwires has a conical tip.8. The device of claim 7 , wherein a radius of the conical tip is less than about 5 micrometers.9. The device of claim 1 , wherein each microwire in the array of microwires has a diameter of about 10 micrometers to about 50 micrometers.10. The device of ...

SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME

A semiconductor structure includes system-on-integrated chips, a first redistribution circuit structure and first conductive terminals. The system-on-integrated chips each include a die stack having two or more than two tiers, and each tier includes at least one semiconductor die. The first redistribution circuit structure is located on and electrically connected to the system-on-integrated chips. The first conductive terminals are connected on the first redistribution circuit structure, where the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals. 1. A semiconductor structure , comprising:system-on-integrated chips, each comprising a die stack having two or more than two tiers, wherein each tier comprises at least one semiconductor die;a first redistribution circuit structure, located on and electrically connected to the system-on-integrated chips; andfirst conductive terminals, connected on the first redistribution circuit structure, wherein the first redistribution circuit structure is located between the system-on-integrated chips and the first conductive terminals.2. The semiconductor structure of claim 1 , further comprising:an insulating encapsulation, laterally encapsulating the system-on-integrated chips, wherein a material of the insulating encapsulation comprises a dielectric material or a molding compound.3. The semiconductor structure of claim 1 , wherein for each of the system-on-integrated chips claim 1 , along a stacking direction of the two or more than two tiers claim 1 , a projection area of each semiconductor die included in one tier is greater than or substantially equal to a projection area of each semiconductor die included in a respectively tier overlying thereto.4. The semiconductor structure of claim 1 , wherein at least one of the system-on-integrated chips further comprising a second redistribution circuit structure located between and electrically connecting two ...

PRINTED BOARD, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING SAME

A method for manufacturing a printed board includes steps of; providing a starting board comprising a base member having a plate-like shape, having an upper surface and a lower surface opposite the upper surface, and having an insulation property, a first metal layer disposed on the upper surface, and a second metal layer disposed on the lower surface; and laser machining a through-hole penetrating the starting board in a thickness direction of the starting board by irradiating a laser beam irradiation area of the starting board with a laser beam from a side of the starting board on which side the first metal layer is disposed. The method further includes a step of etching the second metal layer so as to remove a portion of the second metal layer located in the laser beam irradiation area, prior to the step of laser machining. 1. A method for manufacturing a printed board , the method comprising steps of:providing a starting board comprising a base member having a plate-like shape, having an upper surface and a lower surface opposite the upper surface, and having an insulation property, a first metal layer disposed on the upper surface, and a second metal layer disposed on the lower surface; andlaser machining a through-hole penetrating the starting board in a thickness direction of the starting board by irradiating a laser beam irradiation area of the starting board with a laser beam from a side of the starting board on which side the first metal layer is disposed,wherein the method further comprises a step of etching the second metal layer so as to remove a second metal layer removal portion of the second metal layer located in the laser beam irradiation area, prior to the step of laser machining.2. The method according to claim 1 , wherein claim 1 , in the step of etching claim 1 , the second metal layer removal portion of the second metal layer is removed such that the second metal layer from which the second metal layer removal portion has been removed is ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the semiconductor body. The semiconductor package structure also includes an insulating layer surrounding the conductive structure. The semiconductor package structure further includes a redistribution layer structure coupled to the conductive structure. In addition, the semiconductor package structure includes a molding compound surrounding the semiconductor body. A portion of the molding compound extends between the redistribution layer structure and the semiconductor body. 1. A semiconductor package structure , comprising:a semiconductor body;a conductive structure disposed below the semiconductor body;an insulating layer surrounding the conductive structure;a redistribution layer structure coupled to the conductive structure; anda molding compound surrounding the semiconductor body, wherein a portion of the molding compound extends between the redistribution layer structure and the semiconductor body.2. The semiconductor package structure as claimed in claim 1 , wherein the semiconductor body has a surface facing the redistribution layer structure claim 1 , and the portion of the molding compound is in direct contact with the surface of the semiconductor body.3. The semiconductor package structure as claimed in claim 1 , further comprising a dielectric layer between the semiconductor body and the insulating layer claim 1 , wherein the dielectric layer surrounds a lower portion of the conductive structure and the insulating layer surrounds an upper portion of the conductive structure.4. The semiconductor package structure as claimed in claim 3 , wherein the portion of the molding compound is sandwiched between the redistribution layer structure and the dielectric layer.5. The semiconductor package structure as claimed in claim 1 , wherein the semiconductor body is wider than the insulating layer.6. The ...

WIRING BOARD, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

A wiring board includes an insulating substrate including a first surface and a mounting portion for an electronic component on the first surface, the insulating substrate having a rectangular shape in a plan view of the first surface; a via conductor located inside the insulating substrate and at a corner portion of the insulating substrate in a plane perspective, and extending in a thickness direction of the insulating substrate; a wiring conductor located on the first surface and connecting the mounting portion and the via conductor to each other; and a heat dissipation portion located inside the insulating substrate at a position overlapping the mounting portion in a plane perspective view, wherein the first surface includes, between the heat dissipation portion and the via conductor in a plane perspective view, a first region surrounded by the wiring conductor in a plan view. 1. A wiring board comprising:an insulating substrate comprising a first surface and a mounting portion for an electronic component on the first surface, the insulating substrate having a rectangular shape in a plan view of the first surface;a via conductor located inside the insulating substrate and at a corner portion of the insulating substrate in a plane perspective view ,the via conductor extending in a thickness direction of the insulating substrate;a wiring conductor located on the first surface and connecting the mounting portion and the via conductor to each other; anda heat dissipation portion located inside the insulating substrate at a position overlapping the mounting portion in a plane perspective view, whereinthe first surface comprises a first region surrounded by the wiring conductor in a plan view, the first region located between the heat dissipation portion and the via conductor in a plane perspective view.2. The wiring board according to claim 1 , whereinin a plane perspective view, the first region is located closer to the via conductor than to the heat dissipation ...

TAPELESS LEADFRAME PACKAGE WITH UNDERSIDE RESIN AND SOLDER CONTACT

The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array. 1. A method , comprising:coupling a semiconductor die onto a first surface of a leadframe, the leadframe having a plurality of recesses on a second surface thereof that is opposite to the first surface;forming a discrete electrical contact in a first recess of the plurality of recesses, the discrete electrical contact having a first portion extending into the first recess and a second portion extending away from the first recess;covering the second surface of the leadframe and the discrete electrical contact with an encapsulant material; andexposing the discrete electrical contact from the encapsulant material by removing a portion of the encapsulant material.2. The method of claim 1 , wherein the exposing the discrete electrical contact from the encapsulant material removes at least partially the second portion of the discrete electrical contact.3. The method of claim 2 , wherein the removing at least partially the second portion makes an exposed surface of the discrete electrical contact substantially flat.4. The method of claim 2 , wherein the removing at least partially the second portion makes an exposed surface of the discrete electrical contact substantially coplanar with a surface of the encapsulant material that covers the second surface of the leadframe.5. The method of claim 1 , wherein the discrete electrical contact ...

Apparatus and method for chip placement and molding

An approach is provided for placing and securing a chip package portion in an aligned position during a curing process. The approach involves providing an apparatus having a first reservoir configured to receive a first chip package, a second reservoir, and a third reservoir. The approach also involves placing the first chip package portion into the first reservoir, the second chip package portion into the second reservoir, and the third chip package portion into the third reservoir. The approach further involves causing the first chip package portion to be secured in a first curing position, the second chip package portion to be secured in a second curing position and the third chip package portion to be secured in a third curing position.

PACKAGE EDGE MOUNTED FRAME STRUCTURES

Embodiments may relate to a semiconductor package. A conductive frame may be coupled with the semiconductor package. The conductive frame may include a first portion, a second portion, and a third portion positioned between the first portion and the second portion. The first portion may be coupled with the first side of the semiconductor package. The second portion may be coupled with the second side of the semiconductor package. The third portion may be coupled with the sidewall of the semiconductor package. Other embodiments may be described or claimed. 1. An electronic device comprising:a semiconductor package with a first side and a second side opposite the first side, and a sidewall positioned between the first side and the second side at a perimeter of the semiconductor package; anda conductive frame that includes a first portion, a second portion, and a third portion positioned between the first portion and the second portion, wherein the first portion is coupled with the first side of the semiconductor package, the second portion is coupled with the second side of the semiconductor package, and the third portion is coupled with the sidewall of the semiconductor package.2. The electronic device of claim 1 , wherein the first portion has a width of 500 micrometers claim 1 , as measured in a direction parallel to the first side of the package.3. The electronic device of claim 1 , wherein the third portion has a width of 200 micrometers claim 1 , as measured in a direction parallel to the first side of the package.4. The electronic device of claim 1 , wherein at least part of the first side and the second side are exposed by an opening in the conductive frame.5. The electronic device of claim 1 , wherein the first portion or the second portion are coupled with a power rail of the semiconductor package.6. The electronic device of claim 1 , wherein the first side of the semiconductor package has a first plurality of interconnects at a first pitch claim 1 , and the ...

SINGLE OR MULTI CHIP MODULE PACKAGE AND RELATED METHODS

Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die. A mold compound or an encapsulating compound may be included around the die and a majority of the at least one clip where a portion of the at least one lead and a portion of the plurality of electrical contacts on the first face of the die are not overmolded or encapsulated. The semiconductor package includes no lead frame. 1. A semiconductor device package consisting of:at least one die comprising at least one electrical contact;at least one clip comprising at least one electrical contact mechanically and electrically coupled with the at least one die;one of an overmolding or an encapsulating compound comprised around the at least one die and a majority of the at least one clip, wherein the at least one electrical contact of the at least one die and the electrical contact of the at least one clip are not one of overmolded and encapsulated;wherein the at least one electrical contact of the at least one die and the electrical contact of the at least one clip are configured to be positioned to electrically couple with one or more conductive paths comprised in a motherboard, the one or more conductive paths forming a distribution layer;wherein the distribution layer is configured to distribute all electrical signals between the semiconductor device package and the motherboard; andwherein the semiconductor device package comprises no lead frame.2. A semiconductor device package comprising:a plurality of electrical contacts comprised on a first face of a first die; andone of a mold ...

Manufacturing method of semiconductor package

A manufacturing method of a semiconductor package includes a groove forming step of cutting a semiconductor package substrate from an upper surface side along division lines in a cut-in-depth range of at least such a depth as to cause a ground line included in a wiring substrate to be exposed in a processing groove to such a depth that the semiconductor package substrate is not fully cut with a first cutting blade, thereby forming the processing groove having a first width at least on an upper surface of a sealing material, a shielding layer forming step of forming a shielding layer on a side surface of the processing groove, a bottom surface of the processing groove, and the upper surface of the sealing material with a conductive material from an upper side of the sealing material, and a dividing step of, cutting the semiconductor package substrate into individual semiconductor packages.

Semiconductor package and semiconductor device using the same

A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

SEMICONDUCTOR DEVICE WITH THROUGH-MOLD VIA

In accordance with the present invention, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically connected to the through-mold vias, and may be covered by the package body and/or disposed in spaced relation thereto. In yet other embodiments of the semiconductor device, the interposer may not be electrically connected to the through mold vias, but may have one or more semiconductor dies of the semiconductor device electrically connected thereto. 1. A packaged semiconductor device structure comprising: a first insulative structure including at least one insulating layer, the first insulative structure having a first major surface and an opposing second major surface;', 'a first conductive pattern disposed proximate to the first major surface of the first insulative structure and exposed to the outside of the first insulative structure, wherein the first conductive pattern comprises a first portion disposed proximate to a perimeter part of the first redistribution structure and a second portion disposed proximate to a central part of the first redistribution structure; and ...

MOLDED INTERCONNECTING SUBSTRATE AND THE METHOD FOR MANUFACTURING THE SAME

A molded interconnecting substrate has an embedded redistribution layer (RDL), an embossed RDL, a plurality of conductive pillars encapsulated in a molding core, and a chip also encapsulated in the molded core. The conductive pillars are disposed on the external pads of the embedded RDL. The chip is die-bonded onto the embedded RDL. The molding core has an external surface and an opposing component-installing surface. The embedded RDL is embedded in the molding core from the external surface. The bottom surface of the embedded RDL is coplanar to the external surface and the pillar-top surfaces of the conductive pillars are coplanar to the component-installing surface. The embossed RDL is disposed on and extruded from the component-installing surface including a plurality of pillar-top pads aligned and bonded to the pillar-top surfaces. Accordingly, it is possible to eliminate a flip-chip molding thickness without manufacture of substrate plating lines where fine-pitch substrate circuitry can be achieved without substrate drilling process. 1. A molded interconnecting substrate comprising:an embedded redistribution layer (RDL) formed on a molding surface, the embedded RDL having a plurality of embedded circuitries, a plurality of external pads, and a plurality of first internal pads, each of the plurality of embedded circuitries being directly coupled to a corresponding external pad and a corresponding first internal pad;a plurality of first conductive pillars correspondingly disposed on the plurality of external pads;a first chip die-bonded on the embedded RDL and electrically connected to the first internal pads;a first molding core formed on the molding surface and configured to encapsulate the first chip and the first conductive pillars, wherein the embedded RDL is embedded in an external surface of the first molding core, wherein each of the plurality of embedded circuitries, each of the plurality of external pads, and each of the plurality of first internal pads ...

METHOD FOR FORMING CHIP PACKAGE STRUCTURE

Methods for forming chip package structures are provided. The method includes disposing a first chip structure, a second chip structure over a carrier substrate and forming a molding compound layer surrounding the first chip structure and the second chip structure. The method includes forming a dielectric structure over the molding compound layer and a first grounding line in the dielectric structure and cutting the first grounding line to form a first end enlarged portion of the first grounding line. In addition, the first end enlarged portion has a gradually increased thickness. 1. A method for forming a chip package structure , comprising:disposing a first chip structure, a second chip structure over a carrier substrate;forming a molding compound layer surrounding the first chip structure and the second chip structure;forming a dielectric structure over the molding compound layer and a first grounding line in the dielectric structure; andcutting the first grounding line to form a first end enlarged portion of the first grounding line, wherein the first end enlarged portion has a gradually increased thickness.2. The method for forming a chip package structure as claimed in claim 1 , wherein the first end enlarged portion adjoins a first main portion of the first grounding line claim 1 , and the first main portion has a substantially uniform thickness after the step of cutting the first grounding line.3. The method for forming a chip package structure as claimed in claim 1 , further comprising:cutting a second grounding line in the dielectric structure to form a third end enlarged portion, wherein the third end enlarged portion is in direct contact with the first end enlarged portion.4. The method for forming a chip package structure as claimed in claim 1 , further comprising:cutting the dielectric structure and the molding compound layer during the step of cutting the first grounding line such that a first chip package structure and a second chip package structure ...

Method for Packaging Quad Flat Non-Leaded Package Body, and Package Body

A method for packaging a quad flat non-leaded (QFN) package body. The method includes: etching an upper surface of a metal plate to process a groove to form a bond wire bench, a component bench, and a bump; processing the bump to a preset height, and assembling a component on the component bench; packaging the processed metal plate to form a package body, and exposing the surface of the processed bump on an upper surface of the package body to form a top lead; and etching a lower surface of the package body to process a bottom lead. In the present invention, large passive components can be stacked on the QFN package body with a top lead; the structure is simplified while the reliability of the welding joints is improved; a plurality of components can be stacked through the top lead to overcome the limitations of component stacking. 1. A method for packaging a quad flat non-leaded package body , comprising:etching an upper surface of a metal plate to process a desired groove and form a bond wire bench, a component bench, and a bump;processing the bump to reach a preset height,assembling a component on the component bench;connecting the component and the bond wire bench;packaging the processed metal plate in plastic to form a package body;exposing a surface of the processed bump on an upper surface of the package body to form a top lead; andetching a lower surface of the package body to process a desired bottom lead and obtain a quad flat non-leaded package body.2. The method according to claim 1 , wherein processing the bump to reach the preset height comprises applying an electroplating process to electroplate the surface of the bump to form a bump of the preset height.3. The method according to claim 1 , wherein processing the bump to reach the preset height comprises:applying an electroplating process to form a welding surface on the surface of the bump;printing solder paste on the welding surface; andthen welding a metal rod with the solder paste to make the bump ...

Module ic package structure with electrical shielding function and method for manufacturing the same

A module IC package structure includes a substrate unit, an electronic unit, a package unit and a shielding unit. The substrate unit including a circuit substrate, a grounding layer disposed inside the circuit substrate, and an outer conductive structure disposed on the outer surrounding peripheral surface of the circuit substrate. The outer conductive structure includes a plurality of outer conductive layers. The grounding layer is exposed from the circuit substrate for directly contacting the outer conductive layers. The electronic unit includes a plurality of electronic components disposed on the circuit substrate. The package unit includes a package gel body disposed on the circuit substrate to enclose the electronic components. The shielding unit includes a metal shielding layer enclosing the package gel body and directly contacting the outer conductive structure. Whereby, the grounding layer is electrically connected to the metal shielding layer through the outer conductive structure directly.

PLATED DITCH PRE-MOLD LEAD FRAME, SEMICONDUCTOR PACKAGE, AND METHOD OF MAKING SAME

An integrated circuit chip package and method for making the same, wherein the integrated circuit chip package includes conductive leads. The method includes trenching a plurality of conductive lead structures along a parting line, plating the trenches with a plating layer, and singulating the lead frame assembly along the parting line to produce an integrated circuit chip package with conductive leads having unplated side portions and plated recessed portions. 1. A method for making an integrated circuit chip package , comprising: opposing first and second sides, and', 'an array of lead frames at least partially surrounded by a first molded structure, each lead frame including a die attach pad and a plurality of conductive lead structures spaced apart from the die attach pad, the first molded structure interposed at least between adjacent conductive lead structures along a parting line;', 'forming a trench in at least one of the plurality of conductive lead structures along the parting line, the trench opening to the second side of the premolded lead frame assembly;', 'depositing a plating layer over at least the trench;', 'coupling an integrated circuit die to the plated die attach pad on the first side of the premolded lead frame assembly;', 'wirebonding the integrated circuit die to the plurality of conductive lead structures on the first side of the premolded lead frame assembly;', 'forming a second molded structure over the integrated circuit die and plurality of conductive lead structures; and', 'singulating the lead frame assembly, the singulating including severing the first molded structure, the second molded structure and the plurality of conductive lead structures along the parting line resulting in an integrated circuit chip package having at least one conductive lead with a side portion and a plated recessed portion., 'providing a premolded lead frame assembly, including2. The method of claim 1 , wherein providing the premolded lead frame assembly ...

Semiconductor device and leadframe

A semiconductor device includes a leadframe, a semiconductor chip mounted on the leadframe, and an encapsulation resin covering the leadframe and the semiconductor chip. The leadframe includes a terminal having a pillar shape. The terminal includes a first end surface, a second end surface facing away from the first end surface, and a side surface extending vertically between the first end surface and the second end surface. The side surface is stepped to form a step surface facing away from the second end surface and having an uneven surface part formed therein. A first portion of the terminal extending from the first end surface toward the second end surface and including the step surface is covered with the encapsulation resin. A second portion of the terminal extending from the first portion to the second end surface projects from the encapsulation resin.

INTERCONNECTION SUBSTRATES FOR INTERCONNECTION BETWEEN CIRCUIT MODULES, AND METHODS OF MANUFACTURE

An interposer () has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs ). The interposer includes a substrate made of multiple layers (). Each layer can be a substrate (S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure () made of vertical layers () corresponding to the interposers' layers. The structure is diced along horizontal planes () to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided. 1. A structure comprising a member operable to function at least as an interconnection substrate providing interconnection between circuit modules , the member comprising:a plurality of contact pads for connection to the circuit modules;interconnection circuitry providing interconnection between at least two of the contact pads;wherein the contact pads comprise one or more first contact pads located at a top surface of the member;wherein the member comprises a multi-layer substrate comprising a plurality of first layers arranged in sequence one after another, each first layer being transverse to the top surface, the first layers comprising at least a part of the interconnection circuitry.2. The structure of wherein at least one first contact pad is part of at least one first layer.3. The structure of wherein the member comprises a dielectric overlying the multi-layer substrate claim 1 , wherein at least one first contact pad overlies the dielectric.4. The structure of wherein the interconnection circuitry comprises a continuous non-dielectric ...

Integrated fan-out package and method of fabricating the same

An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.

Package structure and fabrication method thereof

A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and having a surface exposed from the first surface of the dielectric layer; a plurality of conductive posts embedded in the dielectric layer and electrically connected to the first circuit layer and having one ends exposed from the second surface of the dielectric layer; a second circuit layer formed on the second surface of the dielectric layer and electrically connected the ends of the conductive posts exposed from the second surface of the dielectric layer; and a plurality of protruding elements formed on the surface of the first circuit layer exposed from the first surface of the dielectric layer, thereby providing a large contact area so as to strengthen bonding between a semiconductor chip and the first circuit layer of the package structure.

SEMICONDUCTOR DEVICE AND A METHOD OF MAKING A SEMICONDUCTOR DEVICE

A semiconductor device and a method of making the same. The device includes a substrate mounted on a carrier, the substrate comprising a High Electron Mobility Transistor (HEMT) having a source, a gate and a drain. The carrier comprises an electrically conductive shielding portion for providing shielding against electromagnetic interference associated with switching of the device during operation. The electrically conductive shielding portion is electrically isolated from the source and from the backside of the substrate. 1. A semiconductor device comprising a substrate mounted on a carrier , the substrate comprising a High Electron Mobility Transistor (HEMT) having a source , a gate and a drain ,wherein the carrier comprises an electrically conductive shielding portion for providing shielding against electromagnetic interference associated with switching of the device during operation, andwherein the electrically conductive shielding portion is electrically isolated from the source and from the backside of the substrate.2. The semiconductor device of claim 1 , wherein the electrically conductive shielding portion extends at least partially beneath the substrate.3. The semiconductor device of claim 1 , wherein the electrically conductive shielding portion extends around a periphery of the substrate claim 1 , when viewed from above a major surface of the substrate claim 1 , at least partially to surround the substrate.4. The semiconductor device of claim 1 , wherein the electrically conductive shielding portion is electrically connected to the drain.5. The semiconductor device of claim 1 , wherein the electrically conductive shielding portion is electrically connected to an external potential.6. The semiconductor device of claim 1 , wherein the carrier comprises a dielectric substrate having one or more metal layers.7. The semiconductor device of claim 6 , wherein the backside of the substrate is mounted on a metal layer located on an upper surface of the dielectric ...

Low Profile Leaded Semiconductor Package

In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed. 1. A method of fabricating a semiconductor package comprising:thinning a metal piece at locations where a die pad and a cantilever segment of a lead are to be formed;thinning the metal piece at a location where a foot of the lead is to be formed; andsevering the metal piece between the location of the die pad and the location of the cantilever segment of the lead.2. The method of wherein thinning the metal piece at a location where a foot of the lead is to be formed and severing the metal piece between the location of the die pad and the location of the cantilever segment of the lead are performed in a single process step.3. The method of wherein thinning a metal piece at locations where a die pad and a cantilever segment of a lead are to be formed comprises thinning the metal piece at a location of a gap between the die pad and the cantilever segment of the lead.4. The method of wherein thinning the metal piece at locations where the die pad claim 3 , the cantilever segment of the lead claim 3 , and the gap between the die pad and the cantilever segment of the lead are to be formed comprises depositing a first mask layer on a first side of the metal piece claim 3 , forming an opening in the first mask layer corresponding to the locations where the die pad claim 3 , the cantilever segment of the lead claim 3 , and the gap between the die pad and the cantilever segment of the lead are to be formed claim 3 , and partially etching the metal piece through the first opening in the first mask layer.5. The method of wherein thinning the metal ...

METHODS AND STRUCTURES FOR INCREASING THE ALLOWABLE DIE SIZE IN TMV PACKAGES

A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized. 131-. (canceled)32. An electronic package comprising:a substrate comprising an upper substrate side;an electronic component comprising an upper component side, a lower component side, and lateral component sides, the lower component side coupled to the upper substrate side;a first plurality of wires laterally displaced from a first lateral component side of the electronic component, each of the first plurality of wires comprising a first upper wire end and a first lower wire end, the first lower wire end of each of the first plurality of wires coupled to the upper substrate side; anda package body enclosing the first plurality of wires and the electronic component, the package body comprising a lower package body side facing the substrate and an upper package body side facing away from the substrate, the first upper wire end of each of the first plurality of wires exposed from the upper package body side of the package body.33. The electronic package of claim 32 , wherein the first plurality of wires is arranged in a row at the first lateral component side.34. The electronic package of claim 33 , wherein the row of the first plurality of wires is parallel to the first lateral component side.35. The electronic ...

SYSTEM AND METHODS FOR SUBSTRATES

One embodiment is directed towards a molded insulator substrate. The molded insulator substrate includes a first insulator having a first surface and a second surface. A recess in said first surface of the first insulator is configured to facilitate venting of a second insulator over exposed regions of the first surface. A first conductive terminal is exposed through the first surface. A second conductive terminal is exposed through the second surface and electrically coupled to the first terminal. 1. A power supply component , comprising:a molded insulator carrier having a first surface and a second surface;a recess in said first surface of the molded insulator carrier configured to facilitate venting of an encapsulant over regions of the first surface;a first conductive terminal having a portion coplanar with the first surface;a second conductive terminal having a portion coplanar with the second surface and electrically coupled to the first terminal; anda device having a conductive device terminal where the device is mounted over the recess and the conductive device terminal is coupled to the first conductive terminal forming a gap between the device and the first surface,wherein the encapsulant encapsulates the device and substantially fills the gap and the recess.2. The power supply component of claim 1 , further comprising an interconnect coupling the first conductive terminal and the second conductive terminal.3. The power supply component of claim 1 , wherein a cross-sectional shape of the recess is rectangular.4. The power supply component of claim 1 , wherein the recess forms claim 1 , wholly or in part claim 1 , a closed plane shape on the first surface.5. The power supply component of claim 1 , wherein the device comprises a driver integrated circuit.6. The power supply component of claim 1 , wherein the device comprises a PWM controller integrated circuit.7. A power supply component claim 1 , comprising:a molded insulator carrier having a first surface ...