МНОГОСЛОЙНАЯ КОРПУСНАЯ СБОРКА СО ВСТРОЕННОЙ АНТЕННОЙ

Использование: для создания многослойной корпусной сборки. Сущность изобретения заключается в том, что корпусная сборка интегральной микросхемы (IC) содержит первый слой, имеющий первую сторону и вторую сторону, расположенную напротив первой стороны; второй слой, соединенный с первой стороной первого слоя; один или более антенных элементов, соединенных со вторым слоем; и третий слой, соединенный со второй стороной первого слоя, при этом первый слой представляет собой армирующий слой, имеющий модуль упругости при растяжении больше, чем модуль упругости при растяжении второго слоя и третьего слоя, при этом первый слой образует плоскость, проходящую в горизонтальном направлении; и никакие металлизированные элементы для маршрутизации электрических сигналов в горизонтальном направлении не расположены непосредственно на первом слое. Технический результат - обеспечение возможности уменьшения потерь в проводниках. 3 н. и 16 з.п. ф-лы, 9 ил.

КОНСТРУКТИВНЫЙ ЭЛЕМЕНТ

... 1. Конструктивный элемент, в частности полупроводниковый компонент, содержащий первую микросхему (10), размещенную на второй микросхеме (20), в котором первая и вторая микросхемы (10, 20) имеют соответственно на одной из своих основных поверхностей (13, 23) первую, соответственно, вторую металлизации (12, 22), которые обращены одна к другой, при этом первые участки металлизаций (12, 22) предусмотрены для выполнения электрического соединения между первой и второй микросхемами (10, 20), а вторые участки металлизации (12, 22) предусмотрены как дополнительная электрическая функциональная поверхность вне первой и второй микросхем (10, 20). 2. Конструктивный элемент по п. 1, отличающийся тем, что первая и/или вторая металлизация (12, 22) через контактные элементы (14, 24) соединены с контактными площадками (11, 21), расположенными в верхнем слое металлизации. 3. Конструктивный элемент по п.1 или 2, отличающийся тем, что первая или вторая микросхема (10, 20) в местах, в которых противолежащая ...

СТРУКТУРА СОЕДИНЕНИЙ ЭЛЕМЕНТОВ МИКРОСХЕМЫ С ПОНИЖЕННЫМ УРОВНЕМ ПЕРЕКРЕСТНЫХ ПОМЕХ ДЛЯ УЛУЧШЕНИЯ ВНЕЧИПОВОЙ ИЗБИРАТЕЛЬНОСТИ

Для снижения уровня перекрестных помех компоненты микросхемы с возвратной внечиповой РЧ избирательностью: дифференциальные функциональные блоки, передающие линии и внечиповые фильтры объединены структурой, которая компенсирует паразитные емкости, обусловленные всеми дифференциальными элементами микросхемы. Эта структура содержит первый подслой с дифференциальными генерирующим и приемным контурами. Контуры подсоединены к близко расположенным одна от другой концевым контактным площадкам посредством двух близко расположенных одна от другой (на некотором участке их длины) дифференциальных передающих линий, каждая из которых имеет постоянный собственный импеданс и скомпенсированную емкость по отношению к земле. Передающие линии снабжены общей заземляющей платой. Во втором подслое, имеющем возвратное межсоединение с первым подслоем, выполнен РЧ функциональный блок, в частности фильтр или линия задержки.

Verbesserte Mehrschichtverpackung

3-DIMENSIONALES GEHÄUSE FÜR MONOLITHISCHE INTEGRIERTE MIKROWELLEN/MILLIMETERWELLETERWELLEN-SCHALTUNGEN

Verbindungsverfahren zwischen einer integrierten Schaltung und einem Schaltungsträger und an dieses Verfahren angepasste, integrierte Schaltung

VERRINGERUNG DER ANFÄLLIGKEIT VON INTEGRIERTEN SCHALTUNGEN UND SENSOREN FÜR HOCHFREQUENZSTÖRUNGEN

Eine Vorrichtung umfasst eine Masseebene (2), einen integrierten Schaltungschip (1), der auf der Masseebene (2) angeordnet ist, wobei der integrierte Schaltungschip (1) eine oder mehrere elektrisch leitende Schichten (10) umfasst, die eine Peripherie des integrierten Schaltungschips (1) umgeben, und eine Vielzahl von Bonddrähten (9), die die eine oder mehreren elektrisch leitenden Schichten (10) mit der Masseebene (2) elektrisch verbinden.

Methode zur Verminderung der gegenseitigen Induktanz zwischen Verbindungsdrähten einer Hochfrequenzverstärkerschaltung

Magnetische Abschirmungsstruktur

Eine magnetische Abschirmungsstruktur ist teilweise mit einem magnetischen Abschirmungskörper versehen, der durch Metallplattierung auf mindestens einer der Außenfläche und der Innenfläche gebildet ist, die die Oberfläche eines Gehäuses aus einem dielektrischen Material bilden.

Gehäuse einer integrierten Schaltung.

Gehäuse einer integrierten Schaltung.

Gehäuse für elektrische/elektronische Schaltungen

HF-Frontend für ein Automobilradarsystem

Es wird eine Anordnung (1) für ein HF-Frontend eines linsenbasierten 77-GHz Automobilradarsystems beschrieben, aufweisend ein HF-Substrat (3) aufweisend eine Oberseite (3a) und eine Unterseite (3b), und einen Halbleiterchip (2), wobei der Halbleiterchip (2) auf der Oberseite (3a) des HF-Substrats (3) angeordnet ist, und wobei das HF-Substrat (3) ein mechanisch festes Material aufweist. Ferner wird ein Verfahren zur Herstellung einer Anordnung (1) für ein HF-Frontend eines linsenbasierten 77-GHz Automobilradarsystems sowie eine Verwendung einer Anordnung (1) für ein HF-Frontend in einem linsenbasierten 77-GHz Automobilradarsystem beschrieben.

Eingebaute Multi-Package-Wellenleiter-Verbindungen

Ausführungsbeispiele können sich auf ein elektronisches Modul zur Verwendung in einer elektronischen Vorrichtung beziehen. Das elektronische Modul kann eine gedruckte Schaltungsplatine (PCB) mit einem ersten Die und einem zweiten Die umfassen. Ein Wellenleiterkanal kann kommunikativ mit dem ersten Die und dem zweiten Die gekoppelt sein und ausgebildet sein zum Übermitteln eines elektromagnetischen Signals von dem ersten Die zu dem zweiten Die. Bei Ausführungsbeispielen kann das elektromagnetische Signal eine Frequenz größer als 30 Gigahertz (GHz) aufweisen. Andere Ausführungsbeispiele können beschrieben oder beansprucht sein.

MIKROWELLEN-/MILLIMETERWELLEN-SCHALTUNGSSTRUKTUR MIT EINZELN MONTIERTEN ELEMENTEN VOM FLIPCHIPTYP UND HERSTELLUNGSVERFAHREN DAFÜR

Leiterplatte, Hochfrequenzmodul und Radarvorrichtung

Die Erfindung bezieht sich auf eine Leiterplatte. Die Leiterplatte (10) umfasst ein Substrat (1), eine Wellenleiterleitung (2) und einen laminierten Wellenleiter (3). Die Wellenleiterleitung (2) ist zumindest teilweise auf einer ersten Oberfläche des Substrats (1) angeordnet. Die Wellenleiterleitung (2) überträgt ein Hochfrequenzsignal. Der laminierte Wellenleiter (3) ist innerhalb des Substrats (1) ausgebildet. Der laminierte Wellenleiter (3) ist mit der Wellenleiterleitung (2) elektromagnetisch gekoppelt und weist einen Ausleitungsabschnitt (3a) auf, der vom Inneren des Substrats (1) zu einer anderen Oberfläche als der ersten Oberfläche ausgeleitet ist. Der laminierte Wellenleiter (3) umfasst eine dielektrische Schicht (31), zwei Hauptleiterschichten (32) und eine Durchgangsleitergruppe (33). Die zwei Hauptleiterschichten (32) legt die dielektrische Schicht (31) in einer Dickenrichtung davon ein. In der Durchgangsleitergruppe (34) sind mehrere Durchgangsleiter (33) entlang einer Hochfrequenzsignal-Übertragungsrichtung ...

BRÜCKE FÜR RADIOFREQUENZ- (RF) MULTI-CHIP-MODULE

Ausführungsbeispiele können sich auf ein Radiofrequenz- (RF) Multi-Chip-Modul beziehen, das einen ersten RF-Die und einen zweiten RF-Die umfasst. Der erste und zweite RF-Die können mit einem Package-Substrat an einer inaktiven Seite des jeweiligen Dies gekoppelt sein. Eine Brücke kann mit einer aktiven Seite des ersten und zweiten RF-Dies gekoppelt sein, sodass der erste und zweite RF-Die kommunikativ durch die Brücke gekoppelt sind und sodass sich der erste und zweite RF-Die zumindest teilweise zwischen dem Package-Substrat und der Brücke befinden. Andere Ausführungsbeispiele können beschrieben oder beansprucht sein.

Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitervorrichtung

... [Aufgabe] Bereitstellen einer Halbleitervorrichtung, bei der die Erzeugung einer Verzerrung eines Signals unterdrückt wird, und eines Verfahrens zur Herstellung der Halbleitervorrichtung.[Lösung] Eine Halbleitervorrichtung, die Folgendes beinhaltet: ein Transistorgebiet, in dem ein Feldeffekttransistor bereitgestellt ist, und ein Verbindungsgebiet, in dem eine Metallschicht bereitgestellt ist, die elektrisch mit dem Feldeffekttransistor verbunden ist. Das Verbindungsgebiet beinhaltet eine Isolierschicht, die zwischen der Metallschicht und einem Substrat bereitgestellt ist, und eine Schicht mit niedriger Permittivität, die in der Isolierschicht unter der Metallschicht bereitgestellt ist und eine niedrigere Permittivität als die Isolierschicht aufweist.

Modul für elektronische Komponente

Microwave module comprising substrate with HF and LF layers forming distribution network structures, includes intervening insulating layer

The high frequency structure layer (4) is separated from the low frequency structure layer (3) by the insulating layer (1). An Independent claim is included for the method of manufacture, which especially employs fine pitch flip-chip technology for bonding to the substrate.

RF LEISTUNGSBAUTEIL MIT EINEM DOPPELTEN ERDSCHLUSS

Packung für Mikrowellenschaltung

Gehäuse für ein oberflächenmontierbares elektronisches Bauelement

Heat sink for HF transistors etc. - is in form of HF delay line with transistor at line end

The heat sink (1) is in the form of a high frequency delay line, on whose one end (3) the high frequency transistor (2) is mounted. The other end of the delay line serves for tapping or supply, of the high frequency. Preferably the heat sink has two branches extending from the transistor in two directions. At least one end of the brances can not be used for tapping, or supply, of the high frequency. This branch may be so long that its impedance near the transistor is much higher than its wave resistance. The latter may be increased by foiling, or by slits orthogonal to the current flow or by meandering structures, or by ferromagnetic material inside or round the heat sink.

Chipkartenmodul-Anordnung, Chipkarten-Anordnung und Verfahren zum Herstellen einer Chipkarten-Anordnung

Chipkartenmodul-Anordnung umfassend (a) eine erste und eine zweite Oberfläche die gegenüberliegend sind; und (b) eine Chip-Aufnahme für einen oder mehrere Halbleiterchips auf den Oberflächen; und (c) eine Verbindungsmaterial-Aufnahmefläche auf einer der beiden Oberflächen, wobei die Verbindungsmaterial-Aufnahmefläche nur einen Abschnitt der Oberfläche einnimmt.

Packungen für drahtlose Signalübertragung mit integrierter Antennengruppe

Antennenpackungsstrukturen werden bereitgestellt, um Packungen für drahtlose Signalübertragung zu implementieren. Eine Antennenpackung enthält zum Beispiel ein mehrschichtiges Packungssubstrat, eine ebene Antennengruppe, Antennenspeiseleitungen und Widerstandsübertragungsleitungen. Die ebene Antennengruppe beinhaltet eine Gruppe von aktiven Antennenelementen und künstliche Antennenelemente, die die Gruppe von aktiven Antennenelementen umgeben. Jedes aktive Antennenelement ist mit einer entsprechenden Antennenspeiseleitung verbunden, und jedes künstliche Antennenelement ist mit einer entsprechenden Widerstandsübertragungsleitung verbunden. Jede Widerstandsübertragungsleitung verläuft durch das mehrschichtige Packungssubstrat und endet in derselben Metallisierungsschicht des mehrschichtigen Packungssubstrats.

Radarmodul

Radarmodul (100); aufweisend:ein erstes Substrat (10) mit einer darauf angeordneten Umverdrahtungslage (11);ein am ersten Substrat (10) in einer Moldstruktur (30) eingeschlossener HF-Chip (1);wobei das erste Substrat (10) mit der Moldstruktur (30) auf einem zweiten Substrat (20) angeordnet ist;wobei mittels der Umverdrahtungslage (11) elektrische Anschlüsse (12) des HF-Chips (1) zu Lötkugeln (21) am zweiten Substrat (20) geführt sind;wobei auf der Moldstruktur (30) ein mittels eines 3D-Druckprozesses gefertigtes Antennenelement (40) angeordnet ist;wobei das Antennenelement (40) definierte Metallisierungsflächen aufweist.

Modul mit einer Hochfrequenzschaltung

HALBLEITER-BAUELEMENTCHIP UND HERSTELLUNGSVERFAHREN FÜR EINEN HALBLEITER-BAUELEMENTCHIP

Ein Halbleiter-Bauelementchip beinhaltet ein Halbleiter-Substrat, das eine erste Oberfläche und eine zweite Oberfläche gegenüber der ersten Oberfläche aufweist, ein Halbleiter-Bauelement, das an der ersten Oberfläche des Halbleiter-Substrats angeordnet ist, eine Verbindungsanordnung, die ein Ende verbunden mit dem Halbleiter-Bauelement und ein anderes Ende freiliegend an einer Oberfläche einer Funktionsschicht aufweist, die an der ersten Oberfläche des Halbleiter-Substrats angeordnet ist, mehrere externe Verbindungselektroden, die an der Oberfläche der Funktionsschicht montiert sind und elektrisch mit dem anderen Ende der Verbindungsanordnung verbunden sind, einen Abschirmfilm für eine elektromagnetische Welle zum Abschirmen elektromagnetischer Wellen, der an der zweiten Oberfläche des Halbleiter-Substrats und seitlichen Oberflächen der Funktionsschicht angeordnet ist, und eine Erdungsverbindung, die elektrisch mit dem elektromagnetischen Abschirmfilm verbunden und an der Funktionsschicht ...

Halbleitervorrichtung

Halbleitervorrichtung miteinem Gehäuse (1),einer Eingangsanpassschaltung (4) und einer Ausgangsanpassschaltung (5) in dem Gehäuse (1) undeiner Mehrzahl von Transistorchips (6) zwischen der Eingangsanpassschaltung (4) und der Ausgangsanpassschaltung (5) in dem Gehäuse (1),wobei jeder Transistorchip (6) ein rechteckiges Halbleitersubstrat (8) mit langen Seiten und kurzen Seiten, die kürzer als die langen Seiten sind, sowie eine Gateelektrode (9), eine Drainelektrode (10) und eine Sourceelektrode (11) auf dem Halbleitersubstrat (8) enthält,die Gateelektrode (9) eine Mehrzahl von Gatefingern (9a), die entlang der langen Seiten des Halbleitersubstrats (8) angeordnet sind, und eine Gateanschlussfläche (9b) enthält, die mit der Mehrzahl von Gatefingern (9a) gemeinsam verbunden ist und die über einen Draht (12) mit der Eingangsanpassschaltung (4) verbunden ist,die Drainelektrode (10) über einen Draht (13) mit der Ausgangsanpassschaltung (5) verbunden ist unddie langen Seiten der Halbleitersubstrate ...

ZELLMONTIERTE MONOLITHISCHE INTEGRIERTE SCHALTUNG

Diese Offenbarung stellt eine zellmontierte monolithische integrierte Schaltung bereit. Ein Batteriesystem weist Folgendes auf: eine Batteriezelle, die einen Becher beinhaltet, und ein keramisches Substrat, das eine gemusterte metallisierte Fläche beinhaltet und über einen wärmeleitfähigen Klebstoff an dem Becher montiert ist. Das Batteriesystem weist zudem eine monolithische integrierte Schaltung auf, die Daten über die Zelle misst und überträgt und derart an der gemusterten metallisierten Fläche montiert ist, dass das keramische Substrat und die monolithische integrierte Schaltung elektrisch voneinander isoliert sind.

Hochfrequenz-Halbleitervorrichtung

MONOLITHISCHE INTEGRIERTE MIKROWELLENSCHALTUNGEN AUS GALLIUMARSENID MIT THERMISCH LEITENDEN HOCKERKONTAKTEN

Laminierter Kondensator und Montageanordnung

Laminierter Kondensator mit folgenden Merkmalen: einem Kondensatorkörper (43) mit einem laminierten Stapel einer Mehrzahl von dielektrischen Schichten (42); zumindest einem Paar einer ersten und einer zweiten inneren Elektrode (44, 45), die sich gegenüberliegen, wobei zumindest eine der dielektrischen Schichten (42) zwischen denselben angeordnet ist, in dem Kondensatorkörper (43); einer Mehrzahl von ersten Durchführungsleitern (46), die zumindest eine der dielektrischen Schichten (42) durchdringen und die innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die ersten Durchführungsleiter (46) von den zweiten inneren Elektroden (45) elektrisch isoliert und mit den ersten inneren Elektroden (44) elektrisch verbunden sind, und einer Mehrzahl von zweiten Durchführungsleitern (47), die den Kondensatorkörper (43) durchdringen und innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die zweiten Durchführungsleiter (47) von den ersten inneren Elektroden (44) elektrisch isoliert ...

Hermetic high-frequency module and method for producing it has a ceramic casing base and a ceramic casing cover with an adjusting device for positioning in a hollow conductor on the casing base.

The invention relates to a high frequency module with a hollow conductor structure, consisting of a housing bottom and a housing lid, preferably consisting of ceramic. The housing bottom and the housing lid are preferably co-ordinated with each other in terms of their expansion characteristics. The adjusting device is mounted on the housing lid for positioning on the housing bottom, and consists of a raised photosensitive resist part which tapers conically starting from the housing lid. The adjusting device engages with the hollow conductor on assembly. The layer thickness of the adjusting device is approximately 100 to 200 um. The housing bottom and the housing lid are permanently interconnected by soldering, preferably using solders which are introduced galvanically in solder deposits. To this end, the solder is either applied locally to the housing lid surface or introduced in vias which are structured in the lid.

Multilayer circuit module for wireless communication system has passive high frequency components and passive base component layer

A connection integration region includes at least one connecting layer (404,408) for electrically coupling the circuit components (409). A passive base component integration region has a passive base component layer (405,407). A passive high frequency component integration region comprises passive high frequency components. An Independent claim is included for a method of manufacturing a multilayer circuit module.

Method and apparatus for high performance passive-active circuit integration

A silicon on insulator (SOI) device has active and passive 125 radiofrequency (RF) circuit components integrated into an SOI substrate, which may include an interlayer dielectric layer formed above a buried oxide (BOX) layer. A dielectric carrier substrate is bonded to the SOI substrate, reducing capacitive coupling and non-linear interactions, and may include fused silicon, borosilicate glass, group III-V materials, sapphire, or high resistance silicon. The dielectric carrier substrate may be bonded by an adhesive layer to the interlayer dielectric layer, or anodically bonded to the BOX layer. Methods of forming the SOI device include removal of a semiconductor carrier substrate. A protective layer may be formed on the BOX layer, and a conductive via formed through both, connecting the RF circuit element to a contact 225 on the protective layer. The RF SOI device may be incorporated into couplers, antenna switching networks, impedance matching or tuning modules.

leadframe package with integrated partial waveguide interface

Microwave circuit package

Input/output architecture for mounted processors, and methods of using same

INTERCONNECTING COMPONENTS

TRANSISTOR MOUNTING APPARATUS

Improved matching techniques for wide-bandgap power transistors

Method for manufacturing semiconductor device

An amorphous Ni-P layer (10) which cancels crystallinity of a base metal layer is formed on the base metal layer, such as an FET electrode, by electroless gilding and then an electrolytic Au gilding layer (9) is formed on the amorphous Ni-P layer. Thus, luster nonuniformity of the electrolytic Au gilding layer formed on the base metal layer, such as the FET electrode, is avoided so that a position of an electrode pad can be mechanically detected in an easy manner, during auto- bonding, and its appearance is improved. Processing of MMICs is thus improved. ...

RESIN ENCAPSULATED DIODES

A diode 18, 19 and its overvoltage protection resistance 41 are assembled in a moulded resin package. The short lead between the diode and the resistance eliminates stray capacitance from the circuit and makes the device suitable especially for high-frequency use. Instead of being integrated on a substrate 18, the resistance may be mounted within the package on a connecting pin or formed in a connection wire within the package.

CERAMIC SUBSTRATE FOR HYBRID MICROCIRCUITS AND METHOD OF MAKING THE SAME

Demountable hybrid assemblies with microwave-bandwidth interconnects

SEALING GLASS COMPOSITIONS

... 1359050 Glass composition PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 29 Dec 1971 [30 Dec 1970 (2)] 60314/71 Heading C1M [Also in Division B3] A sealing glass consists in mol per cent of SiO 2 4-20; B 2 O 3 20-45; Li 2 O 5-10; ZnO 30-55; Al 2 O 3 0-5 and CaO + SrO + BaO 0-10. Such a glass is produced by melting a mixture consisting of in weight per cent SiO 2 3-16; B 2 O 3 18-41; Li 2 CO 3 4À5-10; ZnO 33-60; Al 2 O 3 0-7 and CaCO 3 +SrCO 3 +BaCO 3 0-25. A ceramic (e.g. Al 2 O 3 or BeO) element can be sealed to a ceramic substrate having a metal (e.g. Au or an Fe-Ni-Co alloy) pattern thereon by depositing a layer of the glass by means of a suspension on a surface of the ceramic element, pre-melting the glass at a temperature of between 800 and 1100‹ C., placing the element on the substrate and heating for several minutes at a temperature which is less than 800‹ C. The glass layer may be deposited on the substrate by forming a frit thereof suspended in an organic liquid (e.g. alcohol, ...

PACKAGES FOR ELECTRONIC CIRCUITS

Hybrid integrated circuit module

Reconstituted device including die and functional material

Dies from a wafer are reassembled with passive components and encapsulated to form a reconstituted electronic device 10 comprising a die 11, a passive, functioning component 13 and a metallic redistribution layer 15 which defines an electronic component in an area at least partially above the functioning material. The electronic component may be a metal-oxide-metal capacitor, an inductor or an antenna. The functioning material may be ceramic or it may be a ferrite. The functioning material may surround the die. In one embodiment the functioning material is a ceramic body with a metallic coating 110 (figure 10) on a face opposite that of the surface of the substrate on which the die and functioning material are embedded, a metallic via 102 (figure 9) is included through the ceramic body to contact the metal coating, the redistribution layer/ceramic body/metal coating structure forms a capacitor. In another embodiment the functioning material may be a metal carrier 120 (figure 11) with an ...

Semiconductor chip housing and method of manufacture

A semiconductor chip housing provides hermetic sealing and appropriate electrical characteristics for use at high frequencies. The housing comprises a substrate in which the chip is mounted and a cylindrical tube having a top cover and extending above the substrate which impinges on a base and thus hermetically seals the chip. Microthin leads extend from the substrate periphery to the chip. The leads carrying high frequency signals have notches therein to compensate for the impedance introduced by the tube and to enable the microstrip to present a constant impedance at high frequencies throughout its length.

Devices and methods related to radio-frequency filters on silicon-on-insulator substrate

High-frequency circuit

In a high-frequency circuit arrangement, passive parts of the circuit are realized in a semiconductor body in which active circuit elements of another semiconductor material are located in recesses in the semiconductor body. When the semi-conductor body is at least in part low-ohmic, a reference plane, for example, the ground plane, can extend very close to the elements of the circuit arrangement. Consequently, due to the shorter connections required, parasitic effects are considerably reduced. When only one active element is mounted and only connections for this element are formed on the semiconductor body, a very suitable support for mounting and measurement is obtained.

Nput/output architechture for mounted processors, and methods of using same

Coil arrangement with metal filling

Package structures including discrete antennas assembled on a device

A semiconductor device

... 1,130,666. Semi-conductor device. NIPPON ELECTRIC CO. Ltd. 27 April, 1967 [30 Sept., 1966], No. 19508/67. Heading H1K. A semi-conductor device comprises a semiconductor element disposed in a substantially central recess on one side of a flat conductor member with one terminal connected thereto so that the conductor member serves as a common electrode for the device, there being a plurality of slots in the conductor member extending from the recess to its periphery with a signal conductor mounted in each slot and separated from the common conductor member by a dielectric layer, the signal conductors being connected to further respective terminals and the semiconductor element. As shown in Fig. 1a, the flat common conductor 13 is in the form of a disc having a diametrical slot cut part of the way through its thickness. A ceramic insulator, such as steatite, is laid in the base of the slot and flat strip conductors 11 and 12 of oxygen-free copper are arranged within the slot as shown. A diffused ...

Improvements in or relating to varactor diode devices

... 1,127,678. Semi-conductor devices; variable capacitors; waveguide switches. MARCONI CO. Ltd. 1 Feb., 1967 [7 May, 1966], No. 20305/66. Headings H1K, H1M and H1W. The housing of a varactor diode includes two metal members, the separation between which can be varied to adjust the capacitance in parallel with the diode. The diode is designed to operate as a waveguide switch, and in such use the variable shunt capacitance is set to the value appropriate to provide an acceptable voltage standing wave ratio performance, this variable capacitance replacing the external matching impedance customarily used for this pupose. The diode 6 is mounted on one of the metal members 1 which constitutes the base of an enclosed housing, and the other metal member 5 is a rod which is axially movable to vary its distance from the housing base. The rod may be a sliding fit, or a screw threaded fit, in the housing cover 2. Electrical connection to the upper electrode of the diode is by way of a gauze 8 connected ...

SEMICONDUCTOR DEVICE

... 1,264,055. Semi-conductor devices. LICENTIA PATENT-VERWALTUNGS G.m.b.H. 17 March, 1970 [21 March, 1969], No. 12838/70. Heading H1K. A semi-conductor device such as a power transistor 17 is mounted on an insulating plate 2 which in turn is mounted on a metal plate 1. Two metallized areas 5, 6 on the insulating plate 2 extend across the edges of the plate 2 to contact the metal plate 1 while two further metallized areas 7, 8 on the plate 2, one of which areas 8 extends between the first two areas 5, 6, carry terminal strips 3, 4. The electrodes of the device 17 are connected to the metallized areas 5-8. In the preferred embodiments the collector of the transistor is mounted directly on the area 8, parallel wires 20 being used to connect the base electrode 18 to the area 7 and the emitter electrode or electrodes 19 to the areas 5, 6. A modified metallization pattern is also described. The metal plate 1 may be of Mo or vacon, the insulating plate 2 being of beryllium oxide and the metallized ...

Packaging system for semiconductor components

SEMICONDUCTOR MICROWAVE DEVICE OF THE KIND UTILIZING THE TRANSIT-TIME EFFECTS

... 1516945 Oscillators and amplifiers using negative resistance semi-conductor devices THOMSON CSF 25 March 1976 [28 March 1975] 12148/76 Heading H3T A transit time oscillator or amplifier comprises a transistor type semiconductor capable of oscillating at high frequency when a direct voltage is applied to across its collector and emitter and a transmission line connected to the base and collector electrodes of the semiconductor and having a short circuit termination which is adjustable along the line to neutralize the damping effect of the collector-base capacitance on the high frequency oscillations. In one embodiment, Fig. 4, the collector of the transistor is soldered to a microstrip base 41 and the base is connected to the transmission line 45 by a lead 150 and the microstrip circuit. The movable h.f. short circuit comprises a cylinder 46 in the line. The output is taken from the emitter via lead 160 and a further coaxial line 44. In a modification, Fig. 5 (not shown) the lines 44 and ...

PROCESS FOR PRODUCING SEMICONDUCTOR DEVICES WITH A VERY LOW THERMAL RESISTANCE

An integrated circuit chip assembly and a method of mounting an integrated circuit chip to external circuitry

HERMETIC HIGH FREQUENCY MODULE AND PROCEDURE FOR THE PRODUCTION

MULTI-CHIP HOUSING WITH INTEGRATED RF-ABILITIES

ELECTRONIC DEVICE, ARRANGEMENT AND PROCEDURE FOR MANUFACTURING AN ELECTRONIC DEVICE

MICROWAVE MINIATURE HOUSING AND PROCEDURE FOR THE PRODUCTION OF THIS HOUSING

COUPLING MECHANISM WITH INTERIOR CONDENSERS IN A MULTI-LAYER SUBSTRATE

PASSIVE SIGNAL PROCESSING COMPONENTS ON LIQUID CRYSTAL POLYMER AND MULTI-LAYER POLYMER BASIS FOR HF-/DRAHTLOS-MULTIPLE REEL-APPLICATIONS

INTEGRATED CIRCUIT AND PROCEDURE FOR THE PRODUCTION

CIRCUIT MODULE

IC HOUSING, CONSISTING OF THREE COATED DIELECTRIC PLATES.

DIELECTRIC MATERIAL of the SYSTEM (1X) BAO.XTIO2 IN PARTICULAR FOR USE IN a MICROWAVE DEVICE.

SEMICONDUCTOR ARRANGEMENT.

SCREEN FOR RADIO FREQUENCY CIRCUIT.

Semiconductor device, in particular transistor

Bulk effect oscillator

PACKING FOR MICROWAVE CONSTRUCTION UNITS

Clock distribution system

One embodiment includes a clock distribution system. The system includes a first resonator spine that propagates a first clock signal and a second resonator spine that propagates a second clock signal that is out-of-phase relative to the first clock signal. The system also includes at least one resonator rib each conductively coupled to at least one of the first and second resonator spines and being arranged as a standing wave resonator with respect to a respective at least one of the first and second clock signals to inductively provide the respective at least one of the first and second clock signals to an associated circuit via a respective transformer-coupling line. The system further includes an isolation element configured to mitigate at least one of inductive and capacitive coupling between the first and second clock signals.

2D and 3D RF lumped element devices for RF system in a package photoactive glass substrates

The present invention includes a method for creating a system in a package with integrated lumped element devices is system-in-package (SiP) or in photo-definable glass, comprising: masking a design layout comprising one or more electrical components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass, wherein the integrated lumped element devices reduces the parasitic noise and losses by at least 25% from a package lumped element device mount to a system-in-package (SiP) in or on photo-definable glass when compared to an equivalent surface mounted device.

Circuit structure having a flip-mounted matrix of devices

HIGH-FREQUENCY CIRCUIT AND HIGH-FREQUENCY PACKAGE

INTEGRATED CIRCUIT WITH INTERNAL IMPEDANCE MATCHING CIRCUIT

Manufacturing process for hybrid circuit modules including e lectronic chip devices

Telecommunications switch array with thyristor addressing

HERMETIC TRANSISTOR OUTLINE HOUSING COMPRISING A CERAMIC CONNECTION FOR HIGH FREQUENCY APPLICATIONS

High frequency power transistor device

INTERFERENCE SUPPRESSION FOR SEMICONDUCTOR SWITCHING DEVICES

Multiple ground signal path ldmos power package

Advanced hybrid power amplifier design

PACKAGE FOR MICROWAVE COMPONENTS

Method for packaging a circuit including exposed components (2) placed on a printed circuit (1), the circuit comprising microwave components (3). At least the part of the circuit that contains microwave components (3) is covered with a layer of syntactic foam (7) comprising a matrix of epoxy resin or cyanate ester, filled with microballoons of glass or a ceramic material. Subsequently, the entire circuit is covered with a moisture-proof top layer (8).

MICROWAVE TRANSISTOR PACKAGE

VOLTAGE LIMITING PROTECTION FOR HIGH FREQUENCY POWER DEVICE

An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

METAL BASE CIRCUIT BOARD AND ITS PRODUCTION PROCESS

A metal base circuit board to be used for a hybrid integrated circuit is provided. The circuit board comprises a metal plate and an insulating layer provided on the metal plate. Circuits are provided on the insulating layer and a plurality of semiconductors are mounted on the circuits. A low dielectric constant portion is provided on the metal plate under a part of the circuits on which no semiconductor is mounted. The low dielectric constant portion may be formed by providing a dent portion on the surface of the metal plate and filling the dent portion with a resin containing an inorganic filler. The side wall of the dent portion may have a gradient from 35 to 65°.

IMPROVEMENTS IN OR RELATING TO WAFER-SCALE- INTEGRATED ASSEMBLIES

IMPROVEMENTS IN OR RELATING TO WAFER-SCALE-INTEGRATED ASSEMBLIES In wafer-scale-integrated assemblies, microminiature transmission lines are utilized as inteconnects on the wafer. The extremely small cross-sectional area of a typical such line results in its total line resistance being relatively large. Such a line exhibits signal reflections and resonances. In practice, it is not feasible to eliminate these effects by conventionl load termination techniques. As a result, the frequency at which digital signals can be transmitted over such a line is typically limited to well below its so-called resonance limit. The invention enables the structural parameters of each line to be selected to meet specified design criteria that ensure optimal high-frequency performance of the line.

HIGH CUT-OFF FREQUENCY PLANAR SCHOTTKY DIODE IN A TRANSMISSION LINE

A planar Schottky diode is disclosed which is inserted into a transmission line without disruption of surge impedance. The diode comprises a plurality of parallel finger-like projections forming Schottky contacts distributed over a width of the transmission line and also of ohmic contacts surrounding these projections but with a longer contact edge.

PRE-MATCHED MODULE FOR AN ULTRA-HIGH FREQUENCY DIODE AND A PROCESS FOR FORMING THE BIASING CONNECTION FOR THE DIODE

A PRE-MATCHED MODULE FOR AN ULTRA-HIGH FREQUENCY DIODE AND A PROCESS FOR FORMING THE BIASING CONNECTION FOR THE DIODE The invention provides a process for mounting an ultrahigh frequency diode so as to form a pre-matched module. The module of the invention comprises a copper base, a quartz ring and a copper cover : these three parts, coated with gold at least on their facing faces, are assembled together by thermocompression. Inside this case, the diode chip, soldered to the base via a gold heat sink is biased by a false"beam-lead" connection, a metal star whose arms are curved, which reduces the inductance and capacity of this connection with respect to the base. The false "beam-lead" is formed by metalizing a mesa obtained on a silicon wafer.

BACK-TO-BACK SEMICONDUCTOR HIGH FREQUENCY DEVICE

Methods of operating electronic devices, and methods of providing electronic devices

Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing.

High-frequency switch

According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

Baluns for rf signal conversion and impedance matching

A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance.

Power amplifier circuit

There is provided a power amplifier circuit capable of improving cross isolation between a high frequency band power coupler and a low frequency band power coupler, by directly transmitting power to the high frequency band power coupler and the low frequency band power coupler from a power amplifier, and forming a predetermined inductance circuit or an LC resonance circuit in a line transmitting the power to the high frequency band power coupler. The power amplifier circuit may include a power amplifying unit supplied with power from the outside and amplifying an input signal, a coupling unit having a high frequency band power coupler and a low frequency band power coupler, and an isolation unit including a first power line and a second power line, wherein the first power line has an inductor blocking signal interference generated in a predetermined frequency band.

High speed digital interconnect and method

In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.

Rf bus controller

A radio frequency (RF) bus controller includes an interface and a processing module. The interface is coupled for communicating intra-device RF bus access requests and allocations. The processing module is coupled to receive an access request to an RF bus via the interface; determine RF bus resource availability; and when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource in response to the access request.

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Radiofrequency amplifier

An integrated radiofrequency amplifier with an operational frequency includes first and second Doherty amplifiers each having a main device, and a peak device connected at respective inputs and outputs by respective phase shift elements configured to provide a 90 degree phase shift at the operational frequency. An input of the amplifier is connected to the input of the main device of the first Doherty amplifier, an output of the amplifier is connected to the outputs of the peak devices of the first and second Doherty amplifiers and the input of the peak device of the first Doherty amplifier is connected to the input of the main device of the second Doherty amplifier by a phase shift element providing a 90 degree phase shift at the operational frequency.

Semiconductor device

A semiconductor device receiving as input a radio frequency signal having a frequency of 500 MHz or more and a power of 20 dBm or more is provided. The semiconductor device includes: a silicon substrate; a silicon oxide film formed on the silicon substrate; a radio frequency interconnect provided on the silicon oxide film and passing the radio frequency signal; a fixed potential interconnect provided on the silicon oxide film and placed at a fixed potential; and an acceptor-doped layer. The acceptor-doped layer is formed in a region of the silicon substrate. The region is in contact with the silicon oxide film. The acceptor-doped layer is doped with acceptors.

Applying trenched transient voltage suppressor (tvs) technology for distributed low pass filters

An electronic circuit includes a filtering circuit implemented with a distributed inductor-and-capacitor (LC) network that includes metal oxide effect (MOS) trenches opened in a semiconductor substrate filled with dielectric material for functioning as capacitors for the distributed LC network. The electronic circuit further includes a transient voltage suppressing (TVS) circuit integrated with the filtering circuit that functions as a low pass filter wherein the TVS circuit includes a bipolar transistor triggered by a diode disposed in the semiconductor substrate. The distributed LC network further includes metal coils to function as inductors disposed on a top surface of the semiconductor electrically contacting the MOS trenches.

Integrated millimeter wave transceiver

A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.

Rf-power device

An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.

Rf identification device with near-field-coupled antenna

An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.

Microwave unit and method therefore

A microwave unit comprising a motherboard and a package adapted to be assembled automatically in, e.g., a Surface Mounted Device, SMD, machine is disclosed. The microwave unit preferably comprises a connecting component interconnecting the motherboard and the package, and operable to make the signal ways on a same level at both the motherboard and at the package. Furthermore, the microwave unit preferably comprises a micro-strip adapted soldering tag for soldering on two sides.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Vertical ballast technology for power hbt device

Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.

Magnetic integration double-ended converter

The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.

Integrated circuit package including miniature antenna

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

On-Chip RF Shields with Backside Redistribution Lines

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.

Impedance matching arrangement for amplifier having split shunt capacitor and amplifier including the same

An amplifier having an operating frequency includes: an input port and an output port; three gain elements, each having an input terminal and an output terminal; an input matching network; and an output matching network. The input matching network includes: a first microstrip line which is connected to the input port and is an inductor at the operating frequency; a second microstrip line extending between the input terminals of the three gain elements; and a first split shunt capacitor connecting the first microstrip line to the second microstrip line. The output matching network includes: a third microstrip line which is connected to the output port and is an inductor at the operating frequency; a fourth microstrip line extending between the output terminals of the three gain elements; and a second split shunt capacitor connecting the third microstrip line to the fourth microstrip line.

Processing Signals by Couplers Embedded in an Integrated Circuit Package

Methods and systems for processing signals via directional couplers embedded in a package are disclosed and may include generating via a directional coupler, one or more output RF signals that may be proportional to a received RF signal. The directional coupler may be integrated in a multi-layer package. The generated RE signal may be processed by an integrated circuit electrically coupled to the multi-layer package. The directional coupler may include quarter wavelength transmission lines, which may include microstrip or coplanar structures. The directional coupler may be electrically coupled to one or more variable capacitances in the integrated circuit. The variable capacitance may include CMOS devices in the integrated circuit. The directional coupler may include discrete devices, which may be surface mount devices coupled to the multi-layer package or may be devices integrated in the integrated circuit. The integrated circuit may be flip-chip bonded to the multi-layer package.

Apparatus and methods for electronic amplification

Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved.

Semiconductor device

A semiconductor device includes: a main body chip; a circuit pattern on a front surface of the main body chip and including a first pad; a cap chip including a first recess in a front surface of the cap chip and a second recess in a back surface of the cap chip, the cap chip being joined to the main body chip with the first recess facing the circuit pattern; a second pad on a bottom surface of the first recess of the cap chip; a first metallic member inlaid in the second recess of the cap chip; a first through electrode electrically connecting the second pad to the first metallic member through the cap chip; and a bump electrically connecting the first pad to the second pad.

Through wafer vias and method of making same

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

System and Method for Wafer Level Packaging

In an embodiment, a semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first cavity disposed through it, and conductive material covers at least the bottom portion of the first cavity. An integrated circuit is disposed on the top surface of the conductive material. The device further includes a cap disposed on the top surface of the substrate, such that a cavity disposed on a surface of the cap overlies the first cavity in the substrate.

Semiconductor device

A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

Power semiconductor module with wireless saw temperature sensor

A power semiconductor module includes a housing, a base plate disposed in the housing, a plurality of substrates mounted to the base plate, a plurality of power transistor die mounted to the substrates and a plurality of terminals mounted to the substrates and protruding through the housing. The terminals are in electrical connection with the power transistor die. The power semiconductor module further includes a wireless surface acoustic wave (SAW) temperature sensor disposed in the housing of the power semiconductor module.

Semiconductor package including an integrated waveguide

Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

Packaging structure and method of fabricating the same

A packaging structure and a method of fabricating the same are provided. The packaging structure includes a substrate, first packaging element disposed on the substrate, a second packaging element disposed on the substrate and spaced apart from the first packaging element, a first antenna disposed on the first packaging element, and a metal layer formed on the second packaging element. The installation of the metal layer and the antenna enhances the electromagnetic shielding effect.

Semiconductor device and fabrication method therefore

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

Interposer and semiconductor package with noise suppression features

Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

Structure for High-Speed Signal Integrity in Semiconductor Package with Single-Metal-Layer Substrate

A semiconductor chip ( 101 ) with bond pads ( 110 ) on a substrate ( 103 ) with rows and columns of regularly pitched metal contact pads ( 131 ). A zone comprises a first pair ( 131 a, 131 b ) and a parallel second pair ( 131 c, 131 d ) of contact pads, and a single contact pad ( 131 e ) for ground potential; staggered pairs of stitch pads ( 133 ) connected to respective pairs of adjacent contact pads by parallel and equal-length traces ( 132 a, 132 b , etc.). Parallel and equal-length bonding wires ( 120 a, 120 b , etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

Wireless ic device

A wireless IC device that improves radiation gain without increasing substrate size and easily adjusts impedance, includes a multilayer substrate including laminated base layers. On a side of an upper or first main surface of the multilayer substrate, a wireless IC element is arranged to process a high-frequency signal. On a side of a lower or second main surface of the multilayer substrate, a first radiator is provided and is coupled to the wireless IC element via a feeding circuit including first interlayer conductors. On the side of the first main surface, a second radiator is provided and is coupled to the first radiator via second interlayer conductors.

Integrated circuit comprising an integrated transformer of the "balun" type with several input and output channels

An integrated circuit includes an integrated transformer of the balanced-to-unbalanced type with N channels, wherein N is greater than 2. The integrated transformer includes, on a substrate, N inductive circuits that are mutually inductively coupled, and respectively associated with N channels.

HIGH FREQUENCY CIRCUIT COMPRISING GRAPHENE AND METHOD OF OPERATING THE SAME

A high frequency circuit includes a first electronic device, a second electronic device, and a graphene interconnection unit, where at least one of a trench and a via is defined under the graphene interconnection unit. 1. A high frequency circuit comprising:a first electronic device;a second electronic device; anda graphene interconnection unit which connects the first and second electronic devices,wherein at least one of a trench and a via is defined under the graphene interconnection unit.2. The high frequency circuit of claim 1 , further comprising:an insulating layer disposed under the graphene interconnection unit,wherein the at least one of the trench and the via is defined in the insulating layer.3. The high frequency circuit of claim 1 , wherein the first electronic device sends an electrical signal to the second electronic device via the graphene interconnection unit in a high frequency field.4. The high frequency circuit of claim 1 , wherein the trench has a depth in the range of about 1 nanometer to about 10 claim 1 ,000 nanometers.5. The high frequency circuit of claim 1 , wherein the first electronic device sends an electrical signal via the graphene interconnection unit at a frequency of about 0.8 gigahertz or higher.6. The high frequency circuit of claim 1 , wherein the first electronic device sends an electrical signal via the graphene interconnection unit at a frequency in a range of about 2 gigahertz to about 300 terahertz.7. The high frequency circuit of claim 1 , wherein each of the first and second electronic devices comprise a transistor.8. The high frequency circuit of claim 1 , wherein the graphene interconnection unit comprises a plurality of graphene units aligned substantially parallel to each other.9. The high frequency circuit of claim 1 , wherein the graphene interconnection unit conveys a current at a frequency in a range of about 1 megahertz to about 800 mega hertz.10. The high frequency circuit of claim 1 , wherein the graphene ...

Backside integration of rf filters for rf front end modules and design structure

A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Devices and methods related to electrostatic discharge-protected cmos switches

Disclosed are devices and methods related to a CMOS switch for radio-frequency (RF) applications. In some embodiments, the switch can be configured to include a resistive body-floating circuit to provide improved power handling capability. The switch can further include an electrostatic discharge (ESD) protection circuit disposed relative to the switch to provide ESD protection for the switch. Such a switch can be implemented for different switching applications in wireless devices such as cell phones, including band-selection switching and transmit/receive switching.

Transmission line transition having vertical structure and single chip package using land grip array coupling

An apparatus for a single chip package using Land Grid Array (LGA) coupling is provided. The apparatus includes a multi-layer substrate, at least one integrated circuit chip, and a Printed Circuit Board (PCB). The a multi-layer substrate has at least one substrate layer, has at least one first chip region and at least one second chip region in a lowermost substrate layer, configures a transmission line transition of a vertical structure for transmitting a signal from at least one integrated circuit chip coupled in the first chip region in a coaxial shape or in a form of a Co-Planar Waveguide guide (CPW), and has an LGP coupling pad for connecting with a Printed Circuit Board (PCB) in the lowermost layer. The at least one integrated circuit chip is coupled in the first chip region and the second chip region. The PCB is connected with the multi-layer substrate using the LGA coupling via the LGA coupling pad.

Semiconductor package, and information processing apparatus and storage device including the semiconductor packages

According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer.

Package with printed filters

Aspects of the disclosure provide a circuit package. The circuit package includes a first signal terminal electrically coupled with a serializer/deserializer (SERDES), a second signal terminal electrically coupled with an external electronic component, and a trace disposed on an insulating layer. The trace is configured to transfer an electrical signal between the first signal terminal and the second signal terminal. The trace is patterned to provide a specific filtering characteristic to filter the electrical signal.

Electronic device

An electronic device comprising a laminate comprising pluralities of insulator layers each provided with conductor patterns, and an amplifier-constituting semiconductor device mounted to a mounting electrode formed on an upper surface of the laminate, a first ground electrode being formed on an insulator layer near an upper surface of the laminate; a second ground electrode being formed on an insulator layer near a lower surface of the laminate; the first ground electrode being connected to the mounting electrode through pluralities of via-holes; conductor patterns constituting the first circuit block being disposed in a region below the amplifier-constituting semiconductor device between the first ground electrode and the second ground electrode; and at least part of a conductor pattern for a line connecting the first circuit block to the amplifier-constituting semiconductor device being disposed on an insulator layer sandwiched by the mounting electrode and the first ground electrode.

HIGH FREQUENCY TRANSITION MATCHING IN AN ELECTRONIC PACKAGE FOR MILLIMETER WAVE SEMICONDUCTOR DIES

A mmWave electronics package constructed from common Printed Circuit Board (PCB) technology and a metal cover. Assembly of the package uses standard pick and place technology and heat is dissipated directly to a pad on the package. Input/output of mmWave signal(s) is achieved through a rectangular waveguide. Mounting of the electronic package to an electrical printed circuit board (PCB) is performed using conventional reflow soldering processes and includes a waveguide I/O connected to an mmWave antenna. The electronic package provides for transmission of low frequency, dc and ground signals from the semiconductor chip inside the package to the PCB it is mounted on. An impedance matching scheme matches the chip to high frequency board transition by altering the ground plane within the chip. A ground plane on the high frequency board encircles the high frequency signal bump to confine the electromagnetic fields to the bump region reducing radiation loss. 1. A high frequency chip to circuit board transition , comprising:a semiconductor chip comprising a ground plane, a first high frequency pad and a plurality of first ground pads;a high frequency circuit board constructed from a dielectric material, said high frequency circuit board comprising a ground plane, a second high frequency pad and a plurality of second ground pads;a high frequency bump electrically connecting said first high frequency pad and said second high frequency pad to convey a high frequency signal;a plurality of bumps operative to electrically connect said plurality of first ground pads with said plurality of second ground pads so as to connect the ground planes on said semiconductor chip and said high frequency circuit board; andwherein a portion of said ground plane of said semiconductor chip above said first high frequency pad is removed.2. The transition according to claim 1 , wherein removing said portion of said ground plane of said semiconductor chip above said first high frequency pad ...

Stacked module

A stacked module includes a first multilayer substrate including an opening having a stepwise wall face, and a first transmission line including a first grounding conductor layer, a second multilayer substrate supported on a stepped portion of the stepwise wall face and including a second transmission line including a second grounding conductor layer, a first chip mounted on a bottom of the opening and coupled to a third transmission line provided on the first multilayer substrate, and a second chip mounted on the front face of the second multilayer substrate and coupled to the second transmission line. A face to which the second grounding conductor layer or a fourth grounding conductor layer coupled thereto is exposed is joined to the stepped portion to which the first grounding conductor layer or a third grounding conductor layer coupled thereto is exposed, and the first and second grounding conductor layers are coupled.

Power recovery circuit based on partial standing waves

A power recovery system includes a transmission line that is coupled to transfer an RF signal received via an antenna. The RF signal generates a partial standing wave in the transmission line and the transmission line has at least one standing wave anti-node. A power recovery circuit converts an anti-node signal from the at least one standing wave anti-node to a power signal.

Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces

Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The semiconductor device of the invention includes a transistor, an insulating layer provided over the transistor, a first conductive layer (corresponding to a source wire or a drain wire) electrically connected to a source region or a drain region of the transistor through an opening portion provided in the insulating layer, a first resin layer provided over the insulating layer and the first conductive layer, a layer containing conductive particles which is electrically connected to the first conductive layer through an opening portion provided in the first resin layer, and a substrate provided with a second resin layer and a second conductive layer serving as an antenna. In the semiconductor device having the above-described structure, the second conductive layer is electrically connected to the first conductive layer with the layer containing conductive particles interposed therebetween. In addition, the second resin layer is provided over the first resin layer. 1. (canceled)2. A semiconductor device comprising:a transistor including a source region and a drain region;an insulating layer over the transistor;a first conductive layer directly connected to one of the source region and the drain region through a first opening portion in the insulating layer;a second conductive layer directly connected to the other of the source region and the drain region through a second opening portion in the insulating layer;a first resin layer over the insulating layer;a layer comprising a conductive particle directly connected to the first conductive layer in a third opening portion of the first resin layer; anda first substrate with a second resin layer and a third conductive layer,wherein the first conductive layer and the second conductive layer are in contact with the first resin layer,wherein the third conductive layer is electrically connected to the first conductive layer with the second resin layer and the layer comprising the conductive particle interposed therebetween ...

Process-compensated hbt power amplifier bias circuits and methods

The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

Miniature Passive Structures for ESD Protection and Input and Output Matching

A miniature passive structure for electrostatic discharge (ESD) protection and input/output (I/O) matching for a high frequency integrated circuit is provided. The miniature passive structure includes at least one shunt stub and at least one load line. The shunt stub(s) each provide a corresponding ESD discharge path. The load line(s) are coupled to the shunt stub(s) and provide loading effects for the shunt stub(s). 1. A miniature passive structure for electrostatic discharge (ESD) protection and input/output (I/O) matching for a high frequency integrated circuit , the structure comprising:at least one shunt stub for providing a corresponding at least one ESD discharge path; andat least one load line a first end open-ended and a second end connected to the ground coupled to the at least one shunt stub, the at least one load line providing loading effects for the at least one shunt stub.2. The miniature passive structure in accordance with further comprising an input signal trace claim 1 , wherein the at least one shunt stub is DC connected to the input signal trace at a first end and at least one of:DC connected to ground at a second end;AC coupled to one supply rail at a second end; orDC connected to one supply rail at a second end.3. (canceled)4. The miniature passive structure in accordance with wherein the at least one shunt stub comprises a structure selected from the group comprising a coplanar waveguide claim 1 , a coplanar waveguide with a ground shield claim 1 , a microstrip line claim 1 , and a strip line.5. The miniature passive structure in accordance with wherein the at least one load line comprises a structure selected from the group comprising a coplanar waveguide claim 1 , a plurality of coplanar waveguides claim 1 , a coplanar waveguide with a ground shield claim 1 , a plurality of coplanar waveguides with ground shields claim 1 , a microstrip line claim 1 , a plurality of microstrip lines claim 1 , a strip line claim 1 , and a plurality of strip ...

SEMICONDUCTOR PACKAGE, METHOD AND MOLD FOR PRODUCING SAME, INPUT AND OUTPUT TERMINALS OF SEMICONDUCTOR PACKAGE

A semiconductor package according to the present invention includes: a semiconductor element where a high frequency signal is input or output; a planar lead terminal having an end electrically connected to an input terminal or an output terminal of the semiconductor element; an encapsulation resin for encapsulating the lead terminal and the semiconductor element, the lead terminal having another end exposed from the resin; and a ground enhancing metal body encapsulated in the encapsulation resin, having a first main surface facing the lead terminal and a second main surface exposed from the encapsulation resin, wherein the ground enhancing metal body has a shape with a cross section parallel to the second main surface and having a smaller area than an area of the first main surface. 122-. (canceled)23. A semiconductor package comprising:a semiconductor element where a high frequency signal is input and/or output;a planar lead for transmitting the high frequency signal to the semiconductor element or an external circuit, the lead having an end electrically connected to an input terminal or an output terminal of the semiconductor element;a resin for encapsulating the lead and the semiconductor element, the lead having another end exposed from the resin; andan electric conductor for ground enhancement having a first main surface and a second main surface opposite to the first main surface, and encapsulated in the resin, the first main surface facing the lead with the resin therebetween, the second main surface being exposed from the resin,wherein the electric conductor has a shape with a cross section parallel to the second main surface and having a smaller area than an area of the first main surface.24. The semiconductor package according to claim 23 , further comprisinga planar die pad having a top surface on which the semiconductor element is disposed,wherein the die pad is encapsulated in the resin such that at least a portion of an undersurface of the die pad is ...

Noise attenuation wall

An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

Efficient Linear Integrated Power Amplifier Incorporating Low And High Power Operating Modes

A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

DE-POP ON-DEVICE DECOUPLING FOR BGA

Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads. 1. An electronic integrated circuit (EIC) package comprising:an EIC substrate;an array of ball grid array (BGA) pads on a first side of said EIC substrate, arranged in a grid pattern of rows and columns; andcontact pads on said first side of said EIC substrate to accommodate electrical connection of a surface-mount device, wherein said surface-mount device occupies a grid location of said grid pattern in place of one or more BGA pads.2. The EIC package of claim 1 , wherein said contact pads comprise at least two adjacent contact pads.3. The EIC package of claim 2 , wherein each of the contact pads is connected to an adjacent BGA pad by a conductor on said first side of said EIC substrate.4. The EIC package of claim 1 , wherein said surface-mount device comprises a two-port device.5. The EIC package of claim 4 , wherein said surface-mount device comprises a decoupling capacitor.6. The EIC package of claim 1 , wherein said surface-mount device is selected from a set of a capacitor claim 1 , a resistor claim 1 , an inductor claim 1 , a diode claim 1 , a transistor claim 1 , a capacitor array claim 1 , and a resistor-capacitor circuit.7. The EIC package of claim 1 , wherein said BGA grid comprises a pitch of between about 0.4 mm×0.4 mm and about 1.27 mm×1.27 mm.8. The EIC package of claim 7 , wherein said BGA grid comprises an irregular pitch.9. A computer-aided design tool for accommodating a surface-mount device on a first surface of a ball grid array (BGA) electronic integrated circuit (EIC) package claim 7 , said tool comprising:a design tool configured to identify, in an EIC configuration of BGA pads in a grid pattern on said first side of said EIC package, at least two contact pads for forming directly on said first ...

Semiconductor package having wire bond wall to reduce coupling

A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

INTERPOSER

The present disclosure relates to an interposer. The interposer includes: a support body formed of a ceramic material, a connection electrode configured to the top surface and bottom surface of the support body, and a shielding member disposed at an outer surface of the support body. At least a part of the support body is disposed along the edge of a substrate, and electrically connects the substrate and a substrate. The interposer is formed of a ceramic material and thus make it possible to implement a fine pattern, to improve dimensional stability by preventing the bending deformation of ceramic green sheets, and to raise the reliability of signal transmission. Therefore, the interposer can contribute to implementing high performance of an electronic device and reducing the size of the electronic device. 1. An interposer comprising:a support body including a top surface and a bottom surface, at least a part of the support body disposed along the edge of a substrate;a connection electrode configured to connect the top surface and bottom surface of the support body; anda shielding member disposed at an outer surface of the support body.2. The interposer of claim 1 , wherein the support body is disposed along the edge of the substrate claim 1 , as one part or a combination of two or more parts claim 1 , selected from a group including:a straight part disposed in a straight line shape along a part of the edge of the substrate;a inclined part disposed in an inclined shape so as to be adjacent to a part of the edge of the substrate or a corner of the substrate; anda curved part disposed in a round shape.3. The interposer of claim 1 , wherein the support body is formed of a ceramic material.4. The interposer of claim 1 , wherein the connection electrode is formed as a conductive material filled in a via hole formed through the support body in a thickness direction thereof to connect the top and bottom surfaces of the support body.5. The interposer of claim 4 , wherein ...

SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES

A semiconductor package includes a redistribution wiring layer having redistribution wirings, a semiconductor chip on the redistribution wiring layer, a frame on the redistribution wiring layer, the frame surrounding the semiconductor chip, and the frame having core connection wirings electrically connected to the redistribution wirings, and an antenna structure on the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another. 1. A semiconductor package , comprising:a redistribution wiring layer having redistribution wirings;a semiconductor chip on the redistribution wiring layer;a frame on the redistribution wiring layer, the frame surrounding the semiconductor chip, and the frame having core connection wirings electrically connected to the redistribution wirings; andan antenna structure on the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another.2. The semiconductor package as claimed in claim 1 , wherein the first antenna insulation layer has a first thermal expansion coefficient claim 1 , and the second antenna insulation layer has a second thermal expansion coefficient smaller than the first thermal expansion coefficient.31314. The semiconductor package as claimed in claim 2 , wherein the second thermal expansion coefficient is within a range of / to / of the first thermal expansion coefficient.4. The semiconductor package as claimed in claim 2 , wherein the second thermal expansion coefficient of the second antenna insulation layer is a same as a thermal expansion coefficient of the frame.5. The semiconductor package as claimed in claim 1 , wherein the first antenna insulation layer has a first thickness claim 1 , and the second ...

Packaging Methods of Semiconductor X-Ray Detectors

Disclosed herein is a method for making an apparatus suitable for detecting X-ray, the method comprising: bonding a plurality of chips to a substrate; wherein the substrate comprises an X-ray absorption layer comprising a first plurality of electrical contacts; wherein each of the plurality of chips comprises an electronic layer comprising a second plurality of electrical contacts and an electronic system configured to process or interpret signals generated by X-ray photons incident on the X-ray absorption layer; aligning the first plurality of electrical contacts to the second plurality of electrical contacts; mounting the chips to the substrate such that the first plurality of electrical contacts are electrically connected to the second plurality of electrical contacts; wherein the second plurality of electrical contacts are configured to feed the signals to the electronic system. 1. A method for making an apparatus suitable for detecting X-ray , the method comprising:bonding a plurality of chips to a substrate;wherein the substrate comprises an X-ray absorption layer comprising a first plurality of electrical contacts;wherein each of the plurality of chips comprises an electronic layer comprising a second plurality of electrical contacts and an electronic system configured to process or interpret signals generated by X-ray photons incident on the X-ray absorption layer;aligning the first plurality of electrical contacts to the second plurality of electrical contacts;mounting the chips to the substrate such that the first plurality of electrical contacts are electrically connected to the second plurality of electrical contacts;wherein the second plurality of electrical contacts are configured to feed the signals to the electronic system.2. The method of claim 1 , further comprising attaching the plurality of chips to a support wafer.3. The method of claim 2 , wherein the plurality of chips are attached to the support wafer with an adhesive.4. The method of claim 2 ...

Electronic apparatus operable in high frequencies

An electronic apparatus that includes a semiconductor device mounted on an assembly base is disclosed. The semiconductor device includes a transmission line, whose impedance is matched to characteristic impedance, and a pad connected to the transmission line, through which a high frequency signal is supplied to or extracted from the semiconductor device. The pad accompanies a stub line that is concurrently formed with the transmission line and grounded within the semiconductor device. The stub line operates as a short stub that may compensate parasitic capacitance attributed to the pad.

BIPOLAR TRANSISTOR HAVING COLLECTOR WITH DOPING SPIKE

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers. 1. A bipolar transistor comprising a collector including a first end and a second end opposite the first end , a sub-collector abutting the second end of the collector , a base abutting the first end of the collector , and an emitter , the collector including a doping spike disposed closer to the first end than to the second end , the doping spike having a thickness of 200 Å or less , the collector also including a doped portion disposed between the doping spike and the base , the bipolar transistor being a single heterojunction bipolar transistor.2. The bipolar transistor of wherein the doping spike extends substantially an entire length of the collector in a direction substantially parallel to a base-collector interface.3. The bipolar transistor of wherein the collector includes a second doped portion disposed between the doping spike and the subcollector claim 2 , the second doped portion comprising a substantially flat doping and extending substantially an entire length of the collector in a direction substantially parallel to a base-collector interface.4. The bipolar transistor of wherein the thickness of the doping spike is substantially equal to 150 Å.5. The bipolar transistor of wherein the thickness of the doping spike is substantially equal to 100 Å.6. The bipolar transistor of wherein the doping spike is disposed at a location that results in approximately a local maximum of BVof the bipolar transistor.7. The bipolar transistor of wherein the doping spike is disposed within about 0.5 μm from a base- ...

APPARATUS AND METHOD FOR PROVIDING A SCALABLE BALL GRID ARRAY (BGA) ASSIGNMENT AND A PCB CIRCUIT TRACE BREAKOUT PATTERN FOR RF CHIP INTERFACES

A pin map covers a surface area of a layer of a printed circuit board (PCB). The pin map includes a plurality of electrical designations for each pin in the pin map and a plurality of empty spaces within the pin map. Each electrical designation may be assigned to a pin on the pin map. Each electrical designation includes a positive polarity (P+) pin, a negative polarity (P−) pin, or an electrical ground (G) pin. If a space in the pin map does not have an electrical designation, then it may include an empty space/plain portion of the printed circuit board (PCB). The pin map may include a plurality of rows and a first repeating pin polarity pattern. The first repeating pin polarity pattern may include a lane unit tile. The pin map may help couple two circuit elements together that are attached to one layer of a PCB. 1. An apparatus , comprising:a first semiconductor die stacked vertically relative to a layer of a printed circuit board (PCB), the first semiconductor die coupled to the PCB with a ball grid array (BGA);a second semiconductor die stacked vertically relative to the layer of the PCB, the second semiconductor die coupled to the PCB with a BGA;a pin map corresponding to each BGA and covering a surface area of the PCB, the pin map comprising a plurality of electrical designations for each pin in the pin map and a plurality of empty spaces within the pin map; each electrical designation of the plurality of electrical designations on the pin map comprising one of a positive polarity (P+), a negative polarity (P−), or an electrical ground (G);each pin map including a first repeating pin polarity pattern; the first repeating pin polarity pattern comprising a lane unit tile, the lane unit tile having a central region defined by four pin map units, two of the four pin map units comprising two pins corresponding to a signal lane within the PCB.2. The apparatus of claim 1 , wherein the pin map comprises a plurality of square units wherein each square unit represents ...

SEMICONDUCTOR SWITCH

A semiconductor switch includes an insulating film on a semiconductor substrate. A switching circuit is on a first portion of the insulating film. The switching circuit is configured to switch a path of a high-frequency signal. A wiring layer is provided on the insulating film. The wiring layering includes a signal wire and a ground wire. A conductive layer is between the wiring layer and the insulating film. The conductive layer, in some embodiments, includes a first conductive region between the high-frequency wiring and the insulating film and a second conductive region between the grounding wiring and the insulating film. 1. A semiconductor switch , comprising:a semiconductor substrate;an insulating film on the semiconductor substrate;a conductive layer on the insulating film;a wiring layer comprising a first wire and a second wire above the conductive layer, the first wire carrying a high-frequency signal and the second wire connected to ground; anda switching circuit on a first portion of the insulating film, the switching circuit configured to switch a path of the high-frequency signal.2. The semiconductor switch according to claim 1 , wherein the insulating film comprises a buried oxide layer claim 1 , a shallow trench isolation layer claim 1 , and an interlayer dielectric layer.3. The semiconductor switch according to claim 2 , wherein the first portion of the insulating film includes only the buried oxide layer.4. The semiconductor switch according to claim 1 , wherein the conductive layer is connectable to a power supply potential such that an electrical potential of the conductive layer is higher than an electrical potential of the semiconductor substrate.5. The semiconductor switch according to claim 2 , whereinthe interlayer dielectric layer covers the conductive layer, anda first via in the interlayer dielectric layer contacts the conductive layer such that the conductive layer is connectable to the power supply potential through the first via.6. The ...

DEVICES AND METHODS RELATED TO HIGH POWER DIODE SWITCHES WITH LOW DC POWER CONSUMPTION

Devices and methods are disclosed, related to high power diode switches. In some embodiments, a radio-frequency switch circuit can include a first switchable path implemented between a pole and a first throw, the first switchable path including one or more PIN diodes, and a second switchable path implemented between the pole and a second throw, the second switchable path including one or more PIN diodes. The radio-frequency switch circuit can further include a switchable shunt path implemented between the second throw and a ground, the switchable shunt path including at least one shunt PIN diode and a capacitance between the second throw and the at least one shunt PIN diode. The pole can be an antenna port, and the first and second throws can be transmit and receive ports, respectively. 1. A radio-frequency switch circuit comprising:a first switchable path implemented between a pole and a first throw, the first switchable path including one or more PIN diodes;a second switchable path implemented between the pole and a second throw, the second switchable path including one or more PIN diodes; anda switchable shunt path implemented between the second throw and a ground, the switchable shunt path including at least one shunt PIN diode and a capacitance between the second throw and the at least one shunt PIN diode.2. The radio-frequency switch circuit of wherein the pole is an antenna port.3. The radio-frequency switch circuit of wherein the first throw is a transmit port configured to receive an amplified radio-frequency signal.4. The radio-frequency switch circuit of further comprising an additional switchable shunt path implemented between the transmit port and a ground.5. The radio-frequency switch circuit of wherein the additional switchable shunt path includes at least one shunt PIN diode.6. The radio-frequency switch circuit of further comprising a transmit bias port electrically connected to a node between the first throw and the one or more PIN diodes of the ...

HIGH-FREQUENCY MODULE AND METHOD FOR MANUFACTURING THE SAME

A high-frequency module includes an integrated body including a semiconductor chip and a reflector, the semiconductor and the reflector being integrated by a resin; an antenna provided with a space from the reflector; and a rewiring layer provided on the surface of the integrated body, the rewiring layer including a rewiring line electrically coupling the semiconductor chip to the antenna. Further, a method for manufacturing a high-frequency module, the method includes forming an integrated body by integrating a semiconductor chip with a reflector by a resin; and forming a rewiring layer on the surface of the integrated body, the rewiring layer including a rewiring line electrically coupling the semiconductor chip to an antenna provided with a space from the reflector. 1. A high-frequency module comprising:an integrated body including a semiconductor chip and a reflector, the semiconductor and the reflector being integrated by a resin;an antenna provided with a space from the reflector; anda rewiring layer provided on the surface of the integrated body, the rewiring layer including a rewiring line electrically coupling the semiconductor chip to the antenna.2. The high-frequency module according to claim 1 , whereinthe integrated body includes a distance adjuster configured to adjust a distance between the reflector and the antenna.3. The high-frequency module according to claim 2 , whereinthe distance adjuster is a dielectric layer provided on the antenna side of the reflector.4. The high-frequency module according to claim 1 , whereinthe integrated body includes a dielectric layer that comes into contact with the antenna side of the reflector, the dielectric layer including a surface exposed on the surface of the integrated body.5. The high-frequency module according to claim 3 , whereinthe antenna is provided on the surface of the dielectric layer.6. The high-frequency module according to claim 2 , whereinthe distance adjuster is a protrusion part configured to ...

SHIELDED PACKAGE WITH INTEGRATED ANTENNA

A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant. 1. A semiconductor structure , comprising: at least one device,', 'a conductive pillar, and', 'an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface of the encapsulant to a second major surface of the encapsulant, opposite the first major surface, and is exposed at the second major surface of the encapsulant and the at least one device is exposed at the first major surface of the encapsulant,', 'a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant, and', 'an isolation region configured to electrically isolate that the conductive shield layer from the conductive pillar; and, 'a packaged semiconductor device havinga radio-frequency (RF) connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.2. The semiconductor structure of claim 1 , wherein the packaged semiconductor device comprises at least one ...

METHODS FOR FORMING SHIELDED RADIO-FREQUENCY MODULES HAVING REDUCED AREA

Shielded radio-frequency (RF) module having reduced area. In some embodiments, a method for fabricating a radio-frequency module includes forming or providing a packaging substrate configured to receive a plurality of components. The method may include mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices. In some embodiments, the method further includes forming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond. 1. A method for fabricating a radio-frequency module , the method comprising:forming or providing a packaging substrate configured to receive a plurality of components;mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices; andforming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond.2. The method of further comprising forming each of the shielding wirebonds to have a loop shape ...

RLINK - ON-DIE INDUCTOR STRUCTURES TO IMPROVE SIGNALING

Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling. 1. An integrated circuit (IC) chip comprising:a data signal circuit disposed on a horizontal inner layer within the chip and having a data signal output contact;a data signal surface contact disposed on a horizontal surface of the chip;a first data signal inductor having (1) a second end electrically coupled to a capacitance value of an electrostatic discharge (ESD) circuit and to the electrostatic discharge (ESD) circuit, and (2) a first end electrically coupled to a capacitance value at the data signal surface contact and to the data signal surface contact; anda second data signal inductor having (1) a second end electrically coupled to the data signal output contact of the data signal circuit, and to a capacitance value of the data signal circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit, wherein loops of the first data signal inductor are disposed within a last silicon metal level LSML and a LSML-1 level of the chip, and wherein loops of the second data signal inductor ...

Integrated Tunable Filter Architecture

An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated. 2. The integrated circuit configuration of claim 1 , wherein at least one tunable filter includes at least one of a tunable notch filter or a tunable bandpass filter.3. The integrated circuit configuration of claim 2 , wherein the tunable notch filter or tunable bandpass filter includes a tunable RLC filter.4. The integrated circuit configuration of claim 3 , wherein the tunable RLC filter includes at least one of a tunable capacitor C and a tunable inductor L.5. The integrated circuit configuration of claim 4 , wherein at least one of the tunable capacitor C or tunable inductor L is digitally tunable.6. The integrated circuit configuration of claim 1 , wherein at least one tunable filter includes at least one of a tunable low pass filter or a tunable high pass filter.7. The integrated circuit configuration of claim 6 , wherein the tunable low pass filter or tunable high pass filter includes a tunable RLC filter.8. The integrated circuit configuration of claim 7 , wherein the tunable RLC filter includes at least one of a tunable capacitor C and a tunable inductor L.9. The integrated circuit configuration of claim 8 , wherein at least one of the tunable capacitor C or tunable inductor L is digitally tunable.10. The integrated circuit configuration of claim 1 , wherein the frequency based circuit is at least one of a radio frequency switch claim ...

SEMICONDUCTOR DEVICE

In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of drain electrodes, each of the drain electrodes being disposed along one direction on the semiconductor substrate;a plurality of source electrodes, each of the source electrodes being disposed in an area between corresponding adjacent two of the drain electrodes on the semiconductor substrate, and being disposed along the one direction;a feed line being disposed on the semiconductor substrate, and having a band shape extending in the one direction; an input line disposed on the semiconductor substrate;', 'an air bridge connecting the feed line and the input line;, 'a plurality of gate fingers, each of the gate fingers having a linear shape extending from the feed line, and being disposed in an area between two adjacent electrodes on the semiconductor substrate, one of the two adjacent electrodes being a corresponding one of the drain electrodes and the other being a corresponding one of the source electrodes; and'}a plurality of open stubs being disposed on the semiconductor substrate, and having a line length that eliminates a target higher harmonic wave, and each of the open stubs passing under the air bridge and being connected directly to the feed line.2. The semiconductor device according to claim 1 , wherein the open stubs are arranged so as to correspond one-to-one to the gate fingers.3. The semiconductor device according to claim 1 , wherein the open stubs are made from a metallic material identical to that of the gate fingers.4. A semiconductor device comprising:a semiconductor substrate;a plurality of drain electrodes, each of the drain electrodes being disposed along one direction on the semiconductor substrate;a plurality of source electrodes, each of the ...

Inductor module

An inductor module includes an insulating flexible substrate including a thermoplastic resin, an IC element included in the flexible substrate, chip capacitors included in the flexible substrate, a chip inductor that includes a magnetic-material body and is located on a first main surface of the flexible substrate, and input and output terminals on a second main surface of the flexible substrate. The IC element may be a switching IC element, the chip inductor may be a choke coil, and the inductor module may be a DC/DC converter module.

RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME

The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between. 1. An apparatus comprising: the BEOL portion comprises a plurality of connecting layers;', 'the FEOL portion comprises an active layer, a contact layer, and isolation sections;', 'the active layer and the isolation sections reside over the contact layer, and the isolation sections surround the active layer;', 'the active layer does not extend vertically beyond the isolation sections;, 'a device region including a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion residing over the BEOL portion, whereina plurality of first bump structures formed at a bottom surface of the BEOL portion, wherein the plurality of first bump structures is electrically coupled to the FEOL portion via the plurality of connecting layers;a first mold compound formed over the bottom surface of the BEOL portion and partially encapsulating each of the plurality of first bump structures, wherein a bottom portion of each of the plurality of first bump structures is not covered by the first mold compound; anda second mold compound residing over ...

MICROELECTRONIC ASSEMBLIES HAVING INTERPOSERS

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a high bandwidth interconnect, a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect, and a second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect. 1. A microelectronic assembly , comprising:a package substrate having a high bandwidth interconnect;a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect; anda second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect.2. The microelectronic assembly of claim 1 , wherein the high bandwidth interconnect is a waveguide.3. The microelectronic assembly of claim 1 , wherein the high bandwidth circuitry of the first interposer is radio frequency (RF) circuitry.4. The microelectronic assembly of claim 1 , further comprising:a first die having a first surface and an opposing second surface, wherein the first surface of the first die is electrically coupled to a surface of the package substrate and the second surface of the first die is electrically coupled to the first interposer; anda second die having a first surface and an ...

EMI Shielding Structure in InFO Package

A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die. 1. A device comprising:a device die;an encapsulating material;a shielding structure encapsulated in the encapsulating material, wherein the device die is in the shielding structure;a through-via penetrating through the encapsulating material; andan antenna having at least a portion overlapping the shielding structure, wherein the antenna is electrically connected to the device die through the through-via.2. The device of claim 1 , wherein the shielding structure comprises:a conductive cap over the device die; anda side-shielding structure underlying and connected to the conductive cap, wherein the side-shielding structure forms a ring encircling the device die.3. The device of claim 2 , wherein the device die and the shielding structure are both encapsulated in the encapsulating material claim 2 , and edges of the conductive cap are in contact with the encapsulating material to form interfaces.4. The device of further comprising a die-attach film claim 2 , wherein the device die is attached to a surface of the conductive cap through the die-attach film.5. The device of claim 2 , wherein the conductive cap and the side-shielding structure have distinguishable interfaces in between.6. The device of claim 1 , wherein the shielding structure is an integrated unit formed of a homogeneous material.7. The device of claim 1 , wherein the shielding structure comprises a conductive paste.8. A device comprising:a molding compound; a top portion; and', 'a first ...

INDUCTOR AND TRANSMISSION LINE WITH AIR GAP

An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines. 1. An integrated circuit structure , comprising:one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm; andan air gap in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.2. The integrated circuit structure of claim 1 , wherein the width of the air gap and a distance between the first and second conductive lines is approximately 1 to 10 μm.3. The integrated circuit structure of claim 1 , wherein the air gap includes one or more spacers along at least one top corner of the air gap and at least one sidewall of the first and second conductive lines.4. The integrated circuit structure of claim 3 , wherein the one or more spacers leave an opening in the air gap of approximately 100-300 nm.5. The integrated circuit structure of claim 3 , wherein the air gap includes left and right spacers formed along the sidewalls of the first and second conductive lines claim 3 , respectively claim 3 , where the left and right spacers are coplanar with a top surface of the first and second conductive lines.6. The integrated circuit structure of claim 1 , wherein the air gap is formed as a continuous recess between the first and second conductive lines.7. The integrated circuit structure of claim 1 , wherein the air gap is formed as non-contiguous air gap segments that are spaced apart by the ILD to provide structural support to the sidewalls of the first and second conductive lines.8. ...

SYSTEMS AND METHODS USING AN RF CIRCUIT ON ISOLATING MATERIAL

A device is disclosed that includes a wafer/chip, a first layer, a first device, an isolation mold and a second device. The first layer is formed over the chip and has non-isolating characteristics. The first device is formed over the first layer. In one example, it is formed only over the first layer. The isolation mold is formed over the chip. The isolation mold has isolating characteristics. The second device is formed substantially over the isolation mold. 1. A fabricating system to enhance radio frequency (RF) signals comprising:a process tool configured to perform fabrication processes on a semiconductor device; anda control unit configured control the process tool and to identify target areas of the device having high frequency components, remove underlying substrate material of the target areas and form a plurality of isolation molds only within the target areas.2. The system of claim 1 , wherein the high frequency components include radio frequency (RF) circuitry that generates RF signals.3. The system of claim 2 , wherein the isolation molds include an encapsulation material.4. The system of claim 2 , wherein the control unit is configured to form coupling regions within the identified target areas prior to forming the plurality of isolation molds.5. The system of claim 1 , wherein the high frequency components are predetermined.6. The system of claim 1 , wherein the control unit is configured to analyze a plurality of components of the device for generation of high frequency signals to identify the high frequency components.7. A method for fabricating a device that enhance radio frequency (RF) signal integrity claim 1 , the method comprising:determining one or more high frequency components from a plurality of components for a device;identifying one or more target areas that include the one or more high frequency components;removing at least coupling regions of the device within the one or more target areas; andforming one or more isolation molds within ...

Integrated circuit structure having gate contact and method of forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.

GUARD BOND WIRES IN AN INTEGRATED CIRCUIT PACKAGE

An integrated circuit package is provided. The integrated circuit package comprises a first and second guard bond wire. The first guard bond wire has a first and second end coupled to ground. The second guard bond wire has a first and second end coupled to ground. The integrated circuit package further comprises a die. The die is mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die. 1. An integrated circuit package , comprising:a first guard bond wire having a first and second end coupled to ground;a second guard bond wire having a first and second end coupled to ground;a die mounted between the first and second guard bond wires such that the first and second guard bond wires distort a magnetic field between at least an input terminal and an output terminal of the die, wherein the die has a surface area with a first side and a second side that is opposite to the first side and at least a portion of the first guard bond wire is aligned with the first side of the die and at least a portion of the second guard bond wire is aligned with the second side of the die; anda flange on which the die is mounted;wherein the at least a portion of the first guard bond wire is aligned with the first side such that the at least a portion of the first bond wire runs parallel to the first side of the die, and wherein the at least a portion of the second guard bond wire is aligned with the second side such that the at least a portion of the second guard bond wire runs parallel to the second side of the die,wherein the first and/or second end of the first guard bond wire is/are coupled to ground through a flange mounted first and/or second capacitor, respectively, and the first and/or second end of the second guard bond wire is/are coupled to ground through a flange mounted third and/or fourth capacitor, respectively.215-. (canceled)16. The ...

HIGH-POWER AMPLIFIER PACKAGE

Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may have cut-outs that allow high-power components to be mounted directly on a heat slug below the laminate. Electrical connections to circuitry on the laminate may be made with wire bonds. The packaging allows more flexible design and tuning of packaged microwave circuitry. 1. A high-power amplifier circuit assembled in a package comprising:a microwave circuit formed on a laminate;a case supporting conductive leads that are connected to the microwave circuit;a heat slug connected to the case and extending from an interior region of the case to an exterior region of the case;a cut-out in the laminate; anda first power transistor mounted directly on the heat slug within the cut-out of the laminate and connected to the microwave circuit.2. The high-power amplifier circuit of claim 1 , wherein the first power transistor is capable of outputting power levels between 50 W and 100 W at duty cycles greater than 50% without significant degradation of the amplifier's performance.3. The high-power amplifier circuit of claim 1 , wherein the first power transistor is capable of outputting power levels between 100 W and 200 W at duty cycles greater than 50% without significant degradation of the amplifier's performance.4. The high-power amplifier circuit of claim 3 , wherein the first power transistor comprises GaN.5. The high-power amplifier circuit of claim 4 , further comprising a second power transistor mounted directly on the heat slug in a second cut-out in the laminate and having an output connected to an input of the first power transistor.6. The high-power amplifier circuit of claim 4 , further comprising a second power transistor mounted directly on the heat slug in a second cut-out in the laminate and connected in parallel with the first power transistor in a Doherty configuration.7. The high-power amplifier ...

Platform with thermally stable wireless interconnects

Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.

TRANSITION FREQUENCY MULTIPLIER SEMICONDUCTOR DEVICE

A transition frequency multiplier semiconductor device having a first source region, a second source region, and a common drain region is disclosed. A first channel region is located between the first source region and the common drain region, and a second channel region is located between the second source region and the common drain region. A first gate region is located within the first channel region to control current flow between the first source region and the common drain region, while a second gate region is located within the second channel region to control current flow between the second source region and the common drain region. An inactive channel region is located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region. 1. A transition frequency multiplier semiconductor device comprising:a first source region;a second source region;a common drain region;a first channel region located between the first source region and the common drain region;a second channel region located between the second source region and the common drain region;a first gate region located within the first channel region to control current flow between the first source region and the common drain region;a second gate region located within the second channel region to control current flow between the second source region and the common drain region; andan inactive channel region located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region.2. The transition frequency multiplier semiconductor device of further including an interconnect capacitor coupled between the first gate region and the second gate region.3. The transition frequency multiplier semiconductor device of further including an interconnect capacitor coupled between the first source region and the second gate region.4. The ...

FLIP CHIP CIRCUIT

A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate. 1. A flip chip circuit comprising:a semiconductor substrate;a power amplifier provided on the semiconductor substrate;a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry;wherein at least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.2. The flip chip circuit of claim 1 , further comprising a metal stack positioned between the metal pad and the power amplifier claim 1 , wherein the metal stack comprises a plurality of metal layers configured to provide a thermal bridge between the power amplifier and the metal pad.3. The flip chip circuit of claim 1 , further comprising an electrically conductive bump coupled to the metal pad claim 1 , wherein the electrically conductive bump comprises a metal pillar that extends away from the metal pad and the semiconductor substrate.4. The flip chip circuit of claim 1 , further comprising an insulating layer having an aperture claim 1 , wherein the metal pad is coupled to the electrically conductive bump through the aperture claim 1 , and wherein the electrically conductive bump extends across at least a portion of the insulating layer.5. The flip chip circuit of claim 1 , wherein the power amplifier comprises a plurality of power transistors distributed across the semiconductor substrate.6. The flip chip circuit of claim 1 , comprising:a plurality of power amplifiers provided on the semiconductor substrate;a plurality of metal pads, each configured to receive an electrically conductive bump for connecting the flip chip to external circuitry;wherein at ...

IMPEDANCE MATCHING CIRCUIT FOR RADIO-FREQUENCY AMPLIFIER

Impedance matching circuit for radio-frequency amplifier. In some embodiments, an impedance matching circuit can include a primary metal trace having a first end configured to be capable of being coupled to a voltage source for the power amplifier, and a second end configured to be capable of being coupled to an output of the power amplifier. The impedance matching circuit can further include a secondary metal trace having first end coupled to the second end of the primary metal trace, and a second end configured to be capable of being coupled to an output node. The impedance matching circuit can further include a capacitance implemented between the first and second ends of the secondary metal trace, and be configured to trap a harmonic associated with an amplified signal at the output of the power amplifier. 1. An impedance matching circuit for a power amplifier , comprising:a primary metal trace having a first end configured to be capable of being coupled to a voltage source for the power amplifier, and a second end configured to be capable of being coupled to an output of the power amplifier;a secondary metal trace having a first end coupled to the second end of the primary metal trace, and a second end configured to be capable of being coupled to an output node; anda capacitance implemented between the first and second ends of the secondary metal trace, the capacitance configured to trap a harmonic associated with an amplified signal at the output of the power amplifier.2. The impedance matching circuit of further comprising a harmonic trap circuit implemented between the output of the power amplifier and a ground.3. The impedance matching circuit of wherein the harmonic trap circuit includes a series combination of a capacitance and an inductance.4. The impedance matching circuit of wherein the capacitance and the inductance of the harmonic trap are configured to trap a second harmonic associated with the amplified signal.5. The impedance matching circuit of ...

SHIELDED INTERCONNECTS

Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines. 1. A quantum computing (QC) assembly , comprising:a quantum processing die;a control die; anda flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines, and the shield structure includes a plurality of air gaps.2. The QC assembly of claim 1 , wherein the flexible interconnect includes a flexible portion having a first end and an opposing second end claim 1 , a first rigid connection portion at the first end claim 1 , and a second rigid connection portion at the second end.3. The QC assembly of claim 2 , further comprising:a circuit component;wherein the quantum processing die and the first rigid connection portion are coupled to the circuit component, and the circuit component includes electrical pathways to electrically couple the quantum processing die and the first rigid connection portion.4. The QC assembly of claim 1 , wherein the plurality of transmission lines have a longitudinal portion and at least one transverse portion.5. The QC assembly of claim 4 , wherein a pitch of the plurality of transmission lines in the longitudinal portion is less than a pitch of the plurality of transmission lines in the transverse portion.6. The QC assembly of claim 4 , wherein the shield structure includes a plurality of rectangular sleeves in the longitudinal portion ...

Method and Apparatus for Integrated Shielded Circulator

An RF circulator in combination with a RF integrated circuit, the RF integrated circuit having a plurality of RF waveguide or waveguide-like structures in or on the RF integrated circuit, the RF circulator comprising a disk of ferrite material disposed on a metallic material disposed on or in the RF integrated circuit, the disk of ferrite material extending away from the RF integrated circuit when disposed thereon, the metallic portion having a plurality of apertures therein adjacent the disk of ferrite material which, in use, are in electromagnetic communication with the disk of ferrite material and with the plurality of RF waveguide or waveguide-like structures, the disk of ferrite material being disposed in a metallic cavity.

STACKED MEMORY PACKAGE INCORPORATING MILLIMETER WAVE ANTENNA IN DIE STACK

A stacked semiconductor device assembly may include a first semiconductor device having a first substrate and a first set of vias through the first substrate. The first set of vias may define a first portion of an antenna structure. The stacked semiconductor device assembly may further include a second semiconductor device having a second substrate and a second set of vias through the second substrate. The second set of vias may define a second portion of the antenna structure. The stacked semiconductor device assembly may also include a stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna. 1. A stacked semiconductor device assembly comprising:a first semiconductor device having a first substrate and a first set of vias through the first substrate, the first set of vias defining a first portion of an antenna structure;a second semiconductor device having a second substrate and a second set of vias through the second substrate, the second set of vias defining a second portion of the antenna structure; anda stack interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.2. The assembly of claim 1 , further comprising:one or more additional semiconductor devices, each having an additional substrate and an additional set of vias through the additional substrate, the additional set of vias defining an additional portion of the antenna structure; andone or more additional interconnect structures electrically coupling the additional portion of the antenna structure of each of the additional semiconductor devices to the first portion of the antenna structure and the second portion of the antenna structure.3. The assembly of claim 1 , wherein the first semiconductor device and the second semiconductor device are incorporated into a stacked three-dimensional integrated circuit claim 1 , and wherein the antenna structure ...

Power amplifier circuit

A power amplifier circuit includes a first amplifier transistor and a bias circuit. The first amplifier transistor amplifies a first signal and outputs a second signal. The bias circuit supplies a bias voltage or a bias current to the first amplifier transistor. The first amplifier transistor includes plural unit transistors disposed in a substantially rectangular region. The bias circuit includes first and second bias transistors and first and second voltage supply circuits. The first and second bias transistors respectively supply first and second bias voltages or first and second bias currents to the bases of unit transistors of first and second groups. The first and second voltage supply circuits respectively supply first and second voltages to the bases of the first and second bias transistors. The first and second voltages are decreased in accordance with a temperature increase. The second voltage supply circuit is disposed within the substantially rectangular region.

Voltage controlled oscillator circuit, device, and method

A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a first reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a cross-coupled pair of transistors. The cross-coupled pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.

RADIO FREQUENCY FILTER AND RADIO FREQUENCY MODULE

A radio frequency filter includes a first conductive pattern; a second conductive pattern connected to a first point of the first conductive pattern and extended; a third conductive pattern connected to a second point of the first conductive pattern and extended to surround a portion of the second conductive pattern; a fourth conductive pattern; a fifth conductive pattern connected to a third point of the fourth conductive pattern and extended; and a sixth conductive pattern connected to a fourth point of the fourth conductive pattern and extended to surround a portion of the fifth conductive pattern. The first conductive pattern extends toward the fourth conductive pattern and the fourth conductive pattern extends toward the first conductive pattern. A distance between the first conductive pattern and the fourth conductive pattern is greater than or equal to a distance between the third conductive pattern and the sixth conductive pattern. 1. A radio frequency filter comprising:a first conductive pattern extended from a first port and comprising a first point and a second point;a second conductive pattern connected to the first point of the first conductive pattern and extended from the first point;a third conductive pattern connected to the second point of the first conductive pattern and extended to surround at least a portion of the second conductive pattern;a fourth conductive pattern extended from a second port and comprising a third point and a fourth point;a fifth conductive pattern connected to the third point of the fourth conductive pattern and extended from the third point; anda sixth conductive pattern connected to the fourth point of the fourth conductive pattern and extended to surround at least a portion of the fifth conductive pattern,wherein the first conductive pattern extends toward the fourth conductive pattern from the first point and the fourth conductive pattern extends toward the first conductive pattern from the third point, anda separation ...

PROCESS-INVARIANT DELAY CELL

An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip. 1. An integrated circuit (IC) device comprising:a first resistive strip having an input terminal and an output terminal;a second resistive strip having a terminal coupled to a voltage, the second resistive strip being coplanar with the first resistive strip; anda capacitor formed by the first resistive strip and the second resistive strip.2. The IC device of claim 1 , wherein the first resistive strip and the second resistive strip comprise polysilicon.3. The IC device of claim 1 , wherein the second resistive strip includes portions substantially parallel to the first resistive strip.4. The IC device of claim 1 , wherein the first resistive strip is interdigitated with the second resistive strip.5. The IC device of claim 1 , wherein the first resistive strip and the second resistive strip are configured to be part of a delay cell or a filter.6. The IC device of claim 1 , wherein the first resistive strip and the second resistive strip are serpentine claim 1 , spiral claim 1 , octagonal claim 1 , and/or circular in shape.7. The IC device of claim 1 , wherein the first resistive strip comprises a first resistive material and the second resistive strip comprises a second resistive material that is different from the first resistive material.8. The IC device of claim 1 , wherein a width of the first resistive strip is substantially equal to a gap between the first resistive strip and the second resistive strip.9. The IC device of claim 8 , wherein the width of the first resistive strip is correlated to the gap between the first resistive strip and the second resistive strip such ...

Body-Source-Tied Semiconductor-On-Insulator (SOI) Transistor

A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers. 1: A semiconductor-on-insulator (SOI) transistor comprising:a semiconductor layer situated over a buried oxide layer, said buried oxide layer being situated over a substrate;said SOI transistor situated in said semiconductor layer and including a transistor body, gate fingers, source regions, and drain regions;said transistor body having a first conductivity type, said source regions and said drain regions having a second conductivity type opposite to said first conductivity type;a heavily-doped body-implant region having said first conductivity type overlapping at least one of said source regions;a common silicided region electrically tying said heavily-doped body-implant region to said at least one of said source regions.2: The SOI transistor of claim 1 , wherein said heavily-doped body-implant region is situated partially outside said source regions and near gate contacts.3: The SOI transistor of claim 2 , wherein at least one of said gate fingers comprises a stub adjacent to said heavily-doped body-implant region.4: The SOI ...

IMPEDANCE ELEMENT WITH BUILT-IN ODD-MODE OSCILLATION SUPPRESSION

A transistor package for a power amplifier is provided. The transistor package includes a plurality of radio frequency, RF, paths that includes a first RF path and second RF path. Each RF path includes a transistor-carrying die and at least one impedance element. The transistor package includes a circuit portion electrically coupling a first impedance element in the first RF path to a second impedance element in the second RF path where the circuit portion includes at least one resistor. 1. A transistor package for a power amplifier , the transistor package comprising: a transistor-carrying die; and', 'at least one impedance element; and', 'a circuit portion electrically coupling a first impedance element in the first RF path to a second impedance element in the second RF path, the circuit portion including at least one resistor., 'a plurality of radio frequency, RF, paths including a first RF path and second RF path, each RF path including2. The transistor package of claim 1 , wherein the at least one resistor is configured to suppress odd mode signal components associated with the first and second RF paths.3. The transistor package of claim 1 , wherein the at least one resistor includes at least a first resistor and a second resistor claim 1 , the first resistor being electrically coupled to the first impedance element claim 1 , the second resistor being electrically coupled to the second impedance element claim 1 , and the first and second resistors being electrically coupled to each other.4. The transistor package of claim 1 , wherein the at least one resistor includes at least a first resistor and a second resistor claim 1 , the first resistor being integrated with the first impedance element claim 1 , the second resistor being integrated with the second impedance element claim 1 , and the first and second resistors being electrically coupled to each other.5. The transistor package of claim 1 , wherein the circuit portion includes at least one of:at least one ...

MULTILAYER SUBSTRATE

A first land and a first ground pattern generate a first parasitic capacitance CLAND by capacitive coupling with a first insulating layer interposed therebetween. Then, the first parasitic capacitance CLAND is defined as a predetermined capacitance that suppresses an impedance of a via part from changing due to a change in an inductance component of the via part with respect to a first transmission line. As a result, it is possible to match the impedance of the via part with a impedance of the first transmission line by adjusting the first parasitic capacitance CLAND caused by the first land and the first ground pattern. Therefore, it is possible to prevent the transmission characteristics of the multilayer substrate from deteriorating without requiring the disposition of cavities such as through holes in the multilayer substrate. 17.-. (canceled)8. A multilayer substrate having a plurality of conductor layers laminated in a thickness direction , the multilayer substrate comprising:a first line including layer having a first transmission line for transmitting a signal and a first land to which the first transmission line is connected;a second line including layer having a second transmission line for transmitting the signal and a second land to which the second transmission line is connected;an adjacent insulating layer adjacent to one side in the thickness direction with respect to the first line including layer;a first ground including layer laminated with the adjacent insulating layer interposed therebetween with respect to the first line including layer and having a first ground pattern extending in a planar shape;a signal via disposed between the first land and the second land and connecting the first land and the second land;another insulating layer different from the adjacent insulating layer, anda second ground including layer formed as a layer different from the ground including layer as a first ground including layer among the plurality of conductor layers ...

HIGH-FREQUENCY POWER TRANSISTOR AND HIGH-FREQUENCY POWER AMPLIFIER

A high-frequency power transistor comprises a transistor, at least one capacitor and a housing, which at least partially encloses the transistor and the capacitor. A first port for a high-frequency input and a gate DC voltage supply are connected to a gate contact of the transistor. A second port is connected to a drain contact of the transistor for a high-frequency output and drain DC voltage supply. A third port and fourth port are connected to a source contact of the transistor. All ports lead out of the same housing. The third port is connected via the capacitor to the source contact, and the fourth port is connected via at least one inductive element to the source contact, so that the third port provides a high-frequency ground, and the fourth port provides a floating low-frequency ground and source DC voltage supply. 1. A high-frequency power transistor comprising:a transistor,at least one capacitor,a housing, which at least partially encloses the transistor and the capacitor,wherein a first port for a high-frequency input and a gate DC voltage supply are connected to a gate contact of the transistor,a second port is connected to a drain contact of the transistor for a high-frequency output and drain DC voltage supply, andwherein a third port and a fourth port are connected to a source contact of the transistor, andwherein the first, second, third and fourth port all lead out of the housing, andwherein the third port is connected via the capacitor to the source contact, and the fourth port is connected via at least one inductive element to the source contact, so that the third port provides a high-frequency ground, and the fourth port provides a floating low-frequency ground and source DC voltage supply, whereinthe inductive element comprises a bond wire or several bond wires connected in parallel.2. (canceled)3. The high-frequency power transistor according to claim 1 , wherein the capacitor is a one-layer capacitor.4. The high-frequency power transistor ...

SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND METHOD OF OPERATING SEMICONDUCTOR DEVICE

A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate. 1. A semiconductor device comprising:a substrate;a circuit element disposed on a first surface side of the substrate;a first transmission line that is disposed on the first surface side of the substrate and has one end coupled to the circuit element;a first terminal that is disposed on the first surface side of the substrate and coupled to the other end of the first transmission line and into which a first direct current voltage and a first alternating current signal for examination or a second direct current voltage for operation are input;a first dielectric that is disposed in a part of the first transmission line on a side opposite to the substrate;a second terminal that is disposed on a side of the first dielectric opposite to the first transmission line so as not to protrude from the first transmission line in a plan view and into which a second alternating current signal for operation is input;a second transmission line that is disposed on the first surface side of the substrate and has one end coupled to the circuit element;a third terminal that is disposed on the first surface side of the substrate and ...

CORE FOR HIGH-FREQUENCY TRANSFORMER, AND MANUFACTURING METHOD THEREFOR

This core for a high-frequency transformer has shape formed by a single roll process by winding a Fe-based nanocrystal alloy thin strip that has a roll contact surface and a free surface while interposing an insulating layer, characterized in that projections having a crater-form depression are dispersed on the free surface of the Fe-based nanocrystal alloy thin strip, and the apexes of the projections are ground and blunted. 1. A core for a high-frequency transformer , having a shape formed by winding an Fe-based nanocrystalline alloy ribbon by a single-roll process with an insulating layer interposed , the Fe-based nanocrystalline alloy ribbon having a roll contact surface and a free surface , whereinthe free surface of the Fe-based nanocrystalline alloy ribbon has dispersed thereon crater-like projections with a concave, and the projections each have a top part that is ground and blunted.2. The core for a high-frequency transformer according to claim 1 , wherein the Fe-based nanocrystalline alloy ribbon has a thickness of 10 to 15 μm.3. A method for manufacturing the core for a high-frequency transformer according to claim 1 , comprising:(1) a step of producing an Fe-based amorphous alloy ribbon for an Fe-based nanocrystalline alloy ribbon by a single-roll process;(2) a step of bring a free surface of the Fe-based amorphous alloy ribbon into contact with a rotating peripheral surface of a cylindrical grindstone, thereby pressure-grinding and blunting top parts of crater-like projections with a concave dispersed on the free surface;(3) a step of forming an insulating layer on the free surface and/or roll contact surface of the Fe-based amorphous alloy ribbon;(4) a step of winding the Fe-based amorphous alloy ribbon having the insulating layer formed thereon; and(5) a step of heat-treating the wound Fe-based amorphous alloy ribbon to cause nanocrystallization, thereby giving an Fe-based nanocrystalline alloy ribbon.4. The core for a high-frequency transformer ...

GRAPHENE LAYER TRANSFER

A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene. 1. A method of transferring a graphene layer from one substrate to another substrate , said method comprising:providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate;removing said copper foil exposing a surface of said layer of graphene;forming an oxide bonding enhancement dielectric layer on said exposed surface of said layer of graphene;providing a second layered structure including a receiver substrate and a dielectric oxide layer;bonding an exposed surface of said dielectric oxide layer of said second layered structure to an exposed surface of said oxide bonding enhancement dielectric layer; andremoving said carrier substrate and said adhesive layer exposing said layer of graphene.2. The method of claim 1 , wherein said providing said first layered structure includes:forming said layer of graphene on an exposed surface of said copper foil; andbonding a structure including said adhesive layer and said carrier substrate to an exposed surface of said layer of graphene.3. The method of claim 2 , wherein said forming said layer of graphene on said exposed surface of said copper foil comprises chemical vapor deposition.4. The ...

HIGH-FREQUENCY PACKAGE

A high-frequency package has: a resin substrate; a high-frequency device mounted on a side of a first surface of the resin substrate; a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface; a transmission line for a high-frequency signal formed in an inner layer of the resin substrate; and a ground via of a ground potential formed within the resin substrate. A through hole is formed in the ground surface conductor. The ground via is placed between the transmission line and the through hole. 1. A high-frequency package comprising:a resin substrate;a high-frequency device mounted on a side of a first surface of the resin substrate;a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface;a transmission line for a high-frequency signal formed in an inner layer of the resin substrate; anda ground via of a ground potential formed within the resin substrate, whereina through hole is formed in the ground surface conductor, andthe ground via is placed between the transmission line and the through hole.2. The high-frequency package according to claim 1 , whereina number of the ground via is plural, andthe plural ground vias are placed along the transmission line.3. The high-frequency package according to claim 1 , wherein a diameter of the through hole is less than half of a wavelength of the high-frequency signal.4. A high-frequency package comprising:a resin substrate;a high-frequency device mounted on a side of a first surface of the resin substrate;a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface; anda transmission line for a high-frequency signal formed in an inner layer of the resin substrate, whereina through hole is formed in the ground surface conductor, anda diameter of the through hole is less than half of a ...

DEVICES AND METHODS RELATED TO STACKED DUPLEXERS

Devices and method related to stacked duplexers. In some embodiments, an assembly may include a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield. The assembly may also include a second WLP device having an RF shield, the second WLP device positioned over the first WLP device such that the RF shield of the second WLP device is electrically connected to the RF shield of the first WLP device. 1. An assembly comprising:a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield; anda second WLP device having an RF shield, the second WLP device positioned over the first WLP device such that the RF shield of the second WLP device is electrically connected to the RF shield of the first WLP device.2. The assembly of wherein the first WLP device includes a first RF filter claim 1 , and the second WLP device includes a second RF filter.3. The assembly of wherein each of the first and second RF filters includes a grounding contact pad claim 2 , at least one input contact pad claim 2 , and at least one output contact pad.4. The assembly of wherein the RF shield of each of the first and second RF filters includes a conformal coating of conductive material.5. The assembly of wherein the conformal coating of each RF filter is electrically connected to the corresponding grounding contact pad.6. The assembly of wherein the second RF filter is in an inverted orientation such that the conformal coating of the RF second filter is in electrical contact with the conformal coating of the first RF filter.7. The assembly of wherein the conformal coating of the second RF filter is electrically connectable to an external ground node through the grounding contact pad of the first RF filter.8. The assembly of wherein the first RF filter has a first lateral dimension and the second RF filter has a second lateral dimension that is greater than the first lateral dimension such that each of a plurality of edges of the second RF filter forms an ...

Packaged Electronic Module and Manufacturing Method Thereof

The present invention is a packaged electronic module with embedded electronics for use in smart cards. This invention assembles a plurality of electronics components on a flexible printed circuit, together with an integrated circuit chip and a contact plate, into a module. This module can then be embedded into a plastic card, using regular milling techniques, by a card manufacturer. This method packages the plurality of electronics components into a module. The present invention provides a business with the capability to avoid additional capital expenditure required for special equipment and enables all existing card manufacturers to manufacture smart cards with embedded electronics.

ELECTRONIC DEVICE

An electronic device is disclosed. The electronic device comprises a transistor provided on a substrate, a transmission line provided on the substrate and connected to the transistor, an electrode pad connected to the transmission line, and a connection wiring electrically connecting the electrode pad and the transmission line through a first wiring and a second wiring. Both of the first wiring and the second wiring are connected to different positions of the electrode pad. 1. An electronic device comprising:a transistor provided on a substrate;a transmission line provided on the substrate and connected to the transistor;an electrode pad connected to the transmission line; anda connection wiring electrically connecting the electrode pad and the transmission line through a first wiring and a second wiring,wherein both of the first wiring and the second wiring are connected to different portions of the electrode pad.2. The electronic device according to claim 1 ,wherein the first wiring and the second wiring are connected in parallel between the electrode pad and the transmission line.3. The electronic device according to claim 1 ,wherein the first wiring and the second wiring are larger in an inductor component per unit length than the transmission line.4. The electronic device according to claim 1 ,wherein the transmission line includes one end connected to the transistor and the other end connected to the electrode pad,wherein the first wiring is connected to a first part positioned on a side of the one end of the transmission line with respect to a center part of the electrode pad, andwherein the second wiring is connected to a second part positioned on an opposite side to the side of the one end of the transmission line with respect to the center part of the electrode pad.5. The electronic device according to claim 4 ,wherein the first wiring and the second wiring are point-symmetrical with respect to the center part of the electrode pad, or line-symmetrical with ...

RF Switch on High Resistive Substrate

A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. 1. A method comprising:performing a first implantation to implant a semiconductor substrate and to form a deep well region, wherein the semiconductor substrate is of a first conductivity type, and has a resistivity higher than about 5,000 ohm-cm, and wherein in the first implantation, an impurity of a second conductivity type opposite to the first conductivity type is implanted; a top portion overlying the well region; and', 'a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are substantially un-implanted in the first and the second implantations;, 'performing a second implantation to implant the semiconductor substrate, wherein a well region of the first conductivity type is formed over the deep well region, and wherein after the first and the second implantations, the semiconductor substrate comprisesforming a gate dielectric over the top portion of the semiconductor substrate;forming a gate electrode over the gate dielectric; andperforming a third implantation to implant the top portion of the semiconductor substrate and to form a source region and a ...

INTEGRATED ANTENNA ON INTERPOSER SUBSTRATE

Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate. 1. A semiconductor module having an integrated antenna structure , comprising:an excitable element;a first ground plane disposed between a substrate and the excitable element; anda second ground plane separated from the first ground plane by the substrate, wherein the second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.2. The semiconductor module of claim 1 , wherein the first ground plane comprises a first metal interconnect layer surrounded by a first dielectric layer and the excitable element comprises a second metal layer surrounded by a second dielectric layer.3. The semiconductor module of claim 2 , further comprising:one or more additional metal interconnect layers located between the excitable element and the first ground plane.4. The semiconductor module of claim 1 , wherein the second ground plane comprises a printed circuit board or a package substrate including a conductive layer.5. The semiconductor module of claim 1 , wherein the TSVs extend along a first direction through the substrate and the second ground plane extends past outermost sidewalls of the first ground plane along a second direction perpendicular to the first direction.6. The semiconductor module of claim 5 , wherein the second ground plane extends along the second direction past outermost sidewalls of the excitable element.7. The semiconductor module of claim 1 , wherein the excitable element and the first ground plane comprise copper.8. The semiconductor module of claim ...