УСТРОЙСТВО КОРРЕКЦИИ ЭЛЕКТРИЧЕСКОЙ ДЛИНЫ КАНАЛОВ УСИЛЕНИЯ

Полезная модель относится к области твердотельных передающих устройств. Достигаемым техническим результатом является повышение эффективности усиления и снижение требований к идентичности электрических длин компонент СВЧ-тракта. Данная полезная модель представляет собой устройство коррекции электрической длины каналов усиления, состоящее из усилителей мощности, коаксиальных кабелей, подводящих СВЧ-мощность к этим усилителям, коаксиальных кабелей, подводящих СВЧ-мощность к сумматорам итоговой мощности, при этом часть итогового сигнала ответвляется направленными ответвителями, объединяется маломощным сумматором в один обобщенный канал и подается на модуль цифровой обработки сигналов, который выдает на формирователь сигналов корректирующие команды для фазовращателей.

IMPROVEMENTS IN PACKAGING CIRCUITRY

... 1,204,795. Circuit assemblies. MUIRHEAD Ltd. 20 Dec., 1968 [29 March, 1968], No. 15399/68. Heading H1R. A circuit assembly comprises a can into which is fitted a rolled flexible printed circuit on which electrical component packs are mounted. A strip of insulating material carrying on both sides printed conductors is wound around a former and packs are soldered to the conductors on one of the faces, Fig. 1 (not shown). The sheet is then wound into a scroll, Fig. 2, and placed in a metal can 8 and potted. Connecting wires 7 are connected where desired before potting. In an alternative arrangement the packs are attached to the insulating strip as it is wound stage by stage around a cylindrical former and the former placed on a can with the scroll on it or the former can be removed. The components are provided with curved leads which are in an unstressed condition by being shaped to follow the curvature of the strip in its rolled form before being attached to the connection points on the conductors ...

ELECTRONICS MODULE WITH ROOF-WELL-BEHAVED TRAGER

ROTARY ELECTRIC RECTIFIER ARRANGEMENT

ROTARY ELECTRIC RECTIFIER ARRANGEMENT

PROCEDURE FOR THE PRODUCTION OF AN ELECTRONIC CIRCUIT MODULE WITH HIGH DEVICE COMPLEXITY

ROTARY ONE GLEICHRICHTBRANORDNUNG

ELECTROSTATICALLY BONDED SEMICONDUCTOR-ON-INSULATOR MOS DEVICE, A METHOD OF MAKING THE SAME

AN ELECTROSTATICALLY BONDED SEMICONDUCTOR-ON-INSULATOR MOS DEVICE, AND A METHOD OF MAKING THE SAME An electrostatically bonded semiconductor-on-insulator and particularly semiconductor-on-sapphire MOS devices are made of bulk materials. A semiconductor body of a bulk material of less than about 75 microns in thickness is electrostatically bonded to an insulator substrate of a bulk material. A dielectric layer of between 500 and 2,000 Angstroms in thickness is then formed on the semiconductor body to make a MOS semiconductor device and preferably a MOS field-effect transistor. The semiconductor-on-insulator MOS device is preferably made by first forming a major surface of the dielectric substrate and a major surface of the semiconductor body in planar configurations, applying a metal layer to the opposed major surface of the insulator substrate, and placing the planar surfaces of the body and substrate in intimate contact. The assembly is then heated to at least 300.degree.C. and preferably ...

ROTIERENDE GLEICHRICHTERANORDNUNG AN EINER ELEKTRISCHEN MASCHINE.

ARRANGEMENT OF RADIALLY INSTALLED SEMICONDUCTOR ELEMENTS ON A CARRIER WHEEL.

HIGH VOLTAGE ELECTRIC RECTIFIER.

Resin multilayer base plate and electronic equipment

The utility model relates to a resin multilayer base plate and electronic equipment, the utility model discloses a characterized in that of flat cable (101), range upon range of have a plurality of resin layers (11-15) that have the compliance, possesses line conductor (23A) and earthing conductor (21A, 25A, 25B), including earthing conductor (21A, 25A, relative and three printed line way (the 106A that constitute in the two sides of an arbitrary and gate conductor (23A) 25B), 106C), and earthing conductor (21A, 25A, a facial features of the arbitrary and gate conductor (23A) 25B) to and the microstripline (106B) that constitutes, three printed line way (the 106A of width ratio of the line conductor (23A) on the microstripline (106B), the width of the line conductor (23A) 106C) will be extended, carry out the bending with this flat cable (101) on the position that is provided with microstripline (106B).

ROTATING RECTIFIER ASSEMBLY FOR BRUSHLESS EXCITERS

Using method of preparation of the devices of the layers of transition between semiconductors from the types p and N

BRUSHLESS DYNAMO-ELECTRIC MACHINE

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to each other. The package structure is over the first surface, and includes a die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the exposed first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant encapsulates the package structure, and exposes at least part of the second conductive terminals ...

CIRCUIT FOR PRODUCING A HIGH DIRECT VOLTAGE FROM A MEDIUM FREQUENCY ALTERNATING VOLTAGE

Circuit comprised of one or a plurality of high voltage transformers and of rectifier systems, which may be appropriately used for the step-up trasnformation of medium frequency voltages, the rectification and the filtration. The implementation of the disclosed circuit enables to obtain systems of reduced size and weight, and which may be used as high voltage supply units with good dynimic characteristics and with less ripples. The secondary winding of the high voltage transformer presents a disc arrangement. From the secondary disc windings are arranged galvanically connected winding systems (a pre-determined number of disc windings are series mounted), the resultant alternating voltage of individual galvanically connected winding systems adds to series connected partial rectifiers under direct current side. A preferred embodiment uses polypropylene or polyethylene as base material for the disc-shaped winding bodies and the isolation of the layers.

High Density electronic circuit modules

The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.

Semiconductor package devices including interposer openings for heat transfer member

A semiconductor package device includes a lower package, an interposer disposed on the lower package and including a ground layer and at least one opening, and an upper package on the interposer. The lower package includes a first package substrate, a first semiconductor chip on the first package substrate, and a first molding compound layer on the first package substrate. The upper package includes a second package substrate and at least one upper semiconductor chip on the second package substrate. A heat transfer member includes a first portion disposed between the interposer and the upper package, a second portion disposed in the at least one opening of the interposer, and a third portion disposed between the interposer and the lower package.

Thermoelectric generator

A thermoelectric generator includes a tube in which a first fluid flows, a power generation module, a holding member, and a heat exchanging fin. The power generation module includes a thermoelectric conversion element. The holding member holds a stacked body in which the power generation module and the tube are stacked with each other such that heat can be transferred between the power generation module and the tube. Both end portions of the holding member are located and fixed outside both ends of the stacked body. The heat exchanging fin includes a pair of end fin portions provided on the reverse surface of the holding member at portions corresponding to the both ends of the stacked body, and an intermediate fin located between the pair of end fin portions and higher in stiffness than the pair of end fin portions.

Package structure having adhesive layer surrounded dam structure

A package structure includes a substrate, a die, an adhesive layer, a dam structure, and an encapsulant. The die is disposed on the substrate. The adhesive layer is disposed between the substrate and the die. The adhesive layer has a curved surface. The dam structure is disposed on the substrate and surrounded by the adhesive layer. The encapsulant encapsulates the die.

Halbleiterbauelement mit mehreren Halbleiterchips

The invention relates to a semiconductor component, comprising at least one semiconductor chip, external contacts and a printed conductor array. The semiconductor component has at least one support layer, at least one intermediate layer and at least one cover layer. The intermediate layer is fitted with at least one opening in which the semiconductor chip is inserted. The carrier layer, the intermediate layer and the cover layer are superimposed, forming a submodule. When several submodules are superimposed, a semiconductor component is produced in which the semiconductor chips are located in several superimposed planes. The semiconductor chips can be interconnected.

Keramische Packung vom Halbleiteranordnungstyp und Verfahren zum Zusammensetzen derselben.

Rectifier arrangement

Two U-shaped sheet metal members having legs through which the cooling air passes have bases onto which at least two of the load current carrying diodes are fastened, the connection between the diodes and the sheet metal members forming the heat sink being a highly heat conductive connection.

MOUNTING RECTIFIERS ON ROTARY SHAFTS

... 1501072 Mounting rectifiers in dynamoelectric machines KRAFTWERK UNION AG 16 Feb 1976 [17 March 1975] 06039/76 Heading H2A In a rectifier assembly arranged to rotate with the shaft 1 of an electrical machine, a discshaped rectifier 8 is mounted between two clamping members 9, 10 and held in position and in contact with an electrical connector 14 by a compression spring 19. The drawing illustrates one of two rectifier carrier wheels on the shaft 1, the rectifier assembly being secured to the conventional flange 6 by bolts 11. The A.C. input lead 14 is a flexible strap whlch carries a contact 16 and a pressure member 17, the latter having a threaded extension 18 surrounded by the spring 19 which is pre-stressed by a bolt 22 engaging the extension of the pressure member. The bolt 22 is removed after assembly. The outer clamping member 9 serves as a heat sink for the rectifier. In addition, ventilation apertures 23, 24 are formed in the inner clamping member 10.

Current rectifier assembly

The invention provides a current rectifier assembly particularly for a motor vehicle alternator and having a pair of thermal radiators 1, 2 carrying groups of rectifier elements 3, 4, 5 and 6, 7, 8 connected so that the radiators constitute different poles. The radiators define an opening through which conductive bars 14 connected to the rectifier elements and connected in pairs to an insulating plate 15 through which they pass, the plate 15 being disposed transversely to the opening defined by the radiators and having on one face 15a thereof a printed circuit arranged to connect together and to a group of excitation rectifier elements 19, 20, 21 the groups of elements 3, 4, 5 and 6, 7, 8. The printed circuit is also arranged to permit the disposition of the rectifier elements 19, 20, 21 directly on the plate 15 as well as the connection together of the cathodes 22, 23, 24 of these rectifier elements. ...

VERFAHREN ZUR MONTAGE EINER ROTIERENDEN GLEICHRICHTERANORDNUNG FUR ELEKTRISCHE MASCHINEN MIT GLEICHRICHTER-SCHEIBENZELLEN

ROTIERENDE GLEICHRICHTERANORDNUNG

PROCEDURE FOR THE ASSEMBLY OF A ROTARY ELECTRIC RECTIFIER ARRANGEMENT FUR ELECTRICAL MACHINES WITH ELECTRIC RECTIFIER DISK CELLS

Electronic module having canopy-type carriers

RECTIFIER ASSEMBLY FOR BRUSHLESS EXCITATION SYSTEMS

BRUSHLESS DYNAMOELECTRIC MACHINE

HIGH-FREQUENCY TRANSMISSION LINE AND ELECTRONIC DEVICE

A high-frequency transmission line (10) is provided with a dielectric element (200) obtained by stacking dielectric layers (201, 202, 203). Resist films (31, 32) are respectively located on the two principal surfaces of the dielectric element (200). A first ground conductor (210) is located on substantially the entire resist film (31)-side surface of the dielectric layer (201). A signal conductor (220) having an elongated shape is located on the dielectric layer (203)-side surface of the dielectric layer (202). A ladder-shaped second ground conductor (230) is located on the resist film (32)-side surface of the dielectric layer (203). The signal conductor (220) is shaped so that the width increases towards the center along the direction of elongation. The first ground conductor (210) has a plurality of openings (211L) provided in the center region along the direction of elongation, and has a plurality of openings (211S) having a small opening area provided so as to flank the region in which ...

BRUSHLESS DYNAMOELECTRIC MACHINE

... 1418996 AC machines with DC excitation WESTINGHOUSE ELECTRIC CORP 19 Feb 1973 [6 March 1972] 7997/73 Heading H2A In a brushless dynamo-electric machine, e.g. an A.C. generator 62, having an A.C. exciter 60 and a rotating rectifier assembly 61 with at least one rectifier wheel 36, 37 mounted on the machine shaft 38 and insulated therefrom, at 40, there is mounted on the wheel a rectifier module 10 which comprises a conductive base member 11 supporting a fuse 25, at least one diode assembly having a disc-shaped pressure contact type rectifier diode 19 disposed between and in electrical and thermal contact with two metal heat sinks 20, 21, e.g. of Cu or Al of which one, 20, engages the base member, spring means supported from the base member and applying a predetermined force to the other, 21, of the heat sinks to maintain contact between the base member, heat sinks, and diode, and means electrically connecting the diode assembly to the fuse. The force is sufficient to hold the assembly together ...

RECTIFIER ARRANGEMENT

PROCEDURE FOR THE ASSEMBLY OF A ROTARY ELECTRIC RECTIFIER ARRANGEMENT FUR ELECTRICAL MACHINES WITH ELECTRIC RECTIFIER DISK CELLS

RECTIFIER ASSEMBLY

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH ELECTRIC POWER GENERATION FUNCTION

... [Problem] To provide a semiconductor integrated circuit device having a power generation function, which makes it possible to suppress an increase in size of a circuit board. [Solution] A power generation function-equipped semiconductor integrated circuit device 200 has a semiconductor integrated circuit device and a thermoelectric element 1. The semiconductor integrated circuit device includes a package 210 in which a semiconductor integrated circuit chip 230 is housed. The semiconductor integrated circuit chip 230 has a lower surface opposing a circuit board and an upper surface opposing a mounting surface. The thermoelectric element 1 includes: a casing part having a housing section; a first electrode portion disposed in the housing section; a second electrode portion that is disposed in the housing section and opposes the first electrode portion so as to be separated in a first direction from the first electrode portion and that has a work function different from that of the first electrode ...

RECTIFIER ASSEMBLY FOR BRUSHLESS EXCITATION SYSTEMS

HIGH DENSITY ELECTRONIC CIRCUIT MODULES

... 2129123 9316491 PCTABS00025 The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.

ELECTRONIC CIRCUIT

Alternateur électrique notamment alternateur triphasé avec redresseur triphasé pour voiture automobile.

A.ALTERNATEUR ELECTRIQUE, NOTAMMENT ALTERNATEUR TRIPHASE AVEC REDRESSEUR TRIPHASE, POUR VOITURE AUTOMOBILE. B.ALTERNATEUR CARACTERISE EN COMBINAISON EN CE QUE: LE REDRESSEUR COMPREND DEUX CORPS DE REFROIDISSEMENT 15, 35, LES DEUX CORPS DE REFROIDISSEMENT 15, 35 COMPORTENT UNE PARTIE ESSENTIELLEMENT ANNULAIRE 38 ENTOURANT L'ARBRE 25 DE L'ALTERNATEUR ET DES SAILLIES 39, 39 EN FORME DE PATTES S'ETENDANT RADIALEMENT VERS L'EXTERIEUR PAR RAPPORT A L'ARBRE 25 A PARTIR DE LA PARTIE ANNULAIRE, DES DIODES DE REDRESSEMENT 36, 36 SONT FIXEES PAR SOUDAGE SUR LES SAILLIES 39, 39 EN FORME DE PATTES, L'UN DES CORPS DE REFROIDISSEMENT EST UTILISE EN TANT QUE FLASQUE DE L'ALTERNATEUR. C.L'INVENTION S'APPLIQUE NOTAMMENT AUX ALTERNATEURS DE VOITURES AUTOMOBILES.

반도체 패키지

... 패키지 기판, 상기 패키지 기판 상에 실장되는 제 1 반도체 칩, 상기 제 1 반도체 칩 상에 배치되고, 연결 단자들을 통해 상기 패키지 기판에 접속되는 제 1 인터포저(interposer) 기판, 상기 제 1 인터포저 기판 상이 실장되는 제 2 반도체 칩, 및 상기 패키지 기판 상에서 상기 제 1 반도체 칩, 상기 제 1 인터포저 기판 및 상기 제 2 반도체 칩을 덮는 몰딩막을 포함하는 반도체 패키지를 제공하되, 상기 제 1 인터포저 기판은 상기 제 1 반도체 칩과 상기 제 2 반도체 칩 사이에서 상기 제 1 인터포저 기판을 수직으로 관통하는 제 1 밴트 홀(vent hole), 및 상기 제 1 인터포저 기판의 하부면 상에 배치되는 제 1 지지부들을 갖고, 상기 제 1 지지부들 각각은 상기 제 1 반도체 칩의 상부면과 접하고, 상기 몰딩막은 상기 제 1 반도체 칩과 상기 제 1 인터포저 기판 사이, 상기 제 2 반도체 칩과 상기 제 1 인터포저 기판 사이 및 상기 제 1 밴트 홀의 내부를 채울 수 있다.

집적 회로 패키지 및 방법

... 일 실시예에서, 디바이스는: 반도체 재료를 포함하는 반도체 다이; 반도체 다이에 인접하고, 금속을 포함하는 관통 비아; 관통 비아 및 반도체 다이 주위의 봉지재 ― 봉지재는 폴리머 수지를 포함함 ―; 및 봉지재와 관통 비아 간의 접착 층을 포함하고, 접착 층은 방향족 화합물과 아미노기를 갖는 접착제 화합물을 포함하고, 아미노기는 봉지재의 폴리머 수지에 결합되고, 방향족 화합물은 관통 비아의 금속에 결합되며, 방향족 화합물은 반도체 다이의 반도체 재료에 대해 화학적으로 불활성이다.

Semiconductor device

A semiconductor device of the present invention includes a first semiconductor package and a second semiconductor package which is mounted onto the first semiconductor package. The first semiconductor package has lands, on the upper surface, for mounting the second semiconductor package and lands, on the lower surface, for external connection, which are used for the connection with a mounting substrate. The second semiconductor package has external leads which are connected to the lands for mounting the second semiconductor package.

Micropackaging method and devices

The invention relates in one aspect to a method of micro-packaging a component. At least a first and a second semi-conductor substrate are provided, one of which has electrical through wafer connections (vias). A depression in either one of said substrates or in both is etched. A component is provided above vias and connected thereto. The substrates are joined to form a sealed package. The invention also relates to a micro-packaged electronic or micromechanic device, comprising a thin-walled casing of a semi-conductor material having electrical through connections through the bottom of the casing. An electronic or micromechanic component is attached to said electrical through connections, and the package is hermetically sealed for maintaining a desired atmosphere, suitably vacuum inside the box.

Package structure and manufacturing method thereof

A package structure includes a substrate, a die, an adhesive layer, a dam structure, and an encapsulant. The die is disposed on the substrate. The adhesive layer is disposed between the substrate and the die. The adhesive layer has a curved surface. The dam structure is disposed on the substrate and surrounded by the adhesive layer. The encapsulant encapsulates the die.

METHOD OF MANUFACTURING A HIGH DENSITY ELECTRONIC CIRCUIT MODULE

DISPLAY DEVICE

A display device is provided. A display device comprises, a first substrate; first and second internal banks disposed to extend in a first direction on the first substrate and spaced apart from each other in a second direction different from the first direction; a first electrode including a first main electrode disposed to extend in the first direction on one side of the first internal bank and a first sub-electrode disposed to extend in the first direction on the other side of the first internal bank and at least partially spaced apart from and facing the first main electrode; a second electrode disposed to extend in the first direction on one side of the second internal bank and spaced apart from and facing the first main electrode; and a light emitting element disposed between the first internal bank and the second internal bank, wherein the light emitting element has one end disposed on the first main electrode and the other end disposed on the second electrode.

HALBLEITERVORRICHTUNGEN, VERFAHREN ZUM HERSTELLEN EINER HALBLEITERVORRICHTUNG, UND SCHNITTSTELLENEINHEIT

Halbleitervorrichtung, die Folgendes umfasst:eine Grundplatte (100);mehrere Halbleitereinheiten (10, 20, 110, 120, 210), die parallel auf der Grundplatte (100) angeordnet sind, wobei die mehreren Halbleitereinheiten (10, 20, 110, 120, 210) ein oder mehrere Paare implementieren, wobei jede Halbleitereinheit (10, 20, 110, 120, 210) einen Halbleiterchip und einen stabförmigen Einheit-seitigen Steuerungsanschluss (11, 12, 13, 14, 21, 22, 23, 24) enthält, wobei der Einheit-seitige Steuerungsanschluss (11, 12, 13, 14, 21, 22, 23, 24) mit dem Halbleiterchip verbunden ist, wobei sich der Einheit-seitige Steuerungsanschluss (11, 12, 13, 14, 21, 22, 23, 24) gegenüber der Grundplatte (100) erstreckt; undeine Schnittstelleneinheit (30, 130, 230), die einen kastenförmigen Aufnahmeabschnitt (30a) enthält, wobei der Aufnahmeabschnitt (30a) auf den mehreren Halbleitereinheiten (10, 20, 110, 120, 210) angeordnet ist, wobei der Aufnahmeabschnitt (30a) eine Innenverdrahtung (91, 91x, 92, 92x, 93, 93x, 94, ...

Keramische Packung vom Halbleiteranordnungstyp und Verfahren zum Zusammensetzen derselben.

MULTI-ELEMENT MAGNETIC HEAD

... 1525007 Magnetic heads MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 11 Nov 1975 [12 Nov 1974 (3) 31 Dec 1974 (3)] 46602/75 Heading G5R In a multi-track magnetic head, the transducing gaps are formed between a common ferromagnetic base 107 and a plurality of ferromagnetic elements 113, signal windings 110 in (Fig. 11, not shown) or near (Fig. 13, not shown) the gaps being provided by a conductive layer and each being connected at one end 110a to a common electrode layer 108. As shown, a further conductive layer 109 provides a common bias winding.

ROTARY ELECTRIC RECTIFIER ARRANGEMENT

ROTIERENDE GLEICHRICHTERANORDNUNG

RECTIFIER ASSEMBLY FOR BRUSHLESS EXCITATION SYSTEMS

ROBUST CONSUMER ELECTRONIC DEVICE

A method includes providing a molded elastomeric mat having an input protrusion, an output device receiving surface including an output device contact, and a battery receiving indentation including a power supply contact. The method further includes insert molding an output conductive path into the elastomeric mat, the output conductive path electrically coupling a circuit carrier output contact to an output device contact, and insert molding a power supply conductive path into the elastomeric mat, the power supply conductive path electrically coupling a circuit carrier power contact to the power supply contact. The method includes interfacing the elastomeric mat with a circuit carrier, aligning the input protrusion with a circuit carrier input contact, interfacing a display device with the output device receiving surface, electrically connecting the display device with the output device contact, and positioning the elastomeric mat into a housing.

ELECTRONIC CIRCUIT

Method of preparation of devices using of the layers of transition between semiconductors from the types p and N

반도체 패키지 및 반도체 패키지의 제조방법

... 반도체 패키지와 반도체 패키지의 제조방법이 제공된다. 반도체 패키지는, 제1 영역과 제2 영역을 포함하는 기판, 제1 영역에서 기판을 관통하고, 일부가 기판의 상면으로 돌출된 관통비아, 제1 영역에서 관통비아의 상면을 노출시키는 트렌치와, 제2 영역에서 기판의 일부를 노출시키는 얼라인 키를 포함하는 절연층, 및 트렌치의 측벽과 바닥면을 따라 컨포말하게 형성된 제1 도전층과, 제1 도전층 상에 트렌치를 채우는 제2 도전층을 포함하는 패드를 포함할 수 있다.

FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES

Ultra high density integrated circuit package

An ultra-thin level-one integrated circuit package with improved moisture penetration characteristics manufactured using a transfer molded casing with metallic lamination layers is provided. Additionally, a method and apparatus for providing a multiple-element modular package including a plurality of such level-one packages in horizontal or vertical stack configuration is provided.

Method for manufacturing a semiconductor device using a circuit transfer film

The invention relates to the formation of arrays of thin film transistors (TFT's) on silicon substrates and the dicing and tiling of such substrates for transfer to a common module body.

Power module package structure

A power module package structure is disclosed. The control circuits are fabricated on a circuit plate, instead of fabricating them directly on a main substrate. The fabrication cost is reduced because the size of the substrate is shrunk. Furthermore, the power chips are placed on a material with high thermal conductivity. The heat produced from the power chips can be transmitted quickly. Thus, the reliability of the power module package can be improved.

Ultra high density integrated circuit packages method

An ultra-thin level-one integrated circuit package with improved moisture penetration characteristics manufactured using a transfer molded casing with metallic lamination layers is provided. Additionally, a method and apparatus for providing a multiple-element modular package including a plurality of such level-one packages in horizontal or vertical stack configuration is provided.

SEMICONDUCTOR MODULE WITH INTERLOCKED CONNECTION

A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.

Integrated circuit system and packaging method therefor

An integrated circuit system and a packaging method therefor are disclosed. The method includes providing a first carrier and a second carrier oppositely, with a first device set of the first carrier and a second device set of the second carrier both located between the first and second carriers, providing a molding material between the first and second carriers to make the first and second device sets respectively in contact with the molding material, curing the material to make the first and second device sets respectively mounted at two sides of the molding material, making the first and second carriers detached from the first device set and the molding material and from the second device set and the molding material respectively; and forming connection holes in the molding material and fabricating a conductive layer which extend into the connection holes to electrically connect the first and second device sets.

Semiconductor package with layer structures, antenna layer and electronic component

A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

Semiconductor package having a stiffener ring

A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.

MULTI-SCREEN DISPLAY DEVICE HAVING LIGHT-TRANSMISSIVE COVER WITH INVISIBLE BEZEL

The present invention is a multi-screen display device including a light transmissive cover with an invisible bezel. The multi-screen display device includes: a plurality of screen display units (11); bezels (12) formed between the screen display units (11); and a plurality of light transmissive covers (120), each of which has a rear surface (110a), a front surface (110c), and a side surface (110b), and is provided to the screen display units (11) while outer peripheral circumferences (120') of the front surfaces (120c) of the adjacent light transmissive covers are in contact with each other, and is provided to the screen display unit (11) so that the bezel (12) is positioned between the pair of facing inclined side surfaces (120b) of the adjacent light transmissive covers (120). Accordingly, there is an advantage in that the bezel is invisible.

RESIN-SEALED SEMICONDUCTOR PACKAGE AND FABRICATION THEREOF

PURPOSE: To miniaturize a semiconductor package and improve electrical characteristics of the same by providing a first conductor portion having a flat upper surface on a bonding pad on a principal surface of a semiconductor chip, and further providing sealing resin for exposing only the upper surface of the first conductor portion and sealing the semiconductor chip and a lump- shaped second conductor portion on the upper surface of the first conductor portion. CONSTITUTION: A bonding pad 4 is formed on a principal surface of a semiconductor chip 3, on which pad 4 an insulating layer 11 is formed so as to possess an opening portion. A buffer coated film 13 is formed on the insulating layer 11 so as to ride on a peripheral edge on which a ground metal layer 12 is formed. A connection layer 8 is formed on the ground metal layer 12, on which connection layer a first conductor portion 9 is formed. Sealing resin 1 is formed so as to expose only the upper surface of the first conductor portion ...

INTEGRIERTE HALBLEITERANORDNUNG

DEVICE OF ROTARY RECTIFICATION FOR ELECTRIC MACHINES

Alternateur électrique, notamment alternateur triphasé avec redresseur triphasé, pour voiture automobile.

A.ALTERNATEUR ELECTRIQUE COMPORTANT UN ENROULEMENT DE PHASES ET UN REDRESSEUR BRANCHE A LA SUITE, NOTAMMENT ALTERNATEUR TRIPHASE AVEC PONT REDRESSEUR TRIPHASE BRANCHE A LA SUITE POUR VEHICULES AUTOMOBILES, AVEC UN CARTER MUNI D'AU MOINS UN FLASQUE ET UN ARBRE MONTE POUR TOURNER DANS CE CARTER. B.ALTERNATEUR CARACTERISE EN COMBINAISON EN CE QUE: LE REDRESSEUR COMPREND DEUX CORPS DE REFROIDISSEMENT 15, 35 LES DEUX CORPS DE REFROIDISSEMENT 15, 35 COMPORTENT UNE PARTIE ESSENTIELLEMENT ANNULAIRE 38 ENTOURANT L'ARBRE 25 DE L'ALTERNATEUR ET DES SAILLIES 39, 39 EN FORME DE PATTES S'ETENDANT RADIALEMENT VERS L'EXTERIEUR PAR RAPPORT A L'ARBRE 25 A PARTIR DE LA PARTIE ANNULAIRE 38. C.L'INVENTION S'APPLIQUE NOTAMMENT AUX ALTERNATEURS DE VOITURES AUTOMOBILES.

BRUSHLESS DYNAMO-ELECTRIC MACHINE

RECTIFYING UNIT, IN PARTICULAR FOR ALTERNATOR OF MOTOR VEHICLE

RECTIFYING UNIT HAS HIGH VOLTAGE ASSOCIATES CONSTRUCTIVEMENT HAS A TRANSFORMER

ELECTRICAL ALTERNATOR INCLUDING AN ALTERNATOR FOR A MOTOR VEHICLE WITH A THREE-PHASE RECTIFIER

Bump forming method, bump forming device, and method for manufacturing semiconductor device

A method of forming bump for semiconductor device is provided which includes: a bonding process, in which a front end portion of a wire extending from a front end portion of a bonding tool is bonded to the first point X1; a wire reeling process, in which the bonding tool is moved in the direction away from the first point X1; a thin part forming process, in which a part of wire is pressed by the bonding tool in a second point X2 of a reference surface to form the thin part (64) on the wire; a wire shaping process, in which the wire bonded to the first point X1 is shaped to erect from the reference surface; and a bump forming process, in which the wire is cut from the thin part and a bump (60) having a shape of erected from the reference surface in the first point X1 is formed. Thereby, the bump having desired height may be formed more easily and efficiently.

Semiconductor device, layered semiconductor device, sealed-then-layered semiconductor device, and manufacturing methods therefor

This invention is a semiconductor device that contains a semiconductor element. Said semiconductor device also contains an above-semiconductor-element metal pad and metal wiring, both of which are electrically connected to the semiconductor element. The metal wiring is electrically connected to a through-electrode and a solder bump. The semiconductor device has a first insulating layer on which the semiconductor element is placed, a second insulating layer formed on top of the semiconductor element, and a third insulating layer formed on top of the second insulating layer. The metal wiring is electrically connected to the semiconductor element via the above-semiconductor-element metal pad on the top surface of the second insulating layer and passes through the second insulating layer from the top surface thereof to electrically connect to the abovementioned through-electrode on the bottom surface of the second insulating layer. Under-semiconductor-element metal wiring is laid out between ...

Stacked packages and systems incorporating the same

A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the bottom surfaces. The top and bottom unit terminals are provided at a set of ordered column positions. Each top unit terminal of the set, except the top unit terminals at the highest ordered column position, is connected to a respective bottom unit terminal of the same unit at a next higher ordered column position. Each bottom unit terminal of the set, except the bottom unit terminals of the lowest unit in the stack, is connected to a respective upper unit terminal of the next lower unit in the stack at the same column position.

Apparatus for stacking semiconductor chips

A multi-chip memory module comprises multiple standard, surface-mount-type memory chips stacked on top of each other, and a pair of printed circuit boards mounted on opposite sides of the memory chips to electrically interconnect the memory chips. Each printed circuit board has vias that are positioned to form multiple rows, with each row of vias used to connect the printed circuit board to a respective memory chip. The vias falling along the bottom-most row of each printed circuit board are also exposed and are used to surface mount the multi-chip module to pads of a memory board.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate including a first side, a second side opposite to the first side, and a device layer over the second side, and a conductive via extending through the substrate, and including a first portion adjacent to the first side and a second portion adjacent to the device layer, wherein the conductive via includes an interface between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.

STACKED MICROELECTRONIC PACKAGES HAVING AT LEAST TWO STACKED MICROELECTRONIC ELEMENTS ADJACENT ONE ANOTHER

A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

Semiconductor device having an on die termination circuit

According to one embodiment, a semiconductor device includes a transistor formed on a semiconductor chip, a lower-layer wiring connected to a diffusion layer of the transistor, and drawn outside the diffusion layer, and an upper-layer wiring drawn out from a pad electrode formed on the semiconductor chip, connected to the lower-layer wiring, and having resistivity lower than that of the lower-layer wiring.

GLEICHREICHTEREINHEIT

Improvements in and relating to asymmetrically conductive apparatus

... 728,304. Semi-conductor rectifiers. GENERAL ELECTRIC CO. Sept. 15, 1952 [Sept. 15, 1951], No. 23109/52. Class 37. A rectifier element comprises two plate members providing a sealed cavity which encloses a semi-conductor element comprising a rectifying barrier, the element being secured to one plate member and connected to the other, and the plate members having a first insulating washer between their edge portions and a second insulating washer which overlies one edge portion and is engaged by the other. In Fig. 1, the metal plate members 1 and 2 are sealed together by a rubber washer 7 and a cambric washer 6. A semi-conductor element 8 comprising a P-N junction is conductively secured to plate 1 and a spring 15 connects the opposite surface of the semi-conductor to plate 2. Portions 11, 12 of impurity deposits, which may be utilized for the production of the P-N junction as described in Specification 727,900 may be provided between the semi-conductor and the connections. The plate members ...

Power converter

A power converter capable of enhancing electric current detection accuracy by minimizing inductance of gate wiring. A power converter, particularly suitable for railway vehicles, includes a power semiconductor module 1, 2 equipped with a main emitter terminal 12, 22, a gate terminal 13, 23 and an auxiliary emitter terminal, 14, 24, and a gate drive substrate 15, 25 connected to the power semiconductor module, wherein the power semiconductor module and the gate drive substrate are connected by a metal conductor plate 16, 26. The metal conductor plate may connect the main emitter terminal and the gate drive substrate. The metal conductor plate may be installed between the main emitter terminal and another conductor plate installed above the main emitter terminal. The power semiconductor module may be an IGBT (Insulated Gate Bipolar Transistor).

Apparatus incorporating small-feature-size and large-feature-size components and method for making same

RECTIFIER ASSEMBLY FOR BRUSHLESS EXCITATION SYSTEMS

Package structure

RECTIFYING UNIT HAS HIGH VOLTAGE ASSOCIATES CONSTRUCTIVEMENT HAS A TRANSFORMER

Method of preparation of devices using of the layers of transition between semiconductors from the types p and N

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Semiconductor device including coupling conductive pattern

A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

High speed digital interconnect and method

In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Source Driver, An Image Display Assembly And An Image Display Apparatus

An image display panel assembly includes a flexible printed circuit (FPC), an image display panel, a gate driver integrated circuit (IC) package, and a source driver IC package. The FPC is configured to receive gate and source driving signals. The image display panel is electrically connected to the FPC, and includes a gate driving signal transfer pattern along a first edge of the image display panel, a source driving signal transfer pattern along a second edge adjacent to the first end, and a plurality of pixels. The gate driver integrated circuit (IC) package is configured to receive the gate driving signal through the gate driving signal transfer pattern and provide the gate driving signal to the plurality of pixels. The source driver IC package is configured to receive the source driving signal through the source driving signal transfer pattern and provide the source driving signal to the plurality of pixels.

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Package with embedded chip and method of fabricating the same

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Electric part package and manufacturing method thereof

A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Packaged semiconductor chips with array

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Dram device with built-in self-test circuitry

A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

Semiconductor package and method for manufacturing semiconductor package

A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Semiconductor chip module, semiconductor package having the same and package module

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

Semiconductor device and method of fabricating the same

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

Semiconductor Package with Embedded Die

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Package 3D Interconnection and Method of Making Same

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Chip-last embedded interconnect structures and methods of making the same

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Electronic device and method for producing a device

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Integrated circuit packaging system with collapsed multi-integration package and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having a side package substrate along a peripheral region of the base substrate and laterally peripheral to the central integrated circuit with the side package substrate coplanar with the central integrated circuit; and encapsulating the central integrated circuit and the side package above the base substrate with a base encapsulation to form a planar surface over the central integrated circuit and the side package facing away from the base substrate.

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Exposed interconnect for a package on package system

An integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation.

Semiconductor package

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

Flip chip assembly process for ultra thin substrate and package on package assembly

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Integrated circuit packaging system with interconnects and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect over the substrate; forming an encapsulation on the substrate and covering the vertical interconnect; and forming a rounded cavity, having a curved side, in the encapsulation with the vertical interconnect exposed in the rounded cavity.

Power Semiconductor Module with Asymmetrical Lead Spacing

A power semiconductor has power terminals arranged in a row at one side of the housing, with control terminals arranged in a row at the other side of the housing. The spacing between adjacent power terminals is greater than the spacing between adjacent control terminals.

Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof

A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.

Stackable integrated circuit package system

A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Package-on-package structures

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Glass as a substrate material and a final package for mems and ic devices

This disclosure provides systems, methods and apparatus for glass packaging of integrated circuit (IC) and electromechanical systems (EMS) devices. In one aspect, a glass package may include a glass substrate, a cover glass and one or more devices encapsulated between the glass substrate and the cover glass. The cover glass may be bonded to the glass substrate with an adhesive such as an epoxy, or a metal bond ring. The glass package also may include one or more signal transmission pathways between the one or more devices and the package exterior. In some implementations, a glass package including an EMS and/or IC device is configured to be directly attached to a printed circuit board (PCB) or other integration substrate by surface mount technology.

System in package and method of fabricating same

An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.

Discrete Three-Dimensional Memory

The present invention discloses a discrete three-dimensional memory (3D-M). It is partitioned into at least two discrete dice: a memory-array die and a peripheral-circuit die. The memory-array die comprises at least a 3D-M array, which is built in a 3-D space. The peripheral-circuit die comprises at least a peripheral-circuit component, which is built on a 2-D plane. At least one peripheral-circuit component of the 3D-M is formed in the peripheral-circuit die instead of in the memory-array die. The array efficiency of the memory-array die can be larger than 70%.

Integrated circuit system with test pads and method of manufacture thereof

A method of manufacture of an integrated circuit system includes: providing a substrate having a test pad with element pads; forming a conductive layer over the test pad, the conductive layer having element layers directly on the element pads; and mounting an integrated circuit over the substrate.

Semiconductor Device and Method of Forming a Reconfigured Stackable Wafer Level Package with Vertical Interconnect

A semiconductor device has a carrier with a semiconductor die mounting area. A plurality of conductive posts is formed in a periphery of the semiconductor die mounting area and in the carrier. A first portion of the carrier is removed to expose a first portion of the plurality of conductive posts such that a second portion of the plurality of conductive posts is embedded in a second portion of the carrier. A first semiconductor die is mounted to the semiconductor die mounting area and between the first portion of the plurality of conductive posts. A first encapsulant is deposited around the first semiconductor die and around the first portion of the plurality of conductive posts. A second portion of the carrier is removed to expose the second portion of the plurality of conductive posts. An interconnect structure is formed over the plurality of conductive posts and the first semiconductor die.

Stacked semiconductor device

Provided is a stacked semiconductor device ( 50 ) in which a semiconductor package ( 5 ) is stacked via connection terminals ( 8 ) on a semiconductor package ( 1 ), including a heat dissipating member ( 10 ) which is disposed between the semiconductor packages ( 1, 5 ), is brought into thermal contact with both of the packages ( 1, 5 ), and hangs over whole outer peripheral portions of the package ( 5 ). Such a structure causes heat generated from the package ( 5 ) to be released by heat dissipation into air above the package ( 5 ), heat dissipation into the air below the semiconductor package ( 5 ), heat transfer via the heat dissipating member ( 10 ) and a semiconductor element ( 3 ) to a first wiring substrate ( 2 ), heat transfer via the connection terminals ( 8 ) to the first wiring substrate ( 2 ), and heat dissipation via the heat dissipating member ( 10 ) into the air, thereby enhancing a temperature reduction effect of the semiconductor element.

Integrated circuit packaging system with external wire connection and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation.

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Integrated circuit packaging system with encapsulation and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.

Stub minimization for wirebond assemblies without windows

A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element. Each central region can have a width within three and one-half times a minimum pitch between adjacent terminals.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Multiple die stacking for two or more die

A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Apparatus and method for stacking integrated circuits

A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.

Package Structures and Methods for Forming the Same

A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

Semiconductor device

A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Molded interposer package and method for fabricating the same

The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

Semiconductor package

A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

Methods and Apparatus for Thinner Package on Package Structures

Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

Integrated circuit package assembly and method of forming the same

An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit package and the second integrated circuit package. At least one support structure is disposed between the first integrated circuit package and the second integrated circuit package to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical signal connections.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Discrete Three-Dimensional Memory Comprising Off-Die Read/Write-Voltage Generator

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (V R /V W -generator) is located on a separate peripheral-circuit die. The V R /V W -generator generates at least a read and/or write voltage to the 3D-array die. A single V R /V W -generator die can support multiple 3D-array dies.

Semiconductor package

A semiconductor package includes a substrate including a mounting surface having a plurality of ground pads, a semiconductor chip disposed on the mounting surface, a conductive connection part connected to at least one of the plurality of ground pads and having a greater width at a center than at an end, a molding member exposing a top surface of the conductive connection part while wrapping the mounting surface, the conductive connection part and the semiconductor chip, and a heat slug disposed on the molding member and connected to the top surface of the conductive connection part.

Package-on-package type semiconductor packages and methods for fabricating the same

A method of forming a semiconductor package may include providing a first package including a first semiconductor chip mounted on a first package substrate having a via-hole and molded by a first mold layer, providing a second package including a second semiconductor chip mounted on a second package substrate having a connection pad and molded by a second mold layer, stacking the first package on the second package to vertically align the via-hole with the connection pad, forming a through-hole penetrating the first and second packages and exposing the connection pad, and forming an electrical connection part in the through-hole. The electrical connection part may electrically connect the first package and the second package to each other.

System and Method for Fine Pitch PoP Structure

A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Semiconductor chip package, semiconductor module, and method for manufacturing same

In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.

Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package

A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.

Integrated circuit packaging system with terminals and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting platform; applying an attach layer on the mounting platform; mounting an integrated circuit die on the attach layer; forming an encapsulation on the integrated circuit die and the attach layer, the mounting platform exposed from the encapsulation; and forming a terminal having a terminal protrusion from the leadframe, the terminal protrusion below a horizontal plane of the mounting platform.

Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer

A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Wiring substrate and method of manufacturing the same

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

Package including an underfill material in a portion of an area between the package and a substrate or another package

Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first package, and a second package coupled to the substrate or the first package, wherein the second package includes at least one die and an underfill material disposed in a portion, but not an entirety, of an area between the package and the substrate or the first package. Other embodiments may be described and claimed.

Method and apparatus for reducing package warpage

Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.

Method of making semiconductor assembly with built-in stiffener and semiconductor assembly manufactured thereby

The present invention relates to a method of making a semiconductor assembly. In accordance with a preferred embodiment, the method includes: preparing a dielectric layer and a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier and the dielectric layer covers the supporting board; then removing the bump and a portion of the flange to form a cavity and expose the dielectric layer; then mounting a semiconductor device into the cavity; and then forming a build-up circuitry that includes a first conductive via in direct contact with the semiconductor device and provides signal routing for the semiconductor device. Accordingly, the direct electrical connection between the semiconductor device and the build-up circuitry is advantageous to high I/O and high performance, and the stiffener can provide adequate mechanical support for the build-up circuitry and the semiconductor device.

Semiconductor device

A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Contact and Method of Formation

A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.

Semiconductor package and package on package having the same

A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Stackable semiconductor assemblies and methods of manufacturing such assemblies

Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.

Method of fabricating a semiconductor package

A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency.

Interface Substrate with Interposer

An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Semiconductor package and method of manufacturing the same

A semiconductor package is provided with a package on package (PoP) configuration, and which may be implemented having a fine pitch. The semiconductor package can include a lower printed circuit board (PCB) having a top surface onto which at least one lower semiconductor chip is attached; an upper printed circuit board (PCB) disposed on the lower printed circuit board (PCB) and having a top surface onto which at least one upper semiconductor chip is attached; and a lower mold layer formed on the top surface of the lower printed circuit board (PCB) so as to be disposed between the lower printed circuit board (PCB) and the upper printed circuit board (PCB). A through via hole, including a first section formed in the lower mold layer and a second section formed on the first section can also be provided. The through via hole extends through the lower mold layer, and a solder layer is formed in the through via hole to electrically connect the upper printed circuit board (PCB) and the lower printed circuit board (PCB). A horizontal cross-sectional area of the first section of the through via hole varies over substantially an entire height of the first section, and a horizontal cross-sectional area of the second section gradually decreases from a top surface thereof toward an inner portion of the lower mold layer.

Stacked microelectronic packages having patterened sidewall conductors and methods for the fabrication thereof

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Methods and Apparatus for Package on Package Structures

A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.

Passive Devices in Package-on-Package Structures and Methods for Forming the Same

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

High density second level interconnection for bumpless build up layer (bbul) packaging technology

An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.

TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

MULTICHIP MODULE WITH STIFFING FRAME AND ASSOCIATED COVERS

A multichip module includes a carrier, a stiffening frame, a plurality of semiconductor chips, and a plurality of covers. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes a plurality of openings that accept the plurality of semiconductor chips and may be attached to the top surface of the carrier with an adhesive that absorbs dimensional changes between the stiffening frame and the carrier. The semiconductor chips are concentrically arranged within the plurality of openings of the stiffening frame and the plurality of covers are attached to the stiffening frame so as to enclose the plurality of openings. 1. A method comprising:attaching a stiffening frame to a carrier with a compliant adhesive that absorbs thermally induced dimensional variations between the stiffening frame and the carrier, the stiffening frame comprising a plurality of openings configured to accept a plurality of semiconductor chips;electronically coupling the plurality of semiconductor chips to the carrier, each semiconductor chip being concentrically arranged within a particular opening, and;attaching a plurality of covers to the stiffening frame to enclose the plurality of openings.2. The method of wherein at least a first cover is in thermal contact with a first semiconductor chip.3. The method of further comprising:attaching a thermal interface material barrier to the stiffening frame perimeter.4. The method of wherein each cover comprises a top surface and wherein the top surface of a first cover is coplanar with the top surface of a second cover.5. The method of wherein each cover comprises a top surface and wherein the top surface of a first cover is non-planar with the top surface of a second cover.6. The method of wherein each cover comprises a top surface claim 1 , wherein the stiffening frame comprises a top surface claim 1 , and wherein the top surface of a first cover is coplanar with the top ...

Semiconductor integrated circuit and signal transmission method thereof

A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

Three-Dimensional Memory Comprising Discrete Read/Write-Voltage Generator Die

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (V R /V W -generator) is located on a separate peripheral-circuit die. The V R /V W -generator generates at least a read and/or write voltage to the 3D-array die. A single V R /V W -generator die can support multiple 3D-array dies.

SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate. 1. A semiconductor package comprising:a package substrate;a semiconductor chip on the package substrate;an interposer substrate on the semiconductor chip, the interposer substrate comprising a first surface facing the semiconductor chip and a trench in the first surface, the trench located to vertically overlap the semiconductor chip; andan insulating filler between the semiconductor chip and the interposer substrate, the insulating filler at least partially filling the trench of the interposer substrate.2. The semiconductor package of claim 1 ,wherein the interposer substrate comprises a first side wall and a second side wall opposite to and facing each other, andwherein the trench extends from the first side wall of the interposer substrate to the second side wall of the interposer substrate.3. The semiconductor package of claim 1 ,wherein the interposer substrate comprises a base insulating layer, and a lower protection insulating layer on a lower surface of the base insulating layer facing the semiconductor chip, andwherein the trench is provided in the lower protection insulating layer.4. The semiconductor package of claim 3 ,wherein the interposer substrate comprises a conductive pattern disposed in the trench, andwherein the conductive pattern comprises an upper surface in contact with the base insulating layer, a lower surface in contact with the lower protection insulating layer and a side wall in contact with the lower protection insulating layer.5. The semiconductor ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer. 1. A semiconductor package comprising:a first redistribution structure having a first surface comprising a first pad and a second pad therein, and a second surface opposite the first surface and comprising a first redistribution layer electrically connected to the first pad and the second pad;a vertical connection structure comprising a land layer on the first pad, and a pillar layer on the land layer and electrically connected to the first redistribution layer;a semiconductor chip on the first surface of the first redistribution structure and comprising a connection electrode electrically connected to the second pad;a first encapsulant on at least a portion of the vertical connection structure and comprising a cavity sized to accept the semiconductor chip;a second encapsulant on the first encapsulant and in the cavity; anda first connection bump on the second surface of the first redistribution structure and electrically connected to the first redistribution layer,wherein the land layer is in the first surface of the first redistribution structure, anda width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer thereon.2. The semiconductor package of claim 1 , wherein a thickness of the first pad is greater than a thickness of the land layer of the vertical connection structure.3. The semiconductor package of claim 2 , wherein a thickness of the pillar layer is in a range of about 100 μm to about 200 μm claim 2 ,the thickness of the land layer is in a ...

SEMICONDUCTOR PACKAGES HAVING RESIDUAL STRESS LAYERS AND METHODS OF FABRICATING THE SAME

A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package. 1. A semiconductor package comprising a lower package and an upper package stacked on the lower package , wherein the lower package includes:a package substrate having upper and lower surfaces;a semiconductor chip disposed on the upper surface of the package substrate;a mold layer encapsulating the semiconductor chip; anda residual stress layer disposed on the semiconductor chip, wherein the residual stress layer includes a plastically deformed surface,wherein the residual stress layer has a residual stress to counterbalance warpage of the lower package.2. The semiconductor package of claim 1 , wherein the semiconductor chip includes an exposed surface not covered by the mold layer claim 1 , and the residual stress layer is in contact with the exposed surface of the semiconductor chip.3. The semiconductor package of claim 2 , wherein the plastically deformed surface of the residual stress includes a plurality of first dents.4. The semiconductor package of claim 3 , wherein the plastically deformed surface of the residual stress layer has first roughness claim 3 , and an upper surface of the mold layer has second roughness less than the first roughness.5. The semiconductor package of claim 3 , wherein the upper surface of the mold layer includes a plurality of second dents.6. The semiconductor package of claim 5 , ...

Method for Producing an Optoelectronic Device and Optoelectronic Device

A method for producing an optoelectronic device is specified. A housing base body is formed with a self-healing polymer material. A recess is found in the housing base body. The recess is confined by a bottom surface and at least one side wall which are formed at least in places by the plastic material of the base body. An optoelectronic semiconductor chip has a first main surface, a second main surface facing away from the first main surface and at least one side surface connecting the first main surface and the second main surface with each other. The optoelectronic semiconductor chip is placed in the recess, so that the first main surface is brought in contact with the bottom surface and the at least one side surface is brought in contact with the at least one side wall. 111-. (canceled)12. A method for producing an optoelectronic device , the method comprising:providing an housing base body, wherein the housing base body is formed with a plastic material that comprises a self-healing polymer material;forming a recess in the housing base body, wherein the recess is confined by a bottom surface and at least one side wall that are formed at least in places by the plastic material of the base body;providing a optoelectronic semiconductor chip, wherein the optoelectronic semiconductor chip has a first main surface, a second main surface facing away from the first main surface and at least one side surface connecting the first main surface and the second main surface with each other; andplacing the optoelectronic semiconductor chip in the recess, wherein the first main surface is brought in contact with the bottom surface and the at least one side surface is brought in contact with the at least one side wall.13. The method according to claim 12 , further comprising providing an electrical insulating material on the second main surface of the optoelectronic semiconductor chip.14. The method according to claim 12 , further comprising forming an electrical contact to the ...

Integrated circuit packages and methods of forming same

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate. 1. A packaged microelectronic device , comprising:an interposer substrate having a first side with a plurality of interposer contacts and a second side opposite the first side, the second side including a plurality of interposer pads arranged in an array corresponding to a standard JEDEC pinout;a microelectronic die attached and electrically coupled to the interposer substrate;a casing covering the die and at least a portion of the interposer substrate, wherein the casing has a thickness and a top facing away from the interposer substrate; anda plurality of electrically conductive through-casing interconnects in contact with and projecting from corresponding interposer contacts, wherein the through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing, and wherein the through-casing interconnects are at least partially encapsulated in the casing,wherein the through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to ...

STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES

A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. 116.-. (canceled)17. A method of forming a stud bump structure in a package structure , comprising:providing a conductive wire;pressing one end of the conductive wire to a bond pad and melting the conductive wire end to form a stud bump on the bond pad;severing the other end of the conductive wire close above the stud bump; andsoldering a solder ball to a top surface of the stud bump, the solder ball encapsulating the stud bump.18. The method of forming a stud bump structure of claim 17 , wherein the conductive wire comprises aluminum claim 17 , aluminum alloy claim 17 , copper claim 17 , copper alloy claim 17 , gold claim 17 , or gold alloy.19. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by wire bonding tool.20. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by a stud bump bonder.21. The method of forming a stud bump structure of claim 17 , wherein the severing the other end of the conductive wire leaves a tail extending from the bond pad.22. The method of forming a stud bump structure of claim 17 , further comprising applying ultrasonic energy to form the stud bump.23. The method of forming a stud bump structure of claim 17 , wherein the stud bump is disposed at a corner of a die.24. A method for forming a package structure claim 17 , the method comprising:providing a die wherein the die has a first periphery region adjacent a first edge of the die and a second ...

Mechanisms For Forming Bonding Structures

Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Semiconductor assemblies including thermal management configurations for reducing heat transfer between vertically stacked devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise at least one memory device mounted over a logic device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the memory device and the logic device. The thermally conductive layer includes a structure configured to transfer the thermal energy across a horizontal plane. The thermal-insulator interposer includes a structure configured to reduce heat transfer between the logic device and the memory device.

PACKAGE AND PACKAGING PROCESS OF A SEMICONDUCTOR DEVICE

A packaging process of a semiconductor device includes following steps. A patterned conductive layer and a solder resist layer that covers the patterned conductive layer are formed through 3D-printing over a carrier having a cavity. The patterned conductive layer and the solder resist layer extend to the outside of the cavity from the inside of the cavity. One portion of the patterned conductive layer is exposed by the solder resist layer. At least one semiconductor device is mounted on the patterned conductive layer in the cavity, such that the at least one semiconductor device is electrically connected to the patterned conductive layer. 1. A packaging process of a semiconductor device , comprising:forming a patterned conductive layer and a solder resist layer through three-dimensional printing over a carrier having a cavity, wherein the solder resist layer covers the patterned conductive layer, the patterned conductive layer and the solder resist layer extend to an outside of the cavity from an inside of the cavity, and one portion of the patterned conductive layer is exposed by the solder resist layer;mounting at least one semiconductor device on the patterned conductive layer in the cavity, such that the at least one semiconductor device is electrically connected to the patterned conductive layer;forming at least one tapered extension structure in the cavity, wherein the at least one tapered extension structure has a inclined layout surface, and the inclined layout surface of the at least one tapered extension structure extends from an active surface of the first semiconductor device to a bottom surface of the cavity; andforming a plurality of connecting traces on the active surface, the inclined layout surface, and the bottom surface through three-dimensional printing, wherein the connecting traces are electrically connected between the semiconductor device and the patterned conductive layer in the cavity.2. The packaging process according to claim 1 , wherein ...

SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed. 111-. (canceled)12. A method for fabricating an integrated circuit (IC) assembly , comprising:providing a package substrate having a first side and a second side disposed opposite to the first side;coupling an active side of a first die with the first side of the package substrate, the first die including an inactive side disposed opposite to the active side and one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; andforming a mold compound on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side;mounting ...

Semiconductor Package and Method

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Electronic circuit device and method of manufacturing electronic circuit device

The electronic circuit device according to the present invention including the wiring layer 13 including a plurality of the metal wirings, the photosensitive resin layer 21 made of the photosensitive resin arranged on the wiring layer 13, and the first electronic circuit element 33 arranged in the photosensitive resin layer 21. In this electronic circuit device, a plurality of opening 41 for exposing a part of the wiring layer 13 is formed on the photosensitive resin layer 21, and further, together with three-dimensionally connected to the first electronic circuit element 33, the re-distribution layer 42 on the first electronic circuit element including a plurality of the metal wirings which is three-dimensionally connected via a plurality of openings to a part of the wiring layer 13, and the first external connection terminal 51 connected to the re-distribution layer 42 are formed.