VARIABLE GATE-LÄNGEN FÜR VERTIKALE TRANSISTOREN

Ein Verfahren zu Fertigen einer vertikalen FET-Struktur beinhaltet vor einem Abscheiden eines Gates auf einem ersten vertikalen FET auf einem Halbleitersubstrat ein Abscheiden einer ersten Schicht auf dem ersten vertikalen FET auf dem Halbleitersubstrat. Das Verfahren beinhaltet des Weiteren vor einem Abscheiden eines Gates auf einem zweiten vertikalen FET auf dem Halbleitersubstrat ein Abscheiden einer zweiten Schicht auf dem zweiten vertikalen FET auf dem Halbleitersubstrat. Das Verfahren beinhaltet des Weiteren ein Ätzen der ersten Schicht auf dem ersten vertikalen FET bis zu einer geringeren Höhe als die zweite Schicht auf dem zweiten vertikalen FET. Das Verfahren beinhaltet des Weiteren ein Abscheiden eines Gate-Materials sowohl auf dem ersten vertikalen FET als auch auf dem zweiten vertikalen FET. Das Verfahren beinhaltet des Weiteren ein Ätzen des Gate-Materials sowohl auf dem ersten vertikalen FET als auch auf dem zweiten vertikalen FET bis zu einer koplanaren Höhe.

Bildung von Source-Drain-Erweiterungen in Metall-Ersatz-Gate-Transistoreinheit

Verfahren zur Herstellung eines Feldeffekttransistors, aufweisend: Bilden einer Platzhalter-Gate-Struktur, die aus einem Stopfen besteht, auf einer Fläche eines Halbleiters; Bilden eines ersten Abstandhalters, welcher den Stopfen umgibt, wobei der erste Abstandhalter ein Opfer-Abstandhalter ist; und Durchführen einer abgewinkelten Ionenimplantation, um in Nachbarschaft zu einer äußeren Seitenwand des ersten Abstandhalters eine Dotierstoffspezies in die Fläche des Halbleiters zu implantieren, um eine Source-Erweiterungszone und eine Drain-Erweiterungszone zu bilden, wobei sich die implantierte Dotierstoffspezies in einem Ausmaß unter der äußeren Seitenwand des ersten Abstandhalters erstreckt, welches eine Funktion des Winkels der Ionenimplantation ist; und Durchführen eines Laser-Temperns, um die Implantation der Source-Erweiterung und der Drain-Erweiterung zu aktivieren.

Verfahren und Struktur für eine Halbleitervorrichtung mit einer Gatespacer-Schutzschicht

Ein Verfahren zum Ausbilden einer Halbleitervorrichtung umfasst ein Bereitstellen einer Vorstufe. Die Vorstufe umfasst ein Substrat, einen Gatestapel über dem Substrat, eine erste dielektrische Schicht über dem Gatestapel, einen Gatespacer auf Seitenwänden des Gatestapels und auf Seitenwänden der ersten dielektrischen Schicht, und Source- und Drainkontakte (S/D-Kontakte) auf gegenüberliegenden Seiten des Gatestapels. Das Verfahren umfasst ferner ein Aussparen des Gatespacers, um die Seitenwände der ersten dielektrischen Schicht zumindest teilweise freizulegen, aber nicht die Seitenwände des Gatestapels freizulegen. Das Verfahren umfasst ferner ein Ausbilden einer Spacerschutzschicht über dem Gatespacer, der ersten dielektrischen Schicht und den S/D-Kontakten.

METALLGATE FÜR EINEN FELDEFFEKTTRANSISTOR UND VERFAHREN

Offenbart werden ein Metallgate (z.B. ein Replacement-Metal-Gate (RMG) für einen Feldeffekttransistor (FET) und ein Verfahren zur Herstellung des Metallgates. Das Verfahren umfasst ein Abscheiden einer konformen dielektrischen Schicht, um eine Gateöffnung auszurichten, und ein Durchführen einer Reihe von nicht-geclusterten und geclusterten konformen Metallabscheidungs- und Zurückätzungsprozessen, um die Höhen der konformen Metallschichten innerhalb der Gateöffnung selektiv anzupassen. Durch ein selektives Steuern der Höhen der konformen Metallschichten bietet das Verfahren eine verbesserte Gesamthöhenkontrolle und Gate-Qualität, insbesondere wenn das Metallgate eine kleine kritische Dimension (CD) und/oder ein hohes Seitenverhältnis (AR) aufweist. Das Verfahren kann auch den Einsatz verschiedener Ätztechniken während der verschiedenen Zurückätzungsprozesse und insbesondere dann umfassen, wenn verschiedene Materialien und/oder verschiedene Materialgrenzflächen einem Ätzmittel ausgesetzt ...

Vorrichtung mit ausgespartem Austrittsarbeitsmetall in CMOS-Transistor-Gates und Herstellungsverfahren

Vorrichtung mit: einem Substrat; einem Paar Abstandshalter, die auf einer Oberfläche des Substrats angeordnet sind; einer dielektrischen High-k-Schicht, die konform auf die Oberfläche des Substrats zwischen dem Paar Abstandshalter und auf Seitenwände der Abstandshalter abgeschieden ist; einer ausgesparten Austrittsarbeitsmetallschicht, die konform auf die dielektrische High-k-Schicht entlang der Oberfläche des Substrats zwischen dem Paar Abstandshalter und entlang einem Teil der Seitenwände der Abstandshalter abgeschieden ist; einer zweiten Austrittsarbeitsmetallschicht, die konform auf die ausgesparte Austrittsarbeitsmetallschicht und dem Paar Abstandshalter abgeschieden ist; und einer Elektrodenmetallschicht, die auf die zweite Austrittsarbeitsmetallschicht abgeschieden ist.

Halbleiterbauelement und Verfahren zur Herstellung des Halbleiterbauelements

Verfahren zur Herstellung eines Halbleiterbauelements, wobei das Verfahren umfasst: Bilden eines Gateschichtstapels mit dem gleichen Schichtaufbau über einem ersten aktiven Gebiet eines ersten Transistors und über einem zweiten aktiven Gebiet eines zweiten Transistors, wobei der Gateschichtstapel ein Gatedielektrikumsmaterial und ein erstes nicht-Halbleiter-Elektrodenmaterial, das eine erste austrittsarbeitseinstellende Sorte zum Einstellen einer Austrittsarbeit für den ersten Transistor aufweist, aufweist; Bilden einer ersten Gateelektrodenstruktur auf dem ersten aktiven Gebiet und einer zweiten Gateelektrodenstruktur auf dem zweiten aktiven Gebiet aus dem Gateschichtstapel; und Ersetzen des ersten Elektrodenmaterials in der zweiten Gateelektrodenstruktur durch ein zweites Elektrodenmaterial mit einer zweiten Austrittsarbeit, die für den zweiten Transistor geeignet ist.

FINNEN-FELDEFFEKTTRANSISTOR-BAUELEMENT UND VERFAHREN

Ein Verfahren weist die folgenden Schritte auf: Entfernen eines ersten Teils einer Dummy-Gate-Struktur über einer ersten Finne, wobei ein zweiter Teil der Dummy-Gate-Struktur über einer zweiten Finne bestehen bleibt, wobei durch das Entfernen des ersten Teils eine erste Aussparung entsteht, die die erste Finne freilegt; Abscheiden eines ersten dielektrischen Gate-Materials in der ersten Aussparung und über der ersten Finne; und Entfernen des zweiten Teils der Dummy-Gate-Struktur über der zweiten Finne, wobei durch das Entfernen des zweiten Teils eine zweite Aussparung entsteht, die die zweite Finne freilegt. Das Verfahren umfasst weiterhin Folgendes: Abscheiden eines zweiten dielektrischen Gate-Materials in der zweiten Aussparung und über der zweiten Finne, wobei das zweite dielektrische Gate-Material das erste dielektrische Gate-Material kontaktiert; und Füllen der ersten Aussparung und der zweiten Aussparung mit einem leitfähigen Material.

Halbleitervorrichtung

Eine Halbleitervorrichtung umfasst eine Halbleiterschicht, die ein erstes Vorrichtungsausbildungsgebiet und ein zweites Vorrichtungsausbildungsgebiet aufweist, einen ersten HEMT, der in dem ersten Vorrichtungsausbildungsgebiet ausgebildet ist und ein Gebiet zweidimensionalen Elektronengases als einen Kanal aufweist, einen zweiten HEMT, der in dem zweiten Vorrichtungsausbildungsgebiet ausgebildet ist und ein Gebiet zweidimensionalen Elektronengases als einen Kanal aufweist, und eine Gebietstrennstruktur, die in der Halbleiterschicht ausgebildet ist und das erste Vorrichtungsausbildungsgebiet und das zweite Vorrichtungsgebiet definiert.

NEUARTIGE STRUKTUR FÜR METALL-GATE-ELEKTRODE UND HERSTELLUNGSVERFAHREN

Eine Halbleitervorrichtung umfasst eine Kanalkomponente eines Transistors und eine über der Kanalkomponente angeordnete Gate-Komponente. Die Gate-Komponente umfasst: eine dielektrische Schicht, eine erste Austrittsarbeitsmetallschicht, die über der dielektrischen Schicht angeordnet ist, eine Füllmetallschicht, die über der ersten Austrittsarbeitsmetallschicht angeordnet ist, und eine zweite Austrittsarbeitsmetallschicht, die über der Füllmetallschicht angeordnet ist.

Fin-Feldeffekttransistor (Finfet) - Bauelementstruktur mit unebenem Gate und Verfahren zur Ausbildung derselben

Es wird eine FinFET-Bauelementstruktur geschaffen. Die FinFET-Bauelementstruktur umfasst eine Isolationsstruktur auf, die über einem Substrat ausgebildet ist, und eine Fin-Struktur, die über dem Substrat ausgebildet ist. Die FinFET-Bauelementstruktur umfasst eine erste Gate-Struktur und eine zweite Gate-Struktur, die über der Fin-Struktur ausgebildet sind, und die erste Gate-Struktur weist in einer Richtung parallel zur Fin-Struktur eine erste Breite auf, die zweite Gate-Struktur weist in einer Richtung parallel zur Fin-Struktur eine zweite Breite auf, und die erste Breite ist kleiner als die zweite Breite. Die erste Gate-Struktur umfasst eine erste Austrittsarbeit-Schicht, die eine erste Höhe aufweist. Die zweite Gate-Struktur umfasst eine zweite Austrittsarbeit-Schicht, die eine zweite Höhe aufweist, und eine Lücke zwischen der ersten Höhe und der zweiten Höhe liegt in einem Bereich von circa 1 nm bis zu circa 6 nm.

Einstellen der Schwellenspannung durch metastabile Plasmabehandlung

Ein Verfahren umfasst ein Ausbilden einer ersten High-k-Dielektrikumsschicht über einem ersten Halbleiterbereich, Ausbilden einer zweiten High-k-Dielektrikumsschicht über einem zweiten Halbleiterbereich, Ausbilden einer ersten Metallschicht, die einen ersten Abschnitt über der ersten High-k-Dielektrikumsschicht und einen zweiten Abschnitt über der zweiten High-k-Dielektrikumsschicht umfasst, Ausbilden einer Ätzmaske über dem zweiten Abschnitt der ersten Metallschicht und Ätzen des ersten Abschnitts der ersten Metallschicht. Die Ätzmaske schützt den zweiten Abschnitt der ersten Metallschicht. Die Ätzmaske wird mit metastabilem Plasma verascht. Eine zweite Metallschicht wird dann über der ersten High-k-Dielektrikumsschicht ausgebildet.

Einstellen einer Schwellwertspannung für komplexe Transistoren durch Diffundieren einer Metallsorte in das Gatedielektrikum vor der Gatestrukturierung

Verfahren mit: Bilden eines Gatedielektrikumsmaterials (210) über einem ersten aktiven Gebiet (202a) und einem zweiten aktiven Gebiet (202b) eines Halbleiterbauelements (202); Bilden einer ersten Diffusionsschicht (221) mit einer ersten Metallsorte selektiv über dem ersten aktiven Gebiet (202a); Bilden einer zweiten Diffusionsschicht (226) mit einer zweiten Metallsorte über dem zweiten aktiven Gebiet (202b); Ausführen einer Wärmebehandlung, um eine Diffusion der ersten Metallsorte von der ersten Diffusionsschicht (221) mit der ersten Metallsorte in das Gatedielektrikumsmaterial (210) über dem ersten aktiven Gebiet (202a) zu initiieren und um eine Diffusion der zweiten Metallsorte von der zweiten Diffusionsschicht (226) mit der zweiten Metallsorte in das Gatedielektrikumsmaterial (210) über dem zweiten aktiven Gebiet (202b) zu initiieren; Entfernen von der ersten Diffusionsschicht (221) mit der ersten Metallsorte und der zweiten Diffusionsschicht (226) mit der zweiten Metallsorte, so dass ...

ERSATZ-METALL-GATE-TRANSISTOREN MIT REDUZIERTER GATEOXID-LECKAGE

Einstellung von Transistoreigenschaften auf der Grundlage einer späten Wannenimplantation

Es wird ein selbstjustierter Wannenimplantationsprozess so ausgeführt, dass die Schwellwertspannung und/oder der Körperwiderstand von Transistoren eingestellt werden. Dazu wird nach dem Entfernen eines Platzhaltermaterials von Gateelektrodenstrukturen der Implantationsprozess auf der Grundlage geeigneter Prozessparameter derart ausgeführt, dass die gewünschten Transistoreigenschaften erreicht werden. Daraufhin wird ein geeignetes Elektrodenmetall eingefüllt, wodurch Gateelektrodenstrukturen mit besseren Verhalten geschaffen werden. Beispielsweise werden Metallgateelektrodenstrukturen mit großem auf der Grundlage eines Austauschgateverfahrens hergestellt, wobei zusätzlich die späte Implantation für einen hohen Grad an Flexibilität beim Bereitstellen unterschiedlicher Transistorversionen der gleichen grundlegenden Struktur bietet.

Halbleiterbauelemente und Verfahren zu deren Herstellung

Halbleiterbauelemente und Verfahren zu deren Herstellung werden offenbart. Bei einer bevorzugten Ausführungsform beinhaltet ein Verfahren zum Herstellen eines Halbleiterbauelements das Bereitstellen eines Werkstücks, die Anordnung eines Gatedielektrikumsmaterials über dem Werkstück und die Anordnung eines Gatematerials über dem Gatedielektrikumsmaterial. Cl oder F wird in das Gatematerial eingeführt, wobei das Einbringen des Cl oder F in das Gatematerial eine Austrittsarbeit des Gatematerials beeinflusst. Das Gatematerial und das Gatedielektrikumsmaterial werden strukturiert, wodurch mindestens ein Transistor entsteht.

Preserving stress benefits of UV curing in replacement gate transistor fabrication

MOS transistor adopting titanium-carbon-nitride gate electrode and manufacturing method thereof

Titanium-carbon-nitride gate electrode

A MOS transistor with a titanium-carbon-nitride (TiCN) gate electrode is provided. The MOS transistor has a gate insulating film, a gate electrode, and a source/drain region on a semiconductor substrate. The gate electrode is formed either of a single TiCN film or a double film having a TiCN film and a low-resistant metal film formed thereon. The TiCN gate electrode exhibits a low resistance of about 80-100* capital Greek omega *-cm, and variations in Fermi energy level can be controlled by use of such a gate electrode.

Replacement gate electrode with planar work function material layers

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

HUMIDITY SENSOR

Vertical transport transistors with equal gate stack thicknesses

Semiconductor device having a gate stack with tunable work function

A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

Logic elements, logic systems and oscillators that include charge-flow transistors

Oscillators that include charge-flow transistor logic elements, each logic element including a charge-flow transistor and a load element, in combination. The charge-flow transistors have TURN-ON times ton and TURN-OFF times toff that can be very different from one another (e.g., ton can range from milliseconds to hundreds of seconds; whereas in the charge-flow transistors shown herein toff is typically less than one microsecond). The magnitude of ton is sensitive to the environment; hence, the period of oscillation can be used as a measure of an environmental condition.

Recessed workfunction metal in cmos transistor gates

Conformal replacement gate electrode for short channel devices

A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 2.5 nm. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.

TRANSITION METAL CRAVING FOR USE AS GATE ELECTRODE AND THESE ALLOYS CONTAINING ELEMENTS

PMOS, NMOSUND CMOS HALBLEITERANORDUNUNGEN AND PROCEEDING TO THEIR PRODUCTION

Halo-free non-rectifying contact on chip with halo source/drain diffusion

A semiconductor device having a metal barrier layer for a dielectric material having a high dielectric constant and method of manufacture thereof

Method for forming integrated structure

Self-Aligned Metal Gate Etch Back Process And Device

Semiconductor structures with coplanar recessed gate layers and fabrication methods

Method for manufacturing semiconductor device

High voltage devices and methods of forming the same

Integrated circuit device having defined gate spacing and method of designing and fabricating thereof

Method and apparatus for doping engineering and threshold voltage regulation by integrated deposition of titanium nitride and aluminum films

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a gate dielectric layer on the substrate, and a gate electrode stack on the gate dielectric layer. The gate electrode stack includes a metal filling line, a wetting layer, a metal diffusion blocking layer, and a work function layer. The wetting layer is in contact with a sidewall and a bottom surface of the metal filling line. The metal diffusion blocking layer is in contact with the wetting layer and covers the sidewall and the bottom surface of the metal filling line with the wetting layer therebetween. The work function layer covers the sidewall and the bottom surface of the metal filling line with the wetting layer and the metal diffusion blocking layer therebetween. A method of manufacturing the semiconductor device is also provided.

Method of manufacturing semiconductor device using acid diffusion

Integrated circuits and fabrication methods thereof

Method for regulating metal gate work function for PMOS (P-channel Metal Oxide Semiconductor) device

The invention relates to a method for regulating a metal gate work function for a PMOS (P-channel Metal Oxide Semiconductor) device. The method comprises the following steps of: depositing a metal nitride film or a metal film on a high-K medium by using a physical vapor-phase deposition method as a metal gate electrode; implanting elements of Al, Pt, Ru, Ga or Ir, and the like into the metal gateelectrode by adopting an ion implanting method; and driving doped metal ions onto the interfaces of the metal gate electrode and the high-K medium to form accumulation or react through the interfacesto generate a dipole so as to achieve the purpose of regulating the effective work function of a metal gate. The method has the advantages of universality, simple and convenient process, strong capacity of regulating the metal gate function and good compatibility with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process.

P-type MOSFET and its manufacturing method

Manufacture method of metal gates in gate-post process

Method for manufacturing semiconductor

Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure. The manufacturing method can provides a larger gate etching permissible level. In addition, the method makes the height of the gate to adjust according to special device and allow to reduce height of the gate in different stages in the manufacturing process.

Semiconductor device and fabricating method thereof

The invention provides a semiconductor device and method for making same. The semiconductor device includes: a semiconductor substrate including source/drain regions and a channel between the source/drain regions; a gate oxide layer pattern on the channel; a metal nitride layer pattern on the gate oxide layer pattern; a silicide on the metal nitride layer pattern; and a spacer on a side of the gate oxide layer pattern, the metal nitride layer pattern, and the silicide. In one embodiment, the metal nitride layer pattern is 1/4 to 1/2 as thick as the silicide.

PUT TRANSISTOR HAS METAL GRID AUTO-ALIGNEE AND ITS MANUFACTORING PROCESS

La présente invention concerne un transistor MIS et son procédé de réalisation. Le procédé comporte les étapes suivantes: a) la réalisation sur un substrat (100) d'une grille factice en un matériau apte à résister à un traitement thermique, b) la formation dans le substrat de régions (118, 120) de source et de drain auto-alignées sur la grille factice, c) l'enrobage latéral de la grille factice avec un matériau isolant électrique (124, 126), d) l'élimination de la grille factice et la formation à la place de la grille factice d'une grille définitive (136) en un matériau de faible résistivité. Application à la fabrication de circuits hyperfréquences.

SEMICONDUCTOR DEVICE WITH ELECTRODE AND METHOD OF CAPACITOR

SELECTIVE GERMANIUM P-CONTACT METALIZATION THROUGH TRENCH

METAL GATE STACK WITH ETCH STOP LAYER IMPROVED THROUGH IMPLANTATION OF METALLIC ATOMS

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME

FINFETS WITH MULTIPLE THRESHOLD VOLTAGES

NMOS 금속 게이트 물질들, 그 제조 방법들, 및 금속계 전구체들을 사용하는 CVD 및 ALD 프로세스들 장비

... 본 발명의 실시예들은 일반적으로 금속-함유 물질들을 증착하기 위한 방법들과 그 조성들을 제공한다. 상기 방법들은, 열분해, CVD, 펄스-CVD 또는 ALD를 포함하는 기상 증착 프로세스에 의해, 금속, 금속 탄화물, 금속 규화물, 금속 질화물 및 금속 탄화물 유도체들을 형성하는 증착 프로세스들을 포함한다. 일 실시예에서, 10 초과의 유전상수를 가진 유전체 물질을 증착하는 단계, 유전체 물질에 내에 피쳐 데피니션을 형성하는 단계, 피쳐 데피니션의 측벽들과 바닥에 컨포멀하게 일함수 물질을 증착하는 단계, 및 피쳐 데피니션을 충진하도록 일함수 물질 상에 금속 게이트 충진 물질을 증착하는 단계를 포함하고, 일함수 물질은 화학식(MXY)을 가진 적어도 하나의 금속-할로겐화물 전구체를 반응시킴으로써 증착되며, 여기서, M은 탄탈륨, 하프늄, 티타늄 및 란타늄이고, X는 불소, 염소, 브롬 또는 요오드로 이루어진 군으로부터 선택된 할로겐화물이며, y는 3 내지 5인, 기판 프로세싱 방법이 제공된다.

SEMICONDUCTOR DEVICE TO CONTROL DIFFUSION OF GERMANIUM AND LEAKAGE CURRENT

PURPOSE: A semiconductor device is provided to control diffusion of germanium and a leakage current by controlling the quantity of added carbon when carbon needs to be added. CONSTITUTION: A semiconductor substrate(1) is prepared. A gate insulation layer(13) is formed on the semiconductor substrate. A gate electrode(14) is formed on the gate insulation layer. The gate electrode contains germanium and cobalt having a smaller quantity than the germanium. The density of cobalt contained in the gate electrode is form 0.03 atom percent to 1.7 atom percent. © KIPO 2005 ...

HIGH TEMPERATURE ELECTRODE AND BARRIER STRUCTURE FOR FRAM AND DRAM

PURPOSE: A semiconductor structure is provided to be capable of enduring an annealing at a high temperature without damaging conductivity and perfection. CONSTITUTION: The semiconductor structure includes a substrate selected among substrates of a group of silicon, polysilicon, silicon dioxide, and silicon germanium, and an electrode located on the substrate. The electrode contains a layer of a composition of Ir-M-O. Where, M is a metal selected from one among metals of a group of Ta, Ti, Nb, Al, Hf, Zr, and V. The semiconductor structure is constructed and arranged so as to endure the annealing at a temperature of 600°C or more without damaging conductivity and perfection. © KIPO 2003 ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a first pin type transistor including a first pin, a first trench formed on the first pin, a first dielectric film formed along inner walls of the first trench, and a first work function metal film of a first conductivity type formed on the first dielectric film in the first trench; a second pin type transistor including a second pin, a second trench formed on the second pin, a second dielectric film formed along the inner walls of the second trench, and a second work function metal film of a first conductivity type formed on the second dielectric film in the second trench; and a third pin type transistor including a third pin, a third trench formed on the third pin, a third dielectric film formed along the inner walls of the third trench, and a third work function metal film of a first conductivity type formed on the third dielectric film in the third trench. The first dielectric ...

SEMICONDUCTOR DEVICE HAVING A METAL GATE CAPABLE OF IMPROVING A WORKING SPEED AND A MANUFACTURING METHOD THEREOF

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to reduce a threshold voltage by using a material which induces the work function movement of a gate electrode. CONSTITUTION: Gate insulating layers(25,34) are formed on a substrate(201). The gate insulating layer has a high dielectric constant. Gate electrodes(26,35) are formed on the gate insulating layer. Work function control films(23,33) are formed between the substrate and the gate insulating layer. The work function control film induces the work function movement of the gate electrode. COPYRIGHT KIPO 2012 ...

트렌치를 통한 선택적 게르마늄 Ｐ―컨택트 금속화

... 종래 소자에 비해 감소된 기생 컨택트 저항을 갖는 트랜지스터 소자를 형성하기 위한 기술이 개시된다. 이 기술들은, 예를 들어, 실리콘 또는 실리콘 게르마늄(SiGe) 소스/드레인 영역들 상에 예를 들어, 일련의 금속과 같은 표준 컨택트 스택을 이용하여 구현될 수 있다. 한 예시적 이러한 실시예에 따르면, 중간의 붕소 도핑된 게르마늄층이 소스/드레인과 컨택트 금속 사이에 제공되어 컨택트 저항을 상당히 줄인다. 평면 및 비평면 트랜지스터 구조(예를 들어, FinFET) 뿐만 아니라 변형된(strained) 및 변형되지 않은(unstrained) 채널 구조를 포함한, 수많은 트랜지스터 구성과 적절한 제조 프로세스가 본 개시에 비추어 명백할 것이다. 불합치 전위(misfit dislocation)를 줄이기 위해 단계화된 버퍼링이 이용될 수 있다. 기술들은 특히 p-타입 소자를 구현하기에 특히 적합하지만, 원한다면 n-타입 소자에 대해서도 이용될 수 있다.

METHOD FOR FORMING TiSiN FILM, DIFFUSION PREVENTIVE FILM COMPRISING TiSiN FILM, SEMICONDUCTOR DEVICE AND ITS PRODUCTION METHOD, AND APPARATUS FOR FORMING TiSiN FILM

A TiSiN film of a barrier metal for a semiconductor device is formed by plasma CVD or thermal CVD to prevent diffusion of Cu. When the film is formed by thermal CVD, a TiCl gas, silane gas, and an NH gas are used as the source gas. When the film is formed by plasma CVD, a TiCl gas, a silane gas, an H gas, and an N gas are used as the source gas.43422 © KIPO & WIPO 2009 ...

DUAL GATE OF A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE SAME, IMPROVING A DEVICE CHARACTERISTIC AND RELIABILITY BY IMPROVING A THRESHOLD VOLTAGE OF A PMOS AND AN NMOS

PURPOSE: A dual gate of a semiconductor device and a method for forming the same are provided to improve a threshold voltage of an NMOS and a PMOS by forming a high density doping film on a recessed semiconductor substrate. CONSTITUTION: A semiconductor substrate(100) is segmented into a cell region and a peripheral region. A gate forming area in the cell region is recessed. The peripheral region includes the PMOS and NMOS forming region. The first conductive SiGe film(106a) is formed on the cell region and the PMOS forming region. A second conductive SiGe film(106b) is formed on the NMOS forming region. A first polysilicon layer(110) is formed on the first conductive SiGe film. The second conductive polysilicon film(110b) is formed on the second conductive SiGe film. © KIPO 2009 ...

FINFET STRUCTURE AND METHOD WITH REDUCED FIN BUCKLING

Semiconductor device and manufacturing method thereof

Semiconductor device and forming method thereof

A method for fabricating semiconductor device

Semiconductor devices and methods of fabricating the same

A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

Method of fabricating semiconductor device

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

Ultra-thin Hf-doped silicon oxynitride film for high performance CMOS applications and method of manufacture

A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer.

Semiconductor device having metal gate and fabrication method thereof

A fabrication method of semiconductor device having a metal gate includes providing a substrate, successively forming a gate insulating layer and a bottom barrier layer on the surface of the substrate, forming a work function layer covering the bottom barrier layer, removing the work function layer, and forming a top barrier layer on the bottom barrier layer to directly contact to the bottom barrier layer, and forming a metal layer on the top bottom barrier layer.

Device having multiple transistors and electronic apparatus

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

Semiconductor device

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.

Tunneling field effect transistor and method of fabricating the same

Semiconductor device having metal gate and method for manufacturing semiconductor device having metal gate

Methods for fabricating integrated circuit devices

Metal gate fermi-threshold field effect transistor

A fermi-threshold field effect transistor includes a metal gate rather than a contra-doped polysilicon gate. The metal gate can lower the threshold voltage of the fermi-FET without degrading other desirable characteristics of the fermi-FET. The metal gate may be a pure metal gate or a metal alloy gate such as a metal silicide gate. The metal gate preferably includes metal having a work function between that of P-type polysilicon and N-type polysilicon.

A method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials

A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed sidewalls. Internal spacers are formed over a portion of the exposed substrate portion within the patterned layer opening on the patterned layer exposed sidewalls. The internal spacers being comprised of a WF1 material having a first work function. A planarized gate electrode body is formed within the remaining portion of the patterned layer opening and adjacent to the internal spacers. The gate electrode body being comprised of a WF2 material having a second work function. The internal spacers and the gate electrode body forming the gate electrode.

Metal carbide gate structure and method of fabrication

DOPING ALUMINUM IN TANTALUM SILICIDE

Provided are methods of providing aluminum-doped TaSix films. Doping TaSix films allows for the tuning of the work function value to make the TaSix film better suited as an N- metal for NMOS applications. One such method relates to soaking a TaSix film with an aluminum-containing compound. Another method relates to depositing a TaSix film, soaking with an aluminum-containing compound, and repeating for a thicker film. A third method relates to depositing an aluminum-doped TaSix film using tantalum, aluminum and silicon precursors.

TRANSISTOR AND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Provided are a transistor and a semiconductor device and a method for manufacturing sameThe method for manufacturing a transistor includes the steps of: determining an active region on a semiconductor substrate, forming on the active region a pseudo-gate lamination, a main side wall around the pseudo-gate lamination, and an insulation layer around the main side wall, and forming a source and drain region embedded in the active region; removing the pseudo-gate electrode in the pseudo-gate lamination to form a first concave part surrounded by the main side wall; and simultaneously filling in copper in the first concave part and a source and drain contact hole through the insulation layer to form a gate electrode and a source and drain contact.By simultaneously filling in metal copper in the gate electrode and the source and drain contact hole in a "Gate Last" structure, the series resistance of the gate electrode and the resistance of the source and drain contact hole in a "Gate Last" process ...

METHOD OF FORMING HIGH-K GATE ELECTRODE STRUCTURES AFTER TRANSISTOR FABRICATION

A sophisticated high-k metal gate electrode structure may be formed after the deposition of a first part of an interlayer dielectric material (119, 119p, 119n, 119s), thereby providing a high degree of process compatibility with conventional CMOS techniques. Thus, sophisticated strain-inducing mechanisms may be readily implemented in the overall process flow, while nevertheless avoiding any high temperature processes during the formation of the sophisticated high-k dielectric gate stack (11Op, 11On).

ANGLED IMPLANTATION FOR REMOVAL OF THIN FILM LAYERS

Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure is provided. The semiconductor structure comprises: a substrate (1); a gate dielectric layer (20) formed on the substrate; a metal gate electrode layer (30) formed on the gate dielectric layer (20); and at least one metal-containing adjusting layer (43) for adjusting a work function of the semiconductor structure, in which an interfacial layer (10) is formed between the substrate (1) and the gate dielectric layer (20), and an energy of bond between a metal atom in the metal-containing adjusting layer (43) and an oxygen atom is larger than that between an atom of materials forming the gate dielectric layer (20) or the interfacial layer (10) and an oxygen atom. Further, a method for forming the semiconductor structure is also provided.

PROGRAMMABLE FETs USING Vt-SHIFT EFFECT AND METHODS OF MANUFACTURE

Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state.

UV-ASSISTED DIELECTRIC FORMATION FOR DEVICES WITH STRAINED GERMANIUM-CONTAINING LAYERS

A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si-containing layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700°C, and exposing the Si- containing layer to oxidation radicals in an UV-assisted oxidation process to form a Si-containing dielectric layer while minimizing oxidation and strain relaxation in the underlying strained Ge-containing layer. A semiconductor device containing a substrate, a strained Ge-containing layer on the substrate, and a Si-containing dielectric layer formed on the strained Ge-containing layer is provided. The semiconductor device can further contain a gate electrode layer on the Si- containing dielectric layer or a high-k layer on the Si-containing dielectric layer and a gate electrode layer on the high-k layer.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A gate insulating film (3) is formed on a semiconductor substrate (1) provided with an NFET forming region (50N) for forming an N-type field effect transistor and a PFET forming region (50P) for forming a P-type field effect transistor. A first polysilicon film (4) is formed on the gate insulating film (3), and the gate insulating film (3) is exposed from the PFET forming region (50P) by removing a portion included in the PFET forming region of the formed first polysilicon film (4). A titanium nitride film (6) is formed on the gate insulating film (3) in the PFET forming region (50P).

METHOD FOR MAKING METAL GATE STACK STRUCTURE IN GATE FIRST PROCESS

A method for making the metal gate stack structure in gate first process is provided. After forming the conventional Local Oxidation of Silicon (LOCOS) and Shallow Trench Isolation (STI), the method comprising the following steps: growing a ultra-thin interfacial oxide or a nitrogen oxide layer on a semiconductor substrate using rapid thermal oxidation or chemical method; depositing a high dielectric constant (K) gate dielectric on the ultra-thin interfacial oxide layer, rapid thermal annealing after the deposition of the high K gate dielectric; depositing a TiN metal gate; depositing a AlN or TaN barrier layer; depositing a polysilicon (1) film and a SiO2 hard mask (2), and then carrying out the lithography and the etching of the SiO2 hard mask (2); and after removing the glue, etching the polysilicon (1) film/metal gate/high K gate dielectric layer in turn to form the metal gate stack structure. The method is suitable for the need of the high K gate dielectric/metal gate integration in ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and manufacturing method thereof are provided. The semiconductor device includes: a semiconductor substrate (10); a first semiconductor layer formed on the said semiconductor substrate (10), and a second semiconductor layer formed around the said first semiconductor layer; a high-k gate dielectric layer (28) and gate conductor (29) formed on the said first semiconductor layer; source / drain regions formed on the said second semiconductor layer; wherein the side walls of the first semiconductor layer and the second semiconductor layer are sloping contacts. The semiconductor device can take advantage of high mobility of the channel region to provide high output current and high operating speed while reducing power consumption.

NANO-PILLAR TRANSISTOR FABRICATION AND USE

A field effect nano-pillar transistor has a pillar shaped gate element incorporating a biomimitec portion that provides various advantages over prior art devices. The small size of the nano-pillar transistor allows for advantageous insertion into cellular membranes, and the biomimitec character of the gate element operates as an advantageous interface for sensing small amplitude voltages such as transmembrane cell potentials. The nano-pillar transistor can be used in various embodiments to stimulate cells, to measure cell response, or to perform a combination of both actions.

Fin-type field effect transistor structure and manufacturing method thereof

A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

Selective germanium P-contact metalization through trench

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Silicon germanium fin channel formation

A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

Fabrication of devices having different interfacial oxide thickness via lateral oxidation

A method for forming a semiconductor device includes forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer; encapsulating the first interfacial oxide layer of the first FET; and performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide.

Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS

A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.

Inversion thickness reduction in high-k gate stacks formed by replacement gate processes

A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (); and forming a metal gate material over the high-k dielectric layer.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a gate insulating film formed on a silicon substrate, a gate electrode formed on the gate insulating film, and an electrical insulating film formed on the gate electrode. The electrical insulating film includes a N—H bond and substantially no Si—H bond. The electrical insulating film is formed by using tetrachlorosilane (SiCl4) that contains no hydrogen (H) as a source gas for a silicon nitride film. Thus, the semiconductor device can suppress residual hydrogen in the gate insulating film and prevent interface defects of the gate insulating film, a shift in the threshold voltage of a transistor, and the degradation of an on-state current. A method for manufacturing the semiconductor device also is provided.

Gate electrodes and matrix lines made of W/Ta alloy for LCD apparatus

A conductive material comprises a tungsten and tantalum alloy including approximately 1 to 5 atm percent of tantalum.

Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions

A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.

FinFET complementary metal-oxide-semiconductor (CMOS) devices

A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.

High performance MOSFET comprising stressed phase change material

The present invention relates to semiconductor devices that each comprises at least one field effect transistor (FET) containing an intrinsically stressed phase change material layer. The intrinsically stressed phase change material layer is arranged and constructed for creating stress in the channel region of the FET. Preferably, the intrinsically stressed phase change material layer is deposited over the channel region of the FET. For an n-channel FET, the intrinsically stressed phase change material layer preferably contains intrinsic compressive stress that is created by phase change, for example, from a polycrystalline phase to an amorphous phase. Alternatively, for a p-channel FET, the intrinsically stressed phase change material layer preferably contains intrinsic tensile stress that is created by phase change, for example, from an amorphous phase to a polycrystalline phase.

interconnection structure for n/p metal gates

The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

Method of manufacturing semiconductor device using acid diffusion

A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate.

Differential stoichiometries by infusion thru gcib for multiple work function metal gate cmos

A method of modulating the work function of a metal layer in a localized manner is provided. Metal gate electrodes having multiple work functions may then be formed from this metal layer. Although the metal layer and metal gate electrodes over both the nFET and pFET regions of the instant substrates are made from only a single metal, they exhibit different electrical performances. The variation of electrical performances is achieved by infusing stoichiometrically-altering atoms into the metal layer, from which the metal gate electrodes are made, via a Gas Cluster Ion Beam process. The resulting metal gate electrodes have the necessary threshold voltages for both nFET and pFET, and are ideal for use in CMOS devices.

Method and structure for forming high-k/metal gate extremely thin semiconductor on insulator device

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Semiconductor device manufacturing method

A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the semiconductor substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the semiconductor substrate on the surface of the semiconductor substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into a insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the semiconductor substrate, and oxygen.

Semiconductor device production method

A semiconductor device production method includes: forming a gate insulating film on the p-type region of a semiconductor substrate; forming a first aluminum oxide film with an oxygen content lower than stoichiometric composition on the gate insulating film; forming a tantalum-nitrogen-containing film that contains tantalum and nitrogen on the first aluminum oxide film; forming an electrically conductive film on the tantalum-nitrogen-containing film; patterning the electrically conductive film to form a gate electrode; injecting n-type impurities into the p-type region using the gate electrode as a mask; and carrying out heat treatment after the formation of the tantalum-nitrogen-containing film.

Method for manufacturing semiconductor device

Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.

Strained structure of a p-type field effect transistor

In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity

Replacement Gate Having Work Function at Valence Band Edge

Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

Methods of fabricating a semiconductor device including metal gate electrodes

A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

Semiconductor device

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.

Semiconductor device having insulated gate field effect transistors and method of manufacturing the same

N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion of the silicon containing film is thinned in the thickness direction. N-type impurities are introduced into a second portion of the silicon containing film above the P-type semiconductor region. A mask is provided on the silicon containing film. The first and second portions of the silicon containing film are etched together using the mask as an etching mask to form gate electrode films above the N-type and P-type semiconductor regions respectively. P-type and N-type impurities are introduced into the N-type and P-type semiconductor regions to form P-type and N-type source and drain layers.

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same are disclosed. A method for forming a semiconductor device includes forming a trench by etching a semiconductor substrate, forming a barrier metal layer having a thickness of 100 Å or less over a surface of the trench, forming a nucleation layer over the barrier metal layer, configured to include a β-tungsten (β-W) structure, and forming a bulk layer over the nucleation layer so as to bury the bottom of the trench. As a result, resistivity can be reduced and a stable-phase barrier metal layer can be obtained. In addition, productivity is improved so that gate resistance is prevented from increasing.

Semiconductor device and method of manufacturing the same

A gate insulating film is formed on a main surface of a substrate in which an element isolation region is formed. A metal film is formed on the gate insulating film. A silicon film is formed on the metal film. A gate electrode of a MIS transistor composed of a stacked structure of the silicon film and metal film is formed on an element region and a high-resistance element composed of a stacked structure of the silicon film and metal film is formed on the element isolation region by patterning the silicon film and metal film. An acid-resistant insulating film is formed on the side of the gate electrode. The metal film of the high-resistance element is oxidized. A diffused layer of the MIS transistor is formed in the substrate.

Semiconductor device

A source region and a drain region are disposed in a substrate. A gate insulating film is disposed on the substrate. A gate electrode is disposed on the gate insulating film. The gate electrode may include a first gate portion adjacent to the source region and a second gate portion adjacent to the drain region. The first and second gate portions have different work functions from each other.

Replacement gate with reduced gate leakage current

Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

High-k/metal gate stack using capping layer methods, ic and related transistors

Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, and Process to Fabricate Same

A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer, selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure.

Semiconductor device and method of manufacturing the same, and power supply apparatus

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

Sealing structure for high-k metal gate and method of making

The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Semiconductor device and method of manufacturing the same

A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.

Semiconductor device and method of manufacturing the same

A p-type MIS transistor Qp arranged in a pMIS region Rp of a silicon substrate 1 includes a pMIS gate electrode GEp formed so as to interpose a pMIS gate insulating film GIp formed of a first insulating film z 1 and a first high-dielectric film hk 1 , and an n-type MIS transistor Qn arranged in an nMIS region Rn includes an nMIS gate electrode GEn formed so as to interpose an nMIS gate insulating film GIn formed of a first insulating film z 1 and a second high-dielectric film hk 2. The first high-dielectric film hk 1 is formed of an insulating film mainly made of hafnium and oxygen with containing aluminum, titanium, or tantalum. Also, the second high-dielectric film hk 2 is formed of an insulating film mainly made of hafnium, silicon, and oxygen with containing an element of any of group Ia, group IIa, and group IIIa.

Semiconductor device exhibiting reduced parasitics and method for making same

A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.

Semiconductor device and method of manufacturing the same

A semiconductor device having a buried gate is provided. The semiconductor device is formed in a structure in which a plurality of contacts having small step differences are stacked without forming a metal contact applying an operation voltage to the buried gate in a single contact and a contact pad is formed between the contacts so that failure due to misalignment can be prevented without a separate additional process for forming the contacts.

Preserving stress benefits of uv curing in replacement gate transistor fabrication

A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.

Transistor, Semiconductor Device, and Method for Manufacturing the Same

The invention provides a transistor, a semiconductor device and a method for manufacturing the same. The method for manufacturing a transistor comprises: defining an active area on a semiconductor substrate, forming a dummy gate stack on the active area, primary spacers surrounding said dummy gate stack, and an insulating layer surrounding said primary spacers, and forming source/drain regions embedded in said active area; removing the dummy gate in said dummy gate stack to form a first recessed portion surrounded by the primary spacers; filling Cu simultaneously in said first recessed portion and in the source/drain contact holes penetrating said insulating layer to form a gate and source/drain contacts. By filling the gate and the source/drain contact holes with the metal Cu simultaneously in the Gate Last structure, the gate serial resistance and the source/drain contact holes resistance in the Gate Last process are decreased. Besides, the effect of metal filling is improved in small scale, and the process complexity and difficulty is efficiently decreased.

Gate dielectric of semiconductor device

A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described.

Manufacturing method for metal gate

A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the polysilicon layer, forming a patterned hard mask on the protecting layer, performing a first etching process to etch the protecting layer and the polysilicon layer to form a dummy gate having a first height on the substrate, forming a multilayered dielectric structure covering the patterned hard mask and the dummy gate, removing the dummy gate to form a gate trench on the substrate, and forming a metal gate having a second height in the gate trench. The second height of the metal gate is substantially equal to the first height of the dummy gate.

Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET

A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T inv and V t of the pFET, while scaling Tiny and maintaining Vt for the nFET, resulting in the V t of the pFET becoming closer to the V t of a similarly constructed nFET with scaled T inv values.

Mosfet gate electrode employing arsenic-doped silicon-germanium alloy layer

A stack of a gate dielectric layer, a metallic material layer, an amorphous silicon-germanium alloy layer, and an amorphous silicon layer is deposited on a semiconductor substrate. In one embodiment, the amorphous silicon-germanium alloy layer is deposited as an in-situ amorphous arsenic-doped silicon-germanium alloy layer. In another embodiment, the amorphous silicon-germanium alloy layer is deposited as intrinsic semiconductor material layer, and arsenic is subsequently implanted into the amorphous silicon-germanium alloy layer. The stack is patterned and annealed to form a gate electrode.

Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure

Disclosed herein are various methods of forming metal-containing insulating material regions on a metal layer of a gate structure of a semiconductor device. In one example, the method includes forming a gate structure of a transistor, the gate structure comprising at least a first metal layer, and forming a first metal-containing insulating material region in the first metal layer by performing a gas cluster ion beam process using to implant gas molecules into the first metal layer.

Buried Gate Transistor

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Nonvolatile memory device and method of manufacturing the same

A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device uses an aluminum alloy, rather than aluminum, for a metal gate. Therefore, the surface of the high-k metal gate after the CMP is aluminum alloy rather than pure aluminum, which can greatly reduce defects, such as corrosion, pits and damage, in the metal gate and improve reliability of the semiconductor device.

Semiconductor structure and process thereof

A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.

Transistor Performance Improving Method with Metal Gate

The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

Metal gate features of semiconductor die

A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio.

Integrated high-k/metal gate in cmos process flow

A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.

Self-aligned contacts

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Atomic Layer Deposition Methods For Metal Gate Electrodes

Provided are devices and methods utilizing TiN and/or TaN films doped with Si, Al, Ga, Ge, In and/or Hf. Such films may be used as a high-k dielectric cap layer, PMOS work function layer, aluminum barrier layer, and/or fluorine barrier. These TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TiInN, TaInN, TiHfN or TaHfN films can be used where TiN and/or TaN films are traditionally used, or they may be used in conjunction with TiN and/or TaN. 1. An integrated circuit transistor device comprising:a high-k dielectric layer disposed over a channel; anda metal nitride layer over the high-k dielectric layer, the metal nitride layer selected from TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TiInN, TaInN, TiHfN and TaHfN.2. The integrated circuit transistor device of claim 1 , wherein the metal nitride layer is in contact with the high-k dielectric layer.3. The integrated circuit transistor device of claim 1 , further comprising one or more intermediate layers between the high-k dielectric layer and the metal nitride layer.4. The integrated circuit transistor device of claim 1 , wherein a layer comprising aluminum overlies the metal nitride film.5. The integrated circuit transistor device of claim 1 , wherein the metal nitride layer is formed by atomic layer deposition and has a thickness having a range of about 2 Angstroms to about 200 Angstroms.6. The integrated circuit transistor device of claim 5 , wherein the metal nitride layer has a thickness having a range of about 5 Angstroms to about 100 Angstroms.7. The integrated circuit transistor device of claim 6 , wherein the metal nitride layer comprises TiSiN.8. A method of forming an integrated circuit transistor device with a metal gate claim 6 , the method comprising:providing a substrate comprising a high-k dielectric layer; andexposing the substrate to a first precursor comprising Ti or Ta, a second precursor comprising an ammonia source, and a third precursor comprising a Si, Al, Ga, Ge, In or Hf ...

Methods of Fabricating Semiconductor Devices and Structures Thereof

Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

Method of hybrid high-k/metal-gate stack fabrication

A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.

Semiconductor process

A semiconductor process includes the following steps. A substrate having a first area and a second area is provided. A thick oxide layer and a dummy gate layer are formed on the substrate and in the first area and the second area. The dummy gate layer is removed to expose the thick oxide layer. The thick oxide layer in the first area is removed and then a thinner oxide layer is formed in the first area; or, the thick oxide layer in the first area is thinned down and a thinner oxide layer is therefore formed.

Metal gate semiconductor device

Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer.

Cost-Effective Gate Replacement Process

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

Replacement gate structures for semiconductor devices

The present disclosure is generally directed to various replacement gate structures for semiconductor devices. One illustrative gate structure disclosed herein includes, among other things, a gate insulation layer and a layer of gate electrode material with a substantially horizontal portion having a first thickness and a substantially vertical portion having a second thickness that is less than the first thickness. Furthermore, the substantially horizontal portion of the layer of gate electrode material is positioned adjacent to a bottom of the replacement gate structure and above at least a portion of the gate insulation layer, and the substantially vertical portion is positioned adjacent to sidewalls of the replacement gate structure.

Display device

Disclosed is a display device and an electronic apparatus incorporating the display device. The display device includes a transistor and a planarization film over the transistor. The planarization film has an opening where an edge portion is rounded. The display device further includes a first electrode over the planarization film and an organic resin film over the first electrode. The organic resin film also has an opening where an edge portion is rounded. The organic resin film is located in the opening of the planarization film. The first electrode and the transistor are electrically connected to each other through a conductive film. The first electrode is in contact with a top surface of the conductive film. Over the first electrode, a light-emitting member and a second electrode are provided.

Semiconductor device and manufacturing method

A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.

Semiconductor device and method for manufacturing the same

The present invention discloses a semiconductor device, comprising a substrate, a gate stack structure on the substrate, a gate spacer structure at both sides of the gate stack structure, source/drain regions in the substrate and at opposite sides of the gate stack structure and the gate spacer structure, characterized in that the gate spacer structure comprises at least one gate spacer void filled with air. In accordance with the semiconductor device and the method for manufacturing the same of the present invention, carbon-based materials are used to form a sacrificial spacer, and at least one air void is formed after removing the sacrificial spacer, the overall dielectric constant of the spacer is effectively reduced. Thus, the gate parasitic capacitance is reduced and the device performance is enhanced.

Semiconductor device having metal gate and manufacturing method thereof

A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

Methods of atomic layer deposition of hafnium oxide / erbium oxide bi-layer as advanced gate dielectrics

Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen diffusion, which can lead to increasing an effective oxide thickness of the gate dielectric and preventing hafnium-silicon reactions that may lead to higher leakage current.

Transistor of semiconductor device and method for manufacturing the same

Provided are a transistor of a semiconductor device and a method for manufacturing the same. A gate induced drain leakage (GIDL) current is reduced by decreasing a work function at an upper portion of a gate electrode, and a threshold voltage of the transistor is maintained by maintaining a work function at a lower portion of the gate electrode at a high level, thereby reducing a leakage current of the transistor and reducing a read time and a write time of the semiconductor device. The transistor of the semiconductor device includes: a recess with a predetermined depth in a semiconductor substrate; a first gate electrode disposed within the recess; and a second gate electrode disposed on the first gate electrode into which ions of one or more of nitrogen (N), oxygen (O), arsenic (As), aluminum (Al), and hydrogen (H) are doped.

Methods to stop contact metal from extruding into replacement gates

A method of preventing contact metal from protruding into neighboring gate devices to affect work functions of the neighboring gate devices is provided includes forming a gate structure. Forming the gate structure includes forming a work function layer, and forming a gate metal layer having a void, wherein the work function layer surrounds the gate metal layer. The method further includes forming a contact plug having a contact metal directly on the gate metal layer of the first gate stack, wherein the contact metal protrudes into the void, and the work function layer prevents the contact metal from protruding into a second gate stack.

Preventing fully silicided formation in high-k metal gate processing

A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.

Semiconductor device and method of manufacturing the same

The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first metal gate electrode provided in a NMOS region of a substrate; and a second metal gate electrode provided in a PMOS region of the substrate, wherein the first and second metal gate electrodes may be formed of TiN material or TiAlN material. Here, the first metal gate electrode may have a higher titanium (Ti) content than the second metal gate electrode, and the second metal gate electrode may have a higher nitrogen (N) content than the first metal gate electrode.

Metal gate electrode of a field effect transistor

A method of fabricating a metal gate electrode of a field effect transistor includes forming a dielectric layer over an active region, and forming an opening in the dielectric layer. The method further includes partially filling the opening with a high-dielectric-constant material, partially filling the opening with a conformal first metal material over the high-dielectric-constant material, and filling the opening with a capping layer over the first metal material. The method further includes partially removing the first metal material and capping layer in the opening using a wet etching process. The method further includes fully removing the remaining capping layer in the opening using a wet etching process. The method further includes depositing a second metal material in the opening over the remaining first metal material, and planarizing the second metal material.

Integrated circuit and method for fabricating the same having a replacement gate structure

A method for fabricating an integrated circuit includes forming a first layer of a workfunction material in a first trench of a plurality of trench structures formed over a silicon substrate, the first trench having a first length and forming a second layer of a workfunction material in a second trench, the second trench having a second length that is longer than the first length. The method further includes depositing a low-resistance fill material onto the integrated circuit to fill any unfilled trenches with the low-resistance fill material and etching the low resistance fill material, the first layer, and the second layer to re-expose a portion of each trench of the plurality of trenches, while leaving a portion of each of the first layer, the second layer, and the low-resistance fill material in place. Still further, the method includes depositing a gate fill material into each re-exposed trench portion.

Finfet device with a graphene gate electrode and methods of forming same

One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.

Gate Structure, Semiconductor Device and Methods for Forming the Same

The disclosure relates to a gate structure, a semiconductor device and methods for forming the same. An embodiment of the disclosure provides a method for forming a gate structure, including: providing a substrate; forming an interface layer on the substrate; forming a gate dielectric layer on the interface layer; forming a gate dielectric capping layer on the gate dielectric layer; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming an oxygen scavenging element capping layer on the oxygen scavenging element layer; performing Post-Metallization Annealing; performing etching until the etching stop layer is exposed; forming a work function adjustment layer on the etching stop layer; and forming a gate layer on the work function adjustment layer. 1. A method for forming a gate structure , comprising:providing a substrate;forming an interface layer on the substrate;forming a gate dielectric layer on the interface layer;forming a gate dielectric capping layer on the gate dielectric layer;forming an etching stop layer on the gate dielectric capping layer;forming an oxygen scavenging element layer on the etching stop layer;forming an oxygen scavenging element capping layer on the oxygen scavenging element layer;performing Post-Metallization Annealing;performing etching until the etching stop layer is exposed;forming a work function adjustment layer on the etching stop layer; andforming a gate layer on the work function adjustment layer.2. The method according to claim 1 , wherein the gate dielectric capping layer comprises a material of TiN claim 1 , and has a thickness of 1 nm to 3 nm.3. The method according to claim 1 , wherein the etching stop layer comprises a material of TaN claim 1 , and has a thickness of 1 nm to 8 nm.4. The method according to claim 1 , wherein the oxygen scavenging element layer comprises a material of Ti claim 1 , and has a thickness of 5 Å to 5 nm.5. ...

Metal semiconductor alloy contact with low resistance

A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Method of manufacturing device having a blocking structure

A method of manufacturing a semiconductor device, and the method includes forming a stack of a work function layer, a blocking structure, and a metal cap layer sequentially on a substrate. The forming of the blocking structure includes sequentially depositing at least a metal diffusion prevention layer over the work function layer and an electrical performance enhancement layer over the metal diffusion prevention layer before forming the metal cap layer. The electrical performance enhancement layer includes a TiN layer having a Ti/N ratio greater than 1.

Insulated gate bipolar transistor structure having low substrate leakage

A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Semiconductor devices having a diffusion barrier layer and methods of manufacturing the same

Methods of manufacturing a semiconductor device include forming a gate insulation layer including a high-k dielectric material on a substrate that is divided into a first region and a second region; forming a diffusion barrier layer including a first metal on a second portion of the gate insulation layer in the second region; forming a diffusion layer on the gate insulation layer and the diffusion barrier layer; and diffusing an element of the diffusion layer into a first portion of the gate insulation layer in the first region.

High-k transistors with low threshold voltage

An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.

Replacement gate electrode with planar work function material layers

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

Semiconductor device having tungsten gate electrode and method for fabricating the same

The present invention provides a semiconductor device in which the threshold voltage of NMOS and the threshold voltage of PMOS are independently controllable, and a method for fabricating the same. The method includes: forming a gate insulating film over an NMOS region and a PMOS region of a semiconductor substrate; forming a carbon-containing tungsten over the gate insulating film formed over one of the NMOS region and the PMOS region; forming a carbon-containing tungsten nitride over the gate insulating film formed over the other one of the PMOS region or the NMOS region; forming a tungsten film over the carbon-containing tungsten and the carbon-containing tungsten nitride; post-annealing the carbon-containing tungsten and the carbon-containing tungsten nitride; and etching the tungsten film, the carbon-containing tungsten, and the carbon-containing tungsten nitride, to form a gate electrode in the NMOS region and the PMOS region

SEMICONDUCTOR DEVICE INCLUDING GRADED GATE STACK, RELATED METHOD AND DESIGN STRUCTURE

A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region. 1. A semiconductor device comprising:a substrate; and a graded region with a varied material concentration profile; and', 'a metal layer disposed on the graded region., 'a gate structure disposed directly on the substrate, the gate structure including2. The semiconductor device of claim 1 , wherein the graded region includes a first portion proximate the substrate and a second portion proximate the metal layer claim 1 , the first portion comprising substantially silicon and the second portion comprising substantially metal.3. The semiconductor device of claim 1 , wherein the graded region contains at least one of aluminum (Al) claim 1 , magnesium (Mg) claim 1 , lanthanum (La) claim 1 , aluminum oxide (AlO) claim 1 , lanthanum oxide (LaO) claim 1 , and zirconium oxide (ZrO).4. The semiconductor device of claim 1 , wherein a concentration of each material in the graded region varies linearly.5. The semiconductor device of claim 1 , wherein a concentration of each material in the graded region varies exponentially.6. The semiconductor device of claim 1 , wherein the graded region includes a plurality of films claim 1 , the plurality of films having a varied material composition relative one another.7. A design structure tangibly embodied in a machine readable medium for design claim 1 , manufacturing claim 1 , or testing a semiconductor device claim 1 , the design structure comprising:a substrate; and a graded region with a varied material concentration profile; and', 'a metal layer disposed on the graded region., 'a gate structure disposed directly on the substrate, the gate structure including8. The design structure of claim 7 , wherein the graded region includes a first portion proximate ...

Integrated circuits with improved gate uniformity and methods for fabricating same

Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.

Semiconductor structure with integrated passive structures

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

INTEGRATED CIRCUIT METAL GATE STRUCTURE

A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer. 1. A semiconductor device , comprising:a gate dielectric layer; a first metal layer, wherein the first metal layer includes an oxygen-gettering composition;', 'a second metal layer adjacent the first metal layer, wherein the second metal layer includes oxygen;', 'a third metal layer on the second metal layer; and, 'a gate electrode formed on the gate dielectric layer, wherein the gate electrode includesa polysilicon layer, wherein the third metal layer includes an interface with the polysilicon layer.2. The device of claim 1 , wherein the first metal layer includes a thickness between approximately 1 and 5 angstroms claim 1 , wherein the second metal layer includes a thickness between approximately 1 and 5 angstroms and wherein the third metal layer includes a thickness between approximately 1 and 15 angstroms.3. The device of claim 1 , wherein the first metal layer is selected from the group consisting of Ta-rich TaC claim 1 , Ti-rich TiN claim 1 , Ti-rich TiSiN claim 1 , and combinations thereof.4. The device of claim 1 , wherein the second metal layer is selected from the group consisting of C-rich TaCO claim 1 , C-rich TaCNO claim 1 , and combinations thereof.5. The device of claim 1 , wherein the first metal layer is selected from the group consisting of Ta-rich TaC claim 1 , Ti-rich TiN claim 1 , Ti-rich TiSiN claim 1 , and combinations thereof and the second metal layer is selected from the group consisting of C-rich TaCO claim 1 , C-rich TaCNO claim 1 , and combinations thereof.6. The device of claim 1 , wherein the third metal layer is selected from the group consisting of N-rich ...

Method for manufacturing a semiconductor device

A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.

FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION

An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor. 2. The semiconductor structure of claim 1 , wherein the first barrier layer is also disposed on the sidewalls.3. The semiconductor structure of claim 1 , wherein the cavity has a width ranging from about 20 nanometers to about 40 nanometers.4. The semiconductor structure of claim 1 , wherein the first barrier layer is comprised of TiN.5. The semiconductor structure of claim 4 , wherein the second barrier layer is comprised of TaN.6. The semiconductor structure of claim 1 , wherein the second metal layer is in direct physical contact with sidewalls the first barrier layer.7. The semiconductor structure of claim 1 , wherein the first barrier layer is flush with a base portion of the second barrier layer. This application is a divisional of, and claims the benefit of, co-pending and co-owned U.S. patent application Ser. No. 13/607,954, filed Sep. 10, 2012, having attorney docket number DU184, the entire contents of which are herein incorporated by reference.1. Technical FieldThe present invention relates generally to semiconductor fabrication, and more particularly, to an improved replacement metal gate of a field effect transistor and method of fabrication.2. Related ArtComplimentary metal-oxide-silicon (CMOS) technology is used in many integrated circuits. CMOS technology utilizes n-channel metal-oxide-silicon field effect transistors (n-MOSFETs) often shortened to NFETs and p-channel metal-oxide-silicon field effect transistors (p-MOSFETs) often shortened to PFETs. Conventional NFETs and PFETs are well known in the art and comprise a ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included. 1. (canceled)2. A semiconductor device comprising:a gate electrode;a first insulating layer over the gate electrode;an oxide semiconductor layer over the first insulating layer;a first conductive layer over and in direct contact with the oxide semiconductor layer;a second conductive layer over and in direct contact with the oxide semiconductor layer;a metal layer over and in direct contact with the first conductive layer;a second insulating layer comprising silicon nitride over the first conductive layer, the second conductive layer, and the metal layer; anda pixel electrode over the second insulating layer,wherein a light transmittance of the first conductive layer is higher than a light transmittance of the metal layer,wherein each of the first conductive layer and the second conductive layer is an oxide layer comprising indium and zinc,wherein the metal layer comprises copper, andwherein the first conductive layer comprises a region in which the first conductive layer and the metal layer do not overlap with each other.3. The semiconductor device according to claim 2 , wherein the pixel electrode is electrically connected with the second conductive layer through a contact hole in the second insulating layer.4. The semiconductor device according to claim 2 , wherein the oxide ...

SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body. 1. An integrated circuit structure , comprising:a semiconductor body having a semiconductor channel, the semiconductor channel having a first side opposite a second side;a gate electrode over the semiconductor body, the gate electrode comprising a first gate electrode portion proximate the first side of the semiconductor channel, and the gate electrode comprising a second gate electrode portion proximate the second side of the semiconductor channel, the second gate electrode portion in alignment with the first gate electrode portion, wherein the semiconductor channel has a first width at a first location between the first gate electrode portion and the second gate electrode portion, and wherein the semiconductor channel has a second width at a second location between the first gate electrode portion and the second gate electrode portion, the second width different than the first width;a source or drain region adjacent to the semiconductor channel;a first sidewall spacer portion proximate a first portion of the source or drain region and proximate the first gate electrode portion;a second sidewall spacer portion proximate the first portion of the source or drain region and proximate ...

METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF

A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer. 1. A first and second metal gate process , comprising:providing a substrate;forming a gate dielectric layer on the substrate;forming a barrier layer on the gate dielectric layer;forming a first work function metal layer on a part of the barrier layer;forming a titanium aluminum metal layer on the barrier layer and the first work function metal layer for serving as a second work function layer; andforming a titanium aluminum nitride metal layer having a U-shaped profile structure in-situ directly on the titanium aluminum metal layer, so that the first metal gate structure comprises the gate dielectric layer, the barrier layer, the first work function metal layer, the second work function metal layer and the titanium aluminum nitride metal layer, and the second metal gate structure comprises the gate dielectric layer, the barrier layer, the second work function metal layer and the titanium aluminum nitride metal layer.2. The metal gate process according to claim 1 , wherein forming the titanium aluminum metal layer in-situ comprises performing a Physical Vapor Deposition (PVD) process.3. The metal gate process according to claim 2 , wherein the target of the Physical Vapor Deposition (PVD) process comprises a titanium aluminum target.4. The metal gate process according to claim 2 , wherein the target of the Physical Vapor Deposition (PVD) process comprises an aluminum target and a titanium target.5. The metal gate process according to claim 1 , wherein forming the titanium aluminum nitride metal layer in-situ comprises importing nitrogen gas into the surface of the titanium aluminum metal layer claim 1 , to transform the titanium aluminum metal layer ...

Semiconductor Device with Split Work Functions

A field effect transistor (FET) configuration is provided having a gate region with a split work function for the source-side and drain-side of the gate region. The work function of a material is defined as the minimum energy required to extract an electron from the surface of the material to free space. Accordingly, the source-side portion of the gate region has a first work function that less than a second work function of the drain-side portion, the result of which is increased breakdown voltage at the drain-gate interface, without significantly increasing the threshold voltage of the FET. The split work function is achieved by layering n-type gate material over p-type gate material in the drain-side portion of the gate region, while only the n-type gate material us used in the source-side portion of the gate region. 1. A transistor , comprising:a source region;a drain region;a channel region formed between the source region and the drain region;a gate electrode having a source-side portion and a drain-side portion, wherein a first work function of the source-side portion is less than a second work function of the drain-side portion; anda gate dielectric layer comprising a horizontal portion, wherein the horizontal portion is disposed between the gate electrode and the channel region.2. The transistor of claim 1 , wherein the source region comprises a heavily doped source region and a lightly-doped source (LDS) region and the LDS region is formed between the heavily doped source region and the channel region claim 1 , andwherein the drain region comprises a heavily doped drain region and a lightly-doped drain (LDD) region and the LDD region is formed between the heavily doped drain region and the channel region.3. The transistor of claim 2 , further comprising:a source-side spacer and a drain-side spacer;wherein the gate dielectric layer further comprises a first vertical portion interposed between the source-side spacer and the gate electrode and a second ...

FIN FIELD EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF

In accordance with various embodiments of the disclosed subject matter, a fin field effect transistor and a fabricating method thereof are provided. In some embodiments, the method comprises: providing a semiconductor substrate including a fin part protruded above a surface of the semiconductor substrate; forming a metal sulfide layer on the semiconductor substrate, and across the top and side walls of the fin part, wherein the metal sulfide layer is used as a channel region of the fin field effect transistor; forming a first gate electrode structure on the metal sulfide layer and across the top and side walls of the fin part; and forming a source electrode layer and a drain electrode layer on both sides of the first gate structure respectively. 1. A method for forming a fin field effect transistor , comprising:providing a semiconductor substrate including a fin part protruded above a surface of the semiconductor substrate;forming a metal sulfide layer on the semiconductor substrate, and across the top and side walls of the fin part, wherein the metal sulfide layer is used as a channel region of the fin field effect transistor;forming a first gate electrode structure on the metal sulfide layer and across the top and side walls of the fin part; andforming a source electrode layer and a drain electrode layer on both sides of the first gate structure respectively.2. The method of claim 1 , wherein a material of the metal sulfide layer is selected form MoS claim 1 , WS claim 1 , MoSe claim 1 , WSe claim 1 , MoTe claim 1 , WTeand a combination thereof.3. The method of claim 1 , wherein the metal sulfide layer is formed by using one of an atomic layer deposition process claim 1 , an atomic layer epitaxy process claim 1 , a metal organic chemical vapor deposition process claim 1 , and a spin-coating process.4. The method of claim 3 , wherein the spin-coating process comprises:providing a hydrazine-based solution containing a metal and a chalcogen used for forming the metal ...

SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE USING THE DISPLAY DEVICE

Provided is a semiconductor device with high capacitance while the aperture ratio is increased or a semiconductor device whose manufacturing cost is low. The semiconductor device includes a transistor, a first insulating film, and a capacitor including a second insulating film between a pair of electrodes. The transistor includes a gate electrode, a gate insulating film in contact with the gate electrode, a first oxide semiconductor film overlapping with the gate electrode, and a source electrode and a drain electrode electrically connected to the first oxide semiconductor film. One of the pair of electrodes of the capacitor includes a second oxide semiconductor film. The first insulating film is over the first oxide semiconductor film. The second insulating film is over the second oxide semiconductor film so that the second oxide semiconductor film is between the first insulating film and the second insulating film. 1. A liquid crystal display device comprising:a first oxide semiconductor layer;a gate electrode overlapping the first oxide semiconductor layer with a first insulating film interposed between the gate electrode and the first oxide semiconductor layer;a second oxide semiconductor layer overlapping the first oxide semiconductor layer with a second insulating film interposed between the first oxide semiconductor layer and the second oxide semiconductor layer;a pixel electrode electrically connected to the first oxide semiconductor layer; anda common electrode including a slit over the pixel electrode,wherein the second oxide semiconductor layer includes a region overlapping the gate electrode with the second insulating film, the first oxide semiconductor layer, and the first insulating film interposed between the second oxide semiconductor layer and the gate electrode, andwherein the slit includes a region overlapping the pixel electrode and a region not overlapping the pixel electrode.2. The liquid crystal display device according to claim 1 , wherein ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a method for manufacturing a semiconductor device whose electric characteristics are prevented from being varied and whose reliability is improved. In the method, an insulating film is formed over an oxide semiconductor film, a buffer film is formed over the insulating film, oxygen is added to the buffer film and the insulating film, a conductive film is formed over the buffer film to which oxygen is added, and an impurity element is added to the oxide semiconductor film using the conductive film as a mask. An insulating film containing hydrogen and overlapping with the oxide semiconductor film may be formed after the impurity element is added to the oxide semiconductor film. 1. (canceled)2. A method for manufacturing a semiconductor device including a transistor comprises:forming an oxide semiconductor film;forming a first insulating film over the oxide semiconductor film;forming a metal oxide film over and in contact with the first insulating film;performing a heat treatment after forming the metal oxide film;forming a conductive film over the metal oxide film after performing the heat treatment; andforming a second insulating film over the conductive film,wherein a top surface of the oxide semiconductor film comprises a first region, a second region, and a third region between the first region and the second region,wherein each of the first region and the second region is in contact with the second insulating film,wherein the conductive film overlaps with the third region with the first insulating film and the metal oxide film therebetween,wherein the second insulating film comprises hydrogen, andwherein the metal oxide film and the conductive film are collectively configured to be a gate electrode of a transistor.3. The method for manufacturing a semiconductor device according to claim 2 ,wherein the metal oxide film comprises at least one of indium, gallium, zinc, and oxygen.4. The method for manufacturing a semiconductor device according to claim 2 ...

FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS

Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions. 1. A semiconductor structure comprising:a first gate dielectric straddling a first semiconductor material portion and containing a stack of an adjustment oxide layer including a silicate of a metal selected from alkaline earth metals, Group IIIB elements, and rare earth metals and a first high dielectric constant (high-k) gate dielectric including a dielectric metal oxide and having a dielectric constant greater than 8.0;a first gate electrode in contact with said first gate dielectric and containing a first metallic material layer in contact with said first high-k gate dielectric;a second gate electrode straddling a second semiconductor material portion and containing a stack of a semiconductor oxide layer and a second high-k gate dielectric, wherein said first high-k gate dielectric differs in composition from said second high-k gate dielectric by presence of oxygen deficiency in said first high-k gate dielectric; anda second gate electrode in contact with said second gate dielectric and containing a second metallic material layer in contact with ...

INTEGRATED METAL GATE CMOS DEVICES

A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region. 1. A method for forming semiconductor devices , the method comprising:forming a first channel region, a second channel region, a third channel region, and a fourth channel region on a substrate;forming a first metal layer on the first channel region, the second channel region, the third channel region, and the fourth channel region;forming a sacrificial block layer on the first metal layer and forming a sacrificial patterning layer on the sacrificial block layer;removing the first metal layer, the sacrificial block layer and the sacrificial patterning layer from the first channel region;forming a barrier metal layer on the first channel region and over a nitride layer along with forming the barrier metal layer on the second channel region, the third channel region, and the fourth channel region;removing, from the second channel region and the third channel region, the first metal layer, the sacrificial block layer, the sacrificial patterning layer, and the barrier metal layer;removing, from the fourth channel region, the barrier metal layer, and the sacrificial patterning layer;removing the sacrificial block layer from the fourth channel region;depositing a third metal layer and a work function metal layer on the first channel region, the second channel region, the third channel ...

SEMICONDUCTOR STRUCTURE HAVING CONTACT HOLES BETWEEN SIDEWALL SPACERS

The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole. 117.-. (canceled)18. A semiconductor structure , comprising:a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers, disposed on a semiconductor substrate, wherein the plurality of discrete gate structures and the sidewall spacers are disposed in the dielectric layer, and one sidewall spacer is on each side of each gate structure;a first protective layer on a surface portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures, wherein the first protective layer is located corresponding to a portion of a length of the neighboring sidewall spacers;a second protective layer on each gate structure;contact holes on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the first protective layer; anda metal plug in each contact hole.19. The semiconductor structure according to claim 18 , wherein:{'sub': 'x', 'each of the first and second protective layers is made of a material including SiN, SiON, SiC, SiCO, or a combination thereof, and'}the first and ...

FORMATION OF A SEMICONDUCTOR DEVICE WITH RIE-FREE SPACERS

A method of forming a fin-type field effect transistor (FinFET) can comprise forming at least one fin having an active region and a non-active region. Thereafter, a nitride is deposited on the fin. A dummy gate and nitride mask are formed on the fin over the nitride. Oxide spacers are formed on sidewalls of the dummy gate. The nitride is removed from the fin. Thereafter, a source region and a drain region are formed in the active region of the at least one fin. The result is a more reliable finFET without any possible pinch-off problems and fin erosion. Other embodiments are also described herein. 1. A method of forming a structure of a semiconductor device , the method comprising:forming at least one fin having an active region and a non-active region;forming a single first nitride on the fin;forming a dummy gate and nitride mask on the fin over the single first nitride, wherein the dummy gate is in contact with the single first nitride on the fin;forming oxide spacers on sidewalls of the dummy gate; andremoving the single first nitride and forming a source region and a drain region.2. The method of further comprising removing the dummy gate and nitride mask to form a trench.3. The method of further comprising forming a gate structure in the trench.4. The method of wherein forming the gate structure comprises:removing nitride covering the fin in the gate trench;depositing a high-K dielectric material in the trench; anddepositing a metal material on the dielectric material.5. The method of wherein the metal material is chosen from aluminum and tungsten.6. The method of further comprising depositing a metal liner between the high-K dielectric material and the gate metal.7. The method of further comprising performing a native oxide clean prior to forming oxide spacers.8. The method of wherein depositing the single first nitride on the fin comprises performing a nitradation in NH.9. The method of wherein the dummy gate comprises either an amorphous silicon or a ...

INTEGRATED METAL GATE CMOS DEVICES

A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region. 1. A semiconductor device comprising:a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region;a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region; a first metal layer arranged on the first channel region;', 'a work function metal layer arranged on the first metal layer; and', 'another work function metal arranged on the work function metal layer; and, 'a first gate stack arranged on the first channel region, the first gate stack comprisinga second gate stack arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.2. The device of claim 1 , wherein the first gate stack further comprises a sacrificial patterning layer arranged on the work function metal layer.3. The device of claim 1 , further comprising a third channel region.4. The device of claim 3 , further comprising a fourth channel region.5. The device of claim 4 , further comprising an interfacial layer on the first channel region claim 4 , the second channel region claim 4 , the third channel region claim 4 , and the fourth channel region.6. The device of claim 1 , wherein the substrate is doped.7. The device of claim 1 , wherein the ...

INTEGRATED CIRCUIT DEVICE

An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion. 1. An integrated circuit device comprising:a substrate comprising a first device region and a second device region;a first fin separation insulating portion over the first device region, the first fin separation insulating portion having a first vertical length in a vertical view;a pair of first fin-type active regions spaced apart from each other in the first device region with the first fin separation insulating portion therebetween, the pair of first fin-type active regions collinearly extending in a first horizontal direction;a plurality of dummy gate structures extending parallel to each other in a second horizontal direction over the first fin separation insulating portion and the pair of first fin-type active regions, the second horizontal direction crossing the first horizontal direction;a second fin separation insulating portion spaced apart from the first fin separation insulating portion and arranged over the second device region, the second fin separation insulating portion having a second vertical length ...

SEMICONDUCTOR DEVICE WITH FIN TRANSISTORS AND MANUFACTURING METHOD OF SUCH SEMICONDUCTOR DEVICE

A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor. 1each of the first conductivity type transistor and the second conductivity type includes agate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode;the gate insulating film is made of a high dielectric constant material; andoffset spacers are (a) between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or (b) offset spacers in the first conductivity type transistor have a different thickness than offset spacers in the second conductivity type transistor.. A semiconductor device including a first conductivity type transistor and a second conductivity type transistor, wherein: This application is a continuation of U.S. Ser. No. 16/443,319 filed Jun. 17, 2019, which is a division of U.S. patent application Ser. No. 15/588,072 filed May 5, 2017, now U.S. Pat. No. 10,373,955 issued Aug. 6, 2019, which is a continuation of U.S. patent application Ser. ...

MOS-VARACTOR DESIGN TO IMPROVE TUNING EFFICIENCY

A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor. 1. A gate stack structure for a MOS varactor , comprising:a substrate including a channel region;a high-k dielectric layer on the channel region of the substrate;a P-type work function adjustment layer on the high-k dielectric layer, the P-type work function adjustment layer including a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion;an N-type work function adjustment layer on the P-type work function adjustment layer; anda metal gate on the N-type work function adjustment layer.2. The gate stack structure of claim 1 , wherein the P-type work function adjustment layer comprises a first TiN layer on a first portion of the high-k dielectric layer and a second TiN layer on the first TiN layer and on a second portion of the high-k dielectric layer;the first portion of the P-type work function adjustment layer comprises the first TiN layer and a first portion of the second TiN layer on the first TiN layer; andthe second portion of the P-type work function adjustment layer comprises a second portion of the second TiN layer on the second portion of the high-k dielectric layer.3. The gate stack structure of claim 1 , wherein the P-type work function adjustment layer comprises a first TiN layer on a ...

Transistor devices having source/drain structure configured with high germanium content portion

Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures. 1. (canceled)2. An integrated circuit device , comprising:a semiconductor nanowire comprising at least one of silicon and germanium;a gate structure around the semiconductor nanowire, the gate structure including a gate electrode and a gate dielectric between the semiconductor nanowire and the gate electrode;a source structure or drain structure adjacent the semiconductor nanowire, the source structure or drain structure including a first portion and a second portion, the first portion comprising at least one of silicon and germanium, and the second portion comprising a p-type dopant and germanium, the second portion having a germanium concentration in excess of 80 atomic %, wherein the first portion is thinner than the second portion, and wherein the first portion is between the second portion and the semiconductor nanowire; anda contact structure on the second portion of the source structure or drain structure.3. The device of claim 2 , wherein the semiconductor nanowire consists essentially of silicon claim 2 , and the ...

Assemblies Having Conductive Structures with Three or More Different Materials

Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions. 1. A memory cell , comprising:a conductive gate; the conductive gate including at least three different materials; said at least three different materials including a first material having an outer perimeter in a cross-section, a second material directly adjacent the first material and compositionally different than the first material, and a third material directly adjacent the second material and compositionally different than each of the first and second materials; the first and third materials comprising metal and being electrically conductive, the third material being present along an entirety of the outer perimeter of the first material in the cross-section;a charge-blocking region adjacent the conductive gate;a charge-storage region adjacent the charge-blocking region;tunneling material adjacent the charge-storage region; andchannel material adjacent the tunneling material, the tunneling material being between the channel material and the charge-storage region.2. The memory cell of wherein the first material comprises one or more of Co claim 1 , Mo claim 1 , Ni claim 1 , Ru and W.3. The memory cell of wherein the first material consists of one or more of Co claim 1 , Mo claim 1 , Ni claim 1 , Ru and W.4. The memory cell of wherein the second material comprises one or more compositions selected from the group consisting of metal nitrides claim 1 , metal carbides claim 1 , metal borides claim 1 , metal oxides and metal carbonitrides.5. The memory cell of wherein the second material comprises one or more of AlO claim 1 , ...

Notched Gate Structure Fabrication

A method includes providing a structure having a first region and a second region, the first region including a first channel region, the second region including a second channel region; forming a gate stack layer over the first and second regions; patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region; and laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously, thereby forming notches at the bottom portions of the first and second gate stacks.

Metal Gate Stack Having TaAlCN Layer

Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary method includes forming a gate stack over a substrate and at least partially removing the gate stack, thereby forming an opening. A multi-function layer is deposited in the opening and a work function layer is deposited over the multi-function layer. The multi-function layer includes nitrogen and one of titanium or tantalum. The work function layer includes nitrogen and one of titanium or tantalum. A concentration of the nitrogen of the work function layer is different than a concentration of the nitrogen of the multi-function layer. In some implementations, the concentration of the nitrogen of the work function layer from about 2% to about 5% and the concentration of the nitrogen of the multi-function layer from about 5% to about 15%. 1. A method comprising: depositing a gate dielectric layer over the substrate;', 'depositing a multi-function layer over the gate dielectric layer, wherein the depositing the multi-function layer includes depositing a first metal nitride material with a first nitrogen (N) concentration to form a first sub-layer of the multi-function layer and depositing a second metal nitride material with a second N concentration to form a second sub-layer of the multi-function layer, wherein the first N concentration is different than the second N concentration; and', 'depositing a work function layer over the multi-function layer., 'forming a gate stack over a substrate by2. The method of claim 1 , wherein the depositing the multi-function layer over the gate dielectric layer includes performing a physical vapor deposition process.3. The method of claim 2 , wherein the performing the physical vapor deposition process includes tuning process parameters to set the first N concentration from about 5% to about 15% and the second N concentration from about 2% to about 5%.4. The method of claim 3 , further ...

Structure and Formation Method of Semiconductor Device Structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling. 1. A semiconductor device comprising:a fin structure;a shallow trench isolation (STI) adjacent the fin structure;a gate structure over a portion of the fin structure and the STI, wherein the gate structure comprises a gate dielectric layer, a work function layer over the gate dielectric layer, and a conductive fill material over the work function layer;spacers along opposing sidewalls of the gate structure, the spacers terminating at ends of the gate structure along a longitudinal axis of the gate structure; anda dielectric layer surrounding the gate structure and the spacers in a plan view, wherein the work function layer terminates over the STI between the fin structure and the dielectric layer along a longitudinal axis of the gate structure, wherein the gate dielectric layer completely separates the conductive fill material from the spacers and the dielectric layer.2. The semiconductor device of claim 1 , wherein the conductive fill material directly contacts the gate dielectric layer.3. The semiconductor device of claim 1 , wherein an uppermost surface of the gate dielectric layer is level with an uppermost surface of the dielectric layer.4. The semiconductor device of claim 1 , wherein a thickness of the work function layer is less than a height of the fin structure above the STI.5. The semiconductor device of claim 1 , wherein the conductive fill material is interposed between the work function layer and the dielectric layer.6. The ...

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate having first and second regions, a first gate electrode layer on the first region, and including a first conductive layer, and a second gate electrode layer on the second region, and including the first conductive layer, a second conductive layer on the first conductive layer, and a barrier metal layer on the second conductive layer, wherein an upper surface of the first gate electrode layer is at a lower level than an upper surface of the second gate electrode layer. 1. A semiconductor device , comprising:a substrate having first and second regions;a first gate electrode layer on the first region, and including a first conductive layer; anda second gate electrode layer on the second region, and including the first conductive layer, a second conductive layer on the first conductive layer, and a barrier metal layer on the second conductive layer,wherein an upper surface of the first gate electrode layer is at a lower level than an upper surface of the second gate electrode layer.2. The semiconductor device as claimed in claim 1 , wherein the first gate electrode layer has a thickness smaller than a thickness of the second gate electrode layer.3. The semiconductor device as claimed in claim 1 , wherein a width of the second gate electrode layer is equal to or narrower than a width of the first gate electrode layer.4. The semiconductor device as claimed in claim 1 , wherein the first conductive layer in the first gate electrode layer has a flat upper surface claim 1 , and the first conductive layer in the second gate electrode layer has a curved upper surface.5. (canceled)6. The semiconductor device as claimed in claim 1 , wherein a width of an upper portion of the second conductive layer in the second gate electrode layer is wider than a width of a lower portion thereof.7. The semiconductor device as claimed in claim 1 , wherein the first conductive layer includes a material having a work function greater than a work ...

MULTI-COMPONENT CONDUCTIVE STRUCTURES FOR SEMICONDUCTOR DEVICES

Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing. 1. A method of forming a semiconductor device , comprising: forming a first conductive material within the recess of the substrate structure by a cyclic deposition process, the deposited first conductive material comprising at least 60% ruthenium, the first filling the majority of the recess; and', 'forming a second conductive material on the first conductive material through a different deposition process than the cyclic deposition process, the deposited second conductive material comprising 40% or less of ruthenium., 'forming conductive materials within a recess within a substrate structure, comprising,'}2. The method of claim 1 , wherein the cyclic deposition process comprises at least one of chemical vapor deposition and atomic layer deposition claim 1 , and is performed through use of a precursor gas comprising carbon.3. The method of claim 2 , wherein the cyclic deposition process is performed through use of a precursor gas comprising carbon and ruthenium.4. The method of claim 3 , wherein the second conductive material further comprises at least one of carbon claim 3 , nitrogen claim 3 , oxygen claim 3 , silicon oxide claim 3 , and polysilicon.5. The method of claim 4 , wherein the second conductive material comprises carbon.6. The method of claim 4 , wherein the first and second conductive materials are formed using a first ruthenium-containing precursor gas; and wherein the second conductive material is formed through introduction of an ...

METAL GATE STRUCTURE CUTTING PROCESS

Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure. 18.-. (canceled)9. A method for manufacturing a semiconductor device structure , the method comprisingforming a metal gate structure over a first fin structure and a second fin structure disposed on a substrate, wherein an interlayer dielectric (ILD) layer is formed between the first and the second fin structures;performing an ILD recess etching process to selectively form a recess in the ILD layer;forming a dielectric structure in the recess;performing a metal gate structure cutting process to form a line-cut that divides the metal gate structure into sub-metal gate structures, the line-cut further being formed at least partially in the dielectric structure; andforming an isolation structure in the line-cut.10. The method of claim 9 , wherein performing the metal gate structure cutting process further comprises:removing a portion of the dielectric structure.11. The method of claim 9 , wherein forming the dielectric structure further comprises:forming a conformal liner layer along a sidewall of the ILD layer and a bottom surface of the recess.12. The method of claim 9 , wherein forming a dielectric structure in the recess further comprises:fully filling the recess with the dielectric structure.13. The method of claim 9 , wherein the dielectric structure has a first side interfaced with the ILD layer and a second side interfaced with the isolation structure.14 ...

ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer. 1. A method of fabricating a fin field-effect transistor (Fin FET) device , the method comprising:forming a first gate structure over a channel region in a first portion of a first fin structure on a semiconductor substrate;forming first source/drain regions on a second portion of the first fin structure on opposing sides of the gate structure;implanting a first dopant in a first region of the first source/drain regions, the first region having a first doping concentration of the first dopant, the first doping concentration being greater than a second doping concentration of a second dopant in a second region of the first source/drain regions; andapplying a thermal anneal operation to at least the first fin structure and the first source/drain regions, the channel region of the first fin structure having greater channel mobility than a channel region of a second fin structure on the substrate.2. The method of claim 1 , further comprising:forming a second gate structure over a channel region in a first portion of a second fin structure on the semiconductor substrate; andforming second source/drain regions on a second portion of the second fin structure on opposing sides of the second gate ...

EIGHT-TRANSISTOR STATIC RANDOM-ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME

A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor. 1. A Static Random Access Memory (SRAM) cell , comprising:a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; anda read port including a read pass-gate transistor and a read pull-down transistor serially connected to each, gate electrodes of the read pass-gate transistor, the second pull-down transistor, and the second pull-up transistors being electrically connected to each other,wherein a first doping concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doping concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.2. The SRAM cell of claim 1 , wherein:the first and second pass-gate transistors, the ...

FINFET SRAM HAVING DISCONTINUOUS PMOS FIN LINES

An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines. 1. A device , comprising:a first static random access memory (SRAM) cell, a second SRAM cell, and a third SRAM cell, wherein the second SRAM cell is disposed between the first SRAM cell and the third SRAM cell in a first direction;a first fin structure extending in the first direction, wherein the first fin structure is partially disposed in the first SRAM cell;a second fin structure extending in the first direction, wherein the second fin structure is partially disposed in the first SRAM cell and partially disposed in the second SRAM cell, and wherein the second fin structure is spaced apart from the first fin structure in a second direction different from the first direction; anda third fin structure extending in the first direction, wherein the third fin structure is partially disposed in the second SRAM cell and partially disposed in the third SRAM cell, wherein the second fin structure is spaced apart from the third fin structure in the second direction, and wherein the first fin structure is spaced apart from the third fin structure in the first direction.2. The device of claim 1 , wherein:the first SRAM cell is contiguous with the second SRAM cell; andthe second SRAM cell is contiguous with the third SRAM cell.3. The device of claim 1 , wherein the first fin structure is aligned with the third fin structure in the first direction.4. The device of claim 1 , wherein:a first end ...