Metal Gate Structure

A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench. 1. A method comprising:forming a trench in one or more dielectric layers over a substrate;depositing a gate dielectric layer on a bottom, a first sidewall, and a second sidewall of the trench;depositing a metal layer over the gate dielectric layer;depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness; andapplying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench.2. The method of further comprising removing the protection layer after applying the etch-back process.3. The method of claim 1 , wherein after applying the etch-back process claim 1 , a corner portion between the metal layer along a first sidewall of the trench and the metal layer along a bottom of the trench has a step.4. The method of claim 3 , wherein the corner portion further comprises a ramp between the step and the metal layer along the first sidewall of the trench.5. The method of claim 1 , wherein the protection layer comprises a dielectric layer.6. The method of claim 1 , wherein an upper portion of the protection layer formed along a sidewall of the trench is thicker than a lower ...

METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN

A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.

Semiconductor device and fabrication method thereof

A semiconductor device includes a semiconductor substrate, a pair of source/drain regions, and a gate stack. The pair of source/drain regions is on the semiconductor substrate. The gate stack is laterally between the source/drain regions and includes a gate dielectric layer over the semiconductor fin, a metal element-containing layer over the gate dielectric layer, and a fill metal layer over the metal element-containing layer. The metal element-containing layer has a dopant, and a concentration of the dopant in an upper portion of the metal element-containing layer is higher than a concentration of the dopant in a bottom portion of the metal element-containing layer.

METHOD FOR FORMING METAL GATES IN A GATE LAST PROCESS

The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

Method of controlling gate thickness in forming FinFET devices

A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.

METHOD OF CONTROLLING GATE THICKNESS IN FORMING FINFET DEVICES

A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin.

Method of making a gate structure

A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.

Metal Gate Structure

A method comprises depositing a dielectric layer on sidewalls and a bottom of a trench of a gate structure, depositing a metal layer on the dielectric layer, depositing a protection layer on the metal layer, wherein an upper portion of a sidewall portion of the protection layer is thinner than a lower portion of the sidewall portion of the protection layer and etching back the metal wherein an upper portion of a first metal sidewall of the metal layer is thinner than a lower portion of the first metal sidewall and an upper portion of a second metal sidewall of the metal layer is thinner than a lower portion of the second metal sidewall. 1. A method comprising:forming a first gate trench and an second gate trench, wherein a width of the second gate trench is greater than a width of the first gate trench;depositing a first dielectric layer in the first gate trench and a second dielectric layer in the second gate trench;depositing a first metal layer on the first dielectric layer and a second metal layer on the second dielectric layer; 'an upper portion of a sidewall portion of the second protection layer is thinner than a lower portion of the sidewall portion of the second protection layer; and', 'depositing a first protection layer on the first metal layer and a second protection layer on the second metal layer, wherein 'an upper portion of a sidewall of the second metal layer is thinner than a lower portion of the sidewall of the second metal layer.', 'performing an etch-back process on the first protection layer and the second protection layer to expose sidewalls of the first metal layer and sidewalls of the second metal layer, wherein2. The method of claim 1 , further comprising:removing a bottom portion of the first protection layer and a bottom portion of the second protection layer to form a first step and a second step in the first gate trench, and a third step and a fourth step in the second gate trench.3. The method of claim 2 , wherein:the first step is ...

Gate structures

An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

Etching Back and Selective Deposition of Metal Gate

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate. 1. A method comprising:forming a first dummy gate stack;forming a dielectric layer, with the first dummy gate stack located in the dielectric layer;removing the first dummy gate stack to form a first opening in the dielectric layer;forming a metal layer extending into the first opening;etching back the metal layer, wherein remaining portions of the metal layer in the first opening have edges lower than a top surface of the dielectric layer; andselectively depositing a first conductive layer in the first opening, wherein the first conductive layer is over the metal layer, and the metal layer and the first conductive layer in combination form a replacement gate.2. The method of claim 1 , wherein the etching back of the metal layer comprises:filling a protection layer over the metal layer, wherein the protection layer is filled into the first opening;etching the metal layer using the protection layer as an etching mask; andremoving the protection layer.3. The method of claim 2 , wherein the filling the protection layer comprises applying a photo resist.4. The method of claim 2 , wherein the metal layer partially fills the first opening before the metal layer is etched back claim 2 , and the method further comprises:forming a second dummy gate stack simultaneously as the first dummy gate stack;removing the second dummy gate stack to form a second opening in the dielectric layer, ...

Semiconductor device and manufacturing method thereof

A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer.

Method and system for metal gate formation with wider metal gate fill margin

A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.

Method for forming metal gates in a gate last process

The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

Etching back and selective deposition of metal gate

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Method of fabricating gate structures

A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening.

Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures

An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides ...

Metal Gate Structure

A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench, wherein the second metal sidewall becomes progressively thinner towards an upper portion of the second metal sidewall and a metal bottom layer on a bottom of the trench and between the first metal sidewall and the second metal sidewall. 1. A structure comprising: a first metal sidewall;', 'a second metal sidewall; and', an upper portion of the first metal sidewall is thinner than a lower portion of the first metal sidewall; and', 'an upper portion of the second metal sidewall is thinner than a lower portion of the second metal sidewall., 'a metal bottom layer between the first metal sidewall and the second metal sidewall, wherein], 'a metal layer partially filling a trench of a metal gate structure, wherein the metal layer comprises2. The structure of claim 1 , further comprising:a first dielectric layer under the metal layer;a plurality of gate spacers surrounding the trench;a barrier layer, wherein the barrier layer is formed between the first dielectric layer and the plurality of gate spacers; anda second dielectric layer, wherein the second dielectric layer is formed adjacent to the plurality of gate spacers.3. The structure of claim 1 , further comprising:a first step region between the first metal sidewall and the metal bottom layer; anda second step region between the second metal sidewall and the metal bottom layer.4. The structure of claim 3 , wherein:a first height of the first step region is in a range from about 5 angstroms to about 35 angstroms; anda second height of the second step region is in a range from about 5 angstroms to about 35 angstroms.5. The structure of claim 1 , wherein:the first metal sidewall becomes progressively thinner towards the ...

METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN

A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion. 112-. (canceled)13. A semiconductor device , comprising:a semiconductor substrate;a source and a drain region formed on the semiconductor substrate; and a trench having a top surface; and', 'a metal layer partially filling the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion., 'a gate structure disposed on the substrate between the source and drain regions, the gate structure including14. The semiconductor device of claim 13 , wherein the sidewall portion is at least approximately 33% thinner than the bottom portion.15. The semiconductor device of claim 13 , wherein a top surface of the metal layer is below the top surface of the trench.16. The semiconductor device of claim 13 , wherein the top surface of the metal layer does not include an overhang.17. The semiconductor device of claim 13 , wherein the top surface of the metal layer includes an overhang.18. The semiconductor device of claim 13 , further comprising a conductive layer filling a remainder of the trench.19. The semiconductor device of claim 13 , wherein ...

Semiconductor device and fabrication method thereof

A semiconductor device includes a substrate, a semiconductor fin extending from the substrate, a gate dielectric layer over the semiconductor fin, a metal nitride layer comprising a first portion over the gate dielectric layer and a second portion over the first portion, and a fill layer over the metal nitride layer. The second portion has an aluminum concentration greater than an aluminum concentration of the first portion.

Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures

An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides ...

Method of making a gate structure

A method of making a gate structure includes forming a trench in a dielectric layer. The method further includes forming a gate dielectric layer in the trench. The gate dielectric layer defines an opening in the dielectric layer. The method includes forming a gate electrode in the opening. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material. The first metal material has a recess. Forming the gate electrode includes filling an entire width of a top portion of the opening with a homogeneous second metal material. The homogeneous second metal material has a protrusion extending into the recess, and a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material. A top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.

Contact structures in semiconductor devices

A semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. The method includes forming first and second source/drain (S/D) regions on first and second fin structures, forming a first dielectric layer between the first and second S/D regions, forming first and second gate-all-around (GAA) structures on the first and second fin structures, forming a second dielectric layer on the first and second GAA structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second GAA structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.

Metal Gate Structure

A method comprises depositing a metal layer partially filling a trench of a gate structure, forming a protection layer on the metal layer, wherein a sidewall portion of the protection layer is thinner than a bottom portion of the protection layer, removing a portion of the metal layer and removing the bottom portion of the protection layer. 1. A method comprising:forming a dielectric layer on a bottom and along sidewalls of a gate trench;depositing a metal layer on the dielectric layer; the protection layer comprises a bottom portion and a sidewall portion; and', 'a lower portion of the sidewall portion of the protection layer is thinner than an upper portion of the sidewall portion of the protection layer;, 'depositing a protection layer on the metal layer, whereinremoving a portion of the metal layer; andremoving the bottom portion of the protection layer.2. The method of claim 1 , wherein:depositing the metal layer on the dielectric layer using a physical vapor deposition process.3. The method of claim 1 , further comprising:depositing the protection layer on the metal layer using a physical vapor deposition process.4. The method of claim 1 , wherein:the protection layer is formed of a dielectric material.5. The method of claim 1 , further comprising:applying an isotropic etching process to the protection layer until the sidewall portion of the protection layer and the portion of the metal layer have been removed.6. The method of claim 1 , further comprising:applying an etching process to the bottom portion of the protection layer until a top surface of a bottom portion of the metal layer is exposed.7. The method of claim 1 , further comprising:after the step of removing the portion of the metal layer, forming a step and a ramp between a bottom portion of the metal layer and a sidewall portion of the metal layer.8. A method comprising:forming a first dielectric layer in a first gate trench and a second dielectric layer in a second gate trench, wherein a width of ...

SEMICONDUCTOR DEVICE WITH MULTI-THRESHOLD GATE STRUCTURE

The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

Metal Gate Structure

A metal gate structure comprises a metal layer partially filling a trench of the metal gate structure. The metal layer comprises a first metal sidewall, a second metal sidewall and a metal bottom layer. By employing an uneven protection layer during an etching back process, the thickness of the first metal sidewall is less than the thickness of the metal bottom layer and the thickness of the second metal sidewall is less than the thickness of the metal bottom layer. The thin sidewalls allow extra space for subsequent metal-fill processes. 1. A structure comprising: a first metal sidewall;', 'a second metal sidewall; and', a thickness of the first metal sidewall is less than a thickness of the metal bottom layer; and', 'a thickness of the second metal sidewall is less than the thickness of the metal bottom layer; and, 'a metal bottom layer, wherein'}], 'a metal layer partially filling a trench of a metal gate structure comprisinga dielectric layer, wherein the metal layer is formed on the dielectric layer.2. The structure of claim 1 , further comprising:a plurality of gate spacers;a barrier layer, wherein the barrier layer is formed between the dielectric layer and the plurality of gate spacers; andan interlayer dielectric layer, wherein the interlayer dielectric layer is formed adjacent to the plurality of gate spacers.3. The structure of claim 1 , wherein the first metal sidewall has a thickness less than 10 angstrom.4. The structure of claim 1 , wherein the second metal sidewall has a thickness less than 10 angstrom.5. The structure of claim 1 , further comprising:a first plateau region formed between the metal bottom layer and the first metal sidewall; anda second plateau region formed between the metal bottom layer and the first metal sidewall.6. The structure of claim 1 , wherein the metal layer comprises metal nitride.7. A device comprising: a first metal sidewall;', 'a second metal sidewall;', the first metal sidewall, the second metal sidewall and the first ...

GATE STRUCTURES

A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening. 1. A semiconductor device , comprising:a semiconductor substrate;first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein; a first dielectric material over the first channel region;', 'a first opening over the first dielectric material and the first channel region; and', 'a pure first metal with an n-type work function value and a low resistivity conformally deposited in the first opening;, 'a first gate structure engaging the first projection adjacent the first channel region, the first gate structure including a second dielectric material over the second channel region;', 'a second opening over the second dielectric material and the second channel region; and', 'a pure second metal with a p-type work function value and a low resistivity conformally deposited in the second opening., 'a second gate structure engaging the second projection adjacent the second channel region, the second gate structure ...

Metal gate structure

A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.

Metal gate structure

A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.

Metal Gate Structure

A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp. 1. A device comprising:a substrate; and a first metal sidewall;', 'a metal bottom layer;', 'a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp;', 'a second metal sidewall; and', 'a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp., 'a metal gate structure over the substrate, wherein the metal gate structure comprises2. The device of claim 1 , wherein:a height of the first step is substantially equal to a height of the second step.3. The device of claim 1 , wherein:the first step and the second step are adjacent to the metal bottom layer; andthe first ramp and the second ramp are adjacent to the first metal sidewall and the second metal sidewall, respectively.4. The device of claim 1 , wherein:a height of the first step is in a range from about 5 angstroms to about 35 angstroms.5. The device of claim 1 , wherein:a thickness of the first metal sidewall is about 10 angstroms.6. The device of claim 1 , further comprising:a barrier on and in contact with the substrate; anda dielectric layer on and in contact with the barrier.7. The device of claim 1 , further comprising:an inter-layer dielectric layer over the substrate, wherein the metal gate structure is embedded in the inter-layer dielectric layer.8. A method comprising:forming a first gate trench and a second gate ...

Metal gate structure

A method comprises depositing a dielectric layer on sidewalls and a bottom of a trench of a gate structure, depositing a metal layer on the dielectric layer, depositing a protection layer on the metal layer, wherein an upper portion of a sidewall portion of the protection layer is thinner than a lower portion of the sidewall portion of the protection layer and etching back the metal wherein an upper portion of a first metal sidewall of the metal layer is thinner than a lower portion of the first metal sidewall and an upper portion of a second metal sidewall of the metal layer is thinner than a lower portion of the second metal sidewall.

Metal gate structure

A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.

Transistor performance with metal gate

The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.

Metal gate structure

A method comprises depositing a metal layer partially filling a trench of a gate structure, forming a protection layer on the metal layer, wherein a sidewall portion of the protection layer is thinner than a bottom portion of the protection layer, removing a portion of the metal layer and removing the bottom portion of the protection layer.

Etching Back and Selective Deposition of Metal Gate

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Metal Gate Structure

A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp. 1. A device comprising: a first metal sidewall;', 'a metal bottom layer;', 'a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp;', 'a second metal sidewall; and', 'a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp., 'a metal layer in a trench over a substrate, wherein the metal layer comprises2. The device of claim 1 , wherein:a height of the first step is substantially equal to a height of the second step.3. The device of claim 1 , wherein:the first step and the second step are adjacent to the metal bottom layer; andthe first ramp and the second ramp are adjacent to the first metal sidewall and the second metal sidewall, respectively.4. The device of claim 1 , wherein:a height of the first step is in a range from about 5 angstroms to about 35 angstroms.5. The device of claim 1 , wherein:a thickness of the first metal sidewall is about 10 angstroms.6. The device of claim 1 , further comprising:a barrier on and in contact with the substrate; anda dielectric layer on and in contact with the barrier.7. The device of claim 1 , further comprising:an inter-layer dielectric layer over the substrate, wherein the metal layer is surrounded by the inter-layer dielectric layer.8. A device comprising: a first metal sidewall, a first metal bottom layer and a second metal ...

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.

Multi-metal-oxide high-k gate dielectrics

A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.

Semiconductor device and fabrication method thereof

A method includes forming a gate dielectric layer over a semiconductor substrate, forming a first metal element-containing layer over the gate dielectric layer, and thermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer.

Method and system for metal gate formation with wider metal gate fill margin

A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.

Multi-metal-oxide high-K gate dielectrics

A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.

METAL GATE WITH PRETREATMENT LAYER

A method of forming a transistor is disclosed. The method includes forming a high-k dielectric constant layer on a semiconductor substrate, forming a pretreatment layer (PL) on the high-k dielectric constant layer, determining a thickness for a conductive work function layer (WFL) based on a target effective work function of the transistor, and forming the conductive work function layer (WFL) on the first pretreatment layer, where the conductive work function layer has a WFL thickness substantially equal to the determined thickness. Forming the transistor also includes forming a coating layer on the first conductive work function layer. The gate stack has a tuned effective work function according to the determined thickness.

Metal Gate Structure

A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench. 1. A method comprising:forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer;depositing a dielectric layer on a bottom and along sidewalls of the trench;depositing a metal layer over the dielectric layer;depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness;applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench; andremoving the protection layer from the trench.2. The method of claim 1 , wherein:the protection layer is formed of a dielectric material.3. The method of claim 1 , wherein:an upper portion of the protection layer formed along a sidewall of the trench is thicker than a lower portion of the protection layer formed along the sidewall of the trench.4. The method of claim 1 , further comprising:forming the protection layer using a physical vapor deposition process.5. The method of claim 4 , wherein:as a result of using the physical vapor deposition process, the protection layer has the uneven thickness.6. The method of claim 1 , further comprising:forming a barrier layer ...

SEMICONDUCTOR DEVICE WITH MULTI-THRESHOLD GATE STRUCTURE

The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

Semiconductor device with multi-threshold gate structure

The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

Method of forming metal gate electrode

An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of H 2 O 2 , NH 4 OH, HCl, H 2 SO 4 or diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NH 4 OH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material.

Etching Back and Selective Deposition of Metal Gate

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, first gate structure, a first metal layer, a first protective layer, and a first contact plug. The first gate structure includes a plurality of first U-shaped layers stacked one another between the first gate spacers in a cross-sectional view and first gate spacers on opposite sides of the first U-shaped layers. The first metal layer is over the first U-shaped layers and has a different shape than the first U-shaped layers in the cross-sectional view. The first protective layer is over the first metal layer and between the first gate spacers. The first contact plug extends through the first protective layer and the first metal layer, and is in contact with the first gate structure.

FinFET having a work function material gradient

A semiconductor device includes a semiconductor substrate having a channel region. A gate dielectric layer is over the channel region of the semiconductor substrate. A work function metal layer is over the gate dielectric layer. The work function metal layer has a bottom portion, an upper portion, and a work function material. The bottom portion is between the gate dielectric layer and the upper portion. The bottom portion has a first concentration of the work function material, the upper portion has a second concentration of the work function material, and the first concentration is higher than the second concentration. A gate electrode is over the upper portion of the work function metal layer.

Metal gate structure

A device comprises a metal gate structure over a substrate, wherein the metal gate structure comprises a first metal sidewall, a metal bottom layer, a first corner portion between the first metal sidewall and the metal bottom layer, wherein the first corner portion comprises a first step and a first ramp, a second metal sidewall and a second corner portion between the second metal sidewall and the metal bottom layer, wherein the second corner portion comprises a second step and a second ramp.

Metal gate structure

A metal gate structure comprises a metal layer partially filling a trench of the metal gate structure. The metal layer comprises a first metal sidewall, a second metal sidewall and a metal bottom layer. By employing an uneven protection layer during an etching back process, the thickness of the first metal sidewall is less than the thickness of the metal bottom layer and the thickness of the second metal sidewall is less than the thickness of the metal bottom layer. The thin sidewalls allow extra space for subsequent metal-fill processes.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.

GATE STRUCTURES AND METHOD OF FABRICATING SAME

A method includes: forming first and second projections; forming a first structure engaging the first projection, and including: a non-metallic conductive layer, and a first opening over the conductive layer; forming a second structure engaging the second projection, and including: a second opening; and conformally depositing a pure metal in the first and second openings. A different aspect involves an apparatus including: a first device that includes a first projection and a first gate structure, the first projection extending from a substrate, and the first gate structure engaging the first projection, and including an opening, and a conformal, pure metal disposed in the opening; and a second device that includes a second projection and a second gate structure, the second projection extending from the substrate, and the second gate structure engaging the second projection, and including a silicide including a metal that is the same metal disposed in the opening.

Metal gate structure

A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench, wherein the second metal sidewall becomes progressively thinner towards an upper portion of the second metal sidewall and a metal bottom layer on a bottom of the trench and between the first metal sidewall and the second metal sidewall.

Metal gate electrode of a field effect transistor

An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.

Gate Structures

An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

Gate structures

A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening.

Metal gate electrode of a field effect transistor

A method of fabricating a metal gate electrode of a field effect transistor includes forming a dielectric layer over an active region, and forming an opening in the dielectric layer. The method further includes partially filling the opening with a high-dielectric-constant material, partially filling the opening with a conformal first metal material over the high-dielectric-constant material, and filling the opening with a capping layer over the first metal material. The method further includes partially removing the first metal material and capping layer in the opening using a wet etching process. The method further includes fully removing the remaining capping layer in the opening using a wet etching process. The method further includes depositing a second metal material in the opening over the remaining first metal material, and planarizing the second metal material.

Etching back and selective deposition of metal gate

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR

An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10. 1. A metal gate electrode for a field effect transistor comprising:a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; andan upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.2. The metal gate electrode of claim 1 , wherein the lower portion is substantially U-shaped.3. The metal gate electrode of claim 1 , wherein a ratio of a maximum height of the lower portion to a minimum height of the upper portion is from 0.1 to 0.9.4. The metal gate electrode of claim 1 , wherein the first metal material comprises a material selected from a group of TiN claim 1 , TaN claim 1 , and WN.5. The metal gate electrode of claim 1 , wherein the upper portion is substantially T-shaped.6. The metal gate electrode of claim 1 , wherein the second metal material comprises an N-work-function metal.7. The metal gate electrode of claim 6 , wherein the N-work-function metal comprises a metal selected from a group of Ti claim 6 , ...

Clip Frame Semiconductor Packages and Methods of Formation Thereof

In one embodiment, a semiconductor package includes a clip frame with a first clip having a first support structure, a first lever, and a first contact portion, which is disposed on a front side of the semiconductor package. The first support structure is adjacent an opposite back side of the semiconductor package. The first lever joins the first contact portion and the first support structure. A first die is disposed over the first support structure of the first clip. The first die has a first contact pad on the front side of the semiconductor package. An encapsulant material surrounds the first die and the first clip. 1. A semiconductor package comprising:a clip frame comprising a first clip having a first support structure, a first lever, and a first contact portion, the first lever joining the first contact portion and the first support structure, the first contact portion being disposed on a front side of the semiconductor package, and the first support structure being adjacent an opposite back side of the semiconductor package;a first die disposed over the first support structure of the first clip, the first die having a first contact pad on the front side of the semiconductor package; andan encapsulant material surrounding the first die and the first clip.2. The package of claim 1 , further comprising:a second die disposed over a second support structure of the first clip and embedded in the encapsulant material, the first clip further comprising a second lever, the second support structure being adjacent the back side of the semiconductor package, the second lever joining the first contact portion and the second support structure.3. The package of claim 1 , further comprising:a second die disposed over a second support structure of a second clip of the clip frame and embedded in the encapsulant material, the second clip further comprising a second lever and a second contact portion, the second support structure being adjacent the back side of the ...

Metal gate electrode of a field effect transistor

A method of fabricating a metal gate electrode of a field effect transistor includes forming a dielectric layer over an active region, and forming an opening in the dielectric layer. The method further includes partially filling the opening with a high-dielectric-constant material, partially filling the opening with a conformal first metal material over the high-dielectric-constant material, and filling the opening with a capping layer over the first metal material. The method further includes partially removing the first metal material and capping layer in the opening using a wet etching process. The method further includes fully removing the remaining capping layer in the opening using a wet etching process. The method further includes depositing a second metal material in the opening over the remaining first metal material, and planarizing the second metal material.

Method of forming metal gate electrode

An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material. The method also includes partially filling the opening with a first metal material over the high-dielectric-constant material. The method further includes filling the opening with a capping layer over the first metal material. The method additionally includes partially removing the first metal material and the capping layer in the opening using a wet etching process in a solution including one or more of H 2 O 2 , NH 4 OH, HCl, H 2 SO 4 or diluted HF. The method also includes fully removing the remaining capping layer in the opening using a wet etching process in a solution includes one or more of NH 4 OH or diluted HF. The method further includes depositing a second metal material in the opening over the remaining first metal material.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer. 1. A method , comprising:forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate;patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure comprising a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer;forming a plurality of first gate spacers on opposite sides of the first stacked structure;removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; andforming a first work function metal layer on the first portion of the metallic capping layer.2. The method of claim 1 , further comprising:forming a gate dielectric layer over the semiconductor substrate prior to forming the metallic capping layer.3. The method of claim 2 , wherein patterning the metallic capping layer and the dummy gate electrode layer is performed such that the gate dielectric layer is patterned.4. The method of claim 1 , wherein forming the first work function metal layer comprises a deposition process claim 1 , and a deposition rate of the first work function metal layer on the metallic capping layer is faster than a deposition rate of the first work function metal layer on the first gate spacers.5. The method of claim 1 , wherein patterning the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor. 1. A semiconductor device , comprising:a substrate; a first gate dielectric; and', 'a first work function metal layer over the first gate dielectric;, 'a first gate structure over the substrate, wherein the first gate structure comprises a second gate dielectric;', 'a second work function metal layer over the second gate dielectric; and', 'a filling conductor over the second work function metal layer;, 'a second gate structure over the substrate, the second gate structure being wider than the first gate structure, wherein the second gate structure comprisesfirst gate spacers on opposite sidewalls of the first gate structure;second gate spacers on opposite sidewalls of the second gate structure;first and second metal layers spanning over the first and second gate structures, respectively; andfirst and second contact plugs extending through the first and second metal layers, respectively, wherein the first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.2. The semiconductor device ...

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A method includes forming a gate dielectric layer over a semiconductor substrate, forming a first metal element-containing layer over the gate dielectric layer, and thermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer. 1. A method , comprising:forming a gate dielectric layer over a semiconductor substrate;forming a first metal element-containing layer over the gate dielectric layer; andthermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer.2. The method of claim 1 , wherein forming the first metal element-containing layer and thermal soaking the first metal element-containing layer are performed in the same processing chamber.3. The method of claim 1 , wherein thermal soaking the first metal element-containing layer in the first gas is performed at a temperature from about 200° C. to about 500° C.4. The method of claim 1 , further comprising:forming a second metal element-containing layer over the first metal element-containing layer using a precursor, wherein the constituent of the first gas diffused into the first metal element-containing layer bonds with a constituent of the precursor.5. The method of claim 1 , wherein the constituent of the first gas includes an N-work function metal or silicon.6. The method of claim 1 , further comprising:thermal soaking the first metal element-containing layer in a second gas after thermal soaking the first metal element-containing layer in the first gas.7. The method of claim 6 , wherein thermal soaking the first metal element-containing layer in the first gas and thermal soaking the first metal element-containing layer in the second gas are performed in the same processing chamber.8. The method of claim 6 , wherein the first gas is an aluminum-containing gas claim 6 , and the second gas is a ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a semiconductor substrate having a channel region. A gate dielectric layer is over the channel region of the semiconductor substrate. A work function metal layer is over the gate dielectric layer. The work function metal layer has a bottom portion, an upper portion, and a work function material. The bottom portion is between the gate dielectric layer and the upper portion. The bottom portion has a first concentration of the work function material, the upper portion has a second concentration of the work function material, and the first concentration is higher than the second concentration. A gate electrode is over the upper portion of the work function metal layer. 1. A semiconductor device comprising:a semiconductor substrate having a channel region;a gate dielectric layer over the channel region of the semiconductor substrate;a work function metal layer over the gate dielectric layer, wherein the work function metal layer has a bottom portion, an upper portion, and a work function material, the bottom portion is between the gate dielectric layer and the upper portion, the bottom portion has a first concentration of the work function material, the upper portion has a second concentration of the work function material, and the first concentration is higher than the second concentration; anda gate electrode over the upper portion of the work function metal layer.2. The semiconductor device of claim 1 , wherein the bottom portion of the work function metal layer has a lower effective work function value than the upper portion of the work function metal layer.3. The semiconductor device of claim 1 , wherein the upper portion of the work function metal layer is thicker than the bottom portion of the work function metal layer.4. The semiconductor device of claim 1 , wherein the work function material has a vacuum work function value smaller than about 4.4 eV.5. The semiconductor device of claim 1 , wherein the semiconductor substrate has a ...

METHOD OF MAKING A GATE STRUCTURE

A method of making a gate structure includes forming a trench in a dielectric layer. The method further includes forming a gate dielectric layer in the trench. The gate dielectric layer defines an opening in the dielectric layer. The method includes forming a gate electrode in the opening. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material. The first metal material has a recess. Forming the gate electrode includes filling an entire width of a top portion of the opening with a homogeneous second metal material. The homogeneous second metal material has a protrusion extending into the recess, and a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material. A top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material. 1. A method of making a gate structure , the method comprising:forming a trench in a dielectric layer;forming a gate dielectric layer in the trench, wherein the gate dielectric layer defines an opening in the dielectric layer; and filling a width of a bottom portion of the opening with a first metal material having a first resistance, wherein the first metal material has a recess; and', 'filling an entire width of a top portion of the opening with a homogeneous second metal material having a second resistance less than the first resistance, wherein the homogeneous second metal material has a protrusion extending into the recess, and a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material,, 'forming a gate electrode in the opening, wherein forming the gate electrode compriseswherein a top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material.2. The method of claim 1 , wherein filling the width of the bottom portion comprises forming the first metal material having a maximum ...

Semiconductor device and fabrication method thereof

A semiconductor device includes a substrate, a semiconductor fin extending from the substrate, a gate dielectric layer over the semiconductor fin, a metal nitride layer comprising a first portion over the gate dielectric layer and a second portion over the first portion, and a fill metal over the metal nitride layer. The second portion has an aluminum concentration greater than an aluminum concentration of the first portion.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A semiconductor device includes a semiconductor substrate, a pair of source/drain regions, and a gate stack. The pair of source/drain regions is on the semiconductor substrate. The gate stack is laterally between the source/drain regions and includes a gate dielectric layer over the semiconductor fin, a metal element-containing layer over the gate dielectric layer, and a fill metal layer over the metal element-containing layer. The metal element-containing layer has a dopant, and a concentration of the dopant in an upper portion of the metal element-containing layer is higher than a concentration of the dopant in a bottom portion of the metal element-containing layer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a semiconductor substrate, first gate structure, a first metal layer, a first protective layer, and a first contact plug. The first gate structure includes a plurality of first U-shaped layers stacked one another between the first gate spacers in a cross-sectional view and first gate spacers on opposite sides of the first U-shaped layers. The first metal layer is over the first U-shaped layers and has a different shape than the first U-shaped layers in the cross-sectional view. The first protective layer is over the first metal layer and between the first gate spacers. The first contact plug extends through the first protective layer and the first metal layer, and is in contact with the first gate structure. 1. A semiconductor device , comprising:a semiconductor substrate;a first gate structure comprising a pair of first gate spacers and a plurality of first U-shaped layers stacked one another between the pair of first gate spacers in a cross-sectional view;a first metal layer over the plurality of first U-shaped layers and having a different shape than the plurality of first U-shaped layers in the cross-sectional view;a first protective layer over the first metal layer and between the pair of first gate spacers; anda first contact plug extending through the first protective layer and the first metal layer, and in contact with the first gate structure.2. The semiconductor device of claim 1 , further comprising a first liner lining the first protective layer.3. The semiconductor device of claim 2 , wherein the first liner is in contact with the pair of first gate spacers.4. The semiconductor device of claim 2 , wherein the first liner comprises a vertical portion and a horizontal portion claim 2 , the vertical portion extends along a sidewall of one of the pair of first gate spacers claim 2 , and the horizontal portion extends along top ends of the plurality of first U-shaped layers.5. The semiconductor device of claim 4 , wherein the ...

METHOD OF MAKING A GATE STRUCTURE

A method of making a gate structure includes forming a gate electrode in an opening defined by a gate dielectric layer having a top surface. Forming the gate electrode includes filling a width of a bottom portion of the opening with a first metal material having a first resistance. Forming the gate electrode further includes defining a recess in the first metal material. Forming the gate electrode further includes filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material. 1. A method of making a gate structure , the method comprising: filling a width of a bottom portion of the opening with a first metal material having a first resistance;', 'defining a recess in the first metal material; and', 'filling an entire width of a top portion of the opening and the recess with a homogeneous second metal material having a second resistance less than the first resistance, wherein a maximum width of the homogeneous second metal material is equal to a maximum width of the first metal material, and the top surface of the gate dielectric layer is co-planar with a top surface of the homogeneous second metal material., 'forming a gate electrode in an opening defined by a gate dielectric layer having a top surface, wherein forming the gate electrode comprises2. The method of claim 1 , wherein filling the width of the bottom portion of the opening with the first metal material comprises depositing the first metal material over the gate dielectric claim 1 , and the deposited first metal material includes a gap located within the opening.3. The method of claim 2 , wherein defining the recess comprises depositing a sacrificial layer ...

Stress relieving film for semiconductor packages

Techniques for reducing the mechanical stress imposed upon semiconductor dice by protective molding compounds during times of temperature fluctuation. A thermoplastic material is attached to a top surface of a die to relieve the stress. The thermoplastic material serves as a cushion between the die and the molding compound when the components expand and contract. The thermoplastic material can be shaped such that it does not cover bond pads on the surface of a die.

Fabrication method for semiconductor device having metal gate stack

Method for manufacturing a semiconductor device

A method for manufacturing a semiconductor device includes: depositing metal sputtered from a metal target on a semiconductor structure having a recess, so as to fill the recess; and oxidizing the metal on the semiconductor structure to turn the metal into dielectric.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.

Integrated circuit devices and fabrication methods thereof

Etching back and selective deposition of metal gate

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Low stress cavity package

The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity.

Contact Structures In Semiconductor Devices

A semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. The method includes forming first and second source/drain (S/D) regions on first and second fin structures, forming a first dielectric layer between the first and second S/D regions, forming first and second gate-all-around (GAA) structures on the first and second fin structures, forming a second dielectric layer on the first and second GAA structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second GAA structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.

Etching back and selective deposition of metal gate

A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Semiconductor device and fabrication method thereof

A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.