ПРИВЕДЕНИЕ В КОНТАКТ УСТРОЙСТВА С ПРОВОДНИКОМ

Изобретение относится к области приведения в контакт ОСИД с проводником. В способе для приведения в контакт ОСИД с проводником, ОСИД содержит подложку, по меньшей мере, с одной ячейкой, область контакта и инкапсулирующую оболочку, содержащую тонкую пленку, которая содержит нитрид кремния, карбид кремния или оксид алюминия, причем инкапсулирующая оболочка инкапсулирует, по меньшей мере, область контакта, а способ содержит этапы компоновки проводника на инкапсулирующей оболочке и взаимного соединения проводника с областью контакта, без предварительного удаления инкапсулирующей оболочки между проводником и областью контакта. Это изобретение обладает преимуществом в том, что инкапсулирующую оболочку между проводником и областью контакта не надо предварительно удалять. 2 н. и 7 з.п. ф-лы, 4 ил.

Verfahren zur Verstärkung eines Halbleiterwafers und verstärkter Halbleiterwafer

Verfahren zur Anordnung von Bauelementen mittels Kleber

Verfahren zur Herstellung einer elektrischen Verbindung für eine integrierte Schaltung.

Connecting wires for semiconductor device - using wires of copper and tin or similar alloy and connecting to aluminium electrodes

The method of forming a connection between conductor strips (2,3) and a semiconductor device (5) such as a transistor, uses thin conductor wires (8) between the strips and the aluminium zones (6,7) forming the base and emitter electrodes. Instead of using gold conductors, a copper-tin, or a copper-tin-lead or a copper-tin-indium alloy is used. The first alloy has a 20 to 60 percent by weight of copper. The second alloy has a 50/40/10 mixture by weight, and the third alloy also has a 50/40/10 mixture.

ELEKTRONISCHE INTEGRIERTE SCHALTUNG MIT MINDESTENS EINEM ELEKTRONISCHEN BAUELEMENT

Verfahren zum Herstellen einer Halbleiteranordnung.

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

Verfahren zum Herstellen eines gestapelten Chip-Paketes

Verfahren zum Herstellen eines gestapelten Chip-Paketes, mit den Schritten: Anbringen eines ersten Substrates einschließlich eines ersten zentralen Fensters auf einem ersten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer ersten Verbindungsleitung, die den ersten Halbleiter-Chip und das erste Substrat verbindet; Anbringen eines zweiten ein zweites zentrales Fenster aufweisenden Substrates auf einem zweiten Halbleiter-Chip mit einer Vielzahl von auf dem zentralen Teil angeordneten Verbindungsplatten; Bilden einer zweiten Verbindungsleitung, die den zweiten Halbleiter-Chip und das zweite Substrat verbindet; Zusammenführen der Rückseiten des sich ergebenden ersten und des sich ergebenden zweiten Halbleiter-Chips; Bilden einer dritten Verbindungsleitung, die das erste und das zweite Substrat verbindet; Bilden eines Gusskörpers, welcher die erste, die zweite und die dritte Verbindungsleitung überdeckt; und Anbringen einer leitenden ...

Sinterwerkstoff, Sinterverbindung sowie Verfahren zum Herstellen eines Sinterverbindung

Die Erfindung betrifft einen Sinterwerkstoff mit metallischen, mit einer organischen Beschichtung versehenen Strukturpartikeln. Erfindungsgemäß ist vorgesehen, dass nicht-organisch beschichtete, metallische und/oder keramische, beim Sinterprozess nicht ausgasende Hilfspartikel (7) vorgesehen sind. Ferner betrifft die Erfindung eine Sinterverbindung (1) sowie ein Verfahren zum Herstellen einer Sinterverbindung (1).

Halbleiterpackung und -modul, Herstellungsverfahren und elektronisches Bauelement

Die Erfindung bezieht sich auf eine Halbleiterpackung mit gestapelten Halbleiterchips, auf ein Halbleitermodul mit einer derartigen Packung, auf ein Verfahren zur Herstellung der Halbleiterpackung sowie auf ein elektronisches Bauelement, das ein derartiges Modul beinhaltet. Eine Halbleiterpackung gemäß der Erfindung beinhaltet ein Packungssubstrat (200) mit einem Durchkontakt (220s), wenigstens einen Halbleiterchip (100, 120), der auf dem Packungssubstrat gestapelt ist, einen thermischen Grenzflächenfilm (132), der auf dem Halbleiterchip gestapelt ist, eine Packungsabdeckung (300), die in Kontakt mit dem thermischen Grenzflächenfilm und über dem Halbleiterchip positioniert ist, und eine Packungshaftstruktur (310) zwischen dem Durchkontakt und einem Teil der Packungsabdeckung. Verwendung in der Halbleiterbauelementtechnologie.

Electrical assembly comprises cooler structure and electrical component on metal-ceramic substrate having electrical module, where electrical module comprises two metal-ceramic substrates

Electrical assembly comprises cooler structure and an electrical component (6) on a metal-ceramic substrate (4,5) having electrical module. The electrical module comprises two metal-ceramic substrates, where each substrate includes a ceramic layer (7,10), which are provided with partially structured metal plating (9,12). An active cooler (2,3) and an electrical component are also provided between two metal-ceramic substrates, which are thermally connected.

Verfahren und Klebstoff zur Flip-Chip-Kontaktierung

Zur Flip-Chip-Kontaktierung wird ein elektrisch leitende, verformbare Partikel 10 enthaltender Klebstoff 11 auf ein mit Kontaktflächen 12 versehenes Substrat 13 aufgetragen, ein mit Kontaktflächen 14 versehener Chip 15 in der richtigen Position zum Substrat 13 plaziert, der Klebstoff 11 im Umfangsbereich 16 zwischen Chip 15 und Substrat 13 versiegelt und danach der unter dem Chip 15 befindliche Klebstoff 11 ausgehärtet. Der beim Aushärten auftretende Schrumpf bewirkt, daß Chip 15 und Substrat 13 gegeneinander gezogen werden, so daß auf äußere Druckanwendung während der Aushärtung des Klebstoffs 11 verzichtet werden kann.

Improvements in or relating to electrical couplings to semiconductor elements

... 753,488. Semiconductor devices. STANDARD TELEPHONES & CABLES, Ltd. July 2, 1954 [July 10, 1953], No. 19173/53. Class 37. [Also in Group XXII] A conductor wire 11 is electrically connected to a wafer 1 of semiconductor material such as germanium, by forming the wire in a double coiled spring, inserting the wafer between the two turns and soldering. Fig. 7 shows the arrangement used for the base electrode 13 of a junction transistor which is sealed in a glass envelope 14. The wire may be of phosphor bronze or beryllium copper. Stannous chloride may be used as a flux and pure tin as the solder. The envelope 14 may be filled with resin. Soldering may be affected with a minimum amount of heat by arranging for the solder to fill the coil on the germanium and may be carried out after the process for forming PN junctions in the device.

Electrical contacts with semiconductor bodies comprising silicon

... 1,106,260. Semi-conductor devices. SIEMENS A.G. 12 Dec., 1966 [11 Dec., 1965], No. 55640/66. Heading H1K. A contact member 8 fixed to a body 4 formed in a semi-conductor material which includes silicon, is made of a material comprising titanium and silicon; e.g. titanium disilicide or a variant thereof of higher silicon content; and has a coating 11 comprising a mixture of silicon and titanium oxides covering the parts of its surface not actually in contact with the body 4. As shown a thermoelectric generator 1 includes two bodies 4, 5, e.g. of a germanium/silicon alloy, respectively doped with boron, gallium or indium, and phosphorus, arsenic or antimony to produce P and N type limbs. The contact member 8 forms a bridge at the hot end of the device, which is heated by a gas, while similar contact members 6, 7 at the liquid-cooled cold end provide external contacts to the device. Foils or grids 12-15 of tungsten or molybdenum may be interposed between the germanium/silicon bodies and the ...

Semiconductor fabrication with contact processing for wrap-around flange interface

Methods of joining components

Semiconductor wafer fabrication of inside-wrapped contacts for electronic devices

A method of soldering

Semiconductor diode device

... 1,080,560. Zener diodes. MOTOROLA Inc. Dec. 31, 1964 [Jan. 2, 1964], No. 53009/64. Heading H1K. A Zener diode, Fig. 3, consists of a wafer 23 of one conductivity type with a recrystallized region 30 and a surrounding diffused region 35 of the opposite type in one surface. The PN junction 36 between the diffused region and the wafer which has a breakdown voltage higher than that between the recrystallized region and the wafer is coated with a dielectric layer 28. Such diodes are made in multiple from a 0À007- 0À08 ohm cm. N-type silicon wafer by oxidizing its surface and photo-engraving annular apertures in the oxide. The wafer is then exposed to boron trioxide in an oxidising atmosphere to form annular P regions overlain with oxide. After gettering out metallic impurities, e.g. copper, by exposing the opposite surface to phosphorus pentoxide vapour and oxygen and then reoxidizing, circular apertures the peripheries of which overlie the diffused annuli are photo-engraved in the oxide. Aluminium ...

SEMICONDUCTOR DIE-ATTACH

Device for regulating the working depth of an implement connected to a tractor

... 954,491. Tractor power lift mechanisms. MASCHINENFABRIK FAHR A.G. June 2, 1960, No. 19540/60. Heading A1P. A feeler device for regulating the working depth of an implement attached to a tractor by a conventional three point power lift linkage comprises a roller 6 carried by a lever 7 pivoted to the implement at 16 and operating upon the control member of the power lift through a system of levers 8, 9, 10, bell crank 9a, 21, and a spring loaded sliding member 11. The bell crank 9a, 21 is connected to the lever 9 by a screw 25 which permits adjustment. Stops 26 and 27 limit the upward movement of the lever 7 and facilitate carrying the feeler in a transport position.

Improvements in or relating to methods of wetting bodies and securing bodies together

A semi-conductor such as germanium is wetted by applying an oxide of a metal or semi-conductor in powder form and heating in a reducing atmosphere to reduce the oxide. The semi-conductor may be joined to a metal body by placing the powdered oxide between the semi-conductor and the metal body and heating in a reducing atmosphere. The oxides may be those of germanium, lead, indium, bismuth, nickel or cadmium. A nickel plate is joined to a germanium body by means of powdered germanium dioxide placed between the parts, the assembly being heated to 750 DEG C. in a mixture of inert gas and hydrogen. A germanium crystal may also be heated with germanium and lead by heating powdered germanium dioxide and lead at 750 DEG C. in a mixture of inert gas and hydrogen.

Method of manufacturing semiconductor devices

... 1,113,217. Semi-conductor devices. MATSUSHITA ELECTRONICS CORPORATION. 20 Oct., 1965 [26 Oct., 1964], No. 44440/65. Heading H1K. Connections are made to electrodes on a semiconductor device using a transparent flat insulator plate having conductive patterns coated thereon. A silicon body 1 having base 2 and emitter 3 regions therein is joined to metal base 16 by gold alloy 17. Metal pins 19 and 20 are mounted in glass holders 18 and are joined to metallic leads 10 and 11 by solder 21. The leads 10 and 11 are formed on a glass slide 9 which has notches 14 and 15 to fit around pins 19 and 20. The base 5 and emitter 6 electrodes are led out through oxide film 4 and joined to the leads 10 and 11 at 7 and 8. The transparent substrate 9 enables the leads to be positioned over the electrodes using a microscope and then pressure bonded. In another embodiment (Fig. 4, not shown) a P-type germanium mesa has leads on transparent substrate joined to it. The mass production of planar transistor units ...

SUPPORTS FOR SEMICONDUCTOR CRYSTALS

... 1315401 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 24 June 1970 [27 June 1969 24 Jan 1970] 30684/70 Heading H1K A support for a semi-conductor body comprises a metal base member of iron, an iron alloy, copper, nickel or a copper or nickel alloy, an outer layer of gold providing a surface for securing a semi-conductor body to the support, and an intermediate layer between the base member and gold layer of a metal which crystallizes in a hexagonal close packing arrangement. The intermediate layer may be of cobalt, osmium, rhenium, ruthenium, titanium or zirconium. Leads may pass through the base member insulated therefrom by glass. The body may be secured to the gold layer by a goldsilicon eutectic. The intermediate layer is said to prevent the grain structure of the base member from influencing the structure of the gold layer, such influence normally causing poor solder joints.

CONDUCTION-COLED CIRCUIT PACKAGE AND METHOD OF FABRICATION

Improvements in or relating to methods of soldering

... 821,551. Soldering; welding by pressure. GENERAL ELECTRIC CO. Ltd. May 3, 1957 [May 4, 1956; March 22, 1957], Nos. 13954/56 and 9417/57. Class 83 (4). [Also in Group XXXVI] In soldering two members together, both of metal or one of metal and the other a semiconductor, a metal member has bonded to it, prior to the heating operation, solder, in the solid state, to be used in the soldering operation, the bond being brought about by pressing together clean mating surfaces on the solder and the member. In making a transistor a plate 1, Fig. 3, of N-type germanium is provided with an indium emitter electrode 2 and an indium collector electrode 3 by cold bonding. The face of the plate on which is bonded the electrode 2 is soldered to one side of an annular dished nickel mount 4 having an indium bead 10 cold-bonded to the other side. The mount is cleaned by heating in dry hydrogen to 1000‹ C., a solder washer 11 of 60% tin, 40% lead, by volume, is scraped on each face and fitted into the mount ...

Bonding of metallic leads to semiconductor elements

... 881,834. Semi-conductor devices. WESTERN ELECTRIC CO. Inc. Oct. 29, 1957 [Oct. 31, 1956], No. 14256/61. Divided out of 881,832. Class 37. A lead of gold, silver, aluminium, copper or gold-plated or tinned copper is bonded to a strip of gold or aluminium 1 mil. wide on a semi-conductor body by pressing the parts together at a temperature above 100‹ C. but below the lowest eutectic temperature of any combination of the materials in contact, and the dislocation forming and displacing temperatures of the semiconductor, and maintaining the pressure and temperature long enough to make a strong low resistance bond. In an example, 1 mil. wide strips 44, 46 of aluminium and gold respectively are first alloyed to a mesa 52 formed on a germanium or silicon block. Leads 48, 50 of gold and aluminium respectively are then pressed against the alloyed strips in a press for 5 seconds to 15 minutes under a pressure sufficient to deform the leads by from 10 to 20%. The electrodes thus formed constitute the ...

Improvements in or relating to germanium transistors

... 1,029,116. Transistors. SIEMENS & HALSKE A.G. June 17, 1964 [June 19, 1963], No. 25018/64. Heading H1K. A germanium transistor in which the collector zone is of higher resistivity than the base zone and which is attached by its collector zone to a Fe-Ni-Co alloy mounting plate may have its performance impaired by back injection of minority carriers present as impurities in the alloy. To avoid this the invention proposes the use of an alloy in which chromium and manganese and Group III and Group V elements are present, if at all, only in insignificant amounts. In practise this is achieved by mixing highly pure iron, cobalt and nickel and alloying them by sintering and by taking precautions that the mounting plate does not become contaminated during assembly of the device: e.g. by attaching the alloy mounting plate, carrying the transistor, to its permanent mounting only after the latter has been provided with its lead-out wires so that the alloy plate is not exposed to the high temperature ...

Improvements in or relating to the manufacture of semi-conductor devices

... 775,191. Welding by pressure. GENERAL ELECTRIC CO., Ltd. Aug. 19, 1955 [Aug. 23, 1954], No. 24500/54. Class 83 (4). [Also in Group XXXVI] In the manufacture of a semi-conductor device in a sealed envelope, at least one seal is made by cold pressure welding, after the operative part of the device is mounted in the envelope. Fig. 1 shows a PN junction rectifier comprising a germanium wafer 3 on an oxygen-free high conductivity copper base I and having an alloy electrode comprising a bead of indium 5 and lead wire 7. The assembly is completed by placing a copper cover-plate 8 on to base 1 and cold welding the flanges 11 and 12. The lead wire 7 which may be of nickel, passes through, and is cold welded to, nickel tube 10 which is insulated from cover 8 by a glass region 9. In Fig. 2, which shows the apparatus for the cold welding, steel punches 15 and 16 sliding in tube 13, compress the flanges 11 and 12 together. A groove 12 in the base 1 accommodates the flow of metal. Wire 7 is welded to ...

METHOD AND APPARATUS FOR THE PRODUCTION OF MODULAR ONES MEHRFACHASSEMBLAGEN

PROCEDURE FOR STICKING SUBSTRATES USING A LIGHT-ACTIVATE-CASH ADHESIVE FOIL

HOCHSTROM-GLEICHRICHTERANORDNUNG

MICROWAVE MINIATURE HOUSING AND PROCEDURE FOR THE PRODUCTION OF THIS HOUSING

PROCEDURE FOR THE PLASMA-STRENGTHENED CONNECTION AND BY PLASMA-STRENGTHENED CONNECTION PRODUCED COMPOUND STRUCTURES

PROCEDURE FOR THE PRODUCTION OF A MATRIX FOR THE DETECTION OF ELECTROMAGNETIC RADIATION IN PARTICULAR INFRARED RADIATION

LAYOUT AND PROCEDURE FOR AN ARRANGEMENT WITH SEGMENTED BLM (BALL LIMITING METALLURGY) FOR EINUND OF EXITS

PROCEDURE FOR SOLDERING ELECTRONIC ELEMENTS WITH SOLDERING PEAKS ON A SUBSTRATE

COMPOSITIONS; PROCEDURE AND DEVICES FOR LEAD FREE HIGH TEMPERATURE SOLDER

PROCEDURE FOR the VERSCHWEIßEN OF TWO PARTS WITH THE HELP OF a SOLDERING MATERIAL

PROCEDURE FOR MANUFACTURING SOLDER BUMPS AND RESULTING STRUCTURE.

PROCEDURE FOR THE PRODUCTION OF SEMICONDUCTOR MICROCHIP

SEMICONDUCTOR ARRANGEMENT WITH SWITCHES ELECTRICAL CONNECTIONS, CONSTRUCTION UNIT THEREBY AND ITS MANUFACTURING PROCESSES

Metallic crystal carrier for a semiconductor crystal

PROCEDURE FOR ANODIC CONNECTION WITH LIGHT RADIATION

Procedure for connecting a metal pus with a semiconductor body

Solar cell and magnetically self-assembled solar cell assembly

Module and method of making same

Adhesive agent, method for connecting wiring terminals and wiring structure

METHOD OF APPLYING NO-FLOW UNDERFILL

Semiconductor wafer fabrication of die-bottom contacts for electronic devices

HIGH-DENSITY INTERCONNECTION OF TEMPERATURE SENSITIVE ELECTRONIC DEVICES

Method for adhering substrates using light activatable adhesive film

Method and materials for printing particle-enhanced electrical contacts

Electrical contact structures from flexible wire

HIGH CURRENT-RECTIFIER ARRANGEMENT

HIGH PERFORMANCE INTEGRATED CIRCUIT CHIP PACKAGE AND METHOD OF MAKING SAME

A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The multilayer wiring substrate may be formed by a self-aligned thin film wiring method, with a self-aligned lift off method being employed to form internal wiring planes. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct ...

ELECTROSTATICALLY BONDED SEMICONDUCTOR-ON-INSULATOR MOS DEVICE, A METHOD OF MAKING THE SAME

AN ELECTROSTATICALLY BONDED SEMICONDUCTOR-ON-INSULATOR MOS DEVICE, AND A METHOD OF MAKING THE SAME An electrostatically bonded semiconductor-on-insulator and particularly semiconductor-on-sapphire MOS devices are made of bulk materials. A semiconductor body of a bulk material of less than about 75 microns in thickness is electrostatically bonded to an insulator substrate of a bulk material. A dielectric layer of between 500 and 2,000 Angstroms in thickness is then formed on the semiconductor body to make a MOS semiconductor device and preferably a MOS field-effect transistor. The semiconductor-on-insulator MOS device is preferably made by first forming a major surface of the dielectric substrate and a major surface of the semiconductor body in planar configurations, applying a metal layer to the opposed major surface of the insulator substrate, and placing the planar surfaces of the body and substrate in intimate contact. The assembly is then heated to at least 300.degree.C. and preferably ...

MULTIPLE SEMICONDUCTOR CHIP ASSEMBLY AND MANUFACTURE

SEMICONDUCTOR DEVICE WITH COMPLIANT ELECTRICAL TERMINALS, APPARATUS INCLUDING THE SEMICONDUCTOR DEVICE, AND METHODS FOR FORMING SAME

A semiconductor device (e.g., a chip scale package or CSP) is described including multiple input/output (I/O) pads arranged on a surface of a semiconductor substrate, a compliant dielectric layer, an outer dielectric layer, and multiple electrically conductive, compliant interconnect bumps (i.e., compliant bumps). The compliant bumps may form electrical terminals of the semiconductor device. The compliant dielectric layer is positioned between the outer dielectric layer and the surface of the semiconductor substrate. The outer dielectric layer and the compliant dielectric both have multiple openings (i.e., holes) extending therethrough. Each of the compliant bumps is formed upon a different one of the I/O pads, and extends through a different one of the openings in the first compliant dielectric layer and the outer dielectric layer. Each of the compliant bumps includes an electrically conductive, compliant body, and an electrically conductive, solderable conductor element. The compliant ...

CONDUCTION-COOLED CIRCUIT PACKAGE AND METHOD FOR MAKING SAME

REACTIVE FOIL ASSEMBLY

HALO-HYDROCARBON POLYMER COATING

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multilayer coating.

PROCESS FOR BRAZING METALLIZED COMPONENTS TO CERAMIC SUBSTRATES

A process for brazing a metallized component to a metallized ceramic-based substrate comprising the steps of: a) applying a second conductor composition over the metallizations on the substrate such that the metallizations are covered by said second conductor composition which consists essentially of a metal powder and an organic medium; b) drying said second conductor composition; c) firing said second conductor composition at a temperature sufficient to sinter the metal powder of the second conductor composition and drive off said organic medium thereby forming a second metallization layer; d) forming an assembly by positioning at least one metallized component on said second metallization layer and a brazing composition at the component-second metallization layer interface; and e) heating said assembly at a temperature sufficient for said brazing composition to form a joint between said component and said second metallization layer.

AFFINITY BASED SELF-ASSEMBLY SYSTEMS AND DEVICES FOR PHOTONIC AND ELECTRONIC APPLICATIONS

This invention relates to techniques which utilize programmable functionalized self-assembling nucleic acids, nucleic acid modified structures, and other selective affinity or binding moieties as building blocks. The invention is a method for the fabrication of micro scale and nanoscale devices comprising the steps of: fabricating first component devices on a first support, releasing at least one first component device from the first support, transporting the first component device to a second support, and attaching the first component device to the second support. The invention also provides for orienting a structure in an electric field, reacting affinity sequences, and assembling chromophoric structures by photoactivation.

LOW TEMPERATURE METHOD AND COMPOSITIONS FOR PRODUCING ELECTRICAL CONDUCTORS

A composition for matter having a metal powder or powders for specified characteristics in a Reactive Organic Medium (ROM). These compositions can be applied by any convenient printing process to produce patterns of electrical conductors on temperature-sensitive electronic substrates. The patterns can be thermally cured in seconds to form pure metal conductors at a temperature low enough to avoid damaging the substrate.

Halbleitereinrichtung mit mindestens einem flächenhaften p-n-Übergang

Verfahren zur Herstellung einer mit einer hermetisch verschlossenen Ummantelung versehenen Halbleiter-Vorrichtung und gemäss dem Verfahren hergestellte Halbleiter-Vorrichtung

Dispositif semi-conducteur et procédé de fabrication de celui-ci

Halbleiter-Kristallvorrichtung

Halbleitereinrichtung mit mindestens einem flächenhaften p-n-Übergang

Verfahren zur Herstellung eines elektrischen Halbleitergerätes mit einkristallinem Halbleiterkörper

Einrichtung mit in einer Fassung angeordneter Gleichrichterzelle

Verfahren zur Herstellung von Halbleitereinrichtungen

Procédé d'établissement d'une liaison entre un conducteur métallique et un élément semi-conducteur

Verfahren zur Herstellung einer eine Legierungselektrode aufweisenden Halbleitervorrichtung und nach dem Verfahren hergestellte Halbleitervorrichtung

Elektrisches Halbleiterbauelement, Verfahren zu seiner Herstellung und Ofen zur Durchführung dieses Verfahrens

Verfahren zum Kontaktieren von in Halbleiterkörpern einlegierten Elektroden

Verfahren zur Herstellung einer Halbleiteranordnung

Verfahren zum Herstellen eines gut wärmeleitenden und elektrisch gut leitenden Kontaktes zwischen zwei Körpern, welche mit zwei angepassten Flächen aufeinandergepresst werden

Halbleiterbauelement

Signalumformungseinrichtung mit einem Körper aus Halbleitermaterial.

Verfahren und Vorrichtung zum Anbringen von Kontaktorganen an Halbleiterkörpern

Halbleiteranordnung

Halbleitervorrichtung mit wenigstens einer aluminiumenthaltenden Elektrode

Verfahren zum Montieren einer Halbleitervorrichtung

Halbleiteranordnung

Verfahren zur Herstellung einer Halbleitervorrichtung z. B. eines Transistors

Verfahren zum Herstellen eines Transistors

Halbleiteranordnung

Halbleiteranordnung

Verfahren zum Herstellen einer Vielzahl von Halbleiteranordnungen

Verfahren zur Herstellung einer Halbleiteranordnung auf der Basis eines Halbleiterkörpers und nach diesem Verfahren hergestellte Halbleiteranordnung

Bistabile Halbleitervorrichtung

Halbleiteranordnung und Verfahren zu ihrer Herstellung

Procédé de fabrication d'un dispositif redresseur au silicium

Verfahren zur Herstellung einer Halbleiteranordnung mit einem Silicium-Halbleiterkörper

Verfahren zur Herstellung von Spitzenelektroden

Halbleitervorrichtung

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Stacked semiconductor package and method of fabricating the same

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Method and electrostatic transfer stamp for transferring semiconductor dice using electrostatic transfer printing techniques

A transfer stamp that can be charged with a spatial pattern of electrostatic charge for picking up selected semiconductor dice from a host substrate and transferring them to a target substrate. The stamp may be bulk charged and then selectively discharged using irradiation through a patterned mask. The technique may also be used to electrostatically transfer selected semiconductor dice from a host substrate to a target substrate.

Semiconductor device and method of manufacturing the same

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Methods of fabricating package stack structure and method of mounting package stack structure on system board

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Package systems and manufacturing methods thereof

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Contact pad

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Heat radiation material, electronic device and method of manufacturing electronic device

The electronic device includes a heat generator 54, a heat radiator 58, and a heat radiation material 56 disposed between the heat generator 54 and the heat radiator 58 and including a plurality of linear structures 12 of carbon atoms and a filling layer 14 formed of a thermoplastic resin and disposed between the plurality of linear structures 12.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

Apparatuses and methods to enhance passivation and ild reliability

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

Contact Metal for Hybridization and Related Methods

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

Methods and structures for forming integrated semiconductor structures

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.

Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads

A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Semiconductor device and method for production of semiconductor device

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Anti-reflection structures for cmos image sensors

Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Method to realize flux free indium bumping

A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited.

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Compliant printed circuit semiconductor package

A method of making a package for a semiconductor device having electrical terminals. At least one semiconductor device is located on a substrate. A first dielectric layer is printed on at least a portion of the semiconductor device to include first recesses aligned with a plurality of the electrical terminals. A conductive material is deposited in the first recesses forming contact members. A second dielectric layer is printed on at least a portion of the first dielectric layer to include second recesses aligned with a plurality of the first recesses. A conductive material is deposited in at least a portion of the second recesses to include a circuit geometry and a plurality of exposed terminals. A compliant material is deposited in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals.

SILVER-INDIUM TRANSIENT LIQUID PHASE METHOD OF BONDING SEMICONDUCTOR DEVICE AND HEAT-SPREADING MOUNT AND SEMICONDUCTOR STRUCTURE HAVING SILVER-INDIUM TRANSIENT LIQUID PHASE BONDING JOINT

A silver-indium transient liquid phase method of bonding a semiconductor device and a heat-spreading mount, and a semiconductor structure having a silver-indium transient liquid phase bonding joint are provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices. 1. An Ag—In transient liquid phase (TLP) method of bonding a semiconductor device and a heat-spreading mount , comprising: 'forming a first Ag TLP bonding layer on a bottom of the semiconductor device;', 'forming a first bonding structure at a bottom side of the semiconductor device, including {'sub': 2', '2', '2, 'forming a multi-layer structure having a second Ag TLP bonding layer on a top of the heat-spreading mount, an intermediate transient AgInIMC (intermetallics compound) layer on a top of the Ag TLP bonding layer, an In TLP bonding layer on a top of the intermediate transient AgInIMC layer, and an anti-oxidation AgInIMC capping layer on a top of the In TLP bonding layer;'}, 'forming a second bonding structure at a top side of the heat-spreading mount, including{'sub': 2', '2, 'performing an Ag—In bonding process on the first bonding structure and the second bonding structure, thereby converting the first bonding structure and the second bonding structure into a bonding joint including a sandwich bonding structure having a first Ag—In solid solution layer in contact with the semiconductor device, a second Ag—In solid solution layer in contact with the heat-spreading mount, and an AgIn IMC layer sandwiched by the first Ag—In solid solution layer and the second Ag—In solid solution layer, such that the bonding joint joins the semiconductor device and the heat- ...

SEMICONDUCTOR CHIP ASSEMBLY AND METHOD FOR MAKING SAME

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly. 120-. (canceled)21. A method for forming a microelectronic assembly comprising:providing a substrate including a first dielectric layer having a first composition having electrically conductive elements thereon, the first dielectric layer having a coefficient of thermal expansion of at least 10 parts per million/° C.;forming a second dielectric layer overlying the first dielectric layer having a surface at which electrically conductive substrate contacts respectively overlying the conductive elements are exposed, the second dielectric layer having a Young's modulus of less than about 2 GPa;electrically connecting the conductive elements respectively with the substrate contacts by conductive vias extending through the second dielectric layer, the vias being disposed entirely below the respective substrate contacts; andjoining the substrate contacts to respective contacts exposed at a face of a microelectronic element, the surface of the substrate confronting the face of the microelectronic element.22. The method of claim 21 , wherein a ratio of a diameter of the conductive vias to a diameter of the respective substrate contacts is less than 40%.23. The method of claim 21 , wherein the vias extend through the second dielectric layer from substantially a center of a surface of the ...

Lead-Free Solder Ball

A lead-free solder ball is provided which suppresses interfacial peeling in a bonding interface of a solder ball, fusion defects which develop between the solder ball and solder paste, and which can be used both with Ni electrodes plated with Au or the like and Cu electrodes having a water-soluble preflux applied atop Cu. The lead-free solder ball for electrodes of BGAs or CSPs consists of 1.6-2.9 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn. It has excellent resistance to thermal fatigue and to drop impacts regardless of the type of electrodes of a printed circuit board to which it is bonded, which are Cu electrodes or Ni electrodes having Au plating or Au/Pd plating as surface treatment.

METHOD OF LIQUID ASSISTED BONDING

A method of liquid assisted bonding includes: forming a structure with a liquid layer between an electrode of a device and a contact pad of a substrate, and two opposite surfaces of the liquid layer being respectively in contact with the electrode and the contact pad in which hydrogen bonds are formed between the liquid layer and at least one of the electrode and the contact pad; and evaporating the liquid layer to break said hydrogen bonds such that at least one of a surface of the electrode facing the contact pad and a surface of the contact pad facing the electrode is activated so as to assist a formation of a diffusion bonding between the electrode of the device and the contact pad in which a contact area between the electrode and the contact pad is smaller than or equal to about 1 square millimeter. 1. A method of liquid assisted bonding , comprising:forming a structure with a liquid layer between an electrode of a device and a contact pad of a substrate and two opposite surfaces of the liquid layer being respectively in contact with the electrode and the contact pad, wherein hydrogen bonds are formed between the liquid layer and at least one of the electrode and the contact pad; andevaporating the liquid layer to break said hydrogen bonds such that at least one of a surface of the electrode facing the contact pad and a surface of the contact pad facing the electrode is activated so as to assist a formation of a diffusion bonding between the electrode of the device and the contact pad, wherein a contact area between the electrode and the contact pad is smaller than or equal to about 1 square millimeter.2. The method of claim 1 , wherein the surface of the electrode facing the contact pad and the surface of the contact pad facing the electrode are curved surfaces which are curved up or down in a thickness direction.3. The method of claim 1 , further comprising:applying an external pressure to compress the electrode and the contact pad during evaporating the ...

Stretchable Form of Single Crystal Silicon for High Performance Electronics on Rubber Substrates

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. 1. A stretchable semiconductor element comprising:a flexible substrate having a supporting surface; anda semiconductor structure having a curved internal surface, wherein at least a portion of said curved internal surface is bonded to said supporting surface of said flexible substrate.2. The stretchable semiconductor element of wherein said semiconductor structure is a bent semiconductor structure.3. The stretchable semiconductor element of wherein said bent semiconductor structure has a wave-shaped claim 2 , wrinkled claim 2 , coiled or buckled conformation.4. The stretchable semiconductor element of wherein said bent semiconductor structure is under strain.5. The stretchable semiconductor element of wherein said bent semiconductor structure is under strain selected over the range of about 1% to about 30%.6. The stretchable semiconductor element of wherein said curved internal surface has at least one convex region claim 1 , at least one concave region or a combination of at least one convex region and at least one concave region.7. The stretchable semiconductor element of wherein said curved internal surface has a contour profile comprising a periodic wave or an aperiodic wave.8. The stretchable semiconductor element of wherein said bent semiconductor structure has a conformation comprising a ...

ELECTRONIC DEVICES FORMED IN A CAVITY BETWEEN SUBSTRATES

An electronic device includes a first substrate and a second substrate. A side wall joins the first substrate to the second substrate. The side wall includes a first alloy layer of a first metal and a second metal bonded directly to an upper surface of the first substrate and a second alloy layer of the first metal and a third metal disposed on top of the first alloy layer and bonded directly to a lower surface of the second substrate, the second metal and the third metal being different from each other and from the first metal. An electronic circuit is disposed on the lower surface of the second substrate within a cavity defined by the lower surface of the first substrate, the upper surface of the second substrate, and the side wall. 1. An electronic device comprising:a first substrate and a second substrate;a side wall joining the first substrate to the second substrate, the side wall including a first alloy layer of a first metal and a second metal bonded directly to an upper surface of the first substrate and a second alloy layer of the first metal and a third metal disposed on top of the first alloy layer and bonded directly to a lower surface of the second substrate, the second metal and the third metal being different from each other and from the first metal; andan electronic circuit disposed on the lower surface of the second substrate within a cavity defined by the lower surface of the first substrate, the upper surface of the second substrate, and the side wall.2. The electronic device of wherein the side wall is disposed about peripheries of the first and second substrates.3. The electronic device of wherein the second substrate includes a piezoelectric body.4. The electronic device of wherein the electronic circuit includes at least one of a film bulk acoustic resonator claim 3 , a bulk acoustic wave element claim 3 , a solidly mounted resonator claim 3 , and a surface acoustic wave element.5. The electronic device of wherein the first metal has a ...

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures. 1. A bonding system comprising:a support structure for supporting a first semiconductor element, the first semiconductor element including a plurality of first conductive structures;a bonding tool for carrying a second semiconductor element including a plurality of second conductive structures, and for applying ultrasonic energy to the second semiconductor element to form tack bonds between ones of the plurality of second conductive structures and corresponding ones of the plurality of first conductive structures.2. The bonding system of wherein claim 1 , after forming the tack bonds claim 1 , the bonding tool is configured to form completed bonds between the ones of the plurality of second conductive structures and corresponding ones of the plurality of first conductive structures.3. The bonding system of wherein the bonding tool is a heated bonding tool claim 2 , and the bonding tool applies heat to the second semiconductor element for forming the completed bonds.4. The bonding system of further comprising a second bonding tool claim 1 , wherein claim 1 , after forming the tack bonds by the bonding tool claim 1 , the second bonding tool is configured to form completed bonds between the ones of the plurality of second conductive structures and corresponding ones of the plurality of first conductive structures.5. The bonding system of wherein the second bonding tool is a heated bonding tool claim 4 , and the second bonding tool applies ...

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. 1. A structure comprising:a substrate having a first region and a second region, the substrate also having a first surface and a second surface remote from the first surface, wherein the first surface extends in first and second lateral directions to define a first plane;electrically conductive elements exposed at the first surface of the substrate within the second region;wire bonds having bases bonded to respective ones of the conductive elements and free ends remote from the substrate and remote from the bases, at least one of the wire bonds having a shape such that the at least one wire bond defines an axis between the free end and the base thereof coincident with a side surface of the at least one wire bond and such that the at least one wire bond defines a second plane, a bent portion of the at least one wire bond extending away from the axis within the second plane, wherein the entire at least one wire bond is positioned on one side of the axis and a substantially straight portion of the at least one wire bond extends between the free end ...

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

SEMICONDUCTOR DEVICE

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. 1. A semiconductor device comprising:(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;(c) a plurality of protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements; and(e) a plurality of bump electrodes formed over the first insulating film, the plurality of bump electrodes being arranged along a first long edge of the pair of long edges,wherein the plurality of bump electrodes are bump electrodes for receiving input signals from an external device,wherein the plurality of protection elements are electrically coupled between the respective plurality of bump electrodes and the internal circuit,wherein the plurality of bump electrodes include a first bump electrode and a second bump electrode,wherein the plurality of protection elements include a first protection element and a second protection element,wherein the first protection element electrically coupled to the first bump electrode is disposed at a position overlapped with the first bump electrode in a planar view when ...

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of AgSn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and wherein a plurality of wires containing Ag are arranged extended from an outside-facing periphery of the alloy layer. 1. A semiconductor device in which a semiconductor element is bonded to a mounting board , said semiconductor device comprising:an alloy layer sandwiched between a first Ag layer formed on the mounting board and a second Ag layer formed on the semiconductor element;{'sub': '3', 'wherein the alloy layer contains an intermetallic compound of AgSn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and a plurality of wires containing Ag are arranged as being extended from an outside-facing periphery of the alloy layer.'}2. The semiconductor device of claim 1 , wherein the wires are arranged as being extended in the same direction.3. The semiconductor device of claim 1 , wherein the wires are arranged as being extended radially from the outside-facing periphery of the alloy layer.4. The semiconductor device of claim 1 , wherein claim 1 , in the wires claim 1 , as a material other than Ag claim 1 , there is added at least one of Pd claim 1 , Ni claim 1 , Cu claim 1 , Fe claim 1 , Au claim 1 , Pt claim 1 , Al claim 1 , Sn claim 1 , Sb claim 1 , Ti and P.5. The semiconductor device of claim 1 , wherein the semiconductor element is formed of a wide bandgap semiconductor material.6. (canceled)7. A semiconductor device fabrication method of fabricating a semiconductor device in which a semiconductor element is bonded to a mounting board claim 1 , said semiconductor device fabrication method comprising:a wire structure forming step of forming a wire structure in which a plurality of wires containing Ag are ...

TOOLING FOR COUPLING MULTIPLE ELECTRONIC CHIPS

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface. 1. A method comprising:constraining a portion of multiple chips adjacent a hardened material such that the hardened material and the multiple chips behave as a rigid body;transferring a force from the hardened material on the rigid body to the multiple chips to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element, without causing damage to the multiple chips or the bonding surface of the element; andremoving the hardened material from contact with the multiple chips.2. The method of claim 1 , further comprising moving the multiple chips constrained by the hardened material from a first location to a second location.3. The method of claim 1 , further comprising bonding each of the multiple chips to the element.4. The method of claim 1 , further comprising removing the rigid body using at least one of a chemical process claim 1 , a mechanical process claim 1 , or a chemical-mechanical process.5. The method of claim 1 , further comprising removing at least a portion of the hardened material through at least one of a chemical process claim 1 , a mechanical process claim 1 ...

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a polymer layer over the metal pad;forming a seed layer over the metal pad and extending over the polymer layer;forming a conductive pillar over the seed layer; and{'sub': 2', '2, 'wet etching the seed layer using an etchant comprising HO, wherein the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.'}2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the slope sidewall extends from a bottommost of a sidewall of the conductive pillar to a top surface of the polymer layer.3. The method for forming a semiconductor structure as claimed in claim 2 , wherein an inclination of the slope sidewall of the extending portion of the seed layer is different from an inclination of the sidewall of the conductive pillar.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an angle between the slope sidewall and a bottom surface of the seed layer is in a range from about 20° to about 80°.5. The method for forming a semiconductor structure as claimed in claim 1 , wherein the conductive pillar is directly formed on the seed layer.6. The method for forming a semiconductor structure as claimed in claim 1 , further ...

Package-on-package Assembly With Wire Bond Vias

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

There is provided a bonding wire that improves bonding reliability of a ball bonded part and ball formability and is suitable for on-vehicle devices. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinthe Cu alloy core material contains Ni,a concentration of Ni is 0.1 to 1.2 wt. % relative to the entire wire, anda thickness of the Pd coating layer is 0.015 to 0.150 □m.2. The bonding wire for a semiconductor device according to claim 1 , further comprising an Au skin layer on the Pd coating layer.3. The bonding wire for a semiconductor device according to claim 2 , wherein a thickness of the Au skin layer is 0.0005 to 0.050 □m.4. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material further contains at least one element selected from B, In, Ca, P and Ti, anda concentration of the elements is 3 to 100 wt. ppm relative to the entire wire.5. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material further contains Pt or Pd, anda concentration of Pt or Pd contained in the Cu alloy core material is 0.05 to 1.20 wt. %.6. The bonding wire for a semiconductor device according to claim 1 , wherein Cu is present at an outermost surface of the bonding wire. The present invention relates to a bonding wire for a semiconductor device used to connect electrodes on a semiconductor device and wiring of a circuit wiring board such as external leads.As a bonding wire for a semiconductor device which connects electrodes on a semiconductor device and external leads (hereinafter referred to as a “bonding wire”), a thin wire with a wire diameter of about 15 to 50 μm is mainly used today. For a bonding method with bonding wire, there is generally used a thermal compressive bonding technique with the aid of ultrasound, in which a general bonding device, a capillary tool used for bonding by ...

QUBIT DIE ATTACHMENT USING PREFORMS

Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary qubit device package includes a qubit die and a package substrate, where the qubit die is coupled to the package substrate using one or more preforms. In particular, a single preform may advantageously be used to replace a plurality of individual contacts, e.g. a plurality of individual solder bumps, electrically coupling the qubit die to the package substrate. Such packages may reduce design complexity and undesired coupling, and enable inclusion of larger numbers of qubits in a single qubit die. 1. A qubit device package , comprising:a qubit die having a first face and an opposing second face, where the qubit die includes one or more qubit devices, and where the first face of the qubit die includes a plurality of conductive contacts;a package substrate having a first face and an opposing second face, where the second face of the package substrate includes a plurality of conductive contacts; andan interconnect structure, coupling two or more of the plurality of conductive contacts at the first face of the qubit die with associated two or more conductive contacts at the second face of the package substrate.2. The qubit device package according to claim 1 , wherein the interconnect structure is a solder preform.3. The qubit device package according to claim 1 , wherein the interconnect structure is an indium preform.4. The qubit device package according to claim 1 , wherein the interconnect structure includes an electrically conductive material that is continuous between two or more of the plurality of conductive contacts at the first face of the qubit die and the associated two or more conductive contacts at the second face of the package substrate.5. The qubit device package according to claim 1 , wherein the interconnect structure is a preform comprising an electrically conductive core material coated with a ...

STRESS SENSOR FOR A SEMICONDUCTOR DEVICE

In a particular embodiment, an apparatus includes a stress sensor located on a first side of a semiconductor device. The apparatus further includes circuitry located on a second side of the semiconductor device. The stress sensor is configured to detect stress at the semiconductor device. In another particular embodiment, a method includes receiving data from a stress sensor located on a first side of a packaged semiconductor device. The packaged semiconductor device includes circuitry located on a second side of the packaged semiconductor device. The data indicates stress detected by the stress sensor. The method further includes performing a test associated with the packaged semiconductor device based on the data. 1. An apparatus comprising:a stress sensor located on a first side of a semiconductor device; andcircuitry located on a second side of the semiconductor device,wherein the stress sensor is configured to detect stress at the semiconductor device.2. The apparatus of claim 1 , wherein the stress sensor is configured to detect stress imposed on the circuitry.3. The apparatus of claim 2 , wherein the circuitry comprises an analog circuit.4. The apparatus of claim 1 , further comprising a package claim 1 , wherein the semiconductor device claim 1 , the stress sensor claim 1 , and the circuitry are integrated within the package.5. The apparatus of claim 4 , further comprising a second semiconductor device that is integrated within the package claim 4 , wherein the stress sensor is configured to detect stress imposed on the semiconductor device by the second semiconductor device.6. The apparatus of claim 1 , further comprising a connector formed on the second side of the semiconductor device claim 1 , the connector configured to couple the second side of the semiconductor device to a substrate via a flip chip process during an assembly process that connects the semiconductor device to the substrate.7. The apparatus of claim 6 , wherein the connector comprises a ...

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Multilayer pillar for reduced stress interconnect and method of making same

A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

COMPOSITION FOR CONDUCTIVE ADHESIVE, SEMICONDUCTOR PACKAGE COMPRISING CURED PRODUCT THEREOF, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME

Provided is a composition for conductive adhesive. The composition for conductive adhesive includes a heterocyclic compound containing oxygen and including at least one of an epoxy group or oxetane group, a reductive curing agent including an amine group and a carboxyl group, and a photoinitiator, wherein a mixture ratio of the heterocyclic compound and the reductive curing agent satisfies Conditional Expression 1 below. 1. A composition for conductive adhesive , comprising:a heterocyclic compound containing oxygen, the heterocyclic compound including at least one of an epoxy group or oxetane group;a reductive curing agent including an amine group and a carboxyl group; anda photoinitiator, {'br': None, 'i': b+c', 'a≤', 'a>', 'b≥', 'c>, '0.5≤()/1.5, 0, 0, 0\u2003\u2003[Conditional Expression 1]'}, 'wherein a mixture ratio of the heterocyclic compound and the reductive curing agent satisfies Conditional Expression 1 belowwhere ‘a’ denotes a mole number of a heterocycle in the heterocyclic compound, ‘b’ denotes a mole number of hydrogen bonded to a nitrogen atom of the amine group included in the reductive curing agent, and ‘c’ denotes a mole number of the carboxyl group.2. The composition for conductive adhesive of claim 1 , wherein the heterocyclic compound comprises at least one of bisphenol-A type epoxy resin claim 1 , bisphenol-F type epoxy resin claim 1 , novolac epoxy resin claim 1 , hydrogenated bisphenol-A type epoxy resin claim 1 , octylene oxide claim 1 , p-butyl phenol glycidyl ether claim 1 , butyl glycidyl ether claim 1 , cresyl glycidyl ether claim 1 , styrene oxide claim 1 , allyl glycidyl ether claim 1 , phenyl glycidyl ether claim 1 , butadiene dioxide claim 1 , divinylbenzene dioxide claim 1 , diglycidyl ether claim 1 , butanediol diglycidyl ether claim 1 , limonene dioxide claim 1 , vinylcyclohexene dioxide claim 1 , diethylene glycol diglycidyl ether claim 1 , 4-vinylcyclohexene dioxide claim 1 , cyclohexene vinyl monoxide claim 1 , (3 claim 1 ,4- ...

LEAD FRAME CONSTRUCT FOR LEAD-FREE SOLDER CONNECTIONS

An electronics packaging arrangement, a lead frame construct for use in an electronics packaging arrangement, and a method for manufacturing an electronics packaging arrangement. A lead frame made of copper, for example, includes a metallic barrier layer of nickel, for example, to prevent oxidation of the metal of the lead frame. A relatively thin wetting promoting layer of copper, for example, is provided on the metallic barrier layer to promote uniform wetting of a solder, such as a lead-free, zinc-based solder, onto the lead frame during a die connect process by which a chip is connected to the lead frame. A copper/zinc intermetallic layer is formed during the flow and solidification of the solder. Substantially all of the copper in the copper layer is consumed during formation of the copper/zinc intermetallic layer, and the intermetallic layer is sufficiently thin to resist internal cracking failure during manufacture and subsequent use of the electronics packaging arrangement. 110-. (canceled)11. A lead frame construct , comprising:a lead frame having a surface;a metallic barrier layer disposed on said surface of said lead frame; anda wetting promoting layer disposed on said metallic barrier layer.12. The construct of claim 11 , wherein the wetting promoting layer is selected from copper and a copper alloy.13. The construct of claim 11 , wherein the wetting promoting layer is selected from zinc claim 11 , bismuth claim 11 , tin claim 11 , indium claim 11 , gold claim 11 , silver claim 11 , palladium claim 11 , platinum and alloys thereof.14. The construct of wherein said wetting promoting layer has a thickness between 1 μm and 10 μm.15. The construct of claim 11 , wherein said metallic barrier layer comprises one of nickel and a nickel alloy claim 11 , and has a thickness between 1 μm and 10 μm.16. The construct of claim 11 , wherein the metallic barrier layer is a discontinuous layer over a plurality of die pad areas of the lead frame.17. An electronics ...

Semiconductor device and production method therefor

An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.

Forming a solder joint between metal layers

Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.

SEMICONDUCTOR STRUCTURE HAVING SILVER-INDIUM TRANSIENT LIQUID PHASE BONDING JOINT

A semiconductor structure having a silver-indium transient liquid phase bonding joint is provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices. 1. A semiconductor structure comprising:a semiconductor device;a heat-spreading mount;{'claim-text': ['a first Ag—In solid solution layer in contact with the semiconductor device;', 'a second Ag—In solid solution layer in contact with the heat-spreading mount; and', {'sub': ['2', '2'], '#text': 'an AgIn IMC (intermetallics compound) layer sandwiched by the first Ag—In solid solution layer and the second Ag—In solid solution layer, wherein a thickness of the AgIn IMC layer is larger than a thickness of the first Ag—In solid solution layer and larger than a thickness of the second Ag—In solid solution layer.'}], '#text': 'a bonding joint joining the semiconductor device and the heat-spreading mount, wherein the bonding joint includes a sandwich bonding structure, and the sandwich bonding structure includes:'}2. The semiconductor structure of claim 1 , further comprising a layer of a composite material of AgIn IMC and AgInIMC in contact with a lateral sidewall of the AgIn IMC layer and a top surface of the second Ag—In solid solution layer.3. The semiconductor structure of claim 2 , wherein the layer of the composite material of AgIn IMC and AgInIMC surrounds the lateral sidewall of the AgIn IMC layer.4. The semiconductor structure of claim 1 , wherein the sandwich bonding structure has a thickness of equal to or less than 3 μm.5. The semiconductor structure of claim 1 , whereinthe semiconductor device includes a first metallization layer at a bottom thereof and in contact with ...

Straight wirebonding of silicon dies

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask

A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

Multi-Stack Package-on-Package Structures

Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor device. The second semiconductor device and the first stacked semiconductor device are encapsulated. Electrical connections are formed on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.

Hybrid bonding structures, semiconductor devices having the same, and methods of manufacturing the semiconductor devices

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

ZN BASED LEAD-FREE SOLDER AND SEMICONDUCTOR POWER MODULE

Zn based lead-free solder is obtained in which its range of practical melting points is between 300° C. and 350° C. The Zn based lead-free solder includes a Cr content of 0.05 through 0.2 wt %, an Al content of 0.25 through 1.0 wt %, an Sb content of 0.5 through 2.0 wt %, a Ge content of 1.0 through 5.8 wt %, and a Ga content of 5 through 10 wt %; or the Zn based lead-free solder includes a Cr content of 0.05 through 0.2 wt %, an Al content of 0.25 through 1.0 wt %, an Sb content of 0.5 through 2.0 wt %, a Ge content of 1.0 through 5.8 wt %, and an In content of 10 through 20 wt %. 1. A Zn based lead-free solder , comprising Zn and , in mass percentages relative to the total mass of the solder:0.05% to 0.2% of chromium (Cr);0.25% to 1.0% of aluminum (Al);0.5% to 2.0% of antimony (Sb);1.0% to 5.8% of germanium (Ge); and5% to 10% of gallium (Ga).2. A Zn based lead-free solder , comprising Zn and , in mass percentages relative to the total mass of the solder:0.05% to 0.2% of chromium (Cr);0.25% to 1.0% of aluminum (Al);0.5% to 2.0% of antimony (Sb);1.0% to 5.8% of germanium (Ge); and10% to 20% of indium (In).3. A Zn based lead-free solder , comprising Zn and , in mass percentages relative to the total mass of the solder:0.05% to 0.2% of chromium (Cr);0.25% to 1.0% of aluminum (Al);0.6% to 1.2% of manganese (Mn);1.0% to 5.8% of germanium (Ge); and5% to 10% of gallium (Ga).4. A Zn based lead-free solder , comprising Zn and , in mass percentages relative to the total mass of the solder:0.05% to 0.2% of chromium (Cr);0.25% to 1.0% of aluminum (Al);0.6% to 1.2% of manganese (Mn);1.0% to 5.8% of germanium (Ge); and10% to 20% of indium (In).5. The Zn based lead-free solder of claim 1 , further comprising at least one selected from the group consisting of Sn claim 1 , Bi claim 1 , P claim 1 , V claim 1 , and Si.6. A semiconductor power module claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a power semiconductor element bonded on a substrate by the Zn ...

METHOD FOR PRODUCING MEMBER FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE, AND MEMBER FOR SEMICONDUCTOR DEVICE

A member for semiconductor device includes a metal portion configured to be bonded to another member by solder, and a treated coating covering a surface of the metal portion, the treated coating including a treatment agent. The treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder. 1. A member for semiconductor device , comprising:a metal portion configured to be bonded to another member by solder, anda treated coating covering a surface of the metal portion, the treated coating including a treatment agent,wherein the treated coating vaporizes at a temperature lower than or equal to a solidus temperature of the solder.2. The member for semiconductor device according to claim 1 , wherein a vaporization temperature of the treated coating is in a range from 80 to 250° C.3. The member for semiconductor device according to claim 1 , wherein the treatment agent comprises at least one organic substance selected from a carboxylic acid claim 1 , a metal salt of carboxylic acid claim 1 , an ammonium salt of carboxylic acid claim 1 , an amine salt of carboxylic acid claim 1 , and a carboxylic acid ester.4. The member for semiconductor device according to claim 3 , wherein the organic substance comprises 1 to 25 carbons.5. The member for semiconductor device according to claim 3 , wherein the organic substance has a molecular weight from 30 to 400 g/mol.6. The member for semiconductor device according to claim 3 , wherein the treatment agent comprises the at least one organic substance claim 3 , and water or alcohol dissolving the at least one organic substance.7. The member for semiconductor device according to claim 3 , wherein the carboxylic acid is a fatty acid.8. The member for semiconductor device according to claim 1 , wherein the treated coating of the treatment agent is physically adsorbed onto the surface of metal portion.9. The member for semiconductor device according to claim 3 , wherein the organic substance is the ...

Cu pillar bump with l-shaped non-metal sidewall protection structure

A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure.

LOW TEMPERATURE SOLDER IN A PHOTONIC DEVICE

Photonic devices include a photonic assembly and a substrate coupled to the photonic assembly. The photonic assembly includes a photonic die and an optical device coupled to the photonic die with an adhesive to form an optical connection between the optical device and the photonic die. The photonic assembly is coupled to the photonic assembly by reflowing a plurality of solder connections at temperature that is less than a cure temperature of the adhesive. 1. A method for forming a photonic device , the method comprising:forming a photonic assembly by attaching an optical device to a photonic die with an optically clear adhesive to form an optical connection between the optical device and the photonic die; andattaching the photonic assembly to a substrate by reflowing one or more solder connections formed between the photonic assembly and the substrate, wherein a reflow temperature of the one or more solder connections is less than a cure temperature of the adhesive.2. The method of claim 1 , wherein attaching the optical device to the photonic die comprises aligning an optical fiber array to the photonic die.3. The method of further comprising attaching a laser to the photonic die.4. The method of further comprising at least one of electrically testing and optically testing the photonic assembly before attaching the photonic assembly to the substrate.5. The method of further comprising heating the photonic assembly and the substrate at a temperature less than the reflow temperature to convert solder of the one or more solder connections to an intermetallic compound; wherein reflowing the one or more solder connections includes reflowing the one or more solder connections at the reflow temperature.6. The method of claim 1 , wherein the cure temperature of the adhesive is less than about 160 degrees Celsius.7. The method of further comprising disposing solder bumps on the photonic die to form the one or more solder connections claim 1 , wherein the solder bumps ...

SEMICONDUCTOR PACKAGE HAVING IMPROVED THERMAL INTERFACE BETWEEN SEMICONDUCTOR DIE AND HEAT SPREADING STRUCTURE

A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer. 1. A semiconductor package , comprising:a base comprising an upper surface and a lower surface that is opposite to the upper surface;a radio-frequency (RF) module embedded near the upper surface of the base;an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation;a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; anda metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.2. The semiconductor package according to claim 1 , wherein the RF module comprises a top antenna layer and a bottom antenna layer spaced apart from the top antenna layer claim 1 , and at least one dielectric layer interposed between the top antenna layer and the bottom antenna layer.3. The semiconductor package according to claim 1 , wherein the backside metal layer comprises Au.4. The semiconductor package according to claim 1 , wherein the solder paste comprises lead-free solder comprising tin claim 1 , copper claim 1 , silver claim 1 , bismuth claim 1 , indium claim 1 , zinc claim 1 , or antimony.5. The semiconductor package according to claim 1 , wherein ...

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

Provided is a method of fabricating a semiconductor package. The method of fabricating the semiconductor package include preparing a lower element including a lower substrate, a lower electrode, an UBM layer, and a reducing agent layer, providing an upper element including an upper substrate, an upper electrode, and a solder bump layer, providing a pressing member on the upper substrate to press the upper substrate to the lower substrate, and providing a laser beam passing through the pressing member to bond the upper element to the lower element. 1. A method of fabricating a semiconductor package , the method comprising:preparing a lower element including a lower substrate, a lower electrode on the lower substrate, an under bump metallurgy (UBM) layer on the lower electrode, and a reducing agent layer on the UBM layer;providing an upper element including an upper substrate, an upper electrode on the upper substrate, and a solder bump layer on the upper electrode;providing a pressing member on the upper substrate to press the upper substrate to the lower substrate; andproviding a laser beam passing through the pressing member to the upper substrate to form the UBM layer, the reducing agent layer, and the solder bump layer as an intermetallic compound layer by using a conductive heat of the upper substrate and the upper electrode.2. The method of claim 1 , wherein the lower element further comprises:a curing agent layer between the UBM layer and the reducing agent layer; anda base material layer between the curing agent layer and the reducing agent layer.3. The method of claim 2 , wherein the curing agent layer and the base material layer are formed as a protective layer around the intermetallic compound layer.4. The method of claim 3 , further comprising dipping the lower element and the upper element in DI (deionized) water through which the laser beam is transmitted claim 3 ,wherein the DI water allows the protective layer to be formed around the lower electrode ...

"Lead-Free Solder Ball"

A lead-free solder ball is provided which suppresses interfacial peeling in a bonding interface of a solder ball, fusion defects which develop between the solder ball and solder paste, and which can be used both with Ni electrodes plated with Au or the like and Cu electrodes having a water-soluble preflux applied atop Cu. The lead-free solder ball for electrodes of BGAs or CSPs consists of 1.6-2.9 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn. It has excellent resistance to thermal fatigue and to drop impacts regardless of the type of electrodes of a printed circuit board to which it is bonded, which are Cu electrodes or Ni electrodes having Au plating or Au/Pd plating as surface treatment. 1. A lead-free solder ball which is installed for use as an electrode on a rear surface of a module substrate for a BGA or a CSP and which is fused with a solder paste , the solder ball having a solder composition consisting of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni; at least one of Fe and Co in a total amount of 0.003-0.1 mass %; and', 'Ge in a total amount of 0.003-0.1 mass %; and, 'at least one ofa remainder of Sn.2. The lead-free solder ball as set forth in claim 1 , wherein the solder composition consists of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni;at least one of Fe and Co in a total amount of 0.003-0.1 mass %; anda remainder of Sn.3. The lead-free solder ball as set forth in claim 1 , wherein the solder composition consists of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni;Ge in a total amount of 0.003-0.1 mass %; anda remainder of Sn.4. The lead-free solder ball as set forth in claim 1 , wherein the solder composition consists of:1.6-2.9 mass % of Ag;0.7-0.8 mass % of Cu;0.05-0.08 mass % of Ni;at least one of Fe and Co in a total amount of 0.003-0.1 mass %;Ge in a total amount of 0.003-0.1 mass %; anda remainder of Sn.5. The lead-free solder ball as set forth in claim 1 ...

Junction and electrical connection

A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor.

HIGH RELIABILITY LEAD-FREE SOLDER ALLOYS FOR HARSH ENVIRONMENT ELECTRONICS APPLICATIONS

A SnAgCuSb-based Pb-free solder alloy is disclosed. The disclosed solder alloy is particularly suitable for, but not limited to, producing solder joints, in the form of solder preforms, solder balls, solder powder, or solder paste (a mixture of solder powder and flux), for harsh environment electronics. 1. A solder alloy , consisting of:2.5-4.5 wt. % of Ag;0.6-2.0 wt. % of Cu;greater than 5.0 wt. % to 6.0 wt. % of Sb;optionally, 0.001-0.2 wt. % of Ni, or Co, or both; anda remainder of Sn.2. The solder alloy of claim 1 , consisting of: 3.0-4.0 wt. % of Ag; 0.6-1.2 wt. % of Cu; greater than 5.0 wt. % to 6.0 wt. % of Sb; optionally claim 1 , 0.001-0.2 wt. % of Ni claim 1 , or Co claim 1 , or both; and the remainder of Sn.3. The solder alloy of claim 2 , consisting of: 3.0-4.0 wt. % of Ag; 0.6-1.2 wt. % of Cu; greater than 5.0 wt. % to 6.0 wt. % of Sb; 0.001-0.2 wt. % of Ni claim 2 , or Co claim 2 , or both; and the remainder of Sn.4. The solder alloy of claim 3 , consisting of: 3.0-4.0 wt. % of Ag; 0.6-1.2 wt. % of Cu; greater than 5.0 wt. % to 6.0 wt. % of Sb; 0.001-0.2 wt. % of Ni; and the remainder of Sn.5. The solder alloy of claim 2 , consisting of: 3.0-4.0 wt. % of Ag; 0.6-1.2 wt. % of Cu; greater than 5.0 wt. % to 6.0 wt. % of Sb; and the remainder of Sn.6. The solder alloy of claim 1 , wherein the solder alloy is a solder ball.7. The solder alloy of claim 1 , wherein the solder alloy is a solder preform.8. The solder alloy of claim 1 , wherein the solder alloy is a solder powder.9. The solder alloy of claim 2 , wherein the solder alloy is a solder ball.10. The solder alloy of claim 2 , wherein the solder alloy is a solder preform.11. The solder alloy of claim 2 , wherein the solder alloy is a solder powder.12. A solder paste claim 2 , consisting of:flux; and 2.5-4.5 wt. % of Ag;', '0.6-2.0 wt. % of Cu;', 'greater than 5.0 wt. % to 6.0 wt. % of Sb;', 'optionally, 0.001-0.2 wt. % of Ni, or Co, or both; and', 'a remainder of Sn., 'a solder alloy powder, consisting ...

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. 1. A microelectronic package , comprising:first conductive elements, including a first trace, obtained from a same conductive layer located on a lower side of the microelectronic package;wire bond wires connected to and extending away from upper surfaces of the first conductive elements;a first microelectronic component coupled with a first attachment layer to the first trace;a first conductive via in the first attachment layer and interconnecting the first trace and a first contact structure of the first microelectronic component;a second microelectronic component coupled to the first microelectronic component with a second attachment layer;second conductive elements, including a second trace, respectively connected to upper surfaces of the wire bond wires; anda second conductive via in a dielectric layer and interconnecting the second trace and a second contact structure of the second microelectronic component.2. The microelectronic package according to claim 1 , wherein the first trace is for a first redistribution.3. The a microelectronic package according to claim 2 , wherein the second ...

LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. 1. A display panel with redundancy scheme comprising:a display substrate including a pixel area that includes an array of subpixels, each subpixel including a pair of landing areas;an array of redundant LED bonding site pairs, each landing area including a corresponding LED bonding site;wherein the array of subpixels includes a first subpixel array, a second subpixel array, and a third subpixel array, wherein the first, second, and third subpixel arrays are designed to emit different primary color emissions;circuitry to switch and drive the array of subpixels; andone or more LED device irregularities among the array of redundant LED bonding site pairs, wherein each corresponding landing area containing a micro LED device irregularity is electrically disconnected from the circuitry.2. The display panel of claim 2 , wherein each corresponding landing area is cut to electrically disconnect the corresponding landing area from the circuitry.3. The display panel of claim 3 , wherein the circuitry is contained within an array of micro controller chips.4. The display panel of claim 3 , wherein the array of micro controller chips is bonded to the display substrate.5. The display panel of claim 4 , wherein each micro controller chip is bonded to the display substrate within the pixel area.6. The display panel of claim 5 , wherein each micro controller chip is connected to a scan driver ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A conductive plate has a front surface at a front side and a rear surface at a rear side. The front surface includes a first front surface on which a first arrangement region is disposed and a second front surface on which a second arrangement region is disposed. The first front surface has a height measured from the rear surface that is different from a height of the second front surface measured from the rear surface. Next, first and second bonding materials are respectively applied to the first and second arrangement regions. A first part is bonded to the first arrangement region via the first bonding material, and a second part is bonded to the second arrangement region via the second bonding material. The heights of the first and second arrangement regions set on the front surface on the conductive plate are different from each other. 1. A semiconductor device manufacturing method , comprising:preparing a conductive plate having a front surface at a front side and a rear surface at a rear side opposite to the front side, the front surface including a first front surface on which a first arrangement region is disposed and a second front surface on which a second arrangement region is disposed, the first front surface having a height measured from the rear surface that is different from a height of the second front surface measured from the rear surface;applying a first bonding material to the first arrangement region and a second bonding material different from the first bonding material to the second arrangement region; andbonding a first part to the first arrangement region via the first bonding material and a second part to the second arrangement region via the second bonding material.2. The semiconductor device manufacturing method according to claim 1 , whereinone of the first front surface or the second front surface is located at a position closer to the rear surface than is the other one of the first front surface or the second front surface, applying, ...

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced. 1. A method of forming a semiconductor device , the method comprising:forming a contact layer over a first major surface of a substrate, the substrate comprising device regions separated by kerf regions, the contact layer disposed in the kerf region and the device regions;forming a structured solder layer over the device regions, wherein the contact layer is exposed at the kerf region after forming the structured solder layer; anddicing through the contact layer and the substrate in the kerf regions.2. The method of claim 1 , wherein the substrate is a semiconductor wafer.3. The method of claim 1 , wherein the substrate is a reconfigured wafer comprising a plurality of dies disposed in an encapsulant.4. The method of claim 1 , wherein the dicing is performed from a second major surface opposite the first major surface.5. The method of claim 1 , wherein the dicing is performed from the second major surface using a dry laser process or a stealth laser process.6. The method of claim 1 , wherein the dicing is performed from the second major surface using a mechanical dicing process.7. The method of claim 1 , wherein the dicing is performed from the first major surface using a plasma dicing process.8. The method of claim 7 , wherein the dicing further comprises using a wet chemical etching process to remove the contact layer disposed in the kerf region prior to the plasma dicing process.9. The method of claim 1 , wherein forming the structured ...

METHOD AND APPARATUS FOR CREATING A BOND BETWEEN OBJECTS BASED ON FORMATION OF INTER-DIFFUSION LAYERS

The present disclosure provides a method of creating a bond between a first object and a second object. For example, creating a joint or die attach between a semiconductor chip and an electronic substrate, especially for harsh and high temperature environments. The method may include a step of filling a space between the first object and the second object with a filler material. Further, the method may include a step of heating the filler material to facilitate formation of a plurality of inter-diffusion layers. Accordingly, a first inter-diffusion layer may be formed between the filler material and the first object. Further, a second inter-diffusion layer may be formed between the filler material and the second object. Furthermore, in some embodiments, the first inter-diffusion layer may be contiguous with the second inter-diffusion layer. The contiguity may be facilitated by placement of at least one insert between the first object and the second object, in which the inter-diffusion of the filler material and the at least one insert may produce the third inter-diffusion layer, wherein the third inter-diffusion layer is contiguous with each of the first inter-diffusion layer and the second inter-diffusion layer. 1. A method of creating a bond between a first object and a second object , the method comprising:a. filling a space between the first object and the second object with a filler material; andb. forming a plurality of inter-diffusion layers, wherein a first inter-diffusion layer is formed between the filler material and the first object, wherein a second inter-diffusion layer is formed between the filler material and the second object, wherein the first inter-diffusion layer is contiguous with the second inter-diffusion layer.2. The method of claim 1 , wherein the space between the first object and the second object comprises at least one insert claim 1 , wherein the at least one insert is in physical contact with the filler material claim 1 , wherein a ...

ROOM TEMPERATURE METAL DIRECT BONDING

A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed. 1. A bonded structure comprising:a first plurality of metallic pads disposed on a first substrate;a first non-metallic region located on a first surface of said first substrate proximate to the first plurality of metallic pads;a second plurality of metallic pads disposed on a second substrate; anda second non-metallic region located on a second surface of the second substrate proximate to the second plurality of metallic pads,wherein a portion of each metallic pad of the first plurality of metallic pads directly contacts a corresponding metallic pad of the second plurality of metallic pads to form a metallic contact, andwherein the first non-metallic region contacts and is directly bonded to the second non-metallic region along an interface, the interface between the first non-metallic region and the second non-metallic region extending substantially to the metallic contact.2. The bonded structure of claim 1 , wherein each metallic pad comprises a reflowable material.3. The bonded structure of claim 1 , wherein the first non-metallic region comprises silicon oxide. This application is a continuation of application Ser. No. 14/959,204 filed Dec. 4, 2015, which is a continuation of application Ser. No. 14/474,476 ...

Preform Diffusion Soldering

A method of joining a semiconductor die to a substrate includes: applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 μm and a lower melting point than both metal regions; forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the die; and setting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the melting point of the preform and the soldering temperature. 1. A method of joining a semiconductor die to a substrate , the method comprising:applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 μm and a lower melting point than both the metal region of the semiconductor die and the metal region of the substrate;forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the semiconductor die; andsetting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases having a melting point above the melting point of the preform and the soldering temperature.2. The method of claim 1 , wherein the solder preform has a maximum thickness of 15 μm.3. The method of claim 1 , wherein the ...

Printed wiring board having metal layers producing eutectic reaction

A printed wiring board includes a Cu wiring pattern formed on a substrate. A first metal layer is formed on the Cu wiring pattern. A second metal layer is formed on the first metal layer. The first metal layer has a less reactivity with Cu than the second metal layer. The first metal layer and the second metal layer together cause an eutectic reaction.

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto. 110-. (canceled)12. The semiconductor device of claim 11 , wherein the first portion of the diffusion preventing layer forming a portion of the first surface contacts the second insulating film.13. The semiconductor device of claim 12 , wherein a second portion of the diffusion preventing layer forming a second surface opposite to the first surface contacts the first insulating film.14. The semiconductor device of claim 13 , wherein the first pad has a first surface extended in a direction perpendicular to the first surface claim 13 , and wherein the first surface of the first pad contacts the diffusion preventing layer and the first insulating film.15. The semiconductor device of claim 11 , wherein the diffusion preventing layer includes at least one of Si claim 11 , N claim 11 , O claim 11 , or C.16. The semiconductor device of claim 15 , wherein the diffusion preventing layer includes SiN or SiOC.17. The semiconductor device of claim 11 , wherein the second pad is partially covered by a barrier metal.18. The semiconductor device of claim 17 , wherein the barrier metal covers at least a portion of at least two surfaces of the second pad that extends in a direction perpendicular to the first surface.19. The semiconductor device of claim 17 , wherein the barrier metal covers at least a portion of at least a part of a surface extended in a direction parallel to the first surface.20. The semiconductor device of claim 17 , wherein the barrier metal includes at least one of Ti claim 17 , N claim 17 , or Ta.21. The semiconductor device of claim 20 , wherein the barrier metal includes TiN or TaN.22. The semiconductor device of claim 17 , wherein a portion of the barrier metal contacts the first pad.23. The semiconductor device of claim ...

Semiconductor sensor chips

Semiconductor sensor chips are provided. In some embodiments, a semiconductor sensor chip can include at least one wire bond pad on one side thereof, at least one bond pad on another, opposite side thereof, and at least one through-silicon via (TSV) extending therebetween and electrically connected to the bond pads on opposite sides of the chip. Each of the bond pads can have a wire attached thereto. In some embodiments, a semiconductor sensor chip can include a pressure sensor, a substrate, and a resistor in a well that provides p-n junction isolation from a body of the substrate. In some embodiments, a semiconductor sensor chip can include a plurality of wire bonds pads with a wire soldered to each of the bond pads. Each of the wires can be soldered with a longitudinal length thereof soldered to its associated bond pad.

System for Low-Force Thermocompression Bonding

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1. A system for bonding microelectronic elements , comprising:a bonding platform for flip-chip bonding, configured to bond elements by compressing them together, without any conductive liquid phase material, thereby deforming contacting metallizations by no more than 40% of their initial height;an atmospheric plasma applicator, integrated into said bonding platform, which is configured to apply reducing and passivating agents to said contacting metallizations on each said element, by use of plasma-activated radical-enriched gas flow at substantially atmospheric pressure;wherein said reducing and passivating agents reduce native oxides from said contacting metallizations and passivate said contacting metallizations against re-oxidation prior to bonding said element;wherein elements are loaded into said bonding platform and aligned for bonding, said atmospheric plasma applicator applies reducing and passivation agents to the contacting metallizations on said elements, ...

Thermocompression Bonding Using Metastable Gas Atoms

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1. A method for bonding microelectronic elements , comprising the steps of:a) directing plasma-activated radical-enriched gas flow at substantially atmospheric pressure both to first contacting metallizations on a first element and also to second contacting metallizations on a second element, both to reduce native oxides from said contacting metallizations and also to passivate said contacting metallizations against re-oxidation;b) compressing said first and second contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;c) repeating said steps a) and b), to thereby bond contacting metallizations on subsequent elements to contacting metallizations on the previous element;wherein said plasma-activated radical-enriched gas flow includes a population of helium metastable states.2. The method of claim 1 , further comprising the step of bonding an additional element to the previous elements ...

Thermocompression Bonding with Passivated Indium-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1. A method for bonding microelectronic elements , comprising the steps of:a) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from the surfaces of contacting metallizations on a first element; and to passivate the surfaces of said contacting metallizations against re-oxidation;b) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from the surfaces of indium-based bumps on a second element; and to passivate the surfaces of said indium-based bumps against re-oxidation;c) compressing said indium-based bumps and said contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;d) repeating said steps a), b), and c), to thereby bond the indium-based bumps on subsequent elements to the contacting metallizations on the previous element;wherein said indium-based bumps are ...

Thermocompression Bonding with Passivated Copper-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1. A method for bonding microelectronic elements , comprising the steps of:a) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from the surfaces of first copper-based contacting metallizations on a first side of a first element; and to passivate the surfaces of said first copper-based contact metallizations against re-oxidation;b) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from the surfaces of second copper-based contacting metallizations on a second element; and to passivate the surfaces of said second copper-based contacting metallizations against re-oxidation;c) compressing said first and second copper-based contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;d) repeating said steps a), b), and c), to thereby bond copper-based contacting ...

Thermocompression Bonding with Passivated Gold Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1. A method for bonding microelectronic elements , comprising the steps of:a) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from first gold contacting metallizations on a first element; and to passivate said first gold contacting metallizations against re-oxidation;b) using plasma-activated radical-enriched gas flow at substantially atmospheric pressure: to reduce native oxides from second gold contacting metallizations on a first side of a second element; and to passivate said second gold contacting metallizations against re-oxidation;c) compressing said first and second gold contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;d) repeating said steps a), b), and c), to thereby bond gold contacting metallizations on subsequent elements to gold contacting metallizations on the previous element.2. The method of claim ...

Thermocompression Bonding with Passivated Silver-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1. A method for bonding microelectronic elements , comprising the steps of:a) directing plasma-activated radical-enriched gas flow at substantially atmospheric pressure both to first contacting metallizations on a first element and also to second contacting metallizations on a second element, both to reduce native oxides from said contacting metallizations and also to passivate said contacting metallizations against re-oxidation;b) compressing said first and second contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;c) repeating said steps a) and b), to thereby bond contacting metallizations on subsequent elements to contacting metallizations on the previous element;wherein said first contacting metallizations are made essentially of silver.2. A method for bonding microelectronic elements , comprising the steps of:a) using plasma-activated radical-enriched gas flow at ...

Thermocompression Bonding with Passivated Nickel-Based Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression. 1. A method for bonding microelectronic elements , comprising the steps of:a) directing plasma-activated radical-enriched gas flow at substantially atmospheric pressure both to first contacting metallizations on a first element and also to second contacting metallizations on a second element, both to reduce native oxides from said contacting metallizations and also to passivate said contacting metallizations against re-oxidation;b) compressing said first and second contacting metallizations together, without any conductive liquid phase material, to thereby bond said second element to said first element;c) repeating said steps a) and b), to thereby bond contacting metallizations on subsequent elements to contacting metallizations on the previous element;wherein said first contacting metallizations are made essentially of nickel.2. A method for bonding microelectronic elements , comprising the steps of:a) using plasma-activated radical-enriched gas flow at ...

Flow underfill for microelectronic packages

A microelectronic assembly includes a first component with first conductive elements; a second component with second conductive elements; a bond metal; and an underfill layer. The posts have a height above the respective surface from which the posts project. A bond metal can be disposed between respective pairs of conductive elements, each pair including at least one of the posts and at least one of the first or second conductive elements confronting the at least one post. The bond metal can contact edges of the posts along at least one half the height of the posts. An underfill layer contacts and bonds the first and second surfaces of the first and second components. A residue of the underfill layer may be present at at least one interfacial surfaces between at least some of the posts and the bond metal or may be present within the bond metal.

CHIP ARRANGEMENTS

A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc. 1. A chip arrangement comprising:a chip comprising a chip back side;a substrate comprising a surface with a plating; anda zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy comprising, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.2. The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 3% to 8% aluminum.3. The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 0.5% to 4% germanium.4. The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 0.5% to 4% gallium.5. The chip arrangement of claim 1 , wherein the zinc-based solder alloy further comprises at least one from the following group of materials: silver claim 1 , gold claim 1 , nickel claim 1 , platinum claim 1 , palladium claim 1 , vanadium claim 1 , molybdenum claim 1 , tin claim 1 , copper claim 1 , arsenic claim 1 , antimony claim 1 , niobium claim 1 , tantalum claim 1 , and/or any combination thereof claim 1 , by weight 0.001% to 10% of the zinc-based solder alloy.6. The chip arrangement of claim 1 , wherein the plating comprises at least one of nickel or nickel-phosphorous.7. The chip arrangement of claim 6 , wherein the substrate comprises one or more of copper claim 6 , nickel claim 6 , silver claim 6 , or ceramic.8. The chip arrangement of claim 7 , wherein the at least one of nickel or nickel-phosphorous in the plating provides a reduced ...

METHOD AND APPARATUS FOR CREATING A BOND BETWEEN OBJECTS BASED ON FORMATION OF INTER-DIFFUSION LAYERS

The present disclosure provides a method of creating a bond between a first object and a second object. For example, at least one insert may be provided at a location in a space formed between the first object and the second object. In additional, a filler material may be provided proximal to the location. An inter-diffusion layer may be formed, wherein a first portion of the inter-diffusion layer is formed by diffusion between the filler material and the at least one insert, wherein a second portion of the inter-diffusion layer is formed between the filler material and the first object, wherein a third portion of the inter-diffusion layer is formed between the filler material and the second object, wherein the first portion is coadunate with each of the second portion and third portion. 1. An electronic module comprising:a substrate;at least one chip; a first set of inserts placed inside a space between the substrate and the at least one chip,', "wherein diffusion of the second set of inserts occurs into at least one of the following: the substrate's mating surface, the at least one chip's mating surface and the first set of inserts;", 'a second set of inserts placed inside a space formed by the substrate, the at least one chip and the first set of inserts,'}], 'a plurality of inserts comprisinga gap between the first set of the inserts and the substrate; and 'wherein the diffusion results in formation of at least one of the following: a coadunate inter-diffusion layer along at least one insert of the first set of inserts to the at least one chip and a coadunate inter-diffusion layer along at least one insert of the first set of the inserts to the substrate.', 'a gap between the first set of inserts and the at least one chip,'}21. The electronic module of lain , wherein the at least one insert of the first set of inserts is comprised in at least one of the substrate's mating surface and the chip's mating surface.3. The electronic module of claim 1 , wherein the at ...

ELECTRICAL CONNECTOR

An electrical connector for electrically connecting a chip module to a circuit board, includes an insulating body, multiple conducting bodies, and multiple pieces of low melting point metal. The insulating body has multiple accommodating spaces. Each accommodating space runs through upper and lower surfaces of the insulating body. The multiple conducting bodies are respectively received in the accommodating spaces. Two ends of each conducting body are exposed on the upper and lower surfaces of the insulating body. The low melting point metal is gallium or gallium alloy. Each piece of the low melting point metal is correspondingly arranged at at least one end of one of the conducting bodies. The low melting point metal protrudes from the insulating body, and is electrically connected to the chip module. 1. An electrical connector for electrically connecting a chip module to a circuit board , comprising:an insulating body having multiple accommodating spaces, wherein each of the accommodating spaces runs through upper and lower surfaces of the insulating body;multiple conducting bodies, respectively received in the accommodating spaces, wherein two ends of each conducting body are exposed on the upper and lower surfaces of the insulating body; andmultiple pieces of low melting point metal, wherein the low melting point metal is gallium or gallium alloy, and each piece of the low melting point metal is correspondingly arranged at at least one end of one of the conducting bodies,wherein the low melting point metal protrudes from the insulating body, and is electrically connected to the chip module.2. The electrical connector according to claim 1 , further comprising fillers disposed in the low melting point metal.3. The electrical connector according to claim 2 , wherein an outer surface of the filler is provided with a material compatible with the low melting point metal.4. The electrical connector according to claim 3 , wherein the material is indium claim 3 , tin ...

SEMICONDUCTOR PACKAGE HAVING IMPROVED THERMAL INTERFACE BETWEEN SEMICONDUCTOR DIE AND HEAT SPREADING STRUCTURE

A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element. 110-. (canceled)11. A semiconductor package , comprising:a base comprising a top surface and a bottom surface that is opposite to the top surface;a first semiconductor chip mounted on the top surface of the base in a flip-chip manner;a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by at least one connecting element;an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; anda molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element, wherein a top surface of the in-package heat dissipating element is not covered by the molding compound and is exposed.12. The semiconductor package according to claim 11 , wherein the second semiconductor chip is adhered to the first semiconductor chip by using a die attach film.13. The semiconductor package according to claim 12 , wherein the die attach film comprises an epoxy adhesive layer.14. The semiconductor package according to claim 12 , wherein the die attach film has thermal conductivity of about 0.3 W/m-K.15. The semiconductor package according to claim 12 , wherein the high-thermal conductive die attach film comprises an adhesive film with a higher thermal ...

3D IC METHOD AND DEVICE

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. 1. A bonded structure comprising:a first substrate having a front side and a back side opposite the front side;a first non-metallic region located on the back side of the first substrate;a first contact structure comprising a conductive material filled in a first via extending through the first substrate, the conductive material comprising a via first structure;a second substrate;a second non-metallic region located on a front side of the second substrate and directly bonded to the first non-metallic region along an interface; anda second contact structure disposed on the second substrate proximate to the second non-metallic region, the second contact structure directly bonded to the first contact structure, the interface extending substantially to the bonded first and second contact structures.2. The bonded structure of claim 1 , wherein the conductive material is approximately coplanar with the first non-metallic region at the back side of the first substrate.3. The bonded structure of claim 1 , wherein the conductive material protrudes the back side of the first substrate and the dielectric sidewall protrudes the back side of the first substrate.4. The bonded structure of claim 1 , wherein the first contact structure comprises a first portion on the back side of the ...

MOUNTING STRUCTURE AND BGA BALL

A mounting structure includes a BGA including a BGA electrode, a circuit board including a circuit board electrode, and a solder joining portion which is arranged on the circuit board electrode and is connected to the BGA electrode. The solder joining portion is formed of Cu having a content ratio in a range from 0.6 mass % to 1.2 mass %, inclusive, Ag having a content ratio in a range from 3.0 mass % to 4.0 mass %, inclusive, Bi having a content ratio in a range from 0 mass % to 1.0 mass %, inclusive, In, and Sn. A range of the content ratio of In is different according to the content ratio of Cu. 1. A mounting structure comprising:a ball grid array (BGA) including a BGA electrode;a circuit board including a circuit board electrode; anda solder joining portion disposed on the circuit board electrode and connected to the BGA electrode,wherein the solder joining portion is formed of Cu having a content ratio in a range from 0.6 mass % to 1.2 mass %, inclusive, Ag having a content ratio in a range from 3.0 mass % to 4.0 mass %, inclusive, Bi having a content ratio of greater than 0 mass % and equal to or less than 1.0 mass %, In, and Sn,(1) in a case that the content ratio of Cu is in a range from 0.6 mass % to 0.91 mass %, inclusive, a content ratio of In is in a range from 5.3+(6−(1.55×Content Ratio of Cu+4.428)) mass % to 6.8+(6−(1.57×Content Ratio of Cu+4.564)) mass %, inclusive,(2) in a case that the content ratio of Cu is greater than 0.91 mass % and equal to or less than 1.0 mass %, the content ratio of In is in a range from 5.3+(6−(1.55×Content Ratio of Cu+4.428)) mass % to 6.8 mass %, inclusive, and(3) in a case that the content ratio of Cu is greater than 1.0 mass % and equal to or less than 1.2 mass %, the content ratio of In is in a range from 5.3 mass % to 6.8 mass %, inclusive.2. The mounting structure according to claim 1 , further comprising:a Ni plating layer disposed on at least one of surfaces of the circuit board electrode and the BGA electrode,{' ...