Halbleitervorrichtung mit Abstrahlungsbauteilen

BONDING PAD INTERCONNECTION STRUCTURE

NICKEL-CONTAINING METALLIZING COMPOSITIONS

... 1334434 Welding by pressure E I DU PONT DE NEMOURS & CO 20 May 1971 [20 May 1970] 16069/71 Heading B3R [Also in Division C7] An inert vehicle such as water or an organic liquid containing Ni powder having a coating consisting of Ni containing 0.1-14 wt. per cent P, applied thereto e.g. by electroless plating, is applied in the form of bumps or pads through a stencil to a noble-metallized printed circuit pattern, e.g. of Au or noble metal/glass frit, fired in a reducing atmosphere, and the powdercoated body is cooled in said atmosphere; Alterminated integrated circuit clips may then be attached to the bumps or pads, optionally after coining thereof, by thermal compression bonding.

SEMICONDUCTOR COMPONENT WITH ELECTRICAL CONTACTS AND PROCEDURE FOR THE PRODUCTION OF SUCH CONTACTS

DEVICE AND PROCEDURE FOR THE CREATION OF SEMICONDUCTOR CHIPS ON CARRIERS

SEMICONDUCTOR COMPONENT WITH ELECTRICAL CONTACTS AND PROCEDURE FOR THE PRODUCTION OF SUCH CONTACTS

RAPID-CURING ADHESIVE FORMULATION FOR SEMICONDUCTOR DEVICES

METHOD FOR CONTACT BONDING ELECTRONIC COMPONENTS ON AN INSULATING SUBSTRATE AND COMPONENT MODULE PRODUCED ACCORDING TO SAID METHOD

FABRICATION OF CIRCUIT PACKAGES

HALL-1 FABRICATION OF CIRCUIT PACKAGES A method of fabricating circuit packages which employ macro-components mounted on supporting substrates. In order to maintain sufficient clearance between the component and substrate and achieve high reliability bonds, massive solder preforms are applied to contact pads on either the component or substrate. After contact pads of both carrier and substrate are brought into contact with the spheres, the bond is formed.

FABRICATION OF CIRCUIT PACKAGES

METHOD FOR LOW TEMPERATURE BONDING AND BONDED STRUCTURE

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity (2). VSE may use reactive ion etching or wet etching to slighthly etch the surfaces being bonded (3). The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces (4).

Halbleitereinrichtung mit mindestens einem flächenhaften p-n-Übergang

In ein Gehäuse eingeschlossene Halbleiteranordnung

Verfahren zur Herstellung von Halbleitervorrichtungen mit aus Aluminium bestehenden Elektroden

Verfahren zur Herstellung eines aus einem Isolierteil und einem mit diesem fest verbundenen elektrisch leitenden Teil bestehenden Gegenstandes

Procédé de fabrication d'un organe conducteur de l'électricité et organe obtenu par ce procédé

Verfahren zur Herstellung eines oder mehrerer Träger für eine miniaturisierte Schaltung

Halbleiterbauelement und Verfahren zu dessen Herstellung

Halbleiteranordnung

Dispositif semi-conducteur et procédé pour sa fabrication

Verfahren zur Herstellung einer Festkörperschaltung

Halbleiterbauelement mit mindestens einem Druckkontaktübergang

Halbleitervorrichtung

CONTACT UNIT

Manufactoring process of electric connections of a semiconductor device

BLOC DE PUCES DE CIRCUITS INTEGRES

BLOC DE PUCES DE CIRCUITS INTEGRES COMPRENANT UN SUBSTRAT 1; UNE PLURALITE DE PUCES 2 DE CIRCUITS INTEGRES, CHAQUE PUCE COMPORTANT UNE PLURALITE DE FILS FLEXIBLES 6 SUR SON CORPS ET ETANT CONNECTEE ELECTRIQUEMENT ET MECANIQUEMENT AU SUBSTRAT VIA CES FILS; UNE PLURALITE DE PLAQUES RAYONNANT LA CHALEUR 9, CONSTITUEES CHACUNE D'UN BON CONDUCTEUR THERMIQUE ET RELIEES RIGIDEMENT AUX PUCES DE CIRCUITS INTEGRES DANS UNE RELATION UN-A-UN, PAR UNE PREMIERE COLLE 10 AYANT UNE IMPEDANCE THERMIQUE RELATIVEMENT FAIBLE; UNE COIFFE 4 RAYONNANT LA CHALEUR, CONSTITUEE D'UN BON CONDUCTEUR DE LA CHALEUR POUR RECOUVRIR UNE SURFACE DE MONTAGE DE PUCE DE SUBSTRAT ET MAINTENUE EN CONTACT AVEC LES PLAQUES RAYONNANT LA CHALEUR PAR L'INTERMEDIAIRE D'UNE SECONDE COLLE 3 AYANT UNE IMPEDANCE THERMIQUE RELATIVEMENT PLUS FAIBLE; UN RADIATEUR DE CHALEUR 5 MONTE RIGIDEMENT SUR LA COIFFE; ET UNE PLURALITE DE BORNES 8 FIXEES A UNE SURFACE DE NON-MONTAGE DE PUCE DU SUBSTRAT POUR L'ENTREE ET LA SORTIE DE SIGNAUX VIS-A-VIS ...

Processes of welding

DEVICE INCLUDING/UNDERSTANDING OF THE STUDS OF WELDING FORMS ON A SUBSTRATE AND METHOD OF MANUFACTURE OF SUCH STUDS OF WELDING

BLOCK OF JUST CHIPS OF CIRCUITS

DEVICE SEMICONDUCTOR HAS DIODE AND MANUFACTORING PROCESS

APPARATUS FOR THE WIRE FIXING BY WELDING, IN PARTICULAR FOR SOLID-STATE COMPONENTS

Process of localised formation of low-size metal balls

Power module, comprises a semiconductor switching element, a freewheel diode in antiparallel connection and a control integrated circuit

The power module comprises an insulator substrate (4), a base plate (2) having the role of a radiator or a heat sink fastened on one face of the substrate, an electrodes layer (6) formed on the other face of the substrate and carrying a circuit configuration which includes a semiconductor switching element (8), a freewheel diode (10) connected in antiparallel with the switching element, and a control integrated circuit (12) placed on the diode and used for controlling the switching element. The semiconductor switching element (8) is an insulated-gate bipolar transistor (IGBT), or a metal-oxide-semiconductor field-effect transistor (MOSFET). The insulator substrate (4) is preferentially of a material having high thermal conductivity. The control circuit (12) is mounted on the diode (10) by the intermediary of an insulator layer (14), for example of silicon nitride (Si3N4), and a fastening layer (16), for example of an insulating fastening agent. The switching element (8) allows a current through the freewheel diode (10) under the action of a counter-electromotive force which is generated at an instant of a switching operation and passes through the connecting wires (20). The control circuit (12) receives an input voltage to activate the switching element (8) on the basis of the input-output terminals (30), and by the intermediary of the connecting wires (20). A voltage and a current are applied to the electrodes layer (6) from a collector/drain terminal (32), and the voltage and the current are transmitted to an emitter/source terminal (31) from the diode (10) by the intermediary of the connecting wires (20). In the second embodiment, the switching element is adjacent to the diode, and the two are implemented in the form of a monolithic integrated circuit. In the third embodiment, the switching element, the diode, and the control circuit are mounted at the same level, and the three are implemented in the form of a monolithic integrated circuit, wherein the diode is ...

ALLOY WIRE Of FINE GOLD TO CONNECT a TRANSISTOR

SUBSTRATE OF WIRING, ITS MANUFACTORING PROCESS AND ELECTRONIC DEVICE WHICH USES It

Un substrat de câblage multicouche en céramique (1) inclut un motif d'isolation en forme de ligne (8) qui est formé de façon à couvrir plusieurs motifs de câblage en surface (4) et à intersecter les motifs de câblage en surface respectifs, de telle sorte que des électrodes de plage (7) obtenues par soudage soinet définiies par les motifs d'isolation. A ceramic multilayer wiring substrate (1) includes a line-shaped insulation pattern (8) which is formed to cover a plurality of surface wiring patterns (4) and to intersect the respective surface wiring patterns, so that range electrodes (7) obtained by welding are defined by the insulation patterns.

Semiconductor device

SUPPORT WITH SOLDER GLOBULE ELEMENTS AND A METHOD FOR ASSEMBLY OF SUBSTRATES WITH GLOBULE CONTACTS

본 발명의 납땜 볼 요소(1)를 갖는 지지대(4)에 관한 것으로, 볼 콘택트를 갖는 기판(2)에 조립한다. 또한, 볼 콘택트를 갖는 기판(2)의 조립을 위한 장치 및 볼 콘택트를 갖는 기판(2)의 조립 방법에 관한 것이다. 지지대(4)는 그 한 측에 도포되는 접착층(5)을 포함하여, 이 접착층(4)은 그 접착력 또는 조사(irradiation)를 대부분 잃는다. 또한, 지지대(4)는 반도체 칩 또는 반도체 부품을 위한 주어진 간격(w)을 두고 접착층(5)상에 행(6)과 열(7)로 빽빽이 밀집되는 납땜 볼 요소(1)를 포함한다. The support base 4 which has the solder ball element 1 of this invention is assembled to the board | substrate 2 which has a ball contact. The present invention also relates to an apparatus for assembling a substrate 2 having a ball contact and a method of assembling a substrate 2 having a ball contact. The support 4 includes an adhesive layer 5 applied on one side thereof, and this adhesive layer 4 loses most of its adhesive force or irradiation. The support 4 also comprises a solder ball element 1 which is densely packed in rows 6 and columns 7 on the adhesive layer 5 at a given spacing w for the semiconductor chip or semiconductor component.

Method For Low Temperature Bonding And Bonded Structure

저온 또는 실온에서의 결합 방법은 세정 또는 에칭에 의한 표면 세정 및 활성화 단계를 포함한다. 상기 방법은 또한 계면 중합의 부산물을 제거하여 역 중합 반응을 방지함으로써, 실리콘, 질화규소 및 SiO 2 와 같은 재료를 실온에서 화학 결합시키는 단계를 포함할 수도 있다. 결합시킬 표면들은 고도의 평활도 및 평면도로 폴리싱한다(2). VSE 단계는 반응성 이온 에칭 또는 습식 에칭을 이용하여 결합시킬 표면들을 약하게 에칭시킬 수 있다(3). VSE 공정에 의해 표면 조도 및 평면도는 저하되지 않으며 높아질 수 있다. 에칭된 표면을 수산화암모늄 또는 플루오르화암모늄과 같은 용액에서 세정하여 표면 위의 원하는 결합 종의 형성을 촉진시킬 수 있다(4).

LED package

According to one embodiment, an LED package includes a first and a second lead frame, an LED chip and a resin body. The first and second lead frames are apart from each other. The LED chip is provided above the first and second lead frames, and has one terminal connected to the first lead frame and another terminal connected to the second lead frame. The wire connects the one terminal to the first lead frame. The resin body covers the first and second lead frames, the LED chip, and the wire. The first lead frame includes a base portion and a plurality of extending portions. As viewed from above, a bonding position of the wire is located inside one of polygonal regions connecting between roots of the two or more of the extending portions. An appearance of the resin body is a part of an appearance of the LED package.

Metal duplex and method

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as ""nanowires"", include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

METHOD OF MANUFACTURING PRINTED WIRING BOARD

... [PROBLEMS] To provide a method of manufacturing a printed wiring board capable of surely forming a high solder bump on a small diameter connection pad provided in the opening of a solder resist. [MEANS FOR SOLVING THE PROBLEMS] A solder ball (77) is molten by reflowing to form a high solder bump (78U) from the solder ball (77) installed in the upper surface opening (71). Since a distance between the solder ball (77) installed in the opening (71) and the connection pad (158P) is reduced by adjusting the thickness of a solder resist layer (70), the solder bump (78U) can be surely connected to the connection pad (158P) when the solder ball (77) is molten by reflowing.

ADHESIVE FOR CONNECTION OF CIRCUIT MEMBER AND SEMICONDUCTOR DEVICE USING THE SAME

Disclosed is an adhesive for connection of circuit members, which is interposed between a semiconductor chip having a projected connection terminal and a substrate provided with a wiring pattern, and pressed and heated therebetween for electrically connecting the connection terminal and the wiring pattern facing each other and bonding the semiconductor chip with the substrate. This adhesive for connection of circuit members contains a resin composition containing a thermoplastic resin, a crosslinkable resin and a curing agent for having the crosslinkable resin form a crosslinking structure, and complex oxide particles dispersed in the resin composition.

CONTACT NODE

Cette invention se rapporte à la fabrication de connexions à demeure lors de la production d'appareils à base de composants micro-électroniques et de dispositifs à semiconducteurs. Cette invention concerne plus précisément des noeuds de contact qui permettent d'assembler, entre autres, des structures de commutation multicouches pour des modules polycristallins, et de monter des cristaux de circuits intégrés à grande échelle sur une structure de commutation lors de la fabrication desdits modules polycristallins. Ce noeud de contact comprend au moins deux contacts métallisés qui sont connectés à des pistes électroconductrices (2, 6) disposées sur les surfaces de couches de commutation (3, 7). Ces couches sont à base d'un matériau diélectrique, sont superposées et sont connectées entre elles électriquement et mécaniquement par un matériau liant électroconducteur (8). Le noeud de contact consiste en une épissure qui relie, d'une part, le contact consistant en une plage métallisée (1) connectée ...

Metal duplex method

Methods and articles are disclosed. The methods are directed to depositing nickel duplex layers on substrates to inhibit corrosion and improve solderability of the substrates. The substrates have a gold or gold alloy finish.

Front-end processing of nickel plated bond pads

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Semiconductor element for electric power with a diode for sensing temperature and a diode for absorbing static electricity

A first diode part (1B) for sensing junction temperature and a second diode part (1C) for absorbing static electricity that are included in a semiconductor element (1) for electric power are formed within the same substrate together with a semiconductor element part (1A) for electric power. Moreover, the number of a plurality of second diodes (1CD) constituting the second diode part (1C) is equal to the number of a plurality of first diodes (1BD) constituting the first diode part (1B). In addition, a capacitor (11) for reducing the impedance is disposed between the input terminals of a forward direction voltage fall operating amplifying circuit part (4) of a controlling circuit part (8). Here, it is effective to form an LC low pass filter as well by covering a forward path side relay lead part (9A) and a backward path side relay lead part (9B) with one tubular ferrite core.

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as "nanowires", include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

High performance system-on-chip using post passivation process

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Corrosion resistance enhancement of tin surfaces

A method for enhancing corrosion resistance of a tin-based surface on a workpiece involving contacting the tin-based surface with a composition comprising a phosphonic acid compound and water to form a phosphorus-based film over the tin-based coating thereby inhibiting corrosion of the tin-based surface. Phosphonic acid containing compositions having a concentration up to about 30 vol. % of an organic solvent, and water.

Printed wiring board

A method of manufacturing a printed wiring board includes preparing a wiring substrate having a conductive circuit, coating a solder-resist layer over the conductive circuit, leveling a surface of the solder-resist layer so as to obtain a maximum surface roughness in a predetermined range, removing the resin film from the surface of the solder-resist layer, and forming multiple openings in the surface of the solder-resist layer to expose multiple portions of the conductive circuit so as to form multiple conductive pads for mounting an electronic components.

High performance system-on-chip using post passivation process

... . An integrated circuit chip comprising: - a silicon substrate; - a first dielectric layer over said silicon substrate; - a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer,wherein said metallization structure comprises electroplated copper; - a second dielectric layer between said first and second metal layers; - a separating layer over said metallization structure and over said first and second dielectric layers, wherein said separating layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers; - a third metal layer over said separating layer, wherein said third metal layer comprises at least a portion, vertically over said separating layer, of an inductor, wherein said third metal layer comprises electroplated copper; and - a first polymer layer over said third metal layer.

Light emitting diode, optical semiconductor element and epoxy resin composition suitable for optical semiconductor element and production methods therefor

A light emitting diode comprising an LED chip (5) having a light emitting layer made of a nitride compound semiconductor and a light transmitting resin (8) that includes a fluorescent material which absorbs at least a part of light emitted by the LED chip and emits light of a different wavelength, wherein the fluorescent material includes a fluorescent particles of small particle size (82) and a fluorescent particles of large particle size (81), the fluorescent particles of large particle size being distributed in the vicinity of the LED chip in the light transmitting resin to form a wavelength converting layer, the fluorescent particles of small particle size being distributed on the outside of the wavelength converting layer in the light transmitting resin.

LIGHT-EMITTING DIODE PACKAGE USING A LIQUID CRYSTAL POLYMER

A light emitting diode (LED) package using a liquid crystal polymer, includes: a package main body formed by using a liquid crystal polymer; a lead frame formed on the package main body; an LED chip mounted on the lead frame; and a resin packaging unit encapsulating the LED chip, the resin packaging unit including phosphors. The LED package is highly reliable.

Buffer-less de-skewing for symbol combination in a CDMA demodulator

A demodulator in a wireless communication network for combining symbols without the need to store the received symbols in buffers for subsequent retrieval and accumulation. The demodulator includes a plurality of accumulators capable of accumulating received symbols, each symbol associated with a physical channel and a propagation path. The demodulator includes a multiplexer for routing the received symbols to an appropriate accumulator selected from the plurality of accumulators. The symbols received from different propagation paths are each routed and accumulated to an appropriate accumulator based on a physical channel of the received symbol and a value of an indicator associated with a propagation path of the received symbol.

PROCESSING FOR COPPER-BONDED PAD

PROBLEM TO BE SOLVED: To improve bonding which uses a copper pad. SOLUTION: Copper wirings 40 and 50, using an integrated circuit, have copper-bonded pads 20 covered by inert layers so that they prevent the undesired reaction of bonded metal and copper. The inert layers can be the stack layers of the alloy of copper and titanium or CuTix/TiN. Nitride such as tungsten nitride, tantalum nitride, silicon titanium nitride and silicon tantalum nitride can similarly be used. COPYRIGHT: (C)2000,JPO ...

Leistungshalbleitervorrichtung

Leistungshalbleitervorrichtung, die folgendes aufweist: ein Strahlungssubstrat (25); Halbleiterelemente (1, 2), die auf dem Strahlungssubstrat (25) angeordnet sind; eine Vielzahl von Hauptelektrodenplatten (8; 8B); und ein Harzgehäuse (23; 23B), in dessen Harzmaterial das Strahlungssubstrat (25), die Halbleiterelemente (1, 2) und die mehreren Hauptelektrodenplatten (8; 8B) vollständig eingebettet sind, und wobei die Abmessungen des Strahlungssubstrates und die des Harzgehäuses in der gleichen Größenordnung ausgebildet sind, wobei eine erste Hauptelektrodenplatte (81; 81B) der Vielzahl der Hauptelektrodenplatten (8; 8B) ein mit einer Hauptelektrode der Halbleiterelemente (1, 2) elektrisch verbundenes erstes Ende und ein anderes an einer Außenseite einer oberen Oberfläche des Harzgehäuses (23; 23B) derart freiliegendes zweites Ende aufweist, dass eine Hauptfläche des anderen Endes parallel entlang einer oberen Oberfläche des Harzgehäuses (23; 23B) verläuft, eine zweite Hauptelektrodenplatte ...

Halbleiterbaugruppe für ein Schaltnetzteil und Verfahren zu dessen Montage

Halbleiterbaugruppe (1, 16) für ein Schaltnetzteil, aufweisend: – mindestens einen Halbleiterleistungsschalter (6), der mindestens eine Gateelektrode (14), mindestens eine Sourceelektrode und mindestens eine Drainelektrode aufweist; – einen Steuerhalbleiterchip (5); – einen Trägerstreifen (2), der ein Chipfeld (3) und eine Vielzahl von Zuleitungen (4) aufweist, die auf einer Seite des Chipfelds (3) angeordnet sind, wobei jede Zuleitung (4) einen inneren Teilbereich und einen äußeren Teilbereich aufweist, wobei sich mindestens eine Zuleitung (4) vom Chipfeld (3) erstreckt und die übrigen Zuleitungen (4) in einem Abstand vom Chipfeld (3) beabstandet sind, und wobei das Chipfeld (3) mindestens zwei mechanisch getrennte Bereiche (9, 10) aufweist, wobei der Halbleiterleistungsschalter (6) auf einen ersten Bereich (9) des Chipfelds (3) montiert ist und der Steuerhalbleiterchip (5) auf einen zweiten Bereich (10) des Chipfelds (3) montiert ist; – mindestens einen ersten Verbindungsdraht (13), der sich vom Steuerhalbleiterchip (5) zur Gateelektrode (14) des Halbleiterleistungsschalters...

Nonlinear tunnel resistor and method of manufacturing the same

An alloy for use in the manufacture of tunnel diodes (see Division H1) consists of 99 parts by weight indium, 0.5 parts gallium and 0.5 parts zinc. The tunnel diode produced by fusing this alloy to an N type germanium body is freed of surface imperfections by treatment in a slow iodide etch and then electroplated with a thin layer of nickel from an aqueous solution containing 32 ozs. nickel sulphate, 6 ozs. of nickel chloride and 4 ozs. of boric acid per gallon of water. The bath has a pH of 4.5-6.

Bonding pad interconnection structure

Semiconductor devices having bonding pads formed over active regions on the device are fabricated by providing protective layers between the bonding pad and the underlying active region(s). The first protective layer is formed from a polyimide material which can absorb shock resulting from tape automated bonding of the bonding pad. The second protective layer is formed from a puncture-resistant material, such as a plasma nitride, which will prevent penetration of the bonding pad resulting from the downward force applied during tape automated bonding. The bonding pad is connected to active regions or metallization pads on the device substrate by a metal interconnect having a vertical run and a lateral run. The vertical run penetrates the protective layers as well as any passivation layers which may be present, while the lateral run provides an offset for the bonding pad. In this way, the bonding pad and the active region of the substrate will be separated by the protective layers.

A method of soldering a semiconductor chip to a backing plate

... 1,084,028. Soldering. STANDARD TELEPHONES & CABLES Ltd. Nov. 29, 1965, No. 50581/65. Heading B3R. In soldering a semi-conductor chip to a larger backing plate a hole is provided in one face of the latter in which a pellet of solder is inserted, the chip is placed in intimate contact with the plate to cover the pellet and heat is applied to melt the solder which is drawn by capillary action into the chip-plate interface. A small hole 4 is drilled or punched in a heat sink 2, a spherical pellet of solder 3 is forced into the hole and a semi-conductor chip 1 is placed over the hole and heat is applied to melt the solder. The solder flows between the chip and the heat sink surface to stop at the edge of the chip, excess solder remaining in the hole. The hole may be blind or merely an indentation in the surface.

Method of producing a solid-state circuit with low shunt capacitance

GLASS PASSIVATED SEMICONDUCTOR DEVICE FABRICATION PROCESS

... 1320391 Coating with glass GENERAL ELECTRIC CO 14 July 1970 [30 July 1969] 34198/70 Heading C1M [Also in Division H1] A semi-conductor device having glass passivation is manufactured as follows: a semiconductor wafer containing at least one junction is mounted on a substrate and protective discs adhered to the other surface, which surface is subsequently abraded to subdivide the wafer into a plurality of pellets 3, each pellet having a sloping peripheral surface 21 between its original faces 7, 11, the pellet is then etched in a metal-ion-free environment and flushed with a metal-ion-free liquid to remove any metal ions from the surface 21, the pellet is then mounted between plates 25, 35 and a glass layer 41 deposited on the surface 21 preferably by electrophoresis from a liquid suspension containing glass particles, the glass layer then being fused to the surface 21, and finally the plates 25, 35 are removed and contacts made to the faces 7, 11. A glass slurry may be used instead of a ...

A method of manufacturing electric asymmetrically conductive systems

... 780,724. Semi-conductor devices.LICENTIA PATENT-VERWALTUNGS-GES. Aug. 24, 1953 [Aug. 18, 1952], No. 21704/55. Divided out of 780,723. Class 37. A method of making an asymmetrically conducting device comprises imparting to at least one region of a semi-conductor body, e.g. Ge or Si of one conductivity type conductivity of the opposite type by passing a thermal forming current into the region through an electrode in contact therewith and then removing a surface layer at least of the converted region. The surface layer may be removed by chemical etching, e.g. using a mixture of HF,HN0 3 ,CU(N0 3 ) 2 and water as etchant for Ge, or by electrochemical etching using as electrolyte e.g. a 10-70 per cent aqueous solution of H 3 PO 4 on Ge, the treatment being preferably effective over the entire surface of the body and being carried on longer on the unconverted regions. After etching the body is subjected to heat, preferably in vacuum or a protective atmosphere. In the embodiment two converted ...

Procedure for the production of at least one carrier with partly freely from the carrier outstanding inlets for a miniaturized circuit with one or more miniaturized logic elements

PROCEDURE FOR SNAPPING GALVANIC DEPOSITING OF GOLD OUT OF GOLD ELECTROLYTES ON A DOCUMENT AND A WAESSERIGER GOLDGALVANISIEUNGSELEKTROLYT FOR THE EXECUTION OF THE PROCEDURE

SUBSTRATE FOR PACKAGING A SEMICONDUCTOR DEVICE

Flip chip mounting technique

WAFER LEVEL ELECTROLESS COPPER METALLIZATION AND BUMPING PROCESS, AND PLATING SOLUTIONS FOR SEMICONDUCTOR WAFER AND MICROCHIP

SUBSTRATE FOR PACKAGING A SEMICONDUCTOR DEVICE

КОНТАКТНЫЙ УЗЕЛ

Изобретение относится к изготовлению неразъемных соединений в процессе производства аппаратуры на основе изделий микроэлектроники и полупроводниковых приборов, а конкретно к контактным узлам, посредством которых осуществляется сборка, в том числе многослойных коммутационных структур для многокристальных модулей (МКМ), а также монтаж кристаллов БИС на коммутационной структуре в процессе изготовления МКМ. Контактный узел содержит, по крайней мере, два металлизированных контакта, связанных с токоведущими дорожками (2, 6), размещенными на поверхностях коммутационных слоев (3, 7), выполненных на основе из диэлектрического материала, совмещенных друг с другом и соединенных между собой электрически и механически электропроводящим связующим материалом (8). Контактный узел представляет собой стык между контактом, изготовленным в виде металлизированной контактной площадки (1), связанной с токоведущими дорожками (2) на поверхности нижележащего коммутационного слоя (3), и ответным контактом, выполненным ...

Method of manufacturing printed wiring board

The invention provides a method of manufacturing a printed wiring board capable of surely forming a high solder bump on a small diameter connection pad provided in the opening of a solder resist. A solder ball (77) is molten by reflowing to form a high solder bump (78U) from the solder ball (77) installed in the upper surface opening (71). Since a distance between the solder ball (77) installed in the opening (71) and the connection pad (158P) is reduced by adjusting the thickness of a solder resist layer (70), the solder bump (78U) can be surely connected to the connection pad (158P) when the solder ball (77) is molten by reflowing.

SEMICONDUCTOR DEVICE HAS RADIANT STRUCTURE, MANUFACTORING PROCESS Of UNDISPOSITIF SEMICONDUCTOR AND MANUFACTORING PROCESS Of an ELECTRONIC INSTRUMENT

A semiconductor device includes two semiconductor chips that are interposed between a pair of radiation members, and thermally and electrically connected to the radiation members. One of the radiation members has two protruding portions and front ends of the protruding portions are connected to principal electrodes of the semiconductor chips. The radiation members are made of a metallic material containing Cu or Al as a main component. The semiconductor chips and the radiation members are sealed with resin with externally exposed radiation surfaces.

SMART CARD AND MANUFACTORING PROCESS Of SUCH a CHART

Miniaturized transistors

SEMICONDUCTOR CIRCUIT HAVING ACTIVE DEVICES EMBEDDED IN FLEXIBLE SHEET

MICROMINIATURE ELECTRICAL COMPONENT HAVING INTEGRAL INDEXING MEANS

Device semiconductor

GLASS PASSIVATED SEMICONDUCTOR DEVICE FABRICATION PROCESS

DEVICE OF NONDESTRUCTIVE DISASSEMBLING Of a MODULAR ELECTRONICS COMPONENT WELDS BY a PLURALITY OF THIMBLES OF CONNECTION ONTO a SUBSTRATE

BLOCK OF JUST CHIPS OF CIRCUITS

BLOC DE PUCES DE CIRCUITS INTEGRES COMPRENANT UN SUBSTRAT 1; UNE PLURALITE DE PUCES 2 DE CIRCUITS INTEGRES, CHAQUE PUCE COMPORTANT UNE PLURALITE DE FILS FLEXIBLES 6 SUR SON CORPS ET ETANT CONNECTEE ELECTRIQUEMENT ET MECANIQUEMENT AU SUBSTRAT VIA CES FILS; UNE PLURALITE DE PLAQUES RAYONNANT LA CHALEUR 9, CONSTITUEES CHACUNE D'UN BON CONDUCTEUR THERMIQUE ET RELIEES RIGIDEMENT AUX PUCES DE CIRCUITS INTEGRES DANS UNE RELATION UN-A-UN, PAR UNE PREMIERE COLLE 10 AYANT UNE IMPEDANCE THERMIQUE RELATIVEMENT FAIBLE; UNE COIFFE 4 RAYONNANT LA CHALEUR, CONSTITUEE D'UN BON CONDUCTEUR DE LA CHALEUR POUR RECOUVRIR UNE SURFACE DE MONTAGE DE PUCE DE SUBSTRAT ET MAINTENUE EN CONTACT AVEC LES PLAQUES RAYONNANT LA CHALEUR PAR L'INTERMEDIAIRE D'UNE SECONDE COLLE 3 AYANT UNE IMPEDANCE THERMIQUE RELATIVEMENT PLUS FAIBLE; UN RADIATEUR DE CHALEUR 5 MONTE RIGIDEMENT SUR LA COIFFE; ET UNE PLURALITE DE BORNES 8 FIXEES A UNE SURFACE DE NON-MONTAGE DE PUCE DU SUBSTRAT POUR L'ENTREE ET LA SORTIE DE SIGNAUX VIS-A-VIS DES PUCES ET LA FOURNITURE D'UNE TENSION AUX PUCES A PARTIR D'UNE SOURCE D'ALIMENTATION. BLOCK OF INTEGRATED CIRCUITS CHIPS INCLUDING A SUBSTRATE 1; A PLURALITY OF CHIPS 2 OF INTEGRATED CIRCUITS, EACH CHIP CONTAINING A PLURALITY OF FLEXIBLE WIRES 6 ON ITS BODY AND BEING ELECTRICALLY AND MECHANICALLY CONNECTED TO THE SUBSTRATE VIA THESE WIRES; A PLURALITY OF HEAT RADIANT PLATES 9, EACH CONSTITUTED OF A GOOD THERMAL CONDUCTOR AND RIGIDLY CONNECTED TO THE CHIPS OF CIRCUITS INTEGRATED IN A ONE-TO-ONE RELATIONSHIP, BY A FIRST GLUE 10 HAVING A RELATIVELY LOW THERMAL IMPEDANCE; A HEAT RADIANT CAP 4, CONSTITUTED OF A GOOD HEAT CONDUCTOR TO COVER A SUBSTRATE CHIP MOUNTING SURFACE AND KEEP IN CONTACT WITH THE HEAT RADIANT PLATES THROUGH A SECOND GLUE 3 HAVING AN IMPEDANCE RELATIVELY LOWER; A HEAT RADIATOR 5 MOUNTS RIGIDLY ON THE HOODING; AND A PLURALITY OF 8 TERMINALS ATTACHED TO A NON-CHIP MOUNTING SURFACE OF THE SUBSTRATE FOR INPUT AND OUTPUT OF SIGNALS TO ...

METHOD OF MAKING A SEMICONDUCTOR DEVICE

TRANSISTOR AND ITS PROCESS OF PRODUCTION.

SEMICONDUCTOR DEVICE HAS RADIANT STRUCTURE, MANUFACTORING PROCESS Of a DEVICE SEMICONDUCTOR AND MANUFACTORING PROCESS Of an ELECTRONIC INSTRUMENT

Ledit dispositif comprend deux puces semi-conductrices (1a, 1b), interposées entre une paire de pièces de rayonnement (2, 3) auxquelles elles sont raccordées thermiquement et électriquement. L'une (2) des pièces de rayonnement possède deux régions saillantes (2a), et des extrémités antérieures desdites régions saillantes (2a) sont raccordées à des électrodes principales des puces (1a, 1b). Les pièces de rayonnement (2, 3) sont fabriquées en un matériau métallique contenant du cuivre ou de l'aluminium en tant que composant principal. Lesdites puces (1a, lb) et lesdites pièces (2, 3) sont scellées à l'aide d'une résine (9), avec des surfaces rayonnantes (10) dépassant vers l'extérieur.

CERAMIC SUBSTRATE MULTI-LAYER FOR COMPONENT OF POWER, MODULATES AND ELECTRONIC CIRCUIT COMPRISING THE SUBSTRATE AND MANUFACTORING PROCESS OF THE SUBSTRATE

L'invention conceme un substrat constitué d'une structure multicouches en céramique (1) comportant des interconnexions électriques et des composants intégrés, caractérisé en ce qu'il comporte en outre, au moins une cavité (2) remplie d'un dépôt conducteur (3) sur au moins une portion de sa profondeur, ledit dépôt conducteur étant destiné à constituer un puits thermique pour recevoir un composant de puissance. Avantageusement le dépôt conducteur est obtenu par voie électrolytique qui est une opération faible coût, réalisable collectivement. L'invention conceme également le module intégrant un composant de puissance au niveau du dépôt conducteur, ainsi que le circuit électronique dans lequel le module est associé à un circuit imprimé. Applications : Hyperfréquences, Radiofréquences.

Treatment of a platelet of bites including the application of an anisotropic carrier adhesive

Pour le traitement d'une plaquette (15) de puces (4), ultérieur à sa production, avec des étape de : . découpe ou "dicing "; . application d'un adhésif (13) anisotropique de report; et . report sur ce substrat de la puce (4); on prévoit que l'adhésif (13) est appliqué, directement ou indirectement, sur la plaquette (15); le rapport d'aires entre celles d'une part d'une surface utile de la plaquette (15) ou puce (4), sur d'autre part celle d'une surface de dépôt d'adhésif (13) appliqué, étant de l'ordre de 80-85 % à 90-95 %.

Method and device for three-dimensional encapsulation of semiconductor chips

L'invention a pour objet une encapsulation en trois dimensions de pastilles semi-conductrices, chacune contenant par exemple un circuit intégré, cette encapsulation visant à optimiser l'évacuation thermique par conduction. Selon l'invention, à chaque pastille (1) sont associés des moyens de connexion, permettant de prolonger les plots de pastilles vers trois côtés de la pastille et dégageant ainsi le quatrième côté. Les pastilles sont empilées les unes sur les autres puis reliées à des moyens d'évacuation thermique (9) par leur quatrième côté.

Method for forming a bump on a semiconductor wafer and a semiconductor wafer on which a bump is formed by it

Dicing die attach film and semiconductor packaging method using the same

본 발명에 따르면, 반도체 웨이퍼의 일면에 부착되는 다이접착층; 상기 반도체 웨이퍼를 다이 단위로 절단하기 위한 다이싱 다이에 부착되는 다이싱필름층; 및 상기 다이접착층과 상기 다이싱필름층 사이에 적층되는 중간층;을 포함하고, 상기 중간층의 탄성 모듈러스는, 상기 다이접착층 및 상기 다이싱필름층의 탄성 모듈러스보다 크며, 100 ~ 3000 MPa인 것을 특징으로 하는 다이싱 다이 접착필름이 개시된다. According to the present invention, a die bonding layer attached to one surface of a semiconductor wafer; A dicing film layer attached to a dicing die for cutting the semiconductor wafer in die units; And an intermediate layer laminated between the die adhesion layer and the dicing film layer, wherein the elastic modulus of the intermediate layer is greater than the elastic modulus of the die adhesion layer and the dicing film layer, and is 100 to 3000 MPa. A dicing die adhesive film is disclosed.

FABRICATION METHOD OF SEMICONDUCTOR DEVICE

PRINTED WIRING BOARD

Disclosed is a printed wiring board wherein a solder resist layer is formed on the surface of a wiring board which is provided with a conductor circuit, a part of the conductor circuit exposed from an opening formed in the solder resist layer is formed into a conductor pad, a solder bump is formed on the conductor pad, an electronic component is mounted on the board via the solder bump, and the electronic component is sealed with an underfill resin. In this printed wiring board, the surface of the solder resist layer is planarized at least in the electronic component mounting region or the planarized surface is further subjected to a roughening treatment. Also disclosed is a method for manufacturing such a printed wiring board. © KIPO & WIPO 2008 ...

FINE PITCH MICROCONTACTS AND METHOD FOR FORMING THEREOF

A method includes applying a final etch-resistant material 34 to an in-process substrate 10 so that the final etch-resistant material 34 at least partially covers first microcontact portions 32 integral with the substrate 10 and projecting upwardly from a surface 18 of the substrate, and etching the surface of the substrate 10 so as to leave second microcontact portions 36 below the first microcontact portions 32 and integral therewith, the final etch-resistant material 34 at least partially protecting the first microcontact portions 32 from etching during the further etching step. A microelectronic unit includes a substrate 10, and a plurality of microcontacts 38 projecting in a vertical direction from the substrate 10, each microcontact 38 including a base region 42 adjacent the substrate and a tip region 32 remote from the substrate, each microcontact 38 having a horizontal dimension which is a first function of vertical location in the base region 42 and which is a second function of ...

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

Method of post-mold grinding a semiconductor package

A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.

Manufacturing method for semiconductor integrated device

In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.

SEMICONDUCTOR PACKAGE WITH CONDUCTIVE CLIP

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can. 117-. (canceled)18. A method comprising:forming at least one terminal for a semiconductor package;forming a dielectric body to electrically insulate said at least one terminal from a conductive clip of said semiconductor package;connecting a power electrode of a power semiconductor device to said conductive clip.19. The method of further comprising depositing a solder resist over at least a portion of said at least one terminal.20. The method of further comprising forming a conductive pad for said semiconductor package.21. The method of further comprising forming a track to connect said conductive pad to said at least one terminal.22. The method of claim 18 , wherein said conductive clip is plated with either gold or silver.23. The method of claim 18 , wherein said dielectric body comprises polymer.24. The method of claim 18 , wherein said dielectric body comprises dielectric particles in an organic base.25. The method of claim 24 , wherein said organic base comprises one of epoxy claim 24 , acrylate claim 24 , polyimide and organopolysiloxane.26. The method of claim 24 , wherein said dielectric particles comprise a metal oxide.27. The method of claim 26 , wherein said metal oxide is alumina. This application is a continuation of U.S. application Ser. No. 11/799,140, filed May 1, 2007, entitled Semiconductor Package which is a division of U.S. application Ser. No. 11/405,825, filed Apr. 18, 2006, entitled Semiconductor Package which is based on and claims benefit of U.S. Provisional Application No. 60/674,162, filed on Apr. 21, 2005, entitled Semiconductor Package, to which a claim of priority is hereby made and the disclosure of which is incorporated by reference.The present invention relates to semiconductor packages ...

SEPARATION OF ALPHA EMITTING SPECIES FROM PLATING BATHS

A non alpha controlled plating bath including Tin species and a trace amount of Polonium species is utilized in a plating tool. The plating tool includes a Polonium filter element to remove Polonium species from the plating bath to selectively plate Tin upon a plating cathode. The filter may include a Titanium inner portion surrounding by a stannic oxide exterior. The filter may reduce the Polonium species by having the polonium absorb and then enter within the stannic oxide matrix. The filter may be located within the plating tool reservoir or filter housing. The filter may be fabricated by forming Tin upon a Titanium backbone and converting the Tin to stannic oxide. 1. A method of fabricating a filter comprising a Polonium (Po) filter element that filters Po , the method comprising:forming a Tin (Sn) exterior upon a Titanium (Ti) interior, and;converting the Sn exterior to a stannic oxide exterior.2. The method of claim 1 , wherein forming Sn upon the Ti interior further comprises:immersing the Ti interior in a Tin(II) Methane Sulfonate solution.3. The method of claim 2 , wherein pure Sn reduces onto the Ti interior and Ti(II) is corroded into the Tin(II) Methane Sulfonate solution.4. The method of claim 1 , wherein converting the Sn to stannic oxide further comprises:heating the Sn exterior in air at a temperature below the melting point of Sn to oxidize the Sn to stannic oxide.5. The method of claim 1 , wherein converting the Sn to stannic oxide comprises:heating the Sn exterior in air at 150° C. Embodiments of invention generally relate to the fabrication of semiconductor devices, such as a wafer, semiconductor chip, chip carrier, etc. More particularly, embodiments relate to removing alpha particle emitting species, such as Polonium (Po), from a plating bath utilized in the fabrication of conductive elements, such as contacts, in semiconductor devices.Formation of integrated circuit structures of a semiconductor device may utilize plating processes. During ...

SEPARATION OF ALPHA EMITTING SPECIES FROM PLATING BATHS

A non alpha controlled plating bath including Tin species and a trace amount of Polonium species is utilized in a plating tool. The plating tool includes a Polonium filter element to remove Polonium species from the plating bath to selectively plate Tin upon a plating cathode. The filter may include a Titanium inner portion surrounding by a stannic oxide exterior. The filter may reduce the Polonium species by having the polonium absorb and then enter within the stannic oxide matrix. The filter may be located within the plating tool reservoir or filter housing. The filter may be fabricated by forming Tin upon a Titanium backbone and converting the Tin to stannic oxide. 1. A plating tool comprising:a reservoir comprising a plating solution comprising a trace amount of Polonium (Po), and;a filter comprising a Polonium (Po) filter element that filters Po.2. The plating tool of claim 1 , wherein the filter further comprises a Titanium (Ti) interior.3. The plating tool of claim 2 , wherein the filter further comprises a stannic oxide exterior upon the Ti interior.4. The plating tool of claim 1 , wherein the filter is a mesh.5. The plating tool of claim 1 , wherein the filter is located within the reservoir.6. The plating tool of claim 1 , wherein the filter is located within a filter housing of the plating tool.7. The plating tool of claim 1 , wherein the trace amount of Po is absorbed by the filter.8. The plating tool of claim 1 , wherein the plating solution further comprises a Sn specie.9. The plating tool of claim 8 , further comprising:a semiconductor wafer, and wherein the Sn specie reduces to Sn upon the semiconductor wafer.10. The plating tool of claim 9 , wherein the filter reduces the alpha emission rate of the semiconductor wafer. Embodiments of invention generally relate to the fabrication of semiconductor devices, such as a wafer, semiconductor chip, chip carrier, etc. More particularly, embodiments relate to removing alpha particle emitting species, such as ...

SEPARATION OF ALPHA EMITTING SPECIES FROM PLATING BATHS

A non alpha controlled plating bath including Tin species and a trace amount of Polonium species is utilized in a plating tool. The plating tool includes a Polonium filter element to remove Polonium species from the plating bath to selectively plate Tin upon a plating cathode. The filter may include a Titanium inner portion surrounding by a stannic oxide exterior. The filter may reduce the Polonium species by having the polonium absorb and then enter within the stannic oxide matrix. The filter may be located within the plating tool reservoir or filter housing. The filter may be fabricated by forming Tin upon a Titanium backbone and converting the Tin to stannic oxide. 1. A semiconductor wafer fabrication system comprising:a semiconductor wafer attached to a plating tool that plates Tin (Sn) to the semiconductor wafer, the plating tool comprising a reservoir that contains a plating solution comprising a Sn specie and a trace amount of a Polonium (Po) specie, the plating tool further comprising a filter that filters Po to reduce the Po specie within the plating solution.2. The semiconductor wafer fabrication system of claim 1 , wherein the filter is located in the reservoir of the plating tool.3. The semiconductor wafer fabrication system of claim 1 , wherein the filter is located in a filter housing of the plating tool.4. The semiconductor wafer fabrication system of claim 1 , wherein the filter comprises a Titanium (Ti) interior surrounded by a stannic oxide exterior. Embodiments of invention generally relate to the fabrication of semiconductor devices, such as a wafer, semiconductor chip, chip carrier, etc. More particularly, embodiments relate to removing alpha particle emitting species, such as Polonium (Po), from a plating bath utilized in the fabrication of conductive elements, such as contacts, in semiconductor devices.Formation of integrated circuit structures of a semiconductor device may utilize plating processes. During plating, a metal or other ...

METHOD FOR MICROSTRUCTURE MODIFICATION OF CONDUCTING LINES

A method for microstructure modification of conducting lines is provided. An electroplating process is performed to deposit the metal thin film/conducting line(s) with a face-centered cubic (FCC) structure and a preferred crystallographic orientation over a surface of a substrate. The metal thin film/ conducting line(s) is subsequently subjected to a thermal annealing process to modify its microstructure with the grain sizes in a range of 5 μm to 100 μm. The thermal annealing process is conducted at the temperature of above 25 degrees Celsius and below 240 degrees Celsius. 1. A method for microstructure modification of conducting lines , comprising:performing an electroplating process to deposit a metal thin film with a preferred crystallographic orientation over a surface of a substrate; andperforming a heat treatment on the metal thin film, to make the metal thin film having the crystal grain sizes in a range of 5 μm to 100 μm, wherein the heat treatment is conducted at a temperature in a range of above 25 degree Celsius and below 240 degree Celsius;wherein the metal thin film has a plurality of crystal grains with the preferred crystallographic orientation before the heat treatment is applied to the metal thin film and less than 50% of structure surface of the metal thin film can have the (111) crystal plane preferred orientation with a nanotwinned structure.2. The method for microstructure modification of conducting lines according to claim 1 , wherein the substrate comprises a conducting substrate claim 1 , an insulating substrate or a combination thereof.3. The method for microstructure modification of conducting lines according to claim 1 , wherein the electroplating process is performed with a plating current density in a range of 0.1 ASD to 10.0 ASD.4. The method for microstructure modification of conducting lines according to claim 1 , wherein the metal thin film has a thickness in a range of 0.1 μm to 500 μm.5. The method for microstructure modification ...

Semiconductor Package with Conductive Clip

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

SEMICONDUCTOR MEMORY DEVICE STRUCTURE

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. 1. (canceled)2. A system , comprising:a plurality of transistors in contact with a substrate;an insulating portion formed over one of the plurality of transistors, the insulating portion having a plurality of openings;a bond pad formed within each opening of the plurality of openings;an array of memory cells; and select a memory cell within the array of memory cells; and', 'access the selected memory cell within the array of memory cells., 'a memory controller coupled with the array of memory cells, wherein the memory controller is operable to3. The system of claim 2 , wherein the array of memory cells is formed over the insulating portion.4. The system of claim 2 , wherein the array of memory cells is formed over the bond pad formed within each of the plurality of openings.5. The system of claim 2 , further comprising:an electrode layer formed over the array of memory cells, wherein the electrode layer comprises a conductive material.6. The system of claim 2 , wherein each of the memory cells comprises a resistance variable cell material.7. The system of claim 2 , wherein a memory cell of the array of memory cells comprises a phase change material (PCM).8. The system of claim 2 , further comprising:a nickel cap formed over the bond pad.9. The system of claim 2 , wherein the bond pad comprises copper.10. The system of claim 2 , wherein each memory cell of the array of memory cells comprises a layer of germanium selenide claim 2 , a layer of chalcogenide glass claim 2 , a layer of silver claim 2 , or a combination thereof.11. The system of claim 2 , wherein the memory controller is in electronic communication with an input/output (I/O) device via a bus.12. An apparatus claim 2 , comprising:a substrate ...

Semiconductor memory device structure

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

Method for low temperature bonding and bonded structure

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO 2 . The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

Methods and apparatuses for assembling elements onto a substrate

Methods and apparatuses for assembling elements onto a substrate. The surfaces of the elements and/or the substrate are treated and the elements are dispensed over the substrate in a slurry. In one example of the invention, the substrate is exposed to a surface treatment fluid to create a surface on the substrate which has a selected one of a hydrophilic or a hydrophobic nature, and a slurry is dispensed over the substrate. The slurry includes a fluid and a plurality of elements (each of which includes a functional component). Each of the plurality of elements is designed to be received by a receptor region on the substrate. The dispensing of the slurry with the fluid occurs after the substrate is exposed to the surface treatment fluid, and the fluid is the selected one of a hydrophilic or a hydrophobic nature. In another example of the invention, a plurality of elements is exposed to a surface treatment fluid to create surfaces on the elements having a selected one of a hydrophilic or a hydrophobic nature. A slurry is dispensed over a substrate, wherein the slurry contains a fluid and the plurality of elements which are designed to be received by a plurality of receptor regions. The fluid is the selected one of a hydrophilic or hydrophobic nature. In another example of an aspect of the invention, a surfactant is used with a slurry having elements which are deposited onto receptor regions in a fluidic self assembly process. Other examples of methods are also described.

Copper bonding wire for semiconductor packaging

Provided is a copper bonding wire formed of a high purity copper of 99.999% or more including at least one of P and Nb within a range between 20 wt ppm and 100 wt ppm and at least one of Zr, Sn, Be, Nd, Sc, Ga, Fr, and Ra within a range between 1 wt ppm and 100 wt ppm. Here, a total content of the added elements is restricted within a range between 20 wt ppm and 200 wt ppm, and a residual amount of the copper bonding wire is a high purity copper of 99.98% or more. As a result, metal squeeze out and chip cratering can be reduced in a general semiconductor chip and a low dielectric semiconductor chip. Also, a short tail of the copper bonding wire occurring during bonding of the copper bonding wire to a lead finger can be reduced.

Hardening flux, soldering resist, semiconductor package reinforced by hardening flux, semiconductor device and method of producing semiconductor package and semiconductor device

A hardening flux acting as a flux during soldering and, when hardened by heating, acting as a reinforcing material for the soldered joint; a soldering resist; a semiconductor package wherein the hardening flux is applied to the circuit exposed surface, solder balls are joined and the solder ball joint is reinforced by the flux which is hardened by heating; a semiconductor device wherein said hardening flux is applied to a semiconductor mounting board having a soldering land and is soldered, and wherein the flux, which is hardened by heating, reinforces the solder joint; and a method of producing said package and said device. A hardening flux which acts as a flux in soldering a semiconductor package to a semiconductor mounting board and which, after soldering, is hardened by further heating to serve as a reinforcing agent for the solder joint; a soldering resist; a semiconductor package reinforced by the hardening flux; a semiconductor device; and a method of producing said semiconductor package and semiconductor device.

印刷线路板及其印刷线路板的制造方法

本发明提供一种印刷线路板及其印刷线路板的制造方法，该制造方法可以在阻焊层的开口直径不同的连接焊盘上以大致相同的高度形成凸块。由被搭载在阻焊层(70)的小直径开口(71S)上的焊锡球(77)形成为高度较高的小直径凸块(78S)，平坦化该小直径凸块(78S)，使其与大直径开口(71P)的焊锡凸块(78P)高度相同。小直径开口(71S)的焊锡凸块(78S)与大直径开口(71P)的焊锡凸块(78P)的焊锡量相同，使用小直径开口(71S)的焊锡凸块(78S)不会产生未连接，可以确保IC芯片(90)与多层印刷线路板(10)的连接可靠性。

Method of coating fine wires and curable composition therefor

A method of reducing wire sweep and shorting during fabrication of a semiconductor device includes spraying a curable composition onto wire bonds, and free-radically B-staging the curable composition, and then thermal curing to a C-stage. A sprayable curable composition is also disclosed.

Electronic component used as a semiconductor chip comprises an electrically conducting adhesive layer between the metallic surfaces of components of the electronic component

Electronic component comprises an electrically conducting adhesive layer (2) between the metallic surfaces (3) of components (4) of the electronic component (1). The metallic surfaces lie opposite each other and the adhesive (5) has agglomerates (6) of electrically conducting nano-particles (7) having electrically conducting paths (9) surrounding the nano-particles in the adhesive base composition. Electronic component comprises an electrically conducting adhesive layer (2) between the metallic surfaces (3) of components (4) of the electronic component (1). The metallic surfaces lie opposite each other and the adhesive (5) has agglomerates (6) of electrically conducting nano-particles (7) having electrically conducting paths (9) surrounding the nano-particles in the adhesive base composition. The opposite-lying surfaces are electrically connected via a number of agglomerates of electrically conducting nano-particles distributed in the adhesive layer. An Independent claim is also included for a process for the production of an electronic component.

印刷线路板及其制造方法

本发明提供一种印刷线路板及其制造方法，在形成有导体电路的布线基板的表面上设置阻焊层，并使从设于该阻焊层的开口部露出的上述导体电路的一部分形成为导体焊盘，在该导体焊盘上形成焊锡凸块，通过该焊锡凸块安装电子部件，通过欠装材料而用树脂密封该电子部件，其中，阻焊层表面中至少电子部件安装区域被实施了平坦化处理，或者对该被平坦化处理过的表面进一步实施粗糙化处理。

UBM Etching Methods

디바이스 형성 방법은 장벽층과 장벽층 위의 씨드층을 포함하는 범핑 하지 금속(UBM)층을 형성하는 단계와; 상기 UMB층 위에 마스크를 형성하는 단계를 포함한다. 마스크는 UBM층의 제1 부분을 피복하고, UBM층의 제2 부분은 마스크의 개구를 통해 노출된다. UBM층의 제1 부분은 장벽층 부분과 씨드층 부분을 포함한다. 금속 범프는 개구 내에 그리고 UBM층의 제2 부분 상에 형성된다. 그 다음, 마스크가 제거된다. 씨드층 부분을 제거하기 위해 습식 에칭이 수행된다. 장벽층 부분을 제거하기 위해 건식 에칭이 수행된다. The device forming method includes forming a bumping base metal (UBM) layer comprising a barrier layer and a seed layer over the barrier layer; Forming a mask on the UMB layer. The mask covers the first portion of the UBM layer, and the second portion of the UBM layer is exposed through the opening of the mask. The first portion of the UBM layer includes a barrier layer portion and a seed layer portion. Metal bumps are formed in the openings and on the second portion of the UBM layer. The mask is then removed. Wet etching is performed to remove the seed layer portion. Dry etching is performed to remove the barrier layer portion.

Contact assembly

FIELD: non-split joints for microelectronic and semiconductor devices. SUBSTANCE: contact assembly has at least two metal-coated contacts coupled with current-carrying tracks placed on switching-layer surfaces on insulating substrate, joined together, and interconnected electrically and mechanically by means of electricity conducting binder. Contact assembly is, essentially, joint between metal-coated contact pad coupled with current-carrying tracks on surface of lower switching layer and mating contact made in the form of metal-coated hole in insulating layer. EFFECT: enlarged functional capabilities of contact assembly. 23 cl, 6 dwg зб с ПЧ ГЭ РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (19) (51) МПК ВИ” 2134 498 13) СЛ Н 05 К 1/41, 3/36, 3/42, 13/04, Н 01 В 4/00, 9/09 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21), (22) Заявка: 98121773109, 08.12.1998 (24) Дата начала действия патента: 08.12.1998 (46) Дата публикации: 10.08.1999 (56) Ссылки: Моряков О.С. Технология полупроводниковых приборов и изделий микроэлектроники. - М.: Высшая школа, 1990, с.38-40. ОЕ 4040226 05, 17.06.92. ЕР 0493103 А2, 01.07.92. ЗЦ 1739529 АЛ, 07.06.92. $ 1757138 АЛ, 23.08.92. (98) Адрес для переписки: 117333, Москва, Ленинский пр-т, 60/2-160, Таран А.И. (71) Заявитель: Таран Александр Иванович (72) Изобретатель: Таран А.И. (73) Патентообладатель: Таран Александр Иванович (54) КОНТАКТНЫЙ УЗЕЛ (57) Реферат: Изобретение относится к изготовлению неразъемных соединений в процессе производства аппаратуры на основе изделий микроэлектроники и — полупроводниковых приборов, а конкретно - к контактным узлам, посредством которых осуществляется сборка, в том числе многослойных коммутационных структур для многокристальных модулей (МКМ)а также монтаж кристаллов БИС на коммутационной структуре в процессе изготовления МКМ. Контактный узел содержит по крайней мере два металлизированных контакта, связанных с токоведущими дорожками, размещенными на поверхностях коммутационных слоев, ...

접촉노드

본 발명은 마이크로전자공학 부품 및 반도체 디바이스에 기초한 장비의 제조시 영구적인 연결부를 제조하는 것에 관한 것으로, 특히 마이크로칩 모듈(MCM)의 제조시 LSIC 칩의 장착공정이 수행될 뿐만 아니라 MCM을 위한 다층 연결플레이트의 조립공정을 위한 접촉 노드에 관한 것이다. 상기 접촉노드는 유전체 재질의 베이스위에 형성되고 상호 정렬되며 도전성 바인딩재에 의해 전기적 및 기계적으로 상호연결된 연결층 표면상에 배치된 도전성 경로에 연결된 적어도 두개의 메탈라이즈 접촉부를 포함한다. 상기 접촉노드는 연결층 표면상의 도전성 경로에 연결된 메탈라이즈 접촉패드 형태로 형성된 접촉부와, 상기 패드와 접합되고 상부 연결층의 메탈라이즈 홀 형태로 형성된 각각의 접촉부 사이의 접합부 형태로 형성되며, 상기 메탈라이즈 홀의 하측 엣지부는 하부 연결층 표면상의 메탈라이즈 접촉패드를 향해 있고, 상기 메탈라이즈 홀의 상측 엣지부는 상부 연결층의 상측면위 도전층 경로에 연결된다.

Copper bonding wire for semiconductor packaging

P 및 Nb 중의 적어도 어느 하나가 20-100 중량ppm으로 첨가된 99.999% 이상의 고순도 구리(Cu)에 Zr, Sn, Be，Nd, Sc, Ga, Fr 및 Ra 중의 적어도 어느 하나가 1-100 중량ppm의 범위로 첨가된 것으로, 첨가원소의 전체 함유량이 20-200 중량ppm으로 제한되고 잔여량은 99.98% 이상의 고순도 구리로 구성되는 구리 본딩 와이어를 개시한다. 이러한 구리 본딩 와이어는 일반적인 반도체 칩뿐만 아니라 저유전체 반도체 칩에서도 패드 밀림 및 칩 패임 현상을 감소시키고 리드 핑거와의 접합시 발생하는 구리 본딩 와이어의 길이 부족 현상을 감소시킨다.  At least one of Zr, Sn, Be, Nd, Sc, Ga, Fr, and Ra is 1-100 ppm by weight to 99.999% or more of high purity copper (Cu) in which at least one of P and Nb is added by 20-100 ppm by weight In addition, the present invention discloses a copper bonding wire in which the total content of added elements is limited to 20-200 ppm by weight and the remaining amount is composed of high purity copper of 99.98% or more. Such copper bonding wires reduce pad push and chip dents in low dielectric semiconductor chips as well as general semiconductor chips, and reduce the shortage of copper bonding wires generated when bonding the lead fingers.

Light-emitting diode package using a liquid crystal polymer

一种使用液晶聚合物的发光二极管(LED)封装件包括：封装件主体，通过使用液晶聚合物形成；引线框架，形成在所述封装件主体上；LED芯片，安装在所述引线框架上；树脂封装单元，封装所述LED芯片，所述树脂封装单元含有磷光体。所述LED封装件是非常可靠的。

Method for fabricating self-assembling microstructures

A method for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the microstructure becomes integral with the substrate 20, 70, 90, 120, 200. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then poured evenly over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.

Method for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Method for fabricating self-assembling microstructures

一种通过液体传送将微结构组装到衬底上的方法。呈成型模块(19)的微结构自对准到位于衬底(50)上的凹槽区域(55)，使微结构变成与衬底结合起来。所改进的方法包括将成型模块移入液体形成一种悬浮物的步骤，然后将这种悬浮物均匀地倾倒在其上具有凹槽区域的衬底的顶面(53)的上方。通过成型和流体的作用微结构跌落到衬底的表面，自对准并接合到凹槽区域。

Substrate for packaging a semiconductor device, packaging structure and method

내용 없음. No content.

Printed wiring board

本发明提供一种印刷线路板及其制造方法，在形成有导体电路的布线基板的表面上设置阻焊层，并使从设于该阻焊层的开口部露出的上述导体电路的一部分形成为导体焊盘，在该导体焊盘上形成焊锡凸块，通过该焊锡凸块安装电子部件，通过欠装材料而用树脂密封该电子部件，其中，阻焊层表面中至少电子部件安装区域被实施了平坦化处理，或者对该被平坦化处理过的表面进一步实施粗糙化处理。

Soldering method, soldering apparatus and method for manufacturing semiconductor device

将焊接目标(92)容纳在能够密闭的容器(17)内。向容器(17)内提供还原性气体，从而使容器(17)的内压(P)上升到常压(Po)以上。在该加压状态下，进行针对电路板(11)的半导体元件(12)的焊接。在从焊料(33)的熔融开始(t3)到该熔融焊料(33)凝固(t7)的焊料熔融阶段(t3～t7)，维持显示设定压力P1(例如0.13MPa)的加压状态。因此，能够抑制凝固后的焊料中的空隙的产生。

Printed wiring board

1 칩에 2 개의 프로세서 코어 (81A, 81B) 를 포함하는 듀얼 코어 프로세서 (80) 를 탑재할 수 있는 실장부 (60) 와, 각 프로세서 코어 (81A, 81B) 마다 독립적으로 형성된 전원 라인 (12A, 12B), 그라운드 라인 (11A, 11B), 제 1 및 제 2 층상 콘덴서 (40A, 40B) 를 구비한 것이다. 이 때문에, 각 프로세서 코어 (81A, 81B) 의 전위가 순간적으로 저하되더라도 그것에 대응하는 층상 콘덴서 (40A, 40B) 의 작용에 의해 전위의 순간적 저하를 억제할 수 있고, 1 개의 프로세서 코어의 전압이 변동되더라도 그 전압 변동이 나머지 프로세서 코어에 영향을 주지 않기 때문에 오동작이 발생하지도 않는다. A mounting unit 60 capable of mounting a dual-core processor 80 including two processor cores 81A and 81B on one chip, and a power line 12A independently formed for each processor core 81A and 81B; 12B), ground lines 11A, 11B, and first and second layered capacitors 40A, 40B. For this reason, even if the potential of each of the processor cores 81A and 81B decreases momentarily, the instantaneous drop of the potential can be suppressed by the action of the layered capacitors 40A and 40B corresponding thereto, and the voltage of one processor core fluctuates. Even if the voltage fluctuation does not affect the rest of the processor core, no malfunction occurs. 프린트 배선판, 빌드업부, 듀얼 코어 프로세서, 층상 콘덴서 Printed Wiring Board, Build-Up, Dual Core Processor, Layered Capacitor

Conductor substrate and semiconductor device

Method for forming high performance system-on-chip using post passivation process

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Light emitting diode, optical semiconductor element and epoxy resin composition suitable for optical semiconductor element and production methods therefor

A light emitting diode comprising an LED chip having a light emitting layer made of a nitride compound semiconductor and a light transmitting resin that includes a fluorescent material which absorbs at least a part of light emitted by the LED chip and emits light of a different wavelength, wherein the fluorescent material includes a fluorescent particles of small particle size and a fluorescent particles of large particle size, the fluorescent particles of large particle size being distributed in the vicinity of the LED chip in the light transmitting resin to form a wavelength converting layer, the fluorescent particles of small particle size being distributed on the outside of the wavelength converting layer in the light transmitting resin.

Patent JPH0564224B2

PURPOSE:To obtain a low-cost copper wire for the titled bonding stabilizing the shape of a ball and having superior tensile strength by adding a specified amount in total of one or more among Mg, Al, Si, P and Ca to oxygen-free copper of a specified high purity. CONSTITUTION:A copper wire for bonding having increased tensile strength is obtd. by adding 3-40wt.ppm in total of one or more among Mg, Al, Si and P in the 3rd period elements and Ca in the 4th period elements to high purity oxygen-free copper of >=99.99wt% purity. The oxidation of the copper wire is prevented during the formation of a ball to form a clean spherical ball and the cracking of a chip and the breaking of a neck are prevented during bonding work.

Multilayer printed wiring board

고주파영역의 IC칩, 특히 3GHz를 초과하여도 오동작이나 에러가 발생하지 않는 패키지 기판을 제공하는 것을 목적으로 하며, 상기 목적을 해결하기 위해, 코어기판(30) 상의 도체층(34P)을 두께 30㎛로 형성하고, 층간수지절연층(50) 상의 도체회로(58)를 15㎛로 형성한다. 도체층(34P)을 두껍게 하므로, 도체 자체의 체적을 증가시키고, 저항을 저감시킬 수 있다. 또한, 도체층(34)을 전원층으로 사용하므로, IC칩으로의 전원 공급능력을 향상시킬 수 있다. An object of the present invention is to provide an IC chip in a high frequency region, in particular, a package substrate in which no malfunction or error occurs even in excess of 3 GHz. To solve the above object, the conductor layer 34P on the core substrate 30 has a thickness of 30. And the conductor circuit 58 on the interlayer resin insulating layer 50 is formed to 15 mu m. Since the conductor layer 34P is made thick, the volume of the conductor itself can be increased and the resistance can be reduced. In addition, since the conductor layer 34 is used as the power supply layer, the power supply capability to the IC chip can be improved.

Multilayer printed wiring board

고주파영역의 IC칩, 특히 3GHz를 초과하여도 오동작이나 에러가 발생하지 않는 패키지 기판을 제공하는 것을 목적으로 하며, 상기 목적을 해결하기 위해, 코어기판(30) 상의 도체층(34P)을 두께 30㎛로 형성하고, 층간수지절연층(50) 상의 도체회로(58)를 15㎛로 형성한다. 도체층(34P) 두껍게 하므로, 도체 자체의 체적을 증가시키고, 저항을 저감시킬 수 있다. 또한, 도체층(34)을 전원층으로 사용하므로, IC칩으로의 전원 공급능력을 향상시킬 수 있다. 다층프린트배선판 An object of the present invention is to provide an IC chip in a high frequency region, in particular, a package substrate in which no malfunction or error occurs even in excess of 3 GHz. And the conductor circuit 58 on the interlayer resin insulating layer 50 is formed to 15 mu m. Since the conductor layer 34P is made thick, the volume of the conductor itself can be increased and the resistance can be reduced. In addition, since the conductor layer 34 is used as the power supply layer, the power supply capability to the IC chip can be improved. Multilayer printed wiring board

Manufacturing method of semiconductor device

A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.

Patent JPH0573079B2

Doped alloys for electrical interconnects, methods of production and uses thereof

在此公开的焊料材料和掺杂剂包括至少一种焊料材料、至少一种磷基掺杂剂和至少一种铜基掺杂剂。形成掺杂焊料材料的方法包括：a)提供至少一种焊料材料；b)提供至少一种磷基掺杂剂；c)提供至少一种铜基掺杂剂，以及d)使该至少一种焊料材料、该至少一种磷基掺杂剂和该至少一种铜基掺杂剂混合，从而形成掺杂焊料材料。在此还公开了层状材料，其包括：a)表面或基底；b)电互连；c)如在此所述的、含有至少一种磷基掺杂剂和至少一种铜基掺杂剂的焊料材料，以及d)半导体芯片或封装。还设想了电子和半导体元件，其包括在此公开的焊料材料和/或层状材料。

Thermosetting resin composition and photosemiconductor encapsulation material

本发明提供一种热固性树脂组合物以及利用该组合物的光半导体周边材料，所述热固性树脂组合物以(A)含有下述通式(1)或通式(2)表示的化合物的有机聚硅氧烷为必要成分。[在此，式中R 1 各自独立地表示具有取代基或者无取代基的碳原子数为1～10的一价烃基，R 2 表示含有环氧基的有机基，R 3 表示R 1 或R 2 ，a各自独立地表示1以上的整数，b各自独立地表示0以上的整数，X表示通式(3)，Y表示-O-或碳原子数为1～6的二价烃基，Z表示下式(4)，式中R 1 各自独立地表示具有取代基或者无取代基的碳原子数为1～10的一价烃基，c表示0以上的整数。]

Light emitting diode, optical semiconductor device, epoxy resin composition suited for optical semiconductor device, and method for manufacturing the same

A LIGHT EMITTING DIODE COMPRISING AN LED CHIP HAVING A LIGHT EMITTING LAYER MADE OF A NITRIDE COMPOUND SEMICONDUCTOR AND A LIGHT TRANSMITTING RESIN THAT INCLUDES A FLUORESCENT MATERIAL WHICH ABSORBS AT LEAST A PART OF LIGHT EMITTED BY THE LED CHIP AND EMITS LIGHT OF A DIFFERENT WAVELENGTH, WHEREIN THE FLUORESCENT MATERIAL INCLUDES A FLUORESCENT PARTICLES OF SMALL PARTICLE SIZE AND A FLUORESCENT PARTICLES OF LARGE PARTICLE SIZE, THE FLUORESCENT PARTICLES OF LARGE PARTICLE SIZE BEING DISTRIBUTED IN THE VICINITY OF THE LED CHIP IN THE LIGHT TRANSMITTING RESIN TO FORM A WAVELENGTH CONVERTING LAYER, THE FLUORESCENT PARTICLES OF SMALL PARTICLE SIZE BEING DISTRIBUTED ON THE OUTSIDE OF THE WAVELENGTH CONVERTING LAYER IN THE LIGHT TRANSMITTING RESIN.

Corrosion resistance enhancement of tin surfaces

A method for enhancing corrosion resistance of a tin-based surface on a workpiece involving contacting the tin-based surface with a composition comprising a phosphonic acid compound and water to form a phosphorus-based film over the tin-based coating thereby inhibiting corrosion of the tin-based surface. Phosphonic acid containing compositions having a concentration up to about 30 vol. % of an organic solvent, and water.

Method for producing metal duplex having tin layer

Nanowires, nanostructures and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Bonding

1,138,401. Joining glass and metal. P. R. MALLORY & CO., Inc. 22 April, 1966 [6 May, 1965; 6 Dec., 1965], No. 17792/66. Heading C1M. [Also in Divisions B3, C7 and H1] An electrically conductive or semi-conductive material is joined to an insulating material (glass, quartz, sapphire) by forming an electrolytic interface layer of oxide, the joining being conducted at a temperature sufficiently high to render the non-conductive material electrically conducting but not sufficiently high to melt either component. The components are solid state electronic devices (see Division H1). Particular conductive or semi-conductive materials referred to are: silicon, aluminium, germanium, gallium arsenide, platinum, beryllium, titanium and palladium.

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

본 발명은 약 200 nm 미만의 균일한 직경을 갖는 1차원 나노구조체를 제공한다. "나노와이어"라 칭하는 이러한 본 발명의 나노구조체는 단결정 동형구조체 및 화학적 조성이 상이한 최소한 2개의 단결정 물질의 이형구조체를 포함한다. 단결정 물질이 이형구조체의 형성에 이용되기 때문에, 얻어지는 이형구조체도 단결정일 것이다. 나노와이어 이형구조체는 일반적으로 반도체 와이어를 기초로 하며, 상이한 물질을 포함하는 와이어를 산출하도록, 도핑 및 조성이 길이방향이나 반경방향으로, 또는 그 두 방향으로 제어된다. 얻어지는 나노와이어 이형구조체의 예로는 길이방향 이형구조체 나노와이어(LOHN) 및 동축 이형구조체 나노와이어(COHN)가 포함된다. The present invention provides one-dimensional nanostructures having a uniform diameter of less than about 200 nm. Such nanostructures of the present invention, referred to as "nanowires", include single crystal homostructures and heterostructures of at least two single crystal materials that differ in chemical composition. Since the single crystal material is used to form the release structure, the release structure obtained will also be single crystal. Nanowire release structures are generally based on semiconductor wires and doping and composition are controlled in the longitudinal or radial direction, or in both directions, to yield wires comprising different materials. Examples of the resulting nanowire release structures include longitudinal release structure nanowires (LOHN) and coaxial release structure nanowires (COHN). 나노구조체, 나노와이어, 이형구조체, 동형구조체, 초격자, 양자 도트, 이형접합, 에피택셜 성장, 에너지 전환 Nanostructures, nanowires, heterostructures, homostructures, superlattices, quantum dots, heterojunctions, epitaxial growth, energy conversion

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Metal duplex and its preparing method

揭示了方法和制品。所述方法涉及在基材上沉积镍二相层，以抑制锡和锡合金的表面氧化，以及改进基材的可焊性。

Thermosetting resin composition and photosemiconductor encapsulation material

본 발명은 (A) 하기 일반식(1) 또는 (2)로 나타내어지는 화합물을 함유하는 오르가노폴리실록산을 필수 성분으로 하는 열경화성 수지 조성물 및 이 조성물을 이용한 광반도체 주변 재료이다. [여기에서, 식 중, R 1 은 각각 독립적으로 치환 또는 비치환의 탄소수 1~10의 1가 탄화수소기, R 2 는 에폭시기 함유 유기기, R 3 은 R 1 또는 R 2 를 나타내고, a는 각각 독립적으로 1이상의 정수, b는 각각 독립적으로 0이상의 정수를 나타내고, X는 일반식(3)을 나타내고, Y는 -O- 또는 탄소수 1~6의 2가 탄화수소기를 나타내고, Z는 하기 식(4)를 나타내고, 식 중, R 1 은 각각 독립적으로 치환 또는 비치환의 탄소수 1~10의 1가 탄화수소기, c는 0이상의 정수를 나타낸다.] This invention is a thermosetting resin composition which has (A) organopolysiloxane containing the compound represented by following General formula (1) or (2) as an essential component, and the optical semiconductor peripheral material using this composition. [Wherein, R 1 each independently represents a substituted or unsubstituted monovalent hydrocarbon group having 1 to 10 carbon atoms, R 2 represents an epoxy group-containing organic group, R 3 represents R 1 or R 2 , and a each independently represents , An integer of 1 or more and b each independently represent an integer of 0 or more, X represents General Formula (3), Y represents -O- or a divalent hydrocarbon group having 1 to 6 carbon atoms, and Z represents the following Formula (4) In the formula, each R 1 independently represents a substituted or unsubstituted monovalent hydrocarbon group having 1 to 10 carbon atoms, and c represents an integer of 0 or more.] 열경화성 수지 조성물 Thermosetting resin composition

Selective heating apparatus

1,039,790. Soldering. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 2, 1963 [July 2, 1962], No. 26119/63. Heading B3R. An apparatus for making one or more solder connections between solder coated bodies, comprises a means for directing heat in a path of thin linear cross-section on to the line of juncture of the bodies. A module 10, Fig. 1, having pre-soldered connections 11 is to be joined to a base 12 having complementary connections (not shown). The apparatus comprises an arm 13 carrying one or more plates 15 of tungsten alumina or beryllium oxide heated by a supporting serpentine element 41 and a pair of locating claws 17, the plates and arms having limited movement in a vertical plane which is restrained when a handle-operated cam 19, 21 is out of engagement with a spring 18. The claws can be engaged with the module when the cam is vertical and in the position shown are released, for example at the end of each heating cycle. The arm 13 may move simply in a vertical plane, or may also have a lateral or swinging movement to obtain modules from a remote location and set them in the required position.

Method for manufacturing semiconductor apparatus, and semiconductor apparatus and electric appliance

According to the package and the method for manufacturing the package of the present invention, a chip can be formed extremely to be thin, and manufactured at lower cost and higher throughput, and the variations of a chip thickness can be reduced without back grind that causes cracks or polishing marks. In the present invention, a semiconductor film with a thickness of at most 500 μm deposited over a substrate serving as a support medium is crystallized with a CW laser light, and a chip having a semiconductor device is formed to have a total thickness of 5 μm, preferably at most 2 μm by using the crystallized semiconductor film. Consequently, the chip is mounted on an interposer after separating a substrate.

System for fabricating semiconductor components with through wire interconnects

A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

SOLDER PLATE INTERCONNECTION STRUCTURE

L'invention concerne la technologie des semiconducteurs. Un dispositif à semiconducteurs comportant une région active dans laquelle se trouvent des plots de métallisation 12, comporte une couche de polyimide 20 formée sur la région active ; une couche résistant au percement 22 formée sur la couche de polyimide ; et des interconnexions métalliques 24 qui connectent des plots de métallisation à des plots de soudage 30 situés sur la région active. La couche de polyimide et la couche résistant au percement protègent la région active au cours d'opérations de soudage par thermocompression effectuées sur le plot de soudage. Application à la fabrication de circuits intégrés. (CF DESSIN DANS BOPI) The invention relates to semiconductor technology. A semiconductor device comprising an active region in which there are metallization pads 12, comprises a polyimide layer 20 formed on the active region; a puncture resistant layer 22 formed on the polyimide layer; and metal interconnects 24 which connect metallization pads to solder pads 30 located on the active region. The polyimide layer and the puncture resistant layer protect the active region during thermocompression welding operations performed on the weld pad. Application to the manufacture of integrated circuits. (CF DRAWING IN BOPI)

DEVICE COMPRISING WELDING PLOTS FORMED ON A SUBSTRATE AND METHOD OF MANUFACTURING SUCH WELDING PLOTS

Dispositif comprenant des plots de soudage formés sur un substrat et méthode de fabrication de tels plots de soudage. Des plots de soudage (2) sont formés sur un substrat (3) et comprennent, en partant du substrat (3), une sous-couche d'accrochage (4), une couche intermédiaire de protection (5) et une couche de soudage (6). La couche intermédiaire (5) est en un alliage de deux métaux au moins, un premier métal (W) offrant la propriété d'une couche de barrière et un deuxième métal (Ti) offrant la propriété de mouillage, vis-à-vis de la couche de soudage. La proportion du premier métal (W) dans l'alliage diminue graduellement en direction de la couche de soudage, depuis une valeur assez élevée pour que la propriété de couche de barrière soit obtenue, jusqu'à une valeur qui soit assez faible pour que la part du deuxième métal (Ti) soit elle-même assez élevée pour que la propriété de mouillabilité soit obtenue. Device comprising solder pads formed on a substrate and a method of manufacturing such solder pads. Solder pads (2) are formed on a substrate (3) and include, starting from the substrate (3), a bonding sub-layer (4), an intermediate protective layer (5) and a solder layer (6). The intermediate layer (5) is made of an alloy of at least two metals, a first metal (W) offering the property of a barrier layer and a second metal (Ti) offering the wetting property, vis-à-vis the welding layer. The proportion of the first metal (W) in the alloy gradually decreases towards the weld layer, from a value high enough that the barrier layer property is obtained, to a value which is low enough that the part of the second metal (Ti) is itself high enough for the wettability property to be obtained.

POWER MODULE

SEMICONDUCTOR DEVICE WITH DIODE AND MANUFACTURING METHOD

Un dispositif à semiconducteur comprend un circuit électronique (112) formé sur un substrat semiconducteur (13); une borne (121) reliée au circuit électronique; et un élément de connexion en métal (3) connecté à la fois à la borne et à une région d'une surface du substrat qui est à nu en position adjacente à la borne. Avec cette structure, une diode dont l'une des électrodes est constituée par la surface du substrat, est formée entre l'élément de connexion (3) et le substrat, de façon à écouler des surtensions susceptibles d'être appliquées au circuit électronique (112). A semiconductor device includes an electronic circuit (112) formed on a semiconductor substrate (13); a terminal (121) connected to the electronic circuit; and a metal connection element (3) connected both to the terminal and to a region of a surface of the substrate which is exposed in position adjacent to the terminal. With this structure, a diode, one of the electrodes of which is formed by the surface of the substrate, is formed between the connection element (3) and the substrate, so as to pass overvoltages which can be applied to the electronic circuit ( 112).

semiconductor element having at least one pressure contact junction

Semiconductor rectifier device

Semiconductor device

MULTI-LAYER WIRING SUBSTRATE.

Semiconductor device processing method

Method for overall regulation of the headbox and/or the former of a paper machine or equivalent

A method for continuous overall regulation of the headbox/former of a paper or board machine. A physical fluid flow model of the suspension flow to be regulated is formed for the headbox (100)/former (100'). The model is solved based on data on a geometry of the headbox (100) and/or former (100') and initial and boundary conditions related to the headbox (100)/former (100'). A target flow state is determined based on quality requirements of the paper and costs of operation and runnability of the paper machine. The difference between the simulated flow state and the target flow state is determined as a cost function. The cost function is optimized and optimal regulation values and set values (C) and determined for instrumentation devices and actuators (105) of the headbox (100)/former (100'). Finally, new optimal regulation and set values (C) are provided to the headbox (100)/former (100') regulation devices.

POWER SEMICONDUCTOR ELEMENT COMPRISING TEMPERATURE DETECTION DIODES AND STATIC ELECTRICITY ABSORPTION DIODES AND SEMICONDUCTOR DEVICE HAVING THE SAME

SEMICONDUCTOR DEVICE COMPRISING A POWER DEVICE AND A CONTROL DEVICE FORMED ON MOUNTING FRAMES

L'invention consiste en un dispositif à semiconducteurs qui utilise un moulage par transfert pour simplifier une étape d'enrobage dans une résine, qui réduit le coût de fabrication en n'utilisant pas d'éléments coûteux et qui a une meilleure efficacité de dissipation de la chaleur produite par un dispositif de puissance. Le dispositif de puissance (101) et un dispositif de commande (102) sont placés dans des positions prédéterminées sur des cadres de montage respectifs (103a, 103b). Une couche isolante (105) de résine époxy ou autre est formée sur une surface principale d'un radiateur (104), et une couche de motif de circuit (106) sur une surface principale de la couche isolante (105) se conforme à un motif de circuit prédéterminé. Les cadres de montage (103a, 103b) sont disposés sur la couche de motif de circuit (106). The invention consists of a semiconductor device which uses transfer molding to simplify a step of coating in a resin, which reduces the manufacturing cost by not using expensive elements and which has a better dissipation efficiency. the heat produced by a power device. The power device (101) and a control device (102) are placed in predetermined positions on respective mounting frames (103a, 103b). An insulating layer (105) of epoxy resin or the like is formed on a main surface of a radiator (104), and a circuit pattern layer (106) on a main surface of the insulating layer (105) conforms to a predetermined circuit pattern. The mounting frames (103a, 103b) are disposed on the circuit pattern layer (106).

ELECTRONIC DEVICE FOR BUS WIRING SYSTEM

WIRING SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE USING SUCH A SUBSTRATE

L'INVENTION CONCERNE UN SUBSTRAT DE CABLAGE, UN PROCEDE DE FABRICATION DE CE SUBSTRAT ET UN DISPOSITIF A SEMI-CONDUCTEURS UTILISANT UN TEL SUBSTRAT. UN DISPOSITIF A SEMI-CONDUCTEURS EST CONSTITUE PAR UNE STRUCTURE DE SUBSTRAT4 FORMEE D'UNE PLAQUE FRITTEE FORMEE A CHAUD ET TRAVERSEE PAR DES CONDUCTEURS2 ET COMPORTE SUR AU MOINS L'UNE DE SES FACES PRINCIPALES UN CABLAGE5 AUQUEL EST FIXEE UNE PASTILLE SEMI-CONDUCTRICE12 ET QUI EST CONSTITUEE PAR DES COUCHES CONDUCTRICES6, 7, 8 SEPAREES PARTIELLEMENT PAR DES COUCHES ISOLANTES9, 10. APPLICATION NOTAMMENT AUX DISPOSITIFS A SEMI-CONDUCTEUR A HAUTE DENSITE D'INTEGRATION. THE INVENTION RELATES TO A WIRING SUBSTRATE, A PROCESS FOR MANUFACTURING THIS SUBSTRATE AND A SEMICONDUCTOR DEVICE USING SUCH A SUBSTRATE. A SEMICONDUCTOR DEVICE IS CONSTITUTED BY A SUBSTRUCTURE4 STRUCTURE FORMED BY A HOT-SHAPED SINTERED PLATE AND CROSSED BY CONDUCTORS2 AND INCLUDES ON AT LEAST ONE OF ITS MAIN FACES A WIRING5 TO WHICH IS FIXED12 A SEMI-PIPELINE WHICH IS CONSTITUTED BY CONDUCTIVE LAYERS6, 7, 8 PARTIALLY SEPARATED BY INSULATING LAYERS9, 10. APPLICATION ESPECIALLY TO SEMICONDUCTOR DEVICES WITH HIGH INTEGRATION DENSITY.

Semiconductor device for e.g. credit card, has passivation edge protection covering edge part on chip surface, where edge part is not occupied by integrated circuit and extends between integrated circuit and outer edge of chip

The device has a semiconductor chip (1) including an integrated circuit (1a) that is electrically connected to a contact unit (3) and a passivation layer (4) that covers the integrated circuit and through which the contact unit passes. A passivation edge protection (5) covers an edge part (6) on a chip surface. The edge part is not occupied by the integrated circuit and extends between the integrated circuit and an outer edge of the chip. An independent claim is also included for a method for producing a semiconductor device.

PROCESS FOR PROVIDING CONDUCTIVE PATHS ON THE SURFACE OF SEMICONDUCTOR ELEMENTS

Procédé pour disposer des chemins conducteurs à la surface d'un élément semi-conducteur; les chemins conducteurs (2) relient les zones de branchement (1) en forme de polygones. Les polygones sont composés de différents points marginaux. Pour ces points marginaux on détermine si la jonction se fait par un chemin conducteur parallèle au système de coordonnées ou dirigé en diagonale. D'autres points marginaux peuvent avoir l'état " branchement impossible ". Method for arranging conductive paths on the surface of a semiconductor element; the conductive paths (2) connect the branching areas (1) in the form of polygons. Polygons are made up of different marginal points. For these marginal points it is determined whether the junction is made by a conductive path parallel to the coordinate system or directed diagonally. Other marginal points may have the state "connection impossible".

Semiconductor device and its manufacturing method

A method of manufacturing a thin, small-sized, inexpensive, non-leaded, resin-sealed type semiconductor device is disclosed. A flexible tape having plural terminals peelably through a first adhesive in a product forming portion formed on a main surface of the tape is provided, a semiconductor element is fixed to the main surface of the tape peelably through a second adhesive, electrodes formed on the semiconductor element and the terminals are connected together through conductive wires, an insulating resin layer is formed in an area including the semiconductor element and the wires on the main surface of the tape to cover the semiconductor element and the wires, and the tape on a back surface of the insulating resin layer is peeled, allowing the terminals to be exposed to the back surface of the insulating resin layer. Exposed surfaces of the terminals are each formed by a gold layer. The terminals each comprise a main metal layer of copper foil and one or plural auxiliary metal layers formed on each of a main surface and a back surface of the main metal layer. The auxiliary metal layer(s) on the main surface of the main metal layer is (are) formed using a material which affords a rough surface, thereby roughening the main surface side of each terminal.

Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Method for low temperature bonding and bonded structure

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity (2). VSE may use reactive ion etching or wet etching to slighthly etch the surfaces being bonded (3). The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces (4).

Manufacturing method of semiconductor device

半導体装置の製造方法は、半導体素子(21A)が搭載される支持基板(51)上に接着剤(52)を配設する工程と、一方の主面に外部接続用端子(24)が配設された半導体素子(21A)の他方の主面に、前記接着剤(52)の流動を阻止する部材(33)を配設する工程と、前記半導体素子(21A)を、前記部材(33)を介して加圧し前記接着剤(52)が配設された前記支持基板(51)上に搭載する工程と、を含むことを特徴とする。 The semiconductor device manufacturing method includes a step of disposing an adhesive (52) on a support substrate (51) on which a semiconductor element (21A) is mounted, and an external connection terminal (24) disposed on one main surface. A step of disposing a member (33) for preventing the flow of the adhesive (52) on the other main surface of the semiconductor element (21A), and the semiconductor element (21A) and the member (33). And mounting on the support substrate (51) on which the adhesive (52) is disposed.

High performance system-on-chip using post passivation process

An integrated circuit chip comprising: - a silicon substrate; - a first dielectric layer over said silicon substrate; - a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated gold; - a second dielectric layer between said first and second metal layers; - a separating layer over said metallization structure and over said first and second dielectric layers, wherein said separating layer comprises a nitride layer; and - a third metal layer over said separating layer, wherein said third metal layer comprises at least a portion, vertically over said separating layer, of an inductor, wherein said third metal layer comprises electroplated gold.

Electrically conductive composite of a component and a carrier plate

Elektrisch leitfähiger Verbund aus einem Bauelement (10) und einer Trägerplatte (25), wobei das Bauelement umfasst: einen integrierten Schaltkreis (12), einen Gehäusekörper (14), eine Verdrahtungsanordnung (16), die den integrierten Schaltkreis und den Gehäusekörper überlappt und die eine Vielzahl von Leitstrukturen enthält, eine Vielzahl von Kontaktvorrichtungen (18 bis 24) an der Verdrahtungsanordnung (16), wobei die Verdrahtungsanordnung (16) eine Dicke kleiner als 50 Mikrometer hat, wobei äußere Kontaktvorrichtungen (22, 24) näher am Rand des Bauelements (10) liegen als innere Kontaktvorrichtungen (18, 20), wobei zwischen den äußeren Kontaktvorrichtungen (22, 24) und den inneren Kontaktvorrichtungen (18, 20) ein Zwischengebiet (31) liegt, das frei von Kontaktvorrichtungen ist, und wobei das Zwischengebiet (31) zwischen äußeren Kontaktvorrichtungen (22, 24) und inneren Kontaktvorrichtungen (18, 20) einen Abstand festlegt, der größer ist, als der Abstand zwischen einander benachbarten äußeren Kontaktvorrichtungen (22, 24) oder inneren Kontaktvorrichtungen (22, 24), wobei die Abstände von Mittelpunkt zu Mittelpunkt der Kontaktvorrichtungen (18, 20) definiert sind, und wobei das Zwischengebiet (31) mit dem Gehäusekörper (14) und mit dem Schaltkreis (12) überlappt, wobei die Überlappung jeweils größer als 500 Mikrometer ist, und wobei der thermische Ausdehnungskoeffizient des Gehäusekörpers (14) im Bereich von +50 Prozent bis –50 Prozent des thermischen Ausdehnungskoeffizienten der Trägerplatte (25) liegt, wobei die Differenz des thermischen Ausdehnungskoeffizienten des Schaltkreises (12) und des thermischen Ausdehnungskoeffizienten der Trägerplatte (25) auf der einen Seite und die Differenz des thermischen Ausdehnungskoeffizienten des Gehäusekörpers (14) und des thermischen Ausdehnungskoeffizienten der Trägerplatte (25) auf der anderen Seite betragsmäßig gleich sind oder um weniger als 20 Prozent oder um weniger als 10 Prozent voneinander abweichen. An electrically ...

Photosensitive adhesive composition, and film adhesive, adhesive sheet, adhesive pattern, semiconductor wafer with adhesive layer and semiconductor device using the photosensitive adhesive composition

There is provided a photosensitive adhesive composition having a lowest melt viscosity at 20°C to 200°C after pattern formation of 30,000 Pa·s or lower.

Bonding pad and support structure and method for their fabrication

A copper bonding pad is directly supported by a copper via pad structure, the copper via pad structure having substantially the same geometry and dimensions as the copper bonding pad. The combination of the copper bonding pad and the copper via pad structure results in an increase in effective thickness of the copper bonding pad. Due to this effective increase in the bonding pad thickness, the bonding pad is more tolerant to the potential dishing problem caused by the CMP process. Additional metal pad structures and via pad structures are used below the bonding pad. The additional metal pad structures and via pad structures comprise alternating segments of interconnect metal and dielectric fillers, and alternating segments of via metal and dielectric fillers, respectively. The alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers prevent or reduce the potential dishing problem that otherwise exists in damascene and CMP processing. The alternating segments of interconnect metal and dielectric fillers and the alternating segments of via metal and dielectric fillers are arranged such that there are a number of columns of solid metal support under the bonding pad. The columns of solid metal support significantly improve the poor mechanical support otherwise provided by the low dielectric constant materials that are presently used in fabrication of modern copper integrated circuits. The columns of solid metal support also improve thermal conductivity of the bonding pad.

Method for soldering a semiconductor substrate onto a carrier board

Low fabrication cost, high performance, high reliability chip scale package

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Method for low temperature bonding and bonded structure

Support with solder ball elements and a method for populating substrates with solder balls

A support with solder ball elements for loading substrates with ball contacts is disclosed. One embodiment provides a system for loading substrates with ball contacts and a method for loading substrates with ball contacts. The support has a layer of adhesive applied on one side, the layer of adhesive losing its adhesive force to the greatest extent when irradiated. The support has solder ball elements, which are arranged closely packed in rows and columns on the layer of adhesive in a prescribed pitch for a semiconductor chip or a semiconductor component.

SEMICONDUCTOR DEVICE (SEMICONDUCTOR MODULE)

Method and apparatus for fabricating self-assembling microstructures

本发明提供一种通过流体输送把微结构装配到基片上的方法和装置。自对准入凹槽区内的定形块微结构位于基片上，俾使微结构与基片变成为一个整体。改进的方法包括把定形块转移到流体中心制成浆体的步骤。然后把该浆体在其上具有凹槽区的上表面上均匀地分配或者循环。微结构通过形状和流体在基片的表面上滚动、自对准并齿合于凹槽区内。

Microminiature electrical component having integral indexing means

Metal duplex method

Methods and articles are disclosed. The methods are directed to depositing nickel duplex layers on substrates to inhibit tin and tin alloy surface oxidation and improve solderability of the substrates.

Curing liquid resin encapsulants of microelectronics components with microwave energy

Patent FR1486855A

Non-conductive and self-leveling leadframe clamp insert for wirebonding integrated circuits

A leadframe clamping apparatus includes a resilient polymeric membrane which permits self-leveling compensation of a variably movable clamp insert for variations in leadframe thickness. The clamp insert is formed of a polymer such as polyimide to provide further compensation for leadframe variations.