ПОЛУПРОВОДНИКОВЫЙ МОДУЛЬ И СПОСОБ ИЗГОТОВЛЕНИЯ ПОЛУПРОВОДНИКОВОГО МОДУЛЯ

Изобретение относится к силовой полупроводниковой технике. Сущность изобретения: полупроводниковый модуль содержит базовый элемент, изоляционный элемент с двухсторонним металлизированным покрытием, расположенный с помощью первого из обоих металлизированных покрытий на базовом элементе, и по меньшей мере один полупроводниковый элемент, расположенный на другом из обоих металлизированных покрытий. На краевом участке изоляционного элемента расположен электроизоляционный слой, причем поверхность этого изоляционного слоя образует с поверхностью второго металлизированного покрытия общую плоскую поверхность. Предложен также способ изготовления полупроводникового модуля. Техническим результатом изобретения является создание полупроводникового модуля, характеризующегося повышенной диэлектрической прочностью и одновременно простотой изготовления. 2 н. и 8 з.п. ф-лы, 5 ил.

СИЛОВОЙ ПОЛУПРОВОДНИКОВЫЙ МОДУЛЬ

... 1. Силовой полупроводниковый модуль, содержащий корпус модуля, включающий электропроводную пластину (2) крышки, и электропроводную пластину (9) основания, расположенную, по существу, параллельно пластине крышки, а также изолирующую стенку (3) корпуса, расположенную между пластиной крышки и пластиной основания, силовую полупроводниковую схему (1), расположенную в корпусе модуля и содержащую, по меньшей мере, два силовых вывода, один из которых электрически соединен с пластиной крышки и второй электрически соединен с пластиной основания, и по меньшей мере, два вывода (5, 52; 6, 61) силовой полупроводниковой схемы выведены из корпуса модуля, причем первый из, по меньшей мере, двух выводов (5, 52) выполнен с возможностью соединения с пластиной (2) крышки, отличающийся тем, что печатная плата (4), сформированная, по существу, плоской и, по меньшей мере, из двух слоев, выступает из корпуса модуля, причем два вывода печатной платы (4) сформированы как проводники (5, 6), расположенные, по существу ...

Halbleiterbauelement

Modular aufgebautes Leistungshalbleitermodul

Die Erfindung beschreibt ein modular aufgebautes Leistungshalbleitermodul (1) zur Montage auf einem Kühlkörper. Dieses Modul besteht aus einer Mehrzahl von Teilmodulen (10), welche ihrerseits aus einer Grundplatte (20) sowie einem rahmenartigen Gehäuse (30) und Anschlusselementen (40) für Last- (42) und Hilfsanschlüsse (44) bestehen. Die einzelnen Teilmodule werden mittels eines die Teilmodule gegeneinander fixierenden Deckels (70) und/oder mittels die einzelnen Teilmodule fixierender Verbindungen (34, 36) zu einem gesamten Leistungshalbleitermodul angeordnet.

Verfahren zur Herstellung einer Harzvergossenen elektronischen Anordnung

Verfahren zur Herstellung einer Harzvergossenen elektronischen Anordnung

Methode zur Verminderung der gegenseitigen Induktanz zwischen Verbindungsdrähten einer Hochfrequenzverstärkerschaltung

Halbleitervorrichtung zur Detektion oder Emission von Magnetfeldlinien oder Licht

Ein Schaltkreisgehäuse, ein elektronisches Schaltkreisgehäuse und Verfahren zum Verkapseln eines elektronischen Schaltkreises

Ein Schaltkreisgehäuse wird bereitgestellt, das Schaltkreisgehäuse aufweisend: einen elektronischen Schaltkreis; einen Metallblock neben dem elektronischen Schaltkreis; eine erste Metallschichtstruktur elektrisch kontaktiert mit mindestens einem ersten Kontakt auf einer ersten Seite des elektronischen Schaltkreises; eine zweite Metallschichtstruktur elektrisch kontaktiert mit mindestens einem zweiten Kontakt auf einer zweiten Seite des elektronischen Schaltkreises, wobei die zweite Seite gegenüberliegend der ersten Seite ist; wobei der Metallblock elektrisch kontaktiert ist mit der ersten Metallschichtstruktur und der zweiten Metallschichtstruktur mittels eines elektrisch leitfähigen Mediums; und wobei das elektrisch leitfähige Medium ein Material verschieden von dem Material der ersten und der zweiten Metallschichtstruktur oder eine Materialstruktur verschieden von dem Material der ersten und der zweiten Metallschichtstruktur aufweist.

Chipgehäuse und Verfahren zum Herstellen eines Chipgehäuses

Ein Verfahren zum Herstellen eines Chipgehäuses wird bereitgestellt. Das Verfahren aufweisend: Halten eines Trägers (402), aufweisend eine Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n); Bilden einer Separation zwischen der Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n) mittels Entfernens eines oder mehr Bereiche (422) des Trägers (402) von dem Träger (402) zwischen der Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n); Bilden eines Verkapselungsmaterials (434) in dem einen oder den mehreren entfernten Bereichen (428) zwischen der Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n Vereinzeln der Dies (4041, 4042, 4043, ..., 404n-1, 404n) durch das Verkapselungsmaterial (434).

Elektronikbauelement und Verfahren zum Herstellen eines Elektronikbauelements

Ein Halbleiterbauelement enthält einen elektrisch leitenden Träger und einen über dem Träger angeordneten Halbleiterchip. Das Halbleiterbauelement enthält auch eine zwischen dem Träger und dem Halbleiterchip bereitgestellte poröse Diffusionslotschicht.

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

Method for manufacturing DCB substrate for e.g. power semiconductor component in power converter, involves electroplating metal film on metallization layer and around cover so as to form pocket at desired position of power component

The method involves providing an electrically non-conductive insulating material body (1). A structured electrically conductive metallization layer (2a) is applied on a side (15a) of the body. An electrically non-conductive cover (3) is applied on the metallization layer at a desired position of a power semiconductor component. A metal film is electroplated on the metallization layer and around the cover so as to form a pocket at a desired position of the semiconductor component. The cover is removed. Independent claims are also included for the following: (1) a substrate for a power semiconductor component (2) a power semiconductor module.

Semiconductor module, has bonding wire bonded at load terminal and connected with upper contact piece, and explosion protection unit arranged between load terminals and upper contact piece and embedded in bonding wire at specific length

The module (100) has an electrically conductive lower contact piece (31) and an electrically conductive upper contact piece (32) spaced in a vertical direction (v). Multiple semiconductor chips comprise load terminals. One of the load terminals is electrical conductively connected with the lower contact piece. A bonding wire (4) is bonded at the load terminal and connected with the upper contact piece. An explosion protection unit is arranged between the load terminals and the upper contact piece and embedded in the bonding wire over 80% or 90% of length. The semiconductor chips are designed as unipolar and bipolar transistors such as IGBTs and MOSFETs. The bonding wire is designed as a flat small strip.

Anordnung mit drei Halbleiterchips und Herstellung einer solchen Anordnung

Anordnung, umfassend:einen ersten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst;einen zweiten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst, wobei der zweite Halbleiterchip über dem ersten Halbleiterchip platziert ist und die erste Seite des ersten Halbleiterchips der ersten Seite des zweiten Halbleiterchips zugewandt ist; genau eine Schicht aus einem elektrisch leitfähigen Material, die zwischen dem ersten Halbleiterchip und dem zweiten Halbleiterchip angeordnet ist, wobei die genau eine Schicht aus einem elektrisch leitfähigen Material die erste Kontaktstelle des ersten Halbleiterchips elektrisch mit der ersten Kontaktstelle des zweiten Halbleiterchips koppelt;eine Passivierungsschicht, die einen Teil der ersten Seite des ersten Halbleiterchips außerhalb der ersten Kontaktstelle überdeckt; undeinen auf der Passivierungsschicht angebrachten dritten Halbleiterchip,wobei der erste und der zweite Halbleiterchip jeweils Leistungs-Halbleiterchips ...

Leistungshalbleiteranordnung, geeignet zur Automation der Herstellung

HALBLEITERANORDNUNG UND VERFAHREN ZU IHRER HERSTELLUNG

Kunststoffzusammensetzung

Es wird eine Kunststoffzusammensetzung zum Herstellen eines gehärteten Kunststoffmaterials zur Verfügung gestellt, das eine verbesserte Wärmefestigkeit und eine höhere Glasübergangstemperatur zeigt. Die Kunststoffzusammensetzung der vorliegenden Erfindung enthält Folgendes: einen Kunststoff, der aus a) einem hitzehärtbaren Kunststoff und einem Härter oder b) einem thermoplastischen Kunststoff gewählt ist; und einen anorganischen Füller mit einem mittleren Teilchendurchmesser von 1000 nm oder weniger.

ELEKTRONISCHE INTEGRIERTE SCHALTUNG MIT MINDESTENS EINEM ELEKTRONISCHEN BAUELEMENT

MIKROWELLEN-/MILLIMETERWELLEN-SCHALTUNGSSTRUKTUR MIT EINZELN MONTIERTEN ELEMENTEN VOM FLIPCHIPTYP UND HERSTELLUNGSVERFAHREN DAFÜR

Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung

Leistungshalbleiterspannstapel

Leistungshalbleiterspannstapel mit einer Vielzahl an Leistungshalbleiterbauelementen (1), die längs der Stapelrichtung (X) in Reihe angeordnet sind, mit einer ersten und zweiten Stirnplatte (2, 3), wobei die Reihe der Leistungshalbleiterbauelemente (1) zwischen der ersten und zweiten Stirnplatte (2, 3) angeordnet ist und die erste und zweite Stirnplatte (2, 3) mit einer Spannkraft (F) beaufschlagbar ist, um die Reihe der Leistungshalbleiterbauelemente (1) zwischen der ersten und zweiten Stirnplatte (2, 3) zu verspannen, dadurch gekennzeichnet, dass zur Einstellung der Spannkraft (F) eine Spannkraftmesseinrichtung (4) zwischen der ersten Stirnplatte (2) und der Reihe der Leistungshalbleiterbauelemente (1) angeordnet ist.

Halbleitervorrichtung

Mehrphasige rotierende elektrische Wechselstrommaschine

Energieumwandlungseinheit und Modul für ihren Aufbau.

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

Baugruppe sowie Herstellung einer Baugruppe

Die Erfindung betrifft eine Baugruppe (1) mit einem Substrat (5) und mindestens einem durch Sintern mit einem Sintermittel (8), insbesondere Sinterpaste, daran befestigten Bauteil (3). Es ist vorgesehen, dass das Sintermittel (8) in einer das Bauteil (3) zumindest bereichsweise aufnehmenden Vertiefung (7) des Substrats (5) angeordnet ist. Weiter betrifft die Erfindung ein Verfahren zur Herstellung einer Baugruppe mit einem Substrat und mindestens einem durch Sintern mit einem Sintermittel, insbesondere Sinterpaste, daran befestigten Bauteil. Es ist vorgesehen, dass das Sintermittel in eine das Bauteil zumindest bereichsweise aufnehmende Vertiefung des Substrats eingebracht wird.

Halbleitervorrichtung mit Wärmeabstrahlplatte und Anheftteil

Eine Halbleitervorrichtung mit: einem Wärmeerzeugungselement (10), das durch einen IGBT bereitgestellt wird; einem Anheftteil (50); ersten und zweiten Wärmeabstrahlplatten (20, 30), welche auf ersten und zweiten Seiten (12, 13) des Wärmeerzeugungselementes (10) entsprechend über das Anheftteil (50) angeordnet sind; einem Wärmeabstrahlblock (40), der zwischen der ersten Wärmeabstrahlplatte (30) und dem Wärmeerzeugungselement (10) über das Anheftteil (50) angeordnet ist; und einem Kunstharzverguss (60), der praktisch die gesamte Vorrichtung eingießt, wobei die ersten und zweiten Wärmeabstrahlplatten (20, 30) in der Lage sind, von dem Wärmeerzeugungselement (10) erzeugte Wärme abzustrahlen; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der ersten Wärmeabstrahlplatte (30) über das Anheftteil (50) und den Wärmeabstrahlblock (40) verbunden ist; das Wärmeerzeugungselement (10) elektrisch und thermisch mit der zweiten Wärmeabstrahlplatte (20) über das Anheftteil (50) verbunden ist ...

Halbleiterchip, Halbleiterbauteil und Verfahren zu deren Herstellung

Halbleiterchip (1) mit einer haftvermittlungsschichtfreien Dreischichtmetallisierung (2) bestehend aus einer Aluminiumschicht (4), die direkt auf dem Halbleiterchip (1) aufgebracht ist, einer Diffusionssperrschicht (5), die direkt auf der Aluminiumschicht (4) aufgebracht ist, einer Lotschicht (6), die direkt auf die Diffusionssperrschicht (5) aufgebracht ist, wobei, die Diffusionssperrschicht (5) Ti, Ni, Pt oder Cr ist, und die Lotschicht (6) eine Diffusionslotschicht ist, die AuSn, AgSn oder CuSn aufweist, und wobei der Halbleiterchip (1) eine aktive Oberseite (16) und eine passive Rückseite (3) aufweist, und wobei alle drei Schichten in einer Prozessabfolge auf der passiven Rückseite (3) aufgesputtert sind.

Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben

Halbleiterbauelement mit Verbindungselementen (6) zur Herstellung einer Verbindung zwischen einem Halbleiterchip (7) aus einem Halbleiterwafer (8) mit diskreten Halbleiterbauelementen (1 bis 5) und einem übergeordneten Schaltungsträger, wobei das Halbleiterbauelement (1 bis 5) eine koplanare Fläche (9) aus Oberseiten (10) der Verbindungselemente (6) und einer Kunststoffmasse (11) aufweist, und wobei das Verbindungselement (6) eine Mesastruktur (12) oder eine Pilzform (13) für eine Oberflächenmontage aufweist und ein Lotdepot in Form einer strukturierten bleifreien Kontaktbeschichtung (14) umfasst, wobei die Verbindungselemente (6) auf Kontaktflächen (15) der Halbleiterchips (7) angeordnet sind, die flächige Erstreckung der Verbindungselemente (6) den Kontaktflächen (15) des Halbleiterchips (7) entsprechen und alle Verbindungselemente (6) auf einer aktiven Oberseite des Halbleiterchips (7) angeordnet sind.

Halbleiterbauteil mit einem vertikalen Halbleiterbauelement und Verfahren zu dessen Herstellung

Ein Halbleiterbauteil (1; 25) weist ein vertikales Halbleiterbauelement (2), eine erste Metallisierung (8) und eine zweite Metallisierung (13) auf. Die zweite Metallisierung (13) weist eine einstückige Folie mit einem ersten Ende (14) mit einer ersten Kontaktfläche (17), einem Zwischenbereich (15) und einem zweiten Ende (16) mit einer zweiten Kontaktfläche (19) auf. Die erste Kontaktfläche (17) ist auf der Rückseite (6) des Halbleiterbauelements (2) angeordnet und die zweite Kontaktfläche (19) ist im Wesentlichen in der Ebene der Außenkontaktfläche (12) der ersten Metallisierung (8) angeordnet und sieht eine Außenkontaktfläche (12) vor. Die erste Kontaktfläche (17) und die zweite Kontaktfläche (19) sind auf gegenüberliegenden Oberflächen der Folie der zweiten Metallisierung (13) angeordnet.

Electronic power package for e.g. diode, has two non-planar insulating substrates connected in connection regions, so that mechanical separation between substrates is controlled by number, arrangement, design and material of regions

The package (100) has two non-planar insulating substrates (1, 2) with high thermal conductivity. Electronic components e.g. semiconductor power transistor chip (20) and diode chip (30), are attached on each of the substrates. The substrates are connected with each other in connection regions, so that a mechanical separation between the substrates is controlled by the number of connection regions, an arrangement of connection regions, and design and material of the connection regions. The mechanical separation supplies an axially directed net compression force into the electronic components.

Wechselstromgenerator

Die vorliegende Erfindung stellt einen Wechselstromgenerator mit einer kleinen Größe und einer hohen Zuverlässigkeit bereit, wobei der Wechselstromgenerator umfaßt: ein Schaltenergiemodul (1) mit einem Harzgehäuse (13), welches Schaltelemente (2), und einen Ansteuerschaltungsabschnitt (5), einen Glättungskondensator (7) zum Glätten eines Gleichstromausgangs, der an die Schaltelemente (2) geführt wird, einen Steuerschaltungsabschnitt (6) zum Ausgeben eines Steuersignals an den Ansteuerschaltungsabschnitt 5 und ein Kühlelement (24) aufnimmt; ein Keramikkondensator wird für den Glättungskondensator verwendet; eine Glättungskondensatorplatte (25) zum Anbringen des Glättungskondensators (7) ist zwischen einer Isolationsplatte, an der die Schaltelemente (2) angebracht sind und einer Ansteuerschaltungsplatte (18), an der der Ansteuerschaltungsabschnitt (5) angebracht ist, angeordnet; und die Glättungskondensatorplatte (25) dient auch als eine elektromagnetische Abschirmungsplatte zum Schützen ...

Elektronische Vorrichtung und Verfahren zu deren Fertigung

Eine elektronische Vorrichtung weist ein Leistungselement (30) auf einem ersten Substrat (10) und eine elektronische Komponente (40) auf einem zweiten Substrat (20) auf. Das erste und das zweite Substrat (10, 20) sind derart übereinander angeordnet, dass das Leistungselement (30) und die elektronische Komponente (40) zwischen dem ersten und dem zweiten Substrat (10, 20) angeordnet werden können. Ein erstes Ende eines ersten Drahtes (50) ist mit dem Leistungselement (30) verbunden. Ein zweites Ende des ersten Drahtes (50) ist mit dem ersten Substrat (10) verbunden. Ein mittlerer Abschnitt des ersten Drahtes (50) ragt in Richtung des zweiten Substrats (20). Ein erstes Ende eines zweiten Drahtes (60) ist mit dem Leistungselement (30) verbunden. Ein zweites Ende des Drahtes (60) erstreckt sich über eine Oberseite (51) des mittleren Abschnitts des ersten leitfähigen Elements (50) und ist mit dem zweiten Substrat (20) verbunden.

Verfahren zum Herstellen von strukturierten Sinterschichten und Halbleiterbauelement mit strukturierter Sinterschicht

Die Erfindung betrifft ein Verfahren zum Herstellestrukturiertes Aufbringens einer Vielzahl von Sinterelementen (22a, 22b, 22c) aus einem die Sinterschicht ausbildenden Ausgangsmaterial auf einer Kontaktfläche (21) einer Hauptoberfläche (11a) eines Substrats (11), des Anordnens eines mit dem Substrat zu verbindenden Chips auf den Sinterelementen (22a, 22b, 22c), und des Erhitzens und Komprimierens der Sinterelemente (22a, 22b, 22c) zum Herstellen einer das Substrat und den Chip verbindenden strukturierten Sinterschicht, welche sich innerhalb der Kontaktfläche (21) erstreckt, wobei die Flächenbelegungsdichte der Sinterelemente (22a, 22b, 22c) auf dem Substrat (11) in einem Mittelbereich (21a) der Kontaktfläche größer ist als die Flächenbelegungsdichte der Sinterelemente in einem Randbereich (21c) der Kontaktfläche, und wobei von jedem der Sinterelemente (22a, 22b, 22c) mindestens ein lateral zur Hauptoberfläche des Substrats verlaufender Durchgangskanal (23) zum Rand der Kontaktfläche (21 ...

Kondensatormodul und dieses verwendende Halbleitereinrichtung

Kondensatormodul (60; 60A; 60B; 60C; 60D; 60E; 60F; 60G), umfassend: zwei Keramikkondensatoren (61) mit je einer Hauptfläche, je einem Paar von Seitenflächen und externen Elektroden (67), die jeweils an einem Paar von Seitenflächen vorhanden sind, die in entgegengesetzte Richtungen weisen; Anschlussteile (68; 63a, 64a), die jeweils mit externen Elektroden (67) der Keramikkondensatoren (61) verbunden sind, wobei die Anschlussteile (68; 63a, 64a) elektrisch leitend und flexibel sind; einen Positivpolaritäts-Verbindungsleiter (63), der Anschlussteile (68; 63a) an jeweils einer Seite der Keramikkondensatoren (61) mit einem Positivpolaritäts-Leiter (41) verbindet, der extern vorgesehen ist; einen Negativpolaritäts-Verbindungsleiter (64), der Anschlussteile (68; 64a) an der jeweils anderen Seite der Keramikkondensatoren (61) mit einem Negativpolaritäts-Leiter (43) verbindet, der extern vorgesehen ist; und eine Leiterplatte (62), die mit dem Positivpolaritäts-Verbindungsleiter (63) sowie dem Negativpolaritäts-Verbindungsleiter ...

Leistungshalbleiterbauelement mit erhöhter Robustheit

Leistungshalbleiterbauelement mit erhöhter Robustheit, umfassend: - einen Halbleiterkörper (1) mit einer ersten Hauptoberfläche (7) auf einer Vorderseite des Halbleiterkörpers (1) und einer zweiten, entgegengesetzt zur ersten Hauptoberfläche (7) gelegenen Hauptoberfläche (11) auf einer Rückseite des Halbleiterkörpers (1), - einer auf der ersten Hauptoberfläche (7) angeordneten ersten Metallisierung (10), und - einer auf der zweiten Hauptoberfläche (11) angeordneten zweiten Metallisierung (12), - wobei der Halbleiterkörper (1) mit der ersten Metallisierung (10) an der ersten Hauptoberfläche (7) und mit der zweiten Metallisierung (12) an der zweiten Hauptoberfläche (11) elektrisch Kontaktiert wird, dadurch gekennzeichnet, dass - beide Metallisierungen (10, 12) als direkt auf der entsprechenden Hauptoberfläche (7, 11) des Halbleiterkörpers (1) aufgebrachte Schicht eine Kontaktschicht (14) aufweisen, die aus Aluminium besteht und eine Schichtdicke zwischen 1 und 5 nm hat.

Halbleiterschaltung

Leistungshalbleitervorrichtung und Verfahren zum Herstellen derselben

Leistungshalbleitervorrichtung mit:einem Isoliersubstrat (1);einem Schaltungsmuster (6), das an einer oberen Fläche des Isoliersubstrats (1) ausgebildet ist;einem Leistungshalbleiter (7), der an dem Schaltungsmuster (6) ausgebildet ist;einer Vielzahl an Elektrodenanschlüssen (8), die senkrecht zu dem Schaltungsmuster (6) oder dem Leistungshalbleiter (7) so ausgebildet sind, dass sie mit externen Anschlüssen verbindbar sind;einer integrierten Harzbuchse (10), in der eine Vielzahl von Buchsenteilen (9) integriert ist, wobei die vielen Buchsenteile (9) entsprechend an die vielen Elektrodenanschlüsse (8) von der oberen Seite der vielen Elektrodenanschlüsse (8) angebracht sind und an ihren beiden Enden Öffnungen haben; undeinem Dichtharz (16), das das Isoliersubstrat (1), das Schaltungsmuster (6), den Leistungshalbleiter (7), die Elektrodenanschlüsse (8), und die integrierte Harzbuchse (10) abdeckt; wobeidie Buchsenteile (9) der integrierten Harzbuchse (10) an die Elektrodenanschlüsse (8) so ...

Power semiconductor module

The module has a housing and a metal base carrying electrically and thermally insulating substrates with conducting tracks and six adjacent controllable power semiconductor switches (1-6), each attached to one track and electrically connected to it. Load current connections are connected to the housing wall. Bonding areas (35-43) on the underside of the substrate are connected to the switches via bonding wires. At least one additional conducting track (30-32) is provided for each two adjacent switches. Each additional track is connected via bonding wires to one of the bonding surfaces and/or to at least one of the adjacent switches and/or to the additional track of the adjacent two switches. There are at least six load current connections with six bonding surfaces. The conducting tracks of two adjacent switches can be directly connected via bonding wires.

Die-Struktur, Die-Anordnung und Verfahren zum Prozessieren eines Dies

Eine Die-Struktur weist einen Die und eine Metallisierungsschicht, die auf oder über der Vorderseite des Dies angeordnet ist, auf. Die Metallisierungsschicht weist Kupfer auf. Zumindest ein Teil der Metallisierungsschicht weist ein raues Oberflächenprofil auf. Der Teil mit dem rauen Oberflächenprofil weist einen Drahtbondbereich auf, an den eine Drahtbondstruktur gebondet werden soll.

Leistungshalbleitereinrichtung und Verfahren zur Herstellung einer Leistungshalbleitereinrichtung

Die Erfindung betrifft eine Leistungshalbleitereinrichtung mit einem Leistungshalbleitermodul und einem Kühlkörper, wobei der Kühlkörper ein erstes Kühlgehäusebauteil, das eine durch das erste Kühlgehäusebauteil hindurchgehende Ausnehmung aufweist und ein zweites Kühlgehäusebauteil aufweist, wobei die Kühlplatte in der Ausnehmung angeordnet ist, wobei das erste und das zweite Kühlgehäusebauteil eine derartige Form aufweisen und derartig zueinander angeordnet sind, dass sich ein Hohlraum an der den Leistungshalbleiterbauelementen abgewandten Seite der Kühlplatte ausbildet, wobei die Kühlplatte mittels einer um die Kühlplatte umlaufenden ersten Schweißnaht mit dem ersten Kühlgehäusebauteil verbunden ist, wobei die erste Schweißnaht die Kühlplatte gegen das erste Kühlgehäusebauteil abdichtet, wobei das zweite Kühlgehäusebauteil mit dem ersten Kühlgehäusebauteil verbunden ist, wobei die erste Schweißnaht ausschließlich hohlraumseitig angeordnet ist und solchermaßen nicht vollständig von einer ...

Halbleitereinheit

Eine Halbleitereinheit umfasst eine Basis, die eine Oberfläche aufweist, auf der eine erste Isolationsschicht angeordnet ist, eine zweite Isolationsschicht, die von der ersten Isolationsschicht getrennt ist, um einen Bereich dazwischen auszubilden, und die parallel zu der Oberfläche der Basis angeordnet ist, auf der die erste Isolationsschicht angeordnet ist, eine einzelne leitfähige Schicht, die über der ersten Isolationsschicht und der zweiten Isolationsschicht angeordnet ist, und eine Halbleitervorrichtung, die mit der leitfähigen Schicht verbunden ist.

Verfahren und Vorrichtung zur Verarbeitung einer Mehrzahl von gehäusten elektronischen Chips, elektronischer Chip, umfassend eine Indikatorschicht, und Artikel, umfassend eine Mehrzahl derartiger elektronischer Chips

Verfahren zur Verarbeitung einer Mehrzahl von gehäusten elektronischen Chips (108, 306), die in einem gemeinsamen Substrat (102) miteinander verbunden sind, wobei das Verfahren umfasst:• Ätzen der elektronischen Chips (108, 306);• Detektieren von Informationen, welche eine wenigstens teilweise Entfernung einer Indikatorstruktur (110) nach einer Freilegung der Indikatorstruktur (110) anzeigen, die innerhalb wenigstens eines Teils der elektronischen Chips (108, 306) eingebettet ist und freigelegt wird, nachdem das Ätzen Chipmaterial über der Indikatorstruktur (110) entfernt hat; und• Einstellen der Verarbeitung bei Detektieren der Informationen, welche die wenigstens teilweise Entfernung der Indikatorstruktur (110) anzeigen, wobei das Detektieren von Informationen ein Analysieren eines flüchtigen Stoffs (1000) in einer Umgebung der elektronischen Chips (108, 306) umfasst, wobei der flüchtige Stoff (1000) von einem Ätzprodukt beeinflusst wird, das durch die Entfernung von Material der Indikatorstruktur ...

PCB-BASIERTER FENSTERRAHMEN FÜR HF-LEISTUNGSPACKAGE, Halbleiterpackage und Verfahren zum Herstellen eines Halbleiterpackage

Halbleiterpackage, umfassend:eine kupferhaltige Grundplatte (100), die einen Chip-Befestigungsbereich (102; 103) und einen peripheren Bereich (101; 104) aufweist;einen Transistorchip (110), der einen ersten Anschluss, der am Chip-Befestigungsbereich (102; 103) der Grundplatte (100) angebracht ist, und einen zweiten Anschluss und einen dritten Anschluss abgewandt von der Grundplatte (100) aufweist; undeinen Rahmen (120), der ein elektrisch isolierendes Glied (122) umfasst, das eine am peripheren Bereich (101; 104) der Grundplatte (100) angebrachte erste Seite (128), eine von der Grundplatte (100) abgewandte zweite Seite (126), eine erste kupferhaltige Metallisierung (138) an der ersten Seite (128) des isolierenden Glieds (122) und eine zweite kupferhaltige Metallisierung (130) an der zweiten Seite (126) des isolierenden Glieds (122) umfasst, wobei jede Rahmenmetallisierung eine Schicht von Ni (250) auf Kupfer und eine Schicht von Au (252) auf dem Ni (250) umfasst,wobei das isolierende Glied ...

Cooler for power semiconductor components and modules with individual cooling elements in two-dimensional matrix

The individual cooling elements (3) with structured surface are arranged in lines and columns, with each individual cooling element thermally coupled to the semiconductor module (1). The individual cooling element consists of two parts, a base body (31) facing the semiconductor module, and a finger- or plate-shaped ridge (32) on the base body.

ANORDNUNG EINES ELEKTRISCHEN BAUELEMENTS UND EINER ZWEI-PHASEN-KÜHLVORRICHTUNG UND VERFAHREN ZUM HERSTELLEN DER ANORDNUNG

Erdsymmetrische Halbleiterintegrierte Anordnung mit einer Parallelresonanzschaltung

Halbleitervorrichtung mit Metallplatten und Halbleiterchip

Es wird eine Halbleitervorrichtung geschaffen, die aufweist: einen Halbleiterchip (10); eine erste Metallplatte (20), die mittels einer ersten Lötschicht (51) auf einer Seite des Chips (10) angeordnet ist; eine zweite Metallplatte (40), die mittels einer zweiten Lötschicht (52) auf der anderen Seite des Chips (10) angeordnet ist; eine dritte Metallplatte (30), die mittels einer dritten Lötschicht (53) auf der zweiten Metallplatte (40) angeordnet ist; eine Stützeinrichtung (80, 85, 87) zum Halten eines Abstands zwischen dem Chip (10) und der ersten Metallplatte (20) und/oder zwischen dem Chip (10) und der zweiten Metallplatte (40); und eine Aufnahmeeinrichtung (90) zum Aufnehmen von überschüssigem Lot, wenn die dritte Lötschicht (53) das überschüssige Lot aufweist.

Halbleiterbauelement

The invention relates to a semiconductor component comprising two semiconductor bodies (3, 11), which are spatially separated from one another and electrically interconnected. According to the invention, a compensation MOS field effect transistor (23) is provided as the first semiconductor body (3), and a silicon carbide Schottky diode is provided as the second semiconductor body (11).

Leistungselektronik-Anlage

Die Leistungselektronik-Anlage gemäß der Erfindung enthält Luftkern-Trenntransformatoren (TU1 bis TU3), welche zwischen eine an Masse, das heißt an die Fahrzeugkarosserie gelegte Steuerschaltung (1) und einen unter einer hohen Vorspannung stehenden oberen Zweig (2) geschaltet sind, und Luftkern-Trenntransformatoren (TD1 bis TD3) zwischen der an Masse, das heißt an die Fahrzeugkarosserie gelegten Steuerschaltung (1) und einem unter einer hohen Vorspannung stehenden unteren Zweig (3), und jeder der Luftkern-Trenntransformatoren (TU1 bis TU3) und (TD1 bis TD3) enthält eine Primärwicklung und eine Sekundärwicklung, welche einander gegenüberliegen. Die Leistungselektronik-Anlage gemäß der Erfindung erleichtert es, dessen Beständigkeit gegen gefährliche Umgebungen zu verbessern, die alterungsbedingte Verschlechterung zu unterdrücken, die nachteiligen Auswirkungen der durch den äußeren magnetischen Fluss verursachten Störungen zu verringern und Signale zu senden und zu empfangen, während Niederspannungs ...

Halbleitervorrichtung

Eine Halbleitervorrichtung enthält ein Halbleitersubstrat (14), eine Oberflächenelektrode (16, 18), die auf dem Halbleitersubstrat gebildet ist, einen nicht aktiven Bereich (22, 24), der so gebildet ist, dass er die Oberflächenelektrode umgibt, und einen ID-Anzeigeabschnitt (20, 44), der aus einem anderen Material als die Oberflächenelektrode besteht und auf der Oberflächenelektrode gebildet ist, um eine ID anzuzeigen. Die Fläche des nicht aktiven Bereichs ist kleiner als die Fläche der Oberflächenelektrode.

Bond for forming connection between semiconductor component and metallic connector, has connector consisting of copper, where semiconductor component having metallization layer containing copper is formed at connector facing side

The bond (10) has a connector (15) consisting of copper, which is designed as laser beam welding connection. A semiconductor component (1) is formed at the connector facing side and provided with a metallization layer (6) consisting of copper. The thickness of metallization layer is 10-50mu m. The connector is formed as band shape.

Halbleitervorrichtung mit Extraktionselektrode und Verfahren

Halbleitervorrichtung, die umfasst: ein Leistungshalbleiterelement (1), das eine erste Hauptelektrode (1PE1), die auf einer vorderen Oberfläche ausgebildet ist, und eine zweite Hauptelektrode (1PE2) umfasst, die auf einer hinteren Oberfläche des Leistungshalbleiterelements (1) ausgebildet ist; eine Metallplatte (3), die mit der zweiten Hauptelektrode (1PE2) des Leistungshalbleiterelements (1) elektrisch verbunden ist; eine erste Verbindungselektrode (10A) und eine zweite Verbindungselektrode (10B), die auf der ersten Hauptelektrode (1PE1) einander gegenüberliegend getrennt ausgebildet sind; und eine Extraktionselektrode (4), die ein erstes Elektrodenverdrahtungsteil (5A), das so ausgebildet ist, dass es von einem Seitenabschnitt der Extraktionselektrode (4) nach unten verläuft, und ein zweites Elektrodenverdrahtungsteil (5B), das getrennt von dem ersten Elektrodenverdrahtungsteil (5A) so ausgebildet ist, dass es von dem anderen Seitenabschnitt der Extraktionselektrode (4), der dem einen ...

Überlastschutz für steuerbare Stromverbraucher

Der Grundgedanke der vorliegenden Erfindung besteht darin, eine Vorrichtung und ein Verfahren zur Absicherung eines steuerbaren Stromverbrauchers zu schaffen, bei der der Strom durch den Stromverbraucher erfasst wird und bei Überschreiten eines Schwellenstroms das Steuersignal derart verändert wird, dass der Strom durch den Stromverbraucher verändert wird. Dabei ist die Schaltung derart angelegt, dass der Stromverbraucher zur gleichen Zeit gegen Überhitzung geschützt wird, d. h. bei Erreichen einer Temperaturschwelle wird das Zündsignal derart verändert, dass der Strom durch den Stromverbraucher sinkt.

Leistungstransistor und Leistungshalbleiterbauteil

Die Erfindung betrifft einen Leistungstransistor und ein Leistungshalbleiterbauteil. Der vertikal leitende Leistungstransistor weist an seiner Vorderseite (11) eine Sourcezone (14) und einen Steuereingang (16) auf. Eine Durchführung für den Steuereingang weist eine Elektrode auf der Vorderseite (11) und eine Elektrode auf der Rückseite (12) auf, sodass der Steuereingang sowohl von der Vorderseite (11) als auch von der Rückseite (12) kontaktiert werden kann.

Halbleitervorrichtung

Halbleitervorrichtung mit einer Vielzahl von auf einem Substrat (4, 5) angeordneten Halbleiterelementen (6, 7), einem Gehäuse (2), dass die Vielzahl der Halbleiterelemente (6, 7) umgibt, einer Hauptstromelektrode (13), die elektrisch mit den Halbleiterelementen (6, 7) unter Verwendung eines Kontaktierungsdrahts verbunden ist und die mit einer bestimmten Höhe (h) über dem Substrat (4, 5) angeordnet ist, die größer als die Höhe der Halbleiterelemente (6, 7) ist, wobei jedes aus der Vielzahl der Halbleiterelemente (6, 7) und die Hauptstromelektrode (13) durch einen Drahtanschluss (14) elektrisch verbunden sind, die Hauptelektrode (13) mit einem Anschluss zum elektrisch Verbinden der Halbleitervorrichtung und einer Schaltung außerhalb der Halbleitervorrichtung versehen ist, und beide Enden der Hauptelektrode (13) durch das Gehäuse (2) derart gestützt werden, dass die Hauptelektrode (13) das Substrat von einem Ende zu einem gegenüberliegenden Ende des Substrats (4, 5) überbrückt und zumindest ...

Elektrisches oder elektronisches Verbundbauteil sowie Verfahren zum Herstellen eines elektrischen oder elektronischen Verbundbauteils

Die Erfindung betrifft ein elektrisches oder elektronisches Verbundbauteil (1), umfassend einen ersten Fügepartner (2) und mindestens einen zweiten Fügepartner (3). Erfindungsgemäß ist vorgesehen, dass zwischen dem ersten und dem zweiten Fügepartner (2, 3) ein offen poröses Sinterformteil (6, 7) aufgenommen ist, welches fest mit dem ersten und dem zweiten Fügepartner (2, 3) verbunden ist.

Halbleitervorrichtung mit Abstrahlungsbauteilen

Structure, electronic element module, heat exchanger, fuel rod, and fuel assembly

The present invention has a first member (2), a second member (3) opposite the first member (2), and a glass layer (4) provided between the first member (2) and the second member (3) and used to bond the first member (2) and the second member (3); the glass transition point of the glass layer (4) being lower than the temperature of the glass layer (4) when a structure (1) is being used. Ceramic particles (4b) and/or metallic particles (4c) are dispersed in the glass layer (4). In a temperature zone of the glass layer (4) that is lower than the glass transition point of the glass layer (4), the coefficient of thermal expansion of the glass layer (4) is a value between the coefficients of thermal expansion of the first member (2) and the second member (3). Therefore, the thermal strain in the inner section of the structure caused when the structure is used at a temperature higher than room temperature can be alleviated. The first member (2) is a film formed on top of the glass layer (4) and ...

ATTACHMENT OF CONDUCTORS TO SEMICONDUCTOR PELLETS

Backside dummy plugs for 3d integration

Electrically isolated power semiconductor package

Photovoltaic relay with past switching circuit

The gate capacitance of a Field effect transistor (24) used as a switch is rapidly charged via a diode (35) to turn the FET on, and is rapidly discharged to turn the FET off by a switching transistor (36) connected across the diode and the FET such that it becomes conductive only when the diode becomes reverse biased, thereby providing a discharge path for the gate capacitance. The circuit is used in a photovoltaic relay, the FET being turned on by a photovoltaic isolator (20) having a LED 21 energised by an input signal optically coupled to and dielectrically isolated from a series-connected stack of photo diodes connected to the switching FET, which may comprise a bilateral semiconductor FET (BOSFET). ...

Semiconductor device having aluminum interconnection

COMPLEX ELECTRONIC SYSTEM

... 1358935 Integrated circuit &c. memories and computing systems TEXAS INSTRUMENTS Inc 6 Jan 1972 [27 Jan 1971 (2) 13 May 1971] 660/72 Heading G4C A memory or computing system comprising a plurality of subsystems on a substrate includes at least one spare subsystem on the substrate, and each subsystem has an associated enabling means for selectively coupling that subsystem to conductors on the substrate whereby the required number of perfect subsystems are selected to form the complete system. In a computing system, spare sub-systems may be provided for each different type of subsystem. The description is mainly concerned with integrated circuit constuctions employing FET storage and gating circuits each enabling means being a set of gates for isolating the associated subsystem from the conductors, but reference is also made to charge transfer devices. Each memory subsystem may include, besides the storage array, the associated decode and drive systems, refresh generators and clock generators ...

THERMAL HEAD DEVICE

MICROWAVE OSCILLATOR DEVICES

Silicon transducer

Semiconductor integrated circuit devices

In a semiconductor integrated circuit device having a polyimide-type resin film 16 formed on a semiconductor substrate 1 and an aluminum wiring layer 17 formed on the surface of the polyimide-type resin film the wiring layer 17 contains between 0.1% to 10% by weight silicon to increase corrosion resistance. Alternatively nickel or boron may be used in place of silicon. ...

Power electronic package having two substrates with multiple semiconductor chips and electronic components

A semiconductor device and method of making

... 1,069,506. Semi-conductor devices. NORTH AMERICAN AVIATION Inc. Feb. 8, 1966, No. 5410/66. Heading H1K. A method of making a semi-conductor device in a thin film of monocrystalline semi-conductor material bonded to an insulating substrate comprises masking the surface of the film and diffusing impurity completely through at least two regions of the film to alter its conductivity. A thin film is defined as having a thickness of 50 Š to 3 Á. A plurality of insulated gate F.E.T.'s are produced by epitaxially growing a thin film of P-type silicon doped with boron on a sapphire substrate 20, polishing the surface of the film, oxide masking and etching to divide the film into a plurality of strips 21, bevelling the edges of the strips by mechanical polishing, Fig. 5 (not shown), covering strips 21 with a thermally grown layer of silicon dioxide, masking and etching this oxide layer to form a plurality of strips (25) extending transversely to strip 21, Fig. 4 (not shown), and diffusing boron into ...

High-frequency circuit

In a high-frequency circuit arrangement, passive parts of the circuit are realized in a semiconductor body in which active circuit elements of another semiconductor material are located in recesses in the semiconductor body. When the semi-conductor body is at least in part low-ohmic, a reference plane, for example, the ground plane, can extend very close to the elements of the circuit arrangement. Consequently, due to the shorter connections required, parasitic effects are considerably reduced. When only one active element is mounted and only connections for this element are formed on the semiconductor body, a very suitable support for mounting and measurement is obtained.

Structure, electronic element module, heat exchanger, fuel rod and fuel assembly

SEMICONDUCTOR MICROWAVE DEVICE OF THE KIND UTILIZING THE TRANSIT-TIME EFFECTS

... 1516945 Oscillators and amplifiers using negative resistance semi-conductor devices THOMSON CSF 25 March 1976 [28 March 1975] 12148/76 Heading H3T A transit time oscillator or amplifier comprises a transistor type semiconductor capable of oscillating at high frequency when a direct voltage is applied to across its collector and emitter and a transmission line connected to the base and collector electrodes of the semiconductor and having a short circuit termination which is adjustable along the line to neutralize the damping effect of the collector-base capacitance on the high frequency oscillations. In one embodiment, Fig. 4, the collector of the transistor is soldered to a microstrip base 41 and the base is connected to the transmission line 45 by a lead 150 and the microstrip circuit. The movable h.f. short circuit comprises a cylinder 46 in the line. The output is taken from the emitter via lead 160 and a further coaxial line 44. In a modification, Fig. 5 (not shown) the lines 44 and ...

POLYIMIDE-SILOXANE COPOLYMER PROTECTIVE COATING FOR SEMICONDUCTOR DEVICES

SIGNAL OR LIGHTING MECHANISM FOR A MOTOR VEHICLE, WITH ELECTRONICS OF HIGH INTEGRATION COMPLEXITY

ELECTRO-CHEMICAL SEPARATING OF SOLDERING BALLS WITH UNIFORM HEIGHT ON SEMICONDUCTOR SUBSTRATES

PLAKSTIKVERKAPSELTE SEMICONDUCTOR DEVICES WITH IMPROVED CORROSION RESISTANCE

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG

A method of manufacturing a semiconductor device having a back surface electrode, including: a step of preparing a semiconductor wafer having a front surface and a back surface; a thermal processing step of forming a first metal layer on the back surface of the semiconductor wafer and executing thermal processing, thereby creating an ohmic contact between the semiconductor wafer and the first metal layer; and a step of forming a second metal layer of Ni on the back surface of the semiconductor substrate after the thermal processing step.

MANUFACTURING PROCESS OF AN ARRANGEMENT WITH POWER SEMICONDUCTOR ELEMENTS, WHICH CONTAINS A STEP PRINTINGINTERNALLY

MODULAR DEVELOPING POWER SEMICONDUCTOR MODULE

SEMICONDUCTOR ACHIEVEMENT MODULE, WITH FLEXIBLE CIRCUIT CARRIER FRAMEWORK

DIELECTRIC MATERIAL of the SYSTEM (1X) BAO.XTIO2 IN PARTICULAR FOR USE IN a MICROWAVE DEVICE.

CASCADE INSTALLING OF TRANSISTORS JOINED IN PARALLEL REALIZES IN HYBRID INTEGRATED CIRCUIT TECHNOLOGY.

PROCEDURE FOR THE PRODUCTION OF AN ELECTRONIC CIRCUIT MODULE WITH HIGH DEVICE COMPLEXITY

GUARD FOR SEMICONDUCTOR CHIPS LOCATED ON A CIRCUIT SUBSTRATE WITH BOND WIRES

Circuit structure having a flip-mounted matrix of devices

DIGITAL AND RF SYSTEM AND METHOD THEREFOR

Electronic power circuit with heat dissipating radiator

Measuring back-side voltage of an integrated circuit

Method for fault correction in a power converter circuit arrangement

Method for constructing regenerative displacers

Method for constructing thermomechanical transducers

CIRCUIT BOARD, METHOD FOR MANUFACTURING SAME, AND HIGH-OUTPUT MODULE

A circuit board comprising a patterned first metal layer 14 formed on a ceramic substrate 11, a patterned second metal layer 16 formed on the first metal layer, and a third metal layer 17 formed covering the entire upper surface and side surfaces of the second metal layer and a part of the upper surface of the first metal layer, wherein portions of the first metal layer not covered by the third metal layer are reduced in width by etching. The circuit board has thick-film fine wiring patterns with high bonding strength between the wiring patterns and the substrate and high reliability and enables realization of high-output modules which are small in size and high in performance, by mounting at least one high-output semiconductor element thereon.

VOLTAGE LIMITING PROTECTION FOR HIGH FREQUENCY POWER DEVICE

An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

MATRIX CONVERTER FOR THE TRANSFORMATION OF ELECTRICAL ENERGY

Convertisseur matriciel pour la transformation d'énergie électrique entre au moins une source de tension (1), notamment un réseau d'alimentation, et au moins une source de courant (2), notamment une charge, ledit convertisseur comportant une matrice d'interrupteurs reliant lesdites sources de tension (1) audites sources de courant (2), caractérisé en ce que lesdits interrupteurs comportent chacun deux bornes disposées dans deux plans parallèles distincts et un substrat diamant photoconducteur interposé entre lesdites deux bornes de l'interrupteur, la commande de chaque interrupteur étant réalisée au moyen d'une source optique (7) venant irradier le substrat diamant (4) interposé entre les deux bornes.

CIRCUIT BOARD ASSEMBLY AND METHOD OF ATTACHING A CHIP TO A CIRCUIT BOARD

An antenna array (100) is assembled by direct attaching a flip chip transmit/receive (T/R) module (1) to an antenna circuit board (2). A fillet bond (6) is applied to the circuit board (2) and the flip chip T/R module (1) around at least a portion of the periphery of the flip chip T/R module (1).

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Semiconductor device

The semiconductor device has a unit stack body including a plurality of units stacked on one another. Each unit includes a power terminal constituted of a lead part and a connection part. The connection part is formed with a projection and a recess. When the units are stacked on one another, the projection of one unit is fitted to the recess of the adjacent unit, so that the power terminals of the respective unit are connected to one another.

Method for Reducing Chip Warpage

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Power semiconductor module and fabrication method

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Method for fabrication of a semiconductor device and structure

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Semiconductor device and method for producing such a device

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

High-voltage packaged device

Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described.

Semiconductor Device and Power Supply Unit Utilizing the Same

A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

Semiconductor device

A semiconductor device includes a first semiconductor chip 1 , a second semiconductor chip 4 , a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4 . A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Semiconductor package

A semiconductor package includes a radiator plate including a stress alleviation section, a resin sheet arranged on the radiator plate, a pair of bus bars joined to the radiator plate through the resin sheet at positions at which the stress alleviation section is interposed between the bus bars, and a semiconductor device joined to the pair of bus bars by being sandwiched between the bus bars, and energized from outside through the pair of bus bars.

Power Semiconductor Chip Package

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor module including a switch and non-central diode

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Semiconductor device

A semiconductor device, in which a control circuit board is mountable outside a sheath case and a power semiconductor element is placeable inside the sheath case, includes a metal step support, a shield plate and a metal ring. The support includes a base portion implanted in the sheath case, a connection portion which extends from an end of the base portion, and a step portion formed at a boundary between the base portion and the connection portion. The shield plate is disposed over the step portion such that the connection portion of the support pierces the shield plate. An end of the metal ring protrudes from an end of the connection portion over the shield plate. The semiconductor device is adapted such that the control circuit board is mounted over the protruded end of the metal ring and is fixed onto the connection portion by an engagement member.

Method and system for minimizing carrier stress of a semiconductor device

A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier.

Semiconductor die package including low stress configuration

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

Semiconductor device having plural insulated gate switching cells and method for designing the same

In a semiconductor device including a plurality of insulated gate switching cells each of which has a gate electrode, an emitter electrode that is commonly provided to cover the plurality of insulated gate switching cells, and a bonding wire connected to the emitter electrode, a gate driving voltage being applied to the gate electrode of each insulated gate switching cell so that emitter current flows through the emitter electrode, mutual conductance of each insulated gate switching cell is varied in accordance with the distance from the connection portion corresponding to the bonding position of the bonding wire so that the emitter current flowing through the emitter electrode is substantially equal among the plurality of insulated gate switching cells.

Atomic layer deposition encapsulation for power amplifiers in rf circuits

Power amplifiers and methods of coating a protective film of alumina (Al 2 O 3 ) on the power amplifiers are disclosed herein. The protective film is applied through an atomic layer deposition (ALD) process. The ALD process can deposit very thin layers of alumina on the surface of the power amplifier in a precisely controlled manner. Thus, the ALD process can form a uniform film that is substantially free of free of pin-holes and voids.

Semiconductor device

A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers. P-type partition region has impurity concentration distribution where concentration decreases from surface toward substrate side, n-type surface region disposed on parallel pn layers in peripheral region, p-type guard rings disposed separately from each other on n-type surface region, and field plate disposed on inner and outer circumferential sides of p-type guard rings, and electrically connected.

Base plate

The present disclosure relates to a base plate, for example, for a power module, including a matrix formed of metal, for example, aluminium, wherein at least two reinforcements are provided in the matrix next to each other, and wherein the reinforcements are spaced apart from each other.

Heater design for heat-trimmed thin film resistors

A heater design for post-process trimming of thin-film transistors is described. The heater incorporates low sheet-resistance material deposited in non-active connecting regions of the heater to reduce heat generation and power consumption in areas distant from active heating members of the heater. The heating members are proximal to a thin-film resistor. The resistance of the thin-film resistor can be trimmed permanently to a desired value by applying short current pulses to the heater. Optimization of a heater design is described. Trimming currents can be as low as 20 mA.

System comprising a semiconductor device and structure

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Radiofrequency amplifier

An integrated radiofrequency amplifier with an operational frequency includes first and second Doherty amplifiers each having a main device, and a peak device connected at respective inputs and outputs by respective phase shift elements configured to provide a 90 degree phase shift at the operational frequency. An input of the amplifier is connected to the input of the main device of the first Doherty amplifier, an output of the amplifier is connected to the outputs of the peak devices of the first and second Doherty amplifiers and the input of the peak device of the first Doherty amplifier is connected to the input of the main device of the second Doherty amplifier by a phase shift element providing a 90 degree phase shift at the operational frequency.

Semiconductor device with vias and flip-chip

Semiconductor devices comprising a flip-chip having passive circuits such as spiral inductors on the back side are disclosed. Provision is made for connection with the spiral inductors using vias and/or bondwires. Further aspects of the invention provide for methods of making such devices.

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

Semiconductor Element Control Device and In-Vehicle Electrical System

A semiconductor element control device that controls a semiconductor element that performs switching operation for converting DC power into AC power, or AC power into DC power, includes: a drive unit that outputs a drive signal for controlling the switching operation of the semiconductor element to a terminal of the semiconductor element; a short-circuit detection unit that detects short-circuit of the semiconductor element on the basis of the voltage at the terminal, and outputs a short-circuit detection signal; and a drive interruption unit that interrupts current flowing in the semiconductor element on the basis of the short-circuit detection signal output from the short-circuit detection unit.

Circuit device and method of manufacturing the same

Provided is a circuit device in which encapsulating resin to encapsulate a circuit board is optimized in shape, and a method of manufacturing the circuit device. A hybrid integrated circuit device, which is a circuit device according to the present invention includes a circuit board, a circuit element mounted on a top surface of the circuit board, and encapsulating resin encapsulating the circuit element, and coating the top surface, side surfaces, and a bottom surface of the circuit board. In addition, the encapsulating resin is partly recessed and thereby provided with recessed areas at two sides of the circuit board. The providing of the recessed areas reduces the amount of resin to be used, and prevents the hybrid integrated circuit device from being deformed by the cure shrinkage of the encapsulating resin.

Semiconductor device

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Trap Rich Layer for Semiconductor Devices

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Method of Manufacturing a Printable Composition of a Liquid or Gel Suspension of Diodes

An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of making a liquid or gel suspension of diodes comprises: adding a viscosity modifier to a plurality of diodes in a first solvent; and mixing the plurality of diodes, the first solvent and the viscosity modifier to form the liquid or gel suspension of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

Semiconductor package and method of fabricating the same

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

Rf identification device with near-field-coupled antenna

An embodiment of a RF identification device is formed by a tag and by a reader. The tag is formed by a processing circuit and a first antenna, which has the function both of transmitting and of receiving data. The reader is formed by a control circuit and by a second antenna, which has the function both of transmitting and of receiving data. The processing circuit is formed by a resonance capacitor, a modulator, a rectifier circuit, a charge-pump circuit and a detection circuit. The antenna of the tag and the processing circuit are integrated in a single structure in completely monolithic form. The first antenna has terminals connected to the input of the rectifier circuit, the output of which is connected to the charge-pump circuit. The charge-pump circuit has an output connected to the detection circuit.

Methods for manufacturing superjunction semiconductor device having a dielectric termination

A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.

Structures for improving current carrying capability of interconnects and methods of fabricating the same

Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

Method for manufacturing semiconductor device

A method of manufacturing a semiconductor device comprises: preparing a lead frame including a package external region and a package internal region, a burred surface being provided at a top end of a side of the lead frame, and a fracture surface being provided in the vicinity of the top end of the side; chamfering the top end of the side in the package external region; mounting a semiconductor element on the lead frame and sealing the semiconductor element with mold resin in the package internal region; and removing resin burr provided on the side of the lead frame in the package external region after the chamfering and the sealing.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

Vertical ballast technology for power hbt device

Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.

Power module

A reliable power module is realized, in which a good performance of radiating heat of the power semiconductor element is secured and it is hard for the heat of a power semiconductor element to be conducted to a driving element. A power module includes a power semiconductor element mounted on a lead frame, and a driving element mounted on the lead frame, and a heat radiating plate radiating heat which is generated by the power semiconductor element, and a resin holding the power semiconductor element, the driving element, and the heat radiating plate, wherein the heat radiating plate has a portion disposed at a side opposite to a surface of the lead frame where the power semiconductor element is mounted, a portion disposed between the power semiconductor element and the driving element, and a portion disposed below the power semiconductor element, as the portions being in a body.

Semiconductor apparatus and method for manufacturing the same

According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.

Electronic device and method for producing a device

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Multilayer resin sheet and method for producing the same, method for producing cured multilayer resin sheet, and highly thermally conductive resin sheet laminate and method for producing the same

A multilayer resin sheet is constituted by including a resin layer containing an epoxy resin having a mesogenic skeleton, a curing agent and an inorganic filler, and an insulating adhesive layer formed on at least either of the surfaces of the resin layer. A cured multilayer resin sheet originated from the multilayer resin sheet has high thermal conductivity, good insulation and adhesive strength, and, further, superior thermal shock resistance, and is suitable as an electric insulating material to be used for an electric or electronic device.

Methods of fabricating light emitting diode devices

An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor.

Heat conduction for chip stacks and 3-d circuits

A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Stacked Composite Device Including a Group III-V Transistor and a Group IV Diode

In one implementation, a stacked composite device comprises a group IV diode and a group III-V transistor stacked over the group IV diode. A cathode of the group IV diode is in contact with a source of the group III-V transistor, an anode of the group IV diode is coupled to a gate of the group III-V transistor to provide a composite anode on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite cathode on a top side of the stacked composite device.

Semiconductor device

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Apparatus and methods for electronic amplification

Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Semiconductor device

A semiconductor device includes: a main body chip; a circuit pattern on a front surface of the main body chip and including a first pad; a cap chip including a first recess in a front surface of the cap chip and a second recess in a back surface of the cap chip, the cap chip being joined to the main body chip with the first recess facing the circuit pattern; a second pad on a bottom surface of the first recess of the cap chip; a first metallic member inlaid in the second recess of the cap chip; a first through electrode electrically connecting the second pad to the first metallic member through the cap chip; and a bump electrically connecting the first pad to the second pad.

Scalable Construction for Lateral Semiconductor Components having High Current-Carrying Capacity

The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode ( 203 ), a plurality of source fields ( 201 ) and a plurality of drain fields ( 202 ). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field ( 206 ) and/or a drain contact field ( 207 ). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate. The method according to the invention for producing a transistor comprises the following steps: providing a substrate; forming a plurality of transistor cells on the substrate, each of which comprises a control electrode, a plurality of source fields and a plurality of drain fields; conductively connecting the control electrodes to each other; forming a source contact field and/or a drain contact field in each transistor cell; conductively connecting the source contact fields

Electronic module

An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 μm.

Semiconductor device

A semiconductor device includes a base plate having one main surface joined to an insulating substrate on which a semiconductor chip and the like are mounted and a transfer mold resin which is so provided as to cover the one main surface of the base plate, the insulating substrate, the semiconductor chip, and the like and expose the other main surface of the base plate. The coefficient of linear expansion of the base plate is lower than that of copper and the coefficient of linear expansion of the transfer mold resin is not higher than 16 ppm/° C. The transfer mold resin has such scooped shapes as to expose opposed short-side centers and the vicinity of the base plate, respectively. The base plate has mounting holes in portions exposed by the scooped shapes of the transfer mold resin.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Semiconductor module manufacturing method, semiconductor module, and manufacturing device

In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other.

Through wafer vias and method of making same

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Semiconductor device, adjustment method thereof and data processing system

A method includes preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip, data electrodes of the first and second memory chips being electrically connected and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip, accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time, accessing the second memory chip so that a data signal is outputted and appears on the side of the second main surface of the second memory chip in second access time, and setting output timing adjustment information into at least one of the first and second memory chips.

System and Method for Packaging of High-Voltage Semiconductor Devices

A method and an electronic device structure comprising at least one access lead to adapted to be connected to an electrical circuit; at least one substrate region; at least one semiconductor die positioned on the substrate; the at least one semiconductor die being operatively connected to the at least one access lead; a dielectric region extending below the at least one semiconductor die; the dielectric region being formed by creating a cavity in the at least one substrate region; whereby the dielectric region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown. The method of making an electronic device structure comprises providing at least one substrate region; providing at least one semiconductor die located on the at least one substrate region; removing a portion of the at least one substrate region to provide a dielectric region within the substrate extending below the at least one semiconductor die; whereby the dielectric region within the at least one substrate region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown.

Semiconductor device

A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

Power Module and Power Converter Containing Power Module

A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Paste and method for connecting electronic component to substrate

A paste may be used to connect at least one electronic component to at least one substrate through contact regions, wherein at least one of the contact regions contains a non-noble metal. The paste contains (a) metal particles, (b) at least one activator that bears at least two carboxylic acid units in the molecule, and (c) a dispersion medium. A method for connecting at least one electronic component to at least one substrate through the contact regions includes steps of providing a substrate having a first contact region and an electronic component having a second contact region; providing the above paste; generating a structure, wherein the first contact region of the substrate contacts the second contact region of the electronic component through the paste; and sintering the structure while producing a module including at least the substrate and the electronic component connected to each other through the sintered paste.

Power semiconductor module with wireless saw temperature sensor

A power semiconductor module includes a housing, a base plate disposed in the housing, a plurality of substrates mounted to the base plate, a plurality of power transistor die mounted to the substrates and a plurality of terminals mounted to the substrates and protruding through the housing. The terminals are in electrical connection with the power transistor die. The power semiconductor module further includes a wireless surface acoustic wave (SAW) temperature sensor disposed in the housing of the power semiconductor module.

Power semiconductor arrangement and method for producing a power semiconductor arrangement

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Novel semiconductor device and structure

A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

Through substrate via structures and methods of forming the same

The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill.

Device

A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit.

Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method

A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

Semiconductor package and method for manufacturing the same and semiconductor package module having the same

Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.

Method for separating a plurality of dies and a processing device for separating a plurality of dies

A method for separating a plurality of dies is provided. The method may include: selectively removing one or more portions from a carrier including a plurality of dies, for separating the plurality of dies along the selectively removed one or more portions, wherein the one or more portions are located between the dies; and subsequently forming over a back side of the dies, at least one metallization layer for packaging the dies

Power Module with Current Routing

According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

Connecting material, method for manufacturing connecting material and semiconductor device

In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material.

Power Converter Device

A power converter device includes first through third semiconductor modules provided for phases of a three-phase inverter circuit, and incorporating upper and lower arms series circuit, and a flow path forming cabinet in a rectangular prism shape having an electric equipment containing space and a coolant flow path formed to surround the electric equipment containing space, the coolant flow path includes a first flow path provided along a first side face of the flow path forming cabinet, a second flow path provided along a second side face contiguous to one side of the first side face and connected to one end of the first flow path, and a third flow path provided along a third side face contiguous to other side of the first side face and connected to other end of the first flow path.

Power Conversion Device

A power conversion device includes: a cooling base 5 in which a flow passage 51 through which a cooling medium flows is formed and an opening portion 50 which is communicated with the flow passage 51 is formed; a power module 1 ; and a flow passage control portion 16 b . The power module 1 has a bottomed cylindrical portion 13 a in which a power semiconductor element is housed and which is inserted into the flow passage 51 through the opening portion 50 , a flange portion 13 b which is formed on an opening of the cylindrical portion 13 a and is fixed to the cooling base 5 so as to close the opening portion 50 , and a group of radiator fins 144 which are mounted on an outer peripheral surface of the cylindrical portion 13 a with a gap of a predetermined distance formed between the flange portion 13 b and the group of radiator fins 144 . The flow passage control portion 16 b is arranged in a gap formed between the flange portion 13 b and the group of radiator fins 144 , and introduces the cooling medium into the group of radiator fins 144 while preventing the cooling medium from flowing into gaps 51 c.

Wafer level chip scale package

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Method of forming a semiconductor device and leadframe therefor

In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

Integrated circuit and method of providing electrostatic discharge protection within such an integrated circuit

An integrated circuit with electrostatic discharge (ESD) protection, and a method of providing such ESD protection within the integrated circuit, are disclosed. The integrated circuit comprises functional circuitry having functional components for performing processing functions required by the integrated circuit, and interface circuitry for providing an interface between the functional circuitry and components external to the integrated circuit. The integrated circuit is formed of a plurality of layers, including component level layers within which any of the functional components formed from a standard cell are constructed, power grid layers providing a power distribution infrastructure for the functional components, and intervening layers between the power grid layers and the component level layers providing interconnections between the functional components. The functional circuitry further comprises at least one ESD protection circuit constructed so as to reside solely within the component level layers in order to provide ESD protection for an associated one or more of the functional components. Such an approach enables the required ESD protection to be provided locally within the functional circuitry, whilst retaining flexibility with regard to the placement of, and routing between, the various functional components of the functional circuitry.

Gate driver with digital ground

Various exemplary embodiments relate to gate driver circuitry that compensate for parasitic inductances. Input buffers in the gate driver are grounded to an exposed die pad. Grounding may involve either a downbond or conductive glue.

Group III-V and Group IV Composite Diode

In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die.

Discrete power transistor package having solderless dbc to leadframe attach

A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

Sinterable silver flake adhesive for use in electronics

A conductive composition comprises (i) micro- or submicro-sized silver flake having a tap density of 4.6 g/cc or higher and (ii) a solvent that dissolves any fatty acid lubricant or surfactant present on the surface of the silver. In one embodiment, (iii) a small amount of peroxide is present. No organic resin is present in the composition.

3d chip stack having encapsulated chip-in-chip

A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.

Method of manufacturing semiconductor device

The invention prevents a conductive fuse blown out by laser trimming from reconnecting by a plating electrode in a plating process and prevents a plating solution etc from entering a fuse blowout portion. On a semiconductor substrate of a multilayered wiring structure including a fuse blowout groove formed by blowing out a conductive fuse by laser trimming in a trimming element forming region, a second protection layer is formed so as to cover the trimming element forming region and then a plating electrode is formed on an draw-out pad electrode made of a topmost metal wiring. A third protection layer is then formed so as to cover the semiconductor substrate including the second protection layer and have an opening on the plating electrode.

Power semiconductor apparatus

A power semiconductor apparatus which is provided with a first power semiconductor device using Si as a base substance and a second power semiconductor device using a semiconductor having an energy bandgap wider than the energy bandgap of Si as a base substance, and includes a first insulated metal substrate on which the first power semiconductor device is mounted, a first heat dissipation metal base on which the first insulated metal substrate is mounted, a second insulated metal substrate on which the second power semiconductor device is mounted, and a second heat dissipation metal base on which the second insulated metal substrate is mounted.

Power module and air conditioner

A power module is a power module having a PFC (power factor correction) function. The power module includes: IGBTs in a pair; first diodes in a pair connected to the IGBTs in a pair, the first diodes forming a reverse-conducting element; and second diodes in a pair connected to the IGBTs in a pair, the second diodes having a rectifying function. The power module further includes a driving IC that drives the IGBTs in a pair, and P terminals in a pair provided independently of each other. The P terminals are connected to one ends of the first diodes in a pair, respectively, the one ends being opposite to the other ends of the first diodes to which the IGBTs in a pair are connected.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Semiconductor Packages and Methods of Forming The Same

In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate.

Power converter apparatus

A power converter apparatus includes a first substrate and a second substrate closely arranged to face each other, switching elements mounted on respective mounting surfaces of the first and second substrates, a primary and a secondary bus bars extending between the first and second substrates, an output terminal electrically connected to the primary bus bar, and two input terminals provided on the second substrate. The direction in which current flows into the first substrate and the direction in which current flows into the second substrate via the input and the output terminals are opposite to each other, and the direction in which the current flows into the primary bus bar and a direction in which the current flows into the secondary bus bar are opposite to each other. The first substrate and second substrate include heat dissipating members provided on surfaces opposite to the mounting surfaces for the switching elements.

Semiconductor device and method for manufacturing the same

An ultrasonic welding tool is used to bond end portions of an external connection terminal to circuit patterns of an insulating substrate, with a Vickers hardness not lower than 90. Bonding end portions are provided integrally with a bar in the external connection terminal. A bonding end portion located substantially in the lengthwise center of the bar is bonded first, then others are bonded alternately in order toward either end. Hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased, and displacement of the bonding end portion in either end from its regular position is suppressed to keep bonding strength high. Bonding strength of the ultrasonic welding portions between the external connection terminal and the circuit patterns of the insulating substrate can be increased so that long-term reliability can be secured in a semiconductor device.

Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

Bonded processed semiconductor structures and carriers

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Monolithic Power Converter Package

According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip.

Method and apparatus for reducing package warpage

Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.

Semiconductor unit

A semiconductor unit includes a cooler having a fluid flow space, an insulating substrate bonded to the cooler through a metal, a semiconductor device soldered to the insulating substrate, an intermediate member interposed between the insulating substrate and the fluid flow space and having a first surface where the insulating substrate is mounted, and a mold resin having a lower coefficient of liner expansion than the intermediate member. The insulating substrate, the semiconductor device and the cooler are molded by the mold resin. The intermediate member has a second surface that extends upward or downward relative to the first surface. The first surface is covered by the mold resin. The second surface is covered by a resin cover.

Double side cooling power semiconductor module and multi-stacked power semiconductor module package using the same

Disclosed herein is a double side cooling power semiconductor module including: a first cooler having a concave part formed in one surface thereof in a thickness direction; a first semiconductor chip mounted on the concave part of the first cooler; a second cooler having one surface and the other surface and formed on one surface of the first cooler so that one surface thereof contacts the first semiconductor chip; a circuit board formed on the other surface of the second cooler; a second semiconductor chip mounted on the circuit board; and a flexible substrate having a circuit layer electrically connecting the first and second semiconductor chips to each other.

Semiconductor device

A semiconductor device according to an embodiment includes: first and second semiconductor chips, each including a first electrode and a second electrode opposite to each other in a predetermined direction; a chip-mount substrate on which the first and second semiconductor chips are mounted; and a first wiring terminal to which the second electrodes of the first and second semiconductor chips are connected. The second semiconductor chip lies over the first semiconductor chip in the predetermined direction such that the second electrode of the first semiconductor chip and the second electrode of the second semiconductor chip face each other across the first wiring terminal, and the chip-mount substrate is bent such that the first electrode of the first semiconductor chip is connected to the first electrode of the second semiconductor chip.