Verfahren zum Kapseln intergrierter Schaltungen und über das Verfahren hergestellte integrierte Schaltungsbausteine

Verfahren zum Kapseln integrierter Schaltungen, umfassend: Anbringen einer ersten integrierten Schaltung an einer ersten Fläche eines Substrats mit einer elektrischen Verbindung zwischen entsprechenden Kontakten des Substrats und der ersten integrierten Schaltung; Anbringen einer zweiten integrierten Schaltung an einer zweiten Fläche eines Substrats mit einer elektrischen Verbindung zwischen elektrischen Kontakten des Substrats und der zweiten integrierten Schaltung; und einen Ausformschritt, bei dem die erste und zweite integrierte Schaltung in Harz gekapselt werden.

GITTERANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG

Mehrchip-Gehäuse auf Glasbasis

In Ausführungsformen enthält das Mehrchip-Gehäuse auf Glasbasis ein photodefinierbares Substrat auf Glasbasis, mindestens ein elektronisches Bauteil, das auf dem photodefinierbaren Substrat auf Glasbasis angeordnet ist, und einen Teilbereich des photodefinierbaren Substrats auf Glasbasis, der mit ultraviolettem Licht belichtet wurde, wobei der Teilbereich des photodefinierbaren Substrats Keramik enthält. Außerdem kann das Sensorgehäuse zusätzliche elektronische Bauteile, ein gläsernes Touch Panel und/oder eine Leiterplatte enthalten. In Ausführungsformen enthält das Herstellen der Sensorgehäuse-Vorrichtung das Erhalten eines photodefinierbaren Substrats auf Glasbasis, das Ätzen des photodefinierbaren Substrats auf Glasbasis und das Ausbilden eines Keramik-Teilbereichs des photodefinierbaren Substrats auf Glasbasis.

Mikrofonpackage und Verfahren zu dessen Herstellung

Es werden Maßnahmen vorgeschlagen, die eine kostengünstige Realisierung eines Mikrofonpackages ermöglichen, wobei eine sehr gute Mikrofonperformance auch bei einem hohen Miniaturisierungsgrad erzielt wird. Ein derartiges Mikrofonpackage (10) umfasst ein MEMS-Mikrofonbauelement (1) mit einer Mikrofonmembran (11) und ein Gehäuse (2) mit einem Gehäuseboden (21) und einem Gehäusedeckel (22), wobei das Gehäuse (2) das Rückseitenvolumen (20) des Mikrofonbauelements (1) einschließt und im Gehäuse (2) ein akustischer Zugangskanal (30) zur Mikrofonmembran (11) ausgebildet ist, der gegen das Rückseitenvolumen (20) abgeschlossen ist und mindestens eine Schallöffnung (24) im Gehäuse (2) mit einer Seite der Mikrofonmembran (11) verbindet. Erfindungsgemäß ist innerhalb des Gehäuses (2) ein Interposer (3) montiert, der den akustischen Zugangskanal (30) zur Mikrofonmembran (11) definiert, indem er an die Schallöffnung (24) des Gehäuses (2) gekoppelt ist und mindestens eine Austrittsöffnung (32) aufweist ...

Ball grid array package

A method of soldering

IC device with a metal thermal conductive layer having an opening for evacuating air

An IC device comprises an interconnection substrate 50 having at least one conductive layer 70 and at least one insulating layer 32, a first metal thermal conductive layer 70 and a second metal thermal conductive layer 83 having a surface exposed to an exterior. This second layer 83 has an opening 84 formed at a central portion, and a hole region 36 is formed within the interconnection substrate 50 and the first metal thermal conductive layer 70. An IC chip 40 is positioned with a first surface disposed at a central portion of the hole region 36. A second surface of the IC chip 40 has a plurality of bond pads 41. The chip 40 has a width larger than the diameter of the opening 84 in the second thermal conductive later 83 and is in contact with the second thermal conductive layer 83. A plurality of bond wires 9 electrically connect the bond pads 41 on the IC chip 40 with the first conductive trace layer 70, and an encapsulation material 42 fills the hole region 36 and encloses the bond wires ...

MEMS devices and processes

MEMS devices and processes

A MEMS transducer comprising a membrane 301 and at least one mount structure 305 for supporting the membrane relative to a substrate provides a flexible membrane and further comprises one or more stress diffusing structures 701 for example a slit, is/are provided in the membrane so as to diffuse stress in the region of the mount. The membrane may have a first/active region 301 and a second/inactive region 302. The slits may be C- or U shaped. The transducer may also comprise a variable vent structure (307 see Figure 5) in the inactive region 302.

MEMS device and process

A MEMS transducer with a flexible membrane 501 and a vent structure comprising at least one moveable portion 502 which in response to differential pressure across the vent structure tilts such that one edge of the moveable portion 502 deflects below the plane of a membrane 501, whilst an opposite edge of the moveable portion 502 deflects above the plane of the membrane 501. In response to differential pressure across the vent, the moveable portion 502 may rotate about two axes (R1, Fig. 5a) & R2 to allow a variable acoustic impedance. The vent bleed holes may allow for pressure equalisation between cavities and may thus prevent damage or overload of the diaphragm 501. Rotation may expose an aperture which provides a flow path for pressure change. The moveable portion 502 may be connected to the membrane 501 by a joint structure. The microelectromechanical transducer may use capacitive sensing with electrodes and may be utilised as a microphone in mobile telephones, computing devices or ...

SEMI-CONDUCTOR ASSEMBLY

DISTRIBUTED CAPACITY

Arrangement for encasing a functional device, and a process for the production of same

EPOXY WASHER FOR RETENTION OF INVERTED SMT COMPONENTS

ARRANGEMENT FOR ENCASING A FUNCTIONAL DEVICE, AND A PROCESS FOR THE PRODUCTION OF SAME

Grid array assembly and method of making

METHOD FOR PRODUCING AN INTEGRATED CIRCUIT CARD AND CARD PRODUCED ACCORDING TO SAID METHOD

L'invention propose un procédé de fabrication d'une carte à circuit intégré, du type comportant l'étape consistant à réaliser un module (12) qui est fixé sur un corps de carte (20) et qui comporte notamment un circuit intégré (14) et des plages de contact (16), caractérisé en ce que l'étape de réalisation du module (12) comporte une étape consistant à former, dans un élément de plaque (26) en matériau conducteur, des fentes (28) qui délimitent au moins partiellement des zones de l'élément de plaque (20) destinées à former les plages de contact (16), et une étape ultérieure consistant à recouvrir, au moins partiellement, une face inférieure (32) de l'élément de plaque (26) d'une masse adhésive (30) par lequel le module (12) est destiné à être fixé ultérieurement sur le corps de carte (20).

ASSEMBLY OF A CARRIER AND A PLURALITY OF ELECTRICAL CIRCUITS FIXED THERETO, AND METHOD OF MAKING THE SAME

A method of obtaining an elongate carrier (12) to which a plurality of circuits (14) are fixed at their outer portions. The central portions (141) of the circuits are removed while the outer portions remain fixed to the carrier. A circuit (14) is fastened to a carrier (12) where electrical conductors extend from conducting pads of the circuit through holes (121) in the carrier to conducting pads of the carrier on an opposite side of the carrier.

Resin mounting structure for an integrated circuit

Hybrid circuit with surface mounted devices - formed from a thin film ceramic substrate and a laminated or adhesive bonded film substrate

The solid component, as a hybrid circuit with conductors and resistance layers, is a combination of a thick film ceramic substrate (1) and a film substrate (2). The two substrates overlap at least partially with contact between them. The two substrates (1,2) are in contact with each other through lamination or adhesive bonding. The film substrate (2) has at least one aperture (3) as a passage for the component on the ceramic substrate (1). At least one film substrate has a number of conductor planes for the electrical connection between the conductors of these planes by electroplating through holes in the film substrate. USE/ADVANTAGE - The component is a hybrid circuit with surface mounted devices. The structure and assembly is simple.

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME

Chip supporting substrate for semiconductor package, semiconductor device, and method for manufacturing them

SEMICONDUCTOR DEVICE

SEMICONDUCTOR PACKAGE AND A MANUFACTURING METHOD THEREOF, CAPABLE OF EFFICIENTLY EMITTING HEAT FROM A SEMICONDUCTOR DIE

PURPOSE: A semiconductor package and a manufacturing method thereof are provided to easily emit heat generated from a semiconductor die in an operating process by exposing a single-side of the semiconductor die through a heat emission hole passing through a substrate. CONSTITUTION: A substrate(110) includes a conductive pattern(111) formed on the upper side of the substrate and a land(112) connected to the conductive pattern. A semiconductor die(120) is formed on the upper side of the substrate. The conductive connecting member(130) electrically connects the conductive pattern of the substrate and the semiconductor die. An encapsulation(140) is formed to cover the semiconductor die. A heat emission hole(115) passes through the substrate. COPYRIGHT KIPO 2010 ...

HIGHLY MOISTURE-SENSITIVE ELECTRONIC DEVICE ELEMENT

PURPOSE: A highly moisture-sensitive electronic device element is provided to prevent wrong operation or degradation by protecting the element against moisture and sealing and encapsulating the single element. CONSTITUTION: A highly moisture-sensitive element(14) includes an encapsulation enclosure encapsulating all of highly moisture-sensitive electronic devices(12) on a substrate(10), and a sealing material positioned between the substrate and the encapsulation enclosure to form a complete seal between the substrate and the encapsulation enclosure around each highly moisture-sensitive electronic device or around groups of highly moisture-sensitive electronic devices, wherein the substrate or encapsulation enclosure, or both, contain vent holes and vent hole seal material or wherein the seal material contains gaps prior to spacing the substrate and the encapsulation enclosure within a predetermined range and the gaps are filled in by spreading the sealing material. © KIPO 2003 ...

FLIP CHIP PACKAGE HAVING SUBSTRATE WITH PLURAL HOLES THROUGH WHICH UNDER FILL MATERIAL IS INTRODUCED

PURPOSE: A flip chip package having a substrate with plural holes is provided to introduce an under fill material through the holes which are formed on the substrate, and easily discharge air generated between a semiconductor chip and the substrate through the holes. CONSTITUTION: A flip chip package includes a semiconductor chip(10) having an active surface with plural bumps(11), a substrate(20) having circuit wiring patterns electrically connected to the bumps and plural holes formed on a mounting region, a resin encapsulating portion(40) encapsulating the semiconductor chip and an upper surface of the substrate, and solder balls(21) electrically connected to the circuit wiring patterns. The holes penetrate the substrate not to expose the circuit wiring patterns. © KIPO 2007 ...

Semiconductor device package and method of manufacturing the same

The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.

Die encapsulation in oxide bonded wafer stack

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Effekttransistormodul, effektförstärkare samt förfarande vid framställning därav

Packaging multi-chip modules without wirebond interconnection

Semiconductor device and method of producing the same

A semiconductor device includes a semiconductor chip, a substrate electrically connected to the semiconductor chip and heat spreading plate thermally connected to the semiconductor chip. The substrate is provided with external connection terminals on a first surface and electrically connects the semiconductor chip and the external connection terminals. The substrate is provided with joining parts made of metal on a second surface. The heat spreading plate and the substrate are joined together by welding the joining parts and the heat spreading plate.

Standing chip scale package and process of making the same

Semiconductor apparatus

A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed in the present invention. In the invented surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate in such a manner that the chips 1 are laid out in the form of an array of two rows and two columns. These four chips 1 regarding the upper side and the lower side are disposed to have a linear symmetry with respect to a centerline of the long side direction of the substrate 2. Each chip 1 has a plurality of pads 9 disposed into an approximately linear array substantially along the centerline in the direction of short side edges. Addressing pads 9a are disposed to locate on the side of central part on a plane of the substrate 2. The control pads 9b for ...

PRESSURE ASSISTED SELF TARGETING ASSEMBLY

The invention relates to a placement method for placement of a chip component (10) on a flexible substrate (20), comprising: providing a support face (21) comprised of by the flexible substrate (20) or by a support structure to be aligned with the flexible substrate (20); administering a chip (10) to the support face (21); generating with a pressure chamber (60) an air flow in an out of plane orientation relative to the support face (21); and directing the chip to a placement position (30) by means of a directional structure (40) provided on the support face (21). In particular the chip (10) is levitated from the support face (21) by said air flow or by vibrational contact between the support face (21) and the chip (10) induced by said air flow; and wherein, when the support face is comprised by a support structure distinct from the flexible substrate, the support face is aligned with the flexible substrate. Accordingly, air cushion or intermittent contact forces (modulated in time and ...

TRANSMISSION CONTROL DEVICE AND ELECTRONIC CIRCUIT DEVICE

It is difficult to dissipate heat generated from a bare chip. In addition, if a bare chip is covered with a sealing resin in such a manner that a heat sink is exposed so as to facilitate heat dissipation, problems such as separation and cracking occur. An electronic circuit device comprises: an electronic circuit assembly for controlling a car transmission and a car brake; a base for fixing the electronic circuit assembly; and a lead terminal for electrically connecting the electronic circuit assembly, wherein the electronic circuit assembly, the base, and the lead terminal are sealed with a mold resin. The electronic circuit device has a heat dissipation structure characterized in that an opening is formed under a heat-emission circuit device (bare chip) through a circuit board and the base and both sides of a heat-emission device are thermally connected to a sealing resin.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a semiconductor chip having an active surface, on which a connection pad is disposed, and an inactive surface disposed to oppose the active surface, a heat dissipation member, disposed on the inactive surface of the semiconductor chip, having a plurality of holes and including a graphite-based material, an encapsulant covering at least a portion of each of the semiconductor chip and the heat dissipation member, and a connection member, disposed on the active surface of the semiconductor chip, including a redistribution layer electrically connected to the connection pad. 0 Подробнее

Method of soldering

In a method of soldering the surfaces of a component (11) to a substrate (12), a solder preform (15) is located in the gap between the surfaces. The solder is heated and an over pressure applied to move the surfaces together whilst the solder is molten. Abutments (17) between the surfaces limit the spacing between them. A trapped void (18) is decreased in volume as the pressure is applied. The method is particularly applicable to monolithic microwave integrated circuits (MMIC) and reduces void areas in joints.

Semiconductor device and method of mounting the semiconductor device

The present invention discloses a suitable mounting of a wafer scale LSI (wafer scale integration) (WSI) in which a slit formed in a wafer is fit to a connector, a U-shaped reinforcing rubber member is disposed at the circumferential edge of the wafer, or a flexible adhesive is used for bonding a substrate formed with through-holes and a wafer, to provide a WSI mounting structure of high integration degree and high reliability. Furthermore, a method of efficient mounting by conducting the wiring of the wafer and the connection with the external terminal of the chip in one identical production step is disclosed.

Power semiconductor switching devices, power converters, integrated circuit assemblies, Integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor

Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

Bare chip mounting structure and manufacturing method therefor

A mounting structure is provided which improves the reliability of the connection between the bumps at the four corners of a flip-chip mounted semiconductor chip which is subject to stress concentrations caused by board warping or a difference in thermal coefficient of expansion when subjecting the mounted chip to thermal cycling tests. In this structure, a sealing resin is caused to flow into a space between the semiconductor chip and the board at the four corners of the semiconductor chip, thereby forming large resin fillets at the four corners, these fillets relieving the above-noted stress at the bump connection parts of the four corners of the semiconductor chip, thereby causing an improvement in reliability of the connection. The flowing distance is shortened and simultaneous flowing resin is performed, thereby shortening the time required for sealing.

Metal electronic package

Semiconductor device with capacitor

A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.

Chip package mounting structure for controlling warp of electronic assemblies due to thermal expansion effects

A chip package is provided for controlling warp of electronic assemblies. The chip package has a first component mounted on one side of a substrate. The substrate is a multi-layered laminate having a plurality of dielectric layers made of an organic material. The first component has a different coefficient of thermal expansion (CTE) than the substrate. The chip package includes a second component mounted on an opposite side of the substrate in a location substantially opposite the first component. The second component has a CTE that approximately matches the CTE of the first component. The second component tends to generate bending moments that offset distorting bending moments that may otherwise exist in the chip package without the second component.

Soft bond for semiconductor dies

On a semiconductor integrated circuit die, a semipermanent electrical connection is effected by the use of wirebond techniques, in which the parameters of the wirebond are controlled, so that less bonding force retains the leadwires to the bondpads than the attachment strength of the bondpads to the die. The wirebond techniques include attaching leadwires to bondpads on the die, using ultrasonic wedge bonding. The strength of the bond between the leadwires is significantly less than the attachment strength of the bondpads, preferably by a ratio which ensures that the bondpads are not lifted from the die when the leadwires are removed by breaking the bond between the leadwires and the bondpads. Subsequent to testing and burnin, the bond between the leadwires and the bondpads is severed. The die are then removed from the package body and the bondpads may then be attached by conventional means. The technique is useful in providing known good die.

Resin structure in which manufacturing cost is cheap and sufficient adhesive strength can be obtained and method of manufacturing it

A resin structure includes a resin layer and a metal layer. The resin layer is formed of a single material. The metal layer is laminated directly on the resin layer without intervention of an adhesive layer between the resin layer and the metal layer. A surface of the resin layer, on which the metal layer is laminated, has a surface roughness of a value in a range of 0.1 microns to 10 microns, as a rough surface. The metal layer is formed on the rough surface of the resin layer.

Tape BGA package die-up/die down

A ball grid array (BGA) package which contains an integrated circuit die that is directly mounted to either a heat sink or a printed circuit board. In one embodiment, the package has an integrated circuit with surface pads that are coupled to a flexible circuit board. Solder balls are attached to the flexible circuit board and solder the BGA package to a printed circuit board. The flexible circuit has an opening that exposes the integrated circuit and allows the IC to be soldered to the printed circuit board by solder balls attached directly to the surface pads of the IC die. The direct attachment between the die and printed circuit board increases the number of IC output pins. The flexible circuit board and die are covered by a protective injection molded plastic housing. In a second embodiment, the integrated circuit die is flipped upside down and a surface of the die is exposed through the plastic housing. A heat sink can be attached to the exposed die surface to improve the thermal ...

Method for injection molded flip chip encapsulation

The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

Substrate for semiconductor package and method of making same

The present invention provides a substrate for a semiconductor and the semiconductor package, wherein with the setup that the conductive fingers around the chip of enclosure structure superposes with the electrical connecting element, the distance between the conductive fingers and the chip will be shortened, so as to effectively shorten the wires from the chip to the conductive fingers and reduce the materials and the processing time, in favor of cutting down the cost of production.

MEMS MICROPHONE PACKAGE USING LEAD FRAME

The present disclosure discloses an MEMS microphone package. The MEMS microphone package in accordance with the present disclosure comprises a lead frame; an integrated MEMS chip mounted on the lead frame, having a vibration unit comprising a diaphragm and a backplate spaced each other with an air gap between them and a signal processing unit for amplifying electric signals generated in the vibration unit formed on a single silicon substrate; and an electric connection means for connecting the lead frame to the integrated MEMS chip.

Method of manufacturing a semiconductor device and a semiconductor device

The back side of a strip substrate with plural semiconductor chips mounted thereon is vacuum-chucked to a lower mold half of a mold, and in this state the plural semiconductor chips are sealed with resin simultaneously to form a seal member. Thereafter, the strip substrate and the seal member are released from the mold and are cut into plural semiconductor devices. The semiconductor devices thus obtained are improved in their mounting reliability.

SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTING STRUCTURES AND FABRICATION METHOD THEREOF

A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices

In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.

Semiconductor device having a heat spreader exposed from a seal resin

A semiconductor element has a circuit formation surface on which electrode terminals are arranged in a peripheral part thereof. The semiconductor element is encapsulated by a mold resin on a substrate which has openings at positions corresponding to the electrodes of the semiconductor element. The semiconductor element is mounted to the substrate in a state where the circuit formation surface faces the substrate and the electrode terminals are positioned at the openings and a back surface opposite to the circuit formation surface of the semiconductor element is exposed from the mold resin. A heat-emitting member formed of a metal plate is provided on a surface of the substrate opposite to a surface on which the semiconductor element is mounted. The surface of the heat-emitting member being exposed from the mold resin.

Semiconductor Package Having Semiconductor Chip Within Central Aperture Of Substrate

Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed. An embodiment of a semiconductor package includes a semiconductor chip having a first major surface and a second major surface, the semiconductor chip being provided at the second major surface with a plurality of input/output pads; a circuit board including a resin substrate having a first major surface and a second major surface, a first circuit pattern formed at the first major surface and provided with a plurality of ball lands, a second circuit pattern formed at the second major surface and provided with a plurality of bond fingers connected with the ball lands by conductive via holes through the resin substrate, cover coats respectively coating the first and second circuit patterns while allowing the bond fingers and the ball lands to be exposed therethrough, and a central through hole ...

Apparatus for sealing a ball grid array package and circuit card interconnection

The present invention provides an electronic package assembly in which a ball grid array (BGA) is surface mounted to a printed wiring board using solder balls. Tubing is placed along the perimeter of the BGA housing to prevent subsequently applied sealant from contacting the solder balls or filling the gap between the BGA housing and the printed wiring board. This results in a seal that prevents electrical disconnection in the solder joint during operation of the electronic package assembly.

High frequency flip chip module and assembling method thereof

The semiconductor device embraces a module substrate; a plurality of substrate-cite interconnects disposed on the first main surface of the module substrate; a semiconductor chip mounted with the flip chip configuration; a plurality of joints connected to the substrate-cite interconnects; a circuit board; a plurality of board-cite interconnects disposed on the top surface of the circuit board, each being connected to one of the joints; and a first heat conductive material thermally connecting the bottom surface of the semiconductor chip with the top surface of the circuit board.

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE

An electronic device includes a substrate, an electronic element mounted on the substrate, bumps that electrically connect the substrate to the electronic element, dummy bumps that are formed on the substrate to surround the electronic element, and a side fill that is formed around the electronic element and is in contact with the dummy bumps. 1. An electronic device , comprising:a substrate;an electronic element mounted on the substrate;bumps that electrically connect the substrate to the electronic element;dummy bumps that are formed on the substrate to surround the electronic element; anda side fill that is formed around the electronic element and is in contact with the dummy bumps.2. The electronic device as claimed in claim 1 , whereinthe electronic element is a light-emitting element or a light-receiving element;the substrate includes an opening that is formed in a position corresponding to a light emitter of the light-emitting element or a light receiver of the light-receiving element; andthe bumps are formed around the opening.3. A method for manufacturing an electronic device claim 1 , the method comprising:forming bumps on a substrate;connecting an electronic element via the bumps to the substrate;after connecting the electronic element to the substrate, forming dummy bumps on the substrate;applying a side fill resin onto the bumps and the dummy bumps; andcuring the side fill resin. The present application is based upon and claims the benefit of priority of Japanese Patent Application No. 2017-029990, filed on Feb. 21, 2017, the entire contents of which are incorporated herein by reference.An aspect of this disclosure relates to an electronic device and a method for manufacturing the electronic device.An electronic device including a light-emitting element and a light-receiving element is used in the field of optical communication. Such an electronic device is called an optical module and is used for high-speed optical communication performed by, for ...

Bonding an interconnect to a circuit device and related devices

This disclosure relates to a system and method for bonding an interconnect to a dense circuit device.

SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.

Image sensor package to limit package height and reduce edge flare

An image sensor package, comprising a silicon substrate; an image sensor pixel array that is formed on the silicon substrate; a peripheral circuit region that is formed around the image sensor pixel array on the silicon substrate; a redistribution layer (RDL) that is electrically coupled to the peripheral circuit region; at least one solder ball that is electrically coupled to the RDL; and a cover glass that is coupled to the RDL. No part of the RDL is located directly above or below the image sensor pixel array. No part of the at least one solder ball is located directly above or below the silicon substrate. A dark material layer is implemented to prevent an edge flare effect of the image sensor pixel array.

Device package with reduced radio frequency losses

A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness.

LEAD FRAMELESS HERMETIC CIRCUIT PACKAGE

Layered features for co-fired module integration

LIGHTING DEVICE WITH LED ELEMENTS ON A MOUNTING ELEMENT ON A FLAT CARRIER AND METHOD OF MANUFACTURING THE SAME

複数のインターポーザを伴うスタックドダイアセンブリ

MANUFACTURE OF INFRARED SENSOR

PROBLEM TO BE SOLVED: To facilitate the highly accurate position alignment with respect to the manufacturing method of an infrared sensor including the process for fixing a plurality of infrared-ray sensing element parts on a substrate. SOLUTION: Metal bumps 3a and 3b are formed at a plurality of places around the light receiving surfaces and the surfaces on the opposite side of infrared-ray sensing element parts 1a and 1b. Metal bumps 4a and 4b are formed at the positions facing the bumps 3a and 3b of the infrared-ray sensing element parts 1a and 1b on a substrate 2. Furthermore, optical hardening bonding agents 5a and 5b are applied to the surfaces for fixing the infrared-ray sensing element parts 1a and 1b. The infrared-ray sensing element parts 1a and 1b are mounted on the substrate 2 and positioned so that the bumps 3a, 4a, 3b and 4b face to each other. The bumps are compressed and fused, and vacuum sucking is performed through vacuum sucking holes 6a and 6b so that the substrate 2 ...

Multichip-Modul und Verfahren zu seiner Herstellung

Ein Multichipmodul enthält eine Montageplatine, eine Anzahl Chips und eine Verdrahtungsplatine. Die Chips sind horizontal auf der Montageplatine angeordnet. Die Chips sind elektrisch mit der Montageplatine verbunden und jeweils mit Durchgangslöchern ausgestattet, die die Chips durchdringen. Die Chips sind auf ihren Oberflächen, die zur Montageplatine zeigen, jeweils mit Schaltungen versehen. Die Verdrahtungsplatine ist auf einer Seite angeordnet, die der Montageplatine bezogen auf die Chips gegenüberliegt. Die Verdrahtungsplatine enthält ein Verdrahtungsmuster, das benachbarte Chips elektrisch miteinander verbindet. Die Schaltung ist über Durchgangslöcher elektrisch mit dem Verdrahtungsmuster verbunden.

EINE INTEGRIERTE SCHALTUNGSPACKUNG MIT EINER LÜFTUNGSÖFFNUNG

Method for manufacturing circuit device, involves making contact portion of semiconductor chip to project into contacting tub of strip guard

The adhesive (3) is coated on contacting region (4) of a semiconductor substrate (1), and a strip guard pattern (2) is formed in contacting region. The solder material (17) is brought in contact with contacting tubs (6) in strip guard, and applied on a contact portion (12) of a semiconductor chip (9). The contact portion of chip is made to project into contacting tub. The chip and contacting region of substrate are heated such that the chip is adhered with the substrate, and the chip contact portions are made to contact with contact surface (2.1) of strip guard pattern. An independent claim is included for circuit device.

Chipmodul zum Einbau in einen Chipkartenträger sowie Verfahren zu dessen Herstellung

A chip module (1) for installation in a chip card carrier, comprising a semiconductor chip (5) and a leadframe (2) in the form of a metal layer. An adhesive layer (11) is provided in between the metal layer and the semiconductor chip (5), whereby said adhesive is flowable in a non-hardened state and spreads on the basis of capillary action. The semiconductor chip (5) is covered with a hotmelt adhesive (7) layer extending from the leadframe (2).

Struktur und Bildungsverfahren für Chippaket

Strukturen und Bildungsverfahren eines Chippakets werden bereitgestellt. Das Chippaket umfasst einen Chipstapel, der eine Anzahl von Halbleiter-Dies umfasst. Das Chippaket umfasst auch einen Halbleiterchip und der Halbleiterchip ist höher als der Chipstapel. Das Chippaket umfasst weiter eine Paketschicht, die eine Oberseite und Seitenwände des Chipstapels und Seitenwände des Halbleiterchips abdeckt.

Anschlußgehäuse für ein elektronisches Bauelement

Das Anschlußgehäuse besitzt einen Grundkörper (1) mit oberseitig ringsum laufenden Seitenwänden (2), welche das einzusetzende Bauelement (6) sowie zwischen dem Bauelement und mindestens einer Seitenwand angeordnete Innenkontakte (8) umschließen. Auf der Unterseite sind angeformte Polymerhöcker (3) zur Bildung von Außenkontakten (4) angeformt. Die Verbindung zwischen den Innenkontakten (8) der Oberseite und den Außenkontakten (4) der Unterseite erfolgt über Mikrobohrungen (11), die im Mittelbereich des Grundkörpers (1) unterhalb des Bauelementes (6) angeordnet sind. Auf diese Weise erhält man ein Gehäuse mit geringem Platzbedarf auf einer Leiterplatte, welches in wirtschaftlicher Weise, vorzugsweise unter Anwendung des Laserstrukturierens, herstellbar ist.

Semiconductor chip assembling method, involves lifting component region of chip from substrate such that region indirectly contacts substrate via soldering material and chip is assembled on substrate by flip-chip technique

The method involves melting a soldering material on an assembling region of a semiconductor chip (5) by a soldering process such that the assembling region moves towards a substrate (10) due to the surface tension of the melted material. A component region of the chip is lifted from the substrate during the process such that the region indirectly contacts the substrate via the soldering material and the chip is assembled on the substrate by the Flip-chip technique. A supporting socket in the component region contacts either the substrate after the chip is assembled. An independent claim is also included for a semiconductor chip assembled on a substrate by a flip-chip technique.

Mikrostrukturbauelement, insbesondere mikrostrukturiertes Hochfrequenzbauelement

Es wird ein Mikrostrukturbauelement (5), insbesondere ein mikrostrukturiertes Hochfrequenzbauelement, mit einem Grundkörper (11) vorgeschlagen, auf dem bereichsweise eine insbesondere planare Leiterstruktur (17, 17', 17'', 17''') angeordnet ist. Weiter ist ein Dichtungsbereich (16) vorgesehen, in dem die Leiterstruktur (17, 17', 17'', 17''') von dem Grundkörper (11) und einem Glas (19) umschlossen ist. Die mit dem Glas (19) eingeschlossene Leiterstruktur (17, 17', 17'', 17''') dient vor allem als hermetisch dichte Durchführung für hochfrequente elektromagnetische Wellen aus dem Innenraum (21) eines verkappten Bauteils (12) oder Sensorelementes.

Verfahren zum Verpacken von Halbleiterchips und entsprechende Halbleiterchipanordnung

Die vorliegende Erfindung schafft ein Verfahren zum Verpacken von Halbleiterchips und eine entsprechende Halbleiterchipanordnung. Das Verfahren weist folgende Schritte auf: Verfahren zum Verpacken von Halbleiterchips mit den Schritten: Bereitstellen eines Halbleiterchips (5) mit einem Membranbereich (55); Vorsehen einer Kappe (10; 10a-g) über dem Membranbereich (55) unter Freilassen des Membranbereichs (55); Anbringen des Halbleiterchips (5) auf einem Trägerrahmen (1) und Vorsehen eines Moldgehäuses (20; 20a-f) um den Halbleiterchip (5) und zumindest einen Teilbereich des Trägerrahmens (1) zum Verpacken des Halbleiterchips (5).

Elektronische Baugruppe mit einem zwischen zwei Substraten eingebauten Bauelement und Verfahren zu dessen Herstellung

Die Erfindung betrifft eine elektronische Baugruppe mit einem Bauelement (11), welches zwischen einem ersten Substrat (12) und einem zweiten Substrat (13) gehalten ist. Zusätzlich ist vorgesehen, dass ein Spalt (18) zwischen dem ersten Substrat (12) und dem Bauelement (11) mit einem Durchgangsloch (21) verbunden ist, so dass durch das Durchgangsloch hindurch ein Fügehilfsstoff (24) unter Ausnutzung von im Durchgangsloch (21) und im Spalt (18) wirkenden Kapillarkräften dosiert werden kann. Dabei erfolgt die Dosierung automatisch, da die Kapillarkräfte nur im Spalt wirken. Erfindungsgemäß bleibt der Fügehilfsstoff während des Betriebes der Baugruppe flüssig und kann daher auch unterschiedliche Wärmedehnungen ausgleichen. Vorteilhaft lässt sich durch die automatische Dosierung des Lotwerkstoffs ein Toleranzausgleich bewerkstelligen, der aufgrund unterschiedlicher Spaltmaße notwendig werden kann. Die Erfindung betrifft auch ein Verfahren zum Herstellen der beschriebenen Baugruppe.

Resin-encapsulated semiconductor device

Alternative 3D Stacking Scheme for DRAMs Atop GPUs

Ball grid array package

MEMS device and process

A MEMS transducer comprising a flexible membrane 501 with a vent structure comprising at least one moveable portion 502 which, in response to differential pressure across the vent, is rotatable about two axes of rotation R1, R2 which are in the plane of the membrane 501. The vent bleed holes allow for pressure equalisation between cavities and the double hinge reduces the effect of high pressure impulses by utilising a double hinge thus preventing damage or overload of the diaphragm 501. The dual axes may allow a variable acoustic impedance. Rotation about R1 may cause deflection away from the membrane plane, whilst rotation about R2 may cause tilting, exposing an aperture which provides a flow path for pressure change. A joint or beam between the triangular, rectangular, or square shaped membrane 501 and flap 502 may be provided off-centre along an edge. The microeletromechanical transducer may use capacitive sensing with electrodes and may be utilised as a microphone in mobile telephones ...

Interated mems transducers

CONNECTION AND PROCEDURE FOR THE CONNECTION OF AN ARTICLE AND A TRAGERS BY LÍTEN

PROCEDURE FOR APPLYING A MICRO-SYSTEM OR A TRANSDUCER ON A SUBSTRATE AND IN THIS PROCEDURE PRODUCIBLE DEVICE

ELECTRONIC MODULE FOR MAPS AND PRODUCTION OF SUCH A MODULE

Distributed capacitor

Method for producing an integrated circuit card and card produced according to said method

PACKAGING MULTI-CHIP MODULES WITHOUT WIRE-BOND INTERCONNECTION

Described is a novel packaging of MCM tiles without wire-bond interconnections and in a total thickness which is reduced relative to conventional MCM packaging The MCM tile includes a substrate with a plurality of peripheral metallizations and at least one chip flip-chip mounted on the substrate. The PWB is provided with an aperture which is smaller than the size of the silicon substrate but larger than the outside dimensions of the mounted chips. The substrate is positioned on the PWB so that its ends overlap areas of the PWB adjacent the aperture and the chips fit into the aperture. Peripheral metallizations on the substrate are interconnected to metallizations on the PWB by either solder reflow technology or conductive adhesive technology.

In the MEMS device embedded circuit

Packaged chip

半导体器件、电子设备及它们的制造方法和电子仪器

... 一种半导体器件、电子设备及它们的制造方法和电子仪器，所述半导体器件通过承载基板(11)上设置的连接台(12c)上分别结合突出电极(26)，(36)，在半导体芯片(13)上分别配置承载基板(21)，(31)的端部，在承载基板(11)上分别安装承载基板(21)，(31)。根据本发明，实现不同种类组件的三维安装结构。 ...

IC安装结构、液晶器件和电子装置

... 简单并快捷地进行将IC芯片安装到不透明电路基板上的操作。在不透明电路基板1中借助通孔形成对准标记4K。通过CCD照相机9穿过对准标记孔4K拍摄IC芯片3的对准标记4I，调节IC芯片3的位置，以使IC侧对准标记4I与基板侧对准标记4K成规定的位置关系。然后，使用如ACF2等的粘合剂将IC芯片3粘附到电路基板1上。通过照相机9的一次拍摄可以同时拍摄对准标记4I和4K，可以连续地进行对准。 ...

半导体装置及其制造方法、电路基板和电子装置

... 本发明提供一种能防止外部电极的裂纹的半导体装置及其制造方法、电路基板和电子装置。半导体装置具有：形成了贯通孔(14a)的绝缘膜(14)；具有电极(13)的半导体芯片(12)；布线图形(18)，通过粘接剂(17)粘接在绝缘膜(14)的一个面的包含贯通孔(14a)上方的区域上并与半导体芯片(12)的电极(13)进行导电性的连接；以及外部电极(16)，通过贯通孔(14a)设置在布线图形(18)上，同时从与布线图形(18)相反一侧的面突出，将粘接剂(17)的一部分引入并介于贯通孔(14a)与外部电极(16)之间。 ...

The electrostatic capacity type sensor, a sound sensor and microphone

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Semiconductor package module

There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.

Stacked semiconductor package

A stacked semiconductor package includes a substrate having an upper surface and a lower surface, and divided into a first region and a second region that adjoins the first region; a support member formed in the second region on the upper surface of the substrate; and a semiconductor chip module including a plurality of semiconductor chips each of which has bonding pads near one edge of a first surface thereof and which are stacked on the support member in a step-like shape such that their bonding pads face the first region and are bent such that the bonding pads are electrically connected with the substrate.

Organic light-emitting display device

An organic light-emitting display device may include a substrate; a plurality of thin film transistors (TFTs) on the substrate; a plurality of first electrodes respectively on the TFTs; a pixel-defining layer between the first electrodes, the pixel-defining layer including a covered portion and an uncovered portion; a plurality of organic layers respectively on the first electrodes, each organic layer including an emission layer; a second electrode covering at least a part of the organic layers and the pixel-defining layer, a portion of the pixel-defining layer covered by the second electrode defining the covered portion, wherein at least one outgassing hole is in the uncovered portion of the pixel-defining layer, the uncovered portion being an exposed area of the pixel-defining layer.

Semiconductor Interposer Having a Cavity for Intra-Interposer Die

A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

Reducing stress in multi-die integrated circuit structures

An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.

Method of forming an electronic package and structure

In one embodiment, an electronic package structure includes multiple rows of I/O pads and is formed without a flag portion. An electronic device may be attached to a pair of adjacent inner rows of I/O pads. The pair of adjacent inner rows of I/O pads is configured to support, at least in part, the electronic device, and to receive connective structures, such as wire bonds. Connective structures may electrically connect the electronic device to the multiple rows of I/O pads, and an encapsulating layer covers portions of the I/O pads, the electronic device and the connective structures.

Semiconductor package and method of fabricating the same

Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.

Solid-state image pickup element and solid-state image pickup element mounting structure

A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.

Semiconductor Device and Method of Forming Trench and Disposing Semiconductor Die Over Substrate to Control Outward Flow of Underfill Material

A semiconductor device has a substrate including an opening. A trench is formed over the substrate around the opening. An interconnect structure is formed in the trench. An underfill material is disposed over the interconnect structure. A first semiconductor die is disposed over the underfill material prior to curing the underfill material. An active region of the first semiconductor die is disposed over the opening in the substrate. The trench contains the outward flow of underfill material. Underfill material is blocked from flowing over unintended areas on the surface of substrate, into the opening in the substrate, and over sensors of the first semiconductor die. A second semiconductor die is disposed over the substrate. The trench is formed by a first and second dam or a first insulating layer. A second insulating layer is formed over the first insulating layer. A dam is formed over the second insulating layer.

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Semiconductor assemblies including thermal management configurations for reducing heat transfer between vertically stacked devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise at least one memory device mounted over a logic device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the memory device and the logic device. The thermally conductive layer includes a structure configured to transfer the thermal energy across a horizontal plane. The thermal-insulator interposer includes a structure configured to reduce heat transfer between the logic device and the memory device.

PACKAGE SUBSTRATE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

Provided are a package substrate and a method of fabricating a semiconductor package. The package substrate includes: a base substrate having a plurality of packaging unit regions arranged along rows and columns on one surface thereof; and a sink portion penetrating at least a portion of the base substrate from the one surface, in which the packaging unit regions may be disposed adjacent to a first side of the one surface and the sink portion may be disposed adjacent to a second side of the one surface. 1. A package substrate comprising:a base substrate having a plurality of packaging unit regions arranged along rows and columns on one surface thereof; anda sink portion oriented toward the other surface of the base substrate opposed to the one surface,wherein the packaging unit regions are disposed adjacent to a first side of the one surface, the sink portion is disposed adjacent to a second side of the one surface, and the second side is opposed to the first side and is parallel to a direction of the rows.2. The package substrate according to claim 1 , wherein a distance from the packaging unit regions of a first row to the first side of the one surface is shorter than a distance from the packaging unit regions of a last row to the second side of the one surface.3. The package substrate according to claim 1 , wherein a total number of the columns is greater than a total number of the rows.4. The package substrate according to claim 1 , wherein the sink portion penetrates the base substrate and connects the one surface and the other surface.5. The package substrate according to claim 1 , wherein the sink portion is recessed from the one surface without penetrating the base substrate.6. The package substrate according to claim 1 , wherein the sink portion comprises a plurality of sink portions claim 1 , and the sink portions are offset-arranged in a direction of the rows with respect to the packaging unit regions of a last row.7. The package substrate according to ...

Substrate design for semiconductor packages and method of forming same

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

Microelectronic Assembly With Thermally and Electrically Conductive Underfill

A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer 1. A microelectronic assembly comprising:a microelectronic element having a surface and a plurality of contacts at the surface;a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element;electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts;a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; andan electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer. ...

Flexible printed wiring board, joined body, pressure sensor and mass flow controller

In a flexible printed wiring board (1), a first electrical conduction pattern (4) prepared on the first surface (3a) on which a bare chip (2) is mounted is prepared only inside a mounting region (3c) of the bare chip. Preferably, the first electrical conduction patterns (4) are prepared so as to avoid positions opposite to test electrodes (2b) which the bare chip comprises. Thereby, in the flexible printed wiring board used for mounting the bare chip, occurrence of malfunction resulting from electrical connection with a part other than a bump of the bare chip can be certainly prevented, and reliability of various devices using the bare chip can be improved.

Flow Sensor and Manufacturing Method of the Same and Flow Sensor Module and Manufacturing Method of the Same

Technique of suppressing performance variations for each flow sensor is provided. In a flow sensor FS 1 of the present invention, a part of a semiconductor chip CHP 1 is configured to be covered with resin (MR) in a state in which a flow sensing unit (FDU) formed on a semiconductor chip CHP 1 is exposed. Since an upper surface SUR(MR) of the resin (MR) is higher than an upper surface SUR(CHP) of the semiconductor chip (CHP 1 ) by sealing the resin (MR) on a part of the upper surface SUR(CHP) of the semiconductor chip CHP 1 in a direction parallel to an air flow direction, the air flow around the flow sensing unit (FDU) can be stabilized. Further, interface peeling between the semiconductor chip (CHP 1 ) and the resin (MR) can be prevented by an increase of contact area between the semiconductor chip (CHP 1 ) and the resin (MR).

System and method of chip package build-up

A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

SEMICONDUCTOR DEVICE

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. 1. A semiconductor device comprising:a semiconductor chip having a first side, a second side opposite the first side, a first upper surface on which a plurality of electrodes is formed and a first back surface opposite the first upper surface;a tab having a first side, a second upper surface to which the semiconductor chip is fixed;a plurality of leads arranged along the first side of the tab in a plan view;a plurality of first wires connecting a plurality of first electrodes of the plurality of electrodes with the plurality of leads, respectively;a plurality of second wires connecting a plurality of second electrodes of the plurality of electrodes with the tab, respectively; anda seal member sealing the semiconductor chip, the tab, a part of each of the plurality of leads, the plurality of first wires and the plurality of second wires,wherein, in the plan view, the plurality of electrodes of the semiconductor chip is arranged along the first side of the semiconductor chip,wherein, in the plan view, the first side of the semiconductor chip extends in a first direction and is disposed between the second side of the semiconductor chip and the first side of the tab, ...

DYNAMIC RANDOM ACCESS MEMORY (DRAM) MOUNTS

Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM. 1. (canceled).2. A circuit package , comprising:a first memory device situated to a first side of a processor in parallel to the processor and mounted on a package board of a processor assembly; anda second memory device situated to a second side of the processor in parallel to the processor and mounted on the package board of the processor assembly.3. The circuit package of claim 2 , wherein the first memory device and the second memory device are donut-shaped.4. The circuit package of further comprising a heat spreader mounted on top of the processor and extending past a first outer edge along the first side past the first memory device and the heat spreader extending past a second outer edge along the second side past the second memory device.5. The circuit package of further comprising claim 2 , at least one additional first memory device stacked on top of the first memory device.6. The circuit package of further comprising claim 5 , at least one additional second memory device stacked on top of the second memory device.7. The circuit package of claim 6 , wherein the at least one additional first memory device claim 6 , the first memory device claim 6 , the at least one additional second memory device claim 6 , and the second memory device have heights that are less than a processor height for the processor on the packaging board of the processor assembly.8. The circuit package of claim 7 , wherein a first outer edge of the first memory device overhangs beyond a first side edge of the packaging board claim 7 , and wherein a second outer edge of the second memory device overhangs beyond a second side edge of the packaging board.9. The circuit ...

MULTI-DEVICE TRANSDUCER MODULE, APPARATUS INCLUDING THE TRANSDUCER MODULE AND METHOD OF MANUFACTURING THE TRANSDUCER MODULE

A multi-device module, comprising: a first substrate, which houses a first MEMS transducer, designed to transduce a first environmental quantity into a first electrical signal, and an integrated circuit, coupled to the first MEMS transducer for receiving the first electrical signal; a second substrate, which houses a second MEMS transducer, designed to transduce a second environmental quantity into a second electrical signal; and a flexible printed circuit, mechanically connected to the first and second substrates and electrically coupled to the integrated circuit and to the second MEMS transducer so that the second electrical signal flows, in use, from the second MEMS transducer to the integrated circuit. 1. A system , comprising:a first substrate;a first MEMS transducer on the first substrate;a second substrate;a second MEMS transducer on the second substrate;an integrated circuit; anda flexible printed circuit having a first end and a second end, the first end being mechanically coupled to the first substrate, the second end being mechanically coupled to the second substrate, the flexible printed circuit being electrically coupled to the integrated circuit and to the second MEMS transducer.2. The system of claim 1 , further comprising:a first covering element coupled to the first substrate, the first substrate and the first covering element defining a first package that houses the first MEMS transducer; anda second covering element coupled to the second substrate, the second substrate and the second covering element defining a second package that houses the second MEMS transducer.3. The system of claim 2 , wherein the first and second covering elements are coupled together; and wherein the first substrate has a through hole that places the first MEMS transducer in acoustic communication with an environment external to the first package.4. The system of claim 3 , wherein the second substrate has a through hole that places the second MEMS transducer in acoustic ...

Multi-chip package

A multi-chip package may include a package substrate, a connecting substrate, a plurality of semiconductor chips and a logic chip. The package substrate may have an opening. The connecting substrate may be arranged on an upper surface of the package substrate. The semiconductor chips may be stacked on an upper surface of the connecting substrate. The semiconductor chips may be electrically connected with the connecting substrate. The logic chip may be arranged in the opening. The logic chip may be electrically connected between the connecting substrate and the package substrate. Thus, the logic chip may not act as to increase a width of the multi-chip package.

Semiconductor package

A semiconductor package includes a substrate, a semiconductor die, a dummy die, a conductive layer, at least one first conductive wire, and at least one second conductive wire. The semiconductor die is disposed on the substrate. The dummy die is disposed on the semiconductor die. The conductive layer is disposed on the dummy die. The first conductive wire electrically connects the semiconductor die to a signal source. The second conductive wire electrically connects the conductive layer to a ground reference.

Double-sided substrate with cavities for direct die-to-die interconnect

Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

Fan-Out WLP With Package

The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate.

Microphone module with sound pipe

A microphone module has a substrate with an aperture to allow sound waves to pass through the substrate, a lid mounted to the substrate to define a first interior volume, a microphone mounted to the substrate within the first interior volume, and a housing coupled to the substrate and covering the aperture. The housing forms a second interior volume and includes an acoustic port configured to allow sound to enter the second interior volume. The module further includes a pipe extending from the acoustic port in the housing, and at least one exterior interface pad outside of the second interior volume. The pipe has an open end to receive sound waves and direct them toward the acoustic port in the housing. Moreover, the at least one exterior interface pad electrically couples to the microphone.

SEMICONDUCTOR PACKAGE USING A POLYMER SUBSTRATE

A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure. 1. A semiconductor device , comprising:a cavity substrate comprising a substrate top side, a substrate bottom side, a substrate sidewall joining the substrate top side to the substrate bottom side, and a cavity through the substrate top side, wherein the cavity comprises a cavity bottom surface and a cavity sidewall, wherein an inner surface of the cavity sidewall extends from the cavity bottom surface to the substrate top side, and wherein the inner surface of the cavity sidewall and an outer surface of the substrate sidewall define a wall thickness of the substrate sidewall;a ground path on the outer surface of the substrate sidewall;an electrical component in the cavity of the cavity substrate;a semiconductor die in the cavity of the cavity substrate, wherein the semiconductor die is coupled to the electrical component;a planar substrate coupled to the substrate top side and the ground path, wherein the planar substrate covers the electrical component and the semiconductor die in the cavity of the cavity substrate;a first conductive land on an external surface of the semiconductor device, wherein the first conductive land is coupled to the ...

Support structure for mems device with particle filter

Various embodiments of the present disclosure are directed towards a microphone including a support structure layer disposed between a particle filter and a microelectromechanical systems (MEMS) structure. A carrier substrate is disposed below the particle filter and has opposing sidewalls that define a carrier substrate opening. The MEMS structure overlies the carrier substrate and includes a diaphragm having opposing sidewalls that define a diaphragm opening overlying the carrier substrate opening. The particle filter is disposed between the carrier substrate and the MEMS structure. A plurality of filter openings extend through the particle filter. The support structure layer includes a support structure having one or more segments spaced laterally between the opposing sidewalls of the carrier substrate. The one or more segments of the support structure are spaced laterally between the plurality of filter openings.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor module having a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed, a cooler, first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler, and second insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease. 1. A semiconductor device comprising:a semiconductor module comprising a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed;a cooler;first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler; andsecond insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease.2. The semiconductor device according to claim 1 , wherein the resin has a resin through hole formed therein which communicates with the at least one radiator plate through hole.3. The semiconductor device according to claim 2 , whereinthe resin has a wide portion formed in at least part of the resin through hole, the wide portion having a larger width than the at least one radiator plate through hole, andthe wide portion has third insulating grease provided therein.4. The semiconductor device according to claim 2 , further comprising a stopper for blocking at least part of the resin through hole.5. The semiconductor device according to claim 4 , further comprising gel for fixing the stopper in place.6. The ...

SEMICONDUCTOR DEVICE PACKAGES WITH DIRECT ELECTRICAL CONNECTIONS AND RELATED METHODS

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Vias may directly electrically connect the uppermost semiconductor die to the substrate. 1. A semiconductor device package , comprising:a substrate;a stack of semiconductor dice attached to the substrate, an uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate being a heat-generating component configured to generate more heat than underlying semiconductor dice of the stack located between the uppermost semiconductor die and the substrate, an active surface of the uppermost semiconductor die facing the underlying semiconductor dice;a first set of vias extending through underlying semiconductor dice located beneath the uppermost semiconductor die, the first set of vias electrically interconnecting the underlying semiconductor dice at least to one another and to the substrate;a second set of vias extending through the underlying semiconductor dice, the second set of vias directly electrically connecting the uppermost semiconductor die to the substrate, the second set of vias located laterally adjacent to the first set of vias; andan encapsulation material at least partially surrounding the stack of semiconductor dice, an inactive surface of the uppermost semiconductor die remaining uncovered by the encapsulation material.2. The semiconductor device package of claim 1 , wherein the first set of vias is located laterally between subgroupings of the second set of vias.3. The semiconductor device package of claim 1 , wherein the second set of vias extend through ...

Warpage Control for Flexible Substrates

A flexible substrate may be provided having a first side and a second side. A device may be electrically coupled to the first side of the flexible substrate through one or more electrical connections. A warpage control device may be attached to the second side flexible substrate. The warpage control device may include an adhesive layer and a rigid layer. The warpage control device may be formed in an area of the second side of the flexible substrate that may be opposite the one or more electrical connections on the first side of the flexible substrate.

Electronic element mounting substrate and electronic device

An electronic element mounting substrate according to the present disclosure includes a base body having a recessed portion including a mounting region on which an electronic element is mounted and a cutout section located on an outer periphery of the base body in a plane perspective, and a channel having an inner end portion located on an inner wall of the base body and an outer end portion located on the outer periphery of the base body. The inner end portion of the channel is open to the recessed portion, and the outer end portion of the channel is continuous with the cutout section.

Multi-port device package

An integrated device package includes a housing having a first opening and a second opening in fluid communication with an interior volume of the housing. A package substrate(s) has a first port and a second port. A first device die is mounted to the substrate(s) over the first port. A second device die is mounted to the substrate(s) over the second port. The substrate(s) is coupled to the housing to cover the first and second openings such that the first device die is disposed within the interior volume through the first opening and the second device die is disposed within the interior volume through the second opening.

Capacitance-type transducer, acoustic sensor, and microphone

A capacitance-type transducer has a substrate having a cavity, a vibrating electrode plate disposed above the substrate, a back plate disposed on the substrate, a fixed electrode plate disposed on the back plate opposite the vibrating electrode plate, a plurality of holes formed in the back plate and the fixed electrode plate, and a protrusion disposed on the back plate at a location opposing the vibrating electrode plate. In a view from a direction perpendicular to an upper surface of the substrate, a shortest distance from a cross-sectional center of the protrusion to an edge of a hole adjacent to the protrusion is larger than a shortest distance from a center of a region that is surrounded by the holes but not provided with the protrusion to an edge of a hole in the periphery.

SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor. 1. A method for electrostatically storing energy in a package assembly including a chip stack and a lid , the method comprising:storing a first charge on a first plate of a capacitor provided by a flange of the lid that is coupled with the chip stack; andstoring a second charge on a second plate of the capacitor provided by a section of a conductive layer located along a sidewall of a first substrate of the package assembly that supports and laterally surrounds the chip stack, wherein the flange of the first plate and the second plate are laterally separated by a gap composed of dielectric material having a permittivity, and the first substrate is a laminated substrate containing a through-hole in which at least a portion of the chip stack and the lid and flange are located.2. The method of claim 1 , wherein the conductive layer is ring-shaped.3. The method of claim 1 , further comprising a solder ball on the conductive layer of the first substrate.4. The method of claim 1 , wherein the lid is cup shaped.5. The method of claim 1 , wherein the dielectric material that provides the gap is air.6. The method of claim 1 , wherein the ...

Acoustic Assembly and Method of Manufacturing The Same

A microelectromechanical system (MEMS) microphone includes a base; a cover having a port extending therethrough; a MEMS die coupled to the cover, the MEMS die including a diaphragm and a back plate; an application specific integrated circuit (ASIC) coupled to the cover and the MEMS die; and an electrical interconnection from the ASIC to the base, the electrical interconnection being disposed on an inside surface of the cover. The base includes customer pads, the customer pads on the base being connected electrically to the ASIC via the electrical interconnection. The microphone is connected to a customer board at the base and arranged such that sound enters through the port in the cover.

Robust and Reliable Power Semiconductor Package

In one implementation, a semiconductor package includes a patterned conductive carrier including a support segment having a partially etched recess. The semiconductor package also includes an integrated circuit (IC) situated on the support segment, and an electrical connector coupling the IC to the partially etched recess. In addition, the semiconductor package includes a packaging dielectric formed over the patterned conductive carrier and the IC. The packaging dielectric interfaces with and mechanically engages the partially etched recess so as to prevent delamination of the electrical connector. 1. A semiconductor package comprising:a patterned conductive carrier including a support segment having a partially etched recess;an integrated circuit (IC) situated on said support segment;an electrical connector coupling said IC to said partially etched recess;a packaging dielectric formed over said patterned conductive carrier and said IC, said packaging dielectric interfacing with and mechanically engaging said partially etched recess so as to prevent delamination of said electrical connector.2. The semiconductor package of claim 1 , wherein said partially etched recess comprises a trench formed in said support segment.3. The semiconductor package of claim 1 , wherein said partially etched recess comprises a ledge formed at a boundary of said support segment.4. The semiconductor package of claim 1 , wherein said partially etched recess is substantially half-etched.5. The semiconductor package of claim 1 , wherein said support segment is configured to provide a ground contact for said IC.6. The semiconductor package of claim 1 , wherein said patterned conductive carrier comprises at least a portion of a lead frame.7. The semiconductor package of claim 1 , further comprising a control FET having a control drain coupled to a control drain segment of said patterned conductive carrier claim 1 , and a sync FET having a sync source coupled to said support segment.8. The ...

Semiconductor devices and methods of controlling temperature thereof

An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole. 1. A semiconductor package comprising:a first substrate;a first semiconductor chip disposed on the first substrate;a plurality of support patterns laterally spaced apart from each other on an upper surface of the first semiconductor chip;a second substrate on the plurality of support patterns;a connection terminal between the first substrate and the second substrate, the connection terminal electrically connecting the first substrate to the second substrate; anda molding structure disposed between the first substrate and the second substrate and surrounding sidewalls of the connection terminal.2. The semiconductor package of claim 1 , wherein each of the plurality of support patterns extends through a portion of the molding structure between the first semiconductor chip and the second substrate so as to contact the upper surface of the first semiconductor chip.3. The semiconductor package of claim 2 , wherein the plurality of support patterns are in contact with a bottom surface of the second substrate.4. The semiconductor package of claim 1 , wherein the molding structure extends to a gap between side surfaces of the plurality of support patterns claim 1 , the gap provided between the upper surface of the first semiconductor chip and a bottom surface of the second substrate.5. The semiconductor package of claim 1 , wherein the plurality of support patterns are connected to the second substrate.6. The semiconductor package of claim 5 , wherein the plurality of support patterns include the same material as ...

MICROPHONE DEVICE WITH INTEGRATED PRESSURE SENSOR

A microphone device comprises a microphone die including a microphone motor, an acoustic integrated circuit structured to process signals produced by the microphone motor, and a sensor die stacked on top of the acoustic integrated circuit, wherein the sensor die comprises a pressure sensor. Another microphone comprises a microphone die including a microphone motor and an integrated circuit die. The integrated circuit die comprises an acoustic integrated circuit structured to process signals produced by the microphone motor, a pressure sensor, and a pressure integrated circuit structured to press signals produced by the pressure sensor. 1. A microphone device comprising:a substrate;a cover attached to the substrate that forms a housing interior with the substrate;a microphone die disposed in the housing interior, wherein the microphone die includes a microphone motor including a diaphragm and a backplate opposing the diaphragm;an acoustic integrated circuit structured to process signals produced by the microphone motor; anda sensor die disposed in the housing interior and stacked on top of the acoustic integrated circuit, wherein the sensor die comprises a pressure sensor and a one-time programmable memory, wherein the pressure sensor carried by the sensor die is calibrated after the sensor die is integrated into the microphone device and calibration information of the pressure sensor is stored in the one-time programmable memory.2. The microphone device of claim 1 , wherein the acoustic integrated circuit is disposed in the housing interior and attached to the substrate claim 1 , and wherein a back surface of the sensor die is attached to the acoustic integrated circuit through a low-pressure adhesive.3. The microphone device of claim 1 , wherein the acoustic integrated circuit is embedded in the substrate claim 1 , and wherein the microphone die is disposed at least partially over the acoustic integrated circuit.4. The microphone device of claim 1 , wherein the ...

METHOD AND APPARATUS FOR USING UNIVERSAL CAVITY WAFER IN WAFER LEVEL PACKAGING

An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer. 2. The electronics module assembly of wherein the dies in the at least one group of dies are interconnected to form an electronic module.3. The electronics module assembly of wherein the frontside cavity is bounded by a full thickness perimeter rim of the cavity wafer.4. The electronics module assembly of where the plurality of fillports are distributed throughout a fillport area that is an area corresponding to the frontside cavity.5. The electronics module assembly of wherein the cavity wafer is made of any rigid material that tolerates 230.degree. C. process temperature.6. The electronics module assembly of claim 4 , wherein a portion of the fillport area is further cut out and the frontside cavity extends to the space formed by cutting out the portion of the fillport area.7. An electronics module assembly claim 4 , comprising:a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports;at least one group of dies, where the dies are placed in the frontside cavity; andencapsulant that fills the frontside cavity and the fillports, wherein the encapsulant secures the position of the at least one group of dies relative to the cavity wafer,wherein a uniform layer of the encapsulant covers a backside of the cavity wafer.8. The electronics module ...

Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die

A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die. 1. A semiconductor device , comprising:a stepped substrate including a first surface, a first step level opposite the first surface, and a second step level offset from the first step level;a first semiconductor die disposed in an opening of the stepped substrate;a second semiconductor die disposed over the first step level;a first conductive via formed through the stepped substrate; anda third semiconductor die disposed over with the second step level and the second semiconductor die.2. The semiconductor device of claim 1 , further including:a first interconnect structure formed over the first surface of the stepped substrate and first semiconductor die; andan encapsulant deposited over the third semiconductor die, first step level, and second step level.3. The semiconductor device of claim 2 , wherein the encapsulant covers a side surface of the stepped substrate.4. The semiconductor device of claim 2 , further including a second interconnect structure formed over a surface of the encapsulant.5. The semiconductor device of claim 2 , further including a second ...

Embedded copper structure for microelectronics package

An electronic component and a method of manufacturing an electronic component, the method including surface mounting electronic components to a printed circuit board (PCB), applying a flip-chip die integrated circuit (IC) to the PCB and underfilling the flip-chip IC to secure the PCB. The method also includes sintering a copper block to the PCB, where the copper block is in thermal communication with the IC and acts as a thermal path for removing heat generated by the flip-chip IC.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a dielectric layer and a patterned conductive layer disposed in the dielectric layer. The dielectric layer has a first surface, a second surface opposite the first surface, and a third surface extended from the first surface to the second surface. The semiconductor device package also includes a first electronic component in direct contact with the first surface of the dielectric layer and a first connection structure disposed between the first electronic component and the patterned conductive layer. A method of manufacturing a semiconductor device package is also disclosed.

Semiconductor device packages with improved thermal management and related methods

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate. A heat sink may be located on a side of the uppermost semiconductor die opposite the substrate. A passivation material may be located between the uppermost semiconductor die and the heat sink.

Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die

A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

Solid state contactor with improved interconnect structure

A printed circuit board for selectively communicating power from a power source to a use has an input bus for receiving a power supply. A transistor is connected to the input bus and is positioned on one side of the input bus in a first direction. An output bus is connected to the transistor on an opposed side of the transistor relative to the input bus. The transistor is intermediate at the first input and output buses in the first dimension. A power supply system is also disclosed.

Module ic package structure with electrical shielding function and method for manufacturing the same

A module IC package structure includes a substrate unit, an electronic unit, a package unit and a shielding unit. The substrate unit including a circuit substrate, a grounding layer disposed inside the circuit substrate, and an outer conductive structure disposed on the outer surrounding peripheral surface of the circuit substrate. The outer conductive structure includes a plurality of outer conductive layers. The grounding layer is exposed from the circuit substrate for directly contacting the outer conductive layers. The electronic unit includes a plurality of electronic components disposed on the circuit substrate. The package unit includes a package gel body disposed on the circuit substrate to enclose the electronic components. The shielding unit includes a metal shielding layer enclosing the package gel body and directly contacting the outer conductive structure. Whereby, the grounding layer is electrically connected to the metal shielding layer through the outer conductive structure directly.

PACKAGE STACK STRUCTURE

A package stack structure is provided, including a first substrate, a second substrate stacked on the first substrate, and an encapsulant formed between the first substrate and the second substrate. A through hole is formed to penetrate the second substrate and allow the encapsulant to be filled therein, thereby increasing the contact area and hence strengthening the bonding between the encapsulant and the second substrate. 1: A package stack structure , comprising:a first substrate;an electronic component disposed on and electrically connected to the first substrate;a second substrate having opposite first and second surfaces and at least one through hole communicating the first and second surfaces, wherein the first surface of the second substrate is stacked on the first substrate through a plurality of conductive elements, and wherein the through hole is positioned at a corner of a projection area of the electronic component on the second substrate; andan encapsulant formed between the second substrate and the first substrate and in the through hole.2: The package stack structure of claim 1 , wherein the through hole has a width not greater than 50 μm.3: The package stack structure of claim 2 , wherein the width of the through hole is between 10 μm and 25 μm.4: The package stack structure of claim 1 , further comprising a plurality of insulating layers formed on the first and second surfaces of the second substrate.5: The package stack structure of claim 4 , wherein the through hole penetrates through the insulating layers.6: The package stack structure of claim 4 , wherein at least one of the insulating layers has an opening communicating with the through hole.7: The package stack structure of claim 6 , wherein the opening is greater in width than the through hole.8: The package stack structure of claim 6 , wherein the opening has a width not greater than 100 μm.9: The package stack structure of claim 6 , wherein at least one of the through hole and the opening ...

Semiconductor device and method of manufacturing the same

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings. The plurality of first wirings connect the plurality of first electrodes, and the plurality of second wirings connect the plurality of second electrodes.

Electronic device, package, electronic apparatus, and moving object

A physical quantity sensor includes an IC chip and a package base mounted with the IC chip. The package base includes a first wiring layer provided with bonding pads connected to the IC chip via a bonding wire, a second wiring layer overlapping the first wiring layer in plan view, and an insulating layer provided between the first wiring layer and the second wiring layer. A contour of a wiring pattern provided on the second wiring layer (of the second wiring layer) is arranged in a position not overlapping the bonding pads in plan view.

SEMICONDUCTOR PACKAGE USING A POLYMER SUBSTRATE

A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure. 1. A semiconductor device comprising:a polymer substrate comprising first metal traces on a first surface of the polymer substrate;a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to the first surface, the semiconductor die electrically coupled to at least one of the first metal traces;a polymer cavity substrate coupled to the first surface of the polymer substrate and encircling the MEMS device and the semiconductor die, the polymer cavity substrate comprising second metal traces electrically coupled to at least a subset of the first metal traces; anda third substrate coupled to the cavity substrate and comprising third metal traces coupled to the second metal traces.2. The semiconductor device according to claim 1 , comprising a ground trace on an outer surface of the polymer cavity substrate.3. The semiconductor device according to claim 1 , comprising ball lands on a surface of the third substrate opposite to a surface with the third metal traces.4. The semiconductor device according to claim 1 , wherein the second metal traces extend from the first metal traces up a sidewall of the polymer cavity substrate and to ...

System and method for a mems transducer

An embodiment as described herein includes a microelectromechanical system (MEMS) with a first MEMS transducer element, a second MEMS transducer element, and a semiconductor substrate. The first and second MEMS transducer elements are disposed at a top surface of the semiconductor substrate and the semiconductor substrate includes a shared cavity acoustically coupled to the first and second MEMS transducer elements.

Semiconductor device packages with direct electrical connections and related methods

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate.

Semiconductor Device and Method of Forming a 3D Interposer System-In-Package Module

A semiconductor device has a first substrate. A first semiconductor component and second semiconductor component are disposed on the first substrate. In some embodiments, a recess is formed in the first substrate, and the first semiconductor component is disposed on the recess of the first substrate. A second substrate has an opening formed through the second substrate. A third semiconductor component is disposed on the second substrate. The second substrate is disposed over the first substrate and second semiconductor component. The first semiconductor component extends through the opening. An encapsulant is deposited over the first substrate and second substrate. 1. A method of making a semiconductor device , comprising:providing a first substrate;disposing a first semiconductor component and second semiconductor component on the first substrate;providing a second substrate;forming an opening through the second substrate;disposing a third semiconductor component on the second substrate;disposing the second substrate over the first substrate and second semiconductor component, wherein the first semiconductor component extends through the opening; anddepositing an encapsulant over the first substrate and second substrate.2. The method of claim 1 , further including:forming a recess in the first substrate; anddisposing the first semiconductor component in the recess of the first substrate.3. The method of claim 1 , wherein the first semiconductor component is an inductor.4. The method of claim 1 , further including disposing a copper-core solder ball (CCSB) between the first substrate and second substrate.5. The method of claim 1 , further including forming a shielding layer over the encapsulant.6. The method of claim 5 , further including coupling the shielding layer to a conductive trace of the first substrate or second substrate.7. A method of making a semiconductor device claim 5 , comprising:providing a first semiconductor component;providing a vertical ...

Pressure pulse wave sensor and biological information measurement device

A pressure pulse wave sensor includes: a sensor chip including: a pressure-sensitive element row configured by a plurality of pressure-sensitive elements arranged in one direction; and a chip-side terminal portion placed in an end portion in the one direction of a pressure-sensitive surface on which the pressure-sensitive element row is formed, and electrically connected to the pressure-sensitive element row; and a substrate including a concave portion, the sensor chip fixed to a bottom surface of the concave portion, a substrate-side terminal portion for being electrically connected to the chip-side terminal portion is disposed on a surface of the substrate in which the concave portion is formed, and the pressure pulse wave sensor further includes: an electroconductive member connecting the chip-side terminal portion and the substrate-side terminal portion to each other; and a protective member covering the electroconductive member.

Method of fabricating electronic package structure with multiple electronic components

An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure.

SEMICONDUCTOR CHIP MODULE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines. The redistribution pads includes shared redistribution pads electrically coupled in common to the redistribution lines electrically coupled to the bonding pads of the first semiconductor chip and the redistribution lines electrically coupled to the bonding pads of the second semiconductor chip; and individual redistribution pads individually electrically coupled to the redistribution lines which are not electrically coupled with the shared redistribution pads. 1. A semiconductor package comprising:a substrate including a top surface, a bottom surface, an opening which passes through the top surface and the bottom surface, and coupling pads formed over the bottom surface;a semiconductor chip module including a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned and a second surface which faces away from the first surface, a plurality of oblique redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads of the first and second semiconductor chips, and extending toward the scribe line region, ...

Methods for bonding substrates

Methods for fabricating and refurbishing an assembly are disclosed herein. The method begins by applying an adhesive layer onto a first substrate. A second substrate is placed onto the adhesive layer, thereby securing the two substrates together, the adhesive layer bounding at least one side of a channel that extends laterally between the substrates to an exterior of the assembly. And, the substrates and the adhesive layer are subjected to a bonding procedure and allowing outgassing of volatiles from the adhesive layer to escape from between the substrates through the channel, wherein the substrates bonded by the adhesive layer form a component for a semiconductor vacuum processing chamber.

Microphone with built-in speaker driver

A microphone package is integrated with a built-in speaker driver. A microphone application-specific integrated circuit (ASIC) and the speaker driver can be directly coupled to an external application processor, eliminating a need for a codec and thus, reducing the size, cost, and/or complexity of a device. In one aspect, the speaker driver and the microphone ASIC are implemented as separate dice mounted on the package substrate. In another aspect, the speaker driver and the microphone ASIC are implemented as stacked die on the package substrate. In yet another aspect, the speaker driver and the microphone ASIC are implemented as a single die on the package substrate.

ELECTRONIC ELEMENT MOUNTING SUBSTRATE AND ELECTRONIC DEVICE

An electronic element mounting substrate includes: a first wiring substrate configured to be a frame defining an interior portion as a first through-hole, the first wiring substrate including a lower surface including an external circuit connection electrode; a metal plate disposed on the lower surface of the first wiring substrate so as to cover an opening of the first through-hole, an outer edge thereof being located between an outer edge of the first wiring substrate and an inner edge of the first wiring substrate, an electronic element mounting portion being disposed in a region of an upper surface of the metal plate which region is surrounded by the first wiring substrate; and a second wiring substrate which is disposed in a peripheral region of the metal plate on the lower surface of the first wiring substrate and is electrically connected to the external circuit connection electrode. 1. An electronic element mounting substrate , comprising:a first wiring substrate configured to be a frame defining an interior portion as a first through-hole, the first wiring substrate comprising a lower surface comprising an external circuit connection electrode;a metal plate disposed on the lower surface of the first wiring substrate that covers an opening of the first through-hole, an outer edge thereof being located between an outer edge of the first wiring substrate and an inner edge of the first wiring substrate, an electronic element mounting portion being disposed in a region of an upper surface of the metal plate which region is surrounded by the first wiring substrate; anda second wiring substrate which is disposed in a peripheral region of the metal plate on the lower surface of the first wiring substrate and is electrically connected to the external circuit connection electrode.2. The electronic element mounting substrate according to claim 1 ,wherein a thickness in a vertical direction of the second wiring substrate is equal to a thickness in a vertical direction ...

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC APPARATUS

A semiconductor device includes a first substrate, a second substrate, a connection portion, and resin. The second substrate faces the first substrate, and has a recess at a position corresponding to an edge portion of the first substrate. The connection portion is interposed between the first substrate and the second substrate, and electrically connects the first substrate and the second substrate. Resin is disposed to remain between the first substrate and the second substrate, and covers the connection portion. Part of the resin is present in the recess of the second substrate. The recess serves as a resin reservoir for resin that is caused to flow upon bonding, and prevents the resin from flowing along a side surface of the first substrate to a back surface thereof, thereby preventing contamination by the resin. 1. A semiconductor device comprising:a first substrate;a second substrate facing the first substrate, and having a recess at a position corresponding to an edge portion of the first substrate;a connection portion interposed between the first substrate and the second substrate, and electrically connecting the first substrate and the second substrate; andresin disposed to remain between the first substrate and the second substrate, and covering the connection portion, part of the resin being present in the recess.2. The semiconductor device according to claim 1 , wherein the recess is provided at an edge portion of the second substrate.3. The semiconductor device according to claim 1 , wherein an inner wall surface and a bottom surface of the recess meet at a curved corner.4. The semiconductor device according to claim 1 , wherein a depth of the recess changes stepwise.5. The semiconductor device according to claim 1 , wherein a depth of the recess changes continuously.6. The semiconductor device according to claim 1 , wherein the recess extends to a side surface of the second substrate.7. The semiconductor device according to claim 1 , wherein the recess ...

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires. 1. A method of forming an integrated circuit (IC) package comprising:providing a first encapsulation layer having a first die and a plurality of electrical routing features at least partially embedded therein, the first die having a first plurality of die-level interconnect structures that are disposed at a first side of the first encapsulation layer, wherein the electrical routing features electrically couple the first side of the first encapsulation layer with a second side of the first encapsulation layer, and wherein the first side of the first encapsulation layer is disposed opposite the second side of the first encapsulation layer;coupling a second die with a second side of the first encapsulation layer, wherein the second die includes a second plurality of die-level interconnect structures;electrically coupling the second plurality of die-level interconnect structures with at least a subset of the plurality of electrical routing features by bonding wires; andforming a second encapsulation layer over the second die and the wire-bonding configuration to encapsulate at least a ...

Enhanced flip-chip die architecture

A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA).

Chip package and chip packaging method

A chip package and a chip packaging method are provided. A MEMS chip and an ASIC chip are packaged by using a packaged circuit board. The packaged circuit board is provided with a receiving hole. The MEMS chip and the ASIC chip are respectively attached to two surfaces of the packaged circuit board and cover receiving hole. The MEMS chip and the ASIC chip are connected with each other via the packaged circuit board, and are connected to an external circuit via the packaged circuit board, thereby facilitating a circuit interconnection between the package and an electronic component.

Semiconductor package using a polymer substrate

A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.

Microphone packaging for a portable communication device

A microphone packaging assembly ( 100 ) provides a printed circuit board (pcb) ( 106 ) for coupling to a microphone device ( 102 ) having a bottom acoustic port ( 104 ). The pcb provides an acoustic port opening ( 108 ) which aligns with the bottom acoustic port ( 104 ) of the microphone device ( 102 ). A solder pad pattern ( 110 ) is disposed on the pcb ( 106 ). The solder pad pattern ( 110 ) is configured to provide both electrical connection ( 114 ) and an incomplete solder seal ( 116 ) having purposeful acoustic leak to the microphone device ( 102 ). A conformable coating ( 126 ) provides a seal to the purposeful acoustic leak. A single acoustic test can be performed to detect proper environmental protection and acoustic sealing of the packaged assembly ( 100 ).

DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above. 117-. (canceled)18. A method of encapsulating a die into a semiconductor wafer assembly , the method comprising:etching a cavity into an oxide bonded semiconductor wafer stack;positioning a semiconductor die in the cavity;mechanically and electrically mounting the semiconductor die to the wafer stack; andencapsulating the semiconductor die within the cavity by bonding a lid wafer to the wafer stack.19. The method of claim 18 , wherein mechanically and electrically mounting the semiconductor die comprises a process selected from bump bonding claim 18 , wire interconnecting claim 18 , ultrasonic bonding claim 18 , and oxide bonding.20. The method of claim 18 , wherein bonding the lid wafer to the wafer stack further comprises:creating an oxide layer a first surface of the wafer stack;creating an oxide layer on a first surface of the lid wafer; andbonding the oxide layer of the first surface of the wafer stack to the oxide layer of the first surface of the lid wafer to create a wafer assembly and to form a hermetic seal around the cavity.21. The method of claim 18 , further comprising forming a conduit from the exterior of the wafer assembly through the lid wafer to the cavity.22. The method of claim 21 , further comprising delivering a sufficient amount of a ...

Fowbcsp chip module with packaging structure and manufacturing method of the same

A FOWBCSP chip module with a packaging structure has the following steps of: a chip having joints on an upper side thereof; a first packing structure enclosing a lower side and lateral sides of the chip; a substrate at the upper side of the chip; the substrate being formed with a plurality of penetrating through holes; and an upper side of the substrate being formed with a plurality of joints; and conductive wires passing through the through holes of the substrate to connect the joints of the substrate and the joints of the chip. Each of the through holes of the substrate is formed with a respective second packaging structure by filling gluing material to seal the through hole of the substrate and each of the joints on the upper side of the substrate is formed with a conductive ball, respectively. A method for forming the module is also included.

SEMICONDUCTOR DEVICE

A semiconductor device may include a first conductive plate, a plurality of semiconductor chips disposed on the first conductive plate, and a first external connection terminal connected to the first conductive plate. The plurality of semiconductor chips may include first, second, and third semiconductor chips. The second semiconductor chip may be located between the first semiconductor chip and the third semiconductor chip. A portion of the first conductive plate where the first external connection terminal is connected may be closest to the second semiconductor chip among the first, second, and third semiconductor chips. The first conductive plate may be provided with an aperture located between the portion of the first conductive plate where the first external connection terminal is connected and a portion of the first conductive plate where the second semiconductor chip is connected. 1. A semiconductor device comprising:a first conductive plate;a plurality of semiconductor chips disposed on the first conductive plate; anda first external connection terminal connected to the first conductive plate,whereinthe plurality of semiconductor chips comprises a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip,the second semiconductor chip is located between the first semiconductor chip and the third semiconductor chip,a portion of the first conductive plate where the first external connection terminal is connected is closest to the second semiconductor chip among the first, second, and third semiconductor chips, andthe first conductive plate comprises an aperture located between the portion of the first conductive plate where the first external connection terminal is connected and a portion of the first conductive plate where the second semiconductor chip is connected.2. The semiconductor device according to claim 1 , wherein the aperture is configured such that at least a part of a current flowing between the first external connection ...

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel. 1. A semiconductor device package , comprising:a supporting element;a plate disposed on the supporting element;a semiconductor device disposed under the plate; andwherein the supporting element and the plate define an opening exposed to outside of the semiconductor device package.2. The semiconductor device package of claim 1 , wherein the plate is a transparent plate.3. The semiconductor device package of claim 1 , further comprising an adhesive disposed between the supporting element and the plate and surrounding the semiconductor device claim 1 , wherein the adhesive has a gap.4. The semiconductor device package of claim 3 , wherein the supporting element has a first upper surface and the first portion has a second upper surface claim 3 , wherein the second upper surface of the first portion is lower than the first upper surface of the supporting element.5. The semiconductor device package of claim 1 , further comprising a lid disposed on the supporting element and surrounding the plate.6. The semiconductor device package of claim 5 , wherein the lid comprises a first portion covering a periphery of the plate.7. The semiconductor device package of claim 1 , wherein an opaque film is disposed on a surface of the plate.8. The semiconductor device package of claim 5 , wherein the supporting element claim 5 , the plate claim 5 , and the lid define the opening.9. The semiconductor device package of claim 1 , wherein the supporting element comprises a through via.10. The semiconductor device package of claim 1 , wherein the supporting element partially overlaps with the plate in a cross sectional perspective.11. A semiconductor device package claim 1 , comprising:a supporting element ...

ELECTRONIC PACKAGE AND SEMICONDUCTOR SUBSTRATE

A semiconductor substrate is provided, including a substrate body having a lateral surface, and a protruding structure extending outward from the lateral surface. The semiconductor substrate distributes stresses generated during a manufacturing process through the protruding structure, and is thus prevented from delamination or being cracked. An electronic package having the semiconductor substrate is also provided. 1. A semiconductor substrate , comprising:a substrate body having a first surface, a second surface, and at least one lateral surface adjacent the first surface and the second surface; andat least one protruding structure extending outward from the lateral surface of the substrate body and occupying a pre-scribing path surrounding the substrate body.2. The semiconductor substrate of claim 1 , wherein the substrate body has a plurality of the lateral surfaces.3. The semiconductor substrate of claim 2 , wherein the plurality of the lateral surfaces intersect to form a corner claim 2 , and the protruding structure is disposed on the corner.4. The semiconductor substrate of claim 1 , wherein the protruding structure is integrated with the substrate body.5. The semiconductor substrate of claim 1 , wherein the protruding structure has a contour composed of straight lines claim 1 , curved lines claim 1 , or a combination thereof.6. The semiconductor substrate of claim 1 , wherein the protruding structure comprises a neck portion connected to the lateral surface of the substrate body.7. The semiconductor substrate of claim 1 , wherein the protruding structure further comprises a head portion connected to the neck portion.8. An electronic package claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the semiconductor substrate according to ;'}an electronic component disposed on the semiconductor substrate; andan encapsulation layer formed on the semiconductor substrate and encapsulating the electronic component.9. The electronic package of claim ...

Edge Coated Ceramic Substrates for Electronic Device Components

An electrical component may be mounted on a substrate such as a ceramic substrate. Contacts may be formed on upper and lower surfaces of the substrate. The electrical component may be soldered to the contacts on the upper surface. The contacts on the lower surface may be used to solder the substrate to a printed circuit. During manufacturing, it may be desirable to use metal traces on a ceramic panel to make connections to contacts on the substrate. Following singulation of the ceramic panel to form the ceramic substrate, some of the metal traces may run to the edge of the ceramic substrate. A folded tab of the printed circuit may form a shield that covers these exposed traces. A divided metal-coated groove or a row of divided metal-coated vias running along each edge of the substrate may also provide shielding.

Semiconductor Device Package and Method of the Same

The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate. 1. A semiconductor device package , comprising:a substrate with electrical through-holes to inter-connect a first wiring circuit on a top surface of said substrate and a second wiring circuit on a bottom surface of said substrate, wherein a contact conductive bump is formed on said first wiring circuit;an adhesive layer on said top surface and said first wiring circuit of said substrate; anda die with a bump structure on the bonding pads of said die, wherein said bump structure of said die is electrically connected to said contact conductive bump of said first wiring circuit of said substrate.2. The package of claim 1 , wherein said adhesive layer is formed only under said die for adhering said die and said substrate.3. The package of claim 2 , further comprising a second contact conductive bump on said second wiring circuit.4. The package of claim 3 , wherein a material of said second contact conductive bump of said substrate includes solder bump or gold bump.5. The package of claim 1 , wherein a material of said bump structure of die includes stud bump claim 1 , solder bump or gold bump.6. The package of claim 2 , further comprising a cover layer on said top surface of said substrate and a bottom surface of said die.7. The package of claim 1 , further comprising a second substrate with a ...

Semiconductor Device and Method of Forming MEMS Package

A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die. 1. A method of making a semiconductor device , comprising:providing a substrate including a first opening formed through the substrate;disposing a first semiconductor die over the substrate and aligned with the first opening;disposing a second semiconductor die over the substrate adjacent to the first semiconductor die; anddisposing a lid over the first semiconductor die and second semiconductor die, wherein the lid includes a second opening formed through the lid.2. The method of claim 1 , wherein the first semiconductor die includes a microelectromechanical system (MEMS).3. The method of claim 2 , wherein the MEMS is responsive to sound entering the semiconductor device through the first opening and second opening.4. The method of claim 1 , further including coupling the first semiconductor die to the substrate using a bond wire.5. The method of claim 4 , wherein the second semiconductor die is flip chip mounted to the substrate.6. The method of claim 1 , further including forming ...

Semiconductor device package and method of manufacturing the same

The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.

Device Package with Reduced Radio Frequency Losses

A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness. 1. A device package comprising: a core layer for mechanically supporting the multilayer protective covering, the core layer comprising a first thickness less than 200 μm,', 'an electrically conductive layer disposed over a first surface of the core layer, the electrically conductive layer comprising a second thickness less than 20 μm, wherein the multilayer protective covering is indented to comprise a recessed region, wherein the core layer surrounds the recessed region,', 'a corrosion resistant layer disposed over the electrically conductive layer, and', 'a metal layer disposed over the corrosion resistant layer., 'a multilayer protective covering comprising'}2. The device package of claim 1 , wherein:the core layer comprises a first type of brass,the electrically conductive layer comprises a second type of brass,an electrical conductivity of the second type of brass is greater than an electrical conductivity of the first type of brass, andthe second thickness is less than about to 10 μm.3. The device package of claim 1 , wherein:the core layer comprises one of brass or nickel silver;the first thickness is about 100 μm;the electrically conductive layer comprises copper; andthe second thickness is between about 3 μm to 6 μm.4. The device package of ...

Mold cap for semiconductor device

A semiconductor package has a substrate with a solder mask layer, and upper and lower surfaces. Conductive traces and electrical contacts are formed on the substrate, and vias are formed in the substrate to electrically connect the conductive traces and electrical contacts. A semiconductor die is attached on the upper surface of the substrate. A mold cap is formed on the upper surface of the substrate and covers the die and the conductive traces. The mold cap includes a mold body having clipped corners and extensions that extend from each of the clipped corners. The extensions and clipped corners help prevent package cracking.

Power electronics assemblies and vehicles incorporating the same

A power electronics assembly includes a semiconductor device, a metal substrate, and a cooling structure. The metal substrate includes a plurality of stress-relief features that extend at least partially through a thickness of the metal substrate. The plurality of stress-relief features are at least partially filled with a transient liquid phase (TLP) bonding material. The semiconductor device is positioned over the plurality of stress-relief features and thermally bonded to the metal substrate via TLP bonding material. Vehicles having power electronics assemblies with stress-relief through-features are also disclosed.

Mems assembly

A MEMS assembly includes a housing having an internal volume V, wherein the housing has a sound opening to the internal volume V, a MEMS component in the housing adjacent to the sound opening, and a layer element arranged at least regionally at a surface region of the housing that faces the internal volume V, wherein the layer element includes a layer material having a lower thermal conductivity and a higher heat capacity than the housing material of the housing that adjoins the layer element.

Microelectronic package having a passive microelectronic device disposed within a package body

A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Substrate Design for Semiconductor Packages and Method of Forming Same

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity. 1. A device comprising: a metal-clad insulated base material core, the metal-clad insulated base material core having a topmost surface and a bottommost surface opposite the topmost surface; and', 'a cavity extending through the metal-clad insulated base material core;, 'a package substrate, wherein the package substrate comprisesa first die at least partially within the cavity; anda first plurality of connectors in the cavity, the first plurality of connectors coupling the first die to the package substrate, the first plurality of connectors extending below the topmost surface of the metal-clad insulated base material core toward a bottommost surface of the cavity, the first plurality of connectors directly contacting the bottommost surface of the cavity.2. The device of claim 1 , further comprising a second die attached to the package substrate claim 1 , the package substrate being interposed between the first die and the second die.3. The device of claim 2 , further comprising a second plurality of connectors electrically coupling the second die to the package substrate.4. The device of claim 3 , further comprising one or more redistribution layers (RDLs) interposed between the second die and the second plurality of connectors.5. The device of claim 2 , further comprising a heat dissipation feature on a surface of the second die claim 2 , the second die being interposed between the heat dissipation feature and the package substrate.6. The device of claim 2 , ...

NON-ROUGHENED CU TRACE WITH ANCHORING TO REDUCE INSERTION LOSS OF HIGH SPEED IO ROUTING IN PACKAGE SUBSTRATE

Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a trace disposed on a conductive layer. The semiconductor package has one or more adhesion anchoring points and a plurality of portions on the trace. An adhesion anchoring point is between two portions on the trace. A surface roughness of an adhesion anchoring point is greater than a surface roughness of a portion on the trace. The trace may be a high-speed input/output (HSIO) trace. The semiconductor package may include via pads disposed on each end of the trace, and a dielectric disposed on the trace. The dielectric is patterned to form openings on the dielectric that expose second portions on the trace. The dielectric remains over the portions. The semiconductor package may have a chemical treatment disposed on the exposed openings on the trace to form the adhesion anchoring points. 1. A semiconductor package , comprising:a trace on a conductive layer;one or more adhesion anchoring points on the trace; anda plurality of portions on the trace, wherein one of the adhesion anchoring points is disposed between two of the portions, and wherein a surface roughness of an adhesion anchoring point is greater than a surface roughness of a portion.2. The semiconductor package of claim 1 , wherein trace is a high-speed input/output (HSIO) trace.3. The semiconductor package of claim 1 , wherein the conductive layer is disposed on an underlying layer of a substrate claim 1 , and wherein the conductive layer further includes a plane and a second trace.4. The semiconductor package of claim 1 , further comprising:one or more via pads disposed on each end of the trace;a dielectric disposed on the trace, wherein the dielectric is patterned on the plurality of portions of the trace; andone or more openings on the dielectric are patterned to expose one or more second portions on the trace, wherein the dielectric only covers the plurality of portions on the ...

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires. 1. A semiconductor package , comprising:a first die having an active side and a backside opposite the active side, the active side having a plurality of die level interconnects thereon;a redistribution layer having a die side and a package level interconnect side, the die side coupled to the active side of the first die, and the package level interconnect side coupled to a plurality of package level interconnects;a first via bar laterally adjacent to and spaced apart from a first edge of the first die, the first via bar coupled to the redistribution layer;a second via bar laterally adjacent to and spaced apart from a second edge of the first die opposite the first edge of the first die, the second via bar coupled to the redistribution layer;a first encapsulation layer laterally surrounding the first die;a second die above the first die, the second die having an active side and a backside opposite the active side, the active side of the second die having a plurality of die level interconnects thereon, the backside of the second die facing the backside of the first die;a third die above ...

TFD I/O Partition for High-Speed, High-Density Applications

A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.

SYSTEM-IN-PACKAGE MODULE WITH MEMORY

A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate. 1. A system-in-package (SIP) module with memory , the SIP module comprising:a cache memory;a memory controller;a memory; anda substrate, wherein the cache memory, the memory controller, and the memory are co-packaged over the substrate, and the cache memory and the memory controller are formed on a same semiconductor chip;wherein the memory controller accesses the memory and the cache memory through a first reconfigurable bus, transmits data to an external circuit or receives data from the external circuit through a second reconfigurable bus, and the memory controller is capable of dynamically changing at least one of a first swing voltage of the first reconfigurable bus and a second swing voltage of the second reconfigurable bus.2. The SIP module of claim 1 , wherein the cache memory claim 1 , the memory controller claim 1 , and the memory are installed on the substrate respectively claim 1 , or are installed on the substrate after the cache memory claim 1 , the memory controller claim 1 , and the memory are stacked together.3. The SIP module of claim 2 , wherein the same semiconductor chip is a Si Chip made according to a complementary metal-oxide-semiconductor (CMOS) process.4. The SIP module of claim 1 , wherein the cache memory is a static random access memory (SRAM) or a dynamic random access memory (DRAM) claim 1 , and the memory is a DRAM claim 1 , or a plurality of DRAMs stacked together claim 1 , and an operation speed or a band width of the cache memory is greater than an ...

STACKED WAFER-LEVEL PACKAGING DEVICES

Stacked wafer-level packaging devices. In some embodiments, a wireless device includes a transceiver configured to generate a radio-frequency (RF) signal. The wireless device also includes a front-end module (FEM) in communication with the transceiver, the front-end module including a packaging substrate configured to receive a plurality of components, the front-end module further including a stacked assembly implemented on the packaging substrate, the stacked assembly including a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield, the stacked assembly further including a second wafer-level packaging device having an RF shield, the second wafer-level packaging device positioned over the first wafer-level packaging device such that the RF shield of the second wafer-level packaging device is electrically connected to the RF shield of the first wafer-level packaging device. The wireless devices further includes an antenna in communication with the front-end module, the antenna configured to transmit the amplified radio-frequency signal. 1. A wireless device comprising:a transceiver configured to generate a radio-frequency (RF) signal;a front-end module (FEM) in communication with the transceiver, the front-end module including a packaging substrate configured to receive a plurality of components, the front-end module further including a stacked assembly implemented on the packaging substrate, the stacked assembly including a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield, the stacked assembly further including a second wafer-level packaging device having an RF shield, the second wafer-level packaging device positioned over the first wafer-level packaging device such that the RF shield of the second wafer-level packaging device is electrically connected to the RF shield of the first wafer-level packaging device; andan antenna in communication with the front-end module, the antenna configured to transmit the ...

Shielded package assemblies with integrated capacitor

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Chip on film package

A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a first conductive film. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed in the mounting region and electrically connected to the patterned circuit layer. The first conductive film covers at least a part of the first solder resist layer and an opening exposing at least a part of the patterned circuit layer, wherein the first conductive film is configured to shield electromagnetic interference (EMI) emanating by the chip and is electrically connected to the patterned circuit layer.

Semiconductor Device and Method of Forming MEMS Package

A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die. 1. A semiconductor device , comprising:a first semiconductor die;a modular interconnect unit disposed adjacent to the first semiconductor die;an encapsulant deposited over the first semiconductor die and modular interconnect unit;a build-up interconnect structure formed over the first semiconductor die, modular interconnect unit, and encapsulant; anda second semiconductor die comprising a microelectromechanical system disposed over the build-up interconnect structure.2. The semiconductor device of claim 1 , further including an opening formed in the build-up interconnect structure over the second semiconductor die.3. The semiconductor device of claim 1 , further including a lid disposed over the second semiconductor die.4. The semiconductor device of claim 3 , further including an opening formed in the lid.5. The semiconductor device of claim 1 , further including a cavity formed in the second semiconductor die.6. The semiconductor device of claim 1 , wherein the second semiconductor ...

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

DOUBLE-SIDED HERMETIC MULTICHIP MODULE

A packaged electronic module for downhole applications, in particular in a petrochemical well or similar environment. The electronic module includes one or more electronic components located on each side of a substrate, where the one or more electronic components are attached to the substrate by means of glue. 1. A packaged electronic module for downhole applications in a borehole , comprising:{'b': '5', 'claim-text': discrete electronic components;', 'surface mounted components;', 'die components;', 'semiconductor ICs; or', 'semiconductor chips., 'a plurality of electronic components, wherein at least one of the plurality of electronic components is located on each of the first and second surfaces, and wherein the plurality of electronic components are attached to the first and second surfaces of the substrate by an adhesive and at least one of the electronic components comprises a multi-chip module and includes one or more of, 'a substrate comprising a first and a second surface; and'}2. The packaged electronic module according to claim 1 , wherein the adhesive does not comprise solder.3. The packaged electronic module according to claim 1 , wherein the substrate comprises a ceramic material or a high temperature co-fired ceramic.4. The packaged electronic module according to claim 1 , further comprising:{'b': '30', 'metallic or ceramic rings disposed on each of the first and second surfaces, wherein the metallic or ceramic rings extend outward from the first and second surfaces and completely surround the one or more of the electronic components disposed thereon; and'}a pair of lids, where each of the pair of lids is coupled with a one of the metallic or ceramic rings and configured to cover the one or more electronic components surrounded by the metallic or ceramic rings.5. The packaged electronic module according to claim 4 , wherein the metallic rings comprise kovar.6. The packaged electronic module according to claim 4 , wherein the each of the pair of lids ...

Semiconductor device and semiconductor device fabrication method

A semiconductor device fabrication method, including preparing a case having a plurality of connection terminals, and fitting a jig onto the case to protect the connection terminals, tips of the connection terminals protruding from the jig. The method further includes fitting a printed circuit board on the tips of the connection terminals protruding from the jig.

Underfill method and apparatus for semiconductor package

Disclosed are an underfill method and apparatus for a semiconductor package, the underfill method includes loading a substrate; charging a filler to be filled in between the substrate and a device; applying the filler to the substrate; and subjecting the applied filler to an electric field.

Bga package substrate and method of manufacturing the same

A BGA package substrate includes a substrate, a resist formed over the substrate and includes an opening, a land formed over the substrate in the opening, and a solder ball fused to the land, wherein the resist includes a notch at an edge of the opening through which the land is exposed, the notch having a bottom at a position lower than a surface of the land.

Electrolyte for a solid-state battery

Electrolyte for a solid-state battery includes a body having grains of inorganic material sintered to one another, where the grains include lithium. The body is thin, has little porosity by volume, and has high ionic conductivity.

HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE

Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads. 1. (canceled)2. A method of making a device , the method comprising:situating a first die on or at least partially in a substrate, the first die including a first high density interconnect pad and a first low density interconnect pad, the substrate including low density interconnect circuitry therein, the first low density interconnect pad electrically coupled to the low density interconnect circuitry;situating a second die on or at least partially in the substrate, the second die including a second high density interconnect pad and a second low density interconnect pad, the first low density interconnect pad electrically coupled to the low density interconnect circuitry; andembedding a high density interconnect element in the substrate, the high density interconnect element including third high density interconnect pads on a side facing the first die and a trace, a first interconnect pad of the third high density interconnect pads electrically coupled to the first high density interconnect pad and a second interconnect pad of the third high density interconnect pads electrically coupled to the second high density interconnect pad, the trace electrically coupling the first ...