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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1527. Отображено 100.
15-03-2012 дата публикации

Semiconductor chip device with polymeric filler trench

Номер: US20120061852A1
Автор: Bryan Black, Gamal Refai-Ahmed, Michael Z. Su
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

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Номер записи: 1
03-05-2012 дата публикации

Semiconductor package and manufacturing method thereof

Номер: US20120104571A1
Автор: Jin O. YOO
Принадлежит: Samsung Electro Mechanics Co Ltd

There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes.

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Номер записи: 2
27-09-2012 дата публикации

Semiconductor Device and Method of Forming a Thermally Reinforced Semiconductor Die

Номер: US20120241941A1
Автор: KyungHoon Lee, OhHan Kim, YongHee Kang
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM.

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Номер записи: 3
27-09-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120241942A1
Автор: Takumi Ihara
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

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Номер записи: 4
25-10-2012 дата публикации

Sealed electronic housing and method for the sealed assembly of such a housing

Номер: US20120266462A1
Автор: Claude Drevon, Olivier Vendier, Walim Ben Naceur
Принадлежит: Thales SA

Method for the sealed assembly of an electronic housing containing one or more electronic components, the method including: assembling the housing by bringing a support, to which the electronic components are fixed, in contact with a cover by means of a mixture including a paste and nanoparticles in suspension in said paste, the size of the nanoparticles ranging from 10 to 30 nm; and closing the housing in a sealed manner by heating the housing to a temperature T of between 150° C. and 180° C. making it possible to sinter the metal nanoparticles, while subjecting the housing to a pressure greater than 2.5×10 5 Pa.

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Номер записи: 5
26-09-2013 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20130249084A1
Автор: Naoki Fujimoto, Tatsuya Usami, Tomoyuki Nakamura
Принадлежит: Renesas Electronics Corp

A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH 3 near a wave number 1270 cm −1 to a peak height of Si—O near a wave number 1030 cm −1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH 2 —Si near a wave number 1360 cm −1 to the peak height of Si—CH 3 near the wave number 1270 cm −1 is 0.031 or greater.

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Номер записи: 6
03-10-2013 дата публикации

Wiring substrate and method of manufacturing the same

Номер: US20130256012A1
Автор: Kotaro Kodani
Принадлежит: Shinko Electric Industries Co Ltd

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.

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Номер записи: 7
03-01-2019 дата публикации

Heat Spreading Device and Method

Номер: US20190006263A1
Автор: Chen-Hua Yu, Ming-Fa Chen, Tsung-Yu Chen, Wensen Hung
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

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Номер записи: 8
03-01-2019 дата публикации

Platform with thermally stable wireless interconnects

Номер: US20190006298A1
Автор: Adel A. Elsherbini, Brandon M. Rawlings, Feras Eid, Georgios C. Dogiamis, Sasha N. OSTER, Telesphor Kamgaing
Принадлежит: Intel Corp

Embodiments of the invention may include a packaged device that includes thermally stable radio frequency integrated circuits (RFICs). In one embodiment the packaged device may include an integrated circuit chip mounted to a package substrate. According to an embodiment, the package substrate may have conductive lines that communicatively couple the integrated circuit chip to one or more external components. One of the external components may be an RFIC module. The RFIC module may comprise an RFIC and an antenna. Additional embodiments may also include a packaged device that includes a plurality of cooling spots formed into the package substrate. In an embodiment the cooling spots may be formed proximate to interconnect lines the communicatively couple the integrated circuit chip to the RFIC.

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Номер записи: 9
12-01-2017 дата публикации

Electronic apparatus and method for fabricating the same

Номер: US20170012013A1
Автор: Kozo Shimizu, Seiki Sakuyama
Принадлежит: Fujitsu Ltd

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

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Номер записи: 10
11-01-2018 дата публикации

Thermal transfer structures for semiconductor die assemblies

Номер: US20180012865A1
Автор: Ed A. Schrock
Принадлежит: Micron Technology Inc

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.

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Номер записи: 11
14-01-2021 дата публикации

Electronic module and electronic device

Номер: US20210013178A1
Автор: Daijiro Ishibashi, Shinya Sasaki, Teru Nakanishi, Yoshihiro Nakata, Yukiko Oshikubo
Принадлежит: Fujitsu Ltd

An electronic module includes: a plurality of heat generating members provided over a first surface of a board; a frame joined to the first surface of the board and provided between the plurality of heat generating members that are arranged; and a lid configured to cover the first surface of the board and thermally coupled to each of the plurality of heat generating members, the frame being a grid-shaped frame or a mesh-shaped frame.

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Номер записи: 12
09-01-2020 дата публикации

Substrate design for semiconductor packages and method of forming same

Номер: US20200013635A1
Автор: Chen-Hua Yu, Chien-Hsiun Lee, Jung Wei Cheng, Mirng-Ji Lii, Tsung-Ding Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

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Номер записи: 13
21-01-2016 дата публикации

Radio frequency shielding cavity package

Номер: US20160020177A1
Автор: Ming-Wa TAM
Принадлежит: UBOTIC Co Ltd

A radio-frequency shielding cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the radio-frequency shielding cavity package comprises a metallic leadframe and plastic molded body. The leadframe has a plurality of contact pads extending from top to bottom surfaces thereof, at least one contact pad on the top surface being surrounded by metal for shielding the contact pad from external electric fields. A plated inner ring surrounds a die attach pad on the leadframe. The die attach pad receives a semiconductor die adapted to be wire bonded to the inner ring and plurality of contact pads. A plated outer ring defines a ground plane circumscribing the perimeter of the leadframe. A cap is connected to the ground plane for enclosing and protecting the wire bonded semiconductor device die and providing electrical grounding thereof.

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Номер записи: 14
10-02-2022 дата публикации

Heat dissipation device having anisotropic thermally conductive sections and isotropic thermally conductive sections

Номер: US20220042750A1
Автор: Adel Elsherbini, Feras Eid, Johanna Swan
Принадлежит: Intel Corp

A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device. The isotropic thermally conductive section(s) allows heat spreading/removal from hotspots or areas with high-power density and the anisotropic thermally conductive section(s) transfers heat away from the at least one integrated circuit device predominately in a single direction with minimum conduction resistance in areas with uniform power density distribution, while reducing heat transfer in the other directions, thereby reducing thermal cross-talk.

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Номер записи: 15
25-01-2018 дата публикации

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Номер: US20180026015A1
Автор: Chandolu Anilkumar
Принадлежит:

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a dielectric material over the substrate;a conductive trace extending at least partially through the dielectric material; and a conductive member coupled to the conductive trace, and', 'a conductive bond material bonded to the conductive member,, 'a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—'}wherein all of the redundant electrical connectors are coupled to the conductive trace.2. The semiconductor device of wherein the dielectric includes a plurality of openings exposing portions of the conductive trace claim 1 , wherein the redundant electrical connectors are formed in the openings.3. The semiconductor device of wherein the conductive member comprises copper and the bond material comprises a solder material.4. The semiconductor device of wherein the conductive member includes an end portion claim 1 , and wherein the conductive bond material and conductive member form a conductive joint at the end portion.5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate claim 1 , ...

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Номер записи: 16
23-01-2020 дата публикации

DYNAMIC RANDOM ACCESS MEMORY (DRAM) MOUNTS

Номер: US20200027867A1
Автор: Goh Eng Huat, Teoh Hoay Tien
Принадлежит:

Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM. 1. (canceled).2. A circuit package , comprising:a first memory device situated to a first side of a processor in parallel to the processor and mounted on a package board of a processor assembly; anda second memory device situated to a second side of the processor in parallel to the processor and mounted on the package board of the processor assembly.3. The circuit package of claim 2 , wherein the first memory device and the second memory device are donut-shaped.4. The circuit package of further comprising a heat spreader mounted on top of the processor and extending past a first outer edge along the first side past the first memory device and the heat spreader extending past a second outer edge along the second side past the second memory device.5. The circuit package of further comprising claim 2 , at least one additional first memory device stacked on top of the first memory device.6. The circuit package of further comprising claim 5 , at least one additional second memory device stacked on top of the second memory device.7. The circuit package of claim 6 , wherein the at least one additional first memory device claim 6 , the first memory device claim 6 , the at least one additional second memory device claim 6 , and the second memory device have heights that are less than a processor height for the processor on the packaging board of the processor assembly.8. The circuit package of claim 7 , wherein a first outer edge of the first memory device overhangs beyond a first side edge of the packaging board claim 7 , and wherein a second outer edge of the second memory device overhangs beyond a second side edge of the packaging board.9. The circuit ...

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Номер записи: 17
04-02-2016 дата публикации

High-frequency component and high-frequency module including the same

Номер: US20160037640A1
Автор: Hidenori OBIYA, Kiyofumi Takai, Shinya HITOMI
Принадлежит: Murata Manufacturing Co Ltd

In a method for mounting a filter circuit component to obtain desired frequency characteristics of the filter circuit component without receiving the influence of a parasitic inductance and a parasitic capacitance, and to increase the packing density of components, since the ground terminal of the filter circuit component connected to the mounting electrode is connected to the ground electrode through the via conductors at the shortest distance, the occurrence of an unnecessary parasitic inductance and an unnecessary parasitic capacitance is prevented. The filter circuit component is mounted on the high-frequency component to obtain the desired frequency characteristics of the filter circuit component without the influence of a parasitic inductance and a parasitic capacitance. Since the component is located in a space surrounded by the inner peripheral surface of the supporting frame body, the packing density of components is increased.

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Номер записи: 18
04-02-2021 дата публикации

Combination stiffener and capacitor

Номер: US20210035738A1
Автор: Eng Huat Goh, Jiun Hann Sir, Min Suet LIM
Принадлежит: Intel Corp

Electronic device package stiffener and capacitor technology is disclosed. A combination stiffener and capacitor can include a structural material configured to be coupled to a substrate. The structural material can have a shape configured to provide mechanical support for the substrate. The combination stiffener and capacitor can also include first and second electrodes forming a capacitor. An electronic device package and a package substrate configured to receive the combination stiffener and capacitor are also disclosed.

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Номер записи: 19
08-02-2018 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20180040598A1
Автор: Deguchi Yoshinori, Hasebe Akio, Kubo Mitsuyuki, Makihira Naohiro, Takei Fumikazu, YASUMURA Bunji
Принадлежит:

To improve the assemblability of a semiconductor device. 120-. (canceled)21. A method for manufacturing a semiconductor device , comprising the steps of:(a) mounting a first semiconductor chip over a second semiconductor chip such that a first surface of the first semiconductor chip faces to a second surface of the second semiconductor chip,wherein the second semiconductor chip includes a plurality of electrode pads and a recognition mark arranged on the second surface, and a plurality of through electrodes electrically coupled with the electrode pads respectively, andwherein the first semiconductor chip includes a plurality of projection electrodes arranged on the first surface, (a1) recognizing the recognition mark;', '(a2) performing alignment of the first semiconductor chip and the second semiconductor chip based on a result of having recognized the recognition mark; and', '(a3) mounting the first semiconductor chip over the second semiconductor chip, and electrically coupling the electrode pads of the second semiconductor chip and the projection electrodes of the first semiconductor chip respectively,, 'the (a) step including the steps of(b) before the (a) step, forming the through electrodes such that the through electrodes are formed penetrating a silicon base portion of the first semiconductor chip, and(c) after the (b) step, forming the recognition mark on the second surface such that the recognition mark is electrically separated from the through electrodes and not overlapped with the through electrodes in plan view.22. The method for manufacturing the semiconductor device according to claim 21 , further comprising the steps of:(d) after the (b) step and before the (c) step, forming the electrode pads on the through electrodes such that the electrode pads are electrically coupled with the through electrodes respectively; andwherein, in the (c) step, the recognition mark is formed by plating.23. The method for manufacturing the semiconductor device ...

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Номер записи: 20
18-02-2021 дата публикации

Semiconductor package structure and manufacturing method thereof

Номер: US20210050296A1
Автор: Hung-Hsin Hsu, Nan-Chun Lin, Pei-Chun Tsai, Shang-Yu Chang Chien
Принадлежит: Powertech Technology Inc

A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

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Номер записи: 21
18-02-2016 дата публикации

Module Arrangement For Power Semiconductor Devices

Номер: US20160049342A1
Автор: Hamit Duran, Munaf Rahimo
Принадлежит: ABB TECHNOLOGY AG

A module arrangement for power semiconductor devices, including one or more power semiconductor modules, wherein the one or more power semiconductor modules include a substrate with a first surface and a second surface being arranged opposite to the first surface, wherein the substrate is at least partially electrically insulating, wherein a conductive structure is arranged at the first surface of the substrate, wherein at least one power semiconductor device is arranged on the conductive structure and electrically connected thereto, wherein the one or more modules includes an inner volume for receiving the at least one power semiconductor device which volume is hermetically sealed from its surrounding by a module enclosure, wherein the module arrangement includes an arrangement enclosure at least partly defining a volume for receiving the one or more modules, and wherein the arrangement enclosure seals covers the volume.

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Номер записи: 22
15-02-2018 дата публикации

LIMITING ELECTRONIC PACKAGE WARPAGE

Номер: US20180047590A1
Автор: LI SHIDONG
Принадлежит:

An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be electrically connected to a system board. The semiconductor chip is electrically connected to the top surface. The lid is attached to the top surface enclosing semiconductor chip and includes a perimeter recess. The lid-ring is juxtaposed within the perimeter recess. The lid-ring exerts a reverse bending moment upon the lid to limit warpage of the electronic package. 1. A electronic package comprising:a carrier comprising a top surface and a bottom surface configured to be electrically connected to a system board;a semiconductor chip electrically connected to the top surface of the carrier;a lid attached to the top surface of the carrier that encloses semiconductor chip, the lid comprising a perimeter recess within the upper half of the lid, the perimeter recess comprising a horizontal recess and vertical recess comprising two recess sidewalls; anda lid-ring attached to the lid within the perimeter recess, the lid ring comprising a horizontal portion orthogonal and distally connected to a vertical portion, wherein the horizontal portion comprises a greater width than height, is parallel with the semiconductor chip, and is juxtaposed within the horizontal recess, wherein the vertical portion comprises a greater height than width and is juxtaposed between the two vertical recess sidewalls, wherein a perimeter sidewall of the lid-ring horizontal portion is coplanar with a perimeter sidewall of the lid, and wherein the lid-ring applies a contracting force against the upper half of the lid to exert a reverse bending moment upon the lid.2. The electronic package of claim 1 , wherein the lid is in thermal contact with the semiconductor chip.3. The electronic package of claim 1 , wherein a top surface of the lid and a top surface the lid-ring are coplanar.4. The electronic package of claim 1 , wherein the lid and the ...

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Номер записи: 23
15-02-2018 дата публикации

THERMAL INTERFACE MATERIAL ON PACKAGE

Номер: US20180047655A1
Автор: DE SOUSA Isabel, LAVOIE Annique, Salvas Eric, TURGEON Michel
Принадлежит:

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. 1. A method , comprising:dispensing a thermal interface material (TIM) on an electronic assembly;placing a lid on the TIM, over the electronic assembly;pressing the lid onto the electronic assembly to perform a packaged assembly;curing the packaged assembly; andperforming a sonoscan of the packaged assembly to determine a presence of voiding in the TIM.2. The method of claim 1 , further comprising removing volatile species of the TIM prior to lid placement.3. The method of claim 2 , wherein the volatile species comprises cyclic siloxanes and decyl trimethoxysilane.4. The method of claim 2 , wherein the removal of the volatile species comprises maintaining the TIM at room temperature for a predetermined time period prior to the lid placement.5. The method of claim 4 , wherein the predetermined time period is about 60 minutes.6. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a predetermined temperature claim 2 , in an oven claim 2 , for a predetermined time period.7. The method of claim 6 , wherein the predetermined temperature is about 45° C. to 55° C. and the predetermined time period is about 15-30 minutes.8. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 20 minutes.9. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 15 minutes.10. The method of claim 2 , wherein the removal ...

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Номер записи: 24
15-02-2018 дата публикации

Electronic Component Package Structure and Electronic Device

Номер: US20180049351A1
Автор: Bai Yadong, Yang Lin, Yu Xuequan
Принадлежит:

An electronic component package structure and an electronic device where the electronic component package structure includes at least a substrate having a set attachment area for attaching an electronic component; a conductive lid having a top and a sidewall that extends toward the substrate, where one side of the sidewall close to the substrate has a bonding end, where the bonding end bonds the conductive lid to the substrate by using a non-conductive adhesive, and the conductive lid bonded to the substrate encloses the attachment area and forms a shielding space over the attachment area; and the non-conductive adhesive is located between the substrate and the bonding end, and has a dielectric constant not less than 7 and a coating thickness not greater than 0.07 millimeters (mm). With the present disclosure, an Electromagnetic Interference (EMI) shielding effect of the shielding space can be improved. 1. An electronic component package structure , comprising:a substrate;a conductive lid; anda non-conductive adhesive,wherein the substrate has a set attachment area for attaching an electronic component,wherein the conductive lid has a top and a sidewall that extend toward the substrate,wherein one side of the sidewall proximate to the substrate has a bonding end,wherein the bonding end bonds the conductive lid to the substrate using the non-conductive adhesive,wherein the conductive lid bonded to the substrate encloses the attachment area and forms a shielding space over the attachment area,wherein the non-conductive adhesive is located between the substrate and the bonding end,wherein the electronic component package structure further comprises a solder mask disposed on a surface of one side of the substrate facing the conductive lid, andwherein in the solder mask, a first open window is disposed in a position in which the non-conductive adhesive is disposed.2. The electronic component package structure according to claim 1 , wherein an air hole is disposed in the ...

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Номер записи: 25
03-03-2022 дата публикации

Semiconductor package

Номер: US20220068845A1
Автор: Chen-hua Lin, Chwen-Ming Liu, Huang-Wen Tseng, Victor Chiang Liang, Yang-Che CHEN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

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Номер записи: 26
14-02-2019 дата публикации

SEMICONDUCTOR DEVICE PACKAGES WITH DIRECT ELECTRICAL CONNECTIONS AND RELATED METHODS

Номер: US20190051578A1
Автор: Groothuis Steven, Li Jian, Luo Shijian
Принадлежит:

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Vias may directly electrically connect the uppermost semiconductor die to the substrate. 1. A semiconductor device package , comprising:a substrate;a stack of semiconductor dice attached to the substrate, an uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate being a heat-generating component configured to generate more heat than underlying semiconductor dice of the stack located between the uppermost semiconductor die and the substrate, an active surface of the uppermost semiconductor die facing the underlying semiconductor dice;a first set of vias extending through underlying semiconductor dice located beneath the uppermost semiconductor die, the first set of vias electrically interconnecting the underlying semiconductor dice at least to one another and to the substrate;a second set of vias extending through the underlying semiconductor dice, the second set of vias directly electrically connecting the uppermost semiconductor die to the substrate, the second set of vias located laterally adjacent to the first set of vias; andan encapsulation material at least partially surrounding the stack of semiconductor dice, an inactive surface of the uppermost semiconductor die remaining uncovered by the encapsulation material.2. The semiconductor device package of claim 1 , wherein the first set of vias is located laterally between subgroupings of the second set of vias.3. The semiconductor device package of claim 1 , wherein the second set of vias extend through ...

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Номер записи: 27
14-02-2019 дата публикации

Semiconductor module

Номер: US20190051640A1
Автор: Shinichi Kinouchi, Shinya Yano, Yasushi Nakayama
Принадлежит: Mitsubishi Electric Corp

In a semiconductor module, first and second semiconductor chips each include a transistor and a temperature-detecting diode connected between first and second control pads. The first control pad of the first semiconductor chip is connected to a first control terminal, the second control pad of the first semiconductor chip and the first control pad of the second semiconductor chip are connected to a second control terminal, and the second control pad of the second semiconductor chip is connected to a third control terminal.

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Номер записи: 28
05-03-2015 дата публикации

Ball arrangement for integrated circuit package devices

Номер: US20150061128A1
Автор: Arun Ramakrishnan, Hongyu Li
Принадлежит: Broadcom Corp

An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs.

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Номер записи: 29
21-02-2019 дата публикации

Semiconductor package and electronic device having the same

Номер: US20190057924A1
Автор: Eun Kyoung Kim, Jung Hyun Lim, Se Min JIN, Seung Goo JANG, Tae Hyun Kim
Принадлежит: Samsung Electro Mechanics Co Ltd

A semiconductor package includes a substrate including an antenna; a heating element disposed on a first surface of the substrate and connected to the antenna; a heat radiating part coupled to the heating element; and a signal transfer part disposed on the first surface of the substrate and configured to electrically connect the substrate to a main substrate. The heat radiating part may include a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other.

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Номер записи: 30
01-03-2018 дата публикации

ELECTRONIC COMPONENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC MODULE

Номер: US20180061751A1
Автор: Moriyama Yousuke, MURAKAMI Kensaku
Принадлежит: KYOCERA CORPORATION

An electronic component mounting substrate includes an insulating base having a rectangular shape in plan view and including a first main surface, a second main surface facing the first main surface, and a recess open on the first main surface, a band-shaped metal layer on a sidewall of the recess, and an electrode extending from a bottom surface of the recess into the insulating base. The electrode has an end disposed in the insulating base, and the end includes an inclined portion inclined toward the second main surface. 1. An electronic component mounting substrate comprising:an insulating base having a rectangular shape in plan view and comprising a first main surface, a second main surface facing the first main surface, and a recess open on the first main surface;a band-shaped metal layer on a sidewall of the recess; andan electrode extending from a bottom surface of the recess into the insulating base,the electrode comprising an end disposed in the insulating base, the end comprising an inclined portion inclined toward the second main surface.2. The electronic component mounting substrate according to claim 1 , wherein the sidewall of the recess and the inclined portion overlap in perspective plan view.3. The electronic component mounting substrate according to claim 1 , wherein the band-shaped metal layer and the inclined portion overlap in perspective plan view.4. The electronic component mounting substrate according to claim 1 , wherein an area of the inclined portion is included in an area of the sidewall of the recess in perspective plan view.5. The electronic component mounting substrate according to claim 1 , wherein the electrode is an outer electrode to be connected to a module substrate claim 1 ,wherein the insulating base further comprises a side surface, andwherein the recess is a solder deposit portion that is open at the side surface and in which the outer electrode is connected to the module substrate via solder.6. The electronic component ...

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Номер записи: 31
02-03-2017 дата публикации

Flip chip backside mechanical die grounding techniques

Номер: US20170062377A1
Автор: James Fred Salzman
Принадлежит: Texas Instruments Inc

A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.

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Номер записи: 32
19-03-2015 дата публикации

Thinned integrated circuit device and manufacturing process for the same

Номер: US20150076682A1
Автор: Heng-Chieh Chien, John H. Lau, Sheng-Tsai Wu, Wei-Chung Lo, Yu-Lin Chao
Принадлежит: Industrial Technology Research Institute ITRI

A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.

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Номер записи: 33
11-03-2021 дата публикации

Polygon integrated circuit (ic) packaging

Номер: US20210074599A1
Автор: Bhupender Singh, Charles L. Arvin, Jon A. Casey, Richard F. Indyk, Shidong Li
Принадлежит: International Business Machines Corp

An electronic system includes two integrated circuit (IC) packages that are connected by a package to package (PP) connector. The PP connector may include cabling between a first cabling connector and a second cabling connector. The first cabling connector may be seated to a first carrier connector upon a first IC device carrier of the first IC device package. The second cabling connector may be seated to a second carrier connector upon a second IC device carrier of the second IC device package. The electronic system may further include a heat sink connected to the IC packages, to the first cabling connector, and to the second cabling connector. An IC device may route I/O data through the PP connector, effectively increasing the number of I/O routes.

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Номер записи: 34
12-03-2020 дата публикации

Electronic device

Номер: US20200083143A1
Автор: Chih-Pin Hung, Ian HU, Jung-Che Tsai
Принадлежит: Advanced Semiconductor Engineering Inc

An electronic device includes a main substrate, a semiconductor package structure and at least one heat pipe. The semiconductor package structure is electrically connected to the main substrate, and includes a die mounting portion, a semiconductor die and a cover structure. The semiconductor die is disposed on the die mounting portion. The cover structure covers the semiconductor die. The heat pipe contacts the cover structure for dissipating a heat generated by the semiconductor die.

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Номер записи: 35
12-03-2020 дата публикации

SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR

Номер: US20200083177A1
Автор: JR. Peter, Lamorey Mark C., Patel Janak G., Slota, Stone David B.
Принадлежит:

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor. 1. A method for electrostatically storing energy in a package assembly including a chip stack and a lid , the method comprising:storing a first charge on a first plate of a capacitor provided by a flange of the lid that is coupled with the chip stack; andstoring a second charge on a second plate of the capacitor provided by a section of a conductive layer located along a sidewall of a first substrate of the package assembly that supports and laterally surrounds the chip stack, wherein the flange of the first plate and the second plate are laterally separated by a gap composed of dielectric material having a permittivity, and the first substrate is a laminated substrate containing a through-hole in which at least a portion of the chip stack and the lid and flange are located.2. The method of claim 1 , wherein the conductive layer is ring-shaped.3. The method of claim 1 , further comprising a solder ball on the conductive layer of the first substrate.4. The method of claim 1 , wherein the lid is cup shaped.5. The method of claim 1 , wherein the dielectric material that provides the gap is air.6. The method of claim 1 , wherein the ...

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Номер записи: 36
29-03-2018 дата публикации

Flip chip ball grid array with low impednce and grounded lid

Номер: US20180090406A1
Автор: Edward J. Yarmchuk, Martin Beaumier, Melania C. Doll, Michael Gaynes, Yves Dallaire
Принадлежит: International Business Machines Corp

A contact spring for placement in a gap between an electrical substrate opposite a lid (electrically conductive heat spreader) of an electronic device comprises a spring that both conducts heat from the substrate to the lid and electrically connects the substrate and lid. The spring comprises a flat single element configured as a plurality of polygons, providing contact points, the spring substantially lying in a plane and extending substantially in a straight line, or a spiral. The spring in an electronic device such as a flip chip ball grid array having this lid and an electrical substrate with EMI emitters: (1) provides low impedance electrical connection between the electronic circuit and lid; (2) grounds the lid to the electronic circuit; (3) minimizes EMI in the electronic circuit; (4) conducts heat from the electronic circuit to the lid; or any one or combination of the foregoing features (1)-(4).

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Номер записи: 37
28-03-2019 дата публикации

3DIC Packaging with Hot Spot Thermal Management Features

Номер: US20190096781A1
Автор: Chen Kim Hong, Huang Szu-Po, Hung Wensen, Jeng Shin-Puu, Lee Hsiang-Fan, WU Chi-Hsi
Принадлежит:

A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material. 1. A package comprising: a plurality of first dies; and', 'a second die bonded to the plurality of first dies, wherein a first portion of the second die is disposed directly under the plurality of first dies, and wherein a second portion of the second die extends laterally past sidewalls of the plurality of first dies; and, 'a die stack comprising a conductive line extending continuously from the plurality of conductive connectors to a thermal interface material (TIM) at the top surface of the package substrate; and', 'a solder resist, wherein the solder resist covers a first portion of the conductive line and does not cover a second portion of the conductive line, and wherein the TIM extends through the solder resist to contact the second portion of the conductive line., 'a package substrate, wherein the die stack is bonded to a top surface of the package substrate by a plurality of conductive connectors, and wherein the package substrate comprises2. The package of claim 1 , further comprising a heat dissipation feature adhered to the package substrate by an adhesive claim 1 , wherein the conductive line is thermally connected to the heat dissipation feature through the TIM.3. The package of claim 2 , wherein the heat dissipation feature is adhered to the package substrate by an adhesive having a lower thermal conductivity than the TIM.4. The package of claim 3 , wherein the adhesive encircles the second portion of the conductive line in a top down view.5. The package of claim 1 , wherein the conductive line is a signal line claim 1 ...

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Номер записи: 38
28-03-2019 дата публикации

SEMICONDUCTOR PACKAGES THAT INCLUDE A HEAT PIPE FOR EXHAUSTING HEAT FROM ONE OR MORE ENDS OF THE PACKAGE

Номер: US20190096786A1
Автор: BAEK Woon-young, JOO Sungwoo, LEE Hanhong, Park Jaehong
Принадлежит:

A semiconductor package includes a package substrate including a fastening section at one end and a connecting terminal section at an opposite end, at least one semiconductor device mounted on the package substrate, at least one heat pipe on the at least one semiconductor device, and a lid on the at least one semiconductor device and the at least one heat pipe. At least one end of the heat pipe is between the at least one semiconductor device and either the fastening section or the connecting terminal section. 1. A semiconductor package , comprising:a package substrate;at least one semiconductor device mounted on the package substrate;at least one heat pipe on the at least one semiconductor device; anda lid on the at least one semiconductor device and the at least one heat pipe, a first extension that runs across the at least one semiconductor device and extends in a first direction; and', 'a second extension that extends from the first extension in a second direction crossing the first direction, the second extension being between one end of the package substrate and one end of the semiconductor device in plan view., 'wherein the at least one heat pipe comprises2. The semiconductor package of claim 1 , whereinthe at least one heat pipe further comprises a third extension that runs across the semiconductor device and extends in the first direction, andthe second extension connects the first and third extensions to each other.3. The semiconductor package of claim 1 , whereinthe lid comprises at least one recession formed at its surface facing the semiconductor device, andthe at least one heat pipe is provided in the recession.4. The semiconductor package of claim 1 , whereinthe package substrate comprises a connecting section physically and/or electrically connected to an external apparatus, andthe second extension is adjacent to the connecting section.5. The semiconductor package of claim 1 , wherein the lid comprises a plurality of protrusions formed on an upper ...

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Номер записи: 39
26-03-2020 дата публикации

Liquid metal tim with stim-like performance with no bsm and bga compatible

Номер: US20200098661A1
Автор: Betsegaw GEBREHIWOT, Chia-Pin Chiu, Edvin Cetegen, Feras Eid, Joseph Petrini, Kelly Lofgreen
Принадлежит: Intel Corp

Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

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Номер записи: 40
30-04-2015 дата публикации

Semiconducor device and method of manufacturing the same

Номер: US20150115433A1
Автор: Charles W.C. Lin, Chia-Chung Wang
Принадлежит: Bridge Semiconductor Corp

The present invention relates to a method of making a semiconductor device having a chip embedded in a heat spreader and electrically connected to a hybrid substrate. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a heat spreader using an adhesive with the chip inserted into a cavity of the heat spreader. The heat spreader provides thermal dissipation and the interposer provides a CTE-matched interface and primary fan-out routing for the chip.

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Номер записи: 41
02-04-2020 дата публикации

Stacked silicon package assembly having thermal management

Номер: US20200105642A1
Автор: Cheang-Whang CHANG, Gamal Refai-Ahmed, Henley Liu, Jaspreet Singh Gandhi, Myongseob Kim, Suresh Ramalingam, Tien-Yu Lee
Принадлежит: Xilinx Inc

A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

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Номер записи: 42
27-04-2017 дата публикации

Semiconductor device packages with improved thermal management and related methods

Номер: US20170117205A1
Автор: JIAN Li, Shijian Luo, Steven Groothuis
Принадлежит: Micron Technology Inc

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate. A heat sink may be located on a side of the uppermost semiconductor die opposite the substrate. A passivation material may be located between the uppermost semiconductor die and the heat sink.

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Номер записи: 43
09-04-2020 дата публикации

Dual side die packaging for enhanced heat dissipation

Номер: US20200111720A1
Автор: Chandra Mohan JHA, Chia-Pin Chiu, Shankar Devasenathipathy, Weihua Tang, Zhimin Wan
Принадлежит: Intel Corp

An Integrated Circuit (IC) device structure is provided. The IC device structure includes a first substrate, first one or more dies coupled to a first side of the first substrate by a first plurality of interconnect structures, second one or more dies coupled to a first section of a second side of the substrate by a second plurality of interconnect structures, and a third plurality of interconnect structures to couple a second section of the second side of the substrate to a second substrate. In an example, at least a part of the second one or more dies are within a cavity in the second substrate.

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Номер записи: 44
05-05-2016 дата публикации

Cavity package with pre-molded cavity leadframe

Номер: US20160126164A1
Автор: Chun Ho Fan
Принадлежит: UBOTIC Co Ltd

A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow.

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Номер записи: 45
05-05-2016 дата публикации

Broadband radio frequency power amplifiers, and methods of manufacture thereof

Номер: US20160126905A1
Автор: Basim H. Noori, Jeffrey K. Jones, Lei Zhao, Michael E. Watts
Принадлежит: FREESCALE SEMICONDUCTOR INC

An embodiment of an amplifier has a bandwidth defined by low and upper cutoff frequencies. The amplifier includes an input impedance matching circuit and a transistor. The transistor has a gate, a first current conducting terminal coupled to an output of the amplifier, and a second current conducting terminal coupled to a reference node. The input impedance matching circuit has a filter input coupled to an input of the amplifier, a filter output coupled to the gate of the transistor, and a multiple pole filter coupled between the filter input and the filter output. A first pole of the filter is positioned at a first frequency within the bandwidth, and a second pole of the filter is positioned at a second frequency outside the bandwidth. The input impedance matching circuit is configured to filter the input RF signal to produce a filtered RF signal at the filter output.

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Номер записи: 46
25-04-2019 дата публикации

Exfoliated Graphite Materials and Composite Materials and Devices for Thermal Management

Номер: US20190124793A1
Автор: John Kenna
Принадлежит: TERRELLA ENERGY SYSTEMS Ltd

Exfoliated graphite materials, and composite materials including exfoliated graphite, having enhanced through-plane thermal conductivity can be used in thermal management applications and devices. Methods for making such materials and devices involve processing exfoliated graphite materials such as flexible graphite to orient or re-orient the graphite flakes in one or more regions of the material.

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Номер записи: 47
03-06-2021 дата публикации

SEMICONDUCTOR DIE ASSEMBLIES HAVING MOLDED UNDERFILL STRUCTURES AND RELATED TECHNOLOGY

Номер: US20210167058A1
Автор: Bitz Bradley R., Li Xiao
Принадлежит:

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die. 120-. (canceled)21. A semiconductor die assembly , comprising:a first semiconductor die having an upper surface and a first footprint;a second semiconductor die carrying the first semiconductor die, wherein the second semiconductor die has a second footprint larger than the first footprint such that the second semiconductor die includes a peripheral portion extending beyond the first footprint;a heat spreader thermally coupled to the first semiconductor die and to the peripheral portion of the second semiconductor die;a first planar thermal interface feature having a first side in direct contact with the upper surface of the first semiconductor die and an opposite second side in direct contact with the heat spreader; anda second planar thermal interface feature having a first side in direct contact with the peripheral portion of the second semiconductor die, and an opposite second side in direct contact with the heat spreader.22. The semiconductor die assembly of wherein the first ...

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Номер записи: 48
17-05-2018 дата публикации

Image sensor package

Номер: US20180138225A1
Автор: Jae-choon Kim, Ji-Chul Kim, Seung-yong Cha, Yong-Hoon Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

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Номер записи: 49
15-09-2022 дата публикации

Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package

Номер: US20220289560A1
Автор: Chen Kang, Choi Won Kyoung, Lin Yaojian, Micallef Ivan
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;disposing a modular interconnect structure adjacent to the first semiconductor die;depositing a first encapsulant over the first semiconductor die and modular interconnect structure;forming a build-up interconnect structure over the first semiconductor die, modular interconnect structure, and first encapsulant; anddisposing a second semiconductor die including a microelectromechanical system (MEMS) over the first semiconductor die opposite the build-up interconnect structure.2. The method of claim 1 , further including forming a bond wire extending from the second semiconductor die to the modular interconnect structure.3. The method of claim 2 , further including disposing a lid on the modular interconnect structure and extending over the second semiconductor die and bond wire.4. The method of claim 2 , further including depositing a ...

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Номер записи: 50
25-05-2017 дата публикации

Electrical package including bimetal lid

Номер: US20170148704A1
Автор: Hiroyuki Mori, Keiji Matsumoto
Принадлежит: International Business Machines Corp

Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads on a surface of the organic substrate via a plurality of solder balls; and a lid for encapsulating the semiconductor chip on the organic substrate, wherein (i) an inner surface of a central part of the lid is connected to a surface of the semiconductor chip via a first TIM, (ii) an inner surface of an outer part of the lid is hermetically connected to the surface of the organic substrate, and (iii) the lid has a bimetal structure including at least two different metals. A circuit module is also provided.

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Номер записи: 51
25-05-2017 дата публикации

Package Structures and Methods of Forming the Same

Номер: US20170148778A1
Автор: Chun-Chih Chuang, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Ming-Che Liu, Tsung-Ding Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first die, and a redistribution structure on the first die and the first encapsulant. The second die is attached by an external electrical connector to the redistribution structure. The second die is on an opposite side of the redistribution structure from the first die. A second encapsulant is on the redistribution structure and at least laterally encapsulates the second die. The second encapsulant has a surface distal from the redistribution structure. A conductive feature extends from the redistribution structure through the second encapsulant to the surface of the second encapsulant. A conductive pillar is on the conductive feature, and the conductive pillar protrudes from the surface of the second encapsulant.

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Номер записи: 52
02-06-2016 дата публикации

Proximity coupling of interconnect packaging systems and methods

Номер: US20160155729A1
Автор: Owen R. Fay, Rich Fogal
Принадлежит: US Bank NA

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

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Номер записи: 53
07-05-2020 дата публикации

SEMICONDUCTOR DEVICE ASSEMBLY WITH VAPOR CHAMBER

Номер: US20200141658A1
Автор: Groothuis Steven K., Li Jian
Принадлежит:

Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die on a base region of the first die, and a thermal transfer device attached to a peripheral region of the first die and extending over the second die. The thermal transfer device includes a conductive structure having an internal cavity and a working fluid at least partially filling the cavity. The conductive structure further includes first and second fluid conversion regions adjacent the cavity. The first fluid conversion region transfers heat from at least the peripheral region of the first die to a volume of the working fluid to vaporize the volume in the cavity, and the second fluid conversion region condenses the volume of the working fluid in the cavity after it has been vaporized. 1. A semiconductor device assembly , comprising:a package support substrate;a first semiconductor die positioned on the package support substrate, the first semiconductor die including a base region and a peripheral region adjacent to the base region;a second semiconductor die positioned on the base region of the first semiconductor die;a thermal transfer device attached to both the peripheral region and to the support substrate via a contiguous first adhesive, and to the second semiconductor die via a second adhesive, wherein the thermal transfer device includes a conductive structure having a cavity.2. The semiconductor device assembly of claim 1 , wherein the first semiconductor die includes a perimeter claim 1 , wherein the peripheral region is adjacent to the perimeter claim 1 , and wherein the base region is laterally inboard of the peripheral region.3. The semiconductor device assembly of claim 1 , wherein the conductive structure includes an outer region containing a first portion of the cavity claim 1 , the outer region ...

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Номер записи: 54
16-05-2019 дата публикации

MULTIPLE PLATED VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON SAME SUBSTRATE

Номер: US20190148344A1
Автор: Katkar Rajesh, Uzoh Cyprian Emeka
Принадлежит: INVENSAS CORPORATION

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component. 1. An apparatus , comprising:a first substrate having a conductive layer;first plated conductors in a first region extending from a surface of the conductive layer;second plated conductors in a second region extending from the surface of the conductive layer;wherein the first plated conductors and the second plated conductors are external to the first substrate;wherein the first region is disposed at least partially within the second region;wherein the first plated conductors are of a first height;wherein the second plated conductors are of a second height greater than the first height;a second substrate coupled to first ends of the first plated conductors;the second substrate having at least one electronic component coupled thereto;a die coupled to second ends of the second plated conductors; andthe die located over the at least one electronic component.2. The apparatus according to claim 1 , wherein the at least one electronic component includes a discrete passive component.3. The apparatus according to claim 2 , wherein the second substrate includes a ...

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Номер записи: 55
23-05-2019 дата публикации

Electronic Devices With Environmental Sensors

Номер: US20190154471A1
Автор: YANG Henry H.
Принадлежит:

An electronic device may be provided with environmental sensors. Environmental sensors may include one or more environmental sensor components and one or more acoustic components. Acoustic components may include a speaker or a microphone. Environmental sensor components may include a temperature sensor, a pressure sensor, a humidity sensor, a gas sensor, or other sensors or combinations of sensors for sensing attributes of the environment surrounding the device. The environmental sensor may have an enclosure with an opening. The enclosure may be formed from a rigid support structure and a portion of a printed circuit. The opening may be formed in the rigid support structure or the printed circuit. The opening in the enclosure for the environmental sensor may be aligned with an opening in an outer structural member for the device. The outer structural member may be a housing structure or a cover layer for a device display. 1. A sensor package , comprising:a printed circuit;a rigid support structure attached to the printed circuit;a first environmental sensor attached to the printed circuit, wherein the rigid support structure and a portion of the printed circuit form an enclosure that surrounds the first environmental sensor; andan ambient light sensor mounted within the enclosure, wherein the enclosure comprises an opening that allows air to pass through the opening into the enclosure.2. The sensor package defined in claim 1 , wherein the first environmental sensor comprises a sensor selected from the group consisting of: a microphone claim 1 , a gas sensor claim 1 , a smoke detector claim 1 , a pressure sensor claim 1 , a temperature sensor claim 1 , and a humidity sensor.3. The sensor package defined in claim 1 , wherein the first environmental sensor comprises a microphone.4. The sensor package defined in claim 1 , wherein the first environmental sensor comprises a gas sensor that is configured to measure a concentration of a gas.5. The sensor package defined in ...

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Номер записи: 56
07-06-2018 дата публикации

Semiconductor device packages with direct electrical connections and related methods

Номер: US20180158751A1
Автор: JIAN Li, Shijian Luo, Steven Groothuis
Принадлежит: Micron Technology Inc

Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate.

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Номер записи: 57
22-09-2022 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

Номер: US20220301970A1
Автор: Chen Chen-Shien, Kao Chin-Fu
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor package includes a substrate, a package structure, a lid structure, and a thermal spreader layer. The package structure is disposed on the substrate, wherein the package structure includes a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies. The lid structure is disposed over substrate and covering the package structure. The thermal spreader layer is disposed between the lid structure and the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap. 1. A semiconductor package , comprising:a substrate;a package structure disposed on the substrate, wherein the package structure comprises a plurality of device dies and a filling material filling a gap between adjacent two of the plurality of device dies;a lid structure disposed over substrate and covering the package structure; anda thermal spreader layer disposed between the lid structure and the package structure, wherein the thermal spreader layer has a profile that is discontinuous in thickness at a gap region corresponding to the gap.2. The semiconductor package as claimed in claim 1 , wherein a thickness of the thermal spreader layer at the gap region is substantially thinner than a thickness of the thermal spreader layer at other region.3. The semiconductor package as claimed in claim 1 , wherein a thickness of the thermal spreader layer at the gap region is substantially equal to zero.4. The semiconductor package as claimed in claim 1 , wherein a young's modulus of the thermal spreader layer is substantially greater than a young's modulus of the filling material.5. The semiconductor package as claimed in claim 1 , wherein the filling material comprising a protruding portion protruding from back surfaces of the plurality of device dies and fills a space defined by thickness discontinuity of the thermal spreader layer at the gap region.6. The ...

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Номер записи: 58
04-09-2014 дата публикации

Copper nanorod-based thermal interface material (tim)

Номер: US20140246770A1
Автор: Ashish Gupta, Chandra M. Jha, Feras Eid, Johanna M. Swan
Принадлежит: Intel Corp

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

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Номер записи: 59
18-06-2015 дата публикации

Three-dimensional (3d) integrated heat spreader for multichip packages

Номер: US20150170989A1
Автор: Hemanth K. DHAVALESWARAPU, Roger D. FLYNN, Sanjoy K. Saha
Принадлежит: Intel Corp

Embodiments of the present disclosure describe thermal management solutions for multichip package assemblies and methods of fabricating multichip package assemblies utilizing the thermal management solutions. These embodiments include multi-level heat spreaders and alleviate issues caused by dimensional variability in die-packages utilized in multichip package assemblies. In one embodiment a package heat spreader is thermally coupled to a first die-package and die-package heat spreader. The die-package heat spreader is thermally coupled to a second die-package and provides a thermal pathway to conduct heat from the second die-package to the package heat spreader. Other embodiments may be described and/or claimed.

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Номер записи: 60
24-06-2021 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20210193550A1
Автор: Chen-Hsiang Lao, Chien-Yuan Huang, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

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Номер записи: 61
14-06-2018 дата публикации

Semiconductor package and method of forming the same

Номер: US20180166351A1
Автор: Chung-Chih Chen, Hsien-Liang Meng, Yen-Miao LIN, Ying-Shin HAN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The lid is disposed over the substrate. The lid includes a cap portion and a foot portion extending from a bottom surface of the cap portion. The cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess. The adhesive includes a sidewall portion and a bottom portion. The sidewall portion contacts a sidewall of the foot portion. The bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate.

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Номер записи: 62
01-07-2021 дата публикации

Semiconductor package

Номер: US20210202462A1
Автор: Chajea JO, Jae Choon Kim, Jichul Kim, Kyoung Soon Cho, Sang-uk Han, Woohyun Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

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Номер записи: 63
06-06-2019 дата публикации

Apparatuses and methods for semiconductor die heat dissipation

Номер: US20190172817A1
Автор: Anilkumar Chandolu, Sameer S. Vadhavkar, XIAO Li
Принадлежит: Micron Technology Inc

Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a substrate and a heat spreader. The substrate may include a thermal interface layer disposed on a surface of the substrate, such as disposed between the substrate and the heat spreader. The heat spreader may include a plurality of substrate-facing protrusions in contact with the thermal interface layer, wherein the plurality of substrate-facing protrusions are disposed at least partially through the thermal interface layer.

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Номер записи: 64
22-06-2017 дата публикации

Semiconductor device

Номер: US20170178985A1
Автор: Yoshiaki Sato, Yosuke Katsura
Принадлежит: Renesas Electronics Corp

A semiconductor device includes a semiconductor chip and a package structure mounted on a wiring substrate, and a lid for covering the semiconductor chip, which is fixed to the surface of the wiring substrate, without overlapping with the package structure in plan view. The lid includes an upper surface portion overlapping with the semiconductor chip, a flange portion fixed to the surface of the wiring substrate, and a slant portion for jointing the upper surface portion and the flange portion. Then, a distance from the surface of the wiring substrate to the top surface of the upper surface portion is larger than a distance from the surface of the wiring substrate to the top surface of the flange portion.

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Номер записи: 65
28-05-2020 дата публикации

Semiconductor device and electronic device

Номер: US20200168540A1
Автор: Shuuichi Kariyazaki, Yoshitaka Okayasu
Принадлежит: Renesas Electronics Corp

The lower surface of the wiring substrate includes a first region overlapping with the semiconductor chip mounted on the upper surface, and a second region surrounding the first region and not overlapping with the semiconductor chip. The first region includes a third region in which the plurality of external terminals is not arranged, and a fourth region surrounding the third region in which the plurality of external terminals is arranged. The plurality of external terminals includes a plurality of terminals arranged in the fourth region of the first region and a plurality of terminals arranged in the second region. The plurality of terminals includes a plurality of power supply terminals for supplying a power supply potential to the core circuit of the semiconductor chip, and a plurality of reference terminals for supplying a reference potential to the core circuit of the semiconductor chip.

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Номер записи: 66
15-07-2021 дата публикации

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS

Номер: US20210217734A1
Автор: Groothuis Steven K., Li Jian
Принадлежит:

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies. 1. A semiconductor die assembly , comprising:a first die including a controller; a central portion beneath a footprint of the first die;', 'a peripheral portion extending beyond the footprint of the first die;', 'a circuit component disposed in the central portion; and', 'a communication component disposed in the peripheral portion and configured to deserialize serial input data into a plurality of input data streams;, 'a second die including—'}a stack of third dies positioned on the second die, wherein the first die is positioned on the stack of third dies;a plurality of first through-stack interconnects extending through the entire stack of third dies to couple the controller to the communication component, wherein the first through-stack interconnects are configured to transmit (a) the plurality of input data streams from the communication component to the controller and (b) a plurality of output data streams from the controller to the communication component;a plurality of second through-stack interconnects extending through the entire stack of third dies to couple the first die to the circuit component; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a casing attached to the peripheral portion of the second die and configured to dissipate heat from the communication component during operation. The semiconductor die assembly of wherein the casing defines a cavity, and wherein the first die and the third dies are positioned in the cavity.'}3. The semiconductor die assembly of wherein the first die includes a bulk portion of a semiconductor substrate ...

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Номер записи: 67
07-07-2016 дата публикации

Semiconductor package with package-on-package stacking capability and method of manufacturing the same

Номер: US20160197063A1
Автор: Charles W. C. Lin, Chia-Chung Wang
Принадлежит: Bridge Semiconductor Corp

The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip.

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Номер записи: 68
05-07-2018 дата публикации

THERMAL INTERFACE MATERIAL ON PACKAGE

Номер: US20180190565A1
Автор: DE SOUSA Isabel, LAVOIE Annique, Salvas Eric, TURGEON Michel
Принадлежит:

A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly. 1. A method , comprising:dispensing a thermal interface material (TIM) on an electronic assembly;pressing a lid onto the electronic assembly to perform a packaged assembly;performing a sonoscan of the packaged assembly for determining a presence of voiding in the TIM.2. The method of claim 1 , further comprising removing volatile species of the TIM prior to pressing the lid.3. The method of claim 2 , wherein the volatile species comprises cyclic siloxanes and decyl trimethoxysilane.4. The method of claim 2 , wherein the removal of the volatile species comprises maintaining the TIM at room temperature for a predetermined time period prior to pressing the lid.5. The method of claim 4 , wherein the predetermined time period is about 60 minutes.6. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a predetermined temperature claim 2 , in an oven claim 2 , for a predetermined time period.7. The method of claim 6 , wherein the predetermined temperature is about 45° C. to 55° C. and the predetermined time period is about 15-30 minutes.8. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 20 minutes.9. The method of claim 6 , wherein the predetermined temperature is about 50° C. and the predetermined time period is about 15 minutes.10. The method of claim 2 , wherein the removal of the volatile species comprises subjecting the TIM to a vacuum outgassing process. ...

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Номер записи: 69
11-06-2020 дата публикации

Semiconductor device and data transferring method for semiconductor device

Номер: US20200185328A1
Автор: Nobuyoshi Tanaka
Принадлежит: Preferred Networks Inc

A semiconductor device includes a first chip, a second chip, a third chip, a fourth chip, and a substrate. The first to fourth chips are mounted on the substrate. The first chip is placed adjacent to the second chip and the fourth chip. The third chip is placed adjacent to the second chip and the fourth chip at a position different from that of the first chip. The second chip has a first transferring circuit that transfers data from the first chip to the third chip, and the fourth chip has a second transferring circuit that transfers data from the third chip to the first chip.

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Номер записи: 70
30-07-2015 дата публикации

System and Method for Bonding Package Lid

Номер: US20150214128A1
Автор: Chin-Liang Chen, Kuan-Lin Ho, Shih-Yen Lin, Wei-Ting Lin, Yu-Chih Liu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.

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Номер записи: 71
30-07-2015 дата публикации

Cover structure and manufacturing method thereof

Номер: US20150216032A1
Автор: Ying-Ming Lee
Принадлежит: Subtron Technology Co Ltd

A method of manufacturing a cover structure is provided. A metal substrate disposed on a carrier is provided. The carrier has a surface, and the metal substrate has a plurality of openings exposing a portion of the surface. A first metal layer is formed on the metal substrate and is conformal with the metal substrate. The first metal layer covers the portion of the surface exposed by the openings. An insulating layer and a second metal layer located on the insulating layer are laminated on the metal substrate. The insulating layer is located between the first metal layer and the second metal layer to cover the first metal layer and fill the openings. The metal substrate and the carrier are removed to expose the first metal layer and define a plurality of cavity regions and a plurality of connecting regions connected with the cavity regions.

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Номер записи: 72
29-07-2021 дата публикации

Integrated circuit assemblies having metal foam structures

Номер: US20210233832A1
Автор: Aastha Uppal, Je-Young Chang
Принадлежит: Intel Corp

An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.

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Номер записи: 73
06-08-2015 дата публикации

Wiring board, method of manufacturing wiring board, electronic device, electronic apparatus, and moving object

Номер: US20150223325A1
Автор: Hidefumi Nakamura, Hideki Ishigami, Tetsuro MIYAO, Tetsuya Otsuki, Yukihiko Shiohara
Принадлежит: Seiko Epson Corp

A base substrate includes a ceramic sintered substrate having through holes, first and second metal wirings which are integrally disposed so as to be connected to the surface of the ceramic sintered substrate and the inside of the through holes, and first and second active metal layers which are disposed between the ceramic sintered substrate and the first and second metal wirings.

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Номер записи: 74
26-07-2018 дата публикации

Electrically Testable Microwave Integrated Circuit Packaging

Номер: US20180211890A1
Автор: Christie Andrew, MOFFAT Mark, Pilgrim Duncan
Принадлежит:

An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies. 1. A method for fabricating and testing a microwave integrated circuit , including:(a) flip-chip assembling a plurality of integrated circuit dies on a thin-film tile provisioned with probe-compatible connection pads such that the probe-compatible connection pads are accessible after assembly for connection to probes;(b) automatically testing at least some of the plurality of dies through the probe-compatible connection pads; and(c) singulating at least some of the plurality of the dies and corresponding segments of the tile into die/tile assemblies.2. The method of claim 1 , further including configuring at least some of the probe-compatible connection pads as ground-signal-ground sets of pads.3. The method of claim 1 , wherein the thin-film tile has a thickness of less than or equal to about 0.35 mm.4. The method of claim 1 , wherein the thin-film tile has a thickness of less than or equal to about 0.23 mm.5. The method of claim 1 , wherein the thin-film tile has a thickness of less than or equal to about 0.175 mm.6. The method of claim 1 , wherein the thin-film tile is made of one of alumina or a low temperature co-fired ceramic.7. The method of claim 1 , further including fabricating the integrated ...

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Номер записи: 75
25-06-2020 дата публикации

Microphone packaging for a portable communication device

Номер: US20200203257A1
Автор: Andrew P. Miehl, Deborah A. Gruenhagen, Ido Amit, Karl F. Mueller, Kathryn Johnson, Rammone Bartlett
Принадлежит: Motorola Solutions Inc

A microphone packaging assembly ( 100 ) provides a printed circuit board (pcb) ( 106 ) for coupling to a microphone device ( 102 ) having a bottom acoustic port ( 104 ). The pcb provides an acoustic port opening ( 108 ) which aligns with the bottom acoustic port ( 104 ) of the microphone device ( 102 ). A solder pad pattern ( 110 ) is disposed on the pcb ( 106 ). The solder pad pattern ( 110 ) is configured to provide both electrical connection ( 114 ) and an incomplete solder seal ( 116 ) having purposeful acoustic leak to the microphone device ( 102 ). A conformable coating ( 126 ) provides a seal to the purposeful acoustic leak. A single acoustic test can be performed to detect proper environmental protection and acoustic sealing of the packaged assembly ( 100 ).

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Номер записи: 76
10-08-2017 дата публикации

METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS

Номер: US20170229439A1
Автор: Derderian James M., Gandhi Jaspreet S., Groothuis Steven K., Hembree David R., Li Jian, Li Xiao, Vadhavkar Sameer S.
Принадлежит:

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material. 1. A method for packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack and attached to the first die , wherein the first die has a peripheral region extending laterally outward from the stack of second dies , the method comprising:positioning at least a portion of a thermal transfer structure at the peripheral region of the first die, wherein the thermal transfer structure comprises a thermally conductive material; andflowing an underfill material between the second dies after positioning the thermal transfer structure on the peripheral region of the first die, wherein the underfill material has a fillet extending laterally from the stack of second dies, and wherein the lateral extension of the underfill material is limited by the thermal transfer structure.2. The method of wherein the first portion of the thermal transfer structure comprises a sidewall extending to a height of an uppermost second die and the second portion of the thermal transfer member comprises a top.3. The method of wherein:the thermal transfer structure comprises a sidewall, a top integrally formed with the sidewall, a cavity formed by the sidewall and the top, and an inlet;the sidewall has a foundation configured to surround at least a portion of the ...

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Номер записи: 77
09-07-2020 дата публикации

SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING THE SAME

Номер: US20200219784A1
Автор: JANG Seung Goo, JIN Se Min, Kim Eun Kyoung, Kim Tae Hyun, LIM Jung Hyun
Принадлежит: SAMSUNG ELECTRO-MECHANICS CO., LTD.

A semiconductor package includes a substrate including an antenna; a heating element disposed on a first surface of the substrate and connected to the antenna; a heat radiating part coupled to the heating element; and a signal transfer part disposed on the first surface of the substrate and configured to electrically connect the substrate to a main substrate. The heat radiating part may include a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other. 1. A semiconductor package comprising:a substrate comprising a wiring layer;a heating element disposed on a first surface of the substrate and connected to the wiring layer;a heat radiating part coupled to the heating element; anda signal transfer part electrically connecting the substrate to a main substrate;a sealing part substantially enclosing the signal transfer part and the heating element,wherein the sealing part is formed of a single insulating material, andthe heat radiating part includes a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other.2. The semiconductor package of claim 1 , wherein the heat transfer part has a flat plate shape or a block shape and comprises a metal.3. The semiconductor package of claim 1 , further comprising connection terminals disposed on one side of the signal transfer part and connected to the main substrate claim 1 ,wherein the heat radiating terminal comprises a material in common with the connection terminal and has substantially the same size as the connection terminal.4. The semiconductor package of claim 1 , wherein the single insulating material is epoxy molding compound (EMC).5. The semiconductor package of claim 1 , wherein the heat transfer part is embedded in the sealing part claim 1 , andthe heat radiating terminal penetrates through the sealing part and is connected to the ...

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Номер записи: 78
25-07-2019 дата публикации

SEMICONDUCTOR DEVICE ASSEMBLY WITH HEAT TRANSFER STRUCTURE FORMED FROM SEMICONDUCTOR MATERIAL

Номер: US20190229096A1
Автор: Derderian James M., Gandhi Jaspreet S., Vadhavkar Sameer S.
Принадлежит:

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity. 1. A method of forming a semiconductor device assembly , comprising:forming a structure from a semiconductor substrate, the structure including an inner region, two or more outer regions proximate the inner region, and a cavity defined by the inner region and the two or more outer regions;positioning a stack of semiconductor dies in the cavity of the structure;disposing an underfill material in the cavity, wherein an excess portion of the underfill material forms a fillet in a gap between a sidewall of the cavity and the stack of semiconductor dies; andattaching a second semiconductor die over the cavity of the structure.2. The method of claim 1 , attaching the second semiconductor die over the cavity includes:attaching a base region of the second semiconductor die to an outermost semiconductor die of the stack; andattaching a peripheral region of the second semiconductor die to a portion of at least one of the two or more outer regions of the structure.3. The method of claim 1 , further comprising:forming an electrically insulating layer on a surface of the cavity, the surface facing the stack of semiconductor dies, wherein the stack of semiconductor dies is positioned in the cavity after forming the insulating layer.4. The method of claim 1 , wherein:the inner region of the ...

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Номер записи: 79
16-07-2020 дата публикации

Microelectronic assemblies

Номер: US20200227384A1
Автор: Adel A. Elsherbini, Johanna M. Swan, Shawna M. LIFF
Принадлежит: Intel Corp

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

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Номер записи: 80
26-08-2021 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20210265174A1
Автор: Doo Hyun Park, Ji Hun Lee, Jong Sik Paek, Seong Min Seo, Won Chul Do
Принадлежит: Amkor Technology Singapore Holding Pte Ltd

Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer.

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Номер записи: 81
17-09-2015 дата публикации

Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package

Номер: US20150259194A1
Автор: Ivan Micallef, KANG Chen, Won Kyoung Choi, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

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Номер записи: 82
14-09-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170263587A1
Автор: FUNATSU Katsuhiko, KANAZAWA Takamitsu, KOIDO Masahiro, Sato Yukihiro, Taya Hiroyoshi
Принадлежит:

Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH. 1. A semiconductor device comprising:a ceramic substrate having a first surface, and a second surface located on an opposite side of the first surface;a plurality of metal patterns formed on the first surface of the ceramic substrate; anda first semiconductor chip mounted on one of the plurality of metal patterns,wherein, in plan view, the ceramic substrate has a first substrate side which is extended in a first direction, and a second substrate side which is extended in a second direction intersecting the first direction,wherein, in plan view, a length of the first substrate side is longer than a length of the second substrate side,wherein, in plan view, a first metal pattern of the plurality of metal patterns has a first side which is extended along the second substrate side, a second side which is extended along the second substrate side and facing to the first side, a third side which is extended along the first substrate side, and located between the first side and the second side, andwherein, in plan view, a second metal pattern of the plurality of metal patterns has a fourth side which is extended along the first substrate side, and is located between the first side and the second side, and facing the third side of the first metal pattern.2. The semiconductor device according to claim 1 ,wherein, in plan view, a plurality of wires intersects with the third side and the fourth side.3. The semiconductor device ...

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Номер записи: 83
22-08-2019 дата публикации

Re-Routable Clip for Leadframe Based Product

Номер: US20190259689A1
Автор: Baltazar Canete, Melvin Martin, Rajesh Subraya Aiyandra, Tung Ching Lui
Принадлежит: Dialog Semiconductor UK Ltd

A method of fabricating an integrated circuit package having improved heat dissipation is described. A re-routable clip is provided having a central portion and a plurality of leads surrounding the central portion. A die is attached to an underside of the central portion of the re-routable clip. The die and the leads of the re-routable clip are attached to a substrate. The die and the leads are encapsulated with a mold compound wherein a top surface of the central portion of the re-routable clip is exposed by the mold compound. The substrate is connected to a printed circuit board wherein thermal pathways are formed 1) from the die downward to the substrate to the printed circuit board and 2) from the die upward to the re-routable clip and then downward through the leads to the substrate and to the printed circuit board.

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Номер записи: 84
22-08-2019 дата публикации

Device Package with Reduced Radio Frequency Losses

Номер: US20190259716A1
Автор: Borrego Lambin Torres Amaral Pedro Augusto, Brox-Napieralska Ewa, Goller Bernd, Wiesbauer Andreas
Принадлежит:

A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness. 1. A device package comprising: a core layer for mechanically supporting the multilayer protective covering, the core layer comprising a first thickness less than 200 μm,', 'an electrically conductive layer disposed over a first surface of the core layer, the electrically conductive layer comprising a second thickness less than 20 μm, wherein the multilayer protective covering is indented to comprise a recessed region, wherein the core layer surrounds the recessed region,', 'a corrosion resistant layer disposed over the electrically conductive layer, and', 'a metal layer disposed over the corrosion resistant layer., 'a multilayer protective covering comprising'}2. The device package of claim 1 , wherein:the core layer comprises a first type of brass,the electrically conductive layer comprises a second type of brass,an electrical conductivity of the second type of brass is greater than an electrical conductivity of the first type of brass, andthe second thickness is less than about to 10 μm.3. The device package of claim 1 , wherein:the core layer comprises one of brass or nickel silver;the first thickness is about 100 μm;the electrically conductive layer comprises copper; andthe second thickness is between about 3 μm to 6 μm.4. The device package of ...

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Номер записи: 85
04-11-2021 дата публикации

Method for forming package structure

Номер: US20210343611A1
Автор: Chih-Chien Pan, Chih-hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.

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Номер записи: 86
13-08-2020 дата публикации

Cold-welded flip chip interconnect structure

Номер: US20200259064A1
Автор: Eric Peter Lewandowski, Jae-Woong Nah, Nicholas Torleiv Bronn
Принадлежит: International Business Machines Corp

In an embodiment, a quantum device includes a first set of protrusions formed on a substrate and a second set of protrusions formed on a qubit chip. In the embodiment, the quantum device includes a set of bumps formed on an interposer, the set of bumps formed of a material having above a threshold ductility at a room temperature range, wherein a first subset of the set of bumps is configured to cold weld to the first set of protrusions and a second subset of the set of bumps is configured to cold weld to the second set of protrusions.

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Номер записи: 87
13-08-2020 дата публикации

Thermal management solutions for integrated circuit packages

Номер: US20200260609A1
Автор: Amitesh Saha, Betsegaw K. Gebrehiwot, Je-Young Chang
Принадлежит: Intel Corp

A heat dissipation device may be formed having a planar structure with a first surface and a surface area enhancement structure projecting from or extending into the first surface of the planar structure. In one embodiment, an integrated circuit package may be formed with the heat dissipation device, wherein the heat dissipation device and at least one integrated circuit device are brought into thermal contact with a thermal interface material between the at least one integrated circuit device and the heat dissipation device and wherein the surface area enhancement structure of the heat dissipation device directly contacts the thermal interface material.

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Номер записи: 88
18-12-2014 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20140370660A1
Автор: Takumi Ihara
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

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Номер записи: 89
19-10-2017 дата публикации

Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package

Номер: US20170297903A1
Автор: Chen Kang, Choi Won Kyoung, Lin Yaojian, Micallef Ivan
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;disposing a modular interconnect structure laterally with respect to the first semiconductor die;depositing an encapsulant around the first semiconductor die and modular interconnect structure;forming a conductive layer over the first semiconductor die and modular interconnect structure; anddisposing a second semiconductor die over the first semiconductor die, wherein the first semiconductor die or second semiconductor die includes a microelectromechanical device.2. The method of claim 1 , further including forming an interconnect structure over the modular interconnect structure opposite the conductive layer.3. The method of claim 1 , further including forming a conductive via through the modular interconnect structure.4. The method of claim 1 , wherein an active surface of the first semiconductor die is oriented toward an active ...

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Номер записи: 90
11-10-2018 дата публикации

Wafer level integration for embedded cooling

Номер: US20180294205A1
Автор: Mark Delorman Schultz, Pritish Ranjan PARIDA, Timothy Joseph Chainer
Принадлежит: International Business Machines Corp

Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming channel structures on a first surface of a silicon first wafer, wherein the channel structures respectively include radial channels that extend from central fluid distribution areas, and wherein integrated circuits are formed on a second surface of the silicon first wafer that opposes the first surface. The method can further include bonding a manifold wafer to the first surface of the silicon wafer such that inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas, thereby enclosing the radial channels and forming a bonded structure.

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Номер записи: 91
11-10-2018 дата публикации

Wafer level integration for embedded cooling

Номер: US20180294206A1
Автор: Mark Delorman Schultz, Pritish Ranjan PARIDA, Timothy Joseph Chainer
Принадлежит: International Business Machines Corp

Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming channel structures on a first surface of a silicon first wafer, wherein the channel structures respectively comprise radial channels that extend from central fluid distribution areas, and wherein integrated circuits are formed on a second surface of the silicon first wafer that opposes the first surface. The method can further include bonding a manifold wafer to the first surface of the silicon wafer such that inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas, thereby enclosing the radial channels and forming a bonded structure.

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Номер записи: 92
11-10-2018 дата публикации

Board Level Shields With Virtual Grounding Capability

Номер: US20180295714A1
Автор: Dixon Paul Francis, Khorrami Mohammadali, Rhyne George William
Принадлежит:

According to various aspects, exemplary embodiments are disclosed of board level shields with virtual grounding capability. In an exemplary embodiment, a board level shield includes one or more resonators configured to be operable for virtually connecting the board level shield to a ground plane or a shielding surface. Also disclosed are exemplary embodiments of methods relating to making board level shields having virtual grounding capability. Additionally, exemplary embodiments are disclosed of methods relating to providing shielding for one or more components on a substrate by using a board level shield having virtual grounding capability. Further exemplary embodiments are disclosed of methods relating to making system in package (SiP) or system on chip (SoC) shielded modules and methods relating to providing shielding for one or more components of SiP or SoC module. 1. An assembly comprising one or more resonators configured to be operable for virtually connecting the assembly to an electrically-conductive surface.2. The assembly of claim 1 , wherein:the assembly includes one or more walls; andthe one or more resonators comprise a plurality of resonators spaced apart from each other and generally disposed around at least a portion of a perimeter defined by the one or more walls; andthe resonators are configured to be operable for virtually connecting the one or more walls to the electrically-conductive surface.3. The assembly of claim 2 , wherein:the one or more walls comprise one or more sidewalls of a board level shield; andthe resonators are spaced apart from each other and generally disposed around at least a portion of a perimeter defined by the one or more sidewalls of the board level shield.4. The assembly of claim 3 , wherein:the one or more sidewalls of the board level shield comprise outer and inner sidewalls of the board level shield; andthe resonators are disposed along the outer and inner sidewalls of the board level shield.5. The assembly of claim ...

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Номер записи: 93
19-10-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170301604A1
Автор: Motofuji Takuma, OOMORI Kouij, UEDA Naoto, YOSHIDA Takayuki
Принадлежит:

A semiconductor device according to the present disclosure includes an electrically conductive first electrode block, an electrically conductive submount, an insulating layer, a semiconductor element, an electrically conductive bump, and an electrically conductive second electrode block. The submount is provided in a first region of the upper surface of the first electrode block, and electrically connected to the first electrode block. The semiconductor element is provided on the submount, and has a first electrode electrically connected to the submount. The bump is provided on the upper surface of a second electrode, opposite the first electrode, of the semiconductor element, and electrically connected to the second electrode. A third region of the lower surface of the second electrode block is electrically connected to the bump via an electrically conductive metal layer. An electrically conductive metal sheet is provided between the metal layer and the bump. 1. A semiconductor device , comprising:a first electrode block being electrically conductive;a submount being electrically conductive, provided in a first region of an upper surface of the first electrode block, and electrically connected to the first electrode block;an insulating layer provided in a second region of the upper surface of the first electrode block other than the first region;a semiconductor element provided on the submount and having a first electrode electrically connected to the submount;a bump being electrically conductive, provided on an upper surface of a second electrode, opposite the first electrode, of the semiconductor element, and electrically connected to the second electrode; anda second electrode block provided on the bump and the insulating layer and electrically conductive,wherein a third region of a lower surface of the second electrode block is electrically connected to the bump via an electrically conductive metal layer,wherein a fourth region of the lower surface of the ...

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Номер записи: 94
18-10-2018 дата публикации

Substrate Design for Semiconductor Packages and Method of Forming Same

Номер: US20180301351A1
Автор: Cheng Jung Wei, Lee Chien-Hsun, Lii Mirng-Ji, WANG Tsung-Ding, Yu Chen-Hua
Принадлежит:

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity. 1. A device comprising: a metal-clad insulated base material core, the metal-clad insulated base material core having a topmost surface and a bottommost surface opposite the topmost surface; and', 'a cavity extending through the metal-clad insulated base material core;, 'a package substrate, wherein the package substrate comprisesa first die at least partially within the cavity; anda first plurality of connectors in the cavity, the first plurality of connectors coupling the first die to the package substrate, the first plurality of connectors extending below the topmost surface of the metal-clad insulated base material core toward a bottommost surface of the cavity, the first plurality of connectors directly contacting the bottommost surface of the cavity.2. The device of claim 1 , further comprising a second die attached to the package substrate claim 1 , the package substrate being interposed between the first die and the second die.3. The device of claim 2 , further comprising a second plurality of connectors electrically coupling the second die to the package substrate.4. The device of claim 3 , further comprising one or more redistribution layers (RDLs) interposed between the second die and the second plurality of connectors.5. The device of claim 2 , further comprising a heat dissipation feature on a surface of the second die claim 2 , the second die being interposed between the heat dissipation feature and the package substrate.6. The device of claim 2 , ...

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Номер записи: 95
18-10-2018 дата публикации

Multiple bond via arrays of different wire heights on a same substrate

Номер: US20180301436A1
Автор: Cyprian Emeka Uzoh, Rajesh Katkar
Принадлежит: Invensas LLC

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

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Номер записи: 96
26-09-2019 дата публикации

PROXIMITY COUPLING INTERCONNECT PACKAGING SYSTEMS AND METHODS

Номер: US20190296003A1
Автор: Fay Owen R., Fogal Rich
Принадлежит:

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad. 1. A method for manufacturing a semiconductor package assembly , the method comprising:disposing a first semiconductor die adjacent to a substrate having bond pads, the first semiconductor die having a first coupling face that faces away from the substrate;disposing a second semiconductor die adjacent to the substrate and spaced laterally apart from the first semiconductor die, the second semiconductor die having a second coupling face that faces away from the substrate; andstacking a third semiconductor die on the first semiconductor die and the second semiconductor die, the third semiconductor die having a third coupling face and bond pads at the third coupling face, the third coupling face facing the first coupling face and the second coupling face;wherein stacking the third semiconductor die includes aligning a third conductive pad on the third coupling face with a first conductive pad on the first coupling face to form a first proximity coupling interconnect, wherein the ...

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Номер записи: 97
26-10-2017 дата публикации

THERMOCOMPRESSION FOR SEMICONDUCTOR CHIP ASSEMBLY

Номер: US20170309586A1
Автор: SYLVESTRE Julien
Принадлежит:

An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the semiconductor chip pads and substrate pads include solder bumps. The solder bumps are deformed against the substrate pads and the semiconductor chip pads, whereby an underfill material is applied to fill the gap between the semiconductor chip and substrate. The underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads. At least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads, and at least another one of the solder bumps have been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads. 1. A semiconductor chip assembly comprising:a semiconductor chip having pads;a substrate having pads aligned to receive the semiconductor chip, wherein at least one of the semiconductor chip pads and substrate pads have solder bumps, the solder bumps being deformed against the substrate pads and the semiconductor chip pads; andan underfill material applied to fill a gap between the semiconductor chip and the substrate, wherein the underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads, andwherein at least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads, andwherein at least another one of the solder bumps have been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads.2. The assembly of claim 1 , wherein the semiconductor chip further comprises copper pillars extending from the semiconductor chip pads and the solder bumps are between the ends of the copper pillars and the substrate pads.3. The assembly ...

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Номер записи: 98
25-10-2018 дата публикации

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

Номер: US20180308785A1
Автор: David R. Hembree, James M. Derderian, Jaspreet S. Gandhi, JIAN Li, Sameer S. Vadhavkar, Steven K. Groothuis, XIAO Li
Принадлежит: Micron Technology Inc

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

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Номер записи: 99
02-11-2017 дата публикации

Thermal Dissipation Through Seal Rings in 3DIC Structure

Номер: US20170317004A1
Автор: Lin Jing-Cheng
Принадлежит:

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer. 1. A semiconductor device comprising:a plurality of dies bonded to each other;an interposer bonded to one of the plurality of dies;a seal-ring comprising thermal path extending through each of the plurality of dies;a metal line on the interposer, the metal line extending away from the plurality of dies in a direction parallel with a major surface of the interposer;an interposer seal ring extending at least partially through the interposer; anda through via extending at least partially through the interposer, the through via in thermal connection with the metal line through the interposer seal ring.2. The semiconductor device of claim 1 , wherein the seal-ring is connected to an electrical ground.3. The semiconductor device of claim 1 , wherein the seal-ring is electrically isolated.4. The semiconductor device of claim 1 , wherein one of the plurality of dies comprises an through substrate via.5. The semiconductor device of claim 4 , wherein the one of the plurality of dies comprises a semiconductor substrate claim 4 , the through substrate via being planar with the semiconductor substrate at a first side and a second side opposite the first side.6. The semiconductor device of ...

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Номер записи: 100