Partially molded direct chip attach package structures for connectivity module solutions

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

Verfahren zur Herstellung eines Leistungsmoduls sowie Leistungsmodul

Die Erfindung betrifft ein Verfahren zur Herstellung eines Leistungsmoduls (10). Das Verfahren umfasst das Bereitstellen eines ersten Bauteils (12) mit einer Oberseite (14) und einer Unterseite (16), das direkte Abscheiden einer ersten Schicht (28), welche ein erstes Material (36) umfasst, auf die Oberseite (14) des ersten Bauteils (12), das direkte Abscheiden einer zweiten Schicht (30), welche ein von dem ersten Material (36) verschiedenes zweites Material (38) umfasst, auf die erste Schicht (28), das Bereitstellen eines zweiten Bauteils (18) mit einer Oberseite (20) und einer Unterseite (22), das Anordnen der Unterseite (22) des zweiten Bauteils (18) auf der zweiten Schicht (30) und das stoffschlüssige Verbinden des ersten Bauteils (12) und des zweiten Bauteils (18) durch Beaufschlagen der Unterseite (16) des ersten Bauteils (12) und/oder der Oberseite (20) des zweiten Bauteils (18) mit einer vorbestimmten Kraft (FN1, FN2).

BOND PAD ARRANGEMENT FOR POWER SEMICONDUCTOR DEVICES

A semiconductor device, comprising: a substrate (50) with an active area (44) and a gate control contact area (52); a source bond pad (46) on at least a portion of the active area (44); a gate bond pad (48) over the gate control contact area (52) and laterally extending over a portion of the source bond pad (46); and dielectric layer (60) between the portion of the source bond pad (46) and the gate control bond pad (48). The arrangement of the gate bond pad (48) partiall on top of the source bond pad (46) enables the active area (44) to extend below the gate bond pad (48), which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area (44) and thus a rated current for a particular semiconductor die size. Methods for manufacturing said semiconductor device are also provided.

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.

SEMICONDUCTOR DEVICE HAVING REDISTRIBUTION LAYER WITH COPPER MIGRATION STOPPING

A semiconductor device having a first dielectric layer and a redistribution layer. The redistribution layer has sidewalls and is formed on a passivation layer of the semiconductor device. The first dielectric layer covers the sidewalls of the redistribution layer. The first dielectric layer is insulative and has a physical property of stopping the migration of the redistribution layer. 1. A semiconductor device , comprising:a semiconductor substrate having an integrated circuit and a metal layer, wherein the metal layer is coupled to the integrated circuit;a passivation layer on the semiconductor substrate;a plurality of vias formed in the passivation layer to expose a plurality of surfaces of the metal layer;a redistribution layer formed on a part of the passivation layer and in the plurality of vias, wherein the redistribution layer is coupled to the metal layer and has sidewalls and a top surface; anda first dielectric layer covering the sidewalls of the redistribution layer, wherein the first dielectric layer is insulative and is configured to stop the migration of the redistribution layer.2. The semiconductor device of claim 1 , further comprising a conductive bump formed on a part of the top surface of the redistribution layer.3. The semiconductor device of claim 2 , wherein the conductive bump comprises:a copper pillar formed on the part of the top surface of the redistribution layer; anda solder bump formed on the copper pillar, wherein the solder bump comprises tin or tin alloy.4. The semiconductor device of claim 2 , wherein the conductive bump comprises a solder ball formed on the part of the top surface of the redistribution layer claim 2 , wherein the solder ball comprises tin or tin alloy.5. The semiconductor device of claim 1 , wherein the first dielectric layer further covers the remaining part of the passivation layer.6. The semiconductor device of claim 2 , wherein the first dielectric layer further covers the remaining part of the top surface of ...

RECONFIGURED WIDE I/O MEMORY MODULES AND PACKAGE ARCHITECTURES USING SAME

In some embodiments, it is desirable to increase memory bandwidth using an integrated solution. In one embodiment, wide I/O memory may be used. Described herein are embodiments of systems and methods of reconfiguring wide I/O memory modules. The reconfigured memory modules may be configured such that the memory modules function in combination with current packaging architectures.

Teilweise geformte, direkte Chipanbringungsstruktur für Konnektivitätsmodullösungen

Es werden Verfahren zum Bilden von mikroelektronischen Packungsstrukturen/Modulen und dadurch gebildete Strukturen beschrieben. Die hierin eingeschlossenen Strukturen können einen Chip auf einem ersten Substrat, mindestens eine erste Komponente benachbart des Chips auf dem ersten Substrat, und eine Formmasse auf dem ersten Substrat umfassen, wobei die mindestens eine Komponente und der Chip in der Formmasse eingebettet sind. Ein zweites Substrat kann physisch mit dem ersten Substrat gekoppelt sein. Eine Kommunikationsstruktur kann auf einer oberen Oberfläche des zweiten Substrats angeordnet sein, wobei mindestens eine zweite Komponente auch auf der oberen Oberfläche des zweiten Substrats angeordnet sein kann.

FLOATING BOND PAD FOR POWER SEMICONDUCTOR DEVICES

Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size.

Semiconductor device having a solder blocking metal layer

A semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes: a semiconductor element having a solder region and a non-solder region on a first face; a first metal member disposed on the first face of the semiconductor element; a second metal member disposed on a rear face of the semiconductor element; a first solder that connects the solder region of the semiconductor element and the first metal member; and a second solder that connects the rear face of the semiconductor element and the second metal member. At least the second solder provides a melt-bond. A gravity center position of the first metal member coincides with a center position of the semiconductor element in a projection view from a stacking direction.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device comprising a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

Method used for manufacturing power module, and power module

Semiconductor device and method for manufacturing the same

A semiconductor device includes: a semiconductor element having a solder region and a non-solder region on a first face; a first metal member disposed on the first face of the semiconductor element; a second metal member disposed on a rear face of the semiconductor element; a first solder that connects the solder region of the semiconductor element and the first metal member; and a second solder that connects the rear face of the semiconductor element and the second metal member. At least the second solder provides a melt-bond. A gravity center position of the first metal member coincides with a center position of the semiconductor element in a projection view from a stacking direction.

Printed RFID circuit

A printed circuit including a non-conductive substrate, a first conductive layer printed on the non-conductive substrate and one or more additional layers printed on the substrate. The first conductive layer is able to have one or more antennas each forming a predetermined pattern, a first conductive sheet and one or more conductive traces. The one or more additional layers include a first electrode printed on the top of the first conductive sheet, a buffer printed on top of the first electrode, a second electrode printed on top of the buffer and a second conductive sheet printed on top of the second electrode. The printed circuit is further able to include an RFID chip electrically coupled with the antennas and at least one of the first and second conductive sheets via the conductive traces, wherein the first and second conductive sheets, the buffer and the first and second electrodes form a power source that provides electrical power to the RFID chip.

Partially molded direct chip attach package structures for connectivity module solutions

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

Floating bond pad for power semiconductor devices

Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size.

Nano-copper pillar interconnects and methods thereof

Embodiments of the present invention relate to nano-copper pillar interconnects. Nano-copper material is a mixture of nano-copper particles and one or more organic fluxes. In some embodiments, the one or more organic fluxes include organic solvents that help bind the nano-copper particles together and allow the nano-copper material to be printable. The nano-copper material is applied onto bond pads on a printed circuit board (PCB) via a printing process, a dipping process or the like, to form nano-copper covered PCB bond pads. A component can thereafter be coupled with the PCB at the nano-copper covered PCB bond pads. What is left when the solvents evaporate are nano-copper pillar interconnects that form, coupling the component with the PCB bond pads. The nano-copper pillar interconnects are of pure copper.

GANG CLIP WITH MOUNT COMPOUND ARRESTER

An integrated circuit package includes a lead frame, a first die adhered to the lead frame on a first side of the first die, and a first clip having a clip foot adhered to the lead frame. The first clip has a first side and a second side. A first die attachment region is defined by a first group of four notches in the first side of the first clip. The first clip extends from the lead frame and contacts a second side of the first die at the first die attachment region via a first layer of solder paste. The integrated circuit package further has a second die adhered to the second side of the first clip on a first side of the second die, and a second clip having a clip foot adhered to the lead frame. The second clip has a first side and a second side. A second die attachment region is defined by a second group of four notches in the first side of the second clip. The second clip extends from the lead frame and contacts a second side of the second die at the second die attachment region via ...

Fixture design for pre-attachment package on package component assembly

Embodiments of the present invention relate to a fixture design for pre-attachment package on package component assembly. The fixture design includes a plurality of pockets arranged in a N×M array. The plurality of pockets is sized to receive bottom packages. The fixture design includes global fiducials that are used to locate positions of the pockets on the fixture, and sets of local fiducials, with each set being specific to one of the pockets and used to refine the position of the location of a corresponding pocket. Each of the pockets can include one or more ear cuts for easy component placement and component removal. The fixture design can include a vacuum port for coupling with a vacuum source for drawing a vacuum to hold the bottom packages down. The fixture design can also include a cover that is used with the fixture to keep the components from being disturbed.

PARTIALLY MOLDED DIRECT CHIP ATTACH PACKAGE STRUCTURES FOR CONNECTIVITY MODULE SOLUTIONS

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

Decoupling capacitor mounted on an integrated circuit die, and method of manufacturing the same

Electronic device package technology is disclosed. In one example, an electronic device comprises a die (18) having a bond pad (22); and a decoupling capacitor (14) mounted on the die (18) and electrically coupled to the die (18). A method for making an electronic device comprises mounting a decoupling capacitor (14) on a die (18); and electrically coupling the decoupling capacitor (14) to the die (18).

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method is disclosed for manufacturing a semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

DECOUPLING CAPACITOR MOUNTED ON AN INTEGRATED CIRCUIT DIE, AND METHOD OF MANUFACTURING THE SAME

Electronic device package technology is disclosed. In one example, an electronic device comprises a die (18) having a bond pad (22); and a decoupling capacitor (14) mounted on the die (18) and electrically coupled to the die (18). A method for making an electronic device comprises mounting a decoupling capacitor (14) on a die (18); and electrically coupling the decoupling capacitor (14) to the die (18).

Integrated circuit chip and manufacturing method therefor

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Spherical solder reflow method

The present disclosure relates to methods of making solder balls having a uniform size. More particularly, the disclosure relates to improved solder ball formation processes that prevent or reduce bridging/merging of two or more solder balls during reflow. The processes of the instant disclosure are desirable because they do not require a sifting step to obtain uniformly-sized solder balls.

Enhanced Bump Pitch Scaling

An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.

System on a chip with interleaved sets of pads

A system on a chip (SOC) includes a physical interface having first and second sets of interface pads. Interface pads from the first set are interleaved with interface pads from the second set. Additionally, the SOC is arranged for operation with a superset die having first and second personalities and has a physical interface with interface pads. The SOC uses a first number of interface pads in the first personality and a second number of interface pads in the second personality, where the first number is greater than the second number. A switch switches signals between the superset die and the physical interface and, in the second personality, switches signals to the physical interface so that interface pads in the second number of interface pads are interleaved with interface pads not in use in the second personality.

Multiple die in a face down package

A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Semiconductor package and stacked semiconductor package

A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

Die connections using different underfill types for different regions

Die connections are described using different underfill types for different regions. In one example, a first electrically-non-conductive underfill paste (NCP) type is applied to an I/O region of a first die. A second NCP type is applied outside the I/O region of the first die, the second NCP type having more filler than the first NCP type, and the second die is bonded to a first die using the NCP.

Bump-on-Trace Structures with High Assembly Yield

A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 μmand about 1,300 μm. 1. A package comprising: 'a first metal trace at a surface of the first package component, wherein the first metal trace has a trace width, with the trace width being measured in a direction perpendicular to a lengthwise direction of the first metal trace;', 'a first package component comprising a first portion, wherein the first portion has a first width smaller than the trace width; and', 'a second portion and a third portion on opposite sides of the first portion, wherein the second portion and the third portion have second widths greater than the first width; and, 'a second package component over the first package component, wherein the second package component comprises a metal bump, and the metal bump comprisesa solder region bonding the metal bump to the first metal trace.2. The package of claim 1 , wherein the second widths are further greater than the trace width.3. The package of claim 1 , wherein the solder region contacts a first portion of the first metal trace claim 1 , and a ratio of a volume of the solder region to the trace width is between about 1 claim 1 ,100 μmand about 1 claim 1 ,300 μm.4. The ...

POWER MODULE

A power module includes a base plate, first, second, and third semiconductor chips. At least one of a third edge or fourth edge of the first semiconductor chip is disposed adjacent to a side end of the base plate. Among a half of a distance from a first edge of the first semiconductor chip to one edge of the second semiconductor chip, a half of a distance from a second edge of the first semiconductor chip to one edge of the third semiconductor chip, and a distance from the third edge or fourth edge of the first semiconductor chip disposed adjacent to the side end of the base plate to the side end of the base plate, a length of a solder fillet formed on the edge of the first semiconductor chip at the shortest distance is formed in the shortest length. 1. A power module comprising:a base plate;a first semiconductor chip having four edges;a second semiconductor chip having four edges, one of the four edges disposed adjacent to a first edge of the first semiconductor chip, the second semiconductor chip soldered to the base plate; anda third semiconductor chip having four edges, one of the four edges disposed adjacent to a second edge of the first semiconductor chip, the third semiconductor chip soldered to the base plate,wherein at least one of a third edge or a fourth edge of the first semiconductor chip is disposed adjacent to a side end of the base plate, andamong a half of a distance from the first edge of the first semiconductor chip to the one edge of the second semiconductor chip, a half of a distance from the second edge of the first semiconductor chip to the one edge of the third semiconductor chip, and a distance from the third edge or the fourth edge of the first semiconductor chip disposed adjacent to the side end of the base plate to the side end of the base plate, a length of a solder fillet formed on the edge of the first semiconductor chip at the shortest distance is formed in the shortest length.2. The power module according to claim 1 ,wherein a half ...

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. 1. A method of forming an integrated circuit (IC) package substrate , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laminating a permanent photodefinable layer over the first dielectric layer;patterning a pad into the permanent photodefinable layer, the pad disposed over the via;electrolytically plating a fill metal into the via and the pad;planarizing the fill metal to a top surface of the permanent photodefinable layer; andperforming a self-aligned plating of a surface finish metal over a top surface of the fill metal.2. The method of claim 1 , wherein filling the pad and via further comprises:depositing a catalyst on the permanent photodefinable layer;electrolessly plating a seed layer on the catalyst; andwherein the method further comprises removing the catalyst, with a wet chemical treatment, from the permanent photodefinable layer that is exposed when the fill metal is planarized.3. The method of claim 2 , wherein plating a surface finish metal over the fill metal further comprises: forming a catalyst on an exposed surface of the fill metal and plating one or more metal layers.4. A method of forming an integrated circuit (IC) package substrate claim 2 , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laser patterning a trace in the dielectric laterally ...

STRUCTURES AND METHODS FOR LOW TEMPERATURE BONDING

A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. 1. A method of making an assembly , comprising:forming a first conductive element at a first surface of a substrate of a first component, the first conductive element extending in a direction away from the first surface;forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, the conductive nanoparticles having long dimensions smaller than 100 nanometers;juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, with the conductive nanoparticles disposed between the surfaces of the first and second conductive elements; andelevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements.2. The method of claim 1 , wherein the first conductive element is one of a plurality of first conductive elements at the first surface claim 1 , and the ...

IMAGE SENSOR WITH TOLERANCE OPTIMIZING INTERCONNECTS

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed. 166-. (canceled)67. An imaging sensor comprising:a plurality of substrates comprising a first substrate and a second substrate;a pixel array comprising a plurality of pixel groups on the first substrate;supporting circuitry for the plurality of pixel groups comprising a plurality of supporting circuitry groups on the second substrate;a plurality of interconnects that connect the plurality of pixel groups to the supporting circuitry; anda first interconnect that connects a first pixel read bus of a first pixel group to a first circuit read bus of a first supporting circuitry group and a second interconnect that connects a second pixel read bus of a second pixel group to a second circuit read bus of a second supporting circuitry group;wherein the first pixel group and the second pixel group are adjacent to each other on the first substrate; andwherein the first supporting circuitry group and the second supporting circuitry group are not adjacent to each other on the second substrate.68. The imaging sensor of claim 67 , wherein the first interconnect connects the first pixel read bus on the first substrate to the first circuit read bus on the second substrate at a point along a physical path where the first pixel read bus on the first ...

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler. 1. A semiconductor device package , comprising:an electronic component;a first set of conductive wires electrically connected to the electronic component; andan insulation layer having a top surface and surrounding the first set of conductive wires, the top surface of the insulation layer exposing a portion of the first set of the conductive wires,wherein the insulation layer is devoid of a filler.2. The semiconductor device package of claim 1 , further comprising an encapsulant encapsulating the electronic component and the insulation layer.3. The semiconductor device package of claim 1 , further comprising a first patterned conductive layer disposed over the insulation layer and including a plurality of conductive pads claim 1 , wherein the conductive pads of the first patterned conductive layer are respectively electrically connected to the exposed portion of the first set of conductive wires.4. The semiconductor device package of claim 3 , whereinthe electronic component comprises a plurality of conductive contacts electrically connected to the first set of the conductive wires; anda pitch between at least two adjacent conductive contacts of the electronic component is less than a pitch between at least two adjacent conductive pads of the first patterned conductive layer.5. The semiconductor device package of claim 1 , further comprising a second set of conductive wires disposed on the insulation layer and electrically connected to the exposed portion of the first set of the conductive wires.6. The semiconductor device package of claim 5 , further comprising an encapsulant covering the electronic component claim 5 , the ...

WIRING BOARD

A wiring board includes an electronic component; an insulating layer containing the electronic component therein, and including a via hole that is open at one surface of the insulating layer to expose an electrode of the electronic component; a first wiring layer embedded in the insulating layer, one surface of the first wiring layer being exposed at the one surface of the insulating layer; a second wiring layer including a wiring pattern formed on the one surface of the first wiring layer, and a via wiring extended from the wiring pattern to be extended in the via hole and directly connected to an electrode of the electronic component. 1. A wiring board comprising:an electronic component;an insulating layer containing the electronic component therein, and including a via hole that is open at one surface of the insulating layer to expose an electrode of the electronic component;a first wiring layer embedded in the insulating layer, one surface of the first wiring layer being exposed at the one surface of the insulating layer; a wiring pattern formed on the one surface of the first wiring layer, and', 'a via wiring extended from the wiring pattern to be extended in the via hole and directly connected to an electrode of the electronic component., 'a second wiring layer including'}2. The wiring board according to claim 1 ,wherein the first wiring layer is formed to be positioned above the electrode of the electronic component, andwherein the via hole is formed to penetrate the first wiring layer that is positioned above the electrode of the electronic component, and penetrate the insulating layer positioned between the first wiring layer and the electrode of the electronic component.3. The wiring board according to claim 1 , wherein the second wiring layer includesa first layer directly formed on the one surface of the first wiring layer and including a through-hole that communicates with the via hole,a second layer formed on the first layer to be extended from above ...

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. 1. An apparatus comprising:a dielectric layer;a conductive trace in the dielectric layer, wherein the conductive trace comprises a first portion having an exposed top surface, and wherein the exposed top surface is recessed from a top surface of the dielectric layer; anda bump pad over and electrically connected to a second portion of the conductive trace.2. The apparatus of claim 1 , wherein the bump pad and the conductive trace comprise different conductive materials.3. The apparatus of claim 2 , wherein the bump pad comprises nickel or tin claim 2 , and wherein the conductive trace comprises copper.4. The apparatus of claim 1 , wherein the conductive trace is connected to a contact pad in the dielectric layer claim 1 , and wherein the apparatus further comprises a conductive pillar extending from the contact pad through the dielectric layer.5. The apparatus of further comprising:an integrated circuit chip; anda conductive bump physically coupled between the integrated circuit chip and the bump pad.6. The apparatus of claim 5 , wherein there are no conductive bumps physically coupling the integrated circuit chip to the first portion of the conductive trace.7. The apparatus of claim 1 , wherein a top surface of the bump pad is substantially level with the top surface of the dielectric layer.8. A device comprising:a substrate;a dielectric layer over the substrate;a conductive trace in the dielectric layer and comprising a first material; anda bump pad over and electrically coupled to a first portion of the conductive trace, wherein the bump pad comprises a second material ...

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Bonding Package Components Through Plating

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

CORNER GUARD FOR IMPROVED ELECTROPLATED FIRST LEVEL INTERCONNECT BUMP HEIGHT RANGE

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package. 1. An electronic package , comprising:a package substrate; a plurality of pads; and', 'a plurality of bumps, wherein each bump is over a different one of the plurality of pads; and, 'a first level interconnect (FLI) bump region on the package substrate, wherein the FLI bump region comprises a guard pad; and', 'a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package., 'a guard feature adjacent to the FLI bump region, wherein the guard feature comprises2. The electronic package of claim 1 , wherein the guard feature is proximate to a corner of the FLI bump region.3. The electronic package of claim 2 , wherein the guard feature is substantially L-shaped claim 2 , and wherein the guard feature wraps around the corner of the FLI bump region.4. The electronic package of claim 3 , wherein a first arm of the guard feature and a second arm of the guard feature have lengths that are approximately 15 mm or less.5. The electronic package of claim 1 , further comprising:a plurality of guard features, wherein the plurality of guard features are positioned around a perimeter of the FLI bump region.6. The electronic package of claim 1 , wherein the plurality of guard features are positioned proximate to two or more corners of ...

Wiring board, electronic apparatus, and method for manufacturing electronic apparatus

A wiring board includes a substrate, an electrode on a surface of the substrate, a wall surface in a ring shape surrounding an outer circumference of the electrode, an upper end of the wall surface is located at a position higher than a surface of the electrode, and a protrusion at the upper end of the wall surface, the protrusion protruding with respect to the wall surface inward of a ring shape defined by the wall surface.

Bump structural designs to minimize package defects

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

STRUCTURES AND METHODS FOR PROVIDING ELECTRICAL ISOLATION IN SEMICONDUCTOR DEVICES

Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 17-. (canceled)8. A method of forming a semiconductor structure , the method comprising:forming a plurality of semiconductor chips, each of the semiconductor chips comprising a substrate with one or more transistors or integrated circuits formed thereon;forming, on a top surface of each of the plurality of semiconductor chips, first solder bumps having a first pitch;flipping the plurality of semiconductor chips having the first solder bumps formed thereon;bonding the flipped plurality of semiconductor chips to a first side of an interposer through the first solder bumps; andbonding the interposer to a printed circuit board (PCB) or package substrate through second solder bumps disposed on a second side of the interposer, the second solder bumps having a second pitch that is greater than the first pitch.9. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer comprises:bonding the plurality of semiconductor chips to the first side of the interposer in an arrangement that includes air gaps or insulating passivation material separating adjacent semiconductor chips, the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.10. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer ...

Wire Bonding For Semiconductor Devices

A semiconductor device includes an integrated circuit die having bond pads and a bond wires. The bond wires are connected to respective ones of the bond pads by a ball bond. An area of contact between the ball bond and the bond pad has a predetermined shape that is non-circular and includes at least one axis of symmetry. A ratio of the ball bond length to the ball bond width may be equal to a ratio of the bond pad length to the bond pad width. 1. A semiconductor device comprising:an integrated circuit die having a plurality of bond pads; anda plurality of bond wires, each of the plurality of bond wires being physically connected to a respective one of the plurality of bond pads by a ball bond,wherein an area of contact between each ball bond and the respective bond pad has a shape that is non-circular and includes a first axis of symmetry.2. The semiconductor device of claim 1 , wherein the shape of the area of contact includes a second axis of symmetry claim 1 , wherein the second axis of symmetry is perpendicular to the first axis of symmetry.3. The semiconductor device of claim 2 , wherein the shape of the area of contact includes no more than two axes of symmetry.4. The semiconductor device of claim 1 , wherein each ball bond includes a ball bond width and a ball bond length claim 1 , and wherein a ratio of the ball bond length to the ball bond width is greater than 1.1.5. The semiconductor device of claim 4 , wherein the ratio of the ball bond length to the ball bond width is equal to or greater than 2.0.6. The semiconductor device of claim 4 , wherein the ball bond length is the largest dimension of the shape of the area of contact along the first axis of symmetry.7. The semiconductor device of claim 4 , wherein each of the bond pads includes a bond pad width and a bond pad length claim 4 , and wherein the ratio of the ball bond length to the ball bond width is equal to a ratio of the bond pad length to the bond pad width±10%.8. The semiconductor device of ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other. 1. A semiconductor package structure comprising:a first package;a second package over the first package and comprising a bonding region and a periphery region surrounding the bonding region;a plurality of connectors between the first package and the second package in the bonding region, wherein the plurality of connectors provide electrical connections between the first package and the second package; anda plurality of baffle structures between the first package and the second package, wherein the plurality of baffle structures are in contact with both of the first package and the second package,wherein the plurality of baffle structures are disposed in the periphery region of the second package and are separated from each other.2. The semiconductor package structure of claim 1 , wherein the plurality of baffle structures comprise insulating materials.3. The semiconductor package structure of claim 2 , wherein at least one of the plurality of baffle structures is in contact with one of the plurality of connectors.4. The semiconductor package structure of claim 2 , further comprising an underfill between the first package claim 2 , the second package claim 2 , adjacent connectors claim 2 , and adjacent baffle structures.5. The semiconductor package structure of claim 1 , wherein the plurality of baffle structures comprise conductive materials.6. The semiconductor package structure of ...

BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME

The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate. 1. An integrated chip structure , comprising:a first copper pillar disposed over a metal pad of an interposer substrate, wherein the first copper pillar has a sidewall defining a recess;a nickel layer disposed over the first copper pillar;a solder layer disposed over the first copper pillar and the nickel layer, wherein the solder layer continuously extends from directly over the first copper pillar to within the recess; anda second copper layer disposed between the solder layer and a second substrate.2. The integrated chip structure of claim 1 , wherein the first copper pillar has a width that is between about 10 microns and about 200 microns.3. The integrated chip structure of claim 1 , wherein the first copper pillar has a width that is between about 25 microns and about 50 microns.4. The integrated chip structure of claim 1 , wherein the sidewall of the first copper pillar defining the recess is a curved surface.5. The integrated chip structure of claim 1 , wherein the recess has a depth of between about 1 micron and about 15 microns.6. The integrated chip structure of claim 1 ,wherein the recess has a depth; andwherein a ratio of the depth to an overall width of the first copper pillar is in a range from about 0.05 to about 0.2.7. The integrated chip structure of claim 1 , wherein the solder layer has a height of between about 10 microns and about 50 microns.8. The integrated chip structure of claim 1 , wherein the first copper pillar is ...

Backplane, Preparation Method Thereof, Backlight Module and Display Device

A preparation method of a backplane includes: forming an insulating structure layer having a groove on a base substrate by a mask exposure process, the groove being used for accommodating a metal trace; and repeating a metal sub-layer forming step including an ashing process and a wet etching process multiple times to form the metal trace positioned in the groove.

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Remapped Packaged Extracted Die with 3D Printed Bond Connections

An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.

SYSTEM AND METHOD FOR SUB-COLUMN PARALLEL DIGITIZERS FOR HYBRID STACKED IMAGE SENSOR USING VERTICAL INTERCONNECTS

Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array. 127-. (canceled)28. An imaging sensor comprising:a pixel array comprising a plurality of pixel columns disposed on a first substrate, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns;a plurality of supporting circuits disposed on one or more additional substrates, the plurality of supporting circuits comprising a plurality of circuit columns, wherein each of the plurality of circuit columns is divided into a plurality of circuit sub-columns; anda plurality of interconnects for electrically connecting each pixel sub-column to one of the plurality of circuit sub-columns;wherein each of the plurality of circuit sub-columns has an area, a size, and an aspect ratio, and each of the plurality of pixel sub-columns that corresponds to each one of the circuit sub-columns has an area, a size, and an aspect ratio; andwherein the aspect ratio of at least one of the circuit sub-columns has a width equal to “N” times the width of the aspect ratio of one of said pixel sub-columns and a length equal to 1/“N” times the length of the aspect ratio of one of said pixel sub-columns.29. The imaging sensor of claim 28 , wherein the one or more additional substrates are disposed remotely relative to the first substrate;30. The imaging sensor of claim 28 , further comprising a pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate and a circuit sub-column bus for each of the plurality of circuit sub-columns on the one or more additional substrates.31. The imaging sensor of claim 30 , wherein each pixel sub-column bus on the first substrate is at least partially superimposed relative to a corresponding circuit sub-column bus on the one or more additional substrates claim 30 , wherein the first substrate and the one or more additional substrates are in a stacked configuration.32. The imaging sensor ...

Semiconductor chip and method of processing a semiconductor chip

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer. 1. A semiconductor chip comprising:a contact area formed at a frontside of the semiconductor chip, wherein a passivation layer is arranged at the frontside adjoining the contact area in a boundary region of the contact area;a multilayer metallization stack comprising an adhesion promoter layer, a contact layer and a planar protection layer, wherein the contact layer is arranged between the adhesion promoter layer and the protection layer,wherein only the adhesion promoter layer of the multilayer metallization stack is formed above at least portions of the contact area, the boundary region and portions of the passivation layer and the contact layer and the planar protection layer are formed only above portions of the contact area.2. The semiconductor chip according to claim 1 , wherein the multilayer metallization stack extends over at least portions of the contact area while at the boundary region only the adhesion promoter layer remains claim 1 , so that sidewalls of the contact layer and the planar protection layer are exposed to the boundary region and the adhesion layer extends laterally over the contact area and the passivation layer claim 1 , wherein the passivation layer is partially free of the adhesion layer.3. The ...

STRESS SENSOR FOR A SEMICONDUCTOR DEVICE

In a particular embodiment, an apparatus includes a stress sensor located on a first side of a semiconductor device. The apparatus further includes circuitry located on a second side of the semiconductor device. The stress sensor is configured to detect stress at the semiconductor device. In another particular embodiment, a method includes receiving data from a stress sensor located on a first side of a packaged semiconductor device. The packaged semiconductor device includes circuitry located on a second side of the packaged semiconductor device. The data indicates stress detected by the stress sensor. The method further includes performing a test associated with the packaged semiconductor device based on the data. 1. An apparatus comprising:a stress sensor located on a first side of a semiconductor device; andcircuitry located on a second side of the semiconductor device,wherein the stress sensor is configured to detect stress at the semiconductor device.2. The apparatus of claim 1 , wherein the stress sensor is configured to detect stress imposed on the circuitry.3. The apparatus of claim 2 , wherein the circuitry comprises an analog circuit.4. The apparatus of claim 1 , further comprising a package claim 1 , wherein the semiconductor device claim 1 , the stress sensor claim 1 , and the circuitry are integrated within the package.5. The apparatus of claim 4 , further comprising a second semiconductor device that is integrated within the package claim 4 , wherein the stress sensor is configured to detect stress imposed on the semiconductor device by the second semiconductor device.6. The apparatus of claim 1 , further comprising a connector formed on the second side of the semiconductor device claim 1 , the connector configured to couple the second side of the semiconductor device to a substrate via a flip chip process during an assembly process that connects the semiconductor device to the substrate.7. The apparatus of claim 6 , wherein the connector comprises a ...

Multiple bond via arrays of different wire heights on a same substrate

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array. 1. A method , comprising:obtaining a substrate;forming a first bond via array of first wire bond wires (“first wires”) extending from a surface of the substrate;forming a second bond via array of second wire bond wires (“second wires”) extending from the surface of the substrate;wherein the first bond via array and the second bond via array are external to the substrate;wherein the first bond via array is disposed within a region of the second bond via array;wherein the first wires of the first bond via array are of a first height; andwherein the second wires of the second bond via array are of a second height greater than the first height for a package-on-package configuration.2. The method according to claim 1 , further comprising:coupling a first die to the first bond via array; andcoupling a second die to the second bond via array disposed over the first die.3. The method according to claim 2 , wherein the first die and at least a portion of the second die are located within a perimeter of the second bond via array.4. The method according to claim 2 , further comprising coupling opposing surfaces of the first die and the second die to one another.5. The method according to claim 2 , further comprising attaching the first wires of the first bond via array and the second wires of the second bond via array by fusion bonding to the surface of the ...

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

LEAD CARRIER STRUCTURE AND PACKAGES FORMED THEREFROM WITHOUT DIE ATTACH PADS

A lead carrier includes a continuous sheet of mold compound having a top side and an opposing back side, and forms an array of package sites corresponding to semiconductor packages. Each package site when fabricated includes a semiconductor die having a top side, and an opposing treated base exposed at the back side of the continuous sheet of mold compound; a set of terminal pads, each having a top side and an opposing back side exposed at the back side of the continuous sheet of mold compound; a plurality of wire bonds formed between a set of input/output junctions on the top side of the semiconductor die and the top side of each terminal pad; and hardened mold compound encapsulating the semiconductor die, the set of terminal pads, and the plurality of wire bonds. Each package site excludes a die attach pad to which the semiconductor die is fixed. 1. A lead carrier for assembling packaged semiconductor die encapsulated in a mold compound , the lead carrier comprising: a semiconductor die having a top side and an opposing treated base that is exposed at the back side of the continuous sheet of mold compound;', 'a set of terminal pads, each terminal pad having a top side and an opposing back side that is exposed at the back side of the continuous sheet of mold compound;', 'a plurality of wire bonds formed between a set of input/output junctions on the top side of the semiconductor die and the top side of each terminal pad within the set of terminal pads; and', 'hardened mold compound that encapsulates the semiconductor die, the set of terminal pads, and the plurality of wire bonds., 'a continuous sheet of mold compound having a top side and an opposing back side, the continuous sheet of mold compound comprising an array of package sites, each package site corresponding to a semiconductor die package, each package site comprising2. The lead carrier of claim 1 , wherein each package site excludes a die attach pad to which the semiconductor die is fixed.3. The lead ...

Multilayer pillar for reduced stress interconnect and method of making same

A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

Fabricating pillar solder bump

A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

Semiconductor device and method for manufacturing the same

A semiconductor device PKG includes a semiconductor chip CP, a lead LD3, a wire BW5 electrically connecting a pad electrode PD2 of the semiconductor chip CP to the lead LD3, a wire BW3 electrically connecting a pad electrode PD3 of the semiconductor chip CP to the lead LD3, and a sealing body sealing them with a resin. The semiconductor chip CP includes internal circuits 5b and 5c, and a switch circuit unit SW. Signal transmission is possible between the internal circuit 5c and the pad electrode PD3. The switch circuit unit SW is a circuit capable of being set in a first state in which signal transmission is possible between the internal circuit 5b and the pad electrode PD2, and in a second state in which signal transmission is not possible between the internal circuit 5b and the pad electrode PD2. The switch circuit unit SW is fixed to the second state during operation of the semiconductor device PKG.

3D Printed Hermetic Package Assembly and Method

A method is provided. The method includes one or more of removing existing ball bonds from an extracted die, placing the extracted die into a recess of a hermetic substrate, the extracted die having a centered orientation in the recess, and applying a side fill compound into the recess between the extracted die and the hermetic substrate. The method also includes 3D printing, by a 3D printer, a plurality of bond connections between die pads of the extracted die and first bond pads of the hermetic substrate in order to create a 3D printed die substrate, and 3D printing a hermetic encapsulation over the die, the side fill compound, and the 3D printed bond connections in order to create a hermetic assembly. The extracted die includes a fully functional semiconductor die removed from a previous package. The hermetic substrate includes the first bond pads coupled to second bond pads.

Bump structure having a side recess and semiconductor structure including the same

In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

INTEGRATED CIRCUIT PACKAGE

An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces. 1. An integrated circuit (IC) package comprising:an IC die having a first side and a second side opposite the first side;a bump pad on the first side;a first substrate having a first side with a plurality of electrical contact surfaces;a plurality of metal pillars, each having a first end attached to the bump pad via a passivation layer, and a second end attached to one of a plurality of electrical contact surfaces of a first substrate;an intermetallic compound surrounding portions of the plurality of metal pillars; anda mold compound encapsulating the intermetallic compound.2. The IC package of claim 1 , wherein the plurality of metal pillars include copper.3. The IC package of claim 1 , wherein the intermetallic compound comprises a copper and lead compound.4. The IC package of claim 3 , wherein the copper and lead compound comprises CuSn.5. The IC package of claim 3 , wherein the copper and lead compound comprises CuSn.6. The IC package of further comprising a second substrate attached to the second side of the IC die.7. The IC package of claim 6 , wherein the mold compound encapsulates at least a portion of the IC die claim 6 , and the first and second substrates.8. The IC package of claim 6 , wherein said first substrate comprises a first leadframe and wherein said second substrate comprises a second leadframe.9. The IC package of claim 1 , wherein the intermetallic compound has higher melting temperatures than solder and lower coefficients of expansion than solder.10. An integrated circuit (“IC”) package comprising:an IC die ...

PACKAGE METHOD FOR GENERATING PACKAGE STRUCTURE WITH FAN-OUT INTERFACES

A semiconductor package structure includes an encapsulant, a chip module, at least one auxiliary conduction block, and a redistribution layer. The chip module is encapsulated by the encapsulant. The chip module has a chip. Each of the at least one auxiliary conduction block has a plurality of auxiliary conductive bumps and a mold layer encapsulating the plurality of auxiliary conductive bumps. The redistribution layer is disposed on the encapsulant. The redistribution layer is used to electrically connect the chip of the chip module and the at least one auxiliary conduction block. 1. A semiconductor package structure , comprising:a chip module having a chip, the chip encapsulated by a first mold layer;at least one auxiliary conduction block, each of the at least one auxiliary conduction block having a plurality of auxiliary conductive pillars and a second mold layer encapsulating the plurality of auxiliary conductive pillars;an encapsulant encapsulating the first mold layer and the second mold layer; anda redistribution layer disposed on the encapsulant, the redistribution layer being configured to electrically connect the chip of the chip module and the at least one auxiliary conduction block,wherein the chip module, the at least one auxiliary conduction block, and the encapsulant are coplanar to each other.2. The semiconductor package of claim 1 , further comprising:a plurality of conduction bumps correspondingly disposed on the chip module and the at least one auxiliary conduction block and configured to electrically connect the chip of the chip module and the at least one auxiliary conduction block to the redistribution layer.3. The semiconductor package of claim 1 , whereineach of the at least one auxiliary conduction block further having a conductive layer disposed on the second mold layer, the conductive layer being patterned to form electrical connection among the plurality of auxiliary conductive pillars.4. The semiconductor package of claim 1 , wherein the ...

Method for manufacturing semiconductor device and adhesive for mounting flip chip

The present invention aims to provide a method for producing a semiconductor device, the method being capable of achieving high reliability by suppressing voids. The present invention also aims to provide a flip-chip mounting adhesive for use in the method for producing a semiconductor device. The present invention relates to a method for producing a semiconductor device, including: step 1 of positioning a semiconductor chip on a substrate via an adhesive, the semiconductor chip including bump electrodes each having an end made of solder; step 2 of heating the semiconductor chip at a temperature of the melting point of the solder or higher to solder and bond the bump electrodes of the semiconductor chip to an electrode portion of the substrate, and concurrently to temporarily attach the adhesive; and step 3 of removing voids by heating the adhesive under a pressurized atmosphere, wherein the adhesive has an activation energy ΔE of 100 kJ/mol or less, a reaction rate of 20% or less at 2 seconds at 260° C., and a reaction rate of 40% or less at 4 seconds at 260° C., as determined by differential scanning calorimetry and Ozawa method.

Design Scheme for Connector Site Spacing and Resulting Structures

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. 1. A device comprising:a first contact pad on a first substrate, the first contact pad having a first line of symmetry and a second line of symmetry, the first line of symmetry being perpendicular to the second line of symmetry, the first contact pad having a first width along the first line of symmetry, the first contact pad having a second width along the second line of symmetry;a first underbump metallization on the first contact pad; anda first conductive bump on the first underbump metallization, the first conductive bump, having a third line of symmetry and a fourth line of symmetry, the third line of symmetry being perpendicular to the fourth line of symmetry, the first conductive bump having a third width along the third line of symmetry, the first conductive bump having a fourth width along the fourth line of symmetry, the third width being greater than the first width, the fourth width being less than the second width.2. The device of claim 1 , wherein the first width is equal to the second width.3. The device of claim 1 , wherein the first width is different from the second width.4. The device of further comprising:a second contact pad on the first substrate; ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Anisotropic conductive film structures

Anisotropic conductive film (ACF) structures and manufacturing methods for forming the same are described. The manufacturing methods include preventing clusters of conductive particles from forming between adjacent bonding pads and that are associated with electrical shorting of ACF structures. In some embodiments, the methods involve use of multiple layered ACF materials that include a non-electrically conductive layer that reduces the likelihood of formation of conductive particle clusters between bonding pads. In some embodiment, the methods include the use of ultraviolet sensitive ACF material combined with lithography techniques that eliminate conductive particles from between neighboring bonding pads. In some embodiments, the methods involve the use of insulation spacers that block conductive particles from entering between bonding pads. Any suitable combination of the described methods can be used.

Copper pillar bump and flip chip package using same

Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.

Semiconductor device having a boundary structure, a package on package structure, and a method of making

A semiconductor device includes a substrate and a first conductive pad on a top surface of the substrate. The semiconductor device further includes a boundary structure on the top surface of the substrate around the conductive pad.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate, a package, first conductors and second conductors. The substrate includes a first surface and a second surface opposite to the first surface. The package is disposed over the substrate. The first conductors are disposed over the substrate. The second conductors are disposed over the substrate, wherein the first conductors and the second conductors are substantially at a same tier, and a width of the second conductor is larger than a width of the first conductor. 1. A semiconductor device , comprising:a substrate including a first surface and a second surface opposite to the first surface;a package over the substrate;a plurality of first conductors over the substrate;a plurality of second conductors over the substrate, wherein the plurality of first conductors and the plurality of the second conductors are substantially at a same tier, and a width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors;a plurality of first bonding pads on the substrate and configured to receive and electrically connect to the plurality of first conductors, respectively;a plurality of second bonding pads on the substrate and configured to receive and electrically connect to the plurality of second conductors, respectively; anda passivation layer over the substrate, wherein the passivation layer includes a plurality of first recesses exposing the plurality of first bonding pads respectively, and a plurality of second recesses exposing the plurality of second bonding pads respectively, and a width of the first recess is wider than a width of the second recess, wherein the first conductor is apart from an edge of the respective first recess, and the second conductor is in contact with an edge of the respective second recess.2. The semiconductor device of claim 1 , wherein a volume of a second conductor of the plurality of second conductors is substantially ...

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. A device comprising:a substrate;an electrical interconnect within the substrate;a barrier structure electrically connected to the electrical interconnect, the barrier structure having a funnel-shaped recess defined therein; andsolder positioned within the funnel-shaped recess of the barrier structure.2. The device of claim 1 , further comprising:a copper structure positioned within the funnel-shaped recess of the barrier structure; anda nickel structure positioned within the funnel-shaped recess of the barrier structure.3. The device of claim 1 , wherein the barrier structure comprises tantalum claim 1 , tungsten claim 1 , titanium nitride claim 1 , or combinations thereof.4. The device of claim 1 , further comprising:a semiconductor device having a via and an under bump metal (UBM) electrically connected to the via, and wherein the UBM is encased in the solder within the funnel-shaped recess of the barrier structure.5. The device of claim 4 , wherein the UBM includes angled sidewalls.6. The device of claim 5 , wherein the angled sidewalls of the UBM are configured to produce a wetting force between the substrate and the semiconductor device during thermal compression bonding.7. The device of claim 4 , wherein the ...

Structures for Providing Electrical Isolation in Semiconductor Devices

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 1. A semiconductor package structure comprising:a printed circuit board (PCB) or package substrate;an interposer bonded to the PCB or package substrate through first solder bumps disposed on a first side of the interposer, the first solder bumps having a first pitch; anda plurality of semiconductor chips, each of the semiconductor chips (i) being bonded to a second side of the interposer through second solder bumps having a second pitch that is less than the first pitch, and (ii) comprising a substrate with one or more transistors or integrated circuits formed thereon.2. The semiconductor package structure of claim 1 , wherein adjacent semiconductor chips bonded to the interposer are separated by air gaps or insulating passivation material claim 1 , the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.3. The semiconductor package structure of claim 1 , wherein the semiconductor chips are bonded to the second side of the interposer in an arrangement that minimizes distances between adjacent semiconductor chips bonded to the interposer.4. The semiconductor package structure of claim 1 , wherein diameters of the first solder bumps are greater than diameters of the second solder bumps.5. The semiconductor package structure of claim 1 , wherein the interposer comprises silicon material and conductive lines and conductive vias formed ...

SEMICONDUCTOR PACKAGE

Provided is a semiconductor package, including: a lower package to which elements are mounted; a metal post connected to the lower package and including at least one metal material portion; and an upper package to which elements is mounted, and which is connected to the metal post via a solder ball. 1. A semiconductor package , comprising:a lower package to which elements are mounted;a metal post connected to the lower package and including at least one metal material portion; andan upper package to which elements is mounted, and which is connected to the metal post via a solder ball.2. The semiconductor package of claim 1 , wherein the metal material portion has a surface treatment layer formed on a surface thereof.3. The semiconductor package of claim 2 , wherein the surface treatment layer is formed an upper surface and a side of the metal post.4. The semiconductor package of claim 2 , wherein the surface treatment layer is made of at least one metal material of Au and Ni.5. The semiconductor package of claim 1 , wherein the metal post is configured such that a width of one end of the metal post connected to the solder ball is smaller than that of another end.6. The semiconductor package of claim 1 , wherein a width of the metal post increases gradually from the one end connected to the solder ball to the other end.7. The semiconductor package of claim 1 , wherein the metal post is configured such that a width of one end is formed in 50% to 90% of a width of another end.8. The semiconductor package of claim 1 , wherein the metal post is configured such that a surface in a longitudinal direction is inclined at an angle of 5° to 45° with respect to a surface of a substrate of the lower package.9. The semiconductor package of claim 1 , wherein the one end of the metal post connected to the solder ball is entered into the solder ball.10. The semiconductor package of claim 1 , wherein the metal post is made of at least one material of Cu claim 1 , Sn claim 1 , Pb ...

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch. 1. A semiconductor device package , comprising:a first conductive layer having a first pitch,a second conductive layer having a second pitch and arranged at two different sides of the first conductive layer;a third conductive layer having a third pitch and disposed above the first conductive layer and the second conductive layer, the third conductive layer electrically connected to the first conductive layer, wherein the first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch;a first dielectric layer surrounding the first conductive layer; anda second dielectric layer surrounding the first dielectric layer, the second conductive layer and a portion of the third conductive layer.2. The semiconductor device package as claimed in claim 1 , further comprising:a first die disposed on the third conductive layer; anda second die disposed adjacent to the first die and on the third conductive layer, wherein the first die is electrically connected to the second die through the first conductive layer.3. The semiconductor device package as claimed in claim 2 , whereinthe first die is disposed over a first portion of the first conductive layer and a first portion of the second conductive layer adjacent to the first portion of the first conductive layer; andthe second die is disposed over a second portion of the first conductive layer and a second ...

Semiconductor package structure

The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.

WIRE BONDING DEVICE AND METHOD OF ELIMINATING DEFECTIVE BONDING WIRE

A method of eliminating a defective bonding wire is provided, including moving a bonding member from a first region of a carrier to a second region of the carrier if the bonding wire of the bonding member is defective, and cooperatively operating a movement member and the bonding member so as to cause the defective bonding wire to be removed from the bonding member and bonded to the second region of the carrier, thereby auto-debugging the bonding member and improving the production efficiency. 1: A wire bonding device , comprising:a carrier having a first region used for performing a wire bonding process and a second region positioned outside the first region;a bonding member for receiving a bonding wire; anda movement member for moving the bonding member to the first region of the carrier so as to perform the wire bonding process, wherein when the bonding wire is defective, the movement member and the bonding member are cooperatively operated so as to cause the defective bonding wire to be removed from the bonding member and bonded to the second region of the carrier.2: The device of claim 1 , further comprising a sensor for sensing whether the bonding wire of the bonding member is defective.3: The device of claim 1 , wherein the bonding member comprises:a nozzle for outputting the bonding wire; anda clamp for holding the bonding wire.4: The device of claim 1 , wherein a bondable block is formed in the second region of the carrier for debugging the bonding member.5: The device of claim 1 , wherein the carrier comprises a plurality of carrying members and the first region and the second region are positioned on different ones of the carrying members.6: A method of eliminating a defective bonding wire claim 1 , comprising the steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'providing a wire bonding device of ;'}moving the bonding member to the second region of the carrier when the bonding wire of the bonding member is defective; andcooperatively operating ...

Apparatus and method for manufacturing semiconductor device

A manufacturing apparatus of a semiconductor device includes a stage, a head unit configured to face the stage, a driving unit configured to move the head unit towards and away from the stage, a heating unit configured to heat the head unit, and a control unit configured to control the driving unit to move the head unit away from the stage when the heating unit heats the head unit.

BVA INTERPOSER

A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds. 1. (canceled)2. A microelectronic package comprising:a dielectric encapsulation having first and second oppositely-facing surfaces;a plurality of wire bonds extending between the first and second surfaces, each wire bond having first and second opposite ends at the respective first and second surfaces, and an edge surface between the first and second ends contacted by the encapsulation and separated from the edge surfaces of adjacent wire bonds by the encapsulation;a redistribution structure having one or more layers overlying the first or second surface of the encapsulation and including a plurality of electrically conductive traces extending in one or more lateral directions substantially parallel to the first surface, the traces electrically connected to the first or second ends of at least some of the wire bonds;a microelectronic element having a front surface having element contacts thereat electrically connected with at least some of the electrically conductive traces, a rear surface opposite the front surface, and edge surfaces extending between the front and rear surfaces, the microelectronic element disposed at least partially within the dielectric encapsulation, with the edge surfaces at least partially covered by the ...

CHIP MOUNTING STRUCTURE

Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate. 1. A method for changing a shape of a substrate to reduce stress exerted on an interlayer insulating layer of a chip , the method comprising:providing the substrate;mounting the chip on the substrate such that a center of the chip corresponds to a center of the substrate and such that sides of the chip are parallel to sides of the substrate;measuring a distance B between a side of the chip and a nearest side of the substrate; andcutting off square portions of the substrate from each corner of the substrate such that a distance between a corner of the chip and a nearest corner of the substrate is less than the distance B.2. The method of claim 1 , wherein each square portion has sides of a length c.4. A method for mounting a chip on a substrate claim 1 , the method comprising:providing a chip having an interlayer insulating layer, the interlayer insulating layer having a low dielectric constant;mounting the chip to a substrate such that there is a distance B between a side of the chip and a nearest side of the substrate;connecting the chip to the substrate using flip-chip bumps; andcutting off right-angle isosceles triangle portions of the substrate from each ...

Package on package structure and method of manufacturing the same

A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same. 2. The semiconductor device of claim 1 , wherein the plurality of pads comprise four non-solder mask defined (NSMD) pads in the four corners of the regular array and a plurality of solder mask defined (SMD) pads disposed away from the four corners of the regular array.3. The semiconductor of claim 2 , wherein each of the four NSMD pads is adjacent to one of the SMD pads in a same horizontal row and another one of the SMD pads in a same vertical column.4. The semiconductor device of claim 1 , wherein the first vertical distances are similar to the second vertical distances.5. The semiconductor device of claim 1 , wherein the first vertical distances are different from the second vertical distances.6. The semiconductor device of claim 1 , wherein a first distance is defined as a distance between the center point and each of the four first recess portions claim 1 , and the first distance is greater than at least one of the first vertical distance and the second vertical distance.7. The semiconductor device of claim 6 , wherein a second distance is defined as a distance between the center point and each of the second recess portions claim 6 , and the second distance is less than the first vertical distance and the second ...

Electronic package and method for fabricating the same

An electronic package includes a circuit structure having a first electronic component disposed on one side thereof, and a second electronic component and conductive pillars disposed on the other side thereof. The second electronic component and the conductive pillars are encapsulated by an encapsulant, and end faces of the conductive pillars are exposed from the encapsulant, allowing the exposed end faces to be connected to an external circuit board. As the end faces of the conductive pillars are used as contact structures, fine-pitch electronic packages can be achieved. Also, by providing sufficient space attributed to the tall columnar structures of the conductive pillars, the second electronic component of an appropriate thickness can be obtained, allowing the electronic package to be suitable for applications requiring high voltages and/or high currents. A method for fabricating an electronic package is further provided.

MEASUREMENTS OF AN INTEGRATED CIRCUIT CHIP AND CONNECTED CHIP CARRIER TO ESTIMATE HEIGHT OF INTERCONNECT

Systems and methods are provided for obtaining measurements of an integrated circuit chip and a connected carrier to obtain the measurements of the interconnect heights. More specifically, a method is provided that includes defining a top best fit reference plane and a bottom best fit reference plane, and adjusting the top best fit reference and the bottom best fit reference to be superposed to one another. The method further includes calculating first distances between each height measurement for a first set of points and the adjusted top best fit reference plane, and calculating second distances between each height measurement for a second set of points and the adjusted bottom best fit reference plane. The method further includes calculating height values of a gap or interconnect between the first substrate and the second substrate by subtracting the thickness of the first substrate and the second distances from the first distances. 1. A method of manufacturing an integrated circuit chip assembly , comprising:defining a top reference plane from measurement heights of a plurality of top reference points on a top surface of a first substrate;defining a bottom reference plane from measurement heights of a plurality of bottom reference points on a bottom surface of the first substrate;adjusting data from the top reference plane and data from the bottom reference plane such that the top reference plane and the bottom reference plane are superposed to one another;obtaining measurement heights of a first set of points on an external surface of a second substrate using an x, y, z coordinate measuring system in relation to data from the top reference plane;calculating first distances between each measurement height of the first set of points on the external surface of the second substrate and the adjusted top reference plane;obtaining measurement heights of a second set of points on the bottom surface of the first substrate using the x, y, z coordinate measuring system in ...

Advanced Device Assembly Structures And Methods

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element. 1. A microelectronic assembly , comprising:a first substrate having a first surface and first conductive elements;a second substrate having a second surface and second conductive elements; anda plurality of electrically conductive masses, each mass joined to a respective pair of the first and second conductive elements,wherein each electrically conductive mass includes a first material, a second material, and a third material, the third material selected to increase the melting point of an alloy including the third material and at least one of the first material or the second material,wherein a concentration of the first material varies from a relatively higher amount at a location disposed toward the respective first conductive element to a relatively lower amount toward the respective second conductive element,wherein a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the respective second conductive element to a relatively lower amount toward the respective first conductive element, andwherein the third material has a highest concentration at a location ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. 2. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in a regular array including a plurality of horizontal rows and a plurality of vertical columns.3. The semiconductor device of claim 1 , wherein the plurality of pads comprise a plurality of non-solder mask defined (NSMD) pads and a plurality of solder mask defined (SMD) pads.4. The semiconductor of claim 3 , wherein the first recess portion entirely exposes one of the NSMD pads claim 3 , and the second recess portion partially exposes one of the SMD pads.5. The semiconductor device of claim 1 , wherein first recess portion is disposed on a corner of the semiconductor device and the second recess portion is disposed away from the corner of the semiconductor device.6. The semiconductor device of claim 1 , wherein the first distance between the central point and the first edge is greater than a fourth distance between the central point and the second recess portion claim 1 , and the second distance between the central point and the second edge is greater than the fourth distance between the central point and the second recess portion.7. A semiconductor device claim 1 , comprising:a substrate comprising a pair of first edges parallel to each other, a pair of second edges orthogonal to the first edge, ...

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

BONDING PAD STRUCTURE, BONDING RING STRUCTURE, AND MEMS DEVICE PACKAGING METHOD

The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a plurality of first metal blocks made of a first metal material; and a plurality of second metal blocks made of a second metal material. The plurality of first metal blocks are used to prevent the squeezing out and extending of the plurality of second metal blocks. On at least one equal dividing plane of the bonding pad structure, the first metal material is shown at least one time; and the second metal material is shown at least one time. 1. A bonding pad structure , comprising:a plurality of first metal blocks made of a first metal material; anda plurality of second metal blocks made of a second metal material, the plurality of first metal blocks are used to protect squeezing out and extending of the second metal blocks; and', 'on at least one equal dividing plane of the bonding pad structure the first metal material is shown at least one time and the second metal material is shown at least one time., 'wherein2. The bonding pad structure according to claim 1 , on top viewing plane claim 1 , wherein:the plurality of first metal blocks and the plurality of second metal blocks are distributed into columns and rows alternatively;one second metal block is disposed between two adjacent first metal blocks in each row; andone first metal block is disposed between two adjacent second metal blocks in each column.3. The bonding pad structure according to claim 2 , further comprising:a first metal ring enclosing the plurality of first metal blocks and the second metal blocks on a top viewing plane of the bonding pad structure.4. The bonding pad structure according to claim 1 , wherein:the plurality of first metal blocks are a plurality of first metal stripes;the plurality of second metal blocks are a plurality of metal stripes; andthe plurality of first metal stripes and the plurality of second metal stripes are ...

Cu pillar bump with l-shaped non-metal sidewall protection structure

A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure.

Method of manufacturing electronic component module and electronic component module

A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.

SELECTIVE AREA HEATING FOR 3D CHIP STACK

A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively. 1. A method of forming a 3D package comprising:electromechanically joining an interposer to a laminate chip carrier with a first plurality of solder bumps by applying a first selective non-uniform heat, a first selective non-uniform cooling, and a first uniform pressure to the first plurality of solder bumps, the first selective non-uniform heat is a temperature less than the reflow temperature of the first plurality of solder bumps, the first selective non-uniform heat and the first selective non-uniform cooling are each applied simultaneously to a top surface of the interposer, a bottom surface of the laminate chip carrier, or both the top surface of the interposer and the bottom surface of the laminate chip carrier; andelectromechanically joining a top chip to the interposer with a second plurality of solder bumps by applying a second selective non-uniform heat and a second uniform pressure to the second plurality of solder bumps, the second selective non-uniform heat is a temperature less than the reflow temperature of the second plurality of solder bumps.2. The method of claim 1 , ...

Integrated circuit with bump connection scheme

An integrated circuit includes first and second bump pads spaced from each other with a first space, configured to receive differential signals for a normal operation, and at least one redundant bump pad spaced from the first bump pad with a second space smaller than the first space, configured to receive a signal for a repair to the differential signals.

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core. 1. A pillar-type connection comprising:a first conductive layer that includes a hollow core; anda second conductive layer coupled to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core.2. The pillar-type connection of claim 1 , further comprising:a conductive via that terminates at a top surface of the first conductive layer; anda plating mask that includes an opening aligned with the conductive via.3. The pillar-type connection of claim 2 , further comprising:a sacrificial plug disposed within the opening;wherein the top surface of the conductive pillar is adjusted using factors comprising at least one of dimensions of the sacrificial plug and height of the hollow core before removing the sacrificial plug.4. The pillar-type connection of claim 3 , further comprising:vertical surfaces aligned parallel to sidewalls of the opening in the plating mask and inclined surfaces connecting a horizontal surface and a vertical surface to define a cavity, wherein the sacrificial plug has a top surface, and the first conductive layer is formed inside the opening by depositing the first conductive layer such that the top surface of the first conductive layer is recessed relative to the top surface of the sacrificial plug.5. The pillar-type connection of claim 2 , wherein the sacrificial plug is formed as part of a different plating mask.6. The pillar-type connection of claim 3 , further comprising:a feature on a package, the feature attached to the conductive pillar using a solder body, wherein the recess is dimensioned to receive the feature so that the feature is self-aligned with the conductive pillar during assembly.7. The pillar-type ...

ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE

The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device. 116-. (canceled)17. A method of manufacturing a semiconductor device , comprising the steps , of:(a) providing a wiring board having an upper surface, a plurality of electrodes formed on the upper surface, solder materials respectively formed over the electrodes of the wiring board, and a lower surface opposite to the upper surface;(b) after the step (a), applying a first solder paste to the upper surface of the wiring board;(c) after the step (b), mounting an electronic component over the upper surface of the wiring board via the first solder paste;(d) after the step (c), carrying out reflow/cleaning on the first solder paste;(e) after the step (d), applying flux to the solder materials;(f) after the step (e), carrying out reflow/cleaning on the solder materials; and(g) after the step (f), positioning a semiconductor chip over the upper surface of the wiring board such that a main surface of the semiconductor chip faces the upper surface of the wiring board, and electrically connecting a plurality of bumps comprised of solder material and formed over the main surface of respectively, by melting the bumps of the semiconductor chip, contacting the bumps of the semiconductor chip to the solder materials of the wiring board, respectively, melting the solder materials of the wiring board, and subsequently scrubbing the bumps of the semiconductor chip and the ...

METHOD OF MANUFACTURING SUBSTRATE STRUCTURE WITH FILLING MATERIAL FORMED IN CONCAVE PORTION

Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased. 113-. (canceled)14: A method for manufacturing a substrate structure , comprising:providing a substrate body including a plurality of electrical contact pads;forming an insulating protection layer on the substrate body and the electrical contact pads, wherein the insulating protection layer includes a plurality of openings exposing the electrical contact pads;forming at least one hole on the insulating protection layer, the hole extending into at least one of the electrical contact pads to form at least one concave portion on the electrical contact pad; andforming a filling material in the concave portion.15: The method of claim 14 , wherein the filling material is further formed in the concave portion.16: A method for manufacturing a substrate structure claim 14 , comprising:providing a substrate body including a plurality of electrical contact pads, wherein at least one of the electrical contact pads includes at least one concave portion; andforming an insulating protection layer on the substrate body, and forming a filling material in the concave portion, wherein the insulating protection layer includes a plurality of openings exposing the electrical contact pads.17: The method of claim 16 , wherein the concave portion ...

Prevention of bridging between solder joints

A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.

INTERCONNECT STRUCTURES FOR FINE PITCH ASSEMBLY OF SEMICONDUCTOR STRUCTURES

A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided. 1. A method for fabricating a semiconductor structure , comprising:providing a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces;providing one or more interconnect pads having first and second opposing surfaces and one or more sides, wherein the first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections;applying an isolating layer having first and second opposing surfaces, wherein the first surface of the isolating layer is disposed over the second surface of the substrate and the second surfaces and one or more sides of the interconnect pads;forming openings having a predetermined shape in select portions of the isolating layer extending between the second surface of the isolating layer and the first surface of the isolating layer;providing one or more pad interconnects having a pad portion and an ...

Three-dimensional structure in which wiring is provided on its surface

One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Package on Package Structure and Method of Manufacturing the Same

A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate. 1. A package on package structure , comprising:a first substrate having a first region and a second region;a bump formed on the first region of the first substrate, wherein the bump comprises a metallic structure and a plurality of minor elements, wherein the metallic structure comprises a central core formed of a metal material and a solder material layer surrounding the central core;a first semiconductor die bonded to the second region of the first substrate; anda semiconductor die package bonded to the first substrate, wherein the first semiconductor die is between the package and the first substrate, and wherein the semiconductor die package comprises a connector bonded to the bump, and further comprising an air gap between an exposed surface of the first semiconductor die and the semiconductor die package.2. The package on package structure of claim 1 , wherein the plurality of minor elements are dispersed in the solder material surrounding the central core.3. The package on package structure of claim 2 , wherein the plurality of minor elements are further dispersed in the central core.4. The package on package structure of claim 1 , wherein the central core is formed of copper or a copper alloy.5. The package on package structure of claim 1 , wherein the plurality of minor elements comprises germanium (Ge) claim 1 , zinc (Zn) indium (In) claim 1 , nickel (Ni) claim 1 , phosphorus (P) claim 1 ...

Bonded Structures for Package and Substrate

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small. 1. A semiconductor device package , comprising:a substrate with a contact pad;a semiconductor die bonded to the contact pad by a first bonding structure; andwherein the first bonding structure includes a metal ball comprising a non-solder material, a solder layer over a surface of the non-solder material, and an intermediate layer between the solder layer and the non-solder material, wherein the intermediate layer is configured to prevent formation of an intermetallic compound between the metal ball and the solder layer, wherein the non-solder material includes copper, aluminum, silver, gold, nickel, tungsten, alloys thereof, or combinations thereof, and the intermediate layer comprises titanium.2. The semiconductor device package of claim 1 , wherein a width or diameter of the metal ball is in a range from about 100 μm to about 200 μm.3. The semiconductor device package of claim 1 , wherein the semiconductor device package has another metal ball next to the metal ball claim 1 , and a pitch of the metal ball and the another metal ball is in a range from about 150 μm to about 300 μm.4. The semiconductor device package of claim 1 , wherein the solder layer is a continuous layer that coats the intermediate layer.5. The semiconductor device package of claim 1 , wherein the metal ball is arranged over and electrically ...

MOUNTING STRUCTURE AND METHOD FOR MANUFACTURING SAME

A mounting structure includes a bonding material () that bonds second electrodes () of a circuit board () and bumps () of a semiconductor package (), the bonding material () being surrounded by a first reinforcing resin (). Moreover, a portion between the outer periphery of the semiconductor package () and the circuit board () is covered with a second reinforcing resin (). Even if the bonding material () is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained. 1. A mounting structure comprising:a semiconductor package having first electrodes;a circuit board having second electrodes;a bonding material containing solder that is disposed between the second electrode and a bump formed on the first electrode and electrically bonds the bump and the second electrode;a first reinforcing resin covering a circumference of the bonding material; anda second reinforcing resin covering a portion between an outer periphery of the semiconductor package disposed on the circuit board and the circuit board,wherein a relationship is established: a melting point of the bump>a reaction starting temperature of the second reinforcing resin≧a reaction starting temperature of the first reinforcing resin>a melting point of the bonding material.2. The mounting structure according to claim 1 , wherein the bump contains a solder material.3. The mounting structure according to claim 1 , wherein the first reinforcing resin and the second reinforcing resin are in contact with each other.4. The mounting structure according to claim 1 , wherein the first reinforcing resin and the second reinforcing resin contain resin components with an identical composition and contain different curing agents.5. The mounting structure according to claim 1 , wherein the bump has an alloy composition of a Sn material claim 1 , and the bonding material is a Sn material.6. The mounting structure according to claim 1 , wherein the bump has an alloy ...

Method and Apparatus for Image Sensor Packaging

A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.

PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed. 1. A method of forming a plurality of microelectronic devices on a semiconductor workpiece , the method comprising:placing a plurality of first interconnect elements on a side of a semiconductor workpiece;forming a layer on the side of the workpiece;reshaping the first interconnect elements by heating the first interconnect elements; andcoupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed, wherein the second portion is opposite the first portion.2. The method of wherein:the semiconductor workpiece comprises a plurality of dies and a redistribution structure on the dies, the redistribution structure including a plurality of terminals;placing the first interconnect elements on the workpiece comprises forming the first interconnect elements on corresponding terminals of the redistribution structure;forming the layer on the workpiece comprises molding a protective layer onto the workpiece;the individual first interconnect elements comprise a proximal end at the side of the workpiece and a distal end opposite the proximal end;reshaping the first interconnect elements comprises forming a generally flat surface at the distal end of the individual first interconnect elements;coupling the detached second interconnect elements comprises ...

BUMP LAYOUT FOR COPLANARITY IMPROVEMENT

A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas. 1. A method comprising:receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area;grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, wherein a bump pattern density of the second region is lower than that of the first region;forming a second design by modifying the first design, wherein modifying the first design comprises modifying a cross-section area of the second group of conductive bumps in the second region; andforming the conductive bumps on the first surface of the interposer in accordance with the second design, wherein after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.2. The method of claim 1 , wherein a size of the first group of conductive bumps remain unchanged in the first design and the second design.3. The method of claim 1 , ...

Bump-on-Trace Design for Enlarge Bump-to-Trace Distance

A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

BALL GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A BGA semiconductor package includes a semiconductor device adhered by adhesive to a substrate, and a conductive micro ball fitted into a through-hole provided in the substrate. A bonding wire electrically connects the semiconductor device and the micro ball to each other. An encapsulation member made of resin encapsulates the semiconductor device, the adhesive, part of the micro ball, and the bonding wire, only on a surface side of the substrate on which the semiconductor device is mounted. At least a part of a bottom surface of the micro ball has an exposed portion as an external connection terminal, which is exposed through the through-hole provided in the substrate as a bottom surface of the encapsulation member. 1. A BGA semiconductor package , comprising:a semiconductor device;a substrate on which the semiconductor device is mounted;an adhesive for adhering the semiconductor device and the substrate to each other;a micro ball having conductivity, the micro ball having a part fitted into a through-hole provided in the substrate;a bonding wire for electrically connecting the semiconductor device and the micro ball to each other; andan encapsulation member for encapsulating, with an encapsulation resin, the semiconductor device, the adhesive, a part of the micro ball which is not fitted into the through-hole, and the bonding wire, only on a surface side of the substrate on which the semiconductor device is mounted,at least a part of a bottom surface of the micro ball having an exposed portion as an external connection terminal, exposed through the through-hole provided in the substrate which forms a bottom surface of the encapsulation member.2. A BGA semiconductor package according to claim 1 , wherein the substrate is made of an insulator of any one of a resin claim 1 , a glass epoxy claim 1 , a ceramics claim 1 , and a glass.3. A BGA semiconductor package according to claim 1 , wherein the through-hole provided in the substrate has a cylindrical shape.4. A BGA ...

LEAD STRUCTURE OF CIRCUIT

The present invention discloses a lead structure of the circuit, which comprises a first lead and a second lead. The first lead includes a first bump connecting part and a first lead segment. The first lead segment is connected to the first bump connecting part. The width of the first lead segment is smaller than the width of the first bump connecting part. The second lead is adjacent to the first lead and there is a lead gap therebetween. The second lead also includes a second bump connecting part and a first lead segment. The first lead segment of the second lead is connected to the second bump connecting part. The second bump connecting part and the first bump connecting part are arranged staggeredly. The second bump connecting part is adjacent to the first lead segment of the first lead. 1. A lead structure of the circuit , comprising:a first lead, including a first bump connecting part and a first lead segment, said first lead segment connected to said first bump connecting part, and the width of said first lead segment is smaller than the width of said first bump connecting part; anda second lead, adjacent to said first lead, having a lead gap between said second lead and said first lead, including a second bump connecting part and a first lead segment, said first lead segment of said second lead connected to said second bump connecting part, said first bump connecting part and said second bump connecting part arranged staggeredly, and said second bump connecting part adjacent to said first lead segment of said first lead.2. The lead structure of the circuit of claim 1 , wherein the width of said first lead segment of said second lead is smaller than the width of said second bump connecting part.3. The lead structure of the circuit of claim 1 , wherein said first lead segment of said first lead is adjacent to said first lead segment of said second lead; said first lead segment of said first lead and said first lead segment of said second lead form a gap ...

Chip stack with electrically insulating walls

A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.

PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES

Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a stand-off layer over a plurality of microelectronic dies on a semiconductor workpiece, and removing selected portions of the stand-off layer to form a plurality of stand-offs with the individual stand-offs positioned on a backside of a corresponding die. The method further includes cutting the semiconductor workpiece to singulate the dies, and attaching the stand-off on a first singulated die to a second die. 1. A system , comprising a microelectronic device including:a support member;a first microelectronic die including a backside attached to the support member, an active side opposite the backside, a plurality of terminals at the active side, and an integrated circuit operably coupled to the terminals;a stand-off attached to the active side of the first die; anda second microelectronic die including a backside, an active side opposite the backside, a plurality of terminals at the active side, and an integrated circuit operably coupled to the terminals, wherein the backside of the second die is attached to the stand-off without an adhesive between the stand-off and the backside of the second die.2. The system of wherein the stand-off is positioned inboard the terminals on the first die.3. The system of claim 1 , further comprising:a plurality of wire-bonds electrically connecting the terminals on the first die to the support member; andan adhesive section positioned between the stand-off and the first die;wherein the wire-bonds project a first distance in a first direction from the first die; andwherein the stand-off and adhesive section project a second distance in the first direction from the first die, the second distance being greater than the first distance.4. The system of wherein the support member comprises a lead frame.5. The system of wherein the ...

COPPER-CONTAINING C4 BALL-LIMITING METALLURGY STACK FOR ENHANCED RELIABILITY OF PACKAGED STRUCTURES AND METHOD OF MAKING SAME

The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device. 1. A process of forming an integrated circuit device comprising:forming a metal pad over a substrate;forming a metal first layer above and on the metal pad, the metal first layer comprising TiW and having a thickness up to 4,000 Angstrom (Å);forming a metal second layer above and on the metal adhesion first layer;forming a metal stud third layer above and on the metal second layer;forming a solder bump above and on the metal third layer,wherein the forming the metal second layer and the forming the metal third layer comprises 'plating a copper stud through a mask that is disposed over the metal second layer.', 'sputtering a copper metal second layer over the metal adhesion first layer under conditions to impart a compressive stress therein; and'}2. A process of forming an integrated circuit device comprising:forming a metal pad disposed on a substrate;forming a metal first layer covering the metal pad, the metal first layer comprising TiW and having a thickness up to 4,000 Angstrom (Å);electroplating a metal stud over the metal first layer, the metal stud comprising copper and having a thickness between 5 micrometer (m) and 15 μm;coupling an electrically conductive bump with the metal stud, wherein the electrically conductive bump comprises a solder including lead and tin; andforming an intermetallic layer between the metal stud and the electrically conductive bump, wherein the intermetallic layer comprises a portion of the metal stud and a portion the electrically conductive bump, and wherein the intermetallic layer is encapsulated between the electrically conductive bump and the metal stud.3. The process of claim 2 , further comprising disposing a metal second layer on the metal first layer claim 2 , ...

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion. 1. A semiconductor package comprising:a first semiconductor chip structure comprising a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part; anda second semiconductor chip structure comprising a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion,wherein the first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.2. The semiconductor package of claim 1 , further comprising a glue layer provided between the first passivation layer and the second passivation layer.3. The semiconductor package of claim 2 , wherein the conductive bump comprises a conductive pillar and a conductive solder disposed on the conductive pillar.4. The semiconductor ...