Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 736. Отображено 100.
18-04-2013 дата публикации

VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130095634A1
Автор: Mikawa Takumi, Takahashi Ichirou
Принадлежит:

Provided is a method for manufacturing a variable resistance nonvolatile storage device, which prevents electrical conduction between lower electrodes and upper electrodes of variable resistance elements in the memory cell holes. The method includes: forming lower copper lines; forming a third interlayer insulating layer; forming memory cell holes in the third interlayer insulating layer, an opening diameter of upper portions of the memory cell holes being smaller than bottom portions; forming a metal electrode layer on the bottom of each memory cell holes by sputtering; embedding and forming a variable resistance layer in each memory cell hole; and forming upper copper lines connected to the variable resistance layer embedded and formed in each memory cell hole. 1. A manufacturing method for manufacturing a variable resistance nonvolatile storage device , the method comprising:(a) forming plural lower lines above a substrate;(b) forming an interlayer insulating layer on the plural lower lines and above the substrate;(c) forming, in the interlayer insulating layer, plural memory cell holes penetrating to surfaces of the plural lower lines, an opening diameter of upper portions of the plural memory cell holes being smaller than an opening diameter of bottom portions;(d) forming a metal electrode layer at least on a bottom of each of the plural memory cell holes by sputtering;(e) embedding and forming a variable resistance layer in each of the plural memory cell holes, the variable resistance layer being connected to the metal electrode layer; and(f) forming, on the interlayer insulating layer and the variable resistance layer, plural upper lines connected to the variable resistance layer embedded and formed in each of the plural memory cell holes.2. The manufacturing method according to claim 1 ,wherein step (c) includes:(i) forming, in the interlayer insulating layer, plural memory cell holes penetrating to the surfaces of the plural lower lines, an opening diameter ...

Подробнее
Номер записи: 1
25-04-2013 дата публикации

Phase Change Memory and Manufacturing Method Therefor

Номер: US20130099193A1
Автор: HONG James, HU MINDA
Принадлежит:

The present invention discloses a phase change memory and a manufacturing method thereof. The phase change memory according to the present invention uses top electrodes provided on the top of storage nodes to heat the storage nodes such that a phase change layer in the storage nodes undergoes a phase change. In the phase change memory of embodiments of the present invention, the contact area between the top electrode and the storage node is relatively small, which is good for phase change. Moreover, each column of storage nodes is connected by the same linear top electrode, which can improve photo alignment shift margin. 1. A phase change memory unit , comprising:a plurality of storage nodes each including a phase change layer; anda top electrode provided on the storage nodes, with one end of the top electrode being electrically connected to more than one of the storage nodes and an opposite end of the top electrode being electrically coupled to a bit line,wherein when a current is applied to the top electrode, the top electrode is configured to heat the storage nodes such that the respective phase change layers each undergo a phase change.2. The phase change memory unit of claim 1 , wherein claim 1 , the storage nodes are each connected to a word line via a diode.3. The phase change memory unit of claim 1 , wherein claim 1 , said top electrode comprises a metal.4. The phase change memory unit of claim 1 , wherein claim 1 , said top electrode comprises Ti or TiN.5. The phase change memory unit of claim 1 , wherein claim 1 , said phase change layer includes a germanium claim 1 , stibium and tellurium (GST) material.6. The phase change memory unit of claim 1 , wherein the top electrode contacts upper surfaces of the storage nodes claim 1 , and wherein an area of contact between the top electrode and the respective upper surface of each storage node is smaller than the respective upper surface of each storage node.7. A phase change memory array claim 1 , comprising: a ...

Подробнее
Номер записи: 2
01-08-2013 дата публикации

PHASE-CHANGE MEMORY

Номер: US20130196467A1
Автор: Chen Frederick T.
Принадлежит: Higgs Opl. Capital LLC

A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact. 1. A method , comprising:forming a dielectric layer on a first electrical contact;forming a second electrical contact on the dielectric layer, wherein the second electrical contact comprises a terminal;forming an opening passing through the second electrical contact, the dielectric layer, and the first electrical contact;filling a phase-change material into at least part of the opening, wherein both the first electrical contact and the second electrical contact interface the phase-change material at one or more sidewalls of the phase-change material; andforming an electrode contacting the terminal.2. The method of claim 1 , further comprising forming a non-metallic layer on a bottom electrode claim 1 , wherein the first electrical contact is electrically coupled to the bottom electrode claim 1 , and wherein the phase-change material is separated from the bottom electrode by the non-metallic layer.3. The method of claim 2 , wherein the non-metallic layer and the bottom electrode create a ladder-like ...

Подробнее
Номер записи: 3
03-10-2013 дата публикации

MEMORY DEVICE MANUFACTURING METHOD WITH MEMORY ELEMENT HAVING A METAL-OXYGEN COMPOUND

Номер: US20130260528A1
Автор: HO ChiaHua, Lai Erh-Kun
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element. 1. A method for manufacturing a memory device , the method comprising:provide a substrate;forming a doped region in the substrate;forming a plug electrically coupled with the doped region;forming a memory element on the plug, the memory element comprising at least one metal-oxygen compound, wherein the memory element and the plug being aligned in a first direction, the first direction being perpendicular to the substrate and the memory element and the plug having the same width, the width measured perpendicular to the first direction; andforming an electrode on the memory element.2. The method according to claim 1 , wherein the electrode comprises a barrier material on the memory element.3. The method according to claim 1 , wherein the doped region comprises a drain on an access transistor.4. The method according to claim 1 , wherein the plug comprises tungsten.5. The method according to claim 1 , wherein the electrode comprises a bit line claim 1 , and further comprising a source line extending in a second direction claim 1 , the second direction being parallel to the substrate and generally perpendicular to the first direction.6. A method for manufacturing a memory device claim 1 , the method comprising:providing a transistor having a source and a drain;forming a memory ...

Подробнее
Номер записи: 4
31-10-2013 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

Номер: US20130285006A1
Автор: CHOI Jungdal, PARK Jintaek, Park Youngwoo
Принадлежит:

A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode, variable resistance patterns between the word lines and the vertical electrode, and an insulating isolation layer between the word lines. The variable resistance patterns are spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer. 1. A variable resistance memory device , comprising:a selection transistor on a substrate, the selection transistor including a first doped region and a second doped region;a vertical electrode coupled to the first doped region of the selection transistor;a bit line coupled to the second doped region of the selection transistor;a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode;variable resistance patterns between the word lines and the vertical electrode; andan insulating isolation layer between the word lines, the variable resistance patterns being spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer.2. The device as claimed in claim 1 , wherein:the word lines include a first word line and a second word line that are located at a same level from the top surface of the substrate and that are spaced apart from each other with the vertical electrode interposed therebetween, andthe variable resistance patterns include first and second variable resistance patterns that are adjacent to the first and second word lines, respectively, and that are separated from each other.3. The device as claimed in claim 1 , wherein a dielectric constant of the insulating isolation layer is less than a dielectric ...

Подробнее
Номер записи: 5
14-11-2013 дата публикации

Method of Forming Semiconductor Device Having Self-Aligned Plug

Номер: US20130302966A1
Автор: Byoung-Jae Bae, Chul-Ho Shin, Dong-Hyun Im, Doo-Hwan Park, Gyu-Hwan OH, Ik-Soo Kim, Kyoung-Ha EOM, Sang-Sup Jeong, Sung-Lae Cho, Sung-Un Kwon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Подробнее
Номер записи: 6
26-12-2013 дата публикации

NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE GROUP, AND MANUFACTURING METHOD THEREOF

Номер: US20130341582A1
Автор: HONDA MOTONARI, SUMINO JUN
Принадлежит: SONY CORPORATION

A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity. 1. A nonvolatile memory device group comprising:(A) a first insulating layer;(B) a second insulating layer that has a concavity and that is disposed on the first insulating layer;(C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the concavity;(D) an information storage layer that is formed on the side wall and the bottom surface of the concavity; and(E) a conductive material layer that is filled in a space surrounded with the information storage layer in the concavity.2. The non-volatile memory device group according to claim 1 , wherein the number of electrodes is N claim 1 ,wherein a nonvolatile memory device is formed by the electrodes, the information storage layer, and the conductive material layer, andwherein the nonvolatile memory device group includes N nonvolatile memory devices.3. The non-volatile memory device group according to claim 1 , wherein the information storage layer includes a resistance change layer that stores information by a change in electrical resistance.4. The non-volatile memory device group according to claim 3 , wherein the resistance change layer has a laminated structure of a high resistance layer and an ion ...

Подробнее
Номер записи: 7
26-12-2013 дата публикации

Memory Arrays and Methods of Forming Memory Cells

Номер: US20130341587A1
Автор: Bez Roberto, Fratin Lorenzo, Pellizzer Fabio
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction. 131-. (canceled)32. A method of forming a plurality of memory cells , comprising:forming a stack over a semiconductor base; the stack comprising a homogeneous n-type doped region, a p-type doped region, and an ovonic material over the p-type doped region;patterning the stack into rails, with the rails extending along a first direction, the rails being spaced from one another by first trenches;filling the first trenches with first electrically insulative material;patterning the rails into pillars, the patterning into the pillars comprising etching into but not entirely through the homogeneous n-type doped region to form a portion of the homogeneous n-type doped region into segments within the pillars, and to leave some of the homogeneous n-type doped region as first conductive lines interconnecting the pillars along the first direction; the patterning forming second trenches which extend along a second direction that intersects ...

Подробнее
Номер записи: 8
06-02-2014 дата публикации

Nonvolatile Memory Cells And Methods Of Forming Nonvolatile Memory Cells

Номер: US20140034896A1
Автор: Ramaswamy D.V. Nirmal, Sandhu Gurtej S.
Принадлежит: MICRON TECHNOLOGY, INC.

A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed. 139-. (canceled)40. A method of forming a nonvolatile memory cell , comprising:forming a first electrode comprising a first current conductive material and a second current conductive material different in composition from the first current conductive material within an opening in dielectric material, at least a portion of the second current conductive material being laterally surrounded by the first current conductive material;elevationally etching the dielectric material in which the opening is received and elevationally etching the first current conductive material to leave second current conductive material projecting elevationally outward from the first current conductive material, the etching leaving all of the second current conductive material entirely within the elevational thickness of the dielectric material in which the opening is received;forming a programmable region over the first current conductive material and over the projecting second current conductive material of the first electrode; andforming a second electrode over the programmable region.41. The method of wherein all of the second current ...

Подробнее
Номер записи: 9
20-03-2014 дата публикации

NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING NONVOLATILE MEMORY ELEMENT

Номер: US20140077144A1
Автор: Yoneda Shinichi
Принадлежит: Panasonic Corporation

A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer between the first and second electrodes. The variable resistance layer having a resistance value that reversibly changes according to an electrical signal provided between the electrodes. The variable resistance layer includes a first variable resistance layer and a second variable resistance layer. The first variable resistance layer comprises a first metal oxide. The second variable resistance layer is planar and includes a first part and a second part. The first part comprises a second metal oxide and is planar. The second part comprises an insulator and is planar. The second metal oxide has a lower oxygen deficient degree than that of the first metal oxide. The first and second parts are in contact with different parts of a main surface of the first variable resistance layer which faces the second variable resistance layer. 1. A nonvolatile memory element , comprising:a first electrode;a second electrode; anda variable resistance layer between the first electrode and the second electrode, the variable resistance layer having a resistance value that reversibly changes according to an electrical signal applied between the first electrode and the second electrode,wherein the variable resistance layer includes at least a first variable resistance layer and a second variable resistance layer,the first variable resistance layer comprises a first metal oxide,the second variable resistance layer is planar and includes a first part and a second part, the first part comprising a second metal oxide and being planar, and the second part comprising an insulator and being planar,the second metal oxide has a lower oxygen deficient degree than an oxygen deficient degree of the first metal oxide, andthe first part and the second part of the second variable resistance layer are in contact with different parts of a main surface of the first variable resistance layer, the ...

Подробнее
Номер записи: 10
20-03-2014 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20140080272A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Подробнее
Номер записи: 11
01-01-2015 дата публикации

PHASE-CHANGE MEMORY CELLS

Номер: US20150001457A1
Автор: Krebs Daniel, Sebastian Abu
Принадлежит:

Phase-change memory cells for storing information in a plurality of programmable cell states. A phase-change component is located between first and second electrodes for applying a read voltage to the phase-change component to read the programmed cell state. The component includes opposed layers of phase-change material extending between the electrodes. A core component extends between the electrodes in contact with respective inner surfaces of the opposed layers. An outer component extends between the electrodes in contact with respective outer surfaces of the opposed layers. At least one of the core and outer component is formed of electrically-conductive material and is arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than the amorphous phase of the phase-change material in any of said cell states. The current path has a length dependent on size of the amorphous phase in the opposed layers. 1. A phase-change memory cell for storing information in a plurality of programmable cell states , the memory cell comprising:a phase-change component, of phase-change material, located between a first and a second electrode for applying a read voltage to the phase-change component to read the programmed cell state, the phase-change component having opposed layers of said phase-change material extending between the first and second electrodes;a core component extending between the first and second electrodes in contact with respective inner surfaces of said opposed layers; andan outer component extending between the electrodes in contact with respective outer surfaces of said opposed layers,wherein at least one of the core component and the outer component is formed of an electrically-conductive material and is arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than an amorphous phase of said phase-change material in any of said programmed cell states, said lower-resistance ...

Подробнее
Номер записи: 12
13-01-2022 дата публикации

METHOD OF FORMING MULTI-BIT RESISTIVE RANDOM ACCESS MEMORY CELL

Номер: US20220013718A1
Автор: YANG PO-YU
Принадлежит: UNITED MICROELECTRONICS CORP.

A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell. 1. A method of forming a multi-bit resistive random access memory cell , comprising:sequentially forming a first dielectric layer, a first bottom electrode, a second dielectric layer, a second bottom electrode, a third dielectric layer, a third bottom electrode and a fourth dielectric layer on a layer;performing a first etching process to pattern the fourth dielectric layer, the third bottom electrode, the third dielectric layer, the second bottom electrode, the second dielectric layer, the first bottom electrode and the first dielectric layer to forma through hole in the first dielectric layer, the first bottom electrode, the second dielectric layer, the second bottom electrode, the third dielectric layer, the third bottom electrode and the fourth dielectric layer; andforming a resistance layer conformally covering a sidewall of the through hole and filling a top electrode in the through hole, thereby the multi-bit resistive random access memory cell being formed.2. The method of forming the multi-bit resistive random access memory cell according to claim 1 , wherein the steps of forming the resistance layer conformally covering the sidewall of the through hole and filling the top ...

Подробнее
Номер записи: 13
07-01-2021 дата публикации

DIELECTRIC BARRIER AT NON-VOLATILE MEMORY TILE EDGE

Номер: US20210005810A1
Автор: BAKER Kevin L., BROWN Jay S., Chhabra Bhumika, GOOD Farrell M., Grubbs Robert K., HILL Ervin T.
Принадлежит:

An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles. 1. A non-volatile memory die comprising:multiple tiles of memory cells, each of the multiple tiles including a plurality of non-volatile memory cells, each of the non-volatile memory cells including a stack of materials including chalcogenide material;an oxidation barrier on a side wall of a trench between adjacent memory tiles; anda dielectric fill in the trench and over the oxidation barrier.2. The non-volatile memory die of claim 1 , wherein:the oxidation barrier comprises a silicon nitride film.3. The non-volatile memory die of claim 2 , wherein:the silicon nitride film has a density that is greater than 2.6 g/cm3.4. The non-volatile memory die of claim 1 , wherein:the oxidation barrier has a thickness in a range between 15-500 Angstroms.5. The non-volatile memory die of claim 1 , wherein:the oxidation barrier comprises multiple nitride films.6. The non-volatile memory die of claim 5 , wherein:the multiple nitride films include:a first nitride film and one or more second nitride films over the first nitride film, wherein the first nitride film is thicker than the one or more second nitride films.7. The non-volatile memory die of claim 1 , wherein:the trench between adjacent memory tiles includes tapered side walls.8. The non-volatile memory die of claim 7 , wherein:the oxidation barrier comprises a conformal layer over the tapered side walls of the trench.9. The non-volatile memory die of claim 1 , wherein:the oxidation barrier is further disposed on a bottom of the trench.10. The non-volatile memory die of claim 1 , wherein:the trench comprises a ...

Подробнее
Номер записи: 14
02-01-2020 дата публикации

SELF-ALIGNED REPEATEDLY STACKABLE 3D VERTICAL RRAM

Номер: US20200006427A1
Автор: "OBrien Kevin", CHANDHOK Manish, HAN Eungnak, HOURANI Rami, Kabir Nafees, LIN Kevin, Sato Noriyuki, Sharma Abhishek, Singh Gurpreet, Yoo Hui Jae
Принадлежит:

An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks. 1. An integrated circuit structure , comprising: a first block insulator layer; and', 'a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers; and, 'a first material block comprising a second block insulator layer; and', 'a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers; and, 'a second material block stacked on the first material block, comprisingat least one pillar extending through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.2. The integrated circuit structure of claim 1 , wherein the top width is less than approximately 100 nm.3. The integrated circuit structure of claim 1 , wherein the at least one pillar is self-aligned from the second material block to the first material block.4. The integrated circuit structure of claim 1 , wherein the at least one pillar exits the bottom of the ...

Подробнее
Номер записи: 15
02-01-2020 дата публикации

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) CELL WITH RECESSED BOTTOM ELECTRODE SIDEWALLS

Номер: US20200006653A1
Автор: Liu Shih-Chang, Tseng Yuan-Tai
Принадлежит:

Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element. 1. A method for forming an integrated circuit comprising a memory cell , the method comprising:forming a lower conductive layer on a substrate;forming a data storage layer overlying the lower conductive layer;forming an upper conductive layer overlying the data storage layer;patterning the upper conductive layer, the data storage layer, and the lower conductive layer to respectively form an upper electrode, a data storage element, and a lower electrode stacked on the substrate, wherein the patterning forms sidewall defects in storage sidewalls of the data storage element; andperforming an etch into the lower electrode to laterally recess electrode sidewalls of the lower electrode respectively relative to neighboring ones of the storage sidewalls.2. The method according to claim 1 , wherein the patterning comprises:performing a second etch into the data storage layer and the lower conductive layer to respectively form the data storage element and the lower electrode, wherein the storage sidewalls are respectively aligned with the electrode sidewalls upon completion of the second etch.3. The method according to claim 2 , wherein the second etch is ...

Подробнее
Номер записи: 16
02-01-2020 дата публикации

NON-VOLATILE MEMORY AND FABRICATION METHOD THEREOF

Номер: US20200006654A1
Автор: Chi Min-Hwa, HONG Zhong Shan, YING Zhan
Принадлежит:

Non-volatile memory and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a first conductive layer on the base substrate; forming an interlayer dielectric layer on the first conductive layer; forming a plurality of through holes exposing the first conductive layer in the interlayer dielectric layer; forming a catalyst layer on at least one of sidewall surfaces and bottom surfaces of the through holes; forming a carbon nanotube layer in the through holes by a catalytic chemical vapor deposition process; and forming a second conductive layer on the carbon nanotube layer and a portion of the interlayer dielectric layer. 1. A method for fabricating a non-volatile memory , comprising:providing a base substrate;forming a first conductive layer on the base substrate;forming an interlayer dielectric layer on the first conductive layer;forming a plurality of through holes exposing the first conductive layer in the interlayer dielectric layer;forming a catalyst layer on at least one of sidewall surfaces and bottom surfaces of the through holes;forming a carbon nanotube layer in the through holes by a catalytic chemical vapor deposition process; andforming a second conductive layer on the carbon nanotube layer and a portion of the interlayer dielectric layer.2. The method according to claim 1 , wherein forming the carbon nanotube layer in the through holes by the catalytic chemical vapor deposition process comprises:introducing a carbon source gas into the through holes; anddisassociating the carbon source gas into free carbon atoms under an action of the catalyst layer and depositing the free carbon ions on the through holes to form the carbon nanotube layer.3. The method according to claim 2 , wherein:{'sub': 2', '4, 'the carbon source gas includes at least one of COand CF; and'}a temperature of the catalytic chemical vapor deposition process is in a range of approximately 300° C.-600° C.4. The method according to ...

Подробнее
Номер записи: 17
27-01-2022 дата публикации

Phase-change memory device having reversed phase-change characteristics and phase-change memory having highly integrated three-dimensional architecture using same

Номер: US20220029094A1
Автор: Yun Heub Song
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

Подробнее
Номер записи: 18
15-01-2015 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20150014621A1
Автор: JUNG Ha Chang, LEE Gi A
Принадлежит: SK HYNIX INC.

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate, a lower electrode formed in a bottom of each of the holes, a first spacer formed on the lower electrode and a sidewall of each of the holes, a second spacer formed on an upper sidewall of the first spacer, a third spacer formed on a lower sidewall of the first spacer below the second spacer, a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole, and an upper electrode formed on the variable resistance part to be buried in each hole. 1. A variable resistance memory device , comprising:a multi-layered insulating layer including a plurality of holes formed on a semiconductor substrate;a lower electrode formed in a bottom of each of the holes;a first spacer formed on the lower electrode and a sidewall of each of the holes;a second spacer formed on an upper sidewall of the first spacer to a predetermined height;a third spacer formed on a lower sidewall of the first spacer below the second spacer;a variable resistance part that is formed on the lower electrode has a height lower than a height of a top of each hole; andan upper electrode formed on the variable resistance part to be buried in each hole.2. The variable resistance memory device of claim , wherein the multi-layered insulating layer includes:a first insulating layer formed on the lower electrode and formed of nitride;a second insulating layer formed on the first insulating layer and formed of oxide;a third insulating layer formed on the second insulating layer and formed of the nitride; anda fourth insulating layer formed on the third insulating layer and formed of the oxide.3. The variable resistance memory device of claim 2 , wherein the second spacer is formed through selectively oxidizing the first spacer.4. ...

Подробнее
Номер записи: 19
10-01-2019 дата публикации

Replacement materials processes for forming cross point memory

Номер: US20190013358A1
Автор: DerChang Kau, Gianpaolo Spadini, Jong-Won Lee, Stephen W. Russell
Принадлежит: Micron Technology Inc

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.

Подробнее
Номер записи: 20
10-01-2019 дата публикации

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190013466A1
Автор: KANG DAE-HWAN, KOH Gwan-hyeob, Park Il-mok
Принадлежит:

A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions. 1. (canceled)235.-. (canceled)36. A memory device , comprising:a plurality of first conductive lines on a substrate, the first conductive lines being spaced apart from each other and extending in a first direction;a plurality of second conductive lines on the plurality of first conductive lines, the second conductive lines being spaced apart from each other and extending in a second direction that is different from the first direction;a plurality of first memory cells respectively arranged at a plurality of cross points between the plurality of first conductive lines and the plurality of second conductive lines, each of the first memory cells having a structure that includes a first selection device layer, a first middle electrode layer, a first variable resistance layer, and a first top electrode layer, wherein the first middle electrode layer is disposed between the first selection device layer and the first variable resistance layer; anda plurality of first insulating structures arranged alternately with the plurality of first memory cells in ...

Подробнее
Номер записи: 21
09-01-2020 дата публикации

PCRAM STRUCTURE

Номер: US20200013951A1
Автор: WU Jau-Yi
Принадлежит:

A memory device includes the following items. A substrate. A bottom electrode disposed over the substrate. An insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer. A heater disposed in the through hole. A phase change material layer disposed over the heater. A selector layer disposed over the phase change material layer. An intermediate layer disposed over the through hole. Also, a metal layer disposed over the selector layer. The metal layer is wider than the phase change material layer. 1. A memory device comprising:a substrate;a bottom electrode disposed over the substrate;an insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer;a heater disposed in the through hole;a phase change material layer disposed over the heater;a selector layer disposed over the phase change material layer;an intermediate layer over the through hole; anda metal layer disposed over the selector layer.2. The memory device of claim 1 , wherein the intermediate layer is wider than a diameter of the through hole.3. The memory device of claim 1 , wherein the metal layer is wider than the phase change material layer.4. The memory device of claim 1 , wherein the phase change material layer is disposed in the through hole.5. The memory device of claim 1 , wherein the selector layer is disposed in the through hole.6. The memory device of claim 1 , wherein the intermediate layer contacting the metal layer.7. The memory device of claim 1 , wherein the intermediate layer is formed of at least one of carbon and tungsten.8. The memory device of claim 1 , wherein the metal layer functions as a top electrode.9. A memory device comprising:a substrate;a bottom electrode disposed over the substrate;a first heater disposed over the bottom electrode;a first phase change material layer disposed over the first heater;a first selector layer disposed over the first ...

Подробнее
Номер записи: 22
18-01-2018 дата публикации

DYNAMIC LOGIC MEMCAP

Номер: US20180017870A1
Автор: GE NING, Li Zhiyong, Williams R. Stanley, Yang Jianhua
Принадлежит: Hewlett-Packard Development Company, L.P.

An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic. 1. An integrated circuit , comprising:a substrate with a plurality of transistors formed in the substrate, the plurality of transistors coupled to a first metal layer formed over the plurality of transistors; anda plurality of high dielectric nanometer capacitors formed of memristor switch material creating an active region between the first metal layer and a second metal layer formed over the plurality of high dielectric memcaps, wherein the plurality of high dielectric memcaps are to operate as memory storage cells in dynamic logic.2. The integrated circuit of claim 1 , wherein the memristor switch material is formed of memristor switch oxide of the first metal layer and additionally operational as memristors.3. The integrated circuit of wherein the memristor switch material active region is formed of memristor switch elemental or compound semiconductor and doped with mobile dopants to allow for memristor operation.4. The integrated circuit of claim 2 , further comprising a second plurality of transistors coupled between respective plurality of high dielectric nanometer memcaps and a programming source to allow for programming the memristors.5. The integrated circuit of wherein the dynamic logic is to operate as a set of shift registers.6. The integrated circuit of wherein the set of shift registers is to control a set of fluid jet resistors.7. The integrated circuit of wherein the set of shift registers have set/reset functionality by programming the ...

Подробнее
Номер записи: 23
21-01-2016 дата публикации

PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20160020393A1
Автор: CHUNG Chil-Hee, Park Tae-Jin, SONG Yoon-jong
Принадлежит:

A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit.

Подробнее
Номер записи: 24
03-02-2022 дата публикации

THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY AND METHOD MAKING IT POSSIBLE TO OBTAIN SUCH A MEMORY

Номер: US20220037398A1
Автор: EL HAJJAM Khalil
Принадлежит:

A memory includes a memory cell including a planar electrode in a first plane; a floating electrode in a second plane, parallel to the first plane; a vertical electrode. The planar electrode includes a first part facing a first part of the floating electrode, the first part of the planar electrode and the first part of the second electrode being separated by a first layer of a first active material, the vertical electrode includes a part facing a second part of the floating electrode, the first part of the vertical electrode and the second part of the floating electrode being separated by a second layer of a second active material. The first active material forms a selector or a memory point and the second active material forms a memory point or a selector. The planar and floating electrodes not sharing any plane parallel to the first or second plane. 2. The memory according to claim 1 , wherein the first layer of a first insulator material is separated from the second layer of a second active material by a second separation distance claim 1 , the second distance being chosen as a function of the nature of the active material.5. The method according to wherein claim 3 , when the step of deposition or growth of a third layer of a third insulator material is a deposition step claim 3 , then the deposition step comprises:a first sub-step of deposition of a third layer of a third insulator material;a second sub-step of anisotropic etching of the third layer of a third insulator material.6. The method according to wherein the step of deposition or growth of a third layer of a third insulator material is a thermal growth step.7. The method according to claim 3 , wherein the conductor material is selected from TiN claim 3 , TaN claim 3 , TaCN claim 3 , Ta claim 3 , Ti claim 3 , W claim 3 , Cu claim 3 , Ru claim 3 , Mo claim 3 , Co claim 3 , C claim 3 , Al and/or Ag claim 3 , or an alloy comprising at least two of said metals.8. The method according to claim 3 , wherein ...

Подробнее
Номер записи: 25
18-01-2018 дата публикации

TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT

Номер: US20180019390A1
Автор: CHANG Chih-Yang, Chen Hsia-Wei, Chu Wen-Ting, Liao Yu-Wen, Shih Sheng-Hung, Tu Kuo-Chi, Yang Chin-Chieh, You Wen-Chun
Принадлежит:

Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess. 1. An integrated circuit device , comprising:a bottom electrode;a dielectric layer disposed over the bottom electrode;a top electrode disposed over the dielectric layer, wherein an upper surface of the top electrode comprises a tapered recess; anda via disposed over the top electrode, wherein the via establishes electrical contact with an inner sidewall of the tapered recess but not with a central bottom surface of the tapered recess.2. The integrated circuit device of claim 1 , further comprising:a dielectric material arranged under the via and contacting the central bottom surface of the tapered recess of the top electrode.3. The integrated circuit device of claim 2 , wherein the dielectric material further comprises outer sidewalls that contact a bottom inner sidewall of the tapered recess under the via.4. The integrated circuit device of claim 1 , further comprising:sidewall spacers disposed over the bottom electrode and along outer sidewalls of the top electrode.5. The integrated circuit device of claim 1 , wherein the top electrode comprises:a central upper electrode portion having a first thickness; anda peripheral upper electrode portion having a second thickness that differs from the first thickness.6. The integrated circuit device of claim 5 , wherein the first thickness is less than the second thickness.7. The integrated circuit device of claim 5 , wherein the first thickness is half of or less than half of the second thickness.8. The integrated circuit device of claim 1 , wherein the ...

Подробнее
Номер записи: 26
17-01-2019 дата публикации

VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF FORMING THE SAME

Номер: US20190019950A1
Автор: Eun Sung-Ho, JEONG Ji-Hyun, Kim Sungwon, Park Ilmok, PARK JUNGHOON, Song Seulji
Принадлежит:

Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines, 1. A variable resistance memory device comprising:a substrate comprising a cell region and a peripheral region, the cell region comprising a boundary region being in contact with the peripheral region;a plurality of first conductive lines extending in a first direction on the substrate;a plurality of second conductive lines extending in a second direction and traversing the plurality of first conductive lines;a plurality of variable resistance structures, each of the plurality of variable resistance structures being at one of a plurality of intersecting points of the plurality of first conductive lines and the plurality of second conductive lines; anda plurality of bottom electrodes between the plurality of first conductive lines and the plurality of variable resistance structures,wherein one of the plurality of first conductive lines is electrically insulated from one of the plurality of variable resistance structures that is on the boundary region and overlaps the one of the plurality of first conductive lines.2. The claim 1 , variable resistance memory device of claim 1 , further comprising:an insulating pattern that is on the boundary region and is between the one of the plurality of first ...

Подробнее
Номер записи: 27
21-01-2021 дата публикации

Phase change memory cell with second conductive layer

Номер: US20210020833A1
Автор: Junli Wang, Juntao Li, Kangguo Cheng, Ruilong Xie
Принадлежит: International Business Machines Corp

A method may include forming a via opening in a dielectric layer, depositing a first conductive layer along a bottom and a sidewall of the via opening, depositing a second conductive layer on top of the first conductive layer. The method may further include recessing the first conductive layer to form a trench and exposing a sidewall of the second conductive layer, depositing a non-conductive material in the trench, and depositing a phase change material layer on top of the dielectric layer. The top surface of the second conductive layer may be in direct contact with a bottom surface of the phase change material layer.

Подробнее
Номер записи: 28
26-01-2017 дата публикации

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20170025475A1
Автор: Ode Hiroyuki, TAKAGI Takeshi, TANAKA Toshiharu, YAMAGUCHI Takeshi, Yamato Masaki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics. 1. A memory device comprising:a first wiring extending in a first direction;a second wiring extending in a second direction crossing the first direction; anda resistance change film provided between the first wiring and the second wiring, a first conductive layer; and', 'a first intermediate layer including a first region provided between the first conductive layer and the resistance change film, and, 'the second wiring includingthe first intermediate layer including a material having nonlinear resistance characteristics.2. The device according to claim 1 , wherein the first intermediate layer includes at least one material selected from the group consisting of silicon nitride claim 1 , titanium oxide claim 1 , tantalum oxide claim 1 , and niobium oxide.3. The device according to claim 1 , wherein a second region; and', 'a third region, and, 'the first intermediate layer further includesthe first conductive layer is disposed between the second region and the third region in the first direction.4. The device according to claim 1 , wherein the first intermediate layer has a thickness in a third direction crossing the first direction and the second direction of not less than 1 nm and not more than 5 nm.5. The device according to claim 1 , wherein a bandgap of a material included in the first intermediate layer is smaller than a bandgap of a material included in the resistance change film.6. The device according to claim 1 , further ...

Подробнее
Номер записи: 29
28-01-2016 дата публикации

FORMING SELF-ALIGNED CONDUCTIVE LINES FOR RESISTIVE RANDOM ACCESS MEMORIES

Номер: US20160028002A1
Автор: Pellizzer Fabio, Petruzza Pietro, Tortorelli Innocenzo
Принадлежит:

Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines. 1. A method , comprising:forming a stack, wherein the stack includes a barrier layer;forming a first plurality of trenches and a second plurality of trenches in the barrier layer, wherein trenches of the first plurality of trenches are spaced from each other by trenches of the second plurality of trenches;filling the first plurality of trenches with a dielectric material;filling the second plurality of trenches with metal; andusing said metal as a hard mask, removing said stack to form a plurality of stacks separated by the second plurality of trenches.2. The method of claim 1 , wherein forming a stack comprises:forming a chalcogenide layer between a heater layer and an electrode layer; andforming the barrier layer on the electrode layer.3. The method of claim 1 , further comprising:forming a plurality of electrodes separated by an insulator, wherein the stack is formed on a top surface of the plurality of electrodes separated by the insulator.4. The method of claim 1 , wherein filling the second plurality of trenches with metal comprises filling the second plurality of trenches with copper based on a damascene process.5. The method of claim 1 , further comprising:forming a sealing layer over the plurality of stacks, wherein the sealing layer is formed on sidewalls of each stack of the plurality of stacks.6. The method of claim 5 , further comprising:removing the sealing layer from a top surface of each stack of the plurality of stacks.7. The method of claim 1 , wherein forming a first plurality of trenches and a second plurality of trenches in the barrier layer comprises:using a single photolithographic mask ...

Подробнее
Номер записи: 30
28-01-2016 дата публикации

Semiconductor device and method for fabricating the same, and microprocessor, processor, system, data storage system and memory system including the semiconductor device

Номер: US20160028011A1
Автор: Hye-Jung Choi, Su-Ock Chung
Принадлежит: SK hynix Inc

A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.

Подробнее
Номер записи: 31
24-01-2019 дата публикации

SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190027538A1
Автор: Matsuda Kazuhisa, Matsuo Kazuhiro, MORI Shinji, Morita Takaumi, OKUCHI Hisashi, Saito Yuta, SAWA Keiichi, Takahashi Atsushi, TANAKA Masayuki, Toratani Kenichiro
Принадлежит: Toshiba Memory Corporation

In one embodiment, a semiconductor storage device includes a first interconnect extending in a first direction, a plurality of second interconnects extending in a second direction different from the first direction, and a plurality of first insulators provided alternately with the second interconnects. The device further includes a resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape. 1. A semiconductor storage device comprising:a first interconnect extending in a first direction;a plurality of second interconnects extending in a second direction different from the first direction;a plurality of first insulators provided alternately with the second interconnects; anda resistance change film provided between the first interconnect and at least one of the second interconnects and including a first metal layer or a first semiconductor layer that includes a first face provided on a first interconnect side and a second face provided on a second interconnect side, at least any of the first face and the second face having a curved plane shape.2. The device of claim 1 , wherein the first face has a convex shape protruding to the first interconnect side or a concave shape recessed from the first interconnect side.3. The device of claim 1 , wherein the second face has a convex shape protruding to the second interconnect side or a concave shape recessed from the second interconnect side.4. The device of claim 1 , wherein the at least one of the second interconnects includes a third face provided on the first interconnect side and having a curved plane shape.5. The device of claim 4 , wherein the third face has a convex shape protruding to the first interconnect ...

Подробнее
Номер записи: 32
24-04-2014 дата публикации

VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20140113429A1
Автор: HWANG Youngnam, KANG Myung Jin
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane. 19-. (canceled)10. A method of manufacturing a variable resistance memory device , the method comprising:forming an ohmic layer on a substrate;forming a sacrificial pattern on the ohmic layer; the preliminary first electrode pattern including a first portion and a second portion,', 'the second portion of the preliminary first electrode pattern contacting a sidewall of the sacrificial pattern; and, 'forming a preliminary first electrode pattern,'}forming a preliminary ohmic pattern by removing a portion of the ohmic layer exposed by the sacrificial pattern and the preliminary first electrode pattern; 'the first portion of the preliminary first electrode pattern contacting the preliminary ohmic pattern;', 'exposing a sidewall of the first electrode pattern by removing the sacrificial pattern,'}forming a preliminary first spacer pattern on a sidewall of the preliminary first electrode pattern;forming an ohmic pattern by etching the preliminary ohmic pattern; andforming a variable resistance pattern and a second electrode pattern on the ohmic pattern.11. The method of claim 10 , further comprising:forming an insulation layer on the substrate, the insulation layer having a hole that exposes a top of the substrate;forming a first semiconductor pattern doped with a first impurity having a first conductive type to partially fill the hole; 'the second semiconductor pattern doped with a ...

Подробнее
Номер записи: 33
23-01-2020 дата публикации

Method for forming a phase change memory (pcm) cell with a low deviation contact area between a heater and a phase change element

Номер: US20200028075A1
Автор: Shih-Chang Liu, Yi Jen Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.

Подробнее
Номер записи: 34
23-01-2020 дата публикации

METAL LANDING ON TOP ELECTRODE OF RRAM

Номер: US20200028077A1
Автор: CHANG Chih-Yang, Chu Wen-Ting
Принадлежит:

Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer. 1. An integrated circuit (IC) including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer , a memory cell comprising:a bottom electrode disposed over the lower metal interconnect layer;a data storage or dielectric layer disposed over the bottom electrode;a top electrode disposed over the data storage or dielectric layer, wherein an upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer; andsidewall spacers arranged along sidewalls of the top electrode, and having bottom surfaces that rest on an upper surface of the data storage or dielectric layer.2. The IC of claim 1 , wherein the top electrode has an upper planar surface which extends continuously between sidewalls of the top electrode and which directly abuts the upper metal interconnect layer.3. The IC of claim 2 , wherein the bottom electrode has sidewalls which are aligned with the sidewalls of the top electrode.4. The IC of claim 1 , further comprising:a capping layer ...

Подробнее
Номер записи: 35
28-01-2021 дата публикации

RESISTIVE 3D MEMORY

Номер: US20210028231A1
Автор: ANDRIEU Francois
Принадлежит: Commissariat A L'Energie Atomique Et Aux Energies Alternatives

A memory device is provided support and several superimposed levels of resistive memory cells formed on the support, each level having one or more rows of one or more resistive memory cell(s), each resistive memory cell having a variable resistance memory element formed by an area of variable resistivity material arranged between first electrode and a second electrode. The memory element is connected to a source region or drain region of a control transistor, the control transistor being formed in a given semiconductor layer of a stack of semiconductor layers formed on the support and wherein respective channel regions of respective control transistors of resistive memory cells are arranged. 1. A memory device provided with a support and several superimposed levels of resistive memory cells formed on the support , each level including one or more rows of one or more resistive memory cell(s) , each resistive memory cell comprising a variable resistance memory element , formed of a variable resistivity material zone disposed between a first electrode and a second electrode , the memory element being connected to a source or drain region of a control transistor , the control transistor being formed into a given semi-conducting layer of a superimposition of semi-conducting layers formed on the support and in which respective channel regions of respective control transistors of resistive memory cells are arranged.2. The memory device according to claim 1 , wherein a first vertical column of cells of different levels includes a first cell of a first level and a second cell of a second level from the superimposed levels of cells claim 1 , the first cell and second cell being respectively provided with a first control transistor and second control transistor claim 1 , the first control transistor and second control transistor having a common gate electrode or having respective gate electrodes connected to each other and to a same conducting zone.3. The memory device ...

Подробнее
Номер записи: 36
28-01-2021 дата публикации

VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20210028357A1
Автор: Chung Jiyoon, Oh Gyuhwan, PAIK Junhwan, PARK Yongjin, YANG Jinwook
Принадлежит:

A variable resistance memory device includes a first conductive line structure having an adiabatic line therein on a substrate, a variable resistance pattern contacting an upper surface of the first conductive line structure, a low resistance pattern contacting an upper surface of the variable resistance pattern, a selection structure on the low resistance pattern, and a second conductive line on the selection structure. 1. A variable resistance memory device , comprising:a first conductive line structure on a substrate, the first conductive line structure having an adiabatic line therein;at least one variable resistance pattern contacting an upper surface of the first conductive line structure;a low resistance pattern contacting an upper surface of the at least one variable resistance pattern;a selection structure on the low resistance pattern; anda second conductive line on the selection structure.2. The variable resistance memory device as claimed in claim 1 , wherein:the first conductive line structure includes the adiabatic line between first conductive lines,the first conductive lines have a resistance lower than that of the at least one variable resistance pattern,the adiabatic line has a heat conductivity lower than that of the first conductive lines, andthe at least one variable resistance pattern contacts an upper surface of the first conductive line.34-. (canceled)5. The variable resistance memory device as claimed in claim 1 , wherein the selection structure includes a first buffer claim 1 , a selection pattern claim 1 , and a second buffer that are sequentially stacked.6. The variable resistance memory device as claimed in claim 5 , wherein:the first buffer has a heat conductivity lower than that of the low resistance pattern, anda bottom surface of the first buffer contacts an upper surface of the low resistance pattern.79-. (canceled)10. The variable resistance memory device as claimed in claim 1 , wherein:the first conductive line structure extends ...

Подробнее
Номер записи: 37
30-01-2020 дата публикации

SELF-SELECTING MEMORY CELL WITH DIELECTRIC BARRIER

Номер: US20200035917A1
Автор: Fratin Lorenzo, Pellizzer Fabio
Принадлежит:

A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar. 1. (canceled)2. A method , comprising:forming an opening through a stack of planes, the stack of planes comprising a first set of planes of a first material interleaved with a second set of planes of a second material different than the first material;forming a dielectric material within the opening, the dielectric material in contact with at least a portion of the first and second sets of planes exposed by the opening; andforming a chalcogenide alloy material in contact with the dielectric material.3. The method of claim 2 , further comprising:forming the stack of planes by forming alternating planes of one of the first set of planes of the first material and one of the second set of planes of the second material.4. The method of claim 3 , wherein the first material comprises a conductive material and the second material comprises an insulating material.5. The method of claim 2 , further comprising:replacing the first material in the first set of planes with a conductive material that is more conductive than the first material.6. The method of claim 5 , wherein ...

Подробнее
Номер записи: 38
30-01-2020 дата публикации

PHASE CHANGE MEMORY STRUCTURE TO REDUCE POWER CONSUMPTION

Номер: US20200035919A1
Автор: Liu Shih-Chang, Tsai Yi Jen
Принадлежит:

A phase change memory (PCM) cell with enhanced thermal isolation and low power consumption is provided. In some embodiments, the PCM cell comprises a bottom electrode, a dielectric layer, a heating element, and a phase change element. The dielectric layer is on the bottom electrode. The heating element extends through the dielectric layer, from a top of the dielectric layer to the bottom electrode. Further, the heating element has a pair of opposite sidewalls laterally spaced from the dielectric layer by a cavity. The phase change element overlies and contacts the heating element. An interface between the phase change element and the heating element extends continuously respectively from and to the opposite sidewalls of the heating element. Also provided is a method for manufacturing the PCM cell. 1. A phase change memory (PCM) cell comprising:a bottom electrode;a first dielectric layer overlying the bottom electrode, wherein the first dielectric layer has a first dielectric sidewall;a phase change element overlying the first dielectric layer;a heater element extending through the first dielectric layer, from the bottom electrode to the phase change element, wherein the heater element has a first heater sidewall facing the first dielectric sidewall and separated from the first dielectric sidewall by a cavity; anda second dielectric layer lining and partially filling the cavity.2. The PCM cell according to claim 1 , wherein the second dielectric layer directly contacts the first dielectric sidewall and the first heater sidewall.3. The PCM cell according to claim 1 , wherein a width of the heater element increases from the bottom electrode to the phase change element.4. The PCM cell according to claim 1 , wherein the second dielectric layer has a ring-shaped profile at the first dielectric sidewall and the first heater sidewall.5. The PCM cell according to claim 1 , wherein the first dielectric layer has a second dielectric sidewall on an opposite side of the heater ...

Подробнее
Номер записи: 39
09-02-2017 дата публикации

SEMICONDUCTOR APPARATUS WITH VARIABLE RESISTOR HAVING TAPERED DOUBLE-LAYERED SIDEWALL SPACERS

Номер: US20170040382A1
Автор: YOON Jae Sung
Принадлежит:

A method for fabricating a semiconductor apparatus includes forming a variable resistor region, and forming a spacer having a top linewidth and a bottom linewidth substantially equal to each other in the variable resistor region. The forming of the spacer includes forming a first insulating layer in the variable resistor region through a first method, forming a second insulating layer along a surface of the first insulating layer in the variable resistor region through a second method for providing step coverage superior to the first method, and etching the first and second insulating layers. 110-. (canceled)11. A semiconductor apparatus comprising:a lower electrode;a variable resistor device including a first variable resistor device and a second variable resistor device, wherein the first variable resistor device is formed over and coupled to the lower electrode and has a substantially uniform width from a top to a bottom of the first variable resistor device, wherein the second variable resistor device is formed over an upper surface of and coupled to the first variable resistor device and has a width larger than that of the first variable resistor device; anda spacer formed over an outer circumference of the first variable resistor device.12. The semiconductor apparatus of claim 11 , further comprising:an upper electrode formed over and coupled to the second variable resistor device.13. The semiconductor apparatus of claim 11 , further comprising:a semiconductor substrate; andan interlayer insulating layer having a hole formed over the semiconductor substrate,wherein the spacer and the variable resistor device are formed in the hole.14. The semiconductor apparatus of claim 13 , wherein the spacer includes:a first insulating layer having a non-uniform width in the hole, anda second insulating layer formed over a surface of the first insulating layer and having a substantially uniform width.15. The semiconductor apparatus of claim 14 , wherein the first insulating ...

Подробнее
Номер записи: 40
12-02-2015 дата публикации

THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE

Номер: US20150044849A1
Автор: Pio Federico
Принадлежит:

Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension. 1. A method of forming a memory array , comprising:forming a stack comprising a plurality of first conductive lines adjacent heater material, the first conductive lines adjacent heater material separated from one another by insulation material;forming a via through the stack such that at least a portion of the via passes through each of the plurality of first conductive lines and adjacent heater material;forming a recess at an exposed region of each of the first conductive lines in a wall of the via;forming an insulating material within the recess;forming storage element material over the insulating material within the via in contact with the heater material but not in contact with the first conductive lines;forming a cell select material over the storage element material; andforming a conductive extension over cell select material within the via.2. The method of claim 1 , wherein forming the via through the stack comprises forming a via that tangentially intersect a longest dimension of each of the plurality of first conductive lines and adjacent heater material.3. The method of claim 1 , wherein forming the via through the stack comprises forming a via that is not entirely surrounded by a first conductive line and adjacent heater material of the plurality of first conductive lines and adjacent heater material.4. ...

Подробнее
Номер записи: 41
07-02-2019 дата публикации

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) CELL WITH RECESSED BOTTOM ELECTRODE SIDEWALLS

Номер: US20190044065A1
Автор: Liu Shih-Chang, Tseng Yuan-Tai
Принадлежит:

Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element. 1. An integrated circuit comprising a memory cell , wherein the memory cell comprises:a lower electrode comprising a pair of electrode sidewalls, wherein the electrode sidewalls are respectively on opposite sides of the lower electrode;a data storage element overlying the lower electrode and comprising a pair of storage sidewalls, wherein the storage sidewalls are respectively on the opposite sides of the lower electrode, and wherein the electrode sidewalls are laterally spaced from and laterally between the storage sidewalls; andan upper electrode overlying the data storage element.2. The integrated circuit according to claim 1 , wherein the lower electrode has a first width claim 1 , and wherein the data storage element has a second width greater than the first width.3. The integrated circuit according to claim 1 , wherein the electrode sidewalls comprise a first electrode sidewall and a second electrode sidewall claim 1 , wherein the data storage element extends laterally and continuously from the first electrode sidewall to the second electrode sidewall in a first direction claim 1 , and wherein the data storage element further extends laterally and ...

Подробнее
Номер записи: 42
18-02-2021 дата публикации

INTERCONNECT STRUCTURE, SEMICONDUCTOR DEVICE, METHOD OF OPERATING ACTIVE ELEMENT, METHOD OF MANUFACTURING INTERCONNECT STRUCTURE, METHOD OF USING INTERCONNECT STRUCTURE, METHOD OF CONTROLLING INTERCONNECT RESISTANCE OF INTERCONNECT STRUCTURE, METHOD OF EVALUATING INTERCONNECT STRUCTURE, METHOD OF EVALUATING DEVICE, METHOD OF DRIVING DEVICE, AND EVALUATION DEVICE

Номер: US20210050513A1
Автор: ASANO Tetsuya, NISHIKAWA Asami, NISHITANI YU, Shibata Satoshi, SUGIMOTO Yuta, Tsujita Takuji
Принадлежит:

An interconnect structure according to the present disclosure includes: an interconnect layer containing a metal element as a main component and extending in a direction; a metal layer opposite to the interconnect layer, and a solid electrolyte layer between the interconnect layer and the metal layer. The solid electrolyte layer encloses the interconnect layer at least in a cross-sectional view taken along a plane orthogonal to the direction. The interconnect layer and the metal layer are electrically insulated from each other by the solid electrolyte layer. 1. An interconnect structure , comprising:an interconnect layer containing a metal element as a main component and extending in a direction;a metal layer opposite to the interconnect layer; anda solid electrolyte layer between the interconnect layer and the metal layer, the solid electrolyte layer enclosing the interconnect layer at least in a cross-sectional view taken along a plane orthogonal to the direction, whereinthe interconnect layer and the metal layer are electrically insulated from each other by the solid electrolyte layer.2. The interconnect structure according to claim 1 , whereinin the cross-sectional view, the interconnect layer has a pair of side surfaces opposite to each other and a bottom surface, andboth the metal layer and the solid electrolyte layer are opposite to each of the pair of side surfaces and the bottom surface.3. The interconnect structure according to claim 1 , whereinin the cross-sectional view, the interconnect layer has a circular or oval shape.4. The interconnect structure according to claim 3 , whereinthe interconnect layer serves as a columnar contact plug.5. The interconnect structure according to claim 1 , whereinin the cross-sectional view, an entire periphery of the interconnect layer is covered by the solid electrolyte layer, andin the cross-sectional view, an entire periphery of the solid electrolyte layer is covered by the metal layer.6. The interconnect structure ...

Подробнее
Номер записи: 43
18-02-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210050517A1
Автор: BANNO Naoki, Tada Munehiro
Принадлежит: NEC Corporation

A semiconductor device includes a first insulation layer, a second insulation layer disposed on the first insulation layer and having an opening on an upper surface of the second insulation layer, a first electrode embedded in the second insulation layer and having an end exposed at the opening, a variable-resistance layer disposed on the first electrode and the second insulation layer in at least one region inside and around the opening, and a second electrode disposed on the variable-resistance layer. The opening and the second electrode are formed in a shape stretched in at least one axial direction. 1. A semiconductor device comprising:a first insulation layer;a second insulation layer disposed on the first insulation layer and having an opening on an upper surface of the second insulation layer;a first electrode embedded in the second insulation layer and having an end that is exposed at the opening;a variable-resistance layer disposed on the first electrode and the second insulation layer in at least one region inside and around the opening; anda second electrode that is disposed on the variable-resistance layer, whereinthe opening and the second electrode are formed in a shape stretched in at least one axial direction.2. The semiconductor device according to claim 1 , whereinthe variable-resistance layer is an ion conductive layer capable of conducting ions of a metal constituting the first electrode.3. The semiconductor device according to claim 1 , wherein at least one of a formation region of the opening and an opening region of the second electrode is elliptical.4. The semiconductor device according to claim 1 , wherein at least one of a formation region of the opening and an opening region of the second electrode is rectangular.5. The semiconductor device according to claim 1 , comprising the first electrode at two locations claim 1 , whereinthe first electrodes at the two locations are disposed to face each other with an interval.6. The semiconductor ...

Подробнее
Номер записи: 44
18-02-2021 дата публикации

Techniques for forming self-aligned memory structures

Номер: US20210050521A1
Автор: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli, Lorenzo Fratin, Stephen W. Russell
Принадлежит: Micron Technology Inc

Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

Подробнее
Номер записи: 45
18-02-2021 дата публикации

METHOD OF FABRICATING SEMICONDUCTOR DEVICES USING A TWO-STEP GAP-FILL PROCESS

Номер: US20210050522A1
Автор: CHOI Dongsung, JUNG Jaeho, KIM Jonguk, KO Youngmin, PARK Kwangmin
Принадлежит:

A method of fabricating a memory device includes forming word lines and cell stacks with gaps between the cell stacks, forming a lower gap-fill insulator in the gaps, forming an upper gap-fill insulator on the lower gap-fill insulator, curing the lower gap-fill insulator and the upper gap-fill insulator to form a gap-fill insulator, and forming bit lines on the cell stacks and the gap-fill insulator. The lower gap-fill process may be performed using a first source gas that includes first and second precursors, and the upper gap-fill process may be performed using a second source gas that includes the first and second precursors, a volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1. 1. A method of fabricating a cross-point type semiconductor memory device , the method comprising:forming a first word line material layer and a first cell stack material layer on an underlayer,patterning the first cell stack material layer and the first word line material layer to form first preliminary cell stacks, first word lines, and first X-directional gaps using a first X-directional trimming process, wherein the first preliminary cell stacks and the first word lines extend in an X-direction, and the first X-directional gaps extend in the X-direction between the first preliminary cell stacks,forming a first lower X-directional gap-fill insulator that fills the first X-directional gaps using a first lower X-directional gap-fill process,forming a first upper X-directional gap-fill insulator on the first lower X-directional gap-fill insulator using a first upper X-directional gap-fill process, andforming a first X-directional gap-fill insulator using a curing process and a planarization process on the first lower X-directional gap-fill insulator and the first upper X-directional gap-fill insulator,wherein:the first ...

Подробнее
Номер записи: 46
16-02-2017 дата публикации

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20170047377A1
Автор: Chiang Kuang-Hao, Lai Erh-Kun
Принадлежит:

A memory device is provided. The memory device includes a substrate, a plurality of alternately stacked semiconductor layers and oxide layers disposed on the substrate, at least one through hole penetrating the stacked semiconductor layers and oxide layers, and an electrode layer disposed in the through hole. Each of the semiconductor layers includes a first area having a first conductive type and a second area having a second conductive type opposite to the first conductive type. 1. A memory device , comprising:a substrate;a plurality of alternately stacked semiconductor layers and oxide layers disposed on the substrate;a through hole penetrating the stacked semiconductor layers and oxide layers; andan electrode layer disposed in the through hole,wherein each of the semiconductor layers comprises a first area having a first conductive type and a second area having a second conductive type opposite to the first conductive type;an array layout of the memory device is a line type array layout;the line type array layout is physical 2 bits/per cell; andeven and odd lines of the array layout are decoded individually.2. The memory device according to claim 1 , further comprising:an isolation layer formed along a periphery of the through hole.3. The memory device according to claim 2 , wherein the second area is adjacent to the isolation layer claim 2 , and the first area is adjacent to the second area.4. The memory device according to claim 3 , wherein a concentration of the second area closer to the isolation layer is larger than a concentration of the second area farther away from the isolation layer.5. The memory device according to claim 2 , wherein the isolation layer comprises metal oxide or phase change material.6. The memory device according to claim 1 , further comprising:a conductive plug disposed in the substrate,wherein the conductive plug is electrically connected to the electrode layer.7. The memory device according to claim 1 , further comprising:a hard ...

Подробнее
Номер записи: 47
16-02-2017 дата публикации

RESISTIVE MEMORY DEVICES WITH AN OXYGEN-SUPPLYING LAYER

Номер: US20170047516A1
Автор: Cho Hans S.
Принадлежит:

A resistive memory device includes a bottom electrode and a top electrode crossing the bottom electrode at a non-zero angle. A switching region operatively contacts the bottom electrode and the top electrode. The switching region defines a current path between the bottom electrode and the top electrode in an ON state. An oxygen-supplying layer operatively contacts a portion of the switching region. The oxygen-supplying layer is positioned orthogonally to the current path and to the switching region. 1. A resistive memory device , comprising:a bottom electrode;a top electrode crossing the bottom electrode at a non-zero angle;a switching region operatively contacting the bottom electrode and the top electrode, the switching region defining a current path between the bottom electrode and the top electrode in an ON state; andan oxygen-supplying layer operatively contacting a portion of the switching region, the oxygen-supplying layer being positioned orthogonally to the current path and to the switching region.2. The resistive memory device as defined in claim 1 , further comprising an insulating layer sandwiching the oxygen-supplying layer to form a stack between the bottom electrode and the top electrode claim 1 , the stack surrounding at least a portion of the switching region.3. The resistive memory device as defined in wherein the switching region includes:an oxygen-rich film in contact with the stack, the top electrode, and the bottom electrode; anda metal-rich film in contact with the oxygen-rich film and the top electrode.4. The resistive memory device as defined in wherein the switching region includes:an oxygen-rich film in contact with the stack, the top electrode, and the bottom electrode; anda metal-rich film in contact with the oxygen-rich film and the bottom electrode.5. The resistive memory device as defined in wherein: an insulating layer sandwiching the oxygen-supplying layer and having two opposed surfaces; and', 'a metal layer positioned between one ...

Подробнее
Номер записи: 48
15-02-2018 дата публикации

Nonvolatile Storage Device and Method of Fabricating Nonvolatile Storage Device

Номер: US20180047787A1
Автор: Morimoto Tamotsu, Nakamura Genji
Принадлежит:

A nonvolatile storage device includes: first wirings arranged in first and second directions that intersect each other, and extending in a third direction perpendicular to the first and second directions; second wirings extending in the first direction, and each of the second wiring installed at a predetermined interval from each other in the third direction; first layers disposed between the first wirings and the second wirings, and extending in the third direction along the plurality of first wirings; and memory cells installed between the first layers and the second wirings and at respective positions where the first layers and the second wirings intersect each other. Each memory cell includes a second layer disposed towards a side closer to the second wirings and a conductive intermediate layer disposed towards a side closer to the first layers. 1. A nonvolatile storage device , comprising:a plurality of first wirings arranged in a first direction and a second direction that intersect each other, and extending in a third direction perpendicular to the first direction and the second direction;a plurality of second wirings extending in the first direction, and each of the plurality of second wiring installed at a predetermined interval from each other in the third direction;a plurality of first layers disposed between the plurality of first wirings and the plurality of second wirings, and extending in the third direction along the plurality of first wirings; anda plurality of memory cells installed between the plurality of first layers and the plurality of second wirings and at respective positions where the plurality of first layers and the plurality of second wirings intersect each other,wherein each of the plurality of memory cells includes a second layer disposed towards a second wiring side closer to the plurality of second wirings and a conductive intermediate layer disposed towards a first layer side closer to the plurality of first layers,the intermediate ...

Подробнее
Номер записи: 49
15-02-2018 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20180047899A1
Автор: Ahn Dong-ho, Horii Hideki, LEE Jung-Moo, PARK Seong-Geon
Принадлежит:

A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines. 1. A variable resistance memory device , comprising:first conductive lines positioned above a substrate, wherein each of the first conductive lines extends in a first direction and the first conductive lines are disposed in a second direction crossing the first direction, and wherein the first and second directions are substantially parallel to an upper surface of the substrate;second conductive lines each extending in the first direction, wherein the second conductive lines are disposed in the second direction, and wherein the second conductive lines are positioned above the first conductive lines; a first electrode;', 'a variable resistance pattern positioned on the first electrode; and', 'a second electrode positioned on the variable resistance pattern;, 'a memory unit positioned between the first and second conductive lines, wherein the memory unit overlaps the first and second conductive lines in a third direction substantially perpendicular to the upper surface of the substrate, and wherein the memory unit includesa selection pattern positioned on the memory unit; anda third ...

Подробнее
Номер записи: 50
03-03-2022 дата публикации

TOP-ELECTRODE BARRIER LAYER FOR RRAM

Номер: US20220069215A1
Автор: Jiang Fa-Shen, Lin Hsing-Lien, WU Chii-Ming
Принадлежит:

Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.

Подробнее
Номер записи: 51
03-03-2022 дата публикации

RESISTIVE RANDOM ACCESS MEMORY WITH PREFORMED FILAMENTS

Номер: US20220069218A1
Автор: LILL Thorsten, Pan Yang, YOON Hyungsuk
Принадлежит:

A method for fabricating a plurality of resistive random access memory (RRAM) cells includes providing a substrate including a memory medium arranged on an underlying layer; creating channel holes in the memory medium having a first critical dimension in a range from 1 nm to 20 nm; depositing switching material defining a filament of the RRAM cells in the channel holes; depositing a top electrode of the RRAM cells on the memory medium and the switching material; and separating adjacent ones of the RRAM cells by etching the top electrode and the memory medium between adjacent ones of the channel holes. 1. A method for fabricating a plurality of resistive random access memory (RRAM) cells , comprising:providing a substrate including a memory medium arranged on an underlying layer;creating channel holes in the memory medium having a first critical dimension in a range from 1 nm to 20 nm;depositing switching material defining a filament of the RRAM cells in the channel holes;depositing a top electrode of the RRAM cells on the memory medium and the switching material; andseparating adjacent ones of the RRAM cells by etching the top electrode and the memory medium between adjacent ones of the channel holes.2. The method of claim 1 , wherein creating the channel holes in the memory medium includes:depositing a first mask layer on the memory medium;patterning the channel holes having the first critical dimension in the mask layer;etching the memory medium through the channel holes to the underlying layer; andremoving the first mask layer.3. The method of claim 1 , wherein creating the channel holes in the memory medium includes:depositing a first mask layer on the memory medium;patterning the channel holes having a second critical dimension that is greater than the first critical dimension in the mask layer;etching the memory medium through the channel holes to the underlying layer;removing the first mask layer; andfilling the channel holes with a conformal layer to reduce ...

Подробнее
Номер записи: 52
13-02-2020 дата публикации

CONTROLLING DOPANT CONCENTRATION IN CORRELATED ELECTRON MATERIALS

Номер: US20200052201A1
Автор: Reid Kimberly Gay, Shifren Lucian, YERIC Gregory Munson
Принадлежит:

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) device. In embodiments, after formation of the one or more CEM traces, a spacer may be deposited in contact with the one or more CEM traces. The spacer may operate to control an atomic concentration of dopant within the one or more CEM traces by replenishing dopant that may be lost during subsequent processing and/or by forming a seal to reduce further loss of dopant from the one or more CEM traces. 121-. (canceled)22. A device , comprising:a plurality of correlated electron material (CEM) traces formed over a first level, one or more individual CEM traces of the plurality of CEM traces to comprise an electron back-donating material to include a dopant; anda spacer formed to fill at least a portion of a trench separating adjacent individual CEM traces of the plurality of CEM traces, the spacer to control an atomic concentration of the dopant within the one or more individual CEM traces of the plurality of CEM traces at least in part by enabling diffusion of the dopant from the spacer into the one or more individual CEM traces to thereby impart particular impedance switching characteristics within the one or more individual CEM traces of the plurality of CEM traces.23. The device of claim 22 , wherein the spacer is adapted to diffuse the dopant into the one or more individual CEM traces of the plurality of CEM traces to maintain the atomic concentration of the dopant within the one or more individual CEM traces in a range of about 0.1% to about 10.0%.24. The device of claim 23 , wherein the dopant to comprise a carbon-containing dopant species or a nitrogen-containing dopant species claim 23 , or a combination thereof.25. The device of claim 22 , wherein the spacer to comprise an atomic concentration of at least 50.0% silicon nitride (SiN).26. The device of claim 22 , wherein the spacer to comprise an atomic concentration of at least 50.0% silicon nitride (SiO).27. The ...

Подробнее
Номер записи: 53
22-05-2014 дата публикации

NANOCOMPOSITE MATERIAL, TUNABLE RESISTOR DEVICE, AND METHOD

Номер: US20140138601A1
Автор: Mares Jeremy West, Weiss Sharon M.
Принадлежит: Vanderbilt Unviersity

Various embodiments of a composite material are provided. In one embodiment of the present invention a nanometer-scale composite material comprises, by volume, from about 1% to about 99% variable-conductivity material and from about 99% to about 1% conductive material. The composite material exhibits memristive properties when a voltage differential is applied to the nanocomposite. In another embodiment, a variable resistor device includes a first electrode terminal and a second electrode terminal and a nanocomposite in electrical communication with the electrode terminals. The composite material comprises, by volume, from about 1% to about 99% variable-conductivity material and from about 99% to about 1% conductive material. The memristor is tunable as the minimum instantaneous resistance can be altered several orders of magnitude by varying the composition and ratio of the variable-conductivity material and conductive material constituents of the composites. 1. A composite material comprising:from about 1% to about 99% variable-conductivity material;from about 99% to about 1% conductive material;wherein the conductive material and variable-conductivity material comprise nanometer-scale particles having an average lineal dimension that ranges from about one nanometer to about one micron; andwherein the composite material exhibits memristive properties when a voltage differential is applied to the composite material.2. The composite material of claim 1 , wherein the conductive material is a metal or a semiconductor material.3. The composite material of claim 1 , wherein the conductive material is a doped semiconductor.4. The composite material of claim 1 , wherein the variable-conductivity material is a solid ionic conductor material.5. The composite material of claim 1 , wherein the variable-conductivity material is a metal oxide.6. The composite material of claim 1 , wherein the composite material comprises claim 1 , by volume claim 1 , from about 10% to about 90% ...

Подробнее
Номер записи: 54
01-03-2018 дата публикации

SWITCHING ELEMENT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Номер: US20180061890A1
Автор: Sugibayashi Tadahiko, Tada Munehiro
Принадлежит: NEC Corporation

In the cases of performing programming by forming a two-terminal-type variable resistance element on a semiconductor device, it has been difficult to control the programming, and malfunctions have often occurred. This switching element includes at least a first variable resistance element, a second variable resistance element, a first rectifying element, and a second rectifying element, one end of the first variable resistance element and one end of the second variable resistance element are respectively connected to one end of the first rectifying element and one end of the second rectifying element, and each of the rectifying elements has two terminals. 1. A switching element comprising: a first variable-resistance element , a second variable-resistance element , a first rectifying element , and a second rectifying element , whereineach of the first rectifying element and the second rectifying element is a two-terminal element, andone end portion of the first variable-resistance element and one end portion of the second variable-resistance element are connected to one end portion of the first rectifying element and one end portion of the second rectifying element.2. The switching element according to claim 1 , whereinthe switching element is to be inserted in a signal path, andinput and output are performed through unconnected terminals of the first variable-resistance element and the second variable-resistance element, and resistance states of the first variable-resistance element and the second variable-resistance element are controlled through unconnected terminals of the first rectifying element and the second rectifying element.3. The switching element according to claim 1 , whereinprogramming of the first variable-resistance element is performed through the second rectifying element, andprogramming of the second variable-resistance element is performed through the first rectifying element.4. The switching element according to claim 1 , whereineach of the ...

Подробнее
Номер записи: 55
01-03-2018 дата публикации

Resistance Variable Memory Structure and Method of Forming the Same

Номер: US20180062074A1
Автор: Hsieh Ching-Pei, Hsu Chern-Yow, Liu Shih-Chang, Sung Fu-Ting, Tsai Chia-Shiung
Принадлежит:

A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening. 1. A memory element comprising:a first dielectric layer over a conductive structure, the first dielectric layer having a first top surface;an opening in the first dielectric layer, the opening exposing an exposed portion of the conductive structure;a first electrode in the opening, wherein the first electrode is on sidewalls and a bottom of the opening, the first electrode in contact with the exposed portion of the conductive structure;a resistance variable layer over the first electrode on the sidewalls and the bottom of the opening;a second electrode over the resistance variable layer in the opening, the resistance variable layer being interposed between the first electrode and the second electrode; anda second dielectric layer in the opening over the second electrode.2. The memory element of claim 1 , wherein the resistance variable layer extends above an uppermost surface of the first electrode.3. The memory element of claim 2 , wherein the resistance variable layer extends above an uppermost surface of the second electrode.4. The memory element of claim 1 ...

Подробнее
Номер записи: 56
04-03-2021 дата публикации

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE

Номер: US20210066393A1
Автор: Kim Tae Hoon, LEE Hyung Dong, YOO Si Jung
Принадлежит:

An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers. 1. An electronic device including a semiconductor memory , the semiconductor memory comprising:material layers each including one or more low-resistance areas and one or more high-resistance areas;insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers;conductive pillars passing through the insulating layers and the low-resistance areas;conductive layers located between the protrusions; andvariable resistance layers interposed between the low-resistance areas and the conductive layers.2. The electronic device of claim 1 , further comprising electrode layers interposed between the variable resistance layers and the conductive layers.3. The electronic device of claim 2 , wherein the electrode layers include carbon.4. The electronic device of claim 1 , wherein each of the material layers includes amorphous carbon claim 1 , a silicon nitride claim 1 , a transition metal oxide claim 1 , or a combination thereof.5. The electronic device of claim 1 , wherein each of the material layers is a single layer including the low-resistance areas and the high-resistance areas arranged alternately with each other.6. The electronic device of claim 1 , wherein the low-resistance areas are electrically conductive and adjacent low-resistance areas are electrically insulated from each other by the high-resistance areas.7. The electronic device of claim 1 , wherein memory cells are located ...

Подробнее
Номер записи: 57
04-03-2021 дата публикации

RESISTIVE RANDOM ACCESS MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20210066594A1
Автор: CHEN Hung-Sheng, LEE Yen-De, WANG Ching-Yung, YU Chien-Hsiang
Принадлежит:

A resistive random access memory structure and its manufacturing method are provided. The resistive random access memory structure includes a substrate having an array region and a peripheral region. A first low-k dielectric layer located in the peripheral region has a dielectric constant of less than 3. Memory cells are located on the substrate and in the array region. A dielectric layer covers the memory cells and fills the space between adjacent memory cells in the peripheral region, and its material layer is different from that of the first low-k dielectric layer. First conductive plugs are located in the dielectric layer and each of them is in contact with one of the memory cells. A dummy memory cell is located at the boundary between the array region and the peripheral region, and the dummy memory cell is not in contact with any one of the first conductive plugs. 1. A resistive random access memory structure , comprising:a substrate, wherein the substrate comprises an array region and a peripheral region;a first low-k dielectric peripheral region, wherein the first low-k dielectric layer has a dielectric constant of less than 3;a plurality of memory cells located on the substrate and in the array region;a gap-filling dielectric layer located in the peripheral region, wherein the gap-filling dielectric layer covers the plurality of memory cells and fills a space between the adjacent memory cells in the peripheral region, wherein a material of the gap-filling dielectric layer is different from a material of the first low-k dielectric layer;a plurality of first conductive plugs located in the gap-filling dielectric layer, wherein each of the plurality of first conductive plugs is in contact with one of the plurality of memory cells; anda dummy memory cell located at a boundary between the array region and the peripheral region, wherein the dummy memory cell is not in contact with any one of the plurality of first conductive plugs.2. The resistive random access ...

Подробнее
Номер записи: 58
12-03-2015 дата публикации

RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF

Номер: US20150069316A1
Автор: CHOU Chung-Cheng, Chu Wen-Ting, LEE Po-Hao
Принадлежит: Taiwan Semiconductor Manufacturing Company Ltd.

The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer. 1. A semiconductor structure , comprising:a conductive layer; a first electrode comprising a first sidewall, a second sidewall, and a bottom surface on the conductive layer, wherein a joint between the first sidewall and the second sidewall includes an electric field enhancement structure;', 'a resistance configurable layer over the first electrode; and', 'a second electrode over the resistance configurable layer., 'a resistance configurable structure over the conductive layer, the resistance configurable structure comprising2. The semiconductor in claim 1 , wherein the electric field enhancement structure comprises an angle about or less than 90 degrees.3. The semiconductor in claim 1 , wherein the resistance configurable structure further comprises a dielectric layer on the conductive layer claim 1 , contacting at least a portion of the first sidewall.4. The semiconductor in claim 3 , wherein a height of the dielectric layer to a height of the first sidewall is in a range of from about 0.2 to about 1.0.5. The semiconductor in ...

Подробнее
Номер записи: 59
29-05-2014 дата публикации

ELECTRONIC MEMORY DEVICE

Номер: US20140145141A1
Автор: Molas Gabriel, Nodin Jean-François
Принадлежит:

An electronic device includes a first electrode made of an inert material; a second electrode made of a soluble material; a solid electrolyte made of an ion-conductive material, wherein the first and second electrodes are in contact respectively with one of the faces of the electrolyte, either side of the electrolyte, wherein the second electrode supplies mobile ions flowing in the electrolyte towards the first electrode, to form a conductive filament when a voltage is applied between the first and second electrodes. The second electrode is a confinement electrode that includes an end surface in contact with the electrolyte which is less than the available surface of the electrolyte, such that confinement of the contact area of the confinement electrode on the solid electrolyte is obtained. 2. A device according to claim 1 , wherein a section of the confinement electrode measured parallel to a contact plane of the electrolyte with the confinement electrode continuously grows from the contact plane over at least part of the height of said confinement electrode.3. A device according to claim 1 , wherein the volume of the electrolyte is chosen such that the surface of the first end of the electrolyte in contact with the first electrode is strictly less than the surface of the second end of the electrolyte opposite the first end.4. A device according to claim 3 , wherein the section of the electrolyte measured parallel to the contact plane of said electrolyte with the first electrode grows continuously from the contact plane over at least part of the height of the electrolyte.5. A device according to claim 3 , wherein the electrolyte has a first portion of constant section in contact with the first electrode followed by a second portion of constant section claim 3 , wherein the constant section of the first portion is less than the constant section of the second portion claim 3 , and wherein the constant sections are measured parallel to the contact planes of the ...

Подробнее
Номер записи: 60
08-03-2018 дата публикации

MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20180069050A1
Автор: NODA Kotaro, Okajima Mutsumi
Принадлежит: Toshiba Memory Corporation

A memory device includes a first interconnect extending in a first direction, semiconductor members extending in a second direction, a second interconnect provided between the semiconductor members and extending in a third direction, a first insulating film provided between the semiconductor member and the second interconnect, third interconnects extending in the second direction, fourth interconnects provided between the third interconnects and arranged along the second direction, a resistance change film provided between the third interconnect and the fourth interconnects, and a first film. The first film is provided between the second interconnect and the fourth interconnect, interposes between the semiconductor member and the resistance change film, and not interpose between the semiconductor member and the third interconnect connected to each other. A first end of the semiconductor member is connected to the first interconnect. The third interconnect is connected to a second end of the semiconductor member. 1. A memory device comprising:a first interconnect extending in a first direction;a plurality of semiconductor members extending in a second direction crossing the first direction, a first end of the semiconductor member being connected to the first interconnect;a second interconnect provided between the plurality of semiconductor members and extending in a third direction crossing the first direction and the second direction;a first insulating film provided between one of the plurality of semiconductor members and the second interconnect;a plurality of third interconnects extending in the second direction, one of the plurality of third interconnects being connected to a second end of one of the plurality of semiconductor members;a plurality of fourth interconnects provided between the plurality of third interconnects and arranged along the second direction;a resistance change film provided between one of the plurality of third interconnects and the ...

Подробнее
Номер записи: 61
28-02-2019 дата публикации

METHOD FOR FORMING A PHASE CHANGE MEMORY (PCM) CELL WITH A LOW DEVIATION CONTACT AREA BETWEEN A HEATER AND A PHASE CHANGE ELEMENT

Номер: US20190067570A1
Автор: Liu Shih-Chang, Tsai Yi Jen
Принадлежит:

A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top conductive. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell. 1. A phase change memory (PCM) structure comprising:a bottom electrode;a dielectric layer overlying the bottom electrode;a heater extending upward from the bottom electrode, through the dielectric layer, wherein the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer; anda phase change element overlying the dielectric layer and protruding into the dielectric layer to contact with the top surface of the heater.2. The PCM structure according to claim 1 , wherein top corners of the dielectric layer that face the phase change element are curved claim 1 , and wherein the phase change element conforms to the top corners.3. The PCM structure according to claim 1 , wherein the dielectric layer has a curved sidewall surface arcing continuously from the top surface of the dielectric layer to a substantially planar sidewall surface of the dielectric layer claim 1 , wherein the top surface of the dielectric layer is substantially planar claim 1 , and wherein an interface between the phase change element and the top surface of the heater is spaced below a bottom edge of the curved sidewall surface.4. The PCM structure according to claim 3 , wherein the heater and the phase change element contact the substantially planar ...

Подробнее
Номер записи: 62
28-02-2019 дата публикации

SELF-SELECTING MEMORY CELL WITH DIELECTRIC BARRIER

Номер: US20190067571A1
Автор: Fratin Lorenzo, Pellizzer Fabio
Принадлежит:

A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar. 1. A memory device , comprising:a stack of planes comprising a first set of planes and a second set of planes;a conductive pillar disposed through the stack of planes;a chalcogenide alloy material at least partially surrounding the conductive pillar; anda dielectric material at least partially surrounding the chalcogenide alloy material.2. The memory device of claim 1 , further comprising:an electrode material at least partially surrounding the conductive pillar.3. The memory device of claim 2 , and further comprising:a second dielectric material positioned between the electrode material and the chalcogenide alloy material, wherein the second dielectric material at least partially surrounds the electrode material and the chalcogenide alloy material at least partially surrounds the second dielectric material.4. The memory device of claim 2 , wherein the chalcogenide alloy material is in contact with the electrode material.5. The memory device of claim 1 , further comprising:a second dielectric material positioned between the conductive pillar and the chalcogenide ...

Подробнее
Номер записи: 63
28-02-2019 дата публикации

PHASE CHANGE MEMORY STRUCTURE TO REDUCE POWER CONSUMPTION

Номер: US20190067572A1
Автор: Liu Shih-Chang, Tsai Yi Jen
Принадлежит:

A phase change memory (PCM) cell with enhanced thermal isolation and low power consumption is provided. In some embodiments, the PCM cell comprises a bottom electrode, a dielectric layer, a heating element, and a phase change element. The dielectric layer is on the bottom electrode. The heating element extends through the dielectric layer, from a top of the dielectric layer to the bottom electrode. Further, the heating element has a pair of opposite sidewalls laterally spaced from the dielectric layer by a cavity. The phase change element overlies and contacts the heating element. An interface between the phase change element and the heating element extends continuously respectively from and to the opposite sidewalls of the heating element. Also provided is a method for manufacturing the PCM cell. 1. A phase change memory (PCM) cell comprising:a bottom electrode;a dielectric layer on the bottom electrode;a heating element extending through the dielectric layer, from a top of the dielectric layer to the bottom electrode, wherein the heating element has a pair of opposite sidewalls laterally spaced from the dielectric layer by a cavity; anda phase change element overlying and contacting the heating element, wherein an interface between the phase change element and the heating element extends continuously respectively from and to the opposite sidewalls of the heating element.2. The PCM cell according to claim 1 , wherein a width of the heating element increases continuously from the bottom electrode to the phase change element.3. The PCM cell according to claim 1 , wherein the opposite sidewalls of the heating element each arc continuously from the bottom electrode to the phase change element.4. The PCM cell according to claim 1 , wherein a two-dimensional (2D) projection of the cavity onto the bottom electrode is ring shaped.5. The PCM cell according to claim 1 , wherein the cavity is hermetically sealed.6. The PCM cell according to claim 1 , further comprising:a ...

Подробнее
Номер записи: 64
09-03-2017 дата публикации

VIA FORMATION FOR CROSS-POINT MEMORY

Номер: US20170069375A1
Автор: Tang Stephen
Принадлежит:

Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device. 1. (canceled)2. A memory device , comprising:a first plurality of electrically conductive lines oriented in a first direction on a first level;a second plurality of electrically conductive lines oriented in a second direction on a second level; anda first memory material positioned between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines, wherein the first memory material includes a plurality of vias each including an electrical conductor, and wherein each via segments a portion of the first memory material.3. The memory device of claim 2 , wherein the first memory material comprises a plurality of etched areas claim 2 , and wherein each etched area of the plurality comprises a trench.4. The memory device of claim 3 , wherein at least one via of the plurality of vias is located within the trench of one etched area of the plurality of etched areas.5. The memory device of claim 2 , wherein the first memory material comprises an array of memory cells positioned between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines.6. The memory device of claim 5 , wherein the array of memory cells comprises an array of selector devices positioned between the array of memory cells and the second plurality of electrically conductive lines.7. The memory device of claim 5 , wherein the first plurality of electrically conductive lines comprise word-lines operatively coupled to the array of memory cells.8. The memory device of claim 5 , wherein the second plurality of electrically conductive lines comprise bit-lines operatively coupled to the array of memory cells.9. A ...

Подробнее
Номер записи: 65
11-03-2021 дата публикации

3D VERTICAL MEMORY ARRAY CELL STRUCTURES WITH INDIVIDUAL SELECTORS AND PROCESSES

Номер: US20210074764A1
Автор: Hsu Fu-Chang
Принадлежит:

Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layers and insulator layers, forming a hole through the array stack to expose internal surfaces of the metal layers and internal surfaces of the insulator layers, and performing a metal-oxidation process on the internal surfaces of the metal layers to form selector devices on the internal surfaces of the metal layers. The operations also include depositing one of resistive material or phase-change material within the hole on the selector devices and the internal surfaces of the insulator layers, such that the hole is reduced to a smaller hole, and depositing conductor material in the smaller hole. 1. A 3D vertical memory array structure , comprising:an array stack having alternating metal layers and insulator layers, and wherein the array stack includes a hole that exposes internal surfaces of the metal layers and internal surfaces of the insulator layers;metal-oxidation on the internal surfaces of the metal layers that forms selector devices on the internal surfaces of the metal layers;one of resistive material or phase-change material within the hole and coupled to the selector devices, and wherein the hole is reduced to a smaller hole; andconductor material in the smaller hole and coupled to the resistive material or the phase-change material.2. The structure of claim 1 , wherein the metal layers comprise one of Tantalum (Ta) claim 1 , Niobium (Nb) claim 1 , Titanium (Ti) claim 1 , Zirconium (Zr) claim 1 , Vanadium-Chromium (VCr) claim 1 , and wherein based on the metal layer the metal-oxidation comprises one of TaOx claim 1 , NbOx claim 1 , TiOX claim 1 , ZrOx claim 1 , or VCrOx claim 1 , respectively.3. The structure of claim 1 , wherein the resistive material comprises one of HfOx claim 1 , LiSiOx claim 1 , ZrSiOx claim 1 , WOx ...

Подробнее
Номер записи: 66
05-06-2014 дата публикации

Uniform critical dimension size pore for pcram application

Номер: US20140154862A1
Автор: Alejandro G. Schrott, Chung H. Lam, Eric A. Joseph, Hsiang-Lan Lung, Matthew J. Breitwisch, Roger W. Cheek
Принадлежит: International Business Machines Corp, Macronix International Co Ltd

A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

Подробнее
Номер записи: 67
07-03-2019 дата публикации

Resistive random access memory device containing replacement word lines and method of making thereof

Номер: US20190074441A1
Автор: Seje TAKAKI, Shin Kikuchi
Принадлежит: SanDisk Technologies LLC

A method of forming a resistive memory device includes forming an alternating stack of insulating layers and sacrificial material layers that extend along a first horizontal direction over a substrate, forming a laterally alternating sequence of vertical conductive lines and dielectric pillar structures that alternate along the first horizontal direction on sidewalls of the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers, selectively growing resistive memory material portions from physically exposed surfaces of the vertical conductive lines in the lateral recesses, and forming electrically conductive layers over the resistive memory material portions in the lateral recesses.

Подробнее
Номер записи: 68
05-03-2020 дата публикации

MEMORY DEVICE

Номер: US20200075674A1
Автор: Park Il-mok, Song Seul-ji
Принадлежит:

A memory device includes a lower conductive line, a first memory unit, a second memory unit, and a shared lower electrode including first and second portions electrically connecting respective ones of the first memory unit and the second memory unit to the lower conductive line. A first insulating region is disposed between the first and second memory units. A second insulating region is disposed on the first insulating region. The device further includes a first switch unit on the first memory unit and including an upper electrode with a portion protruding from the second insulating region and a second switch unit on the second memory unit and including an upper electrode with a portion protruding from the second insulating region. First and second upper conductive lines contact the protruding portions of the respective upper electrodes. 1. A memory device comprising:a lower conductive line;a first memory unit;a second memory unit;a shared lower electrode comprising first and second portions electrically connecting respective ones of the first memory unit and the second memory unit to the lower conductive line;a filling insulating pattern between the first and second memory units;an upper insulating pattern on the filling insulating pattern;a first switch unit on the first memory unit in the upper insulating pattern and comprising an upper electrode with a portion protruding from the upper insulating pattern;a second switch unit on the second memory unit in the upper insulating pattern and comprising an upper electrode with a portion protruding from the upper insulating pattern;a first upper conductive line contacting the protruding portion of the upper electrode of the first switch unit; anda second upper conductive line contacting the protruding portion of the upper electrode of the second switch unit.2. The memory device of claim 1 , wherein the first upper conductive line contacts a pair of side surfaces of the protruding portion of the upper electrode of the ...

Подробнее
Номер записи: 69
05-03-2020 дата публикации

INTEGRATED CIRCUIT DEVICES BASED ON METAL ION MIGRATION AND METHODS OF FABRICATING SAME

Номер: US20200075849A1
Автор: Goux Ludovic
Принадлежит:

The disclosed technology generally relates to integrated circuit (IC) devices and more particularly to IC devices based on metal ion migration, and to manufacturing of the IC devices. In one aspect, a method of manufacturing an integrated electronic circuit, which includes at least one component based on metal ion migration and reduction, allows improved control of an amount of the metal which is incorporated into the component. This amount is produced from a metal supply layer and transferred into a container selectively with respect to the rest of the component. The container is configured as part of an electrolyte portion or active electrode in the final component. The method is compatible with two-dimensional and three-dimensional configurations of the component. 1. A method of manufacturing an integrated electronic circuit which includes at least one component based on metal ion migration and reduction , the method comprising:providing a metal and a first material different from the metal and capable of containing ions or atoms of the metal, and providing at least one second material so that each second material is electrically insulating and has a capacity of containing the metal ions or metal atoms which is less than that of the first material;forming on a substrate of the integrated circuit a container comprising at least one portion of the first material and a boundary portion comprising at least one portion of the at least one second material, wherein the container and the boundary portion are next to each other;depositing a supply layer over the container and the boundary portion, the supply layer containing ions or atoms of the metal, such that a path from the supply layer to the container is available for some of the ions or atoms of the metal;activating a movement of some of the ions or atoms of the metal in the supply layer into at least part of the container selectively with respect to the boundary portion;removing the supply layer, while leaving ...

Подробнее
Номер записи: 70
05-03-2020 дата публикации

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) CELL WITH RECESSED BOTTOM ELECTRODE SIDEWALLS

Номер: US20200075855A1
Автор: Liu Shih-Chang, Tseng Yuan-Tai
Принадлежит:

Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element. 1. An integrated circuit (IC) comprising a memory cell , wherein the memory cell comprises:a lower electrode;a high k dielectric layer overlying the lower electrode, wherein the high k dielectric layer has a peripheral region with a first concentration of crystalline defects and further has a central region with second concentration of crystalline defects less than the first concentration; andan upper electrode overlying the high k dielectric layer;wherein the lower electrode has an electrode sidewall, wherein a top edge of the electrode sidewall and a bottom edge of the electrode sidewall underlie a boundary at which the central and peripheral regions directly contact.2. The IC according to claim 1 , wherein the electrode sidewall is concave and arcs continuously from the top edge to the bottom edge.3. The IC according to claim 1 , wherein the lower electrode and the high k dielectric layer collectively have a T-shaped profile.4. The IC according to claim 1 , wherein the peripheral region is a region of the high k dielectric layer damaged by plasma etching during formation of the memory cell claim 1 , and wherein the central region is a region of the ...

Подробнее
Номер записи: 71
05-03-2020 дата публикации

OXYGEN VACANCY AND FILAMENT-LOSS PROTECTION FOR RESISTIVE SWITCHING DEVICES

Номер: US20200075860A1
Автор: Ando Takashi, KIM Seyoung, Miyazoe Hiroyuki, Narayanan Vijay
Принадлежит:

Embodiments of the invention are directed to a fabrication method that includes forming a dielectric region of a wafer, forming a bottom contact embedded within the dielectric region such that a top surface of the bottom contact is exposed, and forming a dummy resistive switching element over the top surface of the bottom electrode. Portions of the dummy resistive switching element are exposed to at least one oxide source. The dummy resistive switching element is replaced with a resistive switching element stack. 1. A fabrication method comprising:forming a dielectric region of a wafer;forming a bottom contact embedded within the dielectric region such that a top surface of the bottom contact is exposed;forming a dummy resistive switching element over the top surface of the bottom contact;exposing portions of the dummy resistive switching element to at least one oxide source; andreplacing the dummy resistive switching element with a resistive switching element stack.2. The method of further comprising:forming a top contact over the resistive switching element stack;coupling a bottom electrode to the bottom contact; andcoupling a top electrode to the top contact;wherein a resistive switching device comprises, the bottom electrode, the resistive switching element stack, and the top electrode.3. The method of claim 2 , wherein the top contact comprises a barrier metal layer and a low resistivity metal.4. The method of claim 1 , wherein the resistive switching element stack comprises a filament region.5. The method of claim 4 , wherein the filament region comprises a metal oxide.6. The method of claim 5 , wherein the metal oxide comprises a compound selected from the group consisting of HfO claim 5 , TaO claim 5 , and ZrO.7. The method of claim 4 , wherein the resistive switching element stack further comprises a reactive electrode.8. The method of claim 7 , wherein oxygen vacancy formation in the filament region is controlled by the reactive electrode.9. The method of ...

Подробнее
Номер записи: 72
26-03-2015 дата публикации

3 DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20150087111A1
Автор: KIM Suk Ki
Принадлежит:

A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes. 18-. (canceled)9. A method of manufacturing a semiconductor device , the method comprising:sequentially stacking a first semiconductor layer and a second semiconductor layer having different etch selectivity from that of the first semiconductor layer on a semiconductor substrate;defining a source formation region and a drain formation region by etching the second semiconductor layer corresponding to a gate formation region by a predetermined thickness;forming a gate insulating layer on a surface of the gate formation region and an oxide semiconductor layer in the first semiconductor layer;defining a transistor region by etching the second semiconductor layer and the oxide semiconductor layer in an outer side of the drain formation region;forming a common source node by selectively removing the exposed first semiconductor layer;forming a gate in the gate formation region;forming a source region and a drain region in the source formation region and the drain formation region, respectively;forming heating electrodes on the source region and the drain region; andforming resistance variable ...

Подробнее
Номер записи: 73
12-06-2014 дата публикации

METHOD FOR FABRICATING PHASE CHANGE MEMORY

Номер: US20140162428A1
Автор: HIROTA Yoshihiro, NAKABAYASHI Hajime, OYAMA Kenichi
Принадлежит: TOKYO ELECTRON LIMITED

A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole. 115-. (canceled)16. A method for fabricating a phase change memory , comprising:forming an opening portion having a substantially square or substantially rectangular shape on an insulating layer;forming a phase change film in the opening portion on the insulating layer; andetching back the phase change film and forming a phase change portion along the sides of a lower surface of the opening portion,wherein two electrodes having one pole and two electrodes having another pole are exposed at four corners of the opening portion, andthe phase change portion is connected to the electrodes having one pole and the electrodes having another pole at the four corners of the opening portion.17. The method of claim 16 , wherein the phase change film is formed through sputtering.18. The method of claim 16 , wherein etching back the phase change film is performed through dry etching.19. A method for fabricating a phase change memory claim 16 , comprising:forming an electrode layer having one pole and a diode layer on an insulating layer formed on a substrate; ...

Подробнее
Номер записи: 74
14-03-2019 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20190081238A1
Автор: KITAMURA Masahito
Принадлежит: KOKUSAI ELECTRIC CORPORATION

Described herein is a technique capable of improving a quality of a phase change film formed on a substrate. According to the technique described herein, there is provided a method of manufacturing a semiconductor device, including: (a) supplying a reducing first gas onto a substrate while heating the substrate, wherein the substrate includes a first metal-containing film and an insulating film with recesses and the first metal-containing film is exposed at the recesses; and (b) supplying a second gas, a third gas and a fourth gas into the recesses to form a phase change film in the recesses after (a) is performed. 1. A method of manufacturing a semiconductor device , comprising:(a) supplying a reducing first gas onto a substrate while heating the substrate, wherein the substrate includes a first metal-containing film and an insulating film with recesses and the first metal-containing film is exposed at the recesses; and(b) supplying a second gas, a third gas and a fourth gas into the recesses to form a phase change film in the recesses after (a) is performed.2. The method of claim 1 , further comprising:(c) forming a second metal-containing film on the first metal-containing film between (a) and (b).3. The method of claim 1 , wherein (a) comprises activating the first gas with two electric powers of different frequencies.4. The method of claim 2 , wherein (a) includes activating the first gas with two electric powers of different frequencies.5. The method of claim 1 , further comprising:(d) supplying an alkaline polishing agent to the substrate to polish the substrate after (b) is performed.6. The method of claim 2 , further comprising:(d) supplying an alkaline polishing agent to the substrate to polish the substrate after (b) is performed.7. The method of claim 3 , further comprising:(d) supplying an alkaline polishing agent to the substrate to polish the substrate after (b) is performed.8. The method of claim 4 , further comprising:(d) supplying an alkaline ...

Подробнее
Номер записи: 75
24-03-2016 дата публикации

Diode/Superionic Conductor/Polymer Memory Structure

Номер: US20160087007A1
Автор: Campbell Kristy A.
Принадлежит: MICRON TECHNOLOGY, INC.

A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode. 139-. (canceled)40. A method of forming a semiconductor device comprising:forming a first electrode over a substrate;forming a polymer memory element in contact with said first electrode;forming a first metal-chalcogenide layer having a first conductivity type in contact with said polymer memory element;forming a second metal-chalcogenide layer having a second conductivity type in contact with said first metal-chalcogenide layer; andforming a second electrode in contact with said second metal-chalcogenide layer.41. The method of claim 40 , wherein said steps of forming said first metal-chalcogenide layer and forming said second metal-chalcogenide layer include sputtering and etching.42. The method of claim 40 , wherein said step of forming a polymer memory element includes depositing a material that adheres preferentially to the second metal-chalcogenide layer.43. The method of claim 42 , wherein said material is a conjugated polymer that changes resistance in response to an applied electric field.44. The method of claim 43 , wherein said conjugated polymer is selected ...

Подробнее
Номер записи: 76
23-03-2017 дата публикации

VARIABLE RESISTANCE MATERIAL LAYERS AND VARIABLE RESISTANCE MEMORY DEVICES INCLUDING THE SAME

Номер: US20170084834A1
Автор: Ahn Dong-ho, Cho Sung-Lae, Kim Do-Hyung, KIM Jong-uk
Принадлежит:

A variable resistance material layer including germanium (Ge), antimony (Sb), tellurium (Te), and at least one type of impurities X. The variable resistance material layer having a composition represented by a chemical formula of X(GeSbTe), wherein an atomic concentration of the impurities X is in a range of 0 Подробнее

Номер записи: 77
23-03-2017 дата публикации

METHOD FOR FABRICATING ELECTRONIC DEVICE WITH VARIABLE RESISTANCE MATERIAL LAYER

Номер: US20170084836A1
Автор: Kim Jung-Nam, Kim Sang-Soo
Принадлежит:

A method for fabricating an electronic device including a semiconductor memory may include: forming a first interlayer dielectric layer over a substrate to have an opening exposing the substrate; forming a bottom electrode in a portion of the opening to have an exposed top surface; forming a variable resistance material layer along sidewalls of the remaining portion of the opening and the exposed top surface of the bottom electrode; forming a top electrode over the variable resistance material layer so as to fill the opening; etching the first interlayer dielectric layer to a predetermined depth to expose a part of the variable resistance material layer surrounding sidewalls of the top electrode; and removing the part of the variable resistance material layer to form a unit cell. 17-. (canceled)8. A method for fabricating an electronic device including a semiconductor memory , comprising:forming a first interlayer dielectric layer and a bottom electrode over a substrate, the first interlayer dielectric layer including an opening to expose the bottom electrode;forming a variable resistance material layer along sidewalls of the opening and the exposed bottom electrode;forming a top electrode over the variable resistance material layer so as to fill the opening;etching the first interlayer dielectric layer to a predetermined depth; anddeactivating a part of the variable resistance material layer which surrounding the sidewalls of the top electrode to form a unit cell.9. The method of claim 8 , wherein the variable resistance material layer has a horizontal part and a vertical part claim 8 , andthe etching of the first interlayer dielectric layer includes etching the first interlayer dielectric layer to a level corresponding to the surface of the horizontal part of the variable resistance material layer.10. The method of claim 8 , wherein the deactivating of the part of the variable resistance material layer includes performing an ion implantation process or oxidation ...

Подробнее
Номер записи: 78
02-04-2015 дата публикации

Phase change memory and fabrication method

Номер: US20150090954A1
Автор: Ying Li
Принадлежит: Semiconductor Manufacturing International Corp, Shanghai Institute of Microsystem and Information Technology of CAS

A phase change memory and its fabrication method are provided. A bottom electrode structure is provided through a substrate. A mask layer is formed on the substrate and the bottom electrode structure. A first opening is formed in the mask layer to expose the bottom electrode structure. A spacer is formed on sidewalls and bottom surface portions of the first opening to expose a surface portion of the bottom electrode structure. The first opening including the spacer therein has a bottom width less than a top width. A heating layer is formed at least on the surface portion of the bottom electrode structure exposed by the spacer. A phase change layer is formed on the heating layer to completely fill the first opening. A top electrode is formed on the phase change layer and the mask layer.

Подробнее
Номер записи: 79
12-03-2020 дата публикации

VERTICAL ARRAY OF RESISTIVE SWITCHING DEVICES HAVING RESTRICTED FILAMENT REGIONS AND TUNABLE TOP ELECTRODE VOLUME

Номер: US20200083293A1
Автор: Ando Takashi, Bruce Robert L., Miyazoe Hiroyuki, Rozen John
Принадлежит:

Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region. 1. A vertical resistive device comprising:a horizontal plate comprising a conductive electrode region and a filament region;an opening extending through the filament region and defined by sidewalls of the filament region, wherein the filament region is positioned outside of the opening; anda conductive pillar positioned within the opening and communicatively coupled to the filament region.2. The device of further comprising:a first dielectric layer across from the conductive electrode region and the filament region of the horizontal plate; anda second dielectric layer on an opposite side the horizontal plate than the first dielectric layer and positioned across from the conductive electrode region and the filament region of the horizontal plate;wherein the opening also extends through the first dielectric layer and the second dielectric layer;wherein sidewalls of the opening are also defined by sidewalls of the first dielectric layer and sidewalls of the second dielectric layer.3. The device of claim 2 , wherein the filament region is bound by the horizontal plate claim 2 , the first dielectric layer claim 2 , the second dielectric layer claim 2 , and the conductive pillar.4. The device of claim 1 , wherein:the pillar comprises a cylindrical shape; andthe filament region comprises a ring shape and extends around the pillar.5. The device of claim 1 , wherein the pillar comprises a reactive electrode and a metal fill material.6. The device of claim 5 , wherein the reactive electrode comprises ...

Подробнее
Номер записи: 80
31-03-2022 дата публикации

PHASE CHANGE MEMORY USING MULTIPLE PHASE CHANGE LAYERS AND MULTIPLE HEAT CONDUCTORS

Номер: US20220102627A1
Автор: Brew Kevin W., OK Injo, Pranatharthiharan Balasubramanian, Wang Wei
Принадлежит:

A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure. 1. A semiconductor structure for reducing a reset current for a phase change memory (PCM) , the semiconductor structure comprising:a bottom electrode;a PCM cell structure disposed over the bottom electrode, the PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers; anda top electrode disposed over the PCM cell structure.2. The semiconductor structure of claim 1 , wherein the plurality of phase change memory layers each include a Ge—Sb—Te (germanium-antimony-tellurium or “GST”) alloy.3. The semiconductor structure of claim 1 , wherein the plurality of phase change memory layers are arranged such that their entire length is perpendicular to the top and bottom electrodes.4. The semiconductor structure of claim 1 , wherein airgaps are defined adjacent the PCM cell structure.5. The semiconductor structure of claim 4 , wherein the airgaps extend from the top electrode to the bottom electrode.6. The semiconductor structure of claim 1 , wherein the PCM cell structure defines a substantially U-shaped configuration.7. The semiconductor structure of claim 6 , wherein an oxide material is disposed within the U-shaped configuration.8. The ...

Подробнее
Номер записи: 81
12-03-2020 дата публикации

METHOD OF FABRICATING RESISTIVE MEMORY

Номер: US20200083446A1
Автор: Chen Frederick, Fu Chih-Cheng, HO Chia-Hua, HSU PO-YEN, Shen Ting-Ying
Принадлежит: WINBOND ELECTRONICS CORP.

Provided is a method of fabricating a resistive memory including forming a first electrode and a second electrode opposite to each other; forming a variable resistance layer between the first electrode and the second electrode; forming an oxygen exchange layer between the variable resistance layer and the second electrode; and forming a protection layer at least covering sidewalls of the oxygen exchange layer. 1. A method of fabricating a resistive memory , comprising:forming a first electrode and a second electrode opposite to each other;forming a variable resistance layer between the first electrode and the second electrode;forming an oxygen exchange layer between the variable resistance layer and the second electrode; andforming a protection layer at least covering sidewalls of the oxygen exchange layer.2. The method of fabricating the resistive memory as recited in claim 1 , wherein the step of forming the oxygen exchange layer between the variable resistance layer and the second electrode comprises:forming a first dielectric layer on the variable resistance layer;forming an opening in the first dielectric layer; andfilling the opening with the oxygen exchange layer.3. The method of fabricating the resistive memory as recited in claim 2 , further comprising conformally forming the protection layer in the opening before filling the opening with the oxygen exchange layer.4. The method of fabricating the resistive memory as recited in claim 3 , wherein the protection layer conformally covers a bottom and sidewalls of the opening and extends to a top surface of the first dielectric layer claim 3 , such that the protection layer is sandwiched between the top surface of the first dielectric layer and a bottom surface of the second electrode.5. The method of fabricating the resistive memory as recited in claim 3 , wherein the protection layer further extends to a space between the oxygen exchange layer and the variable resistance layer and extends to a top surface of ...

Подробнее
Номер записи: 82
29-03-2018 дата публикации

PHASE-CHANGE MEMORY CELL

Номер: US20180090542A1
Автор: Favennec Laurent, Gourvest Emmanuel, Le Friec Yannick
Принадлежит: STMICROELECTRONICS (CROLLES 2) SAS

Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via. 1. An assembly of two phase-change memory cells , comprising:a first conductive via and a second conductive via each made of a first metal;a central conductive via located between the first and second conductive vias, a lower portion of the central conductive via being made of the first metal and an upper portion of the central conductive via being made of a second metal;a first resistive element on the first conductive via and a second resistive element on the second conductive via; anda layer of phase-change material in contact with a top portion of each of the first and second resistive elements.2. The assembly of two phase-change memory cells of claim 1 , wherein the first metal is tungsten and the second metal is copper.3. The assembly of two phase-change memory cells of claim 1 , wherein the central via has a shape in the form of an elongated conductive strip.4. The assembly of two phase-change memory cells of claim 1 , wherein the first and second conductive vias are each formed of a lower portion made of the first metal and of an upper portion made of the second metal.5. The assembly of two phase-change memory cells of claim 1 , comprising a first transistor and a second transistor claim 1 , a drain of the first transistor being in contact with the first conductive via ...

Подробнее
Номер записи: 83
21-03-2019 дата публикации

MEMORY DEVICE

Номер: US20190088718A1
Автор: Sakamoto Kei
Принадлежит: Toshiba Memory Corporation

A memory device includes: a wiring; an electrode that includes a first portion provided on the wiring, and a second portion provided on the first portion; a first pillar and a second pillar that are provided inside the second portion; a first conductive layer that is provided below the first pillar; and a second conductive layer that is provided below the second pillar. The second portion includes a first conductive portion provided around the first pillar and including a first conductive material, a second conductive portion provided around the second pillar and containing the first conductive material, and a third conductive portion provided around the first and second conductive portions, containing a second conductive material, and electrically connected to the first portion and the first and second conductive portions. The first portion includes the second conductive material. 1. A memory device comprising:a wiring;an electrode that includes a first portion provided on the wiring and electrically connected to the wiring, and a second portion provided on and electrically connected to the first portion;a first pillar provided inside the second portion;a second pillar provided inside the second portion;a first conductive layer provided below the first pillar, extending in a first direction, and electrically connected to the first pillar; anda second conductive layer provided below the second pillar, extending in the first direction, and electrically connected to the second pillar, a first conductive portion provided around the first pillar and comprising a first conductive material,', 'a second conductive portion provided around the second pillar and comprising the first conductive material, and', 'a third conductive portion provided around the first and second conductive portions, comprising a second conductive material, and electrically connected to the first and second conductive portions, and', 'wherein the first portion of the electrode comprises the second ...

Подробнее
Номер записи: 84
21-03-2019 дата публикации

Storage device and method for manufacturing the same

Номер: US20190088872A1
Автор: Atsushi Hieno, Yusuke Tanaka
Принадлежит: Toshiba Memory Corp

A storage device according to an embodiment includes a first conductive layer, a second conductive layer, and a resistance change layer. The resistance change layer is positioned between the first conductive layer and the second conductive layer. The resistance change layer including an organic compound. The organic compound has at least one first functional group selected from the group consisting of an amino group, a thiol group, a carboxy group, and an azide group, and the organic compound has one or less aromatic rings.

Подробнее
Номер записи: 85
05-05-2022 дата публикации

PHASE-CHANGE MEMORY

Номер: US20220140232A1
Автор: Boivin Philippe, MOUSTAPHA-RABAULT Yohann, SIMOLA Roberto
Принадлежит:

The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

Подробнее
Номер записи: 86
05-05-2022 дата публикации

FILL-IN CONFINED CELL PCM DEVICES

Номер: US20220140237A1
Автор: Adusumilli Praneet, BrightSky Matthew Joseph, Bruce Robert L., Cohen Guy M.
Принадлежит:

A method for manufacturing a phase-change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase-change material over the substrate, implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize at least a portion of the phase-change material inside the pore, planarizing the device to exposed the surface of the substrate, and forming a plurality of top electrodes over the pores, in contact with the phase-change material.

Подробнее
Номер записи: 87
30-03-2017 дата публикации

Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells

Номер: US20170092695A1
Автор: Jun Liu, Kunal R. Parekh
Принадлежит: Micron Technology Inc

An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

Подробнее
Номер записи: 88
26-06-2014 дата публикации

PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140175358A1
Автор: CHEONG Jung Taik, LEE Hyun Min
Принадлежит:

A phase-change random access memory device and a method of manufacturing the same are provided. The method includes providing a semiconductor substrate including a heating electrode, forming an interlayer insulating layer including a preliminary phase-change region on the semiconductor substrate, reducing a diameter of an inlet portion of the preliminary phase-change region to be smaller than that of a bottom portion of the preliminary phase-change region, filling an insulating layer having a void in the preliminary phase-change region using a difference between the diameter of the inlet portion and the diameter of the bottom portion, removing the insulating layer to an interface between the inlet portion and the bottom portion, thereby forming a key hole exposing the heating electrode, and forming a phase-change material layer to be buried in the key hole and the preliminary phase-change region. 1. A method of manufacturing a phase-change random access memory (PRAM) device , comprising:providing a semiconductor substrate including a heating electrode;forming an interlayer insulating layer including a preliminary phase-change region on the semiconductor substrate;reducing a diameter of an inlet portion of the preliminary phase-change region to be smaller than that of a bottom portion of the preliminary phase-change region;filling an insulating layer having a void in the preliminary phase-change region using a difference between the diameter of the inlet portion and the diameter of the bottom portion;removing the insulating layer to an interface between the inlet portion and the bottom portion, thereby forming a key hole exposing the heating electrode; andforming a phase-change material layer to be buried in the key hole and the preliminary phase-change region.2. The method of claim 1 , further comprising: between the forming an interlayer insulating layer including an preliminary phase-change region on the semiconductor substrate and the reducing a diameter of an ...

Подробнее
Номер записи: 89
19-03-2020 дата публикации

VERTICAL ARRAY OF RESISTIVE SWITCHING DEVICES HAVING A TUNABLE OXYGEN VACANCY CONCENTRATION

Номер: US20200091231A1
Автор: Ando Takashi, Lee Choonghyun
Принадлежит:

Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a conductive horizontal electrode, an opening extending through the horizontal electrode, a filament region positioned within the opening and communicatively coupled to a sidewall of the horizontal electrode, and a conductive vertical electrode positioned within the opening and communicatively coupled to the filament region. The vertical electrode includes a first conductive alloy material. Oxygen vacancy formation in the filament region is controlled by the first conductive alloy material of the vertical electrode. A room temperature resistivity of the first conductive alloy material is below about 5×10ohm meters and controlled by at least one of the metals that form the first conductive alloy material. 1. A method of fabricating a vertical resistive device , the method comprising:forming a conductive horizontal electrode;forming an opening that extends through the horizontal electrode;depositing a filament region within the opening such that the filament region is communicatively coupled to a sidewall of the horizontal electrode;depositing a barrier region within the opening such that the barrier region is communicatively coupled to the filament region; andforming a conductive vertical electrode within a remaining portion of the opening such that the vertical electrode is communicatively coupled to the barrier region; the vertical electrode comprises a first conductive alloy material;', 'oxygen vacancy formation in the filament region is controlled by the first conductive alloy material of the vertical electrode; and', {'sup': '−8', 'a room temperature resistivity of the first conductive alloy material is below about 5×10ohm meters and controlled by at least one of the metals that form the first conductive alloy material.'}], 'wherein2. The method of claim 1 , wherein the at least one of the metals that form the first ...

Подробнее
Номер записи: 90
19-03-2020 дата публикации

STORAGE DEVICE

Номер: US20200091238A1
Автор: SANUKI Tomoya
Принадлежит:

According to one embodiment, a storage device includes a first conductor extending along a first direction, first variable-resistance elements on the first conductor, and a second conductor on the first variable-resistance elements and extending along a second direction. A plurality of second variable-resistance elements is on the second conductor. A third conductor is on the plurality of second variable-resistance elements. The third conductor extends along the first direction. A first switching element is connected between the second conductor and a corresponding one of the first variable-resistance elements. A second switching element is connected between the third conductor and a corresponding one of second variable-resistance elements. 1. A storage device , comprising:a first conductor extending along a first direction;a plurality of first variable-resistance elements on the first conductor;a second conductor on the plurality of first variable-resistance elements, the second conductor extending along a second direction;a plurality of second variable-resistance elements on the second conductor;a third conductor on the plurality of second variable-resistance elements, the third conductor extending along the first direction;a first switching element connected between the second conductor and a corresponding one of the first variable-resistance elements; anda second switching element connected between the third conductor and a corresponding one of second variable-resistance elements.2. The storage device according to claim 1 , wherein the first switching element is between the second conductor and the corresponding one of the first variable-resistance elements.3. The storage device according to claim 1 , wherein the first switching element is between the first conductor and the corresponding one of the first variable-resistance elements.4. The storage device according to claim 1 , wherein the second switching element is between the second conductor and the ...

Подробнее
Номер записи: 91
05-04-2018 дата публикации

METAL LANDING ON TOP ELECTRODE OF RRAM

Номер: US20180097177A1
Автор: CHANG Chih-Yang, Chu Wen-Ting
Принадлежит:

Some embodiments relate to a method. A semiconductor substrate is received. The semiconductor substrate has an interconnect structure disposed over a memory region and a logic region of the semiconductor substrate. A bottom electrode and a top electrode are formed over the interconnect structure over the memory region. The bottom electrode is coupled to a lower metal layer in the interconnect structure, and the bottom and top electrode are separated from one another by a data storage or dielectric layer. An interlayer dielectric (ILD) layer is formed over the top electrode. A trench opening having vertical or substantially vertical sidewalls is formed in the ILD layer and exposes an upper surface of the top electrode. An upper metal layer is formed in the trench opening and is in direct contact with the top electrode. 1. A method , comprising:receiving a semiconductor substrate having an interconnect structure disposed over a memory region and a logic region of the semiconductor substrate;forming a bottom electrode and a top electrode over the interconnect structure over the memory region, wherein the bottom electrode is coupled to a lower metal layer in the interconnect structure and wherein the bottom and top electrode are separated from one another by a data storage or dielectric structure;forming an interlayer dielectric (ILD) layer over the top electrode;forming a trench opening having vertical or substantially vertical sidewalls in the ILD layer and which exposes an upper surface of the top electrode; andforming an upper metal layer in the trench opening, the upper metal layer being in direct contact with the top electrode.2. The method of claim 1 , further comprising:forming a via opening that extends downward from a trench opening in the ILD layer over the logic region, wherein the via opening exposes an upper surface of the lower metal layer over the logic region, wherein the via opening is filled concurrently with the trench opening.3. The method of claim ...

Подробнее
Номер записи: 92
01-04-2021 дата публикации

METHOD OF MAKING RESISTIVE STRUCTURE OF RRAM

Номер: US20210098699A1
Автор: Tang Youqing, Zhang Zhigang
Принадлежит:

A method for making an RRAM resistive structure includes, step 1, forming a via structure, which includes depositing an ultra-low dielectric constant material layer on a substrate, depositing a copper layer on the ultra-low dielectric constant material layer, depositing a carbon-containing silicon nitride layer, and patterning a via in the carbon-containing silicon nitride layer. step 2, filling the via structure with a TaN layer, followed by planarizing a surface of the via structure without dishing; step 3, forming a first TiN layer on the TaN-filled via structure; and step 4, forming an RRAM resistive structure stack having layers of TaOx, TaO, Ta, and a second TiN from bottom to top on the first TiN layer, and step 5, patterning the RRAM resistive structure stack the first TiN layer over the TaN-filled via structure to form the RRAM resistive structure. 1. A method for making an RRAM resistive structure , comprising at least the following steps:Step 1, forming a via structure of the RRAM resistive structure;Step 2, filling the via structure with a TaN layer, followed by planarizing a surface of the via structure;Step 3, forming a first TiN layer on the TaN-filled via structure; andStep 4, forming an RRAM resistive structure stack on the first TiN layer.2. The method for making the RRAM resistive structure claim 1 , according to claim 1 , wherein forming the via structure in Step 1 comprises depositing an ultra-low dielectric constant material layer on a substrate claim 1 , depositing a copper layer on the ultra-low dielectric constant material layer claim 1 , depositing a carbon-containing silicon nitride layer claim 1 , and patterning a via in the carbon-containing silicon nitride layer claim 1 , wherein a bottom of the via exposes the copper layer.3. The method for making the RRAM resistive structure claim 1 , according to claim 1 , wherein filling the via structure with the TaN layer in Step 2 applies a deposition method.4. The method for making the RRAM ...

Подробнее
Номер записи: 93
28-03-2019 дата публикации

Semiconductor memory device

Номер: US20190096481A1
Автор: Chika Tanaka, Masumi SAITOH
Принадлежит: Toshiba Memory Corp

A semiconductor memory device includes a substrate, a stacked body comprising a plurality of first conductors extending in a first direction away from a surface of the substrate and spaced from one another in second and third directions intersecting the first direction and each other, the stacked body having a first region and a second region, a plurality of second conductors extending in the second direction, a plurality of third conductors extending in the third, each third conductor connected to a first end, in the second direction, of a plurality of second conductors in the first region, a plurality of fourth connectors extending in the first direction, each fourth conductor connected to the plurality of second conductors in the second region, and memory cells located between adjacent surfaces of the first and second conductors in the first region.

Подробнее
Номер записи: 94
28-03-2019 дата публикации

Methods for forming narrow vertical pillars and integrated circuit devices having the same

Номер: US20190097129A1
Автор: Jun Liu, Kunal Parekh
Принадлежит: Micron Technology Inc

In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

Подробнее
Номер записи: 95
14-04-2016 дата публикации

METHOD OF FABRICATING A VARIABLE RESISTANCE MEMORY DEVICE

Номер: US20160104841A1
Автор: AHN JUNKU
Принадлежит:

A method of fabricating a variable resistance memory device includes preparing a substrate having a lower electrode, forming a mold layer on the substrate, patterning the mold layer to form an opening, forming a variable resistance layer having a first portion in the opening and a second portion disposed on a top surface of the mold layer, and separating the second portion of the variable resistance layer from the first portion by irradiating the variable resistance layer to form a variable resistance element in the opening. 1. A method of fabricating a variable resistance memory device , the method comprising:providing a substrate on which a lower electrode is disposed;forming a mold layer on the substrate;patterning the mold layer to form an opening;forming a variable resistance layer on the mold layer, the variable resistance layer having a first portion in the opening, and a second portion extending over a top surface of the mold layer; andseparating the second portion of the variable resistance layer from the first portion to thereby form a variable resistance element in the opening, wherein said separating comprise irradiating the variable resistance using a laser.2. The method of claim 1 , wherein the separating of the second portion of the variable resistance layer from the first portion comprises melting and/or vaporizing only the second of the first and second portions of the variable resistance layer using the laser.3. The method of claim 1 , further comprising:forming a sacrificial layer on the mold layer before forming the opening; andpatterning the sacrificial layer to form a sacrificial pattern on the mold layer.4. The method of claim 3 , wherein the separating of the second portion of the variable resistance layer from the first portion comprises melting the sacrificial pattern using the laser to facilitate a separating of the sacrificial pattern from the mold layer.5. The method of claim 4 , wherein the separating of the second portion of the ...

Подробнее
Номер записи: 96
08-04-2021 дата публикации

RESISTIVE SWITCHING DEVICE HAVING CONTROLLED FILAMENT FORMATION

Номер: US20210104664A1
Автор: Lee Choonghyun, OK Injo, Reznicek Alexander, Seo Soon-Cheon
Принадлежит:

Embodiments of the invention are directed to an integrated circuit structure that includes a resistive switching device (RSD). The RSD includes a bottom electrode, an insulator region, and a top electrode. The insulator region includes a filament region and is communicatively coupled to the bottom electrode. The top electrode is communicatively coupled to the insulator region. The filament region includes an apex region having a first apex region sidewall and a second apex region sidewall that intersects the first apex region sidewall at an angle that is less than about 90 degrees. 1. An integrated circuit structure comprising: a bottom conductive electrode;', 'an insulator region communicatively coupled to the bottom conductive electrode, wherein the insulator region comprises a filament region; and', 'a top conductive electrode communicatively coupled to the insulator region;, 'a resistive switching device (RSD) comprisingwherein the filament region comprises an apex region comprising a first apex region sidewall and a second apex region sidewall; andwherein the second apex region sidewall intersects the first apex region sidewall at an angle that is less than about 90 degrees.2. The structure of claim 1 , wherein the first apex region sidewall is substantially planar and the second apex region sidewall is substantially planar.3. The structure of claim 1 , wherein the first apex region sidewall is substantially non-planar and the second apex region sidewall is substantially non-planar.4. The structure of claim 1 , wherein the RSD is configured to claim 1 , based on a voltage applied across the bottom conductive electrode and the top conductive electrode claim 1 , form filaments in the filament region.5. The structure of claim 4 , wherein more than one half of the filaments formed in the filament region are formed in the apex region.6. The structure of claim 1 , wherein the filament region comprises a metal oxide.7. The structure of claim 6 , wherein the metal ...

Подробнее
Номер записи: 97
08-04-2021 дата публикации

Three-dimensional stacked memory and preparation method thereof

Номер: US20210104670A1
Автор: Hao Tong, Xiangshui Miao, Yushan SHEN
Принадлежит: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

The disclosure discloses a three-dimensional stacked memory and a preparation method thereof. The storage unit adopts a constrained structure phase change storage unit, and uses a crossbar storage array structure to build a large-capacity storage array. The preparation method includes: preparing N first strip-shaped electrodes along a crystal direction on a substrate; preparing a first insulating layer with M*N array of through holes; filling the M*N array of through holes of the first insulating layer with a phase change material to form first phase change units; preparing M second strip-shaped electrodes; preparing a second insulating layer, using spin-coated photoresist as a sacrificial material, performing a local planarization on the surface of the second insulating layer; forming M*N array of through holes on the second insulating layer; filling a phase change material to form second phase change units; preparing N third strip-shaped electrodes to form a two-layer stacked phase change memory.

Подробнее
Номер записи: 98
26-03-2020 дата публикации

TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT

Номер: US20200098983A1
Автор: CHANG Chih-Yang, Chen Hsia-Wei, Chu Wen-Ting, Liao Yu-Wen, Shih Sheng-Hung, Tu Kuo-Chi, Yang Chin-Chieh, You Wen-Chun
Принадлежит:

Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface. 1. A device , comprising:a top electrode having a recess in its upper surface;a blocking structure disposed over the top electrode and arranged within the recess; anda via disposed over the blocking structure, wherein the via contacts the top electrode within the recess in an area above the blocking structure.2. The device of claim 1 , wherein the blocking structure comprises a dielectric material sandwiched between a lower surface of the via and the upper surface of the top electrode.3. The device of claim 1 , wherein the top electrode comprises:a central upper electrode portion having a first thickness; anda peripheral upper electrode portion having a second thickness that differs from the first thickness.4. The device of claim 3 , wherein the first thickness is less than the second thickness.5. The device of claim 4 , wherein the first thickness is half of or less than half of the second thickness.6. The device of claim 1 , further comprising:a bottom electrode, wherein the top electrode is arranged over the bottom electrode and wherein a dielectric layer separates the bottom electrode from the top electrode; andwherein the bottom electrode is disposed over a semiconductor substrate, and wherein at least one metal layer is disposed between the bottom electrode and the semiconductor substrate.7. The device of claim 6 , further comprising:sidewall spacers disposed over an upper surface of the bottom electrode and along outer sidewalls of the top electrode.8. The device of claim 6 , further comprising:an etch stop ...

Подробнее
Номер записи: 99
26-03-2020 дата публикации

METHOD FOR MANUFACTURING PHASE CHANGE MEMORY

Номер: US20200098986A1
Автор: BRIGHTSKY Matthew, BRUCE Robert, Carta Fabio, FRACZAK, Fraczak Gloria Wing Yun, Lam Chung Hon, Masuda Takeshi, Suu Koukou
Принадлежит:

Method(s) and apparatuses for forming a phase change memory. A method includes: forming a crystalline phase-change layer at a first position in along a surface of a first semiconductor layer, and forming an amorphous phase-change layer at a second position along the surface of a second semiconductor layer, wherein the crystalline phase-change layer and the amorphous phase-change layer are in contact. 1. A method for manufacturing a phase-change memory , the method comprising:forming a crystalline phase-change layer at a first position in a recess of an insulation layer; andforming an amorphous phase-change layer at a second position, which differs from the first position, in the recess.2. The method according to claim 1 , wherein forming the amorphous phase-change layer is performed after forming the crystalline phase-change layer.3. The method according to claim 1 , wherein forming the crystalline phase-change layer is performed after forming the amorphous phase-change layer.4. The method according to claim 3 , whereinforming the amorphous phase-change layer includes forming a first amorphous phase-change layer, andthe method further comprises forming a second amorphous phase-change layer at a third position in the recess after forming the crystalline phase-change layer, wherein the third position differs from the first position and the second position.5. The method according to claim 1 , whereinforming the crystalline phase-change layer and forming the amorphous phase-change layer fills a cavity defined by the recess with the crystalline phase-change layer and the amorphous phase-change layer, andthe amorphous phase-change layer and the crystalline phase-change layer are formed in the cavity of the recess so that the amorphous phase-change layer has a smaller volume than the crystalline phase-change layer.6. The method according to claim 1 , wherein forming the crystalline phase-change layer comprises:forming the crystalline phase-change layer with a different ...

Подробнее
Номер записи: 100