МИНИМИЗАЦИЯ ПЕРЕХОДНОГО ПРОЦЕССА В ВИДЕ КОЛЕБАНИЙ В ПОЛУПРОВОДНИКОВЫХ УСТРОЙСТВАХ С ШИРОКОЙ ЗАПРЕЩЕННОЙ ЗОНОЙ

Steuerschaltung für Halbleitervorrichtung

Miniaturisiertes Schaltnetzteil mit Gateansteuerung mit programmiertem Niveau

FET-Tiefpass

Integriertes Schaltelement umfassend mindestens einen Feldeffekttransistor (1), eine mindestens ebensolche Anzahl an Ansteuerungsschaltvorrichtungen (12) für den mindestens einen Feldeffekttransistor (1), einen variabel einstellbaren ohmschen Widerstandswert (13), angeordnet zwischen Feldeffekttransistor (1) und Ansteuerungsschaltvorrichtung (12).

Halbleiterrelais

GATE-ANSTEUERVORRICHTUNG, SCHALTVORRICHTUNG UND GATE-ANSTEUERVERFAHREN

Wenn sich ein Strom, der durch eine Schalteinrichtung fließt, wesentlich ändert, beginnt ein Zeitraum nach dem Ausschalten, bis sich eine Stoßspannung ändert, so dass die Stoßspannung nicht verringert werden muss. Eine Gate-Ansteuervorrichtung wird geschaffen. Die Gate-Ansteuervorrichtung enthält eine Gate-Ansteuereinheit, die konfiguriert ist, ein Gate einer Schalteinrichtung anzusteuern; eine Parametermesseinheit, die konfiguriert ist, einen Parameter zu messen, der einem Strom, der durch die Schalteinrichtung fließt, entspricht; eine Diskrepanzdetektionseinheit, die konfiguriert ist, eine Diskrepanz zwischen einem Strom, der während eines Ein-Zustands der Schalteinrichtung durch die Schalteinrichtung fließt, und einem Bezugswert auf der Grundlage des Parameters zu detektieren; und eine Steuereinheit, die dann, wenn die Diskrepanz nicht detektiert wird, eine Änderungsgeschwindigkeit einer Gate-Spannung der Schalteinrichtung zu einem Zeitpunkt, wenn eine Bezugszeit seit einem Ausschaltbeginn ...

High-seitige Gate-Treiberschaltung, Halbleitermodul und Dreiphasen-Invertersystem

High-seitige Gate-Treiberschaltung (103) zum Ansteuern eines high-seitigen Schaltelements (Q1), wobei die high-seitige Gate-Treiberschaltung (103) Folgendes umfasst:- Impulsgenerierungsschaltungen (11, 12), die konfiguriert sind, einen ersten Impuls zu generieren, der mit einem Eingangssignal synchronisiert ist; und- Pegelverschiebungsschaltungen (17, 18), die konfiguriert sind, einen Pegel einer Referenzspannung für den ersten Impuls zu einer Versorgungsspannung (VB) des High-seitigen Schaltelementes (Q1) zu verschieben, wobei:- die Pegelverschiebungsschaltungen (17, 18) MOSFETs (176, 186) aufweisen, die jeweils durch den ersten Impuls angesteuert werden,- die high-seitige Gate-Treiberschaltung (103) Folgendes umfasst:- eine Maskensignalgenerierungsschaltung (26), die konfiguriert ist, ein Maskensignal (M) zu generieren, das in einer Periode zu einem hohen Pegel wird, in der das Source-Potenzial der MOSFETs (176, 186) zu einem hohen Pegel wird; und- Reshot-Schaltungen (36, 37), die konfiguriert ...

HALBBRÜCKENTREIBERSCHALTUNG

DATA OUTPUT BUFFER CIRCUIT FOR BYTE-WIDE MEMORY

Minimizing ringing in wide band gap semiconductor devices

A power conversion circuit 100 comprises first and second semiconductor switches 102, 104, and a drive circuit 114 configured to create a period of operational overlap for the first and second switches. The drive circuit sets a gate voltage of the first switch to an intermediate value VInt above a threshold voltage VThreshold of the first switch during turn-ON and turn-OFF operations of the second switch. A method of operating first and second semiconductor devices (Fig.4) comprises reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is OFF, turning OFF the first device after the second device is ON, increasing the gate voltage of the first device to the intermediate value while the second device is ON, and fully turning ON the first device after the second device is OFF. The semiconductor switches may be metal oxide semiconductor field effect transistors (MOSFETs) comprising a wide band gap (WBG) material, e.g. Silicon ...

Current switching circuit

Wear assembly for the digging edge of an excavator

Wear assembly for the digging edge of an excavator.

Wear assembly for the digging edge of an excavator.

Wear assembly for the digging edge of an excavator.

Wear assembly for the digging edge of an excavator.

ARRANGEMENT FOR NOISE SUPPRESSION IN A CURRENT ELECTRIC CURRENT

GATE ELECTRODE DRIVER

PROCEDURE FOR THE SWITCHING ON REGULATION OF A IGBTS AND A DEVICE FOR THE EXECUTION OF THE PROCEDURE

EMENT

Gate drive for insulated gate power semiconductors

CIRCUIT ARRANGEMENT AND METHOD FOR DRIVING A GATE OF A TRANSISTOR, IN PARTICULAR A MOSFET

The present invention relates to a circuit arrangement for driving a gate of a transistor, in particular a MOSFET, which is arranged in an electronic ballast, the circuit arrangement (2) being designed for the variable driving of the gate (221) as a function of the operating state of the electronic ballast. The invention also relates to a method for driving a gate of such a transistor.

BUS TRANSMITTER HAVING CONTROLLED TRAPEZOIDAL SLEW RATE

A transmitter circuit for transmitting a digital data signal over a bus in a digital data processing system includes a MOSFET bus driver transistor having a gate to drain capacitance CGD which substantially dominates other capacitances at the gate terminal. The bus driver transistor is driven by a buffer circuit having pull-up and pull-down transistors current through which is controlled by current sources. The gate terminal of the driver transistor is connected to, and controlled by, the node between the pull-up and pull-down transistors. The drain terminal of the driver transistor is connected to, and controls, a bus line. To assert a signal on the bus line, the pull-up transistor is turned on to drive current into the node at a rate governed by the current source, which increases the voltage level of the node. When the voltage level of the node reaches the driver transistor's threshold level, the driver transistor begins to turn on, allowing the voltage level of the bus line to drop.

GATE DRIVE FOR INSULATED GATE POWER SEMICONDUCTORS

A method of control of the current and voltage switching trajectories of insulated gate power semiconductor switches, more specifically MOSFETs and insulated gate bipolar transistor devices (IGBTs), is disclosed. MOSFETs and IGBTs are used in switch mode power supplies because of their easy driving ability and their ability to handle high currents and voltages at high- switching frequencies. However, the switching trajectories for both types of devices are responsible for both common-mode electromagnetic emissions generated by the drain current waveform and power losses in the commutation cell. These two characteristics represent opposing design objectives for power converters. The current invention uses a hybrid voltage/current gate signal source with feedback of the gate charge (or discharge) current to dynamically and independently control the drain current and drain voltage of an insulated semiconductor device. The rate of change of drain current is controlled by the voltage source ...

POWER SWITCH WITH INRUSH CURRENT CONTROL

A power control circuit is provided for coupling a load to a power source. It includes a transistor for coupling said load to the power supply through the transistor dependent upon a control voltage applied to a control terminal of the transistor, a charge pump circuit having its output connected to the transistor control terminal to apply a controlled turn on signal to the transistor when the charge pump is activated, wherein the controlled signal gradually increases until the transistor is biased into its fully on state.

Device for controlling detachable power semiconductors, has common mode interference resistance of more than fifteen kilowatt per microsecond for potential-free control of interconnection of multiple power semiconductors

The device (1) has a common mode interference resistance of more than fifteen kilowatt per microsecond for the potential-free control of an interconnection of multiple power semiconductors (2), which contain connections. The connections are functionally equivalent to a gate, a source and a drain of a transistor. A diode forms the input voltage of the direct current converter (6). The diode is branched from a drain (8) of the power semiconductor.

Intelligenter Taster für eine Gebäudeinstallation.

Die Erfindung betrifft einen intelligenten Taster (1) für eine Gebäudeinstallation. Der Taster (1) weist eine für die Gebäudeinstallation geeignete vorgegebene Grösse auf und elektrische Anschlüsse (1224) auf, an welche wahlweise eine elektrische Lichtquelle oder ein elektrischer Motor anschliessbar sind, wobei der Taster ausgebildet ist zum Ein-/Ausschalten und allenfalls Dimmen der anschliessbaren Lichtquelle und zum Betreiben des anschliessbaren elektrischen Motors.

ИЗНАШИВАЕМОЕ УСТРОЙСТВО ДЛЯ РЕЖУЩЕЙ КРОМКИ ЭКСКАВАТОРА

Настоящее изобретение относится к изнашиваемому устройству для присоединения изнашиваемых элементов к краю ковша экскаватора, содержащему изнашиваемый элемент, выступ и замок. Край ковша включает внутреннюю поверхность, внешнюю поверхность, режущую кромку и ряд сквозных окон, отстоящих от режущей кромки. Каждый выступ присоединен к поверхности края ковша позади сквозных окон. В каждом изнашиваемом элементе у задних концов выполнены пазы для введения выступов и отверстия для замков, расположенные перед выступами. Отверстия расположены на одной оси со сквозными окнами края ковша. Замок содержит клин и вставку.

WEARABLE DEVICE ARRANGED FOR CUTTING EDGE EXCAVATOR

Semiconductor device

For the selection of the power semiconductor in the disconnection of the speed of the disconnect process method

Output driver with low ground jump noise

CONTROL DEVICE Of a TRANSISTOR OF POWER

INTEGRATED CIRCUIT INCLUDING/UNDERSTANDING A TRANSISTOR OF EXIT HAVING A TIME OF PASSAGE HAS ZERO CONTROL

L'invention concerne un circuit intégré (20) comprenant un transistor MOS de sortie (TOUT) dont la grille est pilotée par la sortie d'un circuit logique (11), le circuit intégré étant alimenté électriquement par une tension déterminée (VCC). Selon l'invention, le circuit intégré comprend un circuit (41) de polarisation de la grille du transistor (TOUT) prévu pour abaisser la tension de polarisation grille-source (VGS) du transistor à l'état passant relativement à celle (VCC) qui serait fixée par la sortie du circuit logique (11) en l'absence d'un tel circuit de polarisation (41). Avantages : augmentation du temps de passage à zéro ("fall time ") sans diminution du courant de sortie à l'état bas. Application notamment aux étages de sortie pour bus I2C.

DRIVE UNIT FOR DRIVING VOLTAGE-DRIVEN ELEMENT

DATA OUTPUT BUFFER CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE

The buffer circuit includes a depletion type transistor (MDEP1; MDEP3) connected between a P-channel transistor (M9, M13) and an n- channel transistor (M10, M14) of a pull-up inverter (I1, I3) and for delaying the rising and falling time of a gate voltage of a pull-up transistor (Mpu3, Mpu4). In addition, there is a depletion type transistor (MDEP2, MDEP4) connected between a P-channel transistor (M11, M15) and an n-channel transistor (M12, M16) of a pull-down inverter (I2, I4) and for delaying the rising and falling time of a pull-down transistor (Mpd3, Mpd4). the circuit reduces noise on the power supply and earthing lines and improves operational velocity. Copyright 1997 KIPO ...

GLOBAL CLOSED LOOP CONTROL SYSTEM WITH DV/DT CONTROL AND EMI/SWITCHING LOSS REDUCTION

A motor drive system (10) control provides global closed loop feedback to cooperatively operate system components to adaptively reduce noise and provide noise cancellation feedback. An active EMI filter (12) reduces differential and common mode noise on an input and provides a noise level indication to a system controller (11). Power switches in both a power converter (14) and power inverter (16) are cooperatively controlled with dynamic dv/dt control to reduce switching noise according to a profile specified by the controller 11). The dv/dt control is provided as an analog signal to a high voltage IC and codified as a pulse width for a level shifting circuit supplying control signals to the high voltage gate drive (18). A noise extraction circuit and technique obtain fast noise sampling to permit noise cancellation and adaptive noise reduction. © KIPO & WIPO 2007 ...

DRIVING CIRCUIT FOR POWER SEMICONDUCTOR SWITCH

The current limit circuit apparatus

The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, and s third resistor. The source and the drain of the first transistor couples with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited, when the current of the gate of the GaN transistor exceeds the predetermined value. The breakdown voltage is increased by limiting the gate current.

DYNAMIC FEEDBACK-CONTROLLED OUTPUT DRIVER WITH MINIMUM SLEW RATE VARIATION FROM PROCESS, TEMPERATURE AND SUPPLY

In examples, apparatus and methods are provided that mitigate buffer slew rate variations due to variations in output capacitive loading, a fabrication process, a voltage, and/or a temperature (PVT). An exemplary embodiment includes an inverting buffer having an input and an output, as well as an active resistance series-coupled with a capacitor between the input and the output. The resistance of the active resistance varies based on a variation in a fabrication process, a voltage, and/or temperature. The active resistance can be a passgate. In another example, a CMOS inverter's output is coupled to the input of the inverting buffer, and two series-coupled inverting buffers are coupled between the input of the CMOS inverter and the output of the inverting buffer.

SWITCHING CIRCUIT FOR THE SERIES IMPLEMENTATION OF IGBT TRANSISTORS

The invention relates to a switching circuit comprising two power transistors (22, 24) connected in series and a circuit (26, 28) for exciting each transistor suitable for simultaneously switching the two transistors. The circuit includes means (30) for generating a corrective current (δi) for controlling a corrected-control transistor (22) among the two transistors (22, 24) according to the difference in temporal variation of the voltage at the conduction terminals of the two series-connected transistors (22, 24), and means (37) for applying said current to the gate electrode of the corrected-control transistor (22).

SWITCHING CONTROL SYSTEMS

We describe a system for controlling very large numbers of power semiconductor switching devices (132) to switch in synchronisation. The devices are high power devices, for example carrying hundreds of amps and/or voltages of the order of kilovolts. In outline the system comprises a coordinating control system (110, 120), which communicates with a plurality of switching device controllers (130) to control the devices into a plurality of states including a fully-off state, a saturated-on state, and at least one intermediate state between the fully-off and saturated-on states, synchronising the devices in the at least one intermediate state during switching.

A MULTIPLE-STAGE CONTROL CIRCUIT TO CONTROL RUSH CURRENT IN A MOSFET LOAD SWITCH

Circuits and methods to turn-on a power MOSFET switch (421a) while limiting rush current delivered to a load (210b) are disclosed. In an exemplary embodiment, a sense circuit (410) senses when the power MOSFET is enhanced by a first level and a second level. A control circuit (405) controls application of three drive forces to the gate of the power MOSFET in response to the sense circuit. The first drive force adjusts the voltage applied to the gate at a first rate. The second drive force adjusts the voltage applied to the gate at a second rate less than the first rate. The third drive force adjusts the voltage applied to the gate at a third rate greater than the second rate. The circuit utilizes most of the allotted turn-on time to linearly control the power MOSFET enhancement, providing optimal slew rate control and limiting the rush current delivered to the load.

Control circuit for semiconductor device

A control circuit for an insulated-gate semiconductor device (IGBT) 1 has a drive circuit 2, which is a series circuit constructed of an npn transistor 3 and a pnp transistor 4, and controls the switching operation of the IGBT 1 in response to an on/off signal 9S from a switching signal source 9. The control circuit includes a switching speed control means 10, a gate potential stabilizing npn transistor 20, and a stable operation extending means 30. The switching speed control means 10 gives predetermined slops to the rise and fall of the on/off signal 9S. The gate potential stabilizing npn transistor 20 is Darlington-connected to the pnp transistor 4 of the drive circuit 2 and has the emitter thereof connected to the source of the IGBT 1. The stable operation extending means 30 generates an on signal to the base of the gate potential stabilizing npn transistor 20 upon sensing a drop in the gate potential of the IGBT 1 to a threshold voltage thereof or less.

Driver circuit having reduced noise

A driver circuit has an output node coupled to a chip pad. A first PFET and a first resistor are connected between a power supply and the output node, wherein the first resistor is connected between the first PFET and the output node. A first NFET and a second resistor are connected between a ground potential and the output node, wherein the second resistor is connected between the first NFET and the output node. A third resistor is connected between an input to the driver circuit and a gate electrode of the first PFET. A fourth resistor is connected between the input to the driver circuit and a gate electrode of the first NFET. The pre-drive circuitry for driving the input to the PFET may include an NFET coupled between the ground potential and the input, wherein the gate electrode of the NFET receives the data signal to be driven. The NFET pre-drive circuitry may include a PFET coupled between the power supply and the input to the NFET portion of the driver circuit, wherein the gate electrode ...

Current controller

A current controller includes a first MOSFET of P type connected at a drain to a first node, at a gate to the input terminal and at a source to a power supply, a second MOSFET of N type connected at a drain to the first node via a first resistor, at a gate to the input terminal and at a source to ground, a third MOSFET of N type connected at a drain to the output terminal, at a gate to the first node via a second resistor and at a source to ground, and a capacitor connected between the gate of the third MOSFET and the power supply. The first and second resistors and the capacitor are set so that the maximum changing rates of rising and falling currents supplied from the output terminal through the third MOSFET are equalized. Therefore, levels of low level data are equalized between the positive and negative sides.

Circuit for accurately discharging a capacitor

A subcircuit for discharging a capacitor at a preselected rate incorporates a first transistor and a second transistor connected with the emitter of the first transistor providing current to the collector of the second transistor. The base of the first transistor is connected to a capacitor to be discharged at a preselected rate. The base current of the first transistor discharges the capacitor as a function of the base current provided to the second transistor. In order to provide a current of very small magnitude to the base of the second transistor, a plurality of lateral PNP transistors are connected in a plural stage arrangement in order to take advantage of the current dividing characteristic of lateral PNP transistors. A collector of one lateral PNP transistor is connected to the emitter of another so that each stage of the subcircuit reduces the output current by a very precise ratio.

Gate drive circuit with feedback-controlled active resistance

An active resistance is controlled to modify a drive signal provided to a gated device such as an insulated gate bipolar transistor (IGBT). The active resistance is between an input lead that receives an input drive signal, such as from a conventional gate driver IC, and an output lead at which an output drive signal is provided to the device's gate. The active resistance is controlled in response to a feedback signal that includes information about the output drive signal, so that the output drive signal is a modified version of the input drive signal. To reduce di/dt and hence control EMI emission, the output drive signal can include turn-on and turn-off transitions where the input drive signal includes steps. A transition can, for example, include an interval during which the active resistance is greater than zero to reduce peak voltage, another interval during which the active resistance is approximately zero to allow a large gate current, and yet another interval during which the active ...

Output buffer circuit of semiconductor integrated circuit

An output buffer circuit for a logical integrated circuit in which the peak value of switching noise is small thereby reducing the possibility of malfunctions. A main driver has first and second transistors. The first transistor increases and decreases the current flowing between a signal output terminal and a first power supply line inversely depending on a first control potential. The second transistor increases and decreases the current flowing between the signal output terminal and a second power supply line depending on a second control potential. A predriver turns on the first and second transistors at a low speed and turns them off at a high speed. As the first and second transistors are turned on at a low speed, the peak value of switching noise is small.

MINIMIZING RINGING IN WIDE BAND GAP SEMICONDUCTOR DEVICES

Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off.

Method and apparatus to minimize switching noise disturbance

A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the ...

CONTROL DEVICE FOR POWER SEMICONDUCTOR SWITCH

A control device for a power semiconductor switch, includes an actuating device, a first current path, a second current path, which connects the second output of the actuating device to a circuit node of the control device in an electrically conductive manner, wherein the second current path incorporates an electrical switching off resistor which is electrically connected in-circuit between a second output of the actuating device and the circuit node of the control device, a third current path, which connects the circuit node of the control device to a control device terminal of the control device in an electrically conductive manner, and an switching off acceleration circuit, which is electrically connected in parallel with the switching off resistor, comprising a diode, an electrical resistor, and a capacitor which is electrically connected in parallel with said resistor, wherein the cathode of the diode is connected to a second electrical terminal of the capacitor in an electrically ...

Low quiescent current load switch

Apparatus, devices, and systems to provide a low quiescent current load switch are disclosed. A disclosed load switch circuit includes a transconductor to convert a voltage to a current input to a transistor gate, the current input to the transistor gate to control the gate to deliver power to a load from a power supply. The example circuit includes a resistor to provide power from a charge pump to the gate as controlled by the transconductor. A disclosed apparatus includes a driver to control a gate of a transistor, the gate to enable the transistor to deliver power to a load from a power supply when the gate is activated, and a gate slope control to control a rate of change over time of a voltage associated with the gate to activate the gate and to disable the driver when the gate is activated.

CONTROLLER, CONTROL METHOD, AD CONVERTER, AND AD CONVERSION METHOD

The present technology relates to a controller, a control method, an AD converter, and an AD conversion method by which settling can be improved. The controller includes: a first current source that generates an output signal corresponding to an input signal; a second current source that supplies a current to charge a predetermined capacitance; and a control unit that controls the current supplied from the second current source to the predetermined capacitance, where the first current source and the second current source are each formed of a transistor. The controller further includes a supply unit that supplies a current flowing to the first current source and the second current source, where the current flowing to the first current source and the second current source is proportional to a current flowing in the supply unit. The present technology can be applied to an AD converter included in an imaging apparatus.

DRIVER AND SLEW-RATE-CONTROL CIRCUIT PROVIDING SOFT START AFTER RECOVERY FROM SHORT

A slew-rate-control (SLC) circuit is coupled to an input for a driver circuit to provide a first binary value when the circuit is powered on and to control a slew rate when a pass element controlled by the driver circuit is enabled. The SLC circuit includes a capacitor node for coupling to a first terminal of an external capacitor, the capacitor node being coupled to the input. The SLC circuit also includes a SLC element coupled between the input and a first source of voltage to define the slew rate and a reset FET coupled between the input and a second source of voltage. The reset FET's gate is controlled by an over-current-protection signal that changes binary value when a short is detected. The reset FET is coupled to return the input to the first binary value responsive to detection of a short ...

Solar module for generating a D.C. voltage and method for its operation

A solar module has a solar cell which generates a DC voltage. The module has a converter for converting a DC voltage fed into its input. The module contains a semiconductor switch and a controller which drives a switching input of the semiconductor switch. The controller drives the semiconductor switch variably so that the semiconductor switch switches more slowly during the transition operation than during normal operation, thereby reducing a dynamic overvoltage on the switch such that the voltage present on the switch does not exceed the blocking voltage of the switch.

REGULATOR DEVICE AND CONTROL METHOD THEREOF

A regulator device includes a first switch, a second switch, and a controlling circuit. A control terminal of the first switch is configured to receive a first control signal. A first terminal of the second switch is coupled with a second terminal of the first switch at a node. A control terminal of the second switch is configured to receive a second control signal. The controlling circuit is coupled to the control terminal of the first switch, the control terminal of the second switch, and the node. The controlling circuit outputs the first control signal with a first slop to the first switch during a first period, and outputs the first control signal with a second slop to the first switch during a second period. The first period is less than the second period, and the first slope is larger than the second slope.

SHORT-CIRCUIT PROTECTION METHOD

A short-circuit protection method for a circuit having a plurality of power switching elements, includes, when a short-circuit of a first power switching element is detected by detection device that detects a short-circuit of the plurality of power switching elements, performing a cut-off process of cutting off a gate of a second power switching element through which a short-circuit current caused by the short-circuit of the first power switching element flows, and changing a resistance value of a gate resistor of the second power switching element while the cut-off process is performed.

GATE DRIVING CIRCUIT

A gate driving circuit (10) adapted to drive a voltage-driven switching device (1) is provided with a current limiting circuit (6) for limiting a gate current (ig) that flows into a gate terminal through a gate resistor (3a) at turn-on to a current limit value (IL) which defines an upper limit value. The current limit value (IL) is set at a value which is larger than a gate current value (I2) at turn-on of the switching device (1) during a period when the Miller effect occurs but is smaller than a gate Current value (I1) at a point in time when a main current begins to flow at turn-on in a case where the gate current (ig) is not limited by the current limiting circuit (6). This arrangement makes a variation in a collector current of the switching device (1) moderate at turn-on thereof when the collector current begins to flow, thereby reducing high-frequency noise.

Circuit for controlling a power MOS transistor

GATE DRIVER WITH TEMPERATURE MONITORING FEATURES

A galvanically isolated gate driver for a power transistor is disclosed. The gate driver provides various temperature protection features that are enabled by (i) diagnostic circuitry to generate fault signals and monitoring signals, (ii) signal processing to enable communication over a shared communication channel across an isolation barrier, (iii) signal processing to reduce operating current needed for real-time thermal monitoring, and (iv) a disable circuit for unused temperature sensing pins.

半導体駆動装置

Semiconductor device driving unit with switchable gate impedance circuits

A drive circuit is disclosed for supplying a drive signal to the gate of a semiconductor switching device such as an IGBT or a MOSFET. The circuit comprises: a plurality of gate impedance circuits 40a, b, c and 42a, b, c selectably connectable to the gate of the semiconductor switching device 2, and a selector (e.g. a microprocessor 8, fig.1) to select one or more of the gate impedance circuits. The turn-on and turn-off times may be independently controlled. The micro-processor may control a number of gate impedance circuits for a plurality of devices 2. The associated method comprises selecting and connecting one or more of a plurality of gate circuits to the base of a switching device based on operating conditions and on stored data relating to the operating conditions. The components in the base drive circuit may thus be selected, in use, to provide or compensate for the cable length of an attached load, or to maintain relatively constant power loss in a switching device at different ...

SOLID STATE RELAY

DATA OUTPUT BUFFER CIRCUIT FOR BYTE-WIDE MEMORY

Method of controlling the slew rate of a mosfet and apparatus thereof

Method of controlling the slew rate of a mosfet and apparatus thereof

Solid state power control

Circuit and method for driving a semiconductor switching element

Um die Probleme mit steilflankigen Steuerspannungen von Halbleiterschaltelementen zu reduzieren ist vorgesehen, dass der Steueranschluss (6) des Halbleiterschaltelements (1) über eine Rampenerzeugungseinheit (5) mit dem Ausgangsanschluss (7) des Halbleiterschaltelements (1) verbunden ist und die Rampenerzeugungseinheit (5) zur Erzeugung einer Transistor-Steuerspannung (VG) am Ausgang der Rampenerzeugungseinheit (5) die steil steigenden und fallenden Flanken der Treiber-Steuerspannung (VS) rampenförmig abflacht.

ENERGY SAVING IN SERIAL DISTANCE TRANSMITTERS

SWITCHING CONFIGURATION FOR STARTING CURRENT DELIMITATION AND TO THE OVERVOLTAGE PROTECTION WITH CLOCKED POWER SUPPLY UNITS.

GLOBAL CLOSED LOOP CONTROL SYSTEM WITH DV/DT CONTROL AND EMI/SWITCHING LOSS REDUCTION

A VOLTAGE SOURCE CONVERTER AND A METHOD FOR CONTROL THEREOF

A VSC converter comprises in each valve one first semiconductor device (24) of turn-off type with a voltage blocking capacity rating of a first, high level and connected in parallel therewith a series connection of a plurality of second semiconductor devices (25-29) of turn-off type with a voltage blocking capacity rating of a second, lower level. A control arrangement (23) of the converter is configured to switch a said valve into a conducting state starting from a forward biased blocking state of the valve by controlling the second semiconductor devices to be turned on and then the first semiconductor devices to be turned on with a delay, and at the end of the conducting state to turn off the first semiconductor device in advance of turning the second semiconductor devices off.

METHOD AND APPARATUS FOR LIMITING CURRENT IN A DIRECT VOLTAGE NETWORK OF A POWER TRANSMISSION SYSTEM

Apparatus and method for limiting current in a direct voltage network of a HVDC power distribution system. A direct voltage network is connected to an alternating voltage network through a VSC-converter. At least one parallel connection including a semiconductor switching element is connected in series with the direct voltage network. A surge diverter is connected in parallel with the semiconductor switching element. During a high current condition in the direct voltage network, the switching element is switched off interrupting the current flow which is then diverted through the surge diverter which reduces the current flowing in the direct voltage network. By inserting a plurality of parallel connections, and selectively turning off a number of said semiconductor switching elements, a number of different levels of over current conditions in said direct voltage network may be controlled.

Gate potential control circuit

Gate driver

Method for forming the edges of signals and emitter/receiver module for a bus system

To used in the electric vehicle power supply system the capacitor in the discharge apparatus and method

DISPOSITIF DE COMMUTATION DE CIRCUITS A COURANT CONTINU PERMETTANT NOTAMMENT D'ASSURER UNE COMMUTATION CONFORMEMENT A UNE LOI LINEAIRE OU EXPONENTIELLE

L'INVENTION CONCERNE LA COMMUTATION DES CIRCUITS. LE DISPOSITIF DE COMMUTATION FAISANT L'OBJET DE L'INVENTION EST CARACTERISE EN CE QUE LE BLOC 11 DE COMMANDE DU TRANSISTOR 1 COMPORTE UN CONDENSATEUR 12 INSERE ENTRE L'ELECTRODE DE COMMANDE 8 ET L'UNE DES ELECTRODES D'ALIMENTATION 3 DU TRANSISTOR DE COMMUTATION, AINSI QUE DEUX GENERATEURS DE COURANT CONTINU 13, 14 RELIES PAR LEURS BORNES DE POLARITE OPPOSEE AUX ELEMENTS DE CONTACT FIXES DU COMMUTATEUR, LEURS AUTRES BORNES DE POLARITE OPPOSEE ETANT RACCORDEES A AU MOINS L'UNE DES ELECTRODES D'ALIMENTATION DU TRANSISTOR DE COMMUTATION. LE DISPOSITIF EN QUESTION PEUT ETRE UTILISE NOTAMMENT POUR LA COMMUTATION SANS CONTACT, SANS RUPTURE, DES CIRCUITS DES SYSTEMES ELECTRIQUES AUTONOMES POUR LA REPARTITION DE L'ENERGIE ELECTRIQUE ENTRE LES DIFFERENTS CONSOMMATEURS EQUIPANT PAR EXEMPLE LES AVIONS, LES HELICOPTERES, LES AUTOMOBILES, LES TRACTEURS ET AUTRES ENGINS.

Switching circuit with MOSFET - uses time-function signal to define resistance change during switching

Buffer stage for driving capacitive load, e.g. logic circuit, has CMOS output transistors driven by control voltages that are initially below and then equal to supply reference voltages

L''invention concerne un circuit tampon de sortie pour composant intégré, ou « buffer » en anglais, comprenant un étage de sortie comprenant un premier et un second transistor de sortie respectivement prévus pour alimenter une charge externe avec une première tension de référence (VCC) et une seconde tension de référence (VSS). Chacun desdits transistors de sortie est piloté par un signal de commande de sortie présentant au moins deux portions : - au moins une portion préliminaire pendant laquelle ledit premier, respectivement second, transistor de sortie est alimenté par une tension inférieure, en valeur absolue, à ladite première, respectivement seconde, tension de référence ; - une portion terminale pendant laquelle ledit premier, respectivement second, transistor de sortie est alimenté par une tension égale à ladite première, respectivement seconde, tension de référence.

DC circuit commutator unit - has contactless commutator to provide linear and exponential characteristic to minimise voltage variations on supply lines

Agencement de circuit comportant un transistor utilisé en commutateur.

LA PRESENTE INVENTION CONCERNE UN AGENCEMENT DE CIRCUIT COMPORTANT UN TRANSISTOR T UTILISE EN COMMUTATEUR, ET EN PARTICULIER UN TRANSISTOR A EFFET DE CHAMP MOS, QUI EST AMENE A PASSER AUX ETATS CONDUCTEUR ET NON CONDUCTEUR PAR UN SIGNAL DE COMMANDE APPLIQUE A UNE BORNE DE COMMANDE Q. L'AGENCEMENT EST CARACTERISE EN CE QU'UNE ENTREE SUPPLEMENTAIRE FE PERMET D'APPLIQUER UN SIGNAL VARIANT AVEC LE TEMPS F(T) QUI DETERMINE LA VARIATION DE RESISTANCE DU COMMUTATEUR T. L'AGENCEMENT DE CIRCUIT AINSI OBTENU PERMET D'OBTENIR UN CHANGEMENT D'ETAT DU COMMUTATEUR QUI N'EST PAS PERTURBE ET NE PROVOQUE PAS DES POINTES INDESIRABLES DANS LE CIRCUIT CONNECTE AU COMMUTATEUR.

게이트 전위 제어 회로

... 게이트 전위 제어 회로 (10a ; 10b) 는 구동용 스위칭 소자 (12), 제 1 게이트 전위 공급부 (60a), 제 1 스위칭 소자 (22), 제 1 저항 (24) 및 제 1 오피 앰프 (32a) 를 구비한다. 상기 제 1 오피 앰프는 상기 제 1 스위칭 소자의 게이트 (22c) 에 접속된 출력과, 제 1 참조 전위가 입력되는 반전 입력과, 상기 제 1 저항의 상기 제 1 게이트 전위 공급부측의 단자 (24a) 의 전위에서 상기 제 1 저항의 상기 구동용 스위칭 소자측의 단자 (24b) 의 전위를 감산한 전위차에 기초하는 제 1 값과 상기 제 1 스위칭 소자의 상기 구동용 스위칭 소자측의 단자 (22a) 의 전위에 기초하는 제 2 값 중, 상기 제 1 게이트 전위 공급부의 전위에 가까운 쪽의 값이 입력되는 비반전 입력을 구비한다.

CMOS 3-STATE BUFFER CIRCUIT AND ITS CONTROL MEANS

The circuit improves the reliability of CMOS-3 state buffer circuit by minimization of count EMF (Electro Motive Force), and reduces the saturation current. The circuit includes a drive circuit which serialy connects to a PMOS and NMOS output transistor, an inverter (I1) which controls the drive circuit, a NOR gate (N1), an inverter (I2), a 1st control circuit which connects to a PMOS gate, a 2nd control circuit which connects outout of an inverter (I3) to the gate of NMOS, a data input terminal which connects one terminal of a NOR gate (N1) and a NAND gate (N2), and an auxilliary drive circuit which supplies the vlotage to the grounding output transistor of the drive circuit. Copyright 1997 KIPO ...

SIGNAL OUTPUT DEVICE AND A TEST DEVICE, CAPABLE OF OUTPUTTING AN OUTPUT SIGNAL HAVING A HIGH VOLTAGE SWING

PURPOSE: A signal output device and a test device are provided to switch high voltage by using an electric field effect transistor such as a switching device of low prices. CONSTITUTION: A switching circuit(14) of high voltage stage opens or makes the gap of a first terminal connected to a reference voltage generating port and a second terminal connected to a second terminal a short circuit. A switching circuit(16) of high voltage stage opens or makes a first terminal connected to the output port and a second terminal a short circuit. If the switching circuit of the low voltage state is a short circuit, a controller(18) opens the switching circuit of the high voltage stage, and if the switching circuit of the high voltage state is a short circuit, a controller opens the switching circuit of the high voltage. COPYRIGHT KIPO 2010 ...

SYSTEM FOR FAULT PROTECTION IN AN IGBT, PARTICULARLY FOR SUPPRESSING A FAULT CURRENT AND PERFORMING THE SHUTDOWN FOR THE IGBT SAFELY

PURPOSE: A system for fault protection in an IGBT(Insulated Gate Bipolar Transistor) is provided to deal with a short circuit fault or a fault under load situation by analyzing a gate voltage pattern without using an emitter resistance, a high voltage diode, etc. CONSTITUTION: A system for fault protection in an IGBT comprises a gate voltage pattern analyzer, a gate voltage clamper and a soft off. The gate voltage pattern analyzer(510) judges a fault state by analyzing a gate voltage pattern of an IGBT(400). The gate voltage clamper(530) suspends the increase of gate voltage of the IGBT according to an output signal from the gate voltage pattern analyzer, if the output signal is fault. The soft off(550) turns off the IGBT slowly according to the output signal. © KIPO 2008 ...

CONTROL CIRCUIT AND CONTROL METHOD FOR TURNING ON POWER SEMICONDUCTOR SWITCH

A control circuit for turning on a power semiconductor switch includes: an input formed to receive a signal characterizing a switch-on behavior of the power semiconductor switch; and a variable current source formed to supply a current having a variable level by the control input of the power semiconductor switch in order to switch on the power semiconductor switch. The control circuit is formed to control the variable current source by a closed control loop in response to the signal characterizing the switch-on behavior of the power semiconductor switch. COPYRIGHT KIPO 2016 (302) State circuit (304) Peak timing detection circuit ...

Improved level-shift circuit utilizing a single level-shift switch

A level-shift circuit for use with a half bridge in accordance with an embodiment of the present application includes an oscillator operable to provide a timing signal, a level-shift switch controlled by the timing signal of the oscillator, a high side control circuit operable to provide a high side control signal to a high side switch of the half bridge to control the high side switch and a low side control circuit operable to provide a low side control signal to a low side switch of the half bridge to control the low side switch. The level-shift switch is turned ON when the timing signal is high such that the level-shift connects the high side control circuit to ground and the high side control signal stays low to keep the high side switch OFF when the timing signal is high. The low side control circuit provides the low side control signal to turn the low side switch ON a predetermined period of time after the timing signal goes high.

Low ground bounce output driver

An output driver with low ground bounce. The output driver receives a data signal and comprises a first transistor of a first type, having a drain connected to a pad, a source connected to receive a first power supply voltage and a gate, a capacitor with one end connected to receive the first power supply voltage and the other end connected to a charging/discharging node, a charging/discharging circuit generating a charging/discharging current output from the charging/discharging node when the data signal is at a first level, a first switch coupling the charging/discharging node to a second power supply voltage when the data signal is at a second level, and a second switch coupling the gate of the first transistor to the charging/discharging node when the data signal is at the first level and coupling the gate of the first transistor to receive the first power supply voltage when the data signal is at the second level.

HIGH VOLTAGE SWITCH WITH ADJUSTABLE CURRENT

The invention relates to a high voltage switch comprising a chain of MOSFET transistors, wherein the current of the individual MOSFETS and hence the chain can be controlled by means of adding a current measuring resistance into the source path of the transistors and transmitting the voltage arising there via a capacitor to the gate connector of the transistors.

METHOD FOR FORMING THE EDGES OF SIGNALS AND EMITTER/RECEIVER MODULE FOR A BUS SYSTEM

The invention relates to a method for forming the edges of signals, and to an emitter/receiver module for a bus system. Said emitter/receiver module (TR) for a bus system comprises a driver transistor (T1) which is looped in between a bus line (BL) of the bus system and a reference potential (GND) and is used for outputting signals (UBL) on the bus line (BL), a control unit (AE) for the driver transistor (T1), and a high-frequency interference detector (HFD) which is embodied in such a way that it determines a high-frequency interference level on the bus line (BL) of the bus system. The control unit (AE) is embodied in such a way that it controls the driver transistor (T1) according to the determined high-frequency interference level, such that an edge steepness of the outputted signals (UBL) increases when the high-frequency interference level on the bus line (BL) increases, and an edge steepness of the outputted signals (UBL) decreases when the high-frequency interference level on the ...

SLEW-RATE CONTROL APPARATUS AND METHODS FOR A POWER TRANSISTOR TO REDUCE VOLTAGE TRANSIENTS DURING INDUCTIVE FLYBACK

Apparatus and methods that reduce the amount of conducted/radiated emissions from a power switch (200) when a transistor (210) is switched OFF are disclosed. In addition, apparatus and methods that reduce the slew rate in a power switch when the power switch is switched off are disclosed. The apparatus comprises a transistor (210) including an inductive load (230) coupled to the transistor, a plurality of current sources (222, 224) coupled to the gate of the transistor, and a clamp (250) coupled to either the gate and the drain of the transistor, or to the gate and to ground depending on the location of the inductive load, wherein the clamp comprises a resistive element (260) to increase the voltage of the clamp when current flows through the clamp, and wherein the increased voltage causes the apparatus to include a different slew rate.

CIRCUIT HAVING A CONTROLLABLE SLEW RATE

A circuit for producing an output signal at an output thereof in response to an input signal at an input thereof is comprised, in one embodiment, of a first switch for connecting the output to a first voltage source and a second switch for connecting the output to a second voltage source. A first control switch is provided for turning off the first switch in response to the logic level of the input signal while a second control switch is provided for turning off the second switch in response to the logic level of the input signal. An integrator is responsive to the input signal for turning on one of the first and second switches depending on the logic level of the input signal. A method of operating such a circuit is also disclosed.

SOFT-SWITCHING CONVERTER AND FUEL CELL SYSTEM WITH SAME

A FC soft-switching converter (250) includes a free-wheel circuit (22c) that includes a free-wheel diode (D6). In a second series-connected body of an auxiliary circuit (22b), an anode of a diode (D2) is connected to the connecting portion of a snubber capacitor (C2) and a diode (D3) of a first series-connected body. Further, a cathode of the diode (D2) is connected to an electrode of a first end portion of a second switching element (S2). Also, an electrode of a second end portion of the second switching element (S2) is connected to a connecting portion of the free-wheel diode (D6) and a coil (L2).

RF COMMUNICATION SYSTEM USING AN RF DIGITAL AMPLIFIER

Band pass amplifiers and methods for driving the same are described. According to one embodiment, a frequency selective network (102) is provided in a feedback loop (112). An analog-to-digital converter (104) is coupled to the frequency selective network. A switching stage (108, 110) is coupled to the analog-to-digital converter for producing a continuous-time output signal. The switching stage includes at least one resonance circuit configured to resonate at a resonance frequency and thereby generate at least a portion of the continuous-time output signal. A continuous-time feedback path continuously senses and feeds back the continuous-time output signal to the frequency selective network.

Method and apparatus for driving capacitive element

When charging the capacitive element by driving opposed electrodes of an electrostatic capacitance of the capacitive element, the capacitive element is charged, with one of driving circuits set in a high impedance state, the one of the driving circuits varying a potential of one of the electrodes, and then the capacitive element is charged, with the one of the driving circuits set in a low impedance state. When discharging the capacitive element by driving the opposed electrodes of the electrostatic capacitance of the capacitive element, the capacitive element is discharged, with one of driving circuits set in the high impedance state, the one of the driving circuits varying a potential of one of the electrodes, and then the capacitive element is discharged, with the one of the driving circuits set in the low impedance state.

Driver circuit including amplifier operated in a switching mode

A driver circuit with an amplifier operated in a switching mode has threshold detectors with devices to compare the amplifier input and output voltage respectively to predetermined minimum and maximum levels representing fully off and fully on conditions for the driver circuit. The circuit provides signals to enable the amplifier to draw current from a supply only during transitions between the threshold levels and to otherwise disable the amplifier. The circuit is beneficial particularly when operating the amplifier from a voltage supply of very limited current capability, such as a charge pump voltage in an integrated circuit. The switching mode amplifier can be applied in high performance driver integrated circuits alone or in combination with innovative techniques for slew rate control and for preslewing the amplifier output that also provide high performance in compact circuit configurations.

CIRCUIT ARRANGEMENT AND METHOD FOR GENERATING A DRIVE SIGNAL FOR A TRANSISTOR

Disclosed is a circuit arrangement for generating a drive signal for a transistor. In one embodiment, the circuit arrangement includes a control circuit that receives a switching signal, a driver circuit that outputs a drive signal, and at least one transmission channel. The control circuit transmits, depending on the switching signal for each switching operation of the transistor, switching information and switching parameter information via the transmission channel to the driver circuit. The driver circuit generates the drive signal depending on the switching information and depending on the switching parameter information.

Global closed loop control system with DV/DT control and EMI/switching loss reduction

A motor drive system control provides global closed loop feedback to cooperatively operate system components to adaptively reduce noise and provide noise cancellation feedback. An active EMI filter reduces differential and common mode noise on an input and provides a noise level indication to a system controller. Power switches in both a power converter and power inverter are cooperatively controlled with dynamic dv/dt control to reduce switching noise according to a profile specified by the controller. The dv/dt control is provided as an analog signal to a high voltage IC and codified as a pulse width for a level shifting circuit supplying control signals to the high voltage gate drive. A noise extraction circuit and technique obtain fast noise sampling to permit noise cancellation and adaptive noise reduction.

High voltage switch with adjustable current

The present disclosure relates to a high voltage switch which may comprise a chain of MOS field-effect transistors (MOSFETs). The current of the individual MOSFETS, and hence the chain, can be controlled by means of adding a current measuring resistance into the source path of the transistors and transmitting the voltage arising there via a capacitor to a gate connector of the transistors.

Load control apparatus

A load control apparatus is provided in which a circuit of detecting an overcurrent can be correctly operated even if a first capacitor (C 1 ) for noise measures is disposed. Since a second capacitor (C 2 ) is provided between a gate and a drain of an FET (T 1 ), when the voltage (V 1 ) of a point (P 1 ) decreases, a part of the gate current of the FET (T 1 ) bypasses the FET (T 1 ) and flows to the capacitor (C 2 ), and the amount of charge supplied to the gate of the FET (T 1 ) decreases. Therefore, the increase of the drain current of the FET (T 1 ) can be suppressed and a sudden change of the voltage (V 1 ) can be prevented. As a result, the voltage (V 1 ) can be prevented from decreasing to such a degree that the comparator (CMP 1 ) cannot operate, and the comparator (CMP 1 ) can be prevented from malfunctioning.

Switch with improved edge rate control

This documents discusses, among other things, apparatus and methods for a switch circuit including a break-before-make delay and a gradual turn-on. In an example, a switch circuit can include a switch transistor having a control node and coupled to a first node and a second node, a delay circuit configured to receive control information and to provide the control information after a delay interval, and a gradual turn-on circuit configured to receive the delayed control information from the delay circuit and to transition the transistor from the off-state to the on-state over a ramp interval in response to the delayed control information.

Electric power conversion device and surge voltage suppressing method

To provide an electric power conversion device that converts direct current power supplied from a direct-current power supply into alternating current power, the electric power conversion device includes six switching elements constituted by a voltage-driven transistor that uses a wide bandgap semiconductor and a diode, and a drive circuit that controls a voltage for driving the transistor at a time of turning off the switching elements based on a predetermined voltage profile specifying that the transistor is operated in a non-linear region.

High speed low loss gate drive circuit

A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch.

External Power Transistor Control

The present document relates to the control of an external power transistor. In particular, the present document relates to a method and system for avoiding ringing at the external power transistor subsequent to switching of the external power transistor. A driver circuit to generate a drive signal for switching a driven switch between an off-state and an on-state is described. The driver circuit comprises a drive signal generation unit configured to generate a high drive signal triggering the driven switch to switch to the on-state; wherein an output resistance of the driver circuit is adjustable; an oscillation detection unit to detect a degree of oscillation on the drive signal; and a resistance control unit to adjust the output resistance of the driver circuit based on the degree of oscillation on the drive signal.

Device and method to discharge a capacitor for use in the electric power system of an electric drive vehicle

A discharge device and method actively discharge a main capacitor in an electric-power system, of an electric-drive vehicle. The discharge device comprises a discharge branch of a circuit that is connected in parallel to the main capacitor and includes a discharge transistor that is biased to “conduction” mode when, the main capacitor is required to be discharged. A control device is connected to a “gate/base” terminal, of the discharge transistor and commands the discharge transistor, biasing the discharge resistor to “conduction” mode when the main capacitor is required to be discharged. The control device includes a safety capacitor that is interposed between the “gate/base” terminal and a power supply and charges when the discharge transistor is in the “conduction” mode, causing a progressive decrease of current at the “gate/base” terminal until the discharge transistor is biased to the non-conductive state.

Driver for semiconductor switch element

Providing a driver for semiconductor switch element capable of securing a sufficient drive power and reliably turning off the semiconductor switch element. The driver includes a converter section 2 which includes a switching element Q 1 and which is configured to output a desired DC voltage by switching the switching element Q 1, a control section 1 configured to control the switching operation of the switching element Q 1, capacitors C 1 A, C 1 B charged by the output of the converter section 2, turn-on circuits 31 A, 31 B configured to supply gates of a bidirectional switch element 4 using electric charges stored in the capacitors C 1 A, C 1 B with drive powers to turn-on the bidirectional switch element 4, and turn-off circuits 32 A, 32 B configured to discharge the capacitors C 1 A, C 1 B to turn-off the bidirectional switch element 4 in response to the halt of the switching operation of the switching element Q 1 by the control section 1.

Low Current Start Up Including Power Switch

The present document relates to a start-up circuit comprising a power switch wherein a circuit charges a supply voltage capacitor. The capacitor provides a supply voltage to a power switch; the power switch forms a switched power converter with a power converter network. The circuit comprises a source and gate interface for coupling the circuit to the power switch; a capacitor interface couples the circuit to the supply voltage capacitor; a start-up path couples the gate interface to the capacitor interface; wherein the startup path provides a voltage at the gate interface which is at or above a threshold voltage of the power switch; and a charging path couples the source interface to the capacitor interface; wherein the charging path provides a charging current to the capacitor interface, when the power switch is in on-state. 1. An electronic circuit configured to charge a supply voltage capacitor , wherein the supply voltage capacitor is intended for providing a supply voltage to a gate of a source-controlled power switch; wherein the power switch forms a switched-mode power converter , in conjunction with a power converter network; and wherein the drain of the power switch is coupled to a mains voltage; wherein the circuit comprisesa gate interface and a source interface intended for coupling the circuit to the gate and a source of the power switch, respectively;a capacitor interface intended for coupling the circuit to the supply voltage capacitor;a start-up path arranged to couple the gate interface to the capacitor interface; wherein the start-up path is configured to apply a voltage at the gate interface, which is at or above a threshold voltage of the power switch; anda charging path arranged to couple the source interface to the capacitor interface; wherein the charging path is configured to provide a charging current to the capacitor interface, when the power switch is in on-state.2. The circuit of claim 1 , whereinwherein a drain and the gate of the power ...

Switched-mode power supply using variable bias current

There is provided a switched-mode power supply including: a PWM control unit generating a clock signal having pulse widths of the clock depending on a load to provide a path switching signal; a clock counter counting the clock signal to generate a control signal; a current source generating a current; a current mirroring circuit unit having a plurality of upper side current mirroring units respectively mirroring the current from the current source to create a current having a predetermined amplitude; a first current adjusting unit individually selecting a portion of the plurality of upper side current mirroring units according to the control signal; and a path switching circuit unit switched according to the path switching signal so as to select a charging path between the first current adjusting unit and a power switch or a discharging path between the power switch and the ground.

Semiconductor device

A semiconductor device according to an embodiment includes a normally off transistor having a first source, a first drain, a first gate connected to a common gate terminal, and a body diode, a normally on transistor having a second source connected to the first drain, a second drain, and a second gate, a capacitor provided between the common gate terminal and the second gate, a first diode having a first anode connected to between the capacitor and the second gate and a first cathode connected to the first source, and a second diode having a second anode connected to the first source and a second cathode connected to the second drain.

VARIABLE SOFT START

Example implementations relate to a variable soft start device. For example, in an implementation, the variable soft start device may set the capacitance of a variable capacitance circuit connected to a soft start pin of the electronic fuse. The variable soft start device may read a power-good signal from the electronic fuse and determine the capacitance to set according to the power-good signal. 1. A variable soft start device comprising:an input to receive a power-good signal from an electronic fuse;an interface to communicate with a variable capacitance circuit that is coupled to a soft start pin of the electronic fuse; and send a control signal over the interface to the variable capacitance circuit, the control signal to set a capacitance exhibited by the variable capacitance circuit to the soft start pin, and', 'determine the capacitance to set by the control signal according to the power-good signal received at the input., 'a controller connected to the input and connected to the interface, the controller to2. The variable soft start device of claim 1 , whereinthe controller is to send a control signal to set the capacitance to an initial value, and read the power-good signal received at the input from the electronic fuse,', 'if the power-good signal indicates that the electronic fuse is not outputting an expected power level, select the capacitance to set to be lower than a present capacitance exhibited by the variable capacitance circuit to the soft start pin if the initial value is a high value and select the capacitance to set to be higher than the present capacitance if the initial value is a low value, and', 'if the power-good signal indicates that the electronic fuse is outputting an expected power level, maintain the present capacitance., 'to determine the capacitance to set, the controller is to3. The variable soft start device of claim 1 , wherein the variable capacitance circuit is integrated with the variable soft start device.4. The variable soft ...

ADAPTIVE GATE DRIVER

A device driver is described that includes an output stage and one or more control components. The output stage is configured to produce a gate driver output for driving a gate terminal of a semiconductor device, the output stage comprising a variable driving capability. The one or more control components are configured to obtain an indication of a rise time of the gate driver output during an initial switching cycle of the semiconductor device, and prior to a subsequent switching cycle of the semiconductor device, adjust, based on the indication of the rise time, a driving capability of the device driver from a first level to a second level. The one or more control components are further configured to cause the output stage to output the gate driver output at the second level of driving capability during the subsequent switching cycle of the semiconductor device. 1. A device driver comprising:an output stage configured to produce a gate driver output for driving a gate terminal of a semiconductor device, wherein the semiconductor device comprises a power metal-oxide-semiconductor field-effect-transistor device of a switched-mode power supply; and at power-on of the device driver and during an initial switching cycle of the semiconductor device, cause the output stage to produce the gate driver output at a maximum driving capability of the device driver;', 'obtain an indication of a rise time of the gate driver output during the initial switching cycle by evaluating a voltage level at a capacitor of the output stage after charging the capacitor with a fixed current source of the output stage from a start time until an end time at which the gate driver output is at the maximum driving capability of the device driver;', 'cause the charging the capacitor with the fixed current source to cease at the end time at which the gate driver output is at the maximum driving capability of the device driver;', 'prior to a subsequent switching cycle of the semiconductor device, ...

Semiconductor device and electronic control device

The power transistor QN1 is provided between the positive power supply terminal Pi2(+) and the load-driving terminal Po2(+), and has a source and a back-gate coupled to the positive power supply terminal Pi2(+). The power transistor QN2 is provided in series with the power transistor QN1, and its sources and backgates are coupled to the load-driving terminal Po2(+). The booster CP1a charges the gates of the power transistors QN1. The gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source when the potential of the negative power supply terminal Pi2(−) is higher than the potential of the positive power supply terminal Pi2(+).

Anti-ringing technique for switching power stage

A driver may provide a transition of a switch between an on state and an off state in two stages. In the first stage, the voltage slew rate of the voltage at an output terminal of the switch may be controlled. In the second stage, the current gradient of the switch may be controlled. The transition between the first stage and the second stage may be made based on the value of the voltage at the output terminal of the switch.

MULTI-STAGE GATE TURN-OFF WITH DYNAMIC TIMING

A turn-off circuit for a semiconductor switch includes an element having a variable resistance coupled to a control input of the semiconductor switch, a circuit for generating a control-input reference signal, and a control circuit coupled to adjust a resistance of the element having a variable resistance in response to the control-input reference signal in a closed control loop in order to turn off the semiconductor switch. 1. A turn-off circuit for a semiconductor switch , wherein the turn-off circuit comprises:an element having a variable resistance, said element being coupled to a control input of the semiconductor switch;a circuit for generating a control-input reference signal; anda control circuit coupled to adjust a resistance of the element having a variable resistance in response to the control-input reference signal in a closed control loop in order to turn off the semiconductor switch.2. The turn-off circuit as claimed in claim 1 , wherein the element having a variable resistance is a semiconductor switch.3. The turn-off circuit as claimed in claim 2 , wherein the element having a variable resistance is a MOSFET semiconductor switch.4. The turn-off circuit as claimed in claim 1 , wherein the variable resistance of the element having the variable resistance is formed between a drain claim 1 , anode or collector terminal and a source claim 1 , cathode or emitter terminal of the semiconductor switch.5. The turn-off circuit as claimed in claim 1 , wherein the element having the variable resistance is coupled in series with a further resistance between the control input of the semiconductor switch and a reference potential.6. The turn-off circuit as claimed in claim 1 , wherein the control-input reference signal has a first drop at a first rate claim 1 , a region with a substantially constant signal level claim 1 , and a second drop at a second rate.7. The turn-off circuit as claimed in claim 6 , wherein the second rate is higher than the first rate.8. The ...

CURRENT DETECTING CIRCUIT AND SWITCHING CIRCUIT

A current detecting circuit includes a first switching element, a second switching element, and a third switching element electrically coupled in series with the first switching element. An output side of the third switching element is electrically coupled to an output terminal. The current detecting circuit includes a current amplifier configured to detect a difference between a first output voltage of the first switching element and a second output voltage of the second switching element. The current amplifier outputs a relative current to be used for detecting an output current that flows out from the output terminal. A ratio of resistance associated with the first switching element to resistance associated with the second switching element is n:1. 1. A current detecting circuit comprising:a power supply terminal;an output terminal;a first switching circuit of which an input side is electrically coupled to the power supply terminal, the first switching circuit including a first control terminal;a second switching circuit of which an input side is electrically coupled to the power supply terminal, the second switching circuit including a second control terminal electrically coupled to the first control terminal of the first switching circuit;a third switching circuit electrically coupled in series with the first switching circuit, an output side of the third switching circuit being electrically coupled to the output terminal; anda current amplifier configured to detect a difference between a first output voltage of the first switching circuit and a second output voltage of the second switching circuit, and to output a relative current to be used for detecting an output current that flows out from the output terminal,wherein a ratio of resistance associated with the first switching circuit to resistance associated with the second switching circuit is n:1, where n is an integer greater than one.2. The current detecting circuit according to claim 1 , further ...

INVERTER DEVICE

An inverter device that includes an inverter circuit that converts power between DC power and multi-phase AC power; a drive circuit that transfers a drive signal to each of a plurality of switching elements that form the inverter circuit to cause a switching element of the plurality of switching elements to perform turn-on, in which the switching element is caused to transition from an off state to an on state, and turn-off, in which the switching element is caused to transition from the on state to the off state; and a current detection circuit that detects a current that flows through each of the plurality of switching elements. 1. An inverter device comprising:an inverter circuit that converts power between DC power and multi-phase AC power;a drive circuit that transfers a drive signal to each of a plurality of switching elements that form the inverter circuit to cause a switching element of the plurality of switching elements to perform turn-on, in which the switching element is caused to transition from an off state to an on state, and turn-off, in which the switching element is caused to transition from the on state to the off state; anda current detection circuit that detects a current that flows through each of the plurality of switching elements, wherein:the drive circuit includes a soft turn-off circuit that causes the switching element to perform the turn-off by transferring the drive signal via a delay resistor in the case where the current which is detected by the current detection circuit is equal to or more than an overcurrent threshold prescribed in advance; andthe soft turn-off circuit includes a capacitor connected in parallel with the delay resistor.2. The inverter device according to claim 1 , wherein {'br': None, 'i': Cs', 'Qg/, '≤(2)/Vge.'}, 'when a charge amount of a control terminal at the time of the turn-on of the switching element is defined as Qg, a control terminal voltage to be applied to the control terminal at the time of the turn-on ...

Cascode compound switch slew rate control

A high-voltage (HV) compound switch can include coupling circuitry to help provide better slew rate (dV/dt) control, such as to limit electromagnetic energy radiation during switching, which can cause undesirable EMI. Further, efficiency and on-state resistance can be improved by controllably forward-biasing the “normally on” JFET when the compound switch is in an “on” state. In such an on-state, the JFET temperature can be monitored, such as by monitoring the gate-source junction voltage or the gate current of the JFET. Such temperature information can be used for control or other purposes.

VOLTAGE REGULATOR

The voltage regulator includes a reference voltage circuit configured to feed back the reference voltage as a feedback voltage and to output the reference voltage, a soft-start circuit configured to output a control signal for controlling the reference voltage to rise linearly at a start of power supply, a voltage divider circuit configured to output a divided voltage, an error amplifier circuit configured to amplify and output a difference between the reference voltage and the divided voltage, and an output transistor controlled by an output voltage of the error amplifier circuit. The reference voltage circuit includes an analog switch transistor having a gate controlled by the control signal, and the feedback voltage is an output voltage from the analog switch transistor. 1. A voltage regulator , comprising:a power supply terminal to which an external power voltage is supplied;an output terminal configured to output a voltage generated by adjusting the external power voltage;a reference voltage circuit configured to feed back a reference voltage as a feedback voltage and to output the reference voltage;a soft-start circuit configured to output a control signal for controlling the reference voltage to rise linearly at a start of power supply;a voltage divider circuit configured to divide a voltage of the output terminal to generate a divided voltage;an error amplifier circuit configured to amplify and output a difference between the reference voltage and the divided voltage; andan output transistor having a gate controlled by an output voltage of the error amplifier circuit, and a drain connected to the output terminal,the reference voltage circuit comprising an analog switch transistor having a gate controlled by the control signal,the feedback voltage being an output voltage of the analog switch transistor.2. A voltage regulator according to claim 1 , a first NMOS transistor having a drain terminal connected to the power supply terminal via a first constant ...

Molded power module having single in-line leads

A power module has a lead frame, a first power chip, a second power chip, a plurality of single in-line leads, a gate drive and protection integrated circuit (IC), a plurality of bonding wires and a molding encapsulation. The first and second power chips are attached to a top surface of the lead frame. The plurality of single in-line leads has a high voltage power lead, a low voltage power lead and a plurality of signal control leads. The low voltage power lead has a lead portion and an extension portion. The gate drive and protection IC is attached to the extension portion of the low voltage power lead. The molding encapsulation encloses the first and second power chips, the extension portion of the low voltage power lead, the gate drive and protection IC, the plurality of bonding wires and at least a majority portion of the lead frame.

Electronic Drive Circuit

An electronic circuit includes a first input pin configured to receive a first input signal that includes an enable information and at least one operation parameter information, a second input pin configured to receive a second input signal, an output pin, a control circuit configured to generate a drive signal based on the first input signal and the second input signal, an output circuit configured to generate an output signal at the output pin, the enable information includes an enabled state and a disabled state, the control circuit is configured to generate the drive signal in the enabled state and to turn to the electronic circuit off in the disabled state, the at least one operation parameter information includes information about an operational parameter of the output signal, and the output circuit is configured to use the at least one operation parameter information to change the operational parameter of the output signal.

Gate driver with integrated miller clamp

A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.

Circuit arrangement for switching switch elements

The invention relates to a circuit arrangement ( 100 ), comprising a control circuit ( 104 ) and a switch element ( 101 ) for switching between a first and a second switching state of the switch element ( 101 ). The control circuit ( 104 ) is designed to provide a variable pre-control voltage dependent on the switching state of the switch element. The pre-control voltage is a voltage that is switched as the control voltage at the switch element ( 101 ) during one of the two switching states. The control circuit ( 104 ) is also designed to vary the pre-control voltage during each of the switching states.

Switch Driver

The present disclosure relates to an apparatus and method for driving a switch, such as a power switch. A driver comprises a voltage sensor to sense a drive voltage, and an electrical source to provide a drive signal having a drive value. The driver is adapted to adjust the drive value based on the drive voltage to limit a switch-current flowing through the switch.

METHOD AND SYSTEM FOR INCREASING EFFICIENCY AND CONTROLLING SLEW RATE IN DC-DC CONVERTERS

One embodiment pertains to a method including transitioning a logic state of at least one enable signal. A first power transistor begins to turn off. A parameter level of the input of the first power transistor is directly sensed. A second power transistor is turned off when the parameter level is less than a threshold level. 1. An apparatus , comprising:first and second power transistors;a driver for generating gate control signals for the first and second power transistors;slew resistors coupled to gates of the first and second power transistors for adjusting slew rates of rising and falling edges of the gate control signals for the first and second power transistors, respectively; anddead time control circuitry that is configured to turn on one of the first and second power transistors only when the other of the first and second power transistors is turned off.2. The apparatus of claim 1 , wherein the dead time control circuitry is configured to directly sense gate voltages of the first and second power transistors.3. The apparatus of claim 1 , wherein at least one of the first and second power transistors is a MOSFET.3. The apparatus of claim 1 , further comprising programmable dead time circuitry coupled to the driver.4. The apparatus of claim 3 , wherein the programmable dead time circuitry is configured to be coupled to a resistor whose value established a programmed dead time.5. The apparatus of claim 1 , further comprising a PWM controller coupled to the driver claim 1 , wherein the driver is configured to generate the gate control signals in response to a PWM signal from the PWM controller.6. The apparatus of claim 1 , wherein the first and second power transistors are connected together at a node claim 1 , the apparatus further comprising a bootstrap capacitor connected between the node and a supply voltage.7. The apparatus of claim 1 , wherein the driver is configured to generate first and second enable signals for the first and second power transistors ...

MULTIPLE STAGE GATE DRIVE FOR CASCODE CURRENT SENSING

A power converter includes an energy transfer element coupled between an input of the power converter and an output of the power converter. A control switch is coupled to a normally-on switch. The normally-on switch is coupled to the energy transfer element. A controller is coupled to control switching of the control switch to control a transfer of energy from the input of the power converter to the output of the power converter. The controller includes a drive circuit coupled to generate a drive signal in response to a control signal to control switching of the control switch. The drive signal in a first stage of a multiple stage gate drive is coupled not to fully enhance the control switch. The drive signal provided by a second stage of the multiple stage gate drive is coupled to fully enhance the control switch. 1. A power converter , comprising;an energy transfer element coupled between an input of the power converter and an output of the power converter;a control switch coupled to a normally-on switch, wherein the normally-on switch is coupled to the energy transfer element; and 'a drive circuit coupled to generate a drive signal in response to a control signal to control switching of the control switch, wherein the drive signal in a first stage of a multiple stage gate drive is coupled not to fully enhance the control switch, and wherein the drive signal provided by a second stage of the multiple stage gate drive is coupled to fully enhance the control switch.', 'a controller coupled to control switching of the control switch to control a transfer of energy from the input of the power converter to the output of the power converter, wherein the controller includes2. The power converter of claim 1 , wherein the control switch comprises one or more fingers coupled to the control switch claim 1 , wherein the one or more fingers has a general ratio of resistance to a resistance of the normally-on switch.3. The power converter of claim 2 , wherein the controller ...

GATE DRIVER CIRCUIT

A gate driver circuit may include a driving signal generating unit generating first and second control signals based on a data signal and a fault state signal and controlling gate detection, a driving inverter operating in response to the first and second control signals to generate a gate signal and providing the gate signal to a power switch element, and a soft turn-off/gate detecting unit operating in response to the second control signal, performing a soft turn-off in the case of a fault, and detecting the gate signal to provide a detected signal. 1. A gate driver circuit , comprising:a driving signal generating unit configured to generate first and second control signals based on a data signal and a fault state signal and control gate detection;a driving inverter configured to operate in response to the first and second control signals to generate a gate signal and provide the gate signal to a power switch element; anda soft turn-off/gate detecting unit configured to operate in response to the second control signal, perform a soft turn-off in the case of a fault, and detect the gate signal to provide a detected signal.2. The gate driver circuit of claim 1 , wherein the driving signal generating unit generates the first control signal using the data signal and the fault state signal and generates the second control signal using the first control signal and the fault state signal.3. The gate driver circuit of claim 1 , wherein the driving signal generating unit includes:a first inverter inverting the data signal;a second inverter inverting the fault state signal;an AND gate performing an AND operation on an output signal of the first inverter and an output signal of the second inverter to provide the first control signal;a first buffer providing the first control signal to the driving inverter;an OR gate performing an OR operation on the first control signal and the fault state signal to provide the second control signal; anda second buffer providing the second ...

POWER SEMICONDUCTOR DRIVE CIRCUIT, POWER SEMICONDUCTOR CIRCUIT, AND POWER MODULE CIRCUIT DEVICE

A power semiconductor drive circuit includes a parallel circuit connected to a gate of a power semiconductor element and constituted by two transistors for setting gate resistance of the power semiconductor element; a gate voltage monitoring circuit connected to the gate of the power semiconductor element and the parallel circuit, wherein a monitoring voltage is set in the gate voltage monitoring circuit to monitor a gate voltage of the power semiconductor element; a signal delay circuit to delay an output signal of the gate voltage monitoring circuit; and a gate control circuit to change the magnitude of combined resistance of the parallel circuit based on an output signal output from the signal delay circuit. 1. A power semiconductor drive circuit for driving an upper power semiconductor element and a lower power semiconductor element coupled in series between a power supply terminal and a ground electric potential , the circuit comprising:a parallel circuit having a first end which is directly connected to a gate of the upper power semiconductor element and a second end which is connected to a connection point between the upper power semiconductor element and the lower power semiconductor element and constituted by at least two transistors for setting gate resistance of the upper power semiconductor element;a gate voltage monitoring circuit directly connected to the gate of the upper power semiconductor element and the parallel circuit, wherein a predetermined monitoring voltage is set in the gate voltage monitoring circuit in order to monitor a gate voltage of the upper power semiconductor element; anda gate control circuit to change a magnitude of combined resistance of the parallel circuit based on an output signal of the gate voltage monitoring circuit.2. The power semiconductor drive circuit of claim 1 , further comprising a signal delay circuit to delay the output signal of the gate voltage monitoring circuit claim 1 ,wherein the gate control circuit ...

LOAD SWITCH CIRCUIT AND CONTROL METHOD

The present application provides a load switch circuit including a power transistor, the first terminal is configured to receive the power supply voltage, and the second terminal is the output terminal of the load switch circuit and is coupled with an external inductive load; a clamping module including at least a mutually coupled clamping unit and a driving unit; the clamping unit, including a voltage-current converter and a first resistor, the first resistor is coupled between the output terminal of the voltage-current converter and the second terminal of the power transistor, the positive input terminal of the voltage-current converter receives the power supply voltage, and the negative input terminal is coupled to the second terminal of the power transistor; the current output by the voltage-current converter generates a reference voltage drop on the first resistor; the output terminal of the drive unit is coupled to the control terminal of the power transistor when the difference between the power supply voltage and the output voltage of the power transistor is greater than or equal to the preset clamping threshold, the clamping unit outputs an effective drive control signal to the driving unit; the preset clamping threshold is sum of the reference voltage drop and the threshold of the first transistor. 1. A control method of a switch circuit , including:generating a reference current through a voltage-current converter, the voltage-current converter having an equivalent resistance;generating a clamping threshold based on at least a reference voltage generated by the reference current on a reference resistor; andin response to a difference between a power supply voltage and an output voltage at an output node of the switching circuit is greater than or equal to the clamping threshold, turning on a power transistor that provides the output voltage.2. The method of claim 1 , further comprising:in response to the output voltage of the switch circuit is lower than ...

Driving Variable Capacitive Loads

Circuitry for driving a variable capacitive load comprising: a variable capacitive load; a digital control circuit configured to generate a digital drive signal; and a drive circuit configured to convert the digital drive signal into an analogue drive signal, the analogue drive signal forming a drive waveform for charging the variable capacitive load, the drive circuit comprising a slewing circuit configured to drive a time dependent voltage component of the drive waveform; wherein the digital control circuit is configured to modify the digital drive signal for each charging cycle so as to match the time dependent voltage component of the drive waveform to the variable capacitive load. 1. Circuitry for driving a variable capacitive load , the circuitry comprising:the variable capacitive load;a digital control circuit configured to generate a digital drive signal; anda drive circuit configured to convert the digital drive signal into an analogue drive signal, the analogue drive signal forming a drive waveform for charging the variable capacitive load, the drive circuit comprising a slewing circuit configured to drive a time dependent voltage component of the drive waveform;wherein the digital control circuit is configured to modify the digital drive signal for each charging cycle so as to match the time dependent voltage component of the drive waveform to the variable capacitive load.2. The circuitry as claimed in claim 1 , wherein the digital control circuit is configured to modify the digital drive signal so as to cause the time dependent voltage component of the drive waveform to maintain a constant slew rate during charging of the variable capacitive load.3. The circuitry as claimed in claim 1 , wherein the analogue drive signal further forms a drive waveform for discharging the variable capacitive load claim 1 , and wherein the digital control circuit is configured to modify the digital drive signal so as to cause the time dependent voltage component of the ...

DRIVE CIRCUIT FOR SWITCHING ELEMENT

A drive circuit for a switching element according to the present embodiment includes a drive-voltage generation circuit that generates a driving voltage for a switching element; and a filter circuit that filters the driving voltage. The filter circuit forms a circuit having a step response represented by a second-order transfer function together with an internal gate resistor and an input capacitor between a gate terminal and an emitter terminal of the switching element. The circuit has a circuit constant that is set to make an attenuation coefficient of the transfer function be a value within a certain range. 1. A drive circuit for a switching element , the drive circuit comprising:a drive-voltage generation circuit that generates a driving voltage for a switching element; anda filter circuit that forms a circuit having a step response represented by an nth-order lag transfer function (n is larger than 1) together with an internal gate resistor and an input capacitor between a gate terminal and an emitter terminal of the switching element, whereinthe switching element has wide-bandgap characteristics2. The drive circuit for a switching element according to claim 1 , whereinan attenuation coefficient of the nth-order lag transfer function is not less than 0.7 and not more than 1.0.3. The drive circuit for a switching element according to claim 1 , wherein reduces a peak value of a gate current of the switching element and', 'increases a gate current value in a miller period when compared to a circuit having a step response represented by a first-order lag transfer function., 'the circuit having the step response represented by the nth-order lag transfer function (n is larger than 1)'} The present invention relates to a drive circuit for a switching element that executes drive control targeted at a switching element. The type of switching element can include an IGBT (Insulated Gate Bipolar Transistor) and a FET (Field Effect Transistor).In recent years, motor ...

POWER UNIT WITH AN INTEGRATED PULL-DOWN TRANSISTOR

One example relates to a circuit that includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die has a power field effect transistor (FET) and a pull-down FET coupled to the power FET. The second integrated circuit die has a pull-up FET coupled to the power FET. 1. A circuit , comprising: a power field effect transistor (FET); and', 'a pull-down FET coupled to the power FET; and, 'a first integrated circuit die includinga second integrated circuit die having a pull-up FET coupled to the power FET.2. The circuit of claim 1 , wherein the second integrated circuit die includes a second pull-down FET coupled to the power FET.3. The circuit of claim 1 , wherein the second integrated circuit die further including control circuitry that receives a control signal and outputs first and second activation voltages to activate the pull-up FET and the pull-down FET claim 1 , respectively.4. The circuit of claim 1 , wherein the power FET is a low-side power FET claim 1 , the pull-down FET is a low-side pull-down FET claim 1 , and the power die is a low-side power die claim 1 ,the first integrated circuit die further including a high-side power FET and a high-side pull-down FET; andthe second integrated circuit die further including a high-side pull-up FET coupled to drive the high-side power FET and a low-side pull-up FET coupled to drive the low-side power FET.5. The circuit of claim 4 , further comprising bond wires that couple the high-side pull-up FET and the low-side pull-up FET to the high-side power FET and the low-side power FET claim 4 , respectively.6. The circuit of claim 1 , further comprising an integrated circuit package comprising the first and second integrated circuit dies.7. The circuit of claim 4 , wherein a gate of the high-side power FET is coupled to a drain of the high-side pull-down FET.8. The circuit of claim 7 , wherein the drain of the high-side pull-down FET is coupled to a source of a high-side pull- ...

METHOD AND APPARATUS TO MINIMIZE SWITCHING NOISE DISTURBANCE

A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration. After the initial duration, the current mirror is disabled and the first transistor is rendered fully conductive. 1. An integrated circuit comprising:a main reference voltage circuit operative to generate a main reference voltage;one or more voltage reference circuits, each configured to receive the main reference voltage and operative to output a reference voltage in an enabled state; a voltage setting circuit operative to generate the reference voltage from the main reference voltage in the enabled state;', 'a first current limiting transistor;', 'a second current limiting transistor;', 'a control circuit operative to enable the voltage reference circuit to switch to the enabled state via an intermediate state,', 'wherein, in the intermediate state, the first current limiting transistor and the second current limiting transistor are connected in a current mirror configuration; and', 'wherein, in the ...

MULTIPLE STAGE GATE DRIVE FOR CASCODE CURRENT SENSING

A power converter comprising an energy transfer element is coupled between an input of the power converter and an output of the power converter. A cascode circuit generates a first sense signal and a second sense signal. A controller controls the switching of the cascode circuit to transfer energy from the input of the power converter to the output of the power converter. The controller comprising a current sense circuit generates a current limit signal and an overcurrent signal in response to the first sense signal and the second sense signal. A control circuit generates a control signal in response to the current limit signal and the overcurrent signal. A drive circuit comprising a first stage gate drive circuit generates a drive signal in response to the control signal to reduce EMI, and a second stage of gate drive circuit to enable accurate current sensing of the cascode circuit. 119-. (canceled)20. A power converter , comprising:an energy transfer element coupled between an input of the power converter and an output of the power converter;a cascode circuit coupled to the energy transfer element, the cascode circuit including a normally-on GaN switch and a control switch, the control switch configured to generate a first sense signal and a second sense signal;a current sensor configured to generate a current limit signal and an overcurrent signal in response to the first sense signal and the second sense signal;a control circuit configured to generate a control signal in response to the current limit signal and the overcurrent signal; anda drive circuit configured to generate a drive signal in response to the control signal, wherein a first stage of the drive circuit is configured to provide the drive signal to reduce EMI, and a second stage of the drive circuit is configured to provide the drive signal to enable accurate current sensing by the cascode circuit.21. The power converter of claim 20 , wherein the first sense signal is generated by a drain of a ...

Gate Driver Controlling a Collector to Emitter Voltage Variation of an electronic Switch and Circuits Including the Gate Driver

The present disclosure introduces a gate driver used to drive a power electronic switch of a commutation cell. The gate driver comprises a turn-off current source connected to a gate of the power electronic switch and an additional current source. The additional current source is in parallel to the turn-off current source of the gate driver and is configured to control a collector to emitter voltage variation at turn off of the power electronic switch. A circuit combining the gate driver with a commutation cell having a power electronic switch, a circuit combining a pair of gate drivers with a leg having two commutation cells including two power electronic switches and a converter including such circuits are also disclosed. 1. A gate driver for driving a power electronic switch of a commutation cell , comprising:a turn-off current source connected to a gate of the power electronic switch; andan additional current source in parallel to the turn-off current source and configured to control a variation of a collector to emitter voltage of the power electronic switch at turn off of the power electronic switch.2. The gate driver of claim 1 , wherein the additional current source is configured to limit a rate of variation of a voltage at the gate of the power electronic switch.3. The gate driver of claim 1 , wherein the additional current source is configured to maintain a gate to emitter voltage of the power electronic switch in a linear region at turn off of the power electronic switch.4. The gate driver of claim 1 , wherein the additional current source comprises an external capacitor connected between the collector and the gate of the power electronic switch.5. The gate driver of claim 4 , wherein the external capacitor is connected in parallel to a parasitic capacitance between the collector and the gate of the power electronic switch.7. The gate driver of claim 5 , wherein a value of the external capacitor is in an order of magnitude of a minimum value of the ...

Drive device for power converter and driving method of power converter

A drive device driving a power converter that includes a switching element formed from a wide bandgap semiconductor, includes a PWM-signal output unit that generates a drive signal that drives the switching element with PWM; an on-speed reducing unit that, when the switching element is changed from off to on, reduces a change rate of the drive signal; and an off-speed improving unit that, when the switching element is changed from on to off, draws charge from the switching element at a high speed and with a charge drawing performance higher than that at a time when the switching element is changed from off to on.

Gate drivers for circuits based on semiconductor devices

An electronic component includes a switching device comprising a source, a gate, and a drain, the switching device having a predetermined device switching rate. The electronic component further includes a gate driver electrically connected to the gate and coupled between the source and the gate of the switching device, the gate driver configured to switch a gate voltage of the switching device at a gate driver switching rate. The gate driver is configured such that in operation, an output current of the gate driver cannot exceed a first current level, wherein the first current level is sufficiently small to provide a switching rate of the switching device in operation to be less than the predetermined device switching rate.

Double Gate Transistor Device and Method of Operating

In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region. 1. A method comprising:switching off a transistor device by interrupting a first conducting channel in a body region by driving a first gate electrode and, after interrupting the first conducting channel, interrupting a second conducting channel in the body region by driving a second gate electrode,wherein the first gate electrode is dielectrically insulated from the body region by a first gate dielectric,wherein the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer, andwherein the body region is arranged between a source region and a drift region, andwherein the drift region is arranged between body region and a drain region.2. The method of claim 1 ,wherein driving the first gate electrode comprises decreasing a first drive voltage between the first gate electrode and the source region from a first on-level to a first off-level, andwherein driving the second gate electrode comprises increasing a second drive voltage between the second gate electrode and the source region from a second on-level to a second off-level.3. The ...

SEMICONDUCTOR DEVICE DRIVING CIRCUIT

A semiconductor device driving circuit includes: a signal transmission circuit including a first level shift circuit, the signal transmission circuit and an unsaturated voltage detection circuit configured to output a first error signal when an unsaturated voltage of a semiconductor switching element driven by the drive signal is detected. The semiconductor device driving circuit generates a second error signal having the second voltage level by level-shifting the first error signal or a converted signal obtained by converting the first error signal into a pulse signal. The semiconductor device driving circuit further includes a soft shutdown circuit configured to change a drive signal for the semiconductor switching element to softly shut down the semiconductor switching element when the second error signal is input. 1. A semiconductor device driving circuit comprising:a signal transmission circuit including a first level shift circuit configured to level-shift an input signal having a first voltage level, the signal transmission circuit being configured to generate a drive signal having a second voltage level higher than the first voltage level based on the input signal; andan unsaturated voltage detection circuit configured to output a first error signal having the first voltage level when an unsaturated voltage of a semiconductor switching element driven by the drive signal is detected,wherein a second error signal having the second voltage level is generated by level-shifting the first error signal, or by a signal obtained by level-shifting a converted signal converted into a pulse signal from the first error signal, andwherein the semiconductor device driving circuit further comprises a soft shutdown circuit configured to change a drive signal for the semiconductor switching element to softly shut down the semiconductor switching element when the second error signal is input.2. The semiconductor device driving circuit according to claim 1 , comprising a second ...

Analog signal soft switching control with precise current steering generator

A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

MULTIPLE STAGE GATE DRIVE FOR CASCODE CURRENT SENSING

A power converter comprising an energy transfer element is coupled between an input of the power converter and an output of the power converter. A cascode circuit generates a first sense signal and a second sense signal. A controller controls the switching of the cascode circuit to transfer energy from the input of the power converter to the output of the power converter. The controller comprising a current sense circuit generates a current limit signal and an overcurrent signal in response to the first sense signal and the second sense signal. A control circuit generates a control signal in response to the current limit signal and the overcurrent signal. A drive circuit comprising a first stage gate drive circuit generates a drive signal in response to the control signal to reduce EMI, and a second stage of gate drive circuit to enable accurate current sensing of the cascode circuit. 1. A power converter , comprising:an energy transfer element coupled between an input of the power converter and an output of the power converter;a cascode circuit coupled to the energy transfer element, the cascode circuit further configured to generate a first sense signal and a second sense signal; and a current sense circuit configured to generate a current limit signal and an overcurrent signal in response to the first sense signal and the second sense signal;', 'a control circuit configured to generate a control signal in response to the current limit signal and the overcurrent signal; and', 'a drive circuit comprising a multiple stage gate drive circuit configured to generate a drive signal in response to the control signal, wherein a first stage of the multiple stage gate drive circuit is configured to provide the drive signal to reduce EMI, and a second stage of the multiple stage gate drive circuit is configured to provide the drive signal to enable accurate current sensing of the cascode circuit., 'a controller coupled to control switching of the cascode circuit to transfer ...

Driving Apparatus For Switching Element

A power conversion circuit is mounted in a vehicle and controls an output torque of the rotating machine based on a requested command torque. A driving apparatus of a switching element controls a current flowing to the rotating machine. The driving apparatus sets at least one of a turn-on speed and a turn-off speed for the switching element to a plurality of switching speeds that are discretely determined, based on a parameter that is correlated with the output torque and has a controllable value. The driving apparatus turns on or off the switching element at the switching speeds. The switching speeds are allocated to the respective magnitudes of the parameter at uneven intervals, and determined such that the number of allocated switching speeds is greater in a range in which an occurrence frequency of the parameter is high, compared to a range in which the occurrence frequency is low.

MINIMIZING RINGING IN WIDE BAND GAP SEMICONDUCTOR DEVICES

Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off. 1. A power conversion circuit , comprising:a controller;first and second power amplifiers electrically coupled to the controller;a first semiconductor switch with a first gate electrically coupled to the first power amplifier;a second semiconductor switch with a first gate electrically coupled to the second power amplifier, a current conducting path of the first semiconductor switch being in series with a current conducting path of the second semiconductor switch; andwherein the controller is to, when controlling the second semiconductor switch to turn on and turn off, drive the first power amplifier to create a period of operational overlap for the first and second semiconductor switches by setting a gate voltage of the first semiconductor switch to an intermediate value above a threshold voltage of the first semiconductor switch.2. The power conversion circuit of claim 1 , wherein to create the period of operational overlap claim 1 , the controller is to:at a first time, set the gate voltage of the first semiconductor switch to the intermediate value; andat a second time, set the gate voltage of the first semiconductor switch to a low ...

Inverter device and air conditioner

An inverter device includes: a rectifier circuit that converts an AC power supply into a DC power supply; a smoothing unit that is connected to a subsequent stage of the rectifier circuit; a short-circuit unit that short-circuits the AC power supply via a reactor that improves a power factor of the AC power supply; an inverter unit that converts a direct current from the smoothing unit into an alternating current; and a control unit that controls the inverter unit, wherein a gate drive circuit is connected to a gate terminal of each switching element in the inverter unit, the gate drive circuit includes a first gate voltage line and a second gate voltage line having a voltage value larger than a voltage value of the first gate voltage line, and the voltage value of the first gate voltage line is variable even during an operation of the inverter device.

Driving device for switching element and power conversion system

In a driving device, a resistor is provided on a current path connected to an on-off control terminal of a switching element. The current path permits a drive current to flow therethrough to or from the on-off control terminal of the switching element. A switching rate setter sets a switching rate of switching the switching element from one of an on state and an off state to the other thereof. A current adjusting unit includes an open-close control element provided on the current path for electrically opening or closing the current path. The current adjusting unit is configured to adjust, according to the switching rate set by the switching rate setter, the drive current flowing through the current path and the resistor while closing the open-close control element.

Driver system with an optical power based isolated power supply

The present invention relates to a driver system that can include an optical power based isolated power supply. The driver system can include an optical receiver that can be in communication with an optical transmitter to receive an optical signal. The optical receiver can be configured to convert the optical signal to a drive signal having a determined drive strength. The driver system can further include a driving circuit that can be configured to drive an input of the transistor device based on the drive signal according to a control signal defining an on-time and off-time for the driving circuit over a time interval. In some examples, the driver system can be integrated with a protection system.

MULTI-STAGE GATE TURN-OFF WITH DYNAMIC TIMING

A turn-off circuit for a semiconductor switch includes an element having a variable resistance coupled to a control input of the semiconductor switch, a circuit for generating a control-input reference signal, and a control circuit coupled to adjust a resistance of the element having a variable resistance in response to the control-input reference signal in a closed control loop in order to turn off the semiconductor switch. 1. A driver circuit for a switch controller to control a power switch , the driver circuit comprising:an on-state driver coupled to receive an on signal, wherein the on-state driver outputs a first control signal to turn ON the power switch in response to the on signal and the first control signal is substantially equal to a high threshold;an off-state driver coupled to receive an off signal, wherein the off-state driver outputs the first control signal to turn OFF the power switch in response to the off signal and the first control signal is substantially equal to a low threshold; anda soft shutdown circuit coupled to receive the first control signal, wherein the soft shutdown circuit regulates the first control signal in a closed loop in response to a fault condition, wherein the soft shutdown circuit decreases the first control signal to a mid-threshold from the high threshold for a period of time and then decreases the first control signal to the low threshold, wherein the period of time ends in response to an end of a Miller plateau of the power switch.2. The driver circuit of claim 1 , wherein the soft shutdown circuit detects the end of the Miller plateau of the power switch when the off signal reaches a first threshold.3. The driver circuit of claim 1 , wherein the off-state driver further includes a transistor claim 1 , wherein the soft shutdown circuit is coupled to receive a gate signal representative of a gate current or a gate voltage of the transistor and detects the end of the Miller plateau of the power switch when the gate ...

Control circuit

A control circuit for a converter for use in a vehicle, such as an electrically powered vehicle. The converter has at least one controllable power semiconductor device. The control circuit is designed to control a changeover procedure of the at least one controllable power semiconductor device based on a control signal, and the control circuit is designed to control the at least one controllable power semiconductor device based on the control signal by temporally adjusting the behaviour of the at least one controllable power semiconductor device during the changeover procedure while taking a shaping parameter into account. The shaping parameter is a shaping parameter for electromagnetic emissions of the at least one controllable power semiconductor device. Also described is a converter for use in a vehicle having the at least one control circuit of that type, a vehicle having at least one converter of that type, and a corresponding method.

METHOD FOR CONTROLLING A SEMICONDUCTOR BRIDGE OF AN ELECTRICALLY OPERABLE MOTOR BY MEANS OF A RAMP SIGNAL, CONTROL DEVICE AND ARRANGEMENT

A method for controlling a semiconductor bridge of an electrically operable motor, the semiconductor bridge being controlled depending on a pulse width modulation signal by a first controllable semiconductor switch and a separate second controllable semiconductor switch for supplying the electrically operable motor with electrical energy, a ramp signal with a predeterminable ramp slope for controlling one of the two controllable semiconductor switches being generated by a ramp generator, depending on the pulse width modulation signal. The invention also relates to a control device and to an arrangement. 1. A method for controlling a semiconductor bridge of an electrically operable motor , the semiconductor bridge being controlled depending on a pulse width modulation signal by a first controllable semiconductor switch and a separate second controllable semiconductor switch for supplying the electrically operable motor with electrical energy ,whereindepending on the pulse width modulation signal, a ramp signal with a predeterminable ramp slope for controlling one of the two controllable semiconductor switches is generated by a ramp generator.2. The method as claimed in claim 1 ,whereinthe ramp signal for a predetermined opening value represents an opening signal for the first controllable semiconductor switch and a closing signal for the second controllable semiconductor switch when the first controllable semiconductor switch is open.3. The method as claimed in claim 2 ,whereinthe ramp signal is generated by the ramp generator with a predetermined fall time, so that the closing signal for the second controllable semiconductor switch is at least only generated after the fall time.4. The method as claimed in claim 3 ,whereinthe closing signal for the second controllable semiconductor switch is only generated after the fall time and after a predetermined fade-out time.5. The method as claimed in claim 1 , whereinan opening signal for the second controllable ...

Rectifier, Alternator, and Power Converter

A rectifier including an autonomous type synchronous-rectification MOSFET is provided, which prevents chattering and through-current caused by a malfunction when a noise is applied. The rectifier includes: a rectification MOSFET for performing synchronous rectification; a determination circuit configured to input a voltage between a pair of main terminals of the rectification MOSFET, and to determine whether the rectification MOSFET is in on or off state on the basis of the inputted voltage; and a gate drive circuit configured such that a gate of the rectification MOSFET is turned on and off by a comparison signal from the determination circuit, and such that a time required to boost a gate voltage when the rectification MOSFET is turned on is longer than a time required to lower the gate voltage when the rectification MOSFET is turned off.

BUS DRIVER WITH RISE/FALL TIME CONTROL

A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.

Floating Body Contact Circuit Method for Improving ESD Performance and Switching Speed

Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates. 1. An electronic circuit including: (1) a gate, a drain, a source, and a body;', '(2) a gate resistor series connected to the gate of such FET;', '(3) an accumulated charge sink (ACS) diode circuit connected to the body of such FET; and', '(4) an ACS resistance series connected to the ACS diode circuit, wherein the series-connected ACS resistance and the ACS diode circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate, and the ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS diode circuit; and, '(a) at least one field effect transistor (FET), each FET including (1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and', '(2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal., '(b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit ...

CONTROL CIRCUIT AND CONTROL METHOD FOR TURNING ON A POWER SEMICONDUCTOR SWITCH

A method of turning on a power semiconductor switch includes receiving a first signal that characterizes a switch-on behavior of the power semiconductor switch, and detecting two or more phases of the switch-on behavior of the power semiconductor switch in response to the first signal. The method further includes detecting a peak indicative of a phase transition between the two or more phases, generating a phase signal indicative of the two or more phases, and providing a variable current to a control input of the power semiconductor switch in response to the first signal. 1. A method of turning on a power semiconductor switch , comprising:receiving a first signal that characterizes a switch-on behavior of the power semiconductor switch;detecting two or more phases of the switch-on behavior of the power semiconductor switch in response to the first signal;detecting a peak indicative of a phase transition between the two or more phases;generating a phase signal indicative of the two or more phases; andproviding a variable current to a control input of the power semiconductor switch in response to the first signal.2. The method of claim 1 , wherein the first signal is a control input voltage.3. The method of claim 2 , wherein the control input voltage is a base-emitter voltage.4. The method of claim 2 , wherein the control input voltage is a gate-source voltage.5. The method of claim 1 , wherein detecting a peak indicative of a phase transition between the two or more phases comprises:using a peak timing detection circuit to detect the peak in the first signal.6. The method of claim 1 , wherein the two or more phases of the switch-on behavior of the power semiconductor switch comprises at least four phases of the switch-on behavior of the power semiconductor switch.7. The method of claim 1 , wherein a first phase begins if a switch-on signal of the control circuit of the power semiconductor switch indicates that the power semiconductor switch is intended to be ...

Circuit arrangement for the temperature-dependent actuation of a switching element

The invention relates to a circuit arrangement (100) for the temperature-dependent actuation of a first switching element (S1), comprising an input terminal (EA) for accepting an input potential, an output terminal (AA) for transferring an output potential to a first control terminal (G1) of the first switching element (S1), and a temperature-dependent component (RT) which is connected between the input terminal (EA) and the output terminal (AA).

DRIVE CIRCUIT FOR HALF-BRIDGES, CORRESPONDING DRIVER, DEVICE AND METHOD

A dead-time circuit includes a signal propagation path from a first input node receiving a PWM modulated control signal to an output node, such signal propagation path switchable between a non-conductive state and a conductive state, such that the signal at the first input node is transferred to the output node when the signal propagation path is in the conductive state. The dead-time circuit further includes a differentiator circuit block coupled to a second input node and to the signal propagation path, the second input node configured to be coupled to an intermediate node of a half-bridge circuit. The differentiator circuit block switches the signal propagation path between the non-conductive state and the conductive state as a function of a time derivative of a signal at the second input node. At least one time-delay circuit component delays transfer of the signal at the first input node to the output node. 1. A circuit , comprising:an output node couplable to a control terminal of a respective one of a high-side electronic switch or low-side electronic switch in a half-bridge arrangement including an intermediate node between the high-side electronic switch and the low-side electronic switch;a first input node configured to receive a PWM-modulated control signal for said respective one of the high-side electronic switch or low-side electronic switch;a second input node configured to be coupled to said intermediate node in the half-bridge arrangement; a signal propagation path from the first input node to the output node, the signal propagation path switchable between a first non-conductive state and a second conductive state wherein the PWM-modulated control signal at the first input node is transferred to the output node;', 'a differentiator circuit block coupled to the second input node and to the signal propagation path from the first input node to the output node, the differentiator circuit block configured to switch the signal propagation path between the ...

MINIMIZING RINGING IN WIDE BAND GAP SEMICONDUCTOR DEVICES

Embodiments include a power conversion circuit comprising first and second semiconductor switches, and a drive circuit configured to create a period of operational overlap for the first and second switches by setting a gate voltage of the first switch to an intermediate value above a threshold voltage of the first switch, during turn-on and turn-off operations of the second switch. Embodiments also include a method of operating first and second semiconductor devices, comprising: reducing a gate voltage of the first device to an intermediate value above a threshold voltage while the second device is off; turning off the first device after the second device is on; increasing the gate voltage of the first device to the intermediate value while the second device is on; and fully turning on the first device after the second device is off. 1. A power conversion circuit , comprising:a controller;a power loop;a first power amplifier and a second power amplifier, wherein both the first power amplifier and the second power amplifier are electrically coupled to the controller; a first semiconductor switch with a first gate electrically coupled to the first power amplifier; and', 'a second semiconductor switch with a first gate electrically coupled to the second power amplifier,, 'a gate control loop comprisingwherein the controller is configured to drive the first power amplifier to create a period of operational overlap for the first and second semiconductor switches by setting a gate voltage of the first semiconductor switch to an intermediate value above a threshold voltage of the first semiconductor switch,wherein a magnetic coupling is formed between a parasitic inductance in the power loop and a parasitic inductance in the gate control loop, andwherein the second semiconductor switch is turned on by the magnetic coupling.2. The power conversion circuit of claim 1 , wherein to create the period of operational overlap claim 1 , the controller is configured to:at a first ...

Floating Body Contact Circuit Method for Improving ESD Performance and Switching Speed

Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates. 1. An electronic circuit including: (1) a gate, a drain, a source, and a body;', '(2) a gate resistor series connected to the gate of such FET;', '(3) an accumulated charge sink (ACS) circuit connected to the body of such FET; and', '(4) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate; and, '(a) at least one field effect transistor (FET), each FET including (1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and', '(2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal., '(b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including2. The invention of claim 1 , wherein the resistance of the ACS resistance is sized to provide substantial ESD tolerance without substantially impairing ...

CIRCUITRY AND METHODOLOGY BENEFITTING FROM REDUCED GATE LOSS

In specific examples, aspects are directed towards eliminating, mitigating or reducing gate loss in circuits including, for example, WBG power devices. One such example is directed towards an apparatus including first and second types of field-effect transistor (FET), where the first type is characterized as being a normally-on FET in a switching-circuit operation with a high-voltage rating, and the second type of FET is characterized as being a normally-off FET in a switching-circuit operation with a voltage rating that is much less than the high-voltage rating of the first type of FET circuit. The FET are arranged in a cascode manner so that, in response to a switching control signal received by the second type of FET circuit, the second type of FET circuit is active to drive the first type of FET. 1. An apparatus comprising:a first type of field-effect transistor (FET) circuit characterized as being a normally-on FET in a switching-circuit operation with a high-voltage rating;a second type of FET circuit characterized as being a normally-off FET in a switching-circuit operation with a voltage rating that is less than an order of magnitude than the high-voltage rating of the first type of FET circuit; andthe first type of FET circuit and the second type of FET circuit configured in a cascode arrangement in which, in response to a switching control signal received by the second type of FET circuit, the second type of FET circuit is active to drive the first type of FET circuit.2. The apparatus of claim 1 , wherein the second type of FET circuit is to drive the first type of FET circuit towards optimization of claim 1 , or at least mitigate claim 1 , power loss due to a gate loss associated with the first type of FET circuit.3. The apparatus of claim 1 , wherein the first type of FET circuit refers to or includes a FET having Silicon Carbide (SiC) claim 1 , and the second type of FET circuit refers to or includes a wide bandgap FET.4. The apparatus of claim 1 , ...

Digital pulse width modulation control for load switch circuits

Example implementations relate to controlling a field-effect transistor (FET) switch in a load switch circuit. A digital pulse width modulated (PWM) voltage signal may be applied to a gate of a FET switch. The pulse width of the PWM voltage signal may be set to a first value. The pulse width of the digital PWM voltage signal may be digitally incremented to a second value. The digital PWM voltage signal having the pulse width of the second value may be applied to the gate of the FET switch.

System and method for controlling power module

A system and method for controlling a power module are provided. The system includes a switch element that adjusts output of a power module, a driving signal generation unit that generates a switch ON signal and a switch OFF signal for the switch element, and a latch that is connected between the driving signal generation unit and the switch element and is configured to delay the switch ON signal generated by the driving signal generation unit by a preset delay time and transfer a delayed signal to the switch element. Additionally, a compensation unit is connected between the latch and the power module and is configured to adjust the output of the power module during the delay time by which the latch delays the switch ON signal.

Semiconductor device and manufacturing method thereof

Reliability of a semiconductor device is improved. In the semiconductor device SA 1 , a snubber capacitor pad SNP electrically connected to the capacitor electrode of the snubber capacitor is formed on the surface of the semiconductor chip CHP.

POWER MODULE

A power module according to the present invention switches an operation mode between a control mode where an ON/OFF operation of a switching element having a first electrode, a second electrode, and a third electrode is controlled, and a deterioration determination mode where the deterioration is determined based on information including ΔVgs based on information including a threshold voltage detected before a stress current is supplied to the switching element and a threshold voltage detected after the stress current is supplied to the switching element. According to the power module of the present invention, the deterioration can be determined during an operation time and hence, breaking of the device can be prevented, and operation efficiency of the power module can be increased, and a manufacturing cost of the power module can be lowered. 1. A power module configured to switch an operation mode between: a control mode where an ON/OFF operation of a switching element having a first electrode , a second electrode , and a third electrode is controlled; and a deterioration determination mode where ΔVgs is calculated based on information including a threshold voltage detected before a stress current is supplied to the switching element and a threshold voltage detected after the stress current is supplied to the switching element , and deterioration of a device is determined based on information including the ΔVgs.2. The power module according to comprising:the switching element;a third electrode voltage control part which controls a third electrode voltage such that the third electrode voltage is increased in a stepwise manner when a threshold voltage is measured in the deterioration determination mode, and controls the third electrode voltage for controlling an ON/OFF operation of the switching element in the control mode;an ON/OFF state determination part which determines an ON/OFF state of the switching element in the deterioration determination mode;a memory part ...

MOTOR DRIVE APPARATUS AND MOTOR DRIVE APPARATUS CONTROL METHOD

Based on an output signal, among a plurality of switching elements, an element control part outputs a PWM signal having a maximum duty ratio to a pair of switching elements that drive a first coil among a plurality of coils to a high level, outputs a PWM signal having a minimum duty ratio to a pair of switching elements that are connected to each other in series and that drive a second coil among the plurality of coils to a low level, and outputs a PWM signal having a medium duty ratio between the maximum duty ratio of the PWM signal and the minimum duty ratio of the PWM signal to a pair of switching elements that are connected to each other in series and that drive a third coil among the plurality of coils. 1. A motor drive apparatus that supplies a current to a plurality of coils and that rotates a rotor , the motor drive apparatus comprising:a plurality of switching elements that turn on or turn off respective current supply routes connected to the plurality of coils;a plurality of detection sensors each of which is provided at a phase different from one another in a rotation direction of the rotor and which are configured to detect a phase in a rotation direction of the rotor and generate an output signal; andan element control part that turns on or turns off the plurality of switching elements individually based on the output signal,wherein, based on the output signal, among the plurality of switching elements, the element control partoutputs a PWM signal having a maximum duty ratio to a pair of switching elements that drive a first coil among the plurality of coils to a high level,outputs a PWM signal having a minimum duty ratio to a pair of switching elements that are connected to each other in series and that drive a second coil among the plurality of coils to a low level, andoutputs a PWM signal having a medium duty ratio between the maximum duty ratio of the PWM signal and the minimum duty ratio of the PWM signal to a pair of switching elements that are ...

SWITCHING ELEMENT DRIVE CIRCUIT

A switching element drive circuit that drives a main switching element by providing a control terminal of the main switching element with a drive signal that has asymmetric positive and negative potentials with respect to a reference potential, the main switching element including a ground terminal, which is a source terminal or an emitter terminal, and to which the reference potential is connected. 1. A switching element drive circuit that drives a main switching element by providing a control terminal of the main switching element with a drive signal that has asymmetric positive and negative potentials with respect to a reference potential , the main switching element including a ground terminal , which is a source terminal or an emitter terminal , and to which the reference potential is connected , the switching element drive circuit comprising:a power source circuit that is a positive and negative bipolar power source and includes a positive power source that provides a positive potential which is positive with respect to the reference potential and a negative power source that provides a negative potential which is negative with respect to the reference potential and whose absolute value is different from an absolute value of the positive potential, the positive and negative potentials being asymmetric with respect to the reference potential;an inductor, one terminal of which is connected to a control terminal side and the other terminal of which is connected to a reference potential side;a first current path in which a first rectification element, a forward direction of which is a direction from the control terminal side to the reference potential side, and a first switch are connected in series with each other; anda second current path in which a second rectification element, a forward direction of which is a direction from the reference potential side to the control terminal side, and a second switch are connected in series with each other, wherein:a ...

Control circuit and control method for turning on a power semiconductor switch

A control circuit for turning on a power semiconductor switch includes an input that receives a signal characterizing a switch-on behavior of the power semiconductor switch. A phase detection circuit detects two or more phases of the switch-on behavior of the power semiconductor switch in response to the signal that characterizes the switch-on behavior of the power semiconductor switch. The phase detection circuit is coupled to generate a phase signal that indicates which of the two or more phases the power semiconductor switch is currently running through. A variable current source is coupled to supply a current with a variable level to a control input of the power semiconductor switch to switch on the power semiconductor switch. The control circuit is coupled to control the variable current source in a closed control loop in response to the signal that characterizes the switch-on behavior of the power semiconductor switch.

SOFT-START CONTROL CIRCUIT

A soft-start control circuit is provided. The soft-start control circuit includes a load switch, a driving unit and a filtering unit. The first terminal of the load switch is configured to receive an input voltage. The control terminal of the load switch is configured to receive a switching signal and perform switching between on and off according to the switching signal, thereby performing a soft-start operation. The second terminal of the load switch is configured to provide a switched voltage. The driving unit is configured to provide a switching signal according to a control signal and release a parasitic charge stored in the load switch when the load switch is turned off. The filtering unit is configured to convert the switched voltage into an output voltage. 1. A soft-start control circuit , comprising:a load switch, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the load switch is configured to receive an input voltage, the control terminal of the load switch is configured to receive a switching signal and perform switching between on and off according to the switching signal, thereby performing the soft-start operation, and the second terminal of the load switch is configured to provide a switched voltage; a driving switch, configured to provide the switching signal according to a control signal; and', 'a first discharging circuit, coupled to the load switch and the driving switch, and configured to release a parasitic charge stored in the load switch when the load switch is turned off;, 'a driving unit, coupled to the first terminal of the load switch and the control terminal of the load switch, wherein the driving unit comprisesa filtering unit, coupled to the second terminal of the load switch and configured to convert the switched voltage into an output voltage and output the output voltage; anda protecting circuit, coupled to the driving switch, configured to pull-down a voltage level of the control ...

Method and Apparatus to Minimize Switching Noise Disturbance

A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration. After the initial duration, the current mirror is disabled and the first transistor is rendered fully conductive. 1. (canceled)2. A voltage reference circuit having a disabled state , an enabled state , and an intermediate state , wherein the voltage reference circuit is configured to receive a main reference voltage and operative to output a reference voltage in the enabled state , comprising:a voltage setting circuit operative to generate the reference voltage from the main reference voltage in the enabled state;a first transistor operative to interrupt current to the voltage setting circuit in the disabled state and to supply current to the voltage setting circuit in the enabled state and the intermediate state;a second transistor;a control circuit operative to enable the voltage reference circuit to switch to the enabled state via the intermediate state,wherein, in the intermediate state, the first ...

Gate drive apparatus

A gate drive apparatus including a constant-current-pulse gate drive circuit which creates a gate signal for a switching device as a constant-current output, a constant-voltage-pulse gate drive circuit which creates the gate signal as a constant-voltage output, and a decision/switch circuit which switches the operation of the constant-current-pulse gate drive circuit and the operation of the constant-voltage-pulse gate drive circuit. The variance of switching speeds attributed to the variances of threshold voltages and mirror voltages in a plurality of switching devices which are driven by the gate drive apparatus can be suppressed, and the variance of losses can be minimized.

Device for driving inverter

본 발명은, 반도체 스위칭 소자를 가지는 인버터의 구동장치에 관한 것이다. 게이트 전압 산출부(20)는, 인버터의 각 IGBT의 온도, 전류, 직류측 전압에 의거하여 서지 전압을 산출하고, 소자 내압과 비교한다. 게이트 전압 산출부(20)는, 소자 내압과 서지 전압의 차분이 소정의 문턱 전압을 넘어 있고, 서지 전압에 여유가 있다고 판단한 경우, 게이트 전압 제어부(22)에 대하여 통상값(기준값)보다 높은 게이트 전압을 지령한다. 게이트 전압 제어부(22)는, 기준값보다 높은 게이트 전압 지령에 의거하여 각 IGBT의 게이트를 스위칭 제어함으로써, IGBT의 정상 손실을 저감한다. The present invention relates to a drive device for an inverter having a semiconductor switching element. The gate voltage calculator 20 calculates a surge voltage based on the temperature, current, and DC voltage of each IGBT of the inverter, and compares it with the element breakdown voltage. When the difference between the element breakdown voltage and the surge voltage exceeds a predetermined threshold voltage, and the surge voltage has a margin, the gate voltage calculator 20 calculates a gate higher than the normal value (reference value) with respect to the gate voltage controller 22. Command the voltage. The gate voltage control unit 22 reduces the normal loss of the IGBT by switching control of the gates of the IGBTs based on the gate voltage command higher than the reference value.

Wear assembly for excavator edge

모스(mos) 전계 효과 트랜지스터를 구동하기 위한 회로

MOS 전계 효과 트랜지스터 (T O )를 게이트 제어하기 위한 회로가 방전 회로 (12)를 포함하고 이 회로를 통해 게이트-소스 캐패시턴스 (C GS )에 저장된 전하가 시정수에 따라 방전될 수 있고 시정수의 값이 상기 방전 회로 (12)의 내부 임피던스에 좌우된다. 이 방전 회로(12)는 큰 내부 임피던스 및 작은 내부 임피던스 각각에 의해 결정되는 두 상태 사이에서 스위치될 수 있고 게이트-소스 전압(U GS )가 소정의 값 이하로 강하하자마자 작은 내부 임피던스에 의해 정해지는 상태를 취한다.

Butter circuit for data output

내용 없음.

디지털 소프트 스타트 회로를 이용한 컨버터

본 발명은 소프트 스타트를 이용하는 컨버터에 관한 것이다. 본 발명의 한 특징에 따른 컨버터는 메인 스위치, 메인 스위치의 온/오프를 제어하는 PWM(pulse width modulate) 제어부 및 소프트 스타트를 포함한다. 소프트 스타트 제1 주기를 갖는 클록 신호가 입력되며, 제1 디지털 제어신호를 생성하고, 상기 제1 디지털 제어신호에 대응하는 소프트 스타트 전압을 생성한다. 소프트 스타트는 상기 PWM 제어부로 상기 소프트 스타트 전압을 전달하고, 상기 제1 디지털 제어신호를 피드백(feedback)시켜, 상기 제1 디지털 제어신호 및 상기 클록 신호를 이용하여 제어신호를 생성한다. 소프트 스타트는 생성된 제어신호에 따라 제2 디지털 제어신호를 생성하며, 상기 제2 디지털 제어신호에 대응하는 소프트 스타트 전압을 생성한다. PWM, 소프트 스타트, 카운터

Electric power conversion device and surge voltage reduction method

직류 전원(2)으로부터 공급된 직류 전력을 교류 전력으로 변환하는 전력 변환 장치로서, 와이드 밴드 갭 반도체를 이용한 전압 구동형의 트랜지스터(6－i)(i〓1, 2,ㆍㆍㆍ, 6)와, 다이오드(4－i)로 구성되는 6개의 스위칭 소자와, 스위칭 소자의 턴 오프 시에, 트랜지스터(6－i)를 구동하기 위한 전압을, 트랜지스터(6－i)를 비직선 영역에서 동작시키도록 정한 소정의 전압 프로파일에 기초하여 제어하는 구동 회로(5－i)를 구비한다. (6, i) (i = 1, 2, ..., 6) using a wide bandgap semiconductor is used as a power converter for converting DC power supplied from a DC power supply 2 into AC power, And a diode 4-i and a transistor 6-i for driving the transistor 6-i in the nonlinear region when the switching element is turned off, And a driving circuit (5-i) for controlling based on a predetermined voltage profile which is set so as to allow the voltage to be applied.

Power conversion device and surging voltage suppressing method

一种功率转换装置，其将由直流电源（2）供给的直流电力转换为交流电力，该功率转换装置具有：6个开关元件，其由使用宽带隙半导体的电压驱动型的晶体管（6-i）（i=1、2、…、6）和二极管（4-i）构成；以及驱动电路（5-i），其在开关元件断开时，将用于驱动晶体管（6-i）的电压，基于规定的电压轨迹进行控制，该规定的电压轨迹是以使晶体管（6-i）在非线性区域中动作的方式确定出的。

Inverter device and air conditioner

本发明提供一种逆变器装置以及空调机，该逆变器装置能与负载电流的大小相适应地使发生噪声与开关损失的折衷选择最佳。该逆变器装置具备：将交流电源变换为直流的整流电路；与整流电路的后级连接的平滑化部；经由改善交流电源的功率因数的电抗器而使交流电源短路的短路部；将来自平滑化部的直流变换为交流的逆变器部；以及控制逆变器部的控制部，逆变器部的开关元件的栅极端子分别连接有栅极驱动电路(14)，栅极驱动电路(14)具备第1栅极电压线(22)和电压值比第1栅极电压线(22)高的第2栅极电压线(23)，第1栅极电压线(22)的电压值在逆变器装置的动作中也是可变的。

Semiconductor integrated circuit

IGBT drive circuit

本发明提供了一种IGBT驱动电路，包括光耦芯片和功率放大电路；所述光耦芯片包括隔离放大单元和故障保护单元；故障保护单元包括去饱和模块和故障反馈模块；所述去饱和模块，用于在检测到IGBT的集电极的电位过高或者IGBT的集电极的电位变化过快时向故障反馈模块发送警示信号所述；故障反馈模块，用于在接收到警示信号后向外部控制器发送故障控制信号，从而控制外部控制器输出的外部驱动信号使得隔离放大单元输出控制IGBT关断的IGBT驱动信号。本发明所述的IGBT驱动电路采用光耦芯片来进行IGBT驱动，并具有对IGBT过压、过流、短路等故障检测的功能。

CMOS 3-state buffer circuit and its control method

본 발명은 출력트랜지스터의 턴온시 발생되는 역기전력을 제거하여 출력 신호가 되지 않도록 CMOS출력 드라이브에 적용가능한 3-스테이트 버퍼회로에 관한 것으로서, 드라이브회로의 출력트랜지스터에 인가되는 전압을 전원 전압보다 낮게 공급하는 보조드라이브회로를 구비하여 출력부를 제어하는 드라이브회로인 출력트랜지스터의 게이트전압을 전원전압보다 낮게 공급하여 역기전력 발생을 최소화되도록 함으로써 CMOS 3-스테이트 버퍼회로의 신뢰성 향상에 기여할 수 있는 것이다.

Signal generator and method for generating electric signal

PURPOSE: A signal generator and a method for generating an electric signal are provided to maintain signal waveforms available regardless of a variation of supply voltages by improving the structure of the signal generator. CONSTITUTION: A slew rate controlled driver circuit includes a supply voltage node, an input unit for receiving an input signal, and a signal generator(10) for generating an output signal of a slew rate. A signal generator(10) includes a transistor and a unit for constantly maintaining a voltage difference between the clamped input voltage of the transistor and the turn-on voltage of the transistor during data transmission. The signal generator(10) further includes an output driver, a current switch for enabling or disabling a current source, and a clamp connected to an input terminal of the output driver.

Semiconductor device

【課題】 パワーデバイスとその駆動回路とを備え、パワーデバイスのスイッチング時における駆動回路の誤動作を精度良く防止できる半導体装置を提供する。 【解決手段】 本発明による半導体装置は、パワーデバイスと、それを駆動させる駆動回路（３６）とを備える。駆動回路（３６）は、コンデンサ（５６）と、コンデンサ（５６）の電圧と第１の基準電圧とを比較して、その比較結果に基づく第１の信号を出力する第１の比較回路（５８）と、第１の信号に応じて、パワーデバイスに駆動信号を出力する駆動制御回路（６０）と、コンデンサ（５６）の電圧を検知して、コンデンサ（５６）の電圧が増加傾向にあり、かつ、所定の範囲内にあるとき、コンデンサ（５６）に電流を供給して、コンデンサ（５６）を充電させるコンデンサ充電回路（６２，６４，６６，６８）とを備える。 【選択図】図４

How to drive the current converter and the current converter driven by that method

Voltage regulator

(과제) 소프트 스타트 시간을 제어하는 아날로그 스위치 트랜지스터를 사용하여도, 오차 증폭 회로의 반전 입력 단자의 전압과 기준 전압 회로가 출력하는 기준 전압 사이에 차이가 생기지 않는 볼티지 레귤레이터를 제공한다. (해결 수단) 기준 전압을 귀환 전압으로서 귀환시켜 기준 전압을 출력하는 기준 전압 회로와, 전원 기동시에 기준 전압을 선형적으로 상승시키도록 제어하는 제어 신호를 출력하는 소프트 스타트 회로와, 분압 전압을 출력하는 분압 회로와, 기준 전압과 분압 전압의 차이를 증폭시켜 출력하는 오차 증폭 회로와, 오차 증폭 회로의 출력 전압에 의해 제어되는 출력 트랜지스터를 구비하고, 기준 전압 회로는 제어 신호에 의해 게이트가 제어되는 아날로그 스위치 트랜지스터를 가지고, 아날로그 스위치 트랜지스터의 출력 전압이 귀환 전압으로 되어 있다.

Drive device for driving voltage-driven element

一种用于驱动电压驱动型元件的驱动装置，其具备第1连接部、第2连接部、开关元件以及控制部。第1连接部被构成为，与电压驱动型元件的栅极电阻部相连接。第2连接部被构成为，与驱动电源相连接。开关元件中，第1输入输出端子被连接在第1连接部上，第2输入输出端子被连接在第2连接部上。控制部被连接在开关元件的控制端子上，并对输入至开关元件的控制端子的电压进行控制。控制部具有：误差放大器、参照电源以及开关。误差放大器的一个输入端子被连接在参照电源上，另一个输入端子被连接在第1连接部上，输出端子被连接在开关元件的控制端子上。开关的一端被连接在第2连接部上，另一端被连接在开关元件的控制端子上。

Driving circuit, converter and driving method

一種驅動電路用以驅動一開關元件。驅動電路包含一主輸出端、一第一電壓產生電路以及一第二電壓產生電路。主輸出端電性耦接開關元件。第一電壓產生電路電性耦接主輸出端。第一電壓產生電路包含一第一比較器及電性耦接第一比較器的一分壓電路。第一電壓產生電路用以於一切換週期之開啟期間的預設時間區間內在主輸出端產生一第一電壓。第二電壓產生電路電性耦接主輸出端。第二電壓產生電路用以於切換週期之開啟期間的剩餘時間區間內在主輸出端產生一第二電壓。第二電壓高於開關元件的臨界電壓。預設時間區間早於剩餘時間區間，第一電壓高於第二電壓。

Semiconductor switch device

提供一种半导体开关装置，该半导体开关装置实现并联设置的导通截止动作特性不同的多种半导体开关元件中的浪涌、损耗的减少。具备：开关电路部，其具备并联连接的、导通截止动作特性不同的多种半导体开关元件，使主电流接通或断开；驱动电路，其具备拉电流端子和灌电流端子，从所述拉电流端子和所述灌电流端子输出使各所述半导体开关元件一并导通或截止的驱动信号；以及阻抗元件，其插入安装于该驱动电路中的所述拉电流端子与所述灌电流端子之间，使将各所述半导体开关元件导通或截止的动作定时互不相同。

Gate driver circuit

본 발명은 게이트 구동 회로에 관한 것으로, 데이터 신호 및 폴트 상태 신호에 기초해서 제1 및 제2 제어 신호를 생성하고, 게이트 검출을 제어하는 구동 신호 생성부; 상기 제1 및 제2 제어 신호에 따라 동작하여 게이트 신호를 생성하여 파워 스위치 소자에 제공하는 구동 인버터; 및 상기 제2 제어신호에 따라 동작하여, 폴트시 소프트 턴오프를 수행하고, 상기 게이트 신호를 검출하여 검출신호를 제공하는 소프트 턴오프/게이트 검출부; 를 포함할 수 있다.

Method and device for soft-driving an array of logic gates and suppression of switching distortion

Switching distortion in a digitally controlled attenuator is effectively suppressed and soft-switching in passgate arrays, present at a certain point of a logic signal path, is implemented with a minimum number of additional components. The soft switching in passgate arrays is implemented by driving the control nodes of each passgate by an inverter, at least a current terminal of which is made switchable from the respective supply node to a node onto which an appropriate ramp signal toward the potential of the respective supply potential is produced by a suitable controlled ramp generator. The passgates for switching the current terminals of the inverters are controlled by the logic signal that preexisted the intervening switching on the respective signal line of the passgate, and by its inverse. The preexistent logic value is momentarily stored in a latch that is updated at the end of any new switching process. The switching distortion is suppressed by causing a fast turn-on of the selected switch and a slowed-down turn-off of the deselected switch and by connecting in parallel to the portion of the resistive voltage divider pertaining to the change of output tap a shunt resistance, deselected from the signal path downstream of the selected switch. The deselected switch is driven by a ramp of a preset slope. A circuit sensing the sign of the change of attenuation of the contingent command, configures a pair of switches that deselect the shunt resistance.

Radio frequency switch circuit with advanced isolation

본 발명은 아이솔레이션이 개선된 고주파 스위치 회로에 관한 것으로, 신호 송수신을 위한 제1 신호 포트와, 안테나 포트에 접속된 공통 접속 노드와의 사이에 직렬로 연결된 제1 내지 제n (여기서, n은 적어도 2인 자연수) 트랜지스터를 포함하고, 제1 게이트 신호에 의해 동작되는 제1 스위치 회로부; 신호 송수신을 위한 제2 신호 포트와, 상기 공통 접속 노드와의 사이에 직렬로 연결되어, 제2 게이트 신호에 의해 동작되는 제2 스위치 회로부; 및 상기 제1 스위치 회로부가 오프상태일 때, 상기 제1 스위치 회로부의 제1 트랜지스터의 게이트와 접지 사이에서, 교류 접지 경로를 형성하는 제1 임피던스 조절부; 를 포함할 수 있다. The present invention relates to a high-frequency switch circuit improved in isolation, in which first to n-th (here, n is at least) connected in series between a first signal port for signal transmission and reception and a common connection node connected to the antenna port 2) transistors, and is operated by a first gate signal; A second switch circuit portion connected in series between the common connection node and operated by a second gate signal; And a first impedance adjusting unit that forms an AC ground path between the gate of the first transistor of the first switch circuit unit and the ground when the first switch circuit unit is in the OFF state; . ≪ / RTI >

Apparatus for driving semiconductor switch element

반도체 스위치 소자의 구동 전력을 충분히 확보할 수 있음과 더불어, 확실하게 턴 오프시킬 수 있는 반도체 스위치 소자의 구동 장치를 제공한다. 구동 장치는, 스위칭 소자(Q1)를 구비하고, 이 스위칭 소자(Q1)를 온·오프함으로써, 원하는 직류 전압을 출력하는 컨버터부(2)와, 스위칭 소자(Q1)의 온·오프를 제어하는 제어부(1)와, 컨버터부(2)의 출력에 의해 충전되는 콘덴서(C1A, C1B)와, 콘덴서(C1A, C1B)에 축적한 전하를 이용하여 쌍방향 스위치 소자(4)의 게이트에 구동 전력을 공급하여, 쌍방향 스위치 소자(4)를 턴 온시키는 턴 온 회로(31A, 31B)와, 제어부(1)가 스위칭 소자(Q1)의 온·오프 동작을 정지시킨 경우에, 콘덴서(C1A, C1B)를 방전시켜, 쌍방향 스위치 소자(4)를 턴 오프시키는 턴 오프 회로(32A, 32B)를 구비한다.

Power semiconductor device with auxiliary gate structure

本公开涉及GaN技术中的功率半导体器件。本公开提出集成的辅助(双)栅极端子和下拉网络以实现具有高于2V的阈值电压、低栅极漏电流和增强的开关性能的常关(E模式)GaN晶体管。高阈值电压GaN晶体管具有高压有源GaN器件和低压辅助GaN器件，其中，高压GaN器件具有与集成的辅助低压GaN的源极(12)连接的栅极(10)晶体管和作为外部高压漏极端子(9)的漏极以及作为外部源极端子(8)的源极，而低压辅助GaN晶体管具有连接至漏极(第二辅助电极16)的用作外部栅极端子的栅极(第一辅助电极15)。在实施例中，用于关断高阈值电压GaN晶体管的下拉网络由附加的辅助低压GaN晶体管(34)以及与低压辅助GaN晶体管并联或串联连接的电阻元件形成。

Switching Gate Drive

본 발명은 게이트 드라이버 제어신호를 제공받아 전달하는 토템플 회로; 적어도 하나의 가변 저항을 구비하며, 상기 토템플 회로에서 제공되는 구동 제어신호를 IGBT 소자의 구동 제어신호로 전달하는 저항부; 상기 IGBT 소자에 인가되는 전압을 제공받아 상기 가변 저항 값을 제어하기 위한 가변저항 제어신호를 상기 저항부로 출력하는 전압 검침부; 및 상기 토템플 회로 및 상기 전압 검침부의 구동전압을 제공하기위한 구동전원부를 포함하는 스위칭 게이트 드라이버를 제공한다. The present invention relates to a saturation circuit for receiving and transmitting a gate driver control signal; A resistive part having at least one variable resistor and transferring a drive control signal provided from the earthed circuit to a drive control signal of the IGBT element; A voltage measuring unit for receiving a voltage applied to the IGBT element and outputting a variable resistance control signal for controlling the variable resistance value to the resistance unit; And a driving power source for supplying the driving voltage of the saturation current and the voltage measuring unit.

Switch driving circuit

本发明是关于一种柔性切换的切换驱动电路，其包含一输入电路，以接收一输入讯号；一第一延迟电路，依据输入讯号的致能产生一第一延迟时间；一第二延迟电路，依据输入讯号的禁能产生一第二延迟时间；一切换讯号产生器，用以产生切换讯号，其所产生的高压侧切换讯号的脉波宽度与输入讯号的脉波宽度成比例。一旦输入讯号致能时，高压侧切换讯号会经第一延迟时间后而致能。切换讯号产生器所产生的低压侧切换讯号依据输入讯号的致能而禁能，一旦高压侧切换讯号禁能时，低压侧切换讯号会经第二延迟时间后而致能。

Integrated circuit comprising logic circuits at least one push-pull stage

내용없음. None.

Semiconductor device

파워디바이스와 그 구동회로를 구비하고, 파워디바이스의 스위칭시에서의 구동회로의 오동작을 정밀도 좋게 방지할 수 있는 반도체장치를 제공한다. 본 발명에 의한 반도체장치는, 파워디바이스와, 그것을 구동시키는 구동회로(36)를 구비한다. 구동회로(36)는, 콘덴서(56)와, 콘덴서(56)의 전압과 제1 기준전압을 비교하여, 그 비교결과에 근거하는 제1 신호를 출력하는 제1 비교회로(58)와, 제1 신호에 따라, 파워디바이스에 구동신호를 출력하는 구동제어회로(60)와, 콘덴서(56)의 전압을 검지하여, 콘덴서(56)의 전압이 증가경향에 있고, 또한, 소정의 범위 내에 있을 때, 콘덴서(56)에 전류를 공급하여, 콘덴서(56)를 충전시키는 콘덴서 충전회로(62, 64, 66, 68)를 구비한다. Provided is a semiconductor device including a power device and a driving circuit thereof, which can accurately prevent malfunction of the driving circuit during switching of the power device. The semiconductor device according to the present invention includes a power device and a drive circuit 36 for driving the same. The drive circuit 36 includes a capacitor 56, a first comparison circuit 58 for comparing the voltage of the capacitor 56 with the first reference voltage, and outputting a first signal based on the comparison result; In response to the one signal, the voltage of the drive control circuit 60 and the capacitor 56 which outputs the drive signal to the power device and the capacitor 56 are detected so that the voltage of the capacitor 56 is in an increasing tendency and within a predetermined range. In this case, capacitor charging circuits 62, 64, 66, and 68 for supplying a current to the capacitor 56 to charge the capacitor 56 are provided. 반도체, 인버터, 트랜지스터, 구동회로, IGBT, 포토커플러, 비교기 Semiconductor, Inverter, Transistor, Driving Circuit, IGBT, Photocoupler, Comparator

Driving circuit of voltage control type power semiconductor element

本发明提供一种电压控制型电力用半导体元件的驱动电路，以使得即使在从检测出过电流起到开始保护切断为止的期间有关断信号的输入，也抑制产生高的浪涌电压。在接收到L电平的控制信号Vin而将IGBT(10)导通时，如果过电流检测电路(34)检测出过电流，且在该过电流检出状态还未经过软切断的延迟电路(35)的延迟时间的期间内，接收到将IGBT(10)关断的H电平的控制信号Vin，则慢切断检测电路(39)输出H电平的慢切断检测信号。由此，通过利用通常切断的NMOS晶体管(30)和慢切断的NMOS晶体管(40)来比通常切断更花费时间地进行IGBT(10)关断时的栅极电容的电荷抽取，从而抑制产生高的浪涌电压。

Semiconductor device and power conversion device using the same

Power mosfet having voltage-clamped gate

본 발명은 전압-클램프된 게이트를 가진 파워 MOSFET에 관한 것이다. 상기 MOSFET은 그 게이트 및 소스와 연결된 하나 이상의 다이오드를 포함하는 전압 클램프를 포함하고, 상기 전압 클램프는 소정 전압에서 파괴되도록 설계되어 게이트 산화층을 과잉 소스-게이트 전압의 결과로 인한 손상으로부터 보호한다. 전압 클램프는 대개 상기 MOSFET의 소스와 게이트 단자 사이에 연결된 하나 이상의 병렬 분기부를 포함한다. 각각의 분기부는 적어도 하나의 다이오드, 및 다수의 경우에 원하는 클램프 전압에 따라 게이트-소스 전압이 선택된 레벨에 도달하는 경우 순방향으로 파괴 또는 도전되도록 연결되는 일련의 다이오드를 포함한다. 낮은 클램프 전압을 얻기 위해 다이오드(들)은 대개 순방향으로 도전하도록 연결되고 높은 클램프 전압을 얻기 위해 다이오드(들)은 애벌란시 항복(avalanche breakdown)이 되도록 연결된다. 다수의 경우 주어진 분기부는 원하는 클램프 전압을 얻기 위해 다른 방향으로 연결된 다이오드들(예를 들어 애노드-애노드 연결된 다이오드쌍)을 포함한다. 하나 이상의 분기부가 사용되는 경우, 한 분기부내 다이오드는 다른 분기부내 다이오드보다 작은 클램프 전압을 제공한다. 그들 다이오드를 통한 전류의 양을 제한하기 위해 낮은 클램프 전압을 제공하여 전류가 강제로 그들을 통하게 되는 상황에서 그들이 타는 것을 방지하는 다이오드와 직렬로 저항이 연결될 수 있다. 특정한 분기부내 다이오드는 한 방향에서 게이트 산화층이 게이트 전압 스윙되는 것을 방지할 수도 있는 반면, 다른 분기부내 다이오드는 다른 방향에서 게이트 산화층이 전압 스윙되는 것을 방지할 수도 있다. 일부 실시예에서, 저항기와 다이오드의 병렬 결합부는 MOSFET의 게이트와 게이트 단자 사이의 경로에서 연결된다. 상기 다이오드는 역방향 바이어스되어, 게이트가 MOSFET을 온시키도록 구동되는 경우 전류가 저항기를 통하도록 하며, 게이트가 MOSFET을 오프시키도록 구동되는 경우 저항기 주위의 전류를 분류한다. 이러한 구성은 차별된 온, 오프 특성을 제공하며, 비교적 느린 온시간은 MOSFET이 온될 때 유도회로에서 발생할 수 있는 전압 오버슈트(overshoot) 및 링잉(ringing)을 방지하는 것을 특징으로 한다. The present invention relates to a power MOSFET having a voltage-clamped gate. The MOSFET includes a voltage clamp comprising one or more diodes connected to its gate and source, the voltage clamp being designed to break at a predetermined voltage to protect the gate oxide layer from damage as a result of excess source-gate voltage. The voltage clamp usually includes one or more parallel branches connected between the source and gate terminals of the MOSFET. Each branch includes at least one diode, and in many cases a series of diodes that are connected to break or conduct in a forward direction when the gate-source voltage reaches a selected level in accordance with the desired clamp voltage. To obtain a low clamp voltage the diode (s) are usually connected to conduct in a forward direction and to obtain a high clamp voltage the diode (s) are connected to have ...