Способ преобразования электрических импульсов в код Манчестер и устройство для его осуществления

Изобретение относится к электронным информационным техническим решениям общего назначения. Технический результат заключается в обеспечении устранения взаимовлияния прямого тракта и обратной связи, а также устранение апериодического эффекта от обратной связи. Предлагаемый способ состоит в том, что последовательность импульсов с входа устройства подвергается инверси знака для каждого четного импульса, посредством сохранения в памяти состояния входа на предыдущем шаге с помощью вспомогательного триггера, если на предыдущем шаге уровень сигнала был зафиксирован, то текущий шаг вычислений рассматривается в качестве четного. Последовательность импульсов на входе подвергается инверсии, чтобы обеспечить срабатывание триггера детектора сигнала на предыдущем шаге в противофазе по отношению к основному триггеру, на который и поступает полученная промежуточная последовательность импульсов с инверсией знака для каждого четного импульса, которая перед этим подвергается дополнительной коррекции. 2 н.п ...

Способ диагностики сверточных кодов

Изобретение относится к технике связи и может быть использовано для определения неизвестной структуры сверточного кодера со скоростью кодирования, равной, и кодовым ограничением, равным K, на основе анализа принимаемой кодовой последовательности. Технический результат – определение структуры используемого кодера для обеспечения работоспособности декодеров и повышение помехоустойчивости передачи информации. При осуществлении декодирования сверточных кодов необходимо знание структуры используемого кодера и сверточного кода, так как при отсутствии этой информации невозможно производить исправление ошибок. В данном способе повторно кодируют составляющие принимаемой общей кодовой последовательности с различными порождающими полиномами, перебирая их структуру, сравнивают результаты повторного кодирования. Поскольку символы исходной кодовой последовательности взаимно независимы, то результаты сравнения для всех сочетаний вида полиномов будут также случайны, кроме искомого вида полиномов. Для него ...

Оптоэлектронный цифровой преобразователь угла

Полезная модель относится к автоматике и вычислительной технике и может быть использовано в системе контроля и управления подвижными объектами. Устройство содержит измерительный вал, на котором укреплена оптическая маска инверсного кода Грея, считывающую диафрагму, группу излучателей, оптически связанных через кодовый диск и диафрагму с соответствующими фотоприемниками, подключенными ко входам фотоусилителей, микроконтроллер с группой аналоговых входов встроенного АЦП и ячейками ввода/вывода цифровых сигналов, аналоговый ключ, управляющий вход которого связан первой ячейкой микроконтроллера, а информационные входы аналогового ключа подключены к источнику опорного напряжения и общей точке цепи питания группы излучателей, механический переключатель режимов работы, подключенный ко второй и третьей ячейкам ввода/вывода микроконтроллера, причем выходы фотоусилителей связаны с соответствующими входами АЦП, а также блок индикации, подключенный к четвертой и пятой ячейкам ввода/вывода. Техническим ...

СПОСОБ ОПРЕДЕЛЕНИЯ ИНТЕГРАЛЬНОЙ И ДИФФЕРЕНЦИАЛЬНОЙ НЕЛИНЕЙНОСТЕЙ АЦП И УСТРОЙСТВО ДЛЯ ЕГО ОСУЩЕСТВЛЕНИЯ

Изобретение относится к области измерительной и вычислительной техники, а именно к метрологическим испытаниям аналого-цифровых преобразователей (АЦП). Техническим результатом является возможность определения интегральной и дифференциальной нелинейностей АЦП, снизив требования к эталонным средствам измерений по классу точности за счет учета нелинейной составляющей измерительного сигнала (ИС). Для этого устройство определения интегральной и дифференциальной нелинейностей АЦП содержит генератор ИС, источник сигнала перемещения ИС, схему перемещения ИС, микроконтроллер и ЭВМ. При этом первый вход схемы перемещения ИС соединен с выходом генератора ИС, а второй вход схемы перемещения ИС соединен с выходом источника сигнала перемещения ИС. Управляющие входы генератора ИС и источника сигнала перемещения ИС соединены с первым и вторым выходами микроконтроллера. Выход схемы перемещения ИС соединен с входом испытываемого АЦП, выход которого соединен с входом микроконтроллера, третий выход которого ...

Интегрирующий аналого-цифровой преобразователь

Изобретение относится к измерительной и вычислительной технике и может использоваться в цифровых измерительных приборах, а также в системах цифровой обработки аналоговой информации. Технический результат – повышение быстродействия преобразователя за счёт совмещения операции интегрирования входного сигнала и компенсационного интегрирования линейно изменяющегося образцового сигнала противоположной полярности. Для этого предложен интегрирующий аналого-цифровой преобразователь, который содержит первый 1, второй 2 и третий 3 аналоговые ключи, сумматор 5, первый 6 и второй 7 интеграторы, компаратор 8, формирователь импульсов 9, генератор тактовых импульсов 10, двухвходовой элемент И 11, R-S триггер режима 12, двоичный счётчик 13, трёхвходовой элемент И 14, элемент задержки 15, вход преобразователя 16, вход эталонного напряжения 17, вход запуска преобразователя 18, двоичный счётчик 13 имеет следующие входы: счётный 19, чтения 20 и обнуления 19, выходы двоичного счётчика. 3 ил.

СИСТЕМА СЧИТЫВАНИЯ ИНФОРМАЦИИ АНАЛОГО-ИНФОРМАЦИОННОГО ПРЕОБРАЗОВАТЕЛЯ (АИП) С ДИНАМИЧЕСКИМ ПРОФИЛЕМ ИНТЕГРИРОВАНИЯ (ДПИ)

Изобретение относится к области аналого-цифровых преобразований. Техническим результатом изобретения является создание системы считывания аналого-информационного преобразователя (АИП) со сниженным энергопотреблением, за счет уменьшенного времени сбора информации о сигнале; с увеличенной производительностью, за счет использования ДПИ; с расширенной областью применения не только для частотно-разреженного сигнала, в режиме, когда минимальный интервал интегрирования не меньше времени оцифровки используемого АЦП; с увеличенной скоростью функционирования, за счет использования блока управления АЦП интегратором; с улучшенной функциональностью, за счет использования смешивающего устройства на базе УВХ на переключаемых конденсаторах; с улучшенной производительностью, за счет использования смешивающего устройства и фильтра низких частот, что позволяет обрабатывать целевой сигнал из широкой полосы частот. 2 з.п. ф-лы, 4 ил.

Устройство для определения углеродногоэКВиВАлЕНТА B жидКОМ МЕТАллЕ

VERFAHREN UND GERAET ZUR SYNTHETISCHEN ERZEUGUNG VON WELLENFORMEN (WELLENFORMSYNTHESIZER)

D-A converter for digitally coded numbers - has signals applied to digitally controlled frequency divider whose output operates switch

The digital-analogue converter is for digitally coded positive and negative numbers having a sign digit in addition to other digits, and converts the numbers into positive or negative analogue voltages. Digital signals are applied to a digitally controlled frequency divider whose output signals operate a switch through which, depending on the input signal sign, a constant positive or negative voltage is applied to a frequency-to-voltage or frequency-to-current converter, connected between a negative and a positive supply potential. The frequency divider is connected to one input of an EXCLUSIVE-OR gate which feeds one input of an AND gate.

Einrichtung zur Abtastung der Position von getriebegekoppelten Scheiben mit modifiziertem Gray-Code

Elektrische Positionsmessvorrichtung mit einem die Position eines Geraeteteils in den Phasenwinkel einer Wechselspannung abbildenden Wandler

Digitaler Spitzenspannungsmesser

Elektrische Einrichtung fuer Messgeraete und Waagen, insbesondere Neigungspendelwaage, zur Registrierung der Ausschlagsweite

Einrichtung zur digitalen Messung von Drehwinkeln

Analog-Digital-Wandler

Verfahren und Anordnung zum Korrigieren von bei Abtastung einer Massverkoerperung anfallenden Abtastsignalen

Einrichtung zur selbsttaetigen Anpassung der Reglerverstaerkung an die Regelstrecke

A-D Converter has microphone at radial arm end - scanning circular acoustic line and detecting acoustic pulses that then stop counter

The A/D converter consists of a rotating arm with a microphone (3) at its outer end scanning a circular acoustic line (1). Acoustic pulses are applied to the circular acoustic line and the time delay between their generation and reception (by the microphone) depends on the position of the microphone on the circular line. The acoustic pulses are prevented from travelling both ways round the line by an absorber (8). A counter (7) is synchronised with the acoustic pulse generator (2) and counts pulses for the time between transmission and reception of the acoustic pulse. Two microphones can also be used.

Analog-Digital-Umsetzer mit einem Impulsgenerator variabler Impulsfrequenz

SPANNUNGS BZW STROM FREQUENZ WANDLER

Movable member position detection and display - uses signal source with distributor, coding elements and converters delivering code

The movable member is shifted with respect to a first member, and its position is displayed in an n-digit code. The device consists of a supporting element for code elements arranged in n separate tracks, and there is a distributor movable relative to the supporting element synchronously with one of the two members. The device comprises further a circuit (1, 3) delivering to a distributor (4) a charging voltage with varying waveform. The distributor transmits a voltage waveform derived from the varying waveform to a code element (2', 2", 2"') over which it just passes. N converters (5) receive the signals from code elements (2) and generate an n-digit code.

Analog-stochastic converter with two way counter - controls charging of capacitor that produces zero point correction voltage

The analog/stochastic converter has a multiplexer (MX) as input changeover switch applying a zero signal at sufficiently frequency intervals to the converter (ASU). The converter outputs are connected during this time to the input of an up-down counter (VR). The up and down transfer outputs of the counter control two current sources (SR, SV) for a given time when a transfer pulse appears. These current sources control the charging of a capacitor (C). The capacitor is connected to the input of the converter to correct for zero point errors.

VERFAHREN ZUR MULTIPLIKATION/DIVISION ANALOGER SPANNUNGEN

Integratable fast A:D converter - has two counters supplied with clock pulses under control of input signal

The fast A/D converter can be readily integrated and consists of a pair of clocked counters (72, 71) reset by a control circuit (St). The analog input signal (E) is switched (S3) to a storage capacitor (C) coupled to the input of a trigger (S). Two constant current sources can be switched to the trigger input by switches (S1, S2) controlled from the control circuit. The trigger detects signal polarity on the capacitor. The control circuit controls the switching of the clock pulses to the counters and their read out eg by means of two AND-gates (U) and an OR-gate (O).

D=A converter using positive negative constant currents - has lead resistors of twice value of two end lead and all transverse resistors

The d-a converter employes U-characteristics and is designed to be comparable price to one employing A-characteristics. This is achieved by realising one and the same halves of the characteristics using constant currents of both more positive and more negative polarity in the distribution at the connection points of an R-2R resistor network. The non-linear kinked characteristics curve is formed from 2 to the power of m linear sections for each signal's half line with 2 to the power of n amplitude stages.

ECL compatible integrated circuit A=D converter - has identical comparators coupled in groups to multiple-input AND=gates

The analog/digital converter has identical comparators connected at one input to one of a series of equidistant reference voltages and at the other to a shared input signal rail. The number n is given by n = 2m - 1, whre m is the number of AND-gates each with 2m-1 inputs connected to the outputs of the comparators. Each AND-gate input is connected to only one comparator. Groups containing 2m-1 comparators are connected to the path comparator. The comparator with the lowest number in the first group assigned to the path gate has the number 2m-1 and there are 2m-1 comparators between each group.

Coding disc scanner setting unit - includes bracket pivoted on stepping motor shaft carrying coding disc

The setting accuracy for sensor of coding disc controlling the location of printing carriage or of a slide in a machine tool is enhanced by the carrier. It tilts on a shaft (3) of the coding disc (7) and mounts the clamp for the bearing of the sensor. The shaft (3) is the output shaft of the stepping motor (1) and both the sensor housing and the coding disc are provided with markings. The coding disc (7) is transparent, and the carriage (39) of the pring head (41) is driven by a cable drum (5) with a cable (17) guided by rollers. The relative position of the sensor (45) and the coding disc (7) is adjusted by a clamping screw.

Signalwandler und Verfahren zum Betreiben eines Signalwandlers

Die Erfindung bezieht sich auf einen Signalwandler und ein Verfahren zum Betreiben eines Signalwandlers, mit: Durchführen einer Analog-Digital-Wandlung eines analogen Eingangssignals, was das Vergleichen des analogen Eingangssignals mit einem analogen Vergleichssignal umfasst; Ermitteln, ob das analoge Eingangssignal eine vorgegebene maximale oder minimale Schwelle übersteigt, was das Vergleichen des analogen Eingangssignals mit einem analogen Schwellensignal umfasst; wobei das analoge Vergleichssignal und das analoge Schwellensignal durch denselben Digital-Analog-Wandler erzeugt werden.

Verfahren zur nicht linearen Umformung eines pulsamplitudenmodulierten Eingangssignals in ein pulscodemoduliertes Signal

Verfahren zur Tonwiedergabe und Vorrichtung zur Durchfuehrung des Verfahrens

Analog-Digital-Spannungswandler

Digitale Verarbeitungsschaltung mit Verstärkungsregelung

Linearisierungseinrichtung fuer Messwert-Umformer

DIGITAL-ANALOG-UMSETZERSCHALTUNG ZUR LIEFERUNG VON ANALOGSPANNUNGEN, DIE FUNKTIONEN EINES DURCH DIGITALE EINGANGSSIGNALE DARGESTELLTEN WINKELS SIND

Verfahren und Einrichtung zur Analog-Digital-Umsetzung

Vorrichtung zur Kraftmessung mit digitaler Messwertanzeige

Gleichstromvoltmeter

Elektrische Schaltungsanordnung

KURVENGENERATOR

TEMPERATURSTABILISIERTER STROMGENERATOR-DA-WANDLER

D-A convertor has analogue output volts from first memory - controlled by measuring difference between internal and external references

The D/A converter has two counter registers which have one reference coupled to the integrator via a cycle control circuit. The integrator is switched via two analogue memories to two output circuits -- one giving the analogue output and the other an analogue reference voltage as in 2329822. The output voltages of one analogue memory is controlled according to the difference between the internally generated analogue reference voltage and an externally applied reference voltage. A gain controlled amplifier is connected before or after the first analogue memory.

Anordnung zur numerischen Codierung der Phasenverschiebung zwischen zwei Wechselspannungen gleicher Frequenz

Vorrichtung zum Abtasten eines nach Massgabe eines Messwertes in einem Ausschlagbereich ausgelenkten Anzeigegliedes und zum Umsetzen dieses Messwertes in eine digitale Information

Anordnung zum Erzeugen von elektrischen Impulsen,insbesondere fuer datenverarbeitende Maschinen

Schaltungsanordnung zur Ausloesung eines elektrischen Schaltvorganges in Abhaengigkeit von einer Vorbestimmten Elektrizitaetsmenge

Electrical data indicator with luminous cells - has electronic switches connected to luminous cell electrodes

The indicator has an electronic switch connected to the other electrode of each luminous cell and control electrodes on the electronic switches, which are interconnected by way of diodes in series. A second electronic switch is connected in series to each of the first electronic switches and the second switches are in series with one another. Their control electrodes are in parallel and ar elinked by way of diodes to the electrode, connected to one of the first switches, of the next following luminous cell. Analogue digital converters are used.

Digitaler Signal-Linearisator

VERFAHREN ZUR ANALOG-DIGITAL-UMSETZUNG VON SPANNUNGSWERTEN

Printing mechanism

... 945,604. Typewriters &c. SMITH-CORONA MARCHANT Inc. April 21, 1960 [July 24, 1959], No. 10992/62. Divided out of 945,603. Heading B6F. [Also in Division H4] In a printing apparatus employed in a type-wheel printer, comprising a rotatable type-wheel assembly and a print-hammer device having a hammer lever pivotally mounted adjacent one end for engaging and impacting a recording medium against a selected portion of the type-wheel, a portion intermediate the ends of the hammer lever is arranged to receive an operating impact for the printing operation, and the lever is provided with a bore into which is adjustably fitted the stem of a low-mass hammer head, the stem being longer than the bore and provided with retaining means to prevent axial movement of the hammer head out of the bore, and an abutment portion on the upper surface of the hammer lever engages a stop upon the impacted movement of the hammer lever so that the hammer head continues its movement relative to the hammer lever due ...

Improvements in receiving apparatus with electronic selector and controller with storage system

... 945,607. Printing - telegraph receiving systems. SMITH-CORONA MARCHANT Inc. April 21, 1960 [July 24, 1959], No. 10995/62. Divided out of 945,603. Drawings to Specification. Heading H4P. [Also in Division G4] The subject-matter is wholly included in Specification 945,603 but the claims are directed to an electronic selector and controller utilized in teleprinter receiving apparatus for messages sent by coded signals and including an electronic storage register system associated with means for supplying input character code combinations, and which is provided with first and second signal storage systems, each having separate connecting channels, the input coded character combinations being applied to the first storage register and output signals from the first storage register being applied to the input terminals of said second storage register together with means connected to the output of the second storage register to withdraw said character code combinations at a varying rate dependent ...

NON-LINEAR DECODER FOR TERNARY CODES

... 1,219,148. Digital to analogue converters. INTERNATIONAL STANDARD ELECTRIC CORP. 22 April, 1968, No. 18872/68. Heading G4H. In non-linear digital to analogue converter for ternary scale numbers, the non-linear characteristic is approximated by a plurality of differently sloped straight line segments, the most significant ternary digits of a number being used to develop a signal representing the minimum voltage of the corresponding segment, the remaining digits being used to develop a signal representing the position within the segment and the two signals being combined in a weighting and summing circuit to produce the analogue output. The characteristic, Fig. 2, comprises seven segments formed by lines having four different slopes. The value of the digits depends upon the zone in which the code falls and this is determined by the value of the two highest valued ternary digits. Each ternary digit is expressed by two binary bits. The four bits corresponding to the two highest ternary digits ...

CONTACT ASSEMBLIES

... 1,216,822. Rotary distributers; switch contacts. LITTON INDUSTRIES Inc. 14 Jan., 1969 [13 June, 1968], No. 2207/69. Heading H1N. A sliding contact assembly for an encoder as in Specification 1,089,120 (see Division G4) is modified to allow lubricant to be continuously and gradually dispensed from the reservoir to the contact-making surface and the device is driven at such a high speed that the hydrodynamic pressure built up reduces the contact pressure substantially to zero.

AN APPARATUS FOR THE CONVERSION OF DISTANCE/ANGLE VARIATIONS INTO A CODED OUTPUT SIGNAL

... 1,239,830. Coding distance and angle variations photo-electrically. KOMBINAT NAGEMA VEB. July 18, 1968. No.34330/68. Heading G1A. Distance or angle variations are converted into digital output signals by converting them into angular movements of one glass plate relatively to another and investigating the interference in the wedge between the plates. Light from a monochromatic source 1 is collimated by a lens 2 and passes through the wedge 5, 6 to a projection system forming an image of the interference pattern in the plane of photo-conductive cells 4. The cells may be arranged to count fringes to provide incremental coding by using an oscillating optical system 3. Absolute coding may be provided by arranging the cells so that the numbers of fringes which pass them are in the same ratio as the light and dark areas on a conventional code strip. In order to provide cells which view the same part of the pattern but 90 degrees out of phase the spacing of the glass plates may increase steadily ...

MODULATED PULSE COMPUTING CIRCUITS

... 1,239,922. Pulse width computation. K.D.G. INSTRUMENTS Ltd. 26 July, 1968 [27 April, 1967], No. 19529/67. Heading G4G. A pulse width modulator (Fig. 4) comprises an integrator with a D.C. amplifier and capacitance feedback C excited by input signal V 1 over resistance R; the integrator output operating a Schmitt trigger whose trip levels are O and V 2 which gates a voltage-V 3 to amplifier input over further resistance R for removal at level V 2 and application at level O. For zero input the integrator output oscillates with equal rise and fall times t 1 = t 2 CRV 2 /V 3 , and for V 1 input t 1 = CRV 2 /V 3 -V 1 t 2 = CR V 2 /V 1 so that mark space ratio = t 1 /t 2 = V 1 /V 3 -V 1 and V 1 /V 3 = t 2 /t 1 +t 2 (Fig. 5, not t 2 V 3 -V 1 V 3 t 1 +t 2 shown), and if the trigger switches an output gate (not shown) between limits of V and +V 4 , mean value of output the gate level voltages V 3 , V 4 being controllably variable. The trigger may derive a P.W.M. output signal indirectly by utilizing ...

Improvements in and relating to pulse code modulation systems

... 657,681. Multiplex pulse code signalling. GENERAL ELECTRIC CO., Ltd. Jan. 26, 1948, No. 2301. [Class 40 (v)] A signalling system uses pulse code modulation to convey coarse information regarding a magnitude, and amplitude, phase or duration modulation of a recurrent pulse to convey fine information. As described in a multiplex system, in each channel the repeated groups of code pulses are transmitted simultaneously, using different radio frequencies and two other simultaneous recurrent pulses, of other radio frequencies, are modulated to convey finer information, the channel pulses being interlaced. In a circuit for handling the odd-numbered channels for a 20-channel system, the channel signals are applied to a known distributer and time modulator TM, Fig. 2, to produce time - modulated pulses such as P1, P3, Fig. 1 (a), shown in channels CH1, CH3, respectively. All these pulses are applied to gating circuits GA, GB and GC to which are applied gating waveforms A, B, C, Figs. 1 (d), (c) ...

Improvements in or relating to electron discharge apparatus

... 663,838. Cathode-ray tubes. WESTERN ELECTRIC CO., Inc. Dec. 12, 1947 [Dec. 13, 1946], No. 32804/47. Addition to 637,820 and 663,837. Class 39 (i). [Also in Groups XXXV and XL (c)] In a signalling system as claimed in the parent Specification in which the amplitude of a complex wave is sampled at recurrent intervals, an electron beam of a cathode-ray tube is deflected in. one direction by plates 20a, Fig. 1, to an extent in accordance with the amplitude of each sample to select a path and is swept along that path by a suitable sweep circuit, and a coding element 26 comprising a plate with rows of apertures formed therein produces pulses at the target 27 representing by a permutation code the sampled signal wave amplitude, a grid electrode 25 with a secondary emission coefficient of greater than unity is arranged in front of the coding element 26, and electrode 24, which collects the secondaries, is connected by a feed-back path comprising an amplifier to the deflecting plates 20a so that ...

MEASURING APPARATUS

... 1435221 A/D converters OKI ELECTRIC INDUSTRY CO Ltd and JAPAN SOCIETY FOR THE PROMOTION OF MACHINE INDUSTRY 24 July 1973 [24 July 1972] 35180/73 Heading H3H An A/D system comprises a plurality of measuring devices each including a sensor adapted to produce a voltage corresponding to a quantity to be measured and a voltage corresponding to a reference quantity, and an A/D converter operatively connected to the measuring devices for receiving from each the measurement voltage at a first input and the reference voltage at a second input, whereby a ratio between the two voltages is obtained in the converter. As shown in Fig. 2, a dual ramp A/D converter 6 is supplied with a reference voltage at 7 derived across a fixed impedance 2 and inverted in polarity at 4, and with an input voltage derived at 5 as the difference between the voltages across the impedance 2 and a variable impedance 3, the two impedances being connected in series across a source of voltage 1, the value of the impedance 3 ...

IMPROVEMENTS IN OR RELATING TO COMPANDING ENCODERS AND DECODERS

... 1299859 Digital companding NIPPON ELECTRIC CO Ltd 31 Dec 1969 [24 March 1969] 61944/68 Heading G4H A digital companding PCM decoder comprises a memory circuit 26 for storing an input PCM binary code, a code conversion matrix 27 adapted to convert the input code into a modified digitally expanded output code having more bits than the input code, the modified output code consisting of a digitally expanded code of which a predetermined number of most significant zero bits are omitted when the most significant bit of the input code is 0 and of which the same number of least significant bits are omitted when the most significant bit of the input code is 1, a linear decoder 28 adapted to convert the modified output code into an analogue signal, and an adjustable attenuator or amplifier 29 controlled by the most significant bit of the input code to adjust the gain to which the analogue signal is subjected when this bit is 1 and U respectively to higher and lower values respectively whose ratio ...

ANGULAR POSITION ENCODING SYSTEMS

... 1398533 Capacitive position encoder NORTHERN ILLINOIS GAS CO 17 Aug 1972 [19 Nov 1971] 38466/72 Heading G4H An encoder for the angular position of a rotary shaft comprises a plurality of segments arranged round the shaft, means for providing excitation signals to each of said segments in sequence, a coupling member mounted for rotation to overlie a different one of said segments in each of said shaft positions and means connecting said coupling member to an otuput. As described, the coupling member is a vane V mounted on and insulated from shaft 21 and overlying segments A to J. Cylinder A to which vane V is connected is mounted partially inside cylinder 62 which is insulated and shielded from the segments and couples a signal electrostatically induced in vane V by an energized adjacent segment to output sensing circuit 60. The sensing pattern applied to the segments is as shown in Fig. 4. A high level signal is applied to a segment (say A) and a low level signal to the next but one segment ...

Improvements in or relating to the surface treatment of titanium or titanium base alloys

Titanium or titanium-base alloy articles are treated with concentrated hydrochloric acid at elevated temperatures prior to deposition of a coating metal thereon. Preferably the treatment is effected at 90 DEG -100 DEG C. If the article is heavily scaled, it may be pre-treated with a standard pickling solution, e.g. HF/HNO3 solution, or with a standard caustic melt descaling bath consisting of molten NaOH with or without other constituents such as sodium hydride, before treatment with the HCl. Electroplating with silver is referred to.

Digital voltmeter

... 1,062,194. Analogue-to-digital converters. INSTITUTE AUTOMATIKI I ELECTROMETRII SIBIRSKOGO OTDELENIJA AKADEMII NAUK U.S.S.R. June 12, 1964, No. 24455/64. Heading G4H. [Also in Division H4] In a self-balancing digital voltmeter for an A.C. voltage of any waveform, a balancing voltage is derived from the unknown voltage which has the same waveform as the unknown voltage and has a known r.m.s. value, being adjusted so that it has the same energy as a reference D.C. voltage, the balancing voltage being fed through a digital attenuator which is adjusted until it balances the unknown voltage, the setting of the attenuator being displayed to indicate the value of the unknown voltage. The A.C. voltage U x , Fig. 1 (not shown), to be measured is of arbitary waveform and is fed to shaper 1 which produces a reference voltage U r and having a similar waveform to the input voltage U x but being constant while U x varies over a given range. The reference voltage is fed to the balance voltage generator ...

A device for performing conversion with a non-linear conversion characteristic between a digital and an analogue signal

... 1,066,082. Analogue-to-digital and digital-toanalogue converters. NIPPON ELECTRIC CO. Ltd. April 10, 1964 [April 12, 1963], No. 14879/64. Heading G4H. A digital-to-analogue converter with a non- linear companding characteristic comprises two series-connected voltage sources (21, 22) with two parallel networks connected across them, the first network comprising first (23) and second (24) weighted-resistor switch circuits which have equal sets of resistors but are controlled inversely by the digital input, and the second network comprising third (27) and fourth (28) weighted-resistor switch circuits which have equal sets of resistors, are controlled inversely by the digital input and are connected together via two non-linear resistors, the converter output being taken from between the first and second switch circuits and from between the non-linear resistors. Each bit (a 1 , a 2 ... a k ) of the digital input, if it is " 1," connect a corresponding binary-weighted resistor in each of the ...

Improvements in or relating to anologue-digital converters

... 1,066,770. Selective signalling. SIEMENS A.G. Dec. 20, 1965 [Dec. 21, 1964], No. 53856/65. Heading G4H. In a non-linear voltage digitizer an exponentially decaying reference voltage, produced by a capacitor or inductor, is compared both with an unknown input voltage and with a known reference voltage and clock pulses are counted from the first instant at which the exponentially decaying reference voltage equals either the input voltage or the reference until the instant at which it equals the other. A sign indicator in the counter is set in accordance with the first equality that occurs. The unknown input voltage may be attenuated selectively, either automatically or manually, in order to effect range changing.

Improvements in or relating to electric measuring devices

... 1,093,760. Electric selective signalling. SIEMENS A.G. Nov. 11, 1965, No. 47845/65. Heading G4H. [Also in Division G1] In an electrical measuring device four transducers e.g. strain gauges, are connected to form a bridge 9, Fig. 1, having the output diagonal connected in opposition with that of a second compensator bridge 10 through an amplifier 15 controlling a servomotor 14 which moves a sliding-contact 13 of a potential divider or potentiometer 12 until the two bridge outputs balance when the position of contact 13 indicates the output voltage of bridge 9. The input diagonals of bridges 9, 10 are fed by current transformers 5, 6 whose primary windings 3, 4 are connected in series with a low-resistance A.C. source, whereby the excitation currents of the two bridges have a constant magnitude ratio. Alternatively, the device comprises a single current transformer, Fig. 6 (not shown), whose secondary winding energizes the transducer bridge, whereas the primary winding energizes the second ...

Digital coder

... 1,126,998. Analogue to digital converters. INTERNATIONAL STANDARD ELECTRIC CORP. 19 May, 1967 [17 June, 1966], No. 23394/67. Heading G4H. In an analogue to digital converter a binary counter controls, through a decoder circuit and a plurality of current generators, the charge on the condenser which is compared with the signal voltage to obtain a signal when they are equal. The converter has a characteristic approximating to a logarithmic function, Fig. 3, Clock pulses H from source 40 are applied to a seven stage counter 10, Fig. 4. As the value in the counter increases a waveform is generated consisting of a series of straight line segments, the capacitor C being charged at a different rate to obtain each segment. Decoder 11 receiving the outputs from the three most significant stages of the counter gives a signal on one of eight leads P0-P7 connected via Or gates 12-15 to control one of the four current sources 16-19 to charge the capacitor at four different rates. The unknown signal ...

Switching circuits

... 1,127,031. Selective signalling. NORTH ATLANTIC INDUSTRIES Inc. 28 Sept., 1965 [25 Feb., 1965], No. 41197/65. Heading G4H. [Also in Division H3] Digital-to-analogue converting and digital measuring systems have switching operations performed by a diode bridge with a signal source and load across one diagonal and a controlled biasing source across the other diagonal with one terminal connected to a terminal of the first diagonal (see Division H3). In a digital to-analogue converter (Fig. 5, not shown) the digital signals control a number of such switching bridges which join a summing amplifier to one of a number of taps of a transformer secondary winding via series resistors. The transformer primary is energized by a constant voltage and the tap positions or the series resistors are weighted according to the binary code. In a measuring system (Fig. 6) an input voltage is resolved in unit DC 61 into sine and cosine terms which are applied to transformers T60 and T70 in either phase depending ...

Improvements in or relating to radiation responsive devices

... 1,137,475. Photo-electric measuring systems. ROSEMOUNT ENG. CO. Ltd. 11 Jan., 1967 [13 Jan., 1966], No. 1730/66. Heading G4H. [Also in Divisions C4 and H1] A fibre which fluoresces when a source of exciting radiation is directed on to it is masked over part of its length so that the position of the source of radiation may be found, a photocell determining when the radiation is falling on the fibre. In one embodiment (Fig. 1) a fibre 10 connected to a photo-cell 11 has a mask (Fig. 2, not shown) movably positioned in front of the fibre so that as the mask is moved a series of output pulses are obtained from the photo-cell 11 representing in binary code the position of a light beam 13. In a second embodiment (Fig. 3) for digitizing the position of a light beam from, for example, the mirror of a mirror galvanometer a plurality of fibres 24, 25; 26, 27; 28, 29; connected to photo-cells 23 are positioned behind a mask 30 so that the light from the mirror 20 falls on to some of the fibres, the ...

Improvements in or relating to digitisers

... 1,141,472. Selective signalling. DECCA Ltd. 19 Sept., 1967 [20 June, 1966], No. 22676/66. Heading G4H. From two D.C. signals representing sin and cos, where O###/4, a digital representation of is obtained by applying sin to the tops of seven potential dividers 71 . . . 77, Fig. 7, and - cos to the bottoms, the dividers being so proportioned that the first provides a positive voltage at its tapping point if > #/ 32 , the second a positive voltage if > #/ 16 , the third a positive voltage if > 3#/ 16 , and so on, and by providing pure binary output signals D4, D5, D6 indicative of the number of positive output signals provided. The complete system described operates over a range of 2#. Three bits representing the octant in which the angle lies are produced by considering the signs of the sine and cosine signals and their relative magnitudes. These bits are then used to control gates 61, 62 ... 68 so that the sine and cosine signals are applied to the potential dividers in such a ...

Digitiser

... 1,149,250. Selective signalling. HOLLANDSE SIGNAALAPPARATEN N.V. 8 March, 1966 [12 March, 1965], No. 57427/68. Divided out of 1,149,249. Heading G4H. The system described in the parent Specification is modified in that a reversible counter is used for the coarse counter, and in that, as a consequence, it is not necessary to give the coarse counter an initial negative bias. The claims relate to this feature.

Analog-to-Digital Converters

... 1,168,047. Analogue/digital converters. SINGER-GENERAL PRECISION Inc. 18 June, 1968, No. 29026/68. Heading G4H. An analogue input signal E (Fig. 3) is fed to analogue-todigital converter 43 which delivers a coarse digital value, this digital signal being converted to analogue form Eb and the difference of the two signals E - Eb after amplification being fed to the same analogue-to-digital converter 43 to form a fine digital signal. In the embodiment described when a reference ramp signal on conductor 67 crosses zero a flip-flop 75 is set to enable a gate 81 to pass clock pulses to a counter 47 and to close a switch 77 so that the analogue signal E and the ramp signal are compared, a comparator amplifier 69 resetting flip-flop 75 to terminate the count of clock pulses when the signals are equal. The count in counter 47 is then transferred to a six-stage register 49 controlling switches 87 in a digital/analogue converter 50 so that the analogue signal Eb is fed to amplifier 89. Amplifier ...

Improvements in or relating to Voltage Generators

... 1,192,706. Staircase wave generators, tuning radio receivers. C.I.T. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 29 Aug., 1968 [4 Sept., 1967], No. 41288/68. Headings H3P and H3Q. [Also in Division G4] A circuit for generating a voltage variable stepwise to selectable values comprises means for producing a preselected number of pulses, each pulse occupying a time period ito in a pulse repetition period Nto, where i has a maximum value of N, means for averaging the pulses so as to produce a smooth D.C. output signal of value proportional to i and means for changing the integer i so as to vary stepwise the output signal. High frequency pulses from 21 step-up a counter 13 (of capacity N) until it reaches the value i set into a similar counter 11 whereupon a coincidence detector 12 produces a pulse which switches over a bi-stable circuit 16 to terminate the output at its upper terminal and via its lower terminal to close the gate 22. A similar counter 14 of capacity N operating in parallel ...

APPARATUS FOR ANALOG-TO-DIGITAL CONVERSION OF PHYSICAL VALUES AND THEIR RATIOS

... 1307334 Electric measurement PENZENSKY POLITEKHNICHESKY INSTITUT 7 July 1970 32831/70 Heading G4A The Specification describes apparatus for converting to digital form various physical values, e.g. time intervals, electric pulse durations, electric frequencies, phase shift angles of two waves and ratios of time intervals. In the embodiment of Fig. 3 for measuring a time interval t x defined by the interval between two pulses, a coarse counter 25 counts n 0 pulses of period T 0 from an oscillator 23 between the two pulses to derive the coarsest digit. The second pulse enables an oscillator 26 which delivers pulses of period T 0 -.1T 0 to a comparator 28, the comparator receiving on its other input pulses of period T 0 and length . 1T 0 . A second counter 34 counts n 1 pulses from oscillator 23 between the second pulse and a pulse produced by the comparator 28 at coincidence of its two inputs to derive a second digit. The comparator output enables an oscillator 26 delivering pulses at period ...

WAVE FORM SYNTHESIZERS

... 1366872 Function generators; waveform generators MARCONI CO Ltd 26 Aug 1971 [15 Oct 1970] 49437/70 Headings G4G and G4H [Also in Division H4] An approximation to a sine wave is produced from a digital output by weighting and combining n equal-amplitude rectangular waveforms where n is 2 or more, the waveforms exhibiting respectively during a time 0 to # (e.g. over half the period of the resultant sine wave), changes in the same direction at times 0, #/2n, 2#/2n, 3#/2n...and changes in the opposite direction at times #, (#-#/2n), (#-2#/2n), (#-3#/2n) ... The drawings show the waveforms for n = 4 (Fig. 2) and the resultant stepped waveform (Fig. 3) which is produced when the waveforms are weighted according to the amplitudes shown and then combined. The stepped waveform may be expressed as a Fourier series which is given in the Specification. The waveforms may be synthesized in a logic circuit 4 (details not described) fed by the four most significant outputs of a 13-bit counter 2. The waveforms ...

Improvements relating to a method and corresponding devices for the transmission of signals by coded pulses

... 662,823. Pulse code modulation circuits. LIBOIS, L. J., and GLOESS, P. F. M. July 25, 1949 [July 27, 1948], No. 19558/49. Classes 40 (v) and 40 (vi). Time or duration modulated pulses are converted to code pulse groups by causing each pulse to initiate N signal waves of period T/20, T/21, T/22... T/2n-1, where N is the number of possible code pulses in a group and T is the maximum modulation time interval, the waves being analysed at a fixed time and code pulses being generated if the individual waves present a predetermined characteristic, e.g. polarity, when the analysis takes place, the code pulses being staggered in time to form a group. The signal waves may be sinusoidal in character or may consist of pulse trains. In one embodiment, the input pulses 4, Fig. 3, have their leading edge modulated in time, the trailing edge 9 being fixed, and the circuit produces 3-element code groups. The pulse 4, after a delay of T/8 in line 20, is applied to cut-off ...

SEMICONDUCTOR STORAGE DEVIC3

... 1407152 Integrated circuits NIPPON GAKKI SEIZO KK 31 July 1972 [31 July 1971 (2) 1 Sept 1971 22 Nov 1971 (3)] Divided out of 1406691 Heading H1K [Also in Division H3] The storage medium of an integrated semiconductor analogue store consists of a diffused resistive track with a plurality of tapping points, representing analogue values, which are selectively connected to an output terminal via switches operated in response to signals from read-out circuitry. The switches may be bipolar transistors or JUGFETs but as described are IGFETs the drains of which are constituted by side branches from the track and the sources of which are interconnected by a diffused strip. The gates may be connected to the terminals of read-out circuitry via a matrix of diffused tracks and deposited aluminium strips interconnected at selected intersections in accordance with fixed information to be stored. A suitable MOS circuit producing read out pulses at its terminals in a predetermined order in response to a ...

Methods of and apparatus for converting digital signals

A method for converting a digital data into an NRZI-coded digital signal is disclosed which is carried out by the steps of first detecting if the value of every even numbered bit of the digital data is digital zero, second detecting if two bits of the detected even numbered bits having digital zero value and a preceding odd numbered bit have a DC component, producing a detecting signal according to the result of the second detecting; and converting the digital data into the NRZI-coded digital signal by using the detecting signal. An apparatus for converting a digital data into an NRZI-coded digital signal is also disclosed which includes a first means for detecting if the value of every even numbered bit of the digital data is digital zero, a second means for detecting if two bits of the detected even numbered bits having digital zero value and a preceding odd numbered bit have a DC component, a means for producing a detecting signal according to the result of the second detecting, and ...

ANALOGUE SIGNAL PROCESSING SYSTEM

... 1,253,978. Analog/digital converter. MICRO CONSULTANTS Ltd. 11 Nov., 1969 [20 Nov., 1968], no. 54996/68. Heading G4H. In an analogue/digital converter of the type in which the unknown analogue input current I 0 is successively modified by subtracting reference currents I 1 , I 3 , I 5 a current detector detects the direction of flow of current after each modification and controls the application of a current I 2 (equal to I 1 ), I 4 (equal to I 3 ) if the flow is negative. Each detector also supplies a digital output bit in accordance with the direction of current flow. In the embodiment of Fig. 1 I 1 = 2I 3 = 4I 5 so that the output is binary coded. A binary coded output may also be obtained by using equal current sources and feeding the current through an amplifier of gain 2 before each modification (Fig. 4, not shown). The currents I 2 , I 4 are fed via transistor or diode switches controlled by the current detectors 1, 2 which are preferably differential amplifiers.

APPARATUS FOR MEASURING NON-ELECTRICAL QUANTITIES

... 1326589 Electric selective signalling MOSKOVSKY ORDENA LENINA ENERGETICHESKY INSTITUT 8 Dec 1970 58188/70 Heading G4H A non-electric variable, e.g. displacement or temperature, is digitized by applying it to an A.C. energized transducer 1, Fig. 1, and digitizing the resulting output voltage in such a way that variations in supply voltage are compensated for, this being effected in two phases each lasting for one half-cycle of the supply. In the first phase switches 8 and 9 are closed and the output voltage from the transducer 1, and the output voltage from a second transducer 2 having the same supply but with its non-electric input held constant, are integrated in integrators 6, 12 and 7, 13 respectively. (Figs. 2a and 2c show the output voltage U from the transducer 1 and the output U, from integrator 6, 12). In the second phase switches 8 and 9 are opened, so that the outputs of the transducers remain steady, and the output U 2 from the second integrator 7, 13 is progressively attenuated ...

DIGITAL VOLTMETER

... 1392050 A/D Converters C MICHEL 19 July 1972 [20 July 1971] 33732/72 Heading G4H Apparatus for supplying a digital measurement of a continuously variable voltage which is affected by A.C. interference comprises a comparator 7 to which are fed the unknown voltage at an input 4 and a voltage derived via A/D converter 8 representing the count at a counter 1, 2 the difference voltage then being applied to both inputs of an AND gate 11 controlling a clock 5, firstly through a threshold device (not shown) and secondly through an integrator 13- 15 and then through a second threshold device (not shown), the outputs of each threshold device also being taken via respective inverters 16, 17 as inputs of a second AND gate 12 controlling a clock 6, the arrangement being that while both inputs 11A, 11B at gate 11 are activated, i.e. when the instantaneous and the integrated difference outputs from 7 are greater than the threshold level, the counter is incremented by the clock 5 and while AND gate 6 is ...

ANALOGUE TO DIGITAL CONVERTERS

... 1373803 Analogue to digital converters NORMALAIR-GARRETT (HOLDINGS) Ltd 9 Oct 1972 [14 Oct 1971] 47892/71 Heading G4H An. analogue to digital converter comprises an oscillator for generating clock pulses, a voltage controlled oscillator for generating pulses at a frequency proportional to a first input signal Vin, a switch S1 for feeding the output of either oscillator to a frequency to voltage converter, a second switch S2 for enabling the output of the frequency to voltage converter to be compared with the first input signal to control the voltage controlled oscillator or with a second input signal Vref. to control the value of the conversion factor in the frequency to voltage converter and a third switch S3 for holding the factor at a particular value during an analogue to digital conversion and for adjusting the factor during calibration of the converter. During the calibration period the ganged switches S1-S3 are in the positions shown and the output voltage Vm of a track and hold ...

Improvements in or relating to decoding equipment

... 1,039,342. Selective signalling systems. STANDARD TELEPHONES & CABLES Ltd. April 10, 1964 [April 17, 1963], No. 15070/63. Heading G4H. A digital-to-analogue converter produces an output voltage representing a ten-bit binary signal from a six-bit contracted floating point representation. If the most significant 1 of the 10-bit number is in the most significant position of that number, the exponent is represented by binary 7, and for other positions the exponent is correspondingly less, taking the value zero when the most significant 1 is in one of the three least significant positions of the 10Àbit number. The remaining three bits of the floating-point representation are the three bits of the 10-bit number which follow the most significant 1 except when the exponent is zero, in which case the three least significant bits of the 10-bit number are all used. Bits 5-7 representing the numerical part selectively open gates 15, 17, 18 supplied by binaryweighted constant current sources. A further ...

Improvements in or relating to tuning arrangements for voltage tunable circuits

... 1,065,907. Digital-to-analogue converters. TELEFUNKEN PATENTVERWERTUNGS G.m.b.H. Dec. 17, 1965 [Dec. 19. 1964], No. 53667/65. Heading G4H. A tuning arrangement for a voltage tunable circuit comprises a digital counter (Fig. 4, not shown) which makes a count representing the frequency of the oscillator (1), and means (6a-6e) for converting each decade value to an analogue form for comparison with a similar signal representing the desired frequency, the comparator outputs (5a, 5o1-5e, 5e1) causing resistors to be switched into the charging circuits of capacitor 3 to control the frequency of the oscillator. The desired frequency is stored in digital storage units (9a-9e) and converted (8a-8e) to an analogue comparison signal. The arrangement is such that an error output on one of the comparators operates a high or low switch (So, Sa1 &c.) the effect of which is to change the frequency to remove -the error.

Digital to analogue voltage converter

... 1,087,503. Selective signalling. RENWELL INDUSTRIES Inc. Feb. 1, 1966, No. 4296/66. Heading G4H. In a non-linear digital-to-analogue converter resistors 18, 20 ... 34 are selectably connectable in parallel either across one arm 14 of a bridge or across one resistor (14) of a potential divider (Fig. 2, not shown) and the arrangement is such that the output voltage approximates either to the sine or the cosine of the input number. In the preferred embodiment transistors are used as switches.

Corpuscle sorter

... 1,103,190. Electrostatic separators. UNITED STATES ATOMIC ENERGY COMMISSION. 1, Feb., 1966 [4, June, 1965], No. 4344/ 66. Heading B2J. [Also in Division G1] In an. apparatus for sorting particles suspended in a liquid, a jet of the liquid is broken into a regular train of droplets by accoustic pulses and a sensor 29 measures a selected characteristic of each particle that passes it and causes an electrostatic charging collar 37 to charge each droplet in accordance with the measured characteristic of any particle it may contain. Electrostatic deflecting plates 39, 41 then direct each droplet into an appropriate collecting vessel or onto an appropriate portion of a moving strip of blotting paper. The selected characteristic may be size, radioactivity, fluorescence, luminescence, electrical conductivity, or light transmissibility. or reflectivity. The particle concentration should be such that about one in seven droplets will contain a particle and the collar 37 should charge one or more droplets ...

Variable gain amplifier and circuits using same

... 1,138,640. A/D converters. INTERNATIONAL STANDARD ELECTRIC CORP. 17 June, 1966 [24 June, 1965], No. 27103/66. Heading G4H. The input analogue signal is applied in push-pull to a pair of differential amplifiers Q3, Q4 and Q5, Q6, Fig. 2, which are supplied by a constant current source Q0 via switching transistors Q1, Q2 and provide push-pull outputs O, O1, amplitude compression being achieved by selectively switching out amplifier Q3, Q4 to alter the overall gain. With both amplifiers Q3, Q4 and Q5, Q6 operative the system has a high gain, but if the associated coder, described below, determines that the signal thus amplified, i.e. OO1 lies outside a given range, a control signal C is generated to switch off Q1 to reduce the overall gain. Several amplifier sections could be used to provide several different input/output characteristics under control of several bits of the coder output. The coder comprises a comparator DSC, Fig. 4, n, e.g. 6 circuits SNj, one for each binary ...

Closed loop proportional plus integral control system

... 1,148,490. Automatic control. INTERNATIONAL BUSINESS MACHINES CORP. Dec. 21, 1966 [Jan.17, 1966 (5)], No.57205/66. Heading G3R. In a closed-loop proportional plus integral control system, the controlled variable is sampled at one rate and compared with a reference value to produce the proportional component which is sampled at a lower rate and the samples integrated to produce the integral component. In Fig. 1, a plurality of variables of a process 20 are measured by separate transducers 22 the outputs of which are applied in succession by a channel selector 25 to an analogue to digital converter 26. Numbers of pulses corresponding to the magnitude of the variable are produced by a ramp generator in the converter during each sampling period and supplied to a register 28. A group of pulses corresponding in number to the appropriate desired value or set point of the variable being sampled is produced from a recirculating memory store 30 by a read circuit 31 and subtracted from the count in ...

Method and device for the linear interpolation of fine divisions

... 909,644. Electric selective signalling systems. BUDNICK, G. A. A. Feb. 19, 1959 [Feb. 24, 1958], No. 5755/59. Class 40 (1). In a system for measuring relative displacement using MoirÚ fringes produced by slightly inclined diffraction gratings extra pulses are interpolated between successive fringe patterns in order to give greater precision. In Fig. 1, three photo-cells 5, 6, 7 are arranged between a pair of adjacent fringe patterns in such a way that as the diffraction gratings are moved a grating width relative to each other one of the fringe patterns moves successively over the three cells, thereby producing three pulses and increasing the resolution normally obtained by a pair of diffraction gratings by a factor of three. Where the diffraction gratings are part of a system so designed that the gratings should be moving at a constant relative speed, the extra pulses can be inserted electronically. Thus by using pulses produced by sensing the fringe patterns with a single cell to trigger ...

Интегральный датчик перегрева ключа

Полезная модель относится к коммутационной технике и может быть использована в качестве встроенного устройства контроля управления силовым ключевым устройством. Технический результат заключается в точном контроле перегрева тепловыделяющего кристалла ключевого МОП транзистора, расположенного на одном кристалле с сенсором.Для достижения данного технического результата встроенный температурный датчик, формирователь опорного напряжения, аналоговый компаратор сигналов и схема управления затвором МОП транзистора выполнены в едином КМОП базисе и располагаются на одном кристалле с ключевым МОП транзистором, при этом настройка и регулировка температуры перегрева устанавливаются посредством дополнительного вывода. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 180 943 U1 (51) МПК H02H 9/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК G01K 7/00 (2006.01); H01L 27/00 (2006.01); H03M 1/00 (2006.01); H02H 9/00 (2006.01); H03K 17/00 (2006.01) (21)(22) Заявка: 2017132135, 13.09.2017 13.09.2017 (73) Патентообладатель(и): Акционерное общество "Протон" (АО "Протон") (RU) Дата регистрации: 02.07.2018 (56) Список документов, цитированных в отчете о поиске: RU 2244936 C2, 20.01.2005. RU (45) Опубликовано: 02.07.2018 Бюл. № 19 1 8 0 9 4 3 R U (54) ИНТЕГРАЛЬНЫЙ ДАТЧИК ПЕРЕГРЕВА КЛЮЧА (57) Реферат: Полезная модель относится к коммутационной формирователь опорного напряжения, технике и может быть использована в качестве аналоговый компаратор сигналов и схема встроенного устройства контроля управления управления затвором МОП транзистора силовым ключевым устройством. Технический выполнены в едином КМОП базисе и результат заключается в точном контроле располагаются на одном кристалле с ключевым перегрева тепловыделяющего кристалла МОП транзистором, при этом настройка и ключевого МОП транзистора, расположенного регулировка температуры перегрева на одном кристалле с сенсором. устанавливаются посредством дополнительного Для достижения ...

Receiver with Orthogonal Beam Forming Technique

A receiver with orthogonal beam forming technique is achieved that is capable of differentiating different signal components within the received composite signal. An adaptive processor is used to eliminate the signal component whose phase information is known or can be calculated. The phase information of the major component of a signal can be easily acquired by using a limiter. The phase information of other signal components can be acquired by their direction information and other characteristics, such as modulation scheme, etc. Multiple orthogonal beams can be formed by eliminating one unwanted signal component each time by the adaptive processor until all unwanted signal is eliminated. Thus, a composite signal from multiple sources can be broken down into their component signals.

Semiconductor device

There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

Hearing aid with audio codec and method

A hearing aid comprising a time domain codec. The codec comprises a decoder adapted to generate a decoded output signal based on an input quantization index and an encoder for generating an output quantization index based on an input signal, said encoder comprising said decoder and a predictor receiving an excitation signal derived from said decoder output signal and outputting a prediction signal. The output quantization index is determined by repeated decoding of the quantization indices in order to minimize the error between the input signal and the prediction signal, and the predictor uses a recursive autocorrelation estimate for the error minimization. The invention further provides a method of encoding an audio signal.

Data look ahead to reduce power consumption

Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa. Eventually, the portions of the digital signal are provided to the sub-system so that the sub-system can respond to the portions of the digital signal.

Successive approximation register analog-to-digital converter

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Current-Mode Active Termination

Embodiments of the present invention, as further described below, provide active termination circuits that can be used with power transmitter circuits. Embodiments reduce power loss due to impedance matching and increase power efficiency in power transmitter circuits. In particular, embodiments provide active termination circuits that can be configured to draw minimal amounts of the output current generated by the power transmitter circuits. At the same time, embodiments achieve optimal impedance matching, thus enabling optimal power transfer to the load. Further, embodiments can be controlled adaptively in real time to reduce parasitic effects on power transfer and to optimize impedance matching. Embodiments can be implemented using various transistor technologies (e.g., MOSFET, BJT, etc.), and can be used with a variety of power transmitter circuits, including, for example, power DACs, analog/digital RF transmitters, and analog/digital PAs.

Solid-state image sensing device

A solid-state image sensing device according to the invention which can reduce an instantaneous current occurring in transferring image digital signals from analog-digital converters to registers to reduce noise sneaking into the analog-digital converters and a pixel array includes a pixel array, a vertical scanning circuit, a plurality of column ADCs, a plurality of registers, and control signal generation units. The control signal generation units are provided for respective groups into which the column ADCs and the registers disposed on one side of the pixel array are divided, and generate control signals of different timings, for respective units including at least one group, of transfer of converted image digital signals to the registers from the column ADCs operating in parallel.

PIPELINED ANALOG-TO-DIGITAL CONVERTER

An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage. 1. An analog-to-digital converter (ADC) , comprising:a stage including an amplifier including an input and an output; anda plurality of copies of a circuit block, each copy of the circuit block including at least one capacitor,wherein, for a clock cycle that drives the ADC,the plurality of copies of the circuit block operate interleavingly in a plurality of modes, the plurality of modes including a pre-gain mode and a gain mode,the copies of the circuit block in the pre-gain mode are decoupled from the amplifier, andthe copies of the circuit block in the gain mode are coupled to the amplifier to produce an output signal for a following stage.2. The ADC of claim 1 , wherein the plurality of modes further includes at least one of a sample mode and a reset mode.3. The ADC of claim 2 , wherein claim 2 , for the clock cycle claim 2 , the circuit block in the sample mode receives an input signal that is supplied to a first capacitor to charge the first capacitor with the input signal claim 2 , and wherein the input signal is supplied to an input of a flash during the sample mode.4. The ADC of claim 3 , wherein the circuit block in the pre-gain mode regenerates a comparator in the flash claim 3 , drives a second capacitor in a digital-to-analog converter (DAC) based on an output of the comparator claim 3 , and distributes voltage charges between the first and second capacitors of the circuit ...

Sensor Circuit for Concurrent Integration of Multiple Differential Signals and Operating Method Thereof

The present invention provides a circuit for concurrent integration of multiple differential signals. The circuit comprises a plurality of Stage 1 integration circuit arranged in array and a plurality of Stage 2 integration circuit arrange in array. Each of said Stage 1 integration circuit is configured to concurrently integrate an input signal to send out a Stage 1 positive signal and a Stage 1 negative signal which is reverse to said Stage 1 positive signal. Each of said Stage 2 integration circuit is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to said corresponding Stage 1 integration circuit to output a Stage 2 signal. 1. A circuit for concurrent integration of multiple differential signals , comprises:a plurality of Stage 1 integration circuit arranged in array, wherein each of said Stage 1 integration circuit is configured to concurrently integrate an input signal to send out a Stage 1 positive signal and a Stage 1 negative signal which is reverse to said Stage 1 positive signal; anda plurality of Stage 2 integration circuit arranged in array, wherein each of said Stage 2 integration circuit is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to said corresponding Stage 1 integration circuit to output a Stage 2 signal.2. The circuit of claim 1 , further comprises:a plurality of analog to digital converters arranged in array, wherein each of analog to digital converter converts a Stage 2 signal from a corresponding Stage 2 integration circuit to a digital signal.3. The circuit of claim 2 , wherein at least one of said plurality of analog to digital converters and corresponding Stage 2 integration circuit is a first successive ...

Method and System for Minimizing Variation of Converter Voltage Reference

A system for minimizing variation of a voltage reference includes a voltage reference generator and a power converter. The voltage reference generator is configured to generate a voltage reference from a supply voltage. The power converter, such as a flyback converter, is configured to supply an adjustable supply voltage to the voltage reference generator. The voltage reference generator generates the voltage reference from the adjustable supply voltage. 1. A system for minimizing variation of a voltage reference , the system comprising:a voltage reference generator configured to generate a voltage reference from a supply voltage; anda power converter configured to supply an adjustable supply voltage to the voltage reference generator;wherein the voltage reference generator generates the voltage reference from the adjustable supply voltage.2. The system of wherein:the power converter is further configured to adjust the adjustable supply voltage to account for external variations which would otherwise cause the voltage reference generator to generate the voltage reference with corresponding variations.3. The system of wherein:the power converter is a flyback converter.4. The system of wherein:the voltage reference generated by the voltage reference generator varies as a function of temperature variation of the voltage reference generator for a given supply voltage;wherein the power converter is configured to adjust the adjustable supply voltage such that the voltage reference generated by the voltage reference generator does not vary in the presence of the temperature variation of the voltage reference generator.5. The system of wherein:the power converter is configured to convert an input voltage into the adjustable supply voltage and is further configured to adjust the adjustable supply voltage independent of variation of the input voltage.6. The system of wherein:the voltage reference generated by the voltage reference generator varies as a function of variation ...

Systems and Methods for Decimation Based Over-Current Control

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active.

SIGNAL CONVERTING APPARATUS OF POWER METERING SYSTEM, POWER METERING SYSTEM AND METHOD FOR SIGNAL-CONVERTING IN POWER METERING SYSTEM

The present invention relates to a signal converting apparatus of a power metering system, a power metering system and a method for signal-converting in a power metering system. In accordance with one embodiment of the present invention, there is proposed to a signal converting apparatus of a power metering system including a frequency shift unit for shifting a frequency(s) of at least one signal of sensed current and voltage signals by a shift frequency(s) so that the current and voltage signals have different frequency bandwidths, a signal coupling unit for coupling the current and voltage signals having different frequency bandwidths into one signal and an analog-digital convert unit for converting an analog signal coupled as said one signal into a digital signal(s). And also, a power metering system including the same and a method for converting a signal of the power metering system are proposed. 1. A signal converting apparatus of a power metering system comprising: a signal coupling unit for coupling the current and voltage signals having different frequency bandwidths into one signal; and', 'an analog-digital convert unit for converting an analog signal coupled as said one signal into a digital signal(s)., 'a frequency shift unit for shifting a frequency(s) of at least one signal of sensed current and voltage signals by a shift frequency(s) so that the current and voltage signals have different frequency bandwidths;'}2. The signal converting apparatus of a power metering system according to claim 1 , wherein the frequency shift unit shifts each of the sensed current and voltage signals by each of different shift frequencies.3. The signal converting apparatus of a power metering system according to claim 1 , wherein the current and voltage signals are 3-phase signals.4. The signal converting apparatus of a power metering system according to claim 1 , wherein the frequency shift unit consists of frequency synthesizers to generate frequency-shifted intermediate ...

STABILITY CORRECTION FOR A SHUFFLER OF A SIGMA-DELTA ADC

A sigma-delta analog-to-digital converter (“ΣΔ ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ΣΔ ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ΣΔ ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler. 1. A second order shuffler , comprising:a first set of N accumulators, each first accumulator to receive corresponding digital-to-analog converter (DAC) unit element selection signals, each to accumulate values representing the corresponding selection signals and to generate corresponding first accumulator output values;a first corrector provided for the first accumulators to compress a range of the first accumulator output values for each first accumulator while maintaining context of each first accumulator with reference to the other first accumulators;a second set of N accumulators, each second accumulator to receive corresponding first accumulator output values, each to accumulate the corresponding output values and to generate corresponding second accumulator output values;a second corrector provided for the second accumulators to compress a range of the second accumulator output values for each second accumulator while maintaining context of each second ...

Low power slope-based analog-to-digital converter

Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.

INPUT CONVERTER FOR A HEARING AID AND SIGNAL CONVERSION METHOD

In order to minimize noise and current consumption in a hearing aid, an input converter including a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage includes an amplifier (Q) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (C, C, C, C). The invention further provides a method of converting an analog signal. 1. A sigma-delta converter converting an analog signal into a digital signal , and comprising:an input transformer receiving an input voltage and outputting a transformed voltage to a summation point;an integrator integrating a voltage present in the summation point;a comparator comparing an output from the integrator with a predetermined threshold and outputting a logical level in accordance with the comparison; anda feedback loop coupling a feedback signal back to the summation point;wherein said input transformer includes a switchable capacitor configuration.2. The converter according to claim 1 , wherein the input transformer includes at least two capacitors claim 1 , a plurality of switching elements and control logic claim 1 , and wherein the control logic switches the input transformer between a first and a second phase of operation.3. The converter according to claim 2 , wherein said plurality of switching elements and control logic is configured to arrange said ...

MULTI-PRIORITY ENCODER

A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input. 117-. (canceled)18. A multi-priority encoder comprising:a highest-priority single-priority encoder configured to indicate only a first match output signal corresponding to a first match line input signal; andone or more lower-priority single-priority encoders arranged in descending priority order, each configured to indicate only a lower-priority match output signal corresponding to a lower-priority match line input signal,wherein each of the single-priority encoders is comprised of at least as many single-priority stages as there are match line input signals, the single-priority stages being arranged in descending order, each stage having an arrangement of switching transistors configured to receive a match line input signal and to link the received match line input signal and an enable signal to a next lower priority single-priority stage.19. The multi-priority encoder of claim 18 , further comprising a NOR gate whose inputs include the match line input signal and a constant voltage signal and which is configured to link the received match line input signal and the enable signal to the a next lower priority single-priority stage.20. The multi-priority encoder of claim 19 , wherein the constant voltage signal is input to the NOR gate using one of the ...

SIGNAL RECEIVING DEVICE AND ELECTRONIC APPARATUS USING THE SAME

A signal receiving device and an electronic apparatus using the same are provided. The signal receiving device includes a signal conversion unit, a signal analysis unit, and an impedance unit. The signal conversion unit receives an analog input signal and converts the analog input signal into a digital input signal. The signal analysis unit receives the digital input signal and analyzes a signal characteristic thereof to generate an impedance adjustment signal. The impedance unit coupled to the signal analysis unit and a signal input terminal of the signal receiving device receives the impedance adjustment signal to dynamically adjust an input impedance of the signal input terminal. Thereby, the signal receiving device analyzes an input signal to dynamically adjust the input impedance of the signal receiving device, so as to maintain an amplitude gain of the input signal to be within a limited input range of the signal receiving device. 1. A signal receiving device , comprising:a signal conversion unit, receiving an analog input signal and converting the analog input signal into a digital input signal;a signal analysis unit, coupled to the signal conversion unit, receiving the digital input signal, and analyzing a signal characteristic of the digital input signal to generate an impedance adjustment signal; andan impedance unit, coupled to the signal analysis unit and a signal input terminal of the signal receiving device, and receiving the impedance adjustment signal to dynamically adjust an input impedance of the signal input terminal.2. The signal receiving device according to claim 1 , wherein the signal analysis unit comprises:a gain analysis module, receiving the digital input signal, and analyzing an amplitude gain of the digital input signal relative to a predetermined signal to generate a digital impedance signal; anda digital-to-analog conversion module, coupled to the gain analysis module, receiving the digital impedance signal, and converting the digital ...

SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD OF ANALOG TO DIGITAL CONVERSION

An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. 1. An analog to digital converter , comprising:a digital to analog converting circuit configured to sample and hold an analog input signal, and convert digital output data to an analog signal to generate a hold voltage signal;a comparator configured to compare the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal; anda signal processing circuit configured to perform successive approximation based on the comparison output voltage signal to generate the digital output data.2. The analog to digital converter of claim 1 , wherein the comparator comprises:a first comparator configured to compare the hold voltage signal with the reference voltage signal in response to a first clock signal to generate a first comparison output voltage signal; anda second comparator configured to compare the hold voltage signal with the reference voltage signal in response to a second clock signal having a phase opposite to a phase of the first clock signal to generate a second comparison output voltage signal.3. The analog to digital converter of claim 2 , wherein the comparison output voltage signal is a signal in which the first comparison output voltage signal and the second comparison output voltage signal are added alternately.4. The analog to ...

Analog to digital converter

An analog to digital converter generating a number of corresponding voltages in response to a number of values of a grey level is provided. The analog to digital converter includes a decoder and an operational amplifier. The decoder provides first to third output voltages having the same level when w most significant bits (MSBs) of the grey level correspond to the same value, provides first and second intermediate voltages in response to the x MSBs next to the w MSBs when the w MSBs correspond to different values, and selectively has the first to the third output voltages equal to one of the first and the second intermediate voltages. The operational amplifier obtains a pixel voltage by interpolating the first to the third output voltages, wherein the sum of w and x is smaller than or equal to the bit number of the gray level.

Da-converter and test apparatus

A DA conversion apparatus comprising a DA converting section that includes a plurality of analog elements; and a control section that generates first shift data and second shift data by shifting the input digital data by respective shift amounts of M bits and N bits, and controls the analog elements based on the first shift data and the second shift data, wherein the control section changes a control state for each of the common analog elements according to the bit shift amounts M and N in the control section, between at least two control states including a control state in which the common analog element is controlled according to higher-order bits of the first shift data and a control state in which the common analog element is controlled according higher-order bits of the second shift data.

SEMICONDUCTOR INTEGRATED CIRCUIT AND IMAGE SENSOR

According to one embodiment, a semiconductor integrated circuit is configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal. The semiconductor integrated circuit includes m (m is an integer greater than or equal to 2) first capacitors and second capacitors. Each of the m capacitors has a first electrode and a second electrode, and the first electrodes are connected to each other. Each of the m second capacitors has a third electrode and a fourth electrode, and the third electrodes are connected to each other. The semiconductor integrated circuits further includes: a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; and a logic circuit configured to generate the digital signal based on a comparison result of the comparator. 1. A semiconductor integrated circuit configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal , the semiconductor integrated circuit comprising:m (m is an integer greater than or equal to 2) first capacitors, each of which comprises a first electrode and a second electrode, the first electrodes being connected to each other;m second capacitors, each of which comprises a third electrode and a fourth electrode, the third electrodes being connected to each other;a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; anda logic circuit configured to generate the digital signal based on a comparison result of the comparator,wherein the first analog voltage is inputted into the first electrode,the second analog voltage is inputted into the third electrode, andone of a ground voltage and substantially ½ of a voltage of an input voltage range of the semiconductor integrated circuit is inputted into each second electrode and each fourth electrode.2. The circuit of claim 1 , whereinonly two switches are connected to each second electrode ...

SWITCHING SCHEME FOR ISI MITIGATION IN DATA CONVERTERS

Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node. 120-. (canceled)21. A method of mitigating inter-symbol interference in a tri-level digital to analog converter (DAC) , comprising:receiving, at the tri-level DAC, a digital data signal;converting the digital data signal into an analog signal in at least one tri-level unit element by switching within the tri-level unit element based on the digital data signal, wherein the inter-symbol interference generated by the conversion is independent of the digital data signal; andoutputting the analog signal.22. The method of claim 21 , further comprising:receiving a clock signal, andcontrolling the switching based on the clock signal.23. The method of claim 22 , wherein the switching occurs multiple times in a clock cycle.24. The method of claim 21 , wherein the inter-symbol interference generated by the conversion is substantially the same as in a preceding conversion.25. The method of claim 21 , further comprising:receiving a current from a current source,wherein the switching includes switching the current to an output based on the digital data signal.26. The method of claim 25 , ...

Integrating A/D Converter

In an integrating A/D converter, first and second reference voltage inputs () alternatingly connect through a reference voltage switch () via a first reference resistor (R) to an inverting input () of an integrator (). A comparator () connected downstream of the integrator () compares a test voltage applied to its test voltage input () with a comparator reference voltage applied to its reference voltage input (). This input () is connected to the output () of the integrator (). A control device () actuates the first reference voltage switch () in a pulsed manner and measures the time intervals between the individual switching processes. An inverter () inverting a measuring voltage (U) and a first heating resistor (R) coupled thermally with a measuring resistor (R), are connected in series between the measuring voltage input () and the output of the first reference voltage switch (). 1. An integrating analog-to-digital (A/D) converter , comprising:a measuring voltage input for an analog measuring voltage, which is connected via a measuring resistor to an inverting input of an integrator,a first reference voltage input for a first reference voltage and a second reference voltage input for a second reference voltage,a first reference voltage switch configured to alternatively connect the first and the second reference voltage inputs via a first reference resistor to the inverting input of the integrator,a comparator connected downstream of the integrator and configured to compare a test voltage applied to a test voltage input of the comparator with a comparator reference voltage applied to a reference voltage input of the comparator, wherein the comparator test voltage input is connected to an output of the integrator,a control device configured to actuate the first reference voltage switch in a clocked manner and to measure time intervals between individual switching processes, andan inverter configured to invert the measuring voltage and a first heating resistor ...

LOW POWER ANALOG TO DIGITAL CONVERTER

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal. 1. An apparatus comprising:a reference generator to provide a reference voltage;a sigma-delta modulator coupled to the reference generator, wherein the sigma-delta modulator is to receive an analog signal; anda finite state machine (FSM) coupled to an output of the sigma-delta modulator, wherein the FSM is to provide a digital code representing the analog signal.2. The apparatus of claim 1 , wherein the sigma-delta modulator comprises an amplifier and a circuit for performing auto zero correction of the amplifier.3. The apparatus of claim 2 , wherein the sigma-delta modulator comprises a chopper which is operable to cancel common-mode noise from the amplifier.4. The apparatus of claim 2 , wherein the amplifier and the circuit are part of an integrator.5. The apparatus of claim 2 , wherein the amplifier comprises an inverter.6. The apparatus of comprises a first multiplexer coupled to the reference generator.7. The apparatus of claim 6 , wherein the first multiplexer is controlled by an input of the FSM.8. The apparatus of claim 6 , wherein the first multiplexer is to selectively provide one of the reference voltage or a digital bit to a first switch.9. The apparatus of claim 8 , comprises a first capacitive device coupled to the first switch and the amplifier.10. The apparatus of claim 9 , comprises a second switch to receive the analog signal claim 9 , wherein the second switch is coupled to the first capacitive device.11. The apparatus of comprises a third switch coupled to an output of the amplifier and the second switch.12. The apparatus of comprises:a fourth switch coupled to the second switch; anda second capacitive device coupled in ...

SYSTEMS AND METHODS OF ELEMENT SCRAMBLING FOR COMPENSATION AND CALIBRATION OF ANALOG-TO-DIGITAL CONVERTER FEEDBACK

An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal. 1. An apparatus comprising: the scrambler element generates at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value;', 'for each of one or more of the possible quantization values, the scrambler element is configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal; and', 'responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element changes the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal., 'a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having ...

Adjustable and buffered reference for adc resolution and accuracy enhancements

An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

Multi-signal realignment for changing sampling clock

An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

Master-slave controller architecture technical field

Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.

Efficient Front End Module

Example aspects of the present disclosure are directed to front end modules for use in communication systems. In one example aspect, a front end module can include a receive path. The receive path can include a low noise amplifier. The receive path can include an analog to digital converter (ADC) circuit operable to receive an analog signal from the low noise amplifier and convert the analog signal to a digital RF receive signal. The receive path can include an ADC post processing circuit operable to process the digital RF receive signal in the digital domain. The front end module can include a transmit path. The transmit path can include a digital to analog converter circuit operable to convert the digital RF transmit signal to an analog RF transmit signal. The transmit path can include a power amplifier. 1. A front end module comprising: a low noise amplifier operable to receive an RF signal from an antenna;', 'an analog to digital converter (ADC) circuit operable to receive an analog signal from the low noise amplifier and convert the analog signal to a digital RF receive signal;', 'an ADC post processing circuit operable to process the digital RF receive signal in the digital domain;', 'a digital down converter circuit operable to convert the digital RF receive signal to a digital baseband receive signal;, 'a receive path, the receive path comprising a digital up converter circuit operable to convert the digital baseband transmit signal to a digital RF transmit signal;', 'a digital to analog converter circuit operable to convert the digital RF transmit signal to an analog RF transmit signal;', 'a power amplifier configured to provide the analog RF transmit signal to the antenna., 'a transmit path, the transmit path comprising2. The front end module of claim 1 , wherein the ADC circuit is operable to convert analog RF signals across a span of about 800 MHz or greater in the 5 GHz band.3. The front end module of claim 1 , wherein the ADC circuit is a gigabit ADC ...

DIGITAL-TO-ANALOG CONVERTERS HAVING MULTIPLE-GATE TRANSISTOR-LIKE STRUCTURE

Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples. 1. An integrated circuit comprising:a body including semiconductor material;a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material;a first gate electrode at least above the body, the first gate electrode including one or more metals; anda second gate electrode at least above the body, the second gate electrode including one or more metals, the second gate electrode distinct from the first gate electrode, the second gate electrode within 20 nanometers (nm) of the first gate electrode.2. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes indium.3. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes gallium.4. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes one of arsenic claim 1 , phosphorous claim 1 , or antimony.5. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes ...

Delta/sigma modulator

According to one embodiment, a delta/sigma modulator includes a first multiplier based on a reference capacitor having capacitance C R and a first variable capacitor having capacitance C S1 according to a distance between electrodes thereof, the first multiplier being defined by a first multiplier factor given by C R /C S1 and being supplied with a reference voltage, a second multiplier based on a second variable capacitor having capacitance C S2 and a third variable capacitor having capacitance C S3 , the second multiplier being defined by a second multiplier factor given by C S3 /C S2 and being provided in a feedback path, and an adder configured to add an output of the first multiplier and an output of the second multiplier, wherein C S1 , C S2 and C S3 are the same.

DRIVING CIRCUIT AND DATA TRANSMITTING METHOD

A driving circuit includes channels, a positive converting unit, a negative converting unit, an input switch, and an operational amplifier. A first digital data and a second digital data are alternatively transmitted in a first channel and a second channel. The positive converting unit and negative converting unit are respectively disposed in first channel and second channel and convert first digital data and second digital data into a positive analog data and a negative analog data. A first input terminal and a second input terminal of operational amplifier are respectively in first channel and second channel. After input switch respectively transmits positive analog data and negative analog data to first input terminal and second input terminal or to second input terminal and first input terminal, positive analog data and negative analog data are transmitted in a channel of the channels corresponding to entering operational amplifier. 1. A driving circuit , comprising:a plurality of channels, comprising a first channel and a second channel, wherein a first digital data and a second digital data are alternatively transmitted in the first channel and the second channel;a positive converting unit, disposed in the first channel, for converting the first digital data into a positive analog data;a negative converting unit, disposed in the second channel, for converting the second digital data into a negative analog data;an input switch, coupled to the positive converting unit and the negative converting unit; andan operational amplifying module, coupled to the input switch, wherein a first input terminal and a second input terminal of the operational amplifying module are disposed in the first channel and the second channel respectively;wherein the input switch transmits the positive analog data and the negative analog data to the first input terminal and the second input terminal respectively or to the second input terminal and the first input terminal respectively ...

Cell site architecture that supports 5g and legacy protocols

In modern networks, RRU and BBU equipment of an access point site typically handles traffic from a single sector. An RRU-BBU pair process that traffic (often limited to a single spectrum from a single sector) according to implemented capabilities and other equipment located further upstream perform functions that rely on information from multiple sectors. An integrated device (e.g., white box) can integrate the functionality of multiple RRU (or NR in 5G) and the functionality of multiple BBU (or DU/CU splits in 5G), which can reduce implementation footprint, costs, and can provide related services more efficiently without going upstream.

INTEGRAL A/D CONVERTER AND CMOS IMAGE SENSOR

The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit. 1. An integral type Analog/Digital (AD) converter comprising:a comparator configured to compare a reference voltage of a ramp waveform linearly changed according to a passing of time with an input voltage and output a comparison signal for the reference voltage and the input voltage;a multi-phase clock generation circuit configured to generate a plurality of clock signals including a main clock signal and clock signals having phases different from that of the main clock signal;a delay adjustment circuit configured to delay the comparison signal output from the comparator by a time period longer than one period of the main clock signal, and output the delayed comparison signal;a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit, based on the signals output from the delay adjustment circuit and the main clock signal, and output the counted result as a high order bit; anda time to digital converter configured to latch the plurality of clock signals generated by the multi-phase ...

SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER

Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. 1. A system for providing a pipelined Analog-to-Digital Converter , comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal;', 'at least two reference capacitors that are charged to a reference voltage;', 'at least two sampling capacitors that are charged to a sampling voltage; and', 'a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage., 'a first multiplying Digital-to-Analog Converter (MDAC) stage comprising2. The system of claim 1 , wherein the first MDAC stage further comprises a first current source coupled to a first of the at least two reference capacitors and a ...

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS)

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. 120-. (canceled)21. An analog-to-digital converter (ADC) , comprising:a comparator comprising an analog input, a reference input, a preemption input, a codeword output, and a validation output, a codeword on the codeword output of the comparator comprising one or more overlapping redundant bits, wherein if a preemption is indicated at the preemption input, the validation output is set to indicate the preemption and one or more bits of the codeword are set to a particular value, and wherein if a preemption is not indicated at the preemption input, the validation output is set to indicate a valid decision and one or more bits of the codeword are set according to a comparison between the analog input and the reference input;a digital-to-analog converter (DAC) comprising a codeword input and a reference output, wherein the reference output of the DAC is operably coupled to the reference input of the comparator and the codeword input of the DAC is operably coupled to the codeword output of the comparator; anda timer operable to set a preemption output ...

ANALOG-TO-DIGITAL CONVERTER

In some examples, a system comprises an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal. The system comprises a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal. The system includes a first capacitor, coupled to the DAC, to receive the internal analog signal. The system comprises a first switch, coupled to the first capacitor, to provide the analog input signal to the first capacitor. The system comprises a second switch to couple the first capacitor to ground. 1. A system comprising:an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal;a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal;a buffer;a first capacitor, coupled to an output of the buffer, and an output of the DAC;a first switch, coupled between the buffer outut and the first capacitor; anda second switch to couple the first capacitor to ground;a second capacitor coupled between an input to the buffer and ground; anda third switch, coupled to the buffer, the second capacitor, and the ADC, to provide the analog input signal to the buffer, the second capacitor, and the ADC while the reset signal is in an asserted state,the first switch to provide the analog input signal to the first capacitor while the second switch is in a closed state, and the reset signal is in a deasserted state, andthe DAC to provide the internal analog signal to the first capacitor while the first switch is in an open state and the second switch is in an open state.2. The system of claim 1 , wherein the first and second switches are both controlled by a switch signal.3. The system of claim 2 , wherein the first capacitor is to output a modified analog signal based on the received internal analog ...

DOUBLE DATA RATE TIME INTERPOLATING QUANTIZER WITH REDUCED KICKBACK NOISE

A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core. 1. An apparatus comprising:a first double data rate comparator circuit configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the first double data rate comparator circuit;a second double data rate comparator circuit configured to determine a relative voltage of a second differential input signal during each of the rising edge and the falling edge in the single clock cycle of the comparator clock input to the second double data rate comparator circuit;a third double data rate comparator circuit configured to determine a relative voltage of a third differential input signal during each of a rising edge and a falling edge in the single clock cycle of an inverted comparator clock input to the third double data rate comparator circuit; anda first floating voltage reference circuit configured to shift a voltage of a differential comparator input signal by a first fixed amount, and produce the first differential input signal;a second floating voltage reference circuit configured to shift the differential comparator input signal by a second fixed amount and produce the second differential input signal; anda clock inverter circuit connected to the comparator ...

Analog-digital converter

AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.

KICKBACK COMPENSATION FOR A CAPACITIVELY DRIVEN COMPARATOR

An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference. 1. An analog-to-digital converter (ADC) , comprising:a comparator having a first input and a second input;a voltage reference circuit having an output; a top plate coupled to the first input of the comparator; and', 'a bottom plate switchably coupled to the output of the voltage reference circuit;, 'a plurality of capacitors, each comprising, 'a first capacitive digital-to-analog converter (CDAC) comprising a top plate coupled to the second input of the comparator; and', 'a bottom plate switchably coupled to a ground reference., 'a plurality of capacitors, each comprising, 'a second CDAC comprising2. The ADC of claim 1 , wherein:the first CDAC comprises a first plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the first CDAC to the output of the voltage reference circuit;the second CDAC comprises a first plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the second CDAC to the ground reference.3. The ADC of claim 2 , wherein:the first CDAC comprises a second plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the first CDAC to the ground reference;the second CDAC comprises a second plurality of switches, each of the switches configured to ...

PROGRAMMABLE GAIN APMPLIFIER (PGA) EMBEDDED PIPELINED ANALOG TO DIGITAL CONVERTERS (ADC) FOR WIDE INPUT FULL SCALE RANGE

A method of incorporating Programmable Gain Amplifier (PGA) function into pipelined ADC for wide input range. The power consumption is saved without adding extra stage to reduce input range. The ADC input range can be adjusted on the fly using resistor bank and capacitor bank to achieve optimal system performance. 1. A Programmable Gain Amplifier (PGA) embedded pipelined ADC for wide input range , comprising:a configuration of 1PstP stage and 2PndP stage coupled together;a gain stage before the 1PstP stage Flash ADC;sampling capacitors in specific ratio;a shared OPAMP between two stages; andmultiple associated switches operating in two clock phases, wherein one OPAMP amplifier is shared by two pipelined stages, the operating phase is determined by internal built-in switches of the amplifier, wherein two differential input pairs couples to one tail current source and one folded cascoded gain stage, each differential pair is enabled at specific clock phase.2. The PGA embedded pipelined ADC of claim 1 , wherein a specific portion of the sampling capacitors are connected to a common-mode voltage and other sampling capacitors are connected to inputs signal.3. The PGA embedded pipelined ADC of claim 1 , wherein the ratio of sampling capacitors can be programmed to adjust the input range for obtaining optimal ADC linearity performance.4. The PGA embedded pipelined ADC of claim 1 , wherein the gain stage before 1PstP stage Flash ADC can be programmed to adjust the input range for obtaining optimal ADC linearity performance.5. The PGA embedded pipelined ADC of claim 1 , wherein the gain stage is implemented using resistor divider claim 1 , capacitor divider or R/C in parallel divider.6. The PGA embedded pipelined ADC of claim 1 , wherein the gain stage is implemented using adjustable resistor bank or adjustable capacitor bank to fine-tune the pipelined ADC input range on the fly for obtaining optimal system performance.7. (canceled)8. (canceled)9. (canceled) As the ...

Decision Feedback Equalizer

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Pulse generator of image sensor and method of driving the same

A pulse generator of an image sensor includes a delay cell including a plurality of transistors arranged in series between a power voltage and a ground, a stabilization capacitor, and a stabilization switch. The power voltage is supplied to a first terminal of a first transistor disposed first among the plurality of transistors, and a gate terminal of the first transistor is connected to a first node. An input voltage is supplied to a gate terminal of an n-th transistor disposed last among the plurality of transistors, and a ground voltage is supplied to a first terminal of the n-th transistor. The stabilization switch is disposed between a reference voltage input terminal providing a reference voltage and the first node. The stabilization switch is turned on by an input bias control signal to supply the reference voltage to the first node.

METHOD AND DEVICE FOR USE IN ANALOG-TO-DIGITAL CONVERSION

Disclosed herein are embodiments of a precharge sample-and-hold circuit. The circuit has an input terminal, a reference voltage terminal and an output terminal. Further, the circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal and configured to provide the sample voltage when said sample-and-hold circuit is in a holding mode and a cancellation capacitance. Implementations of a precharge sample-and-hold circuit and of methods to operate a precharge sample-and-hold circuit in an analog/digital converter are also disclosed.

DIGITAL-TO-ANALOG CONVERTER

A digital-to-analog converter (DAC) circuit includes a first DAC that produces a first analog output signal based upon a received multi-bit digital data and upon a received clock. A second DAC that produces a second analog output signal based upon the received multi-bit digital data and upon the received clock, wherein the first and second DACs are connected in parallel and process the same input signal comprising the multi-bit digital data. In one embodiment, the DACs produce differential signals. A low pass filter connected to receive the first and second analog outputs is configured to sum the first and second analog outputs and to filter the summed first and second analog outputs to produce an ingoing analog signal. An amplifier connected to receive the ingoing analog signal to produce an amplified ingoing analog signal. 1. A digital-to-analog converter (DAC) circuit , comprising:a first DAC that produces a first analog output signal based upon a received multi-bit digital data and upon a received clock;a second DAC that produces a second analog output signal based upon the received multi-bit digital data and upon the received clock, wherein the first and second DACs are connected in parallel and process the same input signal comprising the multi-bit digital data;a low pass filter connected to receive the first and second analog outputs and configured to sum the first and second analog outputs and to filter the summed first and second analog outputs to produce an ingoing analog signal; andan amplifier connected to receive the ingoing analog signal to produce an amplified ingoing analog signal.2. The DAC circuit of wherein the first and second DACs each produce differential first and second analog output signals claim 1 , respectively.3. The DAC circuit of wherein the low pass filter is configured to receive the differential first and second analog output signals sum and filter the differential first and second analog output signals to produce a differential ...

FAST BANDWIDTH SPECTRUM ANALYSIS

An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal. 120-. (canceled)21. An apparatus , comprising:a processor to generate control command signals, receive a digital data input signal, and analyze the digital data input signal;a Phase-Locked Loop Waveform Generator (PLLWG), coupled to the processor, to receive the control command signals and generate a charge pump output signal based on the control command signals;a Voltage Controlled Oscillator (VCO), coupled to the PLLWG, to receive a tuning signal based on the charge pump output signal and output a VCO output signal based on the tuning signal;a demodulator to receive an incoming modulated signal and the VCO output signal, and output an in-phase analog data signal and a quadrature analog data signal based on the incoming modulated signal and the VCO output signal;an image reject circuit to receive the in-phase analog data signal and the quadrature analog data signal and sum the in-phase analog data signal and the quadrature analog data signal into the analog output signal; andan Analog-to-Digital Converter (ADC) to convert the analog output ...

LOW-NOISE CURRENT-IN CLASS D AMPLIFIER WITH SLEW RATE CONTROL MECHANISM

A circuit applied to speaker includes a tri-level current DAC and a class D amplifier. The current DAC is arranged to receive a digital signal to generate a current signal, and the class D amplifier is arranged to directly receive the current from the current DAC and to amplify the current signal to generate an output signal. SNR performance is well improved class D amplifier due to small signal noise reduced by preceding tri-level DAC. In addition, the circuit further includes a driving stage, and a gate-drain voltage of a power transistor within the driving stage can be controlled to set the appropriate slew rate. 1. A circuit , comprising:a current digital-to-analog converter (DAC), for receiving a digital signal to generate a current signal; anda class D amplifier, coupled to the current DAC, for receiving the current signal from the current DAC and amplifying the current signal to generate an output signal.2. The circuit of claim 1 , wherein the class D amplifier has an integration stage claim 1 , and a common voltage applied to the pseudo-differential amplifier also serves as a common voltage of the current DAC.3. The circuit of claim 1 , wherein further comprising:a common voltage generator, coupled to the current DAC and the class D amplifier, for generating a common voltage to the current DAC and the class D amplifier.4. The circuit of claim 3 , wherein the class D amplifier has a pseudo-differential integration stage claim 3 , and the common voltage generator generates the common voltage to the current DAC and the class D amplifier according to a common voltage of reference voltages of the current DAC.5. The circuit of claim 1 , wherein the current signal comprises a first current signal and a second current signal claim 1 , and the class D amplifier comprises:a pseudo-differential integration stage comprising a first operational amplifier and a second operational amplifier, wherein a first node of the first operational amplifier is arranged to receive the ...

Device for converting analogue signals into digital signals

Method and device for converting analogue signals, of a plurality of pathways, into digital signals. A common circuit ( 2, 3 ) generates first analogue signals corresponding to high-order bits of digital signals For each pathway, a first means compares the first analogue signals with the signal to be converted. A first means ( 18 ) stores high-order bits corresponding to the value of a first analogue signal close to the signal to be converted. A means ( 9 ) stores the deviation between the analogue signal to be converted and said first detected value. A generator means ( 11, 12 ) generates a predetermined number of second analogue signals. A second means compares by successive approximations said second analogue signals with said deviation. A means ( 20 ) stores said low-order bits corresponding to the results arising from said second means of comparison. A means ( 22 ) assembles said high-order bits and said low-order bits.

IMAGING APPARATUS FOR DIAGNOSIS, METHOD OF CONTROLLING IMAGING APPARATUS FOR DIAGNOSIS, COMPUTER PROGRAM, AND COMPUTER READABLE STORAGE MEDIUM

A pulse signal corresponding to rotation of an imaging core is input, and a repetition frequency of the input pulse signal is converted in accordance with the number of radially-aligned lines of an ultrasound tomographic image. Based on the pulse signal of which the repetition frequency has been converted, a drive signal for an ultrasound transceiver is generated to obtain an ultrasound tomographic image with the number of lines. A valid pulse is determined in accordance with the number of lines from the pulse signal of which the repetition frequency has been converted. A signal having a pulse train selected, based on the valid pulse from a pulse signal representing a cycle of a light source of light for interfering with the light from an optical transceiver is generated as a pulse signal representing a timing of sampling of an optical coherence signal for generating an optical tomographic image. 1. An imaging apparatus for diagnosis configured to generate an ultrasound tomographic image and an optical tomographic image of a diagnosis target site of a subject using a catheter which rotatably accommodates an imaging core provided with an ultrasound transceiver configured to transmit and receive an ultrasound wave and an optical transceiver configured to transmit and receive light , the imaging apparatus for diagnosis comprising:a motor drive unit that is connected to the catheter and configured to rotate the imaging core;a converter configured to receive a pulse signal corresponding to rotation of the imaging core and to convert a repetition frequency of the pulse signal in accordance with a number of radially-aligned lines of the ultrasound tomographic image;a transmitting and receiving board configured to generate a drive signal for the ultrasound transceiver and to obtain an ultrasound tomographic image with the number of radially-aligned lines, based on a pulse signal of which the repetition frequency has been converted by the converter, and configured to ...

COMMON MODE REJECTION IN RESERVOIR CAPACITOR ANALOG-TO-DIGITAL CONVERTER

A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF−. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF−, can be used to provide any common mode charge to the input capacitors. 1. A differential digital-to-analog (DAC) circuit comprising: a pair of input capacitors configured to couple to a comparator;', control operation of a first set of switches to transfer a differential residue charge from the dedicated reference capacitor to the pair of input capacitors when setting the pair of input capacitors in a differential configuration based on a decision of the comparator; and', 'control operation of a second set of switches to transfer a common-mode residue charge from a reference voltage to set the pair of input capacitors when setting the pair of input capacitors in a common-mode configuration based on a decision of the comparator., 'a dedicated reference capacitor associated with the pair of input capacitors; and a control circuit configured to], 'a capacitor array including a number of DAC units, each DAC unit including2. The differential DAC circuit of claim 1 , wherein the input capacitors are bit-trial capacitors claim 1 , and wherein the control circuit configured to control operation of the first set of switches to transfer the differential residue charge from the dedicated reference capacitor to the pair of input capacitors when setting the pair of input capacitors in the differential configuration based on the decision of the comparator is configured to:control operation of the first set of switches to directly couple or cross-couple plates of the reference capacitor to a first plate of a first one of the pair of bit-trial capacitors and a first ...

PIPELINED ANALOG-TO-DIGITAL CONVERTER

The invention provides a pipelined analog-digital converter (ADC) and pertains to the technical field of integrated circuit (IC) design. The pipelined ADC at least comprises: a sampling holder, n multiplier digital-analog converters that are connected stage by stage, a clock generator, a reference generator and a digital encoder, wherein at least the sampling holder and n multiplier digital-analog converters are substantially arranged in a loop so as to form an intermediate area in an encircling manner; the clock generator and the reference generator are disposed in the intermediate area so that the clock generator and the reference generator respectively provide corresponding signal inputs to the surrounding n multiplier digital-analog converters in a star connection. The pipelined ADC has an excellent performance and is in particular applicable to high speed/high accuracy application. 1. A pipelined analog-digital converter (ADC) , at least comprising:n multiplier digital-analog converters that are connected stage by stage,a clock generator,a reference generator, anda digital encoder;characterized in that at least n multiplier digital-analog converters are substantially arranged in a loop so as to form an intermediate area in an encircling manner; the clock generator and the reference generator are disposed in the intermediate area so that the clock generator and the reference generator respectively provide corresponding signal inputs to the surrounding n multiplier digital-analog converters in a star connection;wherein n is an integer larger than or equal to 2.2. The pipelined ADC according to claim 1 , characterized in that the pipelined ADC further comprises a power bus for supplying power claim 1 , wherein the power bus is arranged substantially in a loop so as to surround therein the sampling holder and n multiplier digital-analog converters connected stage by stage.3. The pipelined ADC according to claim 2 , characterized in that the power bus is arranged in ...

Counter circuit, analog-to-digital converter, and image sensor including the same and method of correlated double sampling

A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

Adaptive quantization

An importance metric, based at least in part on an energy metric, may be determined for each of a plurality of received audio objects. Some methods may involve: determining a global importance metric for all of the audio objects, based, at least in part, on a total energy value calculated by summing the energy metric of each of the audio objects; determining an estimated quantization bit depth and a quantization error for each of the audio objects; calculating a total noise metric for all of the audio objects, the total noise metric being based, at least in part, on a total quantization error corresponding with the estimated quantization bit depth; calculating a total signal-to-noise ratio corresponding with the total noise metric and the total energy value; and determining a final quantization bit depth for each of the audio objects by applying a signal-to-noise ratio threshold to the total signal-to-noise ratio.

POWER CONVERSION DEVICE

A solar cell power conversion device is disposed between a solar cell and a consumer premises distribution system. A storage battery power conversion device is disposed between a storage battery and the consumer premises distribution system. When an AC effective voltage in the consumer premises distribution system deviates from a voltage range defined in accordance with dead zone information transmitted from HEMS, system voltage stabilization control for returning the AC effective voltage to fall within the voltage range is performed by control of active power and reactive power that are output from a first DC/AC conversion circuit and a second DC/AC conversion circuit. 1. A power conversion device disposed between a distributed power supply and an AC distribution system , the power conversion device comprising:an inverter to convert DC power output from the distributed power supply into AC power;a voltage measurement sensor to measure an AC voltage in the AC distribution system;an effective voltage calculator circuit to calculate an AC effective voltage in the AC distribution system from the AC voltage measured by the voltage measurement sensor;a voltage control target value generator to generate a voltage control target value for the AC distribution system from the AC effective voltage calculated by the effective voltage calculator circuit;a communication interface to transmit and receive data to and from outside the power conversion device; andan inverter controller circuit to control an output from the inverter, whereinwhen the AC effective voltage deviates from a voltage range defined to include the voltage control target value in accordance with dead zone information received by the communication interface, the inverter controller circuit controls an operation of the inverter to perform system voltage stabilization control for returning the AC effective voltage to fall within the voltage range by control of active power and reactive power that are output from ...

CONTROL OF SEMICONDUCTOR DEVICES

This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit () includes a first MOS device () and a bias controller (). The circuit is operable in at least a first circuit state (P) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V, V) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions. 1. A circuit comprising a first MOS device and a bias controller , wherein:the circuit is configured to be operable in a first circuit state in which the first MOS device is active to contribute to a first signal and a second circuit state in which the first MOS device does not contribute to the first signal;the bias controller is configured to be operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias to the first MOS device during an instance of the second circuit state, wherein the pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device to limit noise from the first MOS device during subsequent operation in the first circuit state; andthe bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.2. The circuit of wherein said one or more operating conditions comprise an operating condition that affects dynamics of charge carrier trapping by the ...

Multi-stage parallel super-high-speed ADC and DAC of logarithmic companding law

Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law has a voltage follower switch having zero voltage drop, and also has a lossless threshold switch group, wherein a quantization voltage of A/D conversion or D/A conversion is directly obtained through voltage-dividing resistance thereof. The ADC and DAC simplify a conversion process and reduce a conversion error. The ADC and DAC provide multi-stage multi-bit parallel super-high-speed A/D conversion and D/A conversion with logarithmic companding law of a high conversion rate and the low conversion error. 1. Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law , wherein the logarithmic ADDA comprises multi-sub-ADDAs , wherein at least one sub-ADDA comprises a stage-potential processing device , wherein the stage-potential processing device at stage λ comprising:{'sup': 'q', 'sub': λQ', 'λ(Q−1)', 'λ1', 'λ0', 'λ(Q−1)', 'λ1', 'λ0', 'λQ', 'p', 'λg', 'λg', 'λ(g+1)', 'λg', 'λZ', 'λQ', 'λZ', 'λ(G+1)', 'λZ', 'λG', 'λZ', 'λG', 'λG', 'λg', 'λZ', 'λg', 'λ(Q−1)', 'λ0', 'λG', 'λG', 'λG', 'λZ, 'a stage-potential generating module at stage λ which comprises a resistor chain for generating reference potential points and a potential stage determining circuit, wherein let Q=2, the q-bit reference potential points of the sub-ADDA at stage λ are formed by series connected Q resistors; the resistor chain of the series connected Q resistors provides Q+1 potential points V, V. . . V, V, among which V. . . V, Vare the Q step reference potential points at stage λ, wherein Vis equal to a power source anode V, and is excluded from the reference potential at step Q; let g be equal to some point whose subscript is within (0˜Q−1), point g is called a test point, and Vis the reference potential at step g stage λ; a quantization distance (also called a step difference) Δ=V−V; when a to-be-compared voltage Ufalls within a conversion range V˜0, there is always a point G correspondent to U, ...

Comparator for low-banding noise and cmos image sensor including the same

A comparator may include: a comparison block suitable for comparing a ramp signal and a pixel signal and outputting a comparison signal; and a gain acquisition and noise reduction block suitable for amplifying the comparison signal outputted from the comparison block to acquire a gain and reduce an occurrence of noise.

SINGLE TRANSDUCER AUDIO IN/OUT DEVICE

An audio in/out device includes an audible in/out transducer operable to convert an audible input signal to an audio receive (RX) signal and convert an audio transmit (TX) signal to an audible output signal. The audio in/out device further includes an audio receive/transmit (RX/TX) circuit operable to convert a digital TX signal to the audio TX signal for transmission to the audible in/out transducer, receive the audio RX signal from the audible in/out transducer, and convert the audio RX signal into a digital transmit/receive (Tx/Rx) signal. The digital Tx/Rx signal includes a representation of the audio RX signal. 1. An audio in/out device comprises: convert an audible input signal to an audio receive (RX) signal; and', 'convert an audio transmit (TX) signal to an audible output signal; and, 'an audible in/out transducer operable to a digital to analog converter module operable to convert the digital TX signal to an analog TX reference signal;', 'an operational amplifier operable to compare an audible in/out transducer voltage with the analog TX reference signal to a produce an analog comparison signal;', 'a feedback circuit operable to convert the analog comparison signal to an analog regulation signal;', 'a controlled source circuit operable to provide the audio TX signal to the audible in/out transducer based on the regulation signal, wherein the audio TX signal is adjusted based on the regulation signal in order to keep the audible in/out transducer voltage and the analog TX reference signal substantially matching; and', 'an analog to digital converter operable to convert the analog comparison signal to the digital Tx/Rx signal, wherein the digital Tx/Rx signal includes a representation of the audio RX signal., 'an audio receive/transmit (RX/TX) circuit including2. (canceled)3. The audio in/out device of further comprises: convert the digital Tx/Rx signal into a digital inbound signal in accordance with a desired inbound audio file format; and', 'convert a ...

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD OF CONTROLLING ANALOG-TO-DIGITAL CONVERTER

To reduce power consumption of a sequential comparison analog-to-digital converter. An analog-to-digital converter includes a sequential conversion unit, a determination unit, and a stop control unit. The sequential conversion unit is configured to sequentially generate a predetermined number of bits of a value corresponding to an analog signal when the analog signal is input. The determination unit is configured to determine whether a value of a digital signal including the predetermined number of bits is within a predetermined range whenever the bits are generated. The stop control unit is configured to stop the sequential conversion unit in a case in which the value of the digital signal is not within the predetermined range. 1. An analog-to-digital converter comprising:a sequential conversion unit configured to sequentially generate a predetermined number of bits of a value corresponding to an analog signal when the analog signal is input;a determination unit configured to determine whether a value of a digital signal including the predetermined number of bits is within a predetermined range whenever the bits are generated; anda stop control unit configured to stop the sequential conversion unit in a case in which the value of the digital signal is not within the predetermined range.2. The analog-to-digital converter according to claim 1 , a comparator configured to compare the analog signal to a reference signal and generate the bits on a basis of a result of the comparison, and', 'a reference signal control unit configured to update a value of the reference signal whenever the bits are generated., 'wherein the sequential conversion unit includes'}3. The analog-to-digital converter according to claim 1 , further comprising:an output control unit configured to output a determination result obtained by determining whether the value of the digital signal is within the predetermined range.4. The analog-to-digital converter according to claim 3 ,wherein the output ...

SUCCESSIVE-APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) WITH ULTRA LOW BURST ERROR RATE

Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment. 1. A method , comprising:applying analog-to-digital conversion, in a signal processing component, to an analog input via a plurality of successive conversion cycles, wherein each conversion cycle corresponds to a particular bit in a corresponding digital output;for each one of the plurality of successive conversion cycles, triggering a next one of the plurality of successive conversion cycles based on a cycle termination event;detecting meta-stability during each one of the plurality of successive conversion cycles;retaining information relating to result of said detecting of meta-stability during each conversion cycle until end of the analog-to-digital conversion;after completing all of the plurality of successive conversion cycles, assessing a meta-stability state based on retained information for results of all of the plurality of successive conversion cycles; andcontrolling the digital output based on the assessing.2. The method of claim 1 , wherein assessing meta-stability state of a conversion cycle is based on settling of a matching search for that conversion cycle.3. The method of claim 2 , comprising determining that ...

Distortion measurement and correction system and method

A method, computer program product, and computer system for determining a magnitude and phase of a spurious-free dynamic range component. A first signal and a second signal may be received from a first source operatively connected to a differential component. A first output associated with the first signal and a second output associated with the second signal may be nulled. The first signal and the second signal may be shorted. A second source operatively connected to the differential component may be disconnected. The first signal of the first source may be applied at a same phase as the second source with an additional phase delta, +Y o . A first differential residual signal may be measured using the first signal at the same phase as the second source with the additional phase delta, +Y o . The second signal of the first source may be applied at the same phase as the second source with an additional phase delta, −Y o . A second differential residual signal may be measured using the second signal at the same phase as the second source with the additional phase delta, −Y o . The magnitude and phase of the distortion component of the first source may be determined based upon, at least in part, the first and second differential residual signal.

CONTINUOUS-TIME OVERSAMPLING PIPELINE ANALOG-TO-DIGITAL CONVERTER

A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. 120-. (canceled)21. A pipelined analog-to-digital converter (ADC) , comprising: a delay unit to generate an analog input current signal representing a delayed version of an analog input voltage signal;', 'an encoder circuit including a plurality of encoders to generate a plurality of digital output signals based on the analog input voltage signal and a plurality of interleaved clock signals;', 'a decoder circuit including a plurality of decoders to generate a plurality of analog output current signals based on the digital output signals and the plurality of interleaved clock signals; and', 'a subtraction circuit to generate a residue signal based on the analog input current signal and at least one of the plurality of analog output current signals., 'at least one pipeline stage including22. The pipelined ADC of claim 21 , wherein the analog input current signal is delayed from the analog input voltage signal by a predetermined period of time.23. The pipelined ADC of claim 22 , wherein the predetermined period of time is based on a period of the plurality of interleaved clock signals.24. The pipelined ADC of claim 21 , wherein the analog input current signal is delayed from the analog input voltage signal by 1.5 times a period of the plurality of interleaved clock signals.25. The pipelined ADC of claim 21 , wherein each of the plurality of encoders generates a respective one of the plurality of digital output signals at a different time based on a respective different one ...

DOUBLE DATA RATE COUNTER, AND ANALOG-TO-DIGITAL CONVERTER AND CMOS IMAGE SENSOR USING THE SAME

A Double Data Rate (DDR) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an LSB control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections. 1. A Double Data Rate DDR counter , comprising:an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal; anda Least Significant Bit (LSB) control portion suitable for holding an LSB based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.2. The DDR counter of claim 1 , wherein the input clock control portion detects the state of a neighboring clock of the input clock based on a first edge of the counter enable signal and inverts or non-inverts the input clock based on a detected state of the neighboring clock.3. The DDR counter of claim 1 , wherein the input clock control portion includes:a counting section determination block suitable for receiving the input clock and the counter enable signal and determining a counting section;a clock sampling block suitable for sampling the state of the input clock based on the counter enable signal; anda first inversion/non-inversion block suitable for inverting or non-inverting an output of the counting section determination block based on a clock sampling result obtained from the clock sampling block and outputting the first clock to the LSB control portion.4. The DDR counter of claim 3 , wherein the input clock control portion further includes:a third inversion/non-inversion block suitable for inverting or non-inverting a cross-correlation double sampling output based on a control signal and outputting the counter enable signal.5. The DDR counter of claim 3 , wherein the counting section ...

DIGITAL DISCRETE-TIME NON-FOSTER CIRCUITS AND ELEMENTS

A method to implement circuits and circuit elements having one or more ports may include digitizing, using analog-to-digital converters, continuous-time input signals received from one or more ports of a circuit to form discrete-time input signals. At a digital signal processor, the discrete-time input signals are received and the discrete-time input signals are processed to calculate a desired discrete-time output signals. Using digital-to-analog converters, the calculated desired discrete-time output signal are calculated to form outputs of continuous-time output signals at the one or more ports of the circuit. The continuous-time output signals are output to the same one or more ports that receive the continuous-time input signals; and producing, thereby, a desired relationship between the continuous-time output signals and the continuous-time input signals at the one or more ports. 1. A method to implement circuits and circuit elements having one or more ports , comprising:digitizing, using analog-to-digital converters, continuous-time input signals received from one or more ports of a circuit to form discrete-time input signals;receiving, at a digital signal processor, the discrete-time input signals and processing the discrete-time input signals to calculate a desired discrete-time output signals;converting, using digital-to-analog converters, the calculated desired discrete-time output signal to form outputs of continuous-time output signals at the one or more ports of the circuit;outputting the continuous-time output signals to the same one or more ports that receive the continuous-time input signals; andproducing, thereby, a desired relationship between the continuous-time output signals and the continuous-time input signals at the one or more ports.2. The method of claim 1 , wherein the digital signal processor performs processing having functionality of at least one of convolution claim 1 , difference equations claim 1 , admittance matrices claim 1 , ...

Signal converter and method for operating a signal converter

In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.

DYNAMIC POWER SWITCHING IN CURRENT-STEERING DACS

Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit. 1. A method , comprising: the DAC circuit is configured to apply the conversion based on current steering; and', 'the DAC circuit is configured to incorporate use of dynamic power switching during current steering., 'applying digital-to-analog conversion to a digital input via a digital-to-analog converter (DAC) circuit, wherein2. The method of claim 1 , comprising applying the dynamic power switching via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage.3. The method of claim 2 , comprising configuring the secondary supply voltage to be less than a main supply voltage used in driving the current steering in the DAC circuit.4. The method of claim 2 , wherein the secondary section comprises at least one transistor element.5. The method of claim 4 , wherein the at least one transistor element comprises a NMOS transistor element claim 4 , PMOS transistor element claim 4 , and/or CMOS transistor element.6. The method of claim 1 , comprising applying the digital-to-analog conversion ...

Multi-zone data converters

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

ANALOG-TO-DIGITAL CONVERSION CIRCUIT, IMAGE SENSOR AND ANALOG-TO-DIGITAL CONVERSION METHOD

An analog-to-digital conversion circuit includes a first comparator, a second comparator and a counter circuit. The first comparator compares an analog signal with a ramp signal. The second comparator compares the analog signal with the ramp signal plus a predetermined offset. When a signal level of the ramp signal is less than a signal level of the analog signal, the counter circuit counts a number of clock cycles of a first clock signal to generate a first portion of a digital signal. When the signal level of the ramp signal plus the predetermined offset is greater than the signal level of the analog signal, the counter circuit counts a number of clock cycles of a second clock signal to generate a second portion of the digital signal. A frequency of the first clock signal is less than a frequency of the second clock signal. 1. An analog-to-digital conversion circuit for converting an analog signal into a digital signal , the analog-to-digital conversion circuit comprising:a first comparator, configured to compare the analog signal with a ramp signal to generate a first comparison signal;a second comparator, configured to compare the analog signal with the ramp signal plus a predetermined offset to generate a second comparison signal; anda counter circuit, coupled to the first comparator and the second comparator, wherein when the first comparison signal indicates that a signal level of the ramp signal is less than a signal level of the analog signal, the counter circuit is configured to count a number of clock cycles of a first clock signal to generate a first portion of the digital signal; when the second comparison signal indicates that the signal level of the ramp signal plus the predetermined offset is greater than the signal level of the analog signal, the counter circuit is configured to count a number of clock cycles of a second clock signal to generate a second portion of the digital signal; a frequency of the first clock signal is less than a frequency of ...

ANALOG-TO-DIGITAL CONVERSION WITH NOISE INJECTION VIA WAVEFRONT MULTIPLEXING TECHNIQUES

An analog-to-digital conversion system comprises a first processor, a bank of N analog-to-digital converters, and a second processor. The first processor is configured to receive M input signal streams, perform a wave-front multiplexing transform in analog domain on the M input signal streams and output concurrently N mixed signal streams, M and N being integers and N≧M>1. The wave-front multiplexing transform comprises a first set of wave-front vectors. The bank of N analog-to-digital converters is coupled to the first processor. The N analog-to-digital converters convert the N mixed signal streams from analog format to digital format and output concurrently N digital data streams. The second processor is coupled to the bank of N analog-to-digital converters. The second processor is configured to receive the N digital data streams, perform a wave-front de-multiplexing transform in digital domain on the N digital data streams and output concurrently N output data streams such that the N output data streams comprise M output data streams that correspond respectively to the M input signal streams. The wave-front de-multiplexing transform comprises a second set of wave-front vectors. 1. An analog-to-digital conversion system comprising:a first processor configured to receive M input signal streams, perform a wave-front multiplexing transform in analog domain on the M input signal streams and output concurrently N mixed signal streams, M and N being integers and N≧M>1, the wave-front multiplexing transform comprising first wave-front vectors;a bank of N analog-to-digital converters coupled to the first processor, the N analog-to-digital converters converting the N mixed signal streams from analog format to digital format and outputting concurrently N digital data streams; anda second processor coupled to the bank of N analog-to-digital converters, the second processor being configured to receive the N digital data streams, perform a wave-front de-multiplexing transform ...

Circuit for sensing an analog signal, corresponding electronic system and method

A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.

Switched Capacitance Converter

A system includes a first capacitor group to facilitate determination of a first bit, and a second capacitor group to facilitate determination of a second bit in combination with the first capacitor group. The system further includes a delayed clock switch to engage the second capacitor group after determination of the first bit. 1. A system , comprising:a first capacitor group to facilitate determination of a first bit;a second capacitor group to, in combination with the first capacitor group, facilitate determination of a second bit; anda delayed clock switch to engage the second capacitor group after determination of the first bit.2. The system of claim 1 , where the first bit comprises a most significant bit.3. The system of claim 1 , where the second bit comprises a least significant bit.4. The system of claim 1 , where the first capacitor group comprises a first capacitor paired with a second capacitor in the second capacitor group.5. The system of claim 4 , where the first capacitor has less capacitance than the second capacitor.6. The system of claim 4 , where the first capacitor is situated in parallel with the second capacitor.7. The system of claim 4 , further comprising a latch to drive the first and second capacitors.8. The system of claim 4 , where the first capacitor comprises a set of unitary capacitors situated in parallel.9. The system of where a first ratio of the capacitance of the first capacitor to the capacitance of the first capacitor group is similar to a second ratio of the capacitance of the first and second capacitors to the capacitance of the first and second capacitor groups.10. The system of claim 4 , further comprising a split-capacitance analog-to-digital converter; andwhere the first capacitor group further comprises a third capacitor with a capacitance equal to a capacitance of the first capacitor;where the first capacitor is configured to initialize in a logical high state; andwhere the third capacitor is configured to initialize ...

SEMICONDUCTOR DEVICE, ANALOG-TO-DIGITAL CONVERSION METHOD, ONBOARD SYSTEM, AND MEASUREMENT METHOD

There is provided a semiconductor device including: an integrator that repeats integrating a first reference voltage after integrating an analog signal; a comparator that compares an output of the integrator and a second reference voltage; a counter circuit that counts a first integration time determined to integrate the analog signal, and a second integration time until the output of the integrator reaches the second reference voltage from start of integration of the first reference voltage; a calculation circuit that calculates a digital value of the analog signal based on the first and the second integration times; a control circuit that performs control so that the analog signal is input to the integrator while the counter circuit counts the first integration time; and an integration time update circuit that updates the first integration time counted by the counter circuit based on the second integration time counted thereby. 1. A semiconductor device comprising:an integrator that repeats integrating a first reference voltage after integrating an analog signal;a comparator that compares an output of the integrator and a second reference voltage;a counter circuit that counts a first integration time determined to integrate the analog signal, and a second integration time until the output of the integrator reaches the second reference voltage from start of integration of the first reference voltage;a calculation circuit that calculates a digital value of the analog signal based on the first and the second integration times;a control circuit that performs control so that the analog signal is input to the integrator while the counter circuit counts the first integration time; andan integration time update circuit that updates the first integration time counted by the counter circuit based on the second integration time counted by the counter circuit.2. The semiconductor device according to claim 1 , whereinthe control circuit controls an input to the integrator so ...

Fractional-N All Digital Phase Locked Loop Incorporating Look Ahead Time To Digital Converter

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. 1. A look-ahead time to digital converter (TDC) for use in an all digital phase locked loop (ADPLL) , comprising:a plurality of controllable delay elements configured in a sequential chain configuration; anda phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a number of delay elements in said chain to function as a digital to time converter and a portion of a remainder of delay elements in said chain to function as a time to digital converter.2. The look-ahead time to digital converter according to claim 1 , wherein said plurality of controllable delay elements are operative to generate an output code representing a fractional portion of a phase error used by said ADPLL to adjust the frequency of the variable clock (CKV).3. The look-ahead time to digital converter according to claim 1 , wherein said phase prediction circuit is coupled to a fractional part of a frequency command word (FCW) signal.4. The look-ahead time to digital converter according to claim 3 , wherein said fractional part of FCW signal is accumulated at said FREF clock.5. A look-ahead time to digital converter (TDC) for use in an ...

Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. 1. A cyclic digital to time converter and time to digital converter (DTC-TDC) circuit for use in an all digital phase locked loop (ADPLL) circuit , comprising:a plurality of controllable delay elements configured in a cyclical sequential chain configuration;a phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a starting delay element in said chain, a first number of delay elements in said chain to function as a digital to time converter (DTC) and a second number of delay elements in said chain to function as a time to digital converter (TDC); andwherein said DTC and TDC elements are dynamically selected.2. The circuit according to claim 1 , wherein said the selection of said DTC and TDC elements is randomized thereby scrambling mismatches between said delay elements with a resultant reduction in fractional frequency spurs output by said ADPLL.3. The circuit according to claim 1 , wherein said plurality of controllable delay elements comprises a cyclic chain of inverter circuits.4. The circuit according to claim 1 , further comprising a dithering circuit operative to generate FREF dithering.5. The ...

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND SENSING METHOD

In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW a comparator for determining whether the value of an analog input signal exists within a predetermined range, an AD conversion circuit for converting the analog input signal to a digital signal in response to a common activation signal, and a CPU for processing the digital signal in response to the common activation signal. When the analog input signal does not exist within the predetermined rang, the comparator generates the common activation signal. Then, the CPU stores the piece of digital information corresponding to the digital signal as well as the piece of time information from the RTC into a storage circuit. 1. A semiconductor device comprising:a timer circuit for generating a piece of time information and a first activation signal which is flowing periodically;a determination circuit for determining whether the value of an analog input signal exists within a predetermined range, in response to the first activation signal;a first conversion circuit for converting the analog input signal to a digital signal, in response to a second activation signal; anda processing circuit for processing the digital signal converted by the first conversion circuit, in response to a third activation signal,wherein, when the analog input signal does not exist within the predetermine range, the determination circuit generates the second activation signal and the third activation signal,wherein the processing circuit stores a piece of digital information corresponding to the digital signal, as well as the piece of time information from the timer circuit, into a storage circuit.2. A semiconductor device according to claim 1 ,wherein the determination circuit is supplied with its operation voltage in response to the first activation signal,wherein the second activation signal and the third activation signal are used as a common ...

DIGITAL-ANALOG CONVERTER AND DIGITAL-ANALOG CONVERSION DEVICE

The DA converter according to the present invention includes: first and second analog segment units a plurality of capacitors of sampling capacitor groups charged according to signal levels of digital signals input in a sampling phase; and a calculation unit that outputs an analog signal according to a charged voltage of each capacitor of the sampling capacitor group of the first or second analog segment unit in an integral phase, wherein, when one analog segment unit of the first and second analog segment units is in the sampling phase, the other analog segment unit is in the integral phase. 1. A digital-analog converter comprising:a first analog segment unit including a first sampling switch group and a first sampling capacitor group, a plurality of capacitors of the first sampling capacitor group charged according to a signal level of a first digital signal in a sampling phase;a second analog segment unit including a second sampling switch group and a second sampling capacitor group, a plurality of capacitors of the second sampling capacitor group charged according to a signal level of a second digital signal in the sampling phase; anda calculation unit including an operational amplifier and an integration capacitor, the calculation unit outputting an analog signal according to a charged voltage of each capacitor of the first sampling capacitor group or a charged voltage of each capacitor of the second sampling capacitor group in an integral phase,wherein, when one analog segment unit of the first and second analog segment units is in the sampling phase, the other analog segment unit is in the integral phase.2. The digital-analog converter according to claim 1 ,wherein the first sampling switch group is switched such that the first analog segment unit is connected to an input terminal inputting the first digital signal and a reference voltage in the sampling phase, and the first sampling switch group is switched such that the first analog segment unit is ...

SYSTEM AND METHOD FOR PROVIDING SINGLE FIBER 4K VIDEO

Aspects of the subject disclosure may include, for example, a device that encodes digital signals representing image data captured by a video camera and provided according to a 4K ultra-high definition (4K-UHD) standard. The digital signals are transmitted as serial digital interface (SDI) streams to a wavelength-division multiplexing (WDM) unit; the WDM unit performs electrical-to-optical conversion of the SDI streams and outputs a multiplexed signal to a single fiber-optic cable. The video camera, encoding unit, and WDM unit form a combined module within a housing; the device connects to a proximal end of a single fiber-optic cable, and a distal end of the single fiber-optic cable is configurable for connection to a demultiplexer of a 4K-UHD video presentation device. The multiplexed signal is transmitted on the single fiber-optic cable unidirectionally from the proximal end to the distal end. Other embodiments are disclosed. 1. A device comprising:a processing system including a processor; anda memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations comprising:encoding a plurality of digital signals representing image data captured by a video camera, wherein the encoding is performed by an encoding unit coupled to the video camera; andtransmitting the digital signals to a wavelength-division multiplexing (WDM) unit coupled to the encoding unit, wherein the WDM unit performs electrical-to-optical conversion of the digital signals and outputs a multiplexed signal comprising a plurality of wavelengths to a cable connector,wherein the cable connector is configured for connecting to a proximal end of a single fiber-optic cable, a distal end of the single fiber-optic cable being configurable for connection to a demultiplexer of a video presentation device,wherein the multiplexed signal is transmitted on the single fiber-optic cable unidirectionally from the proximal end to the distal end,wherein the ...

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. 1. A method of an analog-to-digital converter , comprising:generating a digital reference code;converting the digital reference code to an analog reference voltage;comparing an analog input voltage to the analog reference voltage to obtain a comparison output;updating the digital reference code based on the comparison output; andafter repeating the converting, comparing, and updating up to a predetermined number of times, outputting the digital reference code as a digital output code representative of the analog input voltage, a first bit accuracy when the analog input voltage falls within a first voltage range, and', 'a second bit accuracy different than the first bit accuracy when the analog input voltage falls within a second voltage range., 'wherein the predetermined number of times results in the digital output code representing the analog input voltage to at least2. The method of claim 1 , wherein the predetermined number of times further results in the digital output code representing the analog voltage to at least a third bit accuracy different than the first and second bit accuracies when the analog input voltage falls within a third voltage range.3. The method of claim 1 , wherein:the first bit accuracy corresponds to a 1-LSB (least significant bit) accuracy; andthe second bit accuracy corresponds to a 2-LSB accuracy.4. The method of ...

Using a sampling switch for multiple evaluation units

In some examples, an integrated circuit device includes a sampling switch configured to sample an input signal. The integrated circuit device also includes a first evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The integrated circuit device further includes a second evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The sampling switch is configured to deliver the sampled input signal to the first evaluation unit and deliver the sampled input signal to the second evaluation unit.

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND METHOD OF ANALOG-TO-DIGITAL CONVERSION

An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. 1. An analog-to-digital converter , comprising: generate a reference voltage signal, the reference voltage signal changing in response to a comparator offset compensation signal,', 'sample and hold an analog input signal, and', 'perform a digital-to-analog conversion on digital output data to generate a hold voltage signal;, 'a digital-to-analog converting circuit configured to,'}a comparator configured to compare the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal;a comparator offset detector configured to generate the comparator offset compensation signal based on the comparison output voltage signal; anda signal processing circuit configured to perform analog-to-digital conversion using a successive approximation based on the comparison output voltage signal to generate the digital output data.2. The analog-to-digital converter of claim 1 , wherein the analog-to-digital converter is configured to claim 1 ,perform an analog-to-digital conversion on a comparator offset to generate the comparator offset compensation ...

ANALOG-TO-DIGITAL CONVERTER AND CONTROL CIRCUIT WITH A LOW QUIESCENT CURRENT AT LOW LOAD

A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator. 1. A circuit , comprising:a successive approximation register;an adjustable capacitor having a set input for setting a capacitance value of the adjustable capacitor;a comparator coupled to an input terminal of the adjustable capacitor, and at least one output coupled to an input of the successive approximation register; andan analog input coupled to a terminal of the adjustable capacitor,wherein the circuit is configured to operate in a first operating mode and a second operating mode, and wherein an output of the circuit is controlled by the successive approximation register in the first operating mode and the output of the circuit is not controlled by the successive approximation register in the second operating mode, the output of the circuit being controlled by an output of the comparator in the second operating mode.2. The circuit according to claim 1 , wherein the successive approximation register is disabled during the second operating mode.3. The circuit according to claim 1 , wherein the comparator comprises a plurality of comparators including a second comparator coupled to a terminal of the adjustable capacitor claim 1 , and a first ...

ENCODER AND APPARATUS HAVING THE SAME

An encoder includes a scale, a detector, and a processor. The processor executes a second process while executing a first process, calculates a first relative position of one of the scale and the detector to the other of the scale and the detector when a calculation of a relative position between them starts, and then calculates a second relative position of the one to the other based on a relative displacement amount between them and the first relative position. 1. An encoder comprising:a scale that has a first periodic pattern and a second periodic pattern that has a period longer than that of the first periodic pattern;a detector movable relative to the scale, andswitchable between a first detecting state in which the detector reads the first periodic pattern by changing a combination in a plurality of read elements and outputs a first signal having a changing period that depends on the first periodic pattern, and a second detecting state in which the detector reads the second periodic pattern and outputs a second signal having a changing period that depends on the second periodic pattern; anda processor configured to execute a first process for calculating a relative displacement amount between the scale and the detector by using one of the first signal and the second signal obtained from the detector that is set to one of the first detecting state and the second detecting state, and a second process for calculating a relative position of one of the scale and the detector relative to the other of the scale and the detector by using both of the first signal and the second signal obtained from the detector that is set to each of the first detecting state and the second detecting state,wherein the processor executes the second process while the processor executes the first process, the processor calculating a first relative position of the one to the other when a calculation of the relative position starts, and then calculating a second relative position of the one ...

ANALOG-TO-DIGITAL CONVERTER AND CLOCK GENERATION CIRCUIT THEREOF

An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal. 1. A clock generation circuit , comprising cascaded clock generation modules , the clock generation module at each stage being configured to generate a corresponding internal clock signal , and the clock generation module at each stage comprising a delay module and a logic gate module;{'sup': ['th', 'th'], '#text': 'an output terminal of a N-stage delay module being connected to an input terminal of a (N+1)-stage delay module, wherein an input terminal of a first-stage delay module is configured to input an external clock signal, and a frequency of the external clock signal is lower than a frequency of the internal clock signal;'}{'sup': ['th', 'th', 'th', 't', 'th', 'th'], '#text': 'each of the logic gate modules comprising a first input terminal, a second input terminal and an output terminal, the first input terminal of a N-stage logic gate module being connected to the output terminal of the N-stage delay module, the second input terminal of the N-stage gate module being connected to the output terminal of a (N−1)-stage logic gate module, and the output terminal of the N-stage logic gate module being configured to output a Ninternal clock signal, where N is larger than or equal to 2; and'}the first input terminal of a first-stage logic gate module being configured to input the external clock ...

MULTI-PATH ANALOG SYSTEM WITH MULTI-MODE HIGH-PASS FILTER

A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode. 152.-. (canceled)53. A system comprising:an input for receiving an input signal;an output for generating an output signal;a capacitor coupled between the input and the output;a resistance circuit coupled to the output and having a plurality of modes including a first mode in which a frequency transfer function of the system has a first high-pass corner frequency and a second mode in which the frequency transfer function of the system has a second high-pass corner frequency; and determine a difference between the input signal and the output signal; and', 'switch between modes of the plurality of modes when the difference is less than a predetermined threshold., 'control circuitry configured to54. The system of claim 53 , wherein the input claim 53 , the output claim 53 , the capacitor claim 53 , and the resistance circuit are arranged as a high-pass filter to generate the output signal as a high-pass filtered version of the input signal.55. The system of claim 54 , wherein: a first processing path configured to generate a first digital signal based on an analog input signal; and', 'a second processing path configured to generate a ...

ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND METHOD

An analog-to-digital conversion circuit and method are provided. At a sampling stage, the first capacitor array connects lower electrode plates of N capacitors to a first input voltage, connect lower electrode plates of the other capacitors to a common-mode voltage, and connect upper electrode plates of all the capacitors to the common-mode voltage to sample the first input voltage; in an iconversion at a conversion stage, the logic circuit controls, the lower electrode plate of an icapacitor to connect to a reference voltage or a ground voltage, a first comparison voltage output by the first capacitor array approximates a second comparison voltage; and the comparator stores a comparison result between the first and the second comparison voltage to an i+1flag bit in the logic circuit, and analog-to-digital conversion is completed when i+1 is equal to the total number of capacitors in the first capacitor array. 1. An analog-to-digital conversion circuit , comprising a first capacitor array , a logic circuit and a comparator; wherein:at a sampling stage, the first capacitor array is configured to connect lower electrode plates of N capacitors in the first capacitor array to a first input voltage, connect lower electrode plates of the other capacitors in the first capacitor array to a common-mode voltage, and connect upper electrode plates of all capacitors in the first capacitor array to the common-mode voltage to sample the first input voltage, wherein N is a positive integer less than a total number of the capacitors in the first capacitor array;{'sup': th', 'th', 'th, 'in an iconversion at a conversion stage, the logic circuit is configured to control, according to an istored flag bit, the lower electrode plate of an icapacitor in the first capacitor array to connect to a reference voltage or a ground voltage, such that a first comparison voltage output by the first capacitor array approximates a second comparison voltage, wherein i is a positive integer less than ...

LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR

In a system for converting digital data into a modulated optical signal, an electrically controllable device having M actuating electrodes provides and optical signal that is modulated in response to binary voltages applied to the actuating electrodes. A digital-to-digital converter provides a mapping of input data words to binary actuation vectors for M bits and supplies the binary actuation vectors as M bits of binary actuation voltages to the M actuating electrodes, where M is larger than the number of bits in each input data word. The digital-to-digital converter maps each digital input data word to a binary actuation vector by selecting a binary actuation vector from a subset of binary actuation vectors available to represent each of the input data words. 1. A optical modulation system , the system comprising:an input for a plurality of N digital input data bits;an input optical signal;a modulator for modulating the input optical signal responsively to the plurality of N digital input data bits to output a modulation of the input optical signal, thereby generating one or more modulated optical signal outputs for transmission over one or more optical fibers; andwherein a digital-to-digital mapping maps the plurality of N digital input data bits to a set of M digital output data bits associated with a plurality of voltage values;wherein the input optical signal is modulated based on the plurality of voltage values;wherein the digital-to-digital mapping comprises, for each digital input value included in a set of possible digital input values for the plurality of N digital input data bits, a set of corresponding output values from a set of possible digital output values;wherein, within the digital-to-digital mapping, for a first subset of successively increasing digital input values specified in the digital-to-digital mapping, deltas between numerical values of successive digital outputs in the set of digital output values corresponding respectively to the ...

SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER, CMOS IMAGE SENSOR INCLUDING THE SAME AND OPERATING METHOD THEREOF

A complementary metal oxide semiconductor (CMOS) image sensor includes a pixel array suitable for outputting a pixel signal corresponding to incident light; a row decoder suitable for selecting and controlling pixels in the pixel array by row lines; a tracking voltage generator suitable for generating a tracking voltage; a plurality of successive approximation register (SAR) analog-to-digital converters suitable for analog-to-digital converting a pixel signal by repeatedly performing N times (where N is a natural number representing desired resolution) a process of comparing the pixel signal generated by the pixel array with the tracking voltage generated by the tracking voltage generator and modulating the pixel signal; and a control unit suitable for controlling operations of the row decoder, the tracking voltage generator, and the plurality of SAR analog-to-digital converters. 1. A complementary metal oxide semiconductor (CMOS) image sensor comprising:a pixel array suitable for outputting a pixel signal corresponding to incident light;a row decoder suitable for selecting and controlling pixels in the pixel array by row lines;a tracking voltage generator suitable for generating a tracking voltage;a plurality of successive approximation register (SAR) analog-to-digital converters suitable for analog-to-digital converting a pixel signal by repeatedly performing N times (where N is a natural number representing desired resolution) a process of comparing the pixel signal generated by the pixel array with the tracking voltage generated by the tracking voltage generator and modulating the pixel signal; anda control unit suitable for controlling operations of the row decoder, the tracking voltage generator, and the plurality of SAR analog-to-digital converters.2. The CMOS image sensor of claim 1 , wherein claim 1 , during each of the repeated processes claim 1 , the tracking voltage generator generates a tracking voltage modulated from a tracking voltage of a preceding ...

HIGH-SPEED COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER

A comparator for an analog-to-digital converter is provided. The comparator includes a differential amplifier unit that receives a sampling signal and provides an output signal, based on a voltage provided by the sampling signal. The differential amplifier unit includes an input stage that receives the sampling signal and integrates a current on the integration nodes based on potentials of the sampling signal. The comparator includes a sense amplifier coupled with the integration nodes that detects a potential difference and amplifies the potential difference to generate the output signal. The comparator includes a charge injection circuit () to inject equal charges into the integration nodes. 1. An analog-to-digital comparator , comprising:a differential amplifier unit wherein the differential amplifier unit receives a sampling signal and provides an output signal based on a voltage provided by the sampling signal, wherein the differential amplifier unit includes:an input stage wherein the input stage receives the sampling signal and integrates a current on integration nodes based on potentials of the sampling signal;a sense amplifier coupled with the integration nodes wherein the sense amplifier detects a potential difference and amplifies the potential difference to generate the output signal; anda charge injection circuit wherein the charge injection circuit injects equal charges into the integration nodes.2. The comparator according to claim 1 , wherein the sense amplifier includes cross-coupled inverters.3. The comparator according to claim 2 , wherein one terminal of each of the cross-coupled inverters is coupled with a respective one of the integration nodes claim 2 , so that the voltage over the cross-coupled inverters depends on the potential on the respective integration node.4. The comparator according to claim 3 , wherein charges are selectively injected into the integration nodes before the voltage over the cross-coupled inverters reaches a value at ...

Analog-to-digital converter circuitry with offset distribution capabilities

Analog-to-digital converter (ADC) circuitry may receive multiple analog signals and output corresponding digital signals. During the conversion process, comparators may receive the analog signals and a ramp waveform and compare the two inputs to generate logic signals. The logic signals correspond to digital signals that are outputted by ADC circuitry. To enable offset distribution capabilities, offset distribution circuitry may be selectively coupled to the inputs of the comparators. The offset distribution circuitry may include switches that couples a voltage supply providing reference voltages to the comparators. The reference voltages may be conveyed via a capacitor to the comparators as offset voltages. The offset voltages may provide may be different for different ADC units to offset power consumption of different ADC units and reduce power surges in power sources coupled to ADC circuitry.

MIXED-SIGNAL CIRCUITRY

Mixed-signal circuitry, comprising: an array of ADC units configured to operate in a time-interleaved manner, and each operable in each of a series of time windows to convert an analogue input value into a corresponding digital output value, each conversion comprising a sequence of sub-conversion operations, each successive sub-conversion operation of a sequence being triggered by completion of the preceding sub-conversion operation; and a controller, wherein: at least one of the ADC units is operable to act as a reporting ADC unit and indicate, for each of one or more monitored said conversions, whether or not a particular one of the sub-conversion operations completed during the time window concerned; and the controller is operable to consider at least one such indication and to control the circuitry in dependence upon the or each considered indication. 1. Mixed-signal circuitry , comprising:an array of ADC units configured to operate in a time-interleaved manner, and each operable in each of a series of time windows to convert an analogue input value into a corresponding digital output value, each conversion comprising a sequence of sub-conversion operations, each successive sub-conversion operation of a sequence being triggered by completion of the preceding sub-conversion operation; anda controller,wherein:at least one of the ADC units is operable to act as a reporting ADC unit and indicate, for each of one or more monitored said conversions, whether or not a particular one of the sub-conversion operations completed during the time window concerned; andthe controller is operable to consider at least one such indication and to control the circuitry in dependence upon the or each considered indication.2. Mixed-signal circuitry as claimed in claim 1 , wherein the time windows for the ADC units are synchronised with one another claim 1 , and/or wherein the series of time windows for the respective ADC units are time-interleaved.3. Mixed-signal circuitry as claimed ...

CONTROL OF SEMICONDUCTOR DEVICES

This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (P) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V, V) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions. 1. A circuit comprising a first MOS device and a bias controller , wherein:the circuit is configured to be operable in a first circuit state in which the first MOS device is active to contribute to a first signal and a second circuit state in which the first MOS device does not contribute to the first signal;the bias controller is configured to be operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias to the first MOS device during an instance of the second circuit state, wherein the pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device to limit noise from the first MOS device during subsequent operation in the first circuit state; andthe bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.2. The circuit of wherein said one or more operating conditions comprise an operating condition that affects dynamics of charge carrier ...

METHOD AND CIRCUIT FOR NOISE SHAPING SAR ANALOG-TO-DIGITAL CONVERTER

An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a digital-to-analog (D/A) conversion circuit, a comparison circuit and a control circuit. The track-and-hold circuit is configured to output a first signal based on an input signal. The D/A conversion circuit is configured to generate a second signal based on an N-bit logical signal. The comparison circuit is configured to generate a comparison result based on the first signal and the second signal. The control circuit is configured to generate the N-bit logical signal according to N comparison results from the comparison circuit. 1. An analog-to-digital (A/D) conversion system , comprising:a track-and-hold circuit configured to output a first signal based on an input signal;a digital-to-analog (D/A) conversion circuit configured to generate a second signal based on an N-bit logical signal;a comparison circuit configured to generate a comparison result based on at least the first signal and the second signal; anda control circuit configured to generate the N-bit logical signal according to N comparison results from the comparison circuit.2. The A/D conversion system of claim 1 , further comprising:a coupling circuit configured to generate an error signal based on the first signal and the second signal.3. The A/D conversion system of claim 2 , further comprising:a loop filter configured to generate a filtered error signal based on the error signal, wherein the comparison circuit is further configured to generate the comparison result based on the first signal, the second signal and the filtered error signal.4. The A/D conversion system of claim 2 , further comprising:a switched buffer connected to the coupling circuit, the switched buffer configured to sample and hold the error signal, and the control circuit further configured to control a timing of the switched buffer.5. The A/D conversion system of claim 1 , wherein the control circuit is further configured to control a timing of the ...

VOLTAGE REGULATOR WITH LOAD COMPENSATION

A voltage regulation system provides a relatively stable voltage source without introducing the typical costs of a ground buffer. The disclosed voltage regulation system includes a voltage regulator that is operative to detect a change of the load current and regulate a current bypass mechanism to stabilize a total supply current. For example, the voltage regulator includes a current sensor and a current compensation circuit. The current sensor is configure to generate a current compensation signal based on the load current change, whereas the current compensation circuit is configured to adjust a bypass current in response to the current compensation signal. As a result, the bypass current dynamically compensates the load current change such that the ground voltage of a variable load becomes relatively stable over a range of load currents. 1. A reference voltage regulation (RVR) circuit for supplying a reference voltage across a variable load , the RVR circuit comprising:a first output node configured to deliver an output current to the variable load;a second output node configured to collect the output current from the variable load;a current compensation circuit coupled between the first and second output nodes, the current compensator circuit having a control terminal configured to receive a current compensation signal for adjusting a compensation current across the first and second output nodes via the current compensator circuit; anda current sensor coupled with the first and second output nodes to sense a change of the output current, the current sensor configured to generate the current compensation signal based on the sensed change of the output current.2. The RVR circuit of claim 1 , wherein the current sensor includes:a supply current path having a supply output node coupled with the first output node to deliver a supply current sustaining the output current and the compensation current; anda monitoring current path configured to deliver a monitoring ...

PIPELINE ADC AND REFERENCE LOAD BALANCING CIRCUIT AND METHOD TO BALANCE REFERENCE CIRCUIT LOAD

Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period. 1. A balancing circuit to balance a load of a reference circuit with an output that provides a reference voltage signal to a load circuit in first and second time periods (S , H) , the balancing circuit comprising:capacitors;a first circuit operative during the first time period to charge one or more of the capacitors using a voltage source; anda second circuit operative during the first time period to select one or more of the charged capacitors according to an expected load of the load circuit in the second time period;the first circuit operative during the second time period to connect the selected one or more capacitors to the output of the reference circuit.2. The balancing circuit of claim 1 , wherein the voltage source has a voltage greater than the reference voltage signal.3. The balancing circuit of claim 2 , wherein the first circuit includes:first switches to connect the one or more capacitors to the voltage source during the first time period, and to disconnect the one or more capacitors from the voltage source during the second time period; andsecond switches individually associated with a corresponding one of the capacitors, the individual second switches operative when a corresponding control signal is in a first state to selectively connect the corresponding capacitor to the output of the reference circuit, and the individual second switches operative when the corresponding control signal is in a second state to ...

ANALOG-TO-DIGITAL CONVERTER WITH NOISE SHAPING

An analog-to-digital converter (ADC) using an amplifier-based noise shaping circuit. The amplifier-based noise shaping circuit generates a noise shaping signal. A comparator of the ADC has a first input terminal coupled to an output terminal of a capacitive data acquisition converter that captures an analog input, a second input terminal receiving the noise shaping signal, and an output terminal for observation of the digital representation of the analog input. The amplifier-based noise shaping circuit uses an amplifier to amplify a residual voltage obtained from the capacitive data acquisition converter and provides a switched capacitor network between the amplifier and the comparator for sampling the amplified residual voltage and generating the noise shaping signal. 1. An analog-to-digital converter with noise shaping , comprising:a comparator, having a first input terminal coupled to an output terminal of a capacitive data acquisition converter that captures an analog input and a second input terminal receiving a noise shaping signal, and outputting a digital representation of the analog input at an output terminal; andan amplifier-based noise shaping circuit, generating the noise shaping signal, comprising:an amplifier, for amplifying a residual voltage obtained from the capacitive data acquisition converter, wherein the amplifier is a dynamic amplifier which is silent on static current; anda switched capacitor network, coupled between the amplifier and the comparator, for sampling the amplified residual voltage and generating the noise shaping signal.2. (canceled)3. The analog-to-digital converter with noise shaping as claimed in claim 1 , wherein:the amplifier-based noise shaping circuit further comprises a finite impulse response filter comprising the amplifier and the switched capacitor network.4. The analog-to-digital converter with noise shaping as claimed in wherein:the amplifier-based noise shaping circuit further comprises an infinite impulse response ...

METHOD AND APPARATUS FOR DIGITAL PRE-DISTORTION WITH REDUCED OVERSAMPLING OUTPUT RATIO

Certain aspects of the present disclosure are directed to a digital predistortion (DPD) device for use within a wireless transmitter that permits the use of a downstream digital-to-analog converter that operates at a clock rate close to the bandwidth of a digital baseband input signal. In some examples, a sampling rate of a digital baseband input signal is increased using an upsampler to obtain an increased rate digital input signal. Predistortion is applied to the increased rate digital input signal using a DPD device to obtain a predistorted digital signal. The sampling rate of the predistorted digital signal is then decreased using a downsampler to obtain a lower-rate predistorted digital signal with a sampling rate below the increased rate of the upsampler (e.g. close to the bandwidth of a digital baseband input signal). A low pass filter may be provided to filter out-of-band signal components from the predistorted digital signal. 1. An apparatus for wireless communications , comprising: generate a first signal with a first sampling rate by converting a second signal associated with a second sampling rate and reducing signal replicas resulting from the conversion by low pass filtering with a first cutoff ratio, the first sampling rate being higher than the second sampling rate;', 'generate a third signal by predistorting the first signal; and', 'generate a fourth signal with a third sampling rate by converting the third signal to the third sampling rate and reducing out-of-band signal components due to the conversion of the second signal by low pass filtering with a second cutoff ratio different than the first cutoff ratio, the third sampling rate being lower than the first sampling rate; and, 'a processing system configured toan interface configured to output the fourth signal for transmission.2. The apparatus of claim 1 , wherein the second signal is a digital baseband input signal claim 1 , the first signal is an increased rate digital input signal claim 1 , ...

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD OF CONTROLLING ANALOG-TO-DIGITAL CONVERTER

To reduce power consumption of an analog-to-digital converter in which a comparator is provided. An analog-to-digital converter includes a comparator and a mode control unit. The comparator is configured to generate a comparison result by comparing an analog signal to a threshold indicating a boundary of a predetermined range in a determination mode and convert the analog signal into a digital signal in a conversion mode. The mode control unit is configured to transition the determination mode to the conversion mode in a case in which the comparison result indicating that the analog signal is not within the predetermined range is generated. 1. An analog-to-digital converter comprising:a comparator configured to generate a comparison result by comparing an analog signal to a threshold indicating a boundary of a predetermined range in a determination mode and convert the analog signal into a digital signal in a conversion mode; anda mode control unit configured to transition the determination mode to the conversion mode in a case in which the comparison result indicating that the analog signal is not within the predetermined range is generated.2. The analog-to-digital converter according to claim 1 , comprising:a digital-to-analog conversion unit configured to generate a positive-side output signal and a negative-side output signal from the analog signal and a predetermined selection signal and output the positive-side output signal and the negative-side output signal to the comparator;a sequential comparison control unit configured to generate a predetermined control signal on a basis of the digital signal in the conversion mode; anda selection unit configured to select the predetermined threshold and supply the predetermined threshold as the predetermined selection signal to the digital-to-analog conversion unit in the conversion mode and to select the predetermined control signal and supply the predetermined control signal as the predetermined selection signal to ...

Kickback compensation for a capacitively driven comparator

An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

Method for amplifying an echo signal suitable for vehicle surroundings detection and device for carrying out the method

A method for amplifying an echo signal, in which an analog echo signal suitable for detection of a vehicle's surroundings is amplified by a gain dependent on the transit time of the echo signal, the analog echo signal being amplified by an amplifier having a plurality of outputs, each having a different gain, and a downstream A/D converter having a time-variable reference voltage. In the process, there is a switch between the different outputs of the amplifier at predefined switching points in time, and the reference voltage of the A/D converter varies over time between the switching points in time in such a way that the echo signal is present at the output of the A/D converter with a transit time-dependent total gain having a predefined characteristic. 19-. (canceled)10. A method for amplifying an echo signal , the method comprising:amplifying an analog echo signal, which is for detecting a vehicle's surroundings, with a gain which depends on a transit time of the echo signal, wherein the analog echo signal is amplified with the aid of an amplifier having a plurality of outputs each having a different gain and a downstream A/D converter having a time-variable reference voltage, switching between different outputs of the amplifier at predefined switching points in time;varying the reference voltage of the A/D converter over time between the switching points in time so that the echo signal is available at the output of the A/D converter having a transit time-dependent total gain, which has a predefined characteristic.11. The method of claim 10 , wherein the analog echo signal is amplified with the aid of a series-connected chain of amplifiers having a fixed gain and of the downstream A/D converter having a time-variable reference voltage.12. The method of claim 10 , wherein the characteristic is predefined in pieces between the switching points in time.13. A method for detecting a vehicle's surroundings with the aid of at least one echo signal claim 10 , the method ...