Verfahren und Gerät zur Analog/Digitalwandlung von SAR Typ mit niedrigem Verbrauch und Rausch

A digital to analog converter

OPTICAL DISPLACEMENT ENCODER

To minimise power consumption in optical encoding, a light source (D1, D2) is pulsed and a detector (PT1, PT2) is activated in synchronism with the light source. Light interrupting means such as a slotted encoder disc (18) opens and closes the optical path from the light source to the detector resulting in a pulsed electrical output signal for use in encoding. A pair of encoders responding respectively to movement in X and Y directions may be used in a mouse for cursor control of a computer display system, the two light sources being pulsed alternatively to minimise peak power consumption. ...

Signal Processing System Having an ADC Delta-Sigma Modulator with Single-Ended Input and Feedback Signal Inputs

HIGH-SPEED ANALOGUE-DIGITAL CONVERTER WITH IMPROVED ONE ANTIALIASING SIGNALSTRUKTUR BY REDUCTION OF THE NUMBER OF ELEMENTARY CELLS

A BODY-BIASED SLICER DESIGN FOR PREDICTIVE DECISION FEEDBACK EQUALIZERS

... 73957/ S1421 A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC. 2062656vl Ln) mW +C ...

High-precision AD collection system based on AD4020

Reducing distortion in analog-to-digital converters

DEVICE FOR CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS

적분형 아날로그-디지털 변환기

... 본 발명은 적분형 아날로그-디지털 변환기에 관한 것이다. 본 발명에 따르면, 적분형 아날로그-디지털 변환기에 차동 증폭기를 채용하여 외부 노이즈에 대한 면역력을 향상시키고, 또한 입력전압과 기준전압을 동시에 차단하는 구간을 제공하여 스위칭 노이즈를 최소화함은 물론 기준 전압이 안정적으로 공급되게 하였다. 그리고 아날로그 입력 값에 대한 적분동작 종료시에 발생할 수 있는 잔류 카운트를 별도의 변환기가 아닌 제어 로직에서 처리하도록 하여 회로 소자의 사이즈를 줄이도록 하였다.

Cyclic Digital to Analog Converter as pipeline architecture

DAC 커패시터 어레이 및 아날로그-디지털 컨버터, 아날로그-디지털 컨버터 전력 소비를 감소하는 방법

... 본 발명의 실시예는 집적 회로 분야에 속하고, DAC 커패시터 어레이 및 아날로그-디지털 컨버터, 아날로그-디지털 컨버터 전력 소비를 감소하는 방법에 관한 것이다. 상기 DAC 커패시터 어레이는 다수의 병렬 연결되는 서브 커패시터 어레이를 포함하고, 상기 각 하나의 서브 커패시터 어레이는, 양의 정수인 N개의 병렬 연결되는 커패시터를 포함하는 커패시터 뱅크; 메인 스위치 및 다수의 다중 선택 스위치를 포함하고; 상기 커패시터 뱅크 중 각 커패시터의 일단은 콤퍼레이터의 입력단에 공동으로 연결되고, 상기 메인 스위치를 통해 하나의 입력 소스에 연결되며; 상기 커패시터 뱅크 중 각 커패시터의 타단은 상응하는 다중 선택 스위치를 통해 다수의 입력 소스에 연결된다. DAC 커패시터 어레이의 각 커패시터에 연결되는 기준 전압을 조절하는 것을 통해, DAC 커패시터 어레이를 최적화하고, DAC 커패시터 어레이의 전체 커패시터 크기를 감소시킬 수 있으며, 이로써 SAR 타입 아날로그-디지털 컨버터의 체적을 감소시켜, 전력 소비를 감소하고, 아울러 칩 제조에서 칩의 원가를 감소시킬 수 있다.

Method and circuit for current integration

An input current (Iin) is transformed into an output integrated voltage (Vout_int)using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (Tclk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (Tclk_DAC).

Low power buffer circuit

A dual-output buffer circuit for providing a first reference voltage and a second reference voltage has a first buffer circuit, a second buffer circuit, a first reference voltage coupled to the first buffer circuit, a second reference voltage coupled to the second buffer circuit, and a diode circuit coupled to a first output terminal of the first buffer circuit and a second output terminal of the second buffer circuit.

Micro-electro-mechanical systems (MEMS), systems and operating methods thereof

A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that is capable of generating a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The MEMS is free from including any amplifier between the micro-mechanical structure and the ADC.

ANALOG-TO-DIGITAL CONVERTER WITH PROGRAMMABLE RAMP GENERATOR

An analog-to-digital (ADC) converter is disclosed that uses aspects of a single-slope ramp ADC, but with jump steps in the ramp voltage to increase speed. A programmable ramp generator can be used to dynamically modify a voltage level associated with the jump step. By programming a voltage level of the jump, a user can dynamically modify the speed of the ADC during operation.

INTERLEAVED PIPELINED BINARY SEARCH A/D CONVERTER

The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising - a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and - a plurality of amplifying circuits, - wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and - wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical ...

REDUCED POWER CONSUMPTION IN ANALOG-TO-DIGITAL CONVERTER

A stage of a pipelined ADC (100) used as a sub- ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals. The first set and second set of clock signals are designed to cause the start of hold phases of the stage to occur earlier than the sample phases of the next stage. In an embodiment, the start of the hold phases is coincident with the end of an immediately preceding sample phase of the stage. As a result, more time is provided for the output of an amplifier used in the stage to settle to a final value, thus permitting use of a low speed amplifier and reduction in power consumption in the interleaved ADC. In an embodiment, the stage corresponds to an earliest stage in the pipelined sub-ADC.

PIPELINE ADC AND REFERENCE LOAD BALANCING CIRCUIT AND METHOD TO BALANCE REFERENCE CIRCUIT LOAD

Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period. 1. A balancing circuit to balance a load of a reference circuit with an output that provides a reference voltage signal to a load circuit in first and second time periods (S , H) , the balancing circuit comprising:capacitors;a first circuit operative during the first time period to charge one or more of the capacitors using a voltage source; anda second circuit operative during the first time period to select one or more of the charged capacitors according to an expected load of the load circuit in the second time period;the first circuit operative during the second time period to connect the selected one or more capacitors to the output of the reference circuit.2. The balancing circuit of claim 1 , wherein the voltage source has a voltage greater than the reference voltage signal.3. The balancing circuit of claim 2 , wherein the first circuit includes:first switches to connect the one or more capacitors to the voltage source during the first time period, and to disconnect the one or more capacitors from the voltage source during the second time period; andsecond switches individually associated with a corresponding one of the capacitors, the individual second switches operative when a corresponding control signal is in a first state to selectively connect the corresponding capacitor to the output of the reference circuit, and the individual second switches operative when the corresponding control signal is in a second state to ...

Analog-to-digital and digital-to-analog converter

A codec having an analog-to-digital converter and is made in the form of a discrete electronic component. The codec has an analog-to-digital conversion circuit (14) for converting an analog input signal into a sequence of digital samples. An output stage (16) is provided for supplying said sequence in serial form outside said component (2). A first signal detection circuit (22, 24, 26, 28)is provided for indicating outside said component the presence or absence of significant data in said sequence.

Analog-to-digital converter for image sensor

A signal processing circuit outputs a digital word responsive to incident light, and includes an analog integrated circuit having a first input terminal receiving a first analog signal during a first active period of a first switching signal and a second input terminal receiving a time varying reference signal; an inverter circuit inverting and amplifying an output of the analog integrated circuit responsive to an activated enable signal; and an output circuit generating the digital word. During a second active period of the first switching signal, the first input terminal is coupled to a data line for receiving a second analog signal corresponding to image charges of an image input element. The enable signal is deactivated between end points of the first and second active periods of the first switching signal.

Systems and methods for analog to digital conversion

Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, an analog to digital converter is disclosed that includes an analog input that is provided to a comparator bank. The comparator bank receives a reference indicator, and is operable to provide a current output based at least in part on a comparison of the analog input with a reference threshold corresponding to the reference indicator. The analog to digital converter further includes a range selection filter that is operable to receive the current output and to generate the reference indicator based at least in part on a prior output of the comparator bank.

CONTROLLER, CONTROL METHOD, AD CONVERTER, AND AD CONVERSION METHOD

The present technology relates to a controller, a control method, an AD converter, and an AD conversion method by which settling can be improved. The controller includes: a first current source that generates an output signal corresponding to an input signal; a second current source that supplies a current to charge a predetermined capacitance; and a control unit that controls the current supplied from the second current source to the predetermined capacitance, where the first current source and the second current source are each formed of a transistor. The controller further includes a supply unit that supplies a current flowing to the first current source and the second current source, where the current flowing to the first current source and the second current source is proportional to a current flowing in the supply unit. The present technology can be applied to an AD converter included in an imaging apparatus.

Interpolator systems and methods

A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.

Analog to digital converter with internal timer

An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.

SEMICONDUCTOR DEVICE, ANALOG-TO-DIGITAL CONVERSION METHOD, ONBOARD SYSTEM, AND MEASUREMENT METHOD

There is provided a semiconductor device including: an integrator that repeats integrating a first reference voltage after integrating an analog signal; a comparator that compares an output of the integrator and a second reference voltage; a counter circuit that counts a first integration time determined to integrate the analog signal, and a second integration time until the output of the integrator reaches the second reference voltage from start of integration of the first reference voltage; a calculation circuit that calculates a digital value of the analog signal based on the first and the second integration times; a control circuit that performs control so that the analog signal is input to the integrator while the counter circuit counts the first integration time; and an integration time update circuit that updates the first integration time counted by the counter circuit based on the second integration time counted thereby. 1. A semiconductor device comprising:an integrator that repeats integrating a first reference voltage after integrating an analog signal;a comparator that compares an output of the integrator and a second reference voltage;a counter circuit that counts a first integration time determined to integrate the analog signal, and a second integration time until the output of the integrator reaches the second reference voltage from start of integration of the first reference voltage;a calculation circuit that calculates a digital value of the analog signal based on the first and the second integration times;a control circuit that performs control so that the analog signal is input to the integrator while the counter circuit counts the first integration time; andan integration time update circuit that updates the first integration time counted by the counter circuit based on the second integration time counted by the counter circuit.2. The semiconductor device according to claim 1 , whereinthe control circuit controls an input to the integrator so ...

MULTI-ZONE DATA CONVERTERS

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

SYSTEM AND METHOD FOR OPTIMIZING POWER IN PIPELINED DATA CONVERTERS

A pipelined data converter current biasing system employs a frequency-to-voltage converter (FVC) operational to convert a plurality of desired sampling frequencies to a plurality of output voltages and a voltage-to-current (V to I) converter operational to convert the plurality of output voltages to a plurality of bias currents. The plurality of bias currents function to bias the data converter operational amplifiers such that the data converter power consumption is dependent on the plurality of sampling frequencies in a way that optimizes power consumed by the data converter with respect to the sampling frequency.

Sуstеms аnd mеthоds fоr аnаlоg tо digitаl соnvеrsiоn

Vаriоus еmbоdimеnts оf thе prеsеnt invеntiоn prоvidе sуstеms аnd mеthоds fоr аnаlоg tо digitаl соnvеrsiоn. Fоr ехаmplе, аn аnаlоg tо digitаl соnvеrtеr is disсlоsеd thаt inсludеs аn аnаlоg input thаt is prоvidеd tо а соmpаrаtоr bаnk. Тhе соmpаrаtоr bаnk rесеivеs а rеfеrеnсе indiсаtоr, аnd is оpеrаblе tо prоvidе а сurrеnt оutput bаsеd аt lеаst in pаrt оn а соmpаrisоn оf thе аnаlоg input with а rеfеrеnсе thrеshоld соrrеspоnding tо thе rеfеrеnсе indiсаtоr. Тhе аnаlоg tо digitаl соnvеrtеr furthеr inсludеs а rаngе sеlесtiоn filtеr thаt is оpеrаblе tо rесеivе thе сurrеnt оutput аnd tо gеnеrаtе thе rеfеrеnсе indiсаtоr bаsеd аt lеаst in pаrt оn а priоr оutput оf thе соmpаrаtоr bаnk.

ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTER

The invention concerns a coder-decoder comprising an analog-to-digital converter and produced in the form of a discrete electronic component (2), including: an analog-to-digital conversion circuit (14) for converting said input analog signal into a sequence of digital samples; an output stage (16) for supplying said sequence in serial form outside said component (2); a first signal detection circuit (22, 24, 26, 28) to indicate outside said component the presence or the absence of significant data in said sequence.

DELAY ELEMENT CIRCUIT FOR RING OSCILLATOR AND STALL DETECTION IN SELF-CLOCKED SAR ADC

Dynamische Elementanpassung mit variabler Länge in Digital-Analog-Wandlern

Steuervorrichtung (306) zum Steuern der Anwendung von einer oder mehreren dynamischen Elementanpassungs(DEM)-Techniken in einem Digital-Analog-Wandler (DAC) (300), welcher eine Mehrzahl von DAC-Zellen aufweist, wobei die Steuervorrichtung (306) ausgelegt ist zum:Bestimmen (400) eines Bereichs von Amplituden von wenigstens einem Teil eines Eingabesignals (910), welches dem DAC (300) bereitgestellt wird oder bereitgestellt werden soll;Bestimmen (404) einer Anzahl von DAC-Zellen (304-1, ..., 304-N), kleiner als eine Anzahl der Mehrzahl von DAC-Zellen (304-1, ..., 304-N), entsprechend dem bestimmten Bereich von Amplituden des Teils des Eingabesignals (910); undBegrenzen der Anwendung der einen oder mehreren DEM-Techniken auf die bestimmte Anzahl von DAC-Zellen (304-1, ..., 304-N),Bestimmen (404-1), ob der Bereich von Amplituden des Teils des Eingabesignals (910) kleiner als ein Schwellenwert ist,wobei die Anzahl von DAC-Zellen (304-1, ..., 304-N) basierend auf dem Schwellenwert bestimmt wird ...

Emitterfolgeschaltung und Analog-Digitalwandler mit einer solchen Schaltung

Analog-to-digital-converter

Analog-to-digital converter

Activity detection

A low-power, “always on” Voice Activity Detector (VAD, 100) generates a first Time Encoding Modulated (TEM) signal 101 (eg. a loop-filtered Pulse Width Modulated signal SPWM) from a microphone input SIN via a hysteretic comparator (201, fig. 4) and inputs this to a Time Decoding Convertor (TDC, 102) along with a clock signal (SCLK) generated from a midpoint reference voltage (VMID) via a second TEM (103) having a second hysteretic comparator (401, fig. 4). The TDC then outputs a count signal (SCT) to an activity monitor 104 to determine if signal activity lies above a threshold, whereupon a control signal EN is sent to wake other elements.

Analog-to-digital convertor

Wireless receiver and method of saving power

Switchable secondary playback path

Apparatus and method for optical encoding

Analog to digital converter

An analog to digital converter has a plurality of comparators arranged to periodically sample an analog signal; a calculator arranged to predict a change in signal magnitude of the analog signal between one sample of the analog signal and another sample of the analog signal based upon predetermined criteria of the analog signal; and a controller 202 for varying an operational parameter of one or more of the comparators based upon the predicted change in the signal magnitude of the analog signal. The threshold of each comparator may be varied, or certain comparators may be disabled. The converter may be used in a sigma delta modulator.

Analog-to-digital converter

Analog-to-digital converter

An analogue-to-digital converter for speech signals is operable in a low-power input monitoring mode to reduce standby power and is then placed in a high-resolution mode when input signals are detected so that speech recognition may be performed by a succeeding DSP (254, figure 9). A signal detector (252, figure 9) selects the high-resolution mode by enabling the feedback DAC 274 and the loop integrator amplifier 294, selecting the filter output Sfilt instead of the signal input Sin for input to the voltage controlled oscillator 300, and increasing the operating frequency of the VCO (figures 13 and 14). To further reduce power consumption the DSP is enabled only when input signals are detected, full speech recognition operation of the DSP being enabled only when a trigger phrase has been detected (figure 4).

Fully-differential current digital-to-analog converter

A playback path includes an input configured to receive an input signal, an output configured to drive a differential output signal, a differential current-mode digital to-analog converter 14 configured to convert the input signal into the differential output signal, and a control circuit 52. The differential current-mode digital-to-analog converter includes a plurality of current-mode digital -to-analog elements 22a-n configured to be selectively enabled and disabled based on the input signal and at least one reference element 20a, 20b in a current mirror relationship with the plurality of current-mode digital -to-analog elements such that each individual current through each current-mode digital -to-analog element is a scaled version of a reference current of the at least one reference element. The control circuit is configured to scale current mirror ratios between the at least one reference element and the plurality of current-mode digital-to-analog elements based on a characteristic ...

Fully-differential current digital-to-analog converter

A playback path may include an input configured to receive an input signal, an output configured to drive a differential output signal, a differential current-mode digital-to-analog converter configured to convert the input signal into the differential output signal, and a control circuit. The differential current-mode digital-to-analog converter may include a plurality of current-mode digital-to-analog elements configured to be selectively enabled and disabled based on the input signal and at least one reference element in a current mirror relationship with the plurality of current-mode digital-to-analog elements such that each individual current through each current-mode digital-to-analog element is a scaled version of a reference current of the at least one reference element. The control circuit may be configured to scale current mirror ratios between the at least one reference element and the plurality of current-mode digital-to-analog elements based on a characteristic of the input ...

DAC SHUTDOWN FOR LOW POWER SUPPLY CONDITION

Analog-to-digital converter

SCANNING

PROCEDURE FOR THE MEASUREMENT AND DETERMINATION OF THE ABSOLUTE POSITION OF A GIVER WAVE AS WELL AS A MECHANISM FOR THE APPLICATION OF THE PROCEDURE

APPARATUS FOR OPTICAL ENCODING

INPUT CURRENT SAVING APPARATUS FOR FLASH A/D CONVERTER

A flash analog-to-digital (A/D) converter includes a plurality of comparators, each of which is arranged to be alternately coupled with the input signal and the respective one of a plurality of reference voltages in order to find the closest match therebetween. The output of the comparators is fed to a programmable logic array (PLA) for determining a binary number related to the particular value of the input signal. Pursuant to this invention, the input signal is continuously tracked, and in dependence upon whether the input signal is above or below the midpoint reference potential, a predetermined potential, instead of the input signal, is applied to particular groups of comparators.

HYBRID ANALOG-TO-DIGITAL CONVERTER FOR LOW POWER APPLICATIONS, SUCH AS USE IN AN IMPLANTABLE MEDICAL DEVICE

A method and apparatus is disclosed for use in an implantable device that includes an analog-to-digital converter (ADC) for converting electrograms (such as EKG signals) into digital codes that can be stored in memory. The ADC constructed according to the present invention is capable of achieving considerable power savings by minimizing the number of clock cycles required to determine the correct digital code for a particular sample point on the electrogram signal, thus making it possible to turn off some or all of the ADC logic during idle periods. The ADC includes prediction logic that provides a starting point for subsequent searching for the correct digital code value. The prediction logic receives recent code conversions values which it uses to predict the current digital code value. This predicted digital code is converted to an analog value and compared with the actual electrogram voltage to determine if the prediction is above or below the correct code representation. Next, the ...

Successive approximation type digital-to-analog converter with feedback advanced set and corresponding Delta-SigmaADC architecture

Electronic system and operation method thereof

Absolute value encoder and method for correcting output of an absolute value encoder.

DIFFERENTIAL DIGITAL-TO-ANALOG CONVERTER HAS FUNCTION OF FILTERING AND COMPENSATION OF SHIFT

DEVICE OF CONVERSION OF ANALOGICAL SIGNALS INTO NUMERIC SIGNALS

Procédé et dispositif de conversion de signaux analogiques, d'une pluralité de voies, en signaux numériques. Un circuit commun (2, 3) génère des premiers signaux analogiques correspondant à de bits de poids forts de signaux numériques. Pour chaque voie, un premier moyen compare les premiers signaux analogiques avec le signal à convertir. Un premier moyen (18) mémorise des bits de poids forts correspondant à la valeur d'un premier signal analogique proche du signal à convertir. Un moyen (9) mémorise l'écart entre le signal analogique à convertir et ladite première valeur détectée. Un moyen générateur (11, 12) génère un nombre prédéterminé de seconds signaux analogiques. Un second moyen compare par approximations successives lesdits seconds signaux analogiques avec ledit écart. Un moyen (20) mémorise les bits de poids faibles correspondant aux résultats issus dudit second moyen de comparaison. Un moyen (22) assemble lesdits bits de poids forts et lesdits bits de poids faibles.

PSEUDO-DIFFERENTIAL CLASS-AB DIGITAL-TO-ANALOG CONVERTER WITH CODE DEPENDENT DC CURRENT

저 밴딩 노이즈를 위한 비교 장치 및 그에 따른 씨모스 이미지 센서

... 본 기술은 저 밴딩 노이즈를 위한 비교 장치 및 그에 따른 씨모스 이미지 센서에 관한 것으로, 게인 발생 위치를 변경하여 입력 트랜지스터들이 새츄레이션(Saturation) 영역에서 동작할 수 있도록 하기 위한 비교 장치 및 그에 따른 씨모스 이미지 센서를 제공한다. 이러한 비교 장치는, 램프 신호와 픽셀 신호를 비교하여 비교 신호를 출력하기 위한 비교 블럭; 및 상기 비교 블럭으로부터의 비교 신호를 증폭하여 이득을 획득하고, 노이즈가 발생되는 것을 완화시키기 위한 이득 획득 및 노이즈 완화 블럭을 포함할 수 있다.

듀얼-스트링 디지털-아날로그 변환기들(DAC들), 및 관련 회로들, 시스템들 및 방법들

... 듀얼-스트링 디지털-아날로그 변환기들(DAC들), 및 관련 회로들, 시스템들 및 방법들이 개시된다. 본 명세서에 개시된 실시예들에서, 듀얼-스트링 DAC의 주 분압기는 적어도 하나의 조절 회로로 구성된다. 조절 회로는, 주 스위치 유닛이 선택된 저항기 노드 쌍을 선택하는 것에 대한 응답으로, 보조 분압기 회로에 걸친 선택된 저항기 노드 쌍의 이상적 전압을 유지하도록 구성된다. 이러한 방식으로, 듀얼-스트링 DAC의 주 분압기와 보조 분압기 회로 사이에 임피던스 분리가 요구되지 않는다. 결과적으로, 비제한적인 예로, 듀얼-스트링 DAC에 대한 집적 회로(IC) 상의 면적이 감소될 수 있고, DAC의 전력 소모가 감소될 수 있고, 그리고/또는 듀얼-스트링 DAC가 안정 시간을 요구하지 않음으로 인해 증가된 성능을 가질 수 있다.

DATA LOCK AHEAD, CAPABLE OF SAVING POWER CONSUMPTION BY SWITCHIGN A STATE OF A SUB SYSTEM

PURPOSE: A data lock ahead is provided to switch a state of a sub system like a segmented DAC(Digital Analog Converter) of an LDD(Laser Diode Driver). CONSTITUTION: Some of digital signals are buffered before some of the digital signals are provided to a sub system which reacts to the digital signals(502). Time for which the sub system and/or other sub systems are switched from the first state to the second state during buffering is determined based on the buffered part(504). The second state has smaller power waste than the first state. The states of the sub system and/or other subsystems are selectively switched(506). Some of the digital signals are provided to the sub system(508). COPYRIGHT KIPO 2011 ...

SEMICONDUCTOR DEVICE, WIRELESS SENSOR, AND ELECTRONIC INSTRUMENT

An objective of the present invention is to reduce electric power consumption of an analog-digital conversion circuit. An analog potential acquired by a sensor or the like is maintained in a sample hold circuit including a transistor having an extremely low off-current. In the sample hold circuit, the analog potential is maintained at a node which enables charges to be held by turning the transistor off. Power supply to a buffer circuit or the like, which is included in the sample hold circuit, is stopped and a decrease in power consumption is achieved. Also, potential is maintained at each node, so the transistor having an extremely low off-current is provided to a node for maintaining potential of a comparator, a successive approximation register, and a digital-analog converting circuit, etc., and power supply to each circuit is stopped, thereby achieving a decrease in power consumption. COPYRIGHT KIPO 2016 ...

Analogized power saving apparatus and method thereof for sharing electric charges

An analogized power saving apparatus and a method thereof for sharing electric charges are disclosed. The apparatus has an analogized mechanism for forbidding the energy storage unit sharing the electric charges stored thereof to the load capacitor, when during the energy storage unit should be shared the electric charges stored thereof to the load capacitor, and the electric charges stored on the energy storage unit are less than the electric charges stored on the load capacitor, and further the discharged electric charges stored on the load capacitor can not lower than the stored electric charges stored on the energy storage unit. Therefore, if the application devices have the apparatus of the present invention within, the application devices can be achieved entirely power saving mechanism.

ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND RELATED METHODS AND APPARATUS

3D IMAGER AND METHOD FOR 3D IMAGING

... 3D imager comprising at least one pixel, each pixel comprising a photodetectorfor detecting photon incidence and a time-to-digital converter system configured for referencing said photon incidence to a reference clock, and further comprising a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for adjusting the frequency of the reference clock on the basis of an estimated time up to a subsequent photon incidence ...

A METHOD FOR CONVERTING ANALOG SIGNAL TO DIGITAL SIGNAL USING A SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER

The present invention relates to a method for converting analog signal to digital signal using a successive approximation register analog to digital converter. The method allows the SAR-ADC (100) to go through a first iteration of bit cycling and then stores the most significant bits and monitor bits in a register of the SAR- ADC (100). The most significant bits are fixed for the subsequent iteration of bit cycling until a change has been detected to the monitor bits.

ELECTRONIC CIRCUIT DEVICE

Circuit (1a) including an analog circuit processes an analog input signal (Vin). Moreover, the circuit (1a) including the analog circuit outputs a coefficient s1 indicating predetermined characteristic of the analog circuit of the circuit (1a) including the analog circuit and inputs it to a coefficient detection/control circuit (1b). The coefficient detection/control circuit (1b) processes and detects the coefficient s1 as a signal value, thereby detecting the characteristic of the analog circuit. The coefficient detection/control circuit (1b) outputs a control signal s2 in accordance with the detection result of the obtained coefficient s1 and inputs it into the circuit (1a) including the analog circuit. Thus, the coefficient detection/control circuit (1b) adjusts the operation state of the analog circuit and controls the operation of the circuit (1a) including the analog circuit. Thus, it is possible to use the manufactured analog circuit with a high accuracy and realize an electronic ...

N-bits successive approximation register analog-to-digital converting circuit

The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

Analog-to-digital conversion with noise injection via wavefront multiplexing techniques

A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality.

Analog to digital converter and a method of operating an analog to digital converter

Example embodiments of this disclosure can provide an apparatus, a system, and a method of correcting for charge lost from a sampling capacitor as a result of an analog to digital conversion being performed. In an embodiment, there is provided a method of operating an analog to digital converter comprising at least a first sampling capacitor used to sample an input signal, where the method can further comprise a correction step of modifying the voltage across the at least first sampling capacitor, the correction step being performed prior to commencing an acquire phase.

ANALOG-TO-DIGITAL CONVERTER AND METHOD OF PERFORMING ANALOG-TO-DIGITAL CONVERSION

An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.

Signal processing apparatus, signal processing method, and non-transitory computer-readable storage medium storing program

To enable processing of a signal at an appropriate level. An analog section in which an acquired signal is processed in an analog fashion and a digital section in which the signal processed in the analog section is digitally processed are included, wherein the analog section includes an adjustment unit that adjusts a gain discretely and the digital section includes a digital step compensation unit that compensates for discrete gain adjustments in the analog section. The digital step compensation unit responds to a transient step in which a gain steeply converts in the analog section and compensates with inverse characteristics of a transient response. The present technology can be applied to an AGC (Automatic Gain Control) system.

Successive approximation analog-to-digital converter (ADC) with dynamic search algorithm

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Successive approximation analog-to-digital converter and method of analog-to-digital conversion

An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.

COMPARING CIRCUIT AND A/D CONVERTER

The first amplifier operates according a first clock, changes voltages of a first terminal and a second terminal from a first fixed voltage to a second fixed voltage according to a voltage of an input signal and a first reference voltage, respectively, when an on period of a first clock starts, and keeps the voltages of the first and second terminals at the second fixed voltage, respectively, after the voltages of the first and second terminals reach the second fixed voltage and until the on period of the first clock ends, and the first comparator generates first and second logic signals that have logical levels different from each other, based on a difference between the voltages of the first and second terminals when the on period of a second clock whose on period at least partially overlaps with that of the first clock starts.

ELECTRONIC SYSTEM AND OPERATING METHOD THEREOF

To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.

Linearized optical digital-to-analog modulator

A modulator device for converting digital data into modulation of an optical signal includes an electronic input for receiving an input data word of N bits and an electrically controllable modulator for modulating the intensity of an optical signal, the modulator including M actuating electrodes where MN. An electrode actuating device, most preferably a digital-to-digital converter, operates actuating electrodes so that at least one electrode is actuated as a function of values of more than one bit of the input data word. According to an alternative, or supplementary, aspect of the invention, the set of electrodes includes at least one electrode having an effective area which is not interrelated to others of the set by factors of two. In one preferred implementation, a Mach-Zehnder modulator also provides phase modulation to give QAM functionality. Another implementation employs a semiconductor laser.

Transimpedance amplifier and analog-digital converter circuit

A transimpedance amplifier according to an exemplary aspect of the present invention includes a first terminal supplied with a first power supply voltage, and a second terminal supplied with a second power supply voltage having a potential lower than that of the first power supply voltage. The transimpedance amplifier outputs a voltage signal that is converted into a binary signal of one of the first power supply voltage and the second power supply voltage, based on an input analog current signal. This makes it possible to reduce a conversion error.

A/D converter with zero power mode

A semiconductor microcontroller includes the capability to perform analog to digital conversions of an analog signal representative of a variable parameter indicative of the need to exercise a control function. While the analog to digital conversions are being performed, the microcontroller processor can be placed in a sleep mode which eliminates noise arising from switching activities of the processor as a source of inaccuracy in the conversion process. At the end of the conversion, the analog to digital converter can either shut itself down or wake up the processor. Alternatively, the converter may shut itself down in response to a different user selected control signal.

Successive approximation register analog-to-digital converter and conversion method therefor

An SAR ADC and a conversion method, which include an SAR control logic circuit configured to control A/D conversion by: 1) sampling analog input signal for first time; 2) subjecting the sampled signal to conversions; 3) sampling analog input signal for another time; 4) subjecting the sampled signal in step 3) to conversion including: i) determining whether the lowest M bits of previous N-bit digital output signal are 1's or 0's, if so, looping back to step 2), otherwise, proceeding to step ii); ii) performing conversions on lowest M bits of new N-bit digital output signal, directly taking N-th to (M+1)-th bits of previous N-bit digital output signal as N-th to (M+1)-th bits of new N-bit digital output signal, and repeating steps 3) and 4) until the analog input signal is fully sampled and converted. Required cycles can be reduced resulting in higher conversion rate and lower power consumption.

Analog-to-digital converter, electronic device, and method of controlling analog-to-digital converter

To reduce power consumption of a sequential comparison analog-to-digital converter. An analog-to-digital converter includes a sequential conversion unit, a determination unit, and a stop control unit. The sequential conversion unit sequentially generates a predetermined number of bits of a value corresponding to an analog signal when the analog signal is input. The determination unit determines whether a value of a digital signal including the predetermined number of bits is within a predetermined range whenever the bits are generated. The stop control unit stops the sequential conversion unit in a case in which the value of the digital signal is not within the predetermined range.

Sуstеms аnd mеthоds fоr аnаlоg tо digitаl соnvеrsiоn

Vаriоus еmbоdimеnts оf thе prеsеnt invеntiоn prоvidе sуstеms аnd mеthоds fоr аnаlоg tо digitаl соnvеrsiоn. Fоr ехаmplе, аn аnаlоg tо digitаl соnvеrtеr is disсlоsеd thаt inсludеs аn аnаlоg input thаt is prоvidеd tо а соmpаrаtоr bаnk. Тhе соmpаrаtоr bаnk rесеivеs а rеfеrеnсе indiсаtоr, аnd is оpеrаblе tо prоvidе а сurrеnt оutput bаsеd аt lеаst in pаrt оn а соmpаrisоn оf thе аnаlоg input with а rеfеrеnсе thrеshоld соrrеspоnding tо thе rеfеrеnсе indiсаtоr. Тhе аnаlоg tо digitаl соnvеrtеr furthеr inсludеs а rаngе sеlесtiоn filtеr thаt is оpеrаblе tо rесеivе thе сurrеnt оutput аnd tо gеnеrаtе thе rеfеrеnсе indiсаtоr bаsеd аt lеаst in pаrt оn а priоr оutput оf thе соmpаrаtоr bаnk.

Analogue to digital converter

An Analogue to Digital Converter (ADC) having a Gated Ring Voltage Controlled Oscillator, GRVCO, to generate a phase signal according to an input voltage; and a quantization circuit to generate a quantized phase output signal according. The GRVCO operates in either a first or second mode of operation according to a gating control signal. In the first mode of operation, the GRVCO operates in a VCO mode with gating disabled. In the second mode of operation, the GRVCO operates in a GRVCO mode wherein gating is enabled or disabled according to a gating signal.

A/D CONVERTER, SYSTEM AND COMPARATOR

PROBLEM TO BE SOLVED: To provide an A/D converter which can be operated in a high frequency and reduces power consumption in low operation frequencies. SOLUTION: The A/D converter is provided with a plurality of comparators for sampling an analog input potential during a first period and comparing the analog input potential with a reference potential during a second period respectively, an encoder for encoding the compared results by the comparators, and a control signal supply unit for generating a control signal specifying the first and second periods so that the length of the first period can be different from the length of the second period, and supplying the control signal to the plurality of comparators. COPYRIGHT: (C)2003,JPO ...

A/D Wandler-Vorspannungsstromschaltkreis

Analog-Digital-Wandler und Verfahren zum Analog-Digital-Wandeln

Analog-Digital-Wandler (100; 200) mit folgenden Merkmalen: einem ersten Register (112; 212; 412) zum Halten einer ersten Approximationszahl (132; 232), die in einem ersten Zyklus variabel ist und in einem zweiten Zyklus fest ist; einem zweiten Register (114; 214; 414) zum Halten einer zweiten Approximationszahl (134; 234), die in dem ersten Zyklus fest ist und in dem zweiten Zyklus variabel ist; einem Addierer (116; 216; 416) zum Addieren der ersten und der zweiten Approximationszahl und zum Bereitstellen einer Summen-Approximationszahl (140; 240; 440), die eine digitale Darstellung eines analogen Eingangssignales (102; 202; 402; 490) darstellt; einer Verarbeitungseinrichtung (122; 212, 214; 412, 414) zum Berechnen der ersten Approximationszahl, wobei die Verarbeitungseinrichtung ausgebildet ist, um in dem ersten Zyklus ansprechend auf das analoge Eingangssignal die erste Approximationszahl so einzustellen, daß die Summen-Approximationszahl von dem analogen Eingangssignal abhängt, und zum ...

Analog-Digital-Umsetzung

Wenigstens ein Asymmetrieelement (250) ist konfiguriert, ein Eingangssignal (Vin) zu empfangen, und ist mit einem ersten Zweig (201-1) eines bistabilen Flipflops (200) gekoppelt, das den ersten Zweig (201-1) und einen zweiten Zweig (201-2) umfasst. Die Asymmetrie zwischen dem ersten Zweig (201-1) und dem zweiten Zweig (201-2) hängt von dem Eingangssignal (Vin) ab. Ein Wert, der das Eingangssignal (Vin) angibt, wird basierend auf den empfangenen Eingangssignalen aus mehreren Ausleseereignissen bestimmt.

Delta-sigma modulator with single-ended input and feedback signal

Signal processing systems described herein include an analog-to-digital delta sigma modulator to process a single-ended input signal using a single-ended analog feedback reference signal. The delta sigma modulator includes a switched capacitor circuit that integrates a difference between the single-ended input signal and the single-ended analog feedback signal derived from a quantization output of the delta sigma modulator. Embodiments of the switched capacitor circuit allow the delta sigma modulator to be implemented with fewer switches, less complicated reference signal generators, and smaller capacitors relative to conventional counterparts. Thus, embodiments of the delta sigma modulator described herein can cost less to build and use less power. Embodiments of the signal processing systems can be implemented in single and multi-bit delta sigma modulators and various sampling topologies, including single and double sampling topologies.

Switched current D/A converter with minimized current drain

A digital-to-analog converter includes a plurality of current sources I-8I adaptable to be turned on and off, coupled to associated switches S1-S8 that are switchable between associated shunt loads R1-R4 and a common current bus. A buffer stage inputs a summed current from the current bus and outputs an analog signal proportional to the summed current. Control signals corresponding to respective bits of the digital input signal are applied to the respective current sources I-8I so as to turn the current sources off and on. Other control signals, also corresponding to bits of the digital input signal, are applied to the switches SI-S8 so as to switch the switches at a predetermined time period after the associated current sources are turned on.

Low power comparator

Ultra low power analog to digital converter

Receiver apparatus

A cable modem reduces sampling rate when not detecting payload data

A receiver receives a downstream signal, received for example from a cable network. The signal includes payload data (Fig. 13) and physical layer signaling (Fig. 15), the latter identifying downstream communications resources containing payload data (e.g. OFDM resource blocks). The physical layer signaling additionally includes a mode-switching signal which indicates whether the receiver should switch from a sleep mode to an active mode, or vice versa. The receiver comprises an analogue receiving filter 906/907 and an analogue to digital converter (ADC) 922. The receiving filter appears to act as an anti-aliasing filter for the ADC. In the sleep mode the filter has a first bandwidth and the ADC a first sampling rate. In the active mode the sleep mode has a second bandwidth which is greater than the first bandwidth and a second sampling rate which is greater than the first sampling rate. Preferably the receiver operates in an active mode when receiving the broadband payload data, but otherwise ...

Power-saving current-mode digital-to-analog converter (DAC)

A digital-to-analog converter (DAC) for an audio system in a media device, such as a portable media device or smart phone, may be operated to turn off portions of the DAC to reduce power consumption. Segments of a segment-able DAC may be powered off when the output level of the DAC is lower than the full scale output of the DAC. For example, DAC elements within a finite impulse response (FIR) DAC may be turned off when a desired output level can be obtained with less than all DAC elements of the FIR DAC. According to the invention, the determination of the number of segments sufficient to generate an output signal is based, at least in part, on the envelope of the input signal. The powering down of segments may be achieved by sending a zero code or a dump code to the segments.

Fully-differential current digital-to-analog converter

Analog-to-digital converter

Current controlled transconduction inverting amplifers

SWITCHING CONFIGURATION FOR THE CONVERSION OF DIGITAL - SIGNALS INTO ANALOG SIGNALS AND FOR THE CONVERSION OF ANALOG SIGNALS TO DIGITAL SIGNALS

Receiver with Orthogonal Beam Forming Technique

A receiver with orthogonal beam forming technique is achieved that is capable of differentiating different signal components within the received composite signal. An adaptive processor is used to eliminate the signal component whose phase information is known or can be calculated. The phase information of the major component of a signal can be easily acquired by using a limiter. The phase information of other signal components can be acquired by their direction information and other characteristics, such as modulation scheme, etc. Multiple orthogonal beams can be formed by eliminating one unwanted signal component each time by the adaptive processor until all unwanted signal is eliminated. Thus, a composite signal from multiple sources can be broken down into their component signals.

Data look ahead to reduce power consumption

Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa. Eventually, the portions of the digital signal are provided to the sub-system so that the sub-system can respond to the portions of the digital signal.

Successive approximation register analog-to-digital converter

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Systems and Methods for Decimation Based Over-Current Control

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active.

SIGNAL CONVERTING APPARATUS OF POWER METERING SYSTEM, POWER METERING SYSTEM AND METHOD FOR SIGNAL-CONVERTING IN POWER METERING SYSTEM

The present invention relates to a signal converting apparatus of a power metering system, a power metering system and a method for signal-converting in a power metering system. In accordance with one embodiment of the present invention, there is proposed to a signal converting apparatus of a power metering system including a frequency shift unit for shifting a frequency(s) of at least one signal of sensed current and voltage signals by a shift frequency(s) so that the current and voltage signals have different frequency bandwidths, a signal coupling unit for coupling the current and voltage signals having different frequency bandwidths into one signal and an analog-digital convert unit for converting an analog signal coupled as said one signal into a digital signal(s). And also, a power metering system including the same and a method for converting a signal of the power metering system are proposed. 1. A signal converting apparatus of a power metering system comprising: a signal coupling unit for coupling the current and voltage signals having different frequency bandwidths into one signal; and', 'an analog-digital convert unit for converting an analog signal coupled as said one signal into a digital signal(s)., 'a frequency shift unit for shifting a frequency(s) of at least one signal of sensed current and voltage signals by a shift frequency(s) so that the current and voltage signals have different frequency bandwidths;'}2. The signal converting apparatus of a power metering system according to claim 1 , wherein the frequency shift unit shifts each of the sensed current and voltage signals by each of different shift frequencies.3. The signal converting apparatus of a power metering system according to claim 1 , wherein the current and voltage signals are 3-phase signals.4. The signal converting apparatus of a power metering system according to claim 1 , wherein the frequency shift unit consists of frequency synthesizers to generate frequency-shifted intermediate ...

Low power slope-based analog-to-digital converter

Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.

INPUT CONVERTER FOR A HEARING AID AND SIGNAL CONVERSION METHOD

In order to minimize noise and current consumption in a hearing aid, an input converter including a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage includes an amplifier (Q) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (C, C, C, C). The invention further provides a method of converting an analog signal. 1. A sigma-delta converter converting an analog signal into a digital signal , and comprising:an input transformer receiving an input voltage and outputting a transformed voltage to a summation point;an integrator integrating a voltage present in the summation point;a comparator comparing an output from the integrator with a predetermined threshold and outputting a logical level in accordance with the comparison; anda feedback loop coupling a feedback signal back to the summation point;wherein said input transformer includes a switchable capacitor configuration.2. The converter according to claim 1 , wherein the input transformer includes at least two capacitors claim 1 , a plurality of switching elements and control logic claim 1 , and wherein the control logic switches the input transformer between a first and a second phase of operation.3. The converter according to claim 2 , wherein said plurality of switching elements and control logic is configured to arrange said ...

Da-converter and test apparatus

A DA conversion apparatus comprising a DA converting section that includes a plurality of analog elements; and a control section that generates first shift data and second shift data by shifting the input digital data by respective shift amounts of M bits and N bits, and controls the analog elements based on the first shift data and the second shift data, wherein the control section changes a control state for each of the common analog elements according to the bit shift amounts M and N in the control section, between at least two control states including a control state in which the common analog element is controlled according to higher-order bits of the first shift data and a control state in which the common analog element is controlled according higher-order bits of the second shift data.

SEMICONDUCTOR INTEGRATED CIRCUIT AND IMAGE SENSOR

According to one embodiment, a semiconductor integrated circuit is configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal. The semiconductor integrated circuit includes m (m is an integer greater than or equal to 2) first capacitors and second capacitors. Each of the m capacitors has a first electrode and a second electrode, and the first electrodes are connected to each other. Each of the m second capacitors has a third electrode and a fourth electrode, and the third electrodes are connected to each other. The semiconductor integrated circuits further includes: a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; and a logic circuit configured to generate the digital signal based on a comparison result of the comparator. 1. A semiconductor integrated circuit configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal , the semiconductor integrated circuit comprising:m (m is an integer greater than or equal to 2) first capacitors, each of which comprises a first electrode and a second electrode, the first electrodes being connected to each other;m second capacitors, each of which comprises a third electrode and a fourth electrode, the third electrodes being connected to each other;a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; anda logic circuit configured to generate the digital signal based on a comparison result of the comparator,wherein the first analog voltage is inputted into the first electrode,the second analog voltage is inputted into the third electrode, andone of a ground voltage and substantially ½ of a voltage of an input voltage range of the semiconductor integrated circuit is inputted into each second electrode and each fourth electrode.2. The circuit of claim 1 , whereinonly two switches are connected to each second electrode ...

SWITCHING SCHEME FOR ISI MITIGATION IN DATA CONVERTERS

Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node. 120-. (canceled)21. A method of mitigating inter-symbol interference in a tri-level digital to analog converter (DAC) , comprising:receiving, at the tri-level DAC, a digital data signal;converting the digital data signal into an analog signal in at least one tri-level unit element by switching within the tri-level unit element based on the digital data signal, wherein the inter-symbol interference generated by the conversion is independent of the digital data signal; andoutputting the analog signal.22. The method of claim 21 , further comprising:receiving a clock signal, andcontrolling the switching based on the clock signal.23. The method of claim 22 , wherein the switching occurs multiple times in a clock cycle.24. The method of claim 21 , wherein the inter-symbol interference generated by the conversion is substantially the same as in a preceding conversion.25. The method of claim 21 , further comprising:receiving a current from a current source,wherein the switching includes switching the current to an output based on the digital data signal.26. The method of claim 25 , ...

Integrating A/D Converter

In an integrating A/D converter, first and second reference voltage inputs () alternatingly connect through a reference voltage switch () via a first reference resistor (R) to an inverting input () of an integrator (). A comparator () connected downstream of the integrator () compares a test voltage applied to its test voltage input () with a comparator reference voltage applied to its reference voltage input (). This input () is connected to the output () of the integrator (). A control device () actuates the first reference voltage switch () in a pulsed manner and measures the time intervals between the individual switching processes. An inverter () inverting a measuring voltage (U) and a first heating resistor (R) coupled thermally with a measuring resistor (R), are connected in series between the measuring voltage input () and the output of the first reference voltage switch (). 1. An integrating analog-to-digital (A/D) converter , comprising:a measuring voltage input for an analog measuring voltage, which is connected via a measuring resistor to an inverting input of an integrator,a first reference voltage input for a first reference voltage and a second reference voltage input for a second reference voltage,a first reference voltage switch configured to alternatively connect the first and the second reference voltage inputs via a first reference resistor to the inverting input of the integrator,a comparator connected downstream of the integrator and configured to compare a test voltage applied to a test voltage input of the comparator with a comparator reference voltage applied to a reference voltage input of the comparator, wherein the comparator test voltage input is connected to an output of the integrator,a control device configured to actuate the first reference voltage switch in a clocked manner and to measure time intervals between individual switching processes, andan inverter configured to invert the measuring voltage and a first heating resistor ...

LOW POWER ANALOG TO DIGITAL CONVERTER

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal. 1. An apparatus comprising:a reference generator to provide a reference voltage;a sigma-delta modulator coupled to the reference generator, wherein the sigma-delta modulator is to receive an analog signal; anda finite state machine (FSM) coupled to an output of the sigma-delta modulator, wherein the FSM is to provide a digital code representing the analog signal.2. The apparatus of claim 1 , wherein the sigma-delta modulator comprises an amplifier and a circuit for performing auto zero correction of the amplifier.3. The apparatus of claim 2 , wherein the sigma-delta modulator comprises a chopper which is operable to cancel common-mode noise from the amplifier.4. The apparatus of claim 2 , wherein the amplifier and the circuit are part of an integrator.5. The apparatus of claim 2 , wherein the amplifier comprises an inverter.6. The apparatus of comprises a first multiplexer coupled to the reference generator.7. The apparatus of claim 6 , wherein the first multiplexer is controlled by an input of the FSM.8. The apparatus of claim 6 , wherein the first multiplexer is to selectively provide one of the reference voltage or a digital bit to a first switch.9. The apparatus of claim 8 , comprises a first capacitive device coupled to the first switch and the amplifier.10. The apparatus of claim 9 , comprises a second switch to receive the analog signal claim 9 , wherein the second switch is coupled to the first capacitive device.11. The apparatus of comprises a third switch coupled to an output of the amplifier and the second switch.12. The apparatus of comprises:a fourth switch coupled to the second switch; anda second capacitive device coupled in ...

DRIVING CIRCUIT AND DATA TRANSMITTING METHOD

A driving circuit includes channels, a positive converting unit, a negative converting unit, an input switch, and an operational amplifier. A first digital data and a second digital data are alternatively transmitted in a first channel and a second channel. The positive converting unit and negative converting unit are respectively disposed in first channel and second channel and convert first digital data and second digital data into a positive analog data and a negative analog data. A first input terminal and a second input terminal of operational amplifier are respectively in first channel and second channel. After input switch respectively transmits positive analog data and negative analog data to first input terminal and second input terminal or to second input terminal and first input terminal, positive analog data and negative analog data are transmitted in a channel of the channels corresponding to entering operational amplifier. 1. A driving circuit , comprising:a plurality of channels, comprising a first channel and a second channel, wherein a first digital data and a second digital data are alternatively transmitted in the first channel and the second channel;a positive converting unit, disposed in the first channel, for converting the first digital data into a positive analog data;a negative converting unit, disposed in the second channel, for converting the second digital data into a negative analog data;an input switch, coupled to the positive converting unit and the negative converting unit; andan operational amplifying module, coupled to the input switch, wherein a first input terminal and a second input terminal of the operational amplifying module are disposed in the first channel and the second channel respectively;wherein the input switch transmits the positive analog data and the negative analog data to the first input terminal and the second input terminal respectively or to the second input terminal and the first input terminal respectively ...

INTEGRAL A/D CONVERTER AND CMOS IMAGE SENSOR

The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit. 1. An integral type Analog/Digital (AD) converter comprising:a comparator configured to compare a reference voltage of a ramp waveform linearly changed according to a passing of time with an input voltage and output a comparison signal for the reference voltage and the input voltage;a multi-phase clock generation circuit configured to generate a plurality of clock signals including a main clock signal and clock signals having phases different from that of the main clock signal;a delay adjustment circuit configured to delay the comparison signal output from the comparator by a time period longer than one period of the main clock signal, and output the delayed comparison signal;a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit, based on the signals output from the delay adjustment circuit and the main clock signal, and output the counted result as a high order bit; anda time to digital converter configured to latch the plurality of clock signals generated by the multi-phase ...

SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER

Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. 1. A system for providing a pipelined Analog-to-Digital Converter , comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal;', 'at least two reference capacitors that are charged to a reference voltage;', 'at least two sampling capacitors that are charged to a sampling voltage; and', 'a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage., 'a first multiplying Digital-to-Analog Converter (MDAC) stage comprising2. The system of claim 1 , wherein the first MDAC stage further comprises a first current source coupled to a first of the at least two reference capacitors and a ...

DOUBLE DATA RATE TIME INTERPOLATING QUANTIZER WITH REDUCED KICKBACK NOISE

A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core. 1. An apparatus comprising:a first double data rate comparator circuit configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the first double data rate comparator circuit;a second double data rate comparator circuit configured to determine a relative voltage of a second differential input signal during each of the rising edge and the falling edge in the single clock cycle of the comparator clock input to the second double data rate comparator circuit;a third double data rate comparator circuit configured to determine a relative voltage of a third differential input signal during each of a rising edge and a falling edge in the single clock cycle of an inverted comparator clock input to the third double data rate comparator circuit; anda first floating voltage reference circuit configured to shift a voltage of a differential comparator input signal by a first fixed amount, and produce the first differential input signal;a second floating voltage reference circuit configured to shift the differential comparator input signal by a second fixed amount and produce the second differential input signal; anda clock inverter circuit connected to the comparator ...

PROGRAMMABLE GAIN APMPLIFIER (PGA) EMBEDDED PIPELINED ANALOG TO DIGITAL CONVERTERS (ADC) FOR WIDE INPUT FULL SCALE RANGE

A method of incorporating Programmable Gain Amplifier (PGA) function into pipelined ADC for wide input range. The power consumption is saved without adding extra stage to reduce input range. The ADC input range can be adjusted on the fly using resistor bank and capacitor bank to achieve optimal system performance. 1. A Programmable Gain Amplifier (PGA) embedded pipelined ADC for wide input range , comprising:a configuration of 1PstP stage and 2PndP stage coupled together;a gain stage before the 1PstP stage Flash ADC;sampling capacitors in specific ratio;a shared OPAMP between two stages; andmultiple associated switches operating in two clock phases, wherein one OPAMP amplifier is shared by two pipelined stages, the operating phase is determined by internal built-in switches of the amplifier, wherein two differential input pairs couples to one tail current source and one folded cascoded gain stage, each differential pair is enabled at specific clock phase.2. The PGA embedded pipelined ADC of claim 1 , wherein a specific portion of the sampling capacitors are connected to a common-mode voltage and other sampling capacitors are connected to inputs signal.3. The PGA embedded pipelined ADC of claim 1 , wherein the ratio of sampling capacitors can be programmed to adjust the input range for obtaining optimal ADC linearity performance.4. The PGA embedded pipelined ADC of claim 1 , wherein the gain stage before 1PstP stage Flash ADC can be programmed to adjust the input range for obtaining optimal ADC linearity performance.5. The PGA embedded pipelined ADC of claim 1 , wherein the gain stage is implemented using resistor divider claim 1 , capacitor divider or R/C in parallel divider.6. The PGA embedded pipelined ADC of claim 1 , wherein the gain stage is implemented using adjustable resistor bank or adjustable capacitor bank to fine-tune the pipelined ADC input range on the fly for obtaining optimal system performance.7. (canceled)8. (canceled)9. (canceled) As the ...

Pulse generator of image sensor and method of driving the same

A pulse generator of an image sensor includes a delay cell including a plurality of transistors arranged in series between a power voltage and a ground, a stabilization capacitor, and a stabilization switch. The power voltage is supplied to a first terminal of a first transistor disposed first among the plurality of transistors, and a gate terminal of the first transistor is connected to a first node. An input voltage is supplied to a gate terminal of an n-th transistor disposed last among the plurality of transistors, and a ground voltage is supplied to a first terminal of the n-th transistor. The stabilization switch is disposed between a reference voltage input terminal providing a reference voltage and the first node. The stabilization switch is turned on by an input bias control signal to supply the reference voltage to the first node.

METHOD AND DEVICE FOR USE IN ANALOG-TO-DIGITAL CONVERSION

Disclosed herein are embodiments of a precharge sample-and-hold circuit. The circuit has an input terminal, a reference voltage terminal and an output terminal. Further, the circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal and configured to provide the sample voltage when said sample-and-hold circuit is in a holding mode and a cancellation capacitance. Implementations of a precharge sample-and-hold circuit and of methods to operate a precharge sample-and-hold circuit in an analog/digital converter are also disclosed.

DIGITAL-TO-ANALOG CONVERTER

A digital-to-analog converter (DAC) circuit includes a first DAC that produces a first analog output signal based upon a received multi-bit digital data and upon a received clock. A second DAC that produces a second analog output signal based upon the received multi-bit digital data and upon the received clock, wherein the first and second DACs are connected in parallel and process the same input signal comprising the multi-bit digital data. In one embodiment, the DACs produce differential signals. A low pass filter connected to receive the first and second analog outputs is configured to sum the first and second analog outputs and to filter the summed first and second analog outputs to produce an ingoing analog signal. An amplifier connected to receive the ingoing analog signal to produce an amplified ingoing analog signal. 1. A digital-to-analog converter (DAC) circuit , comprising:a first DAC that produces a first analog output signal based upon a received multi-bit digital data and upon a received clock;a second DAC that produces a second analog output signal based upon the received multi-bit digital data and upon the received clock, wherein the first and second DACs are connected in parallel and process the same input signal comprising the multi-bit digital data;a low pass filter connected to receive the first and second analog outputs and configured to sum the first and second analog outputs and to filter the summed first and second analog outputs to produce an ingoing analog signal; andan amplifier connected to receive the ingoing analog signal to produce an amplified ingoing analog signal.2. The DAC circuit of wherein the first and second DACs each produce differential first and second analog output signals claim 1 , respectively.3. The DAC circuit of wherein the low pass filter is configured to receive the differential first and second analog output signals sum and filter the differential first and second analog output signals to produce a differential ...

Device for converting analogue signals into digital signals

Method and device for converting analogue signals, of a plurality of pathways, into digital signals. A common circuit ( 2, 3 ) generates first analogue signals corresponding to high-order bits of digital signals For each pathway, a first means compares the first analogue signals with the signal to be converted. A first means ( 18 ) stores high-order bits corresponding to the value of a first analogue signal close to the signal to be converted. A means ( 9 ) stores the deviation between the analogue signal to be converted and said first detected value. A generator means ( 11, 12 ) generates a predetermined number of second analogue signals. A second means compares by successive approximations said second analogue signals with said deviation. A means ( 20 ) stores said low-order bits corresponding to the results arising from said second means of comparison. A means ( 22 ) assembles said high-order bits and said low-order bits.

COMMON MODE REJECTION IN RESERVOIR CAPACITOR ANALOG-TO-DIGITAL CONVERTER

A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF−. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF−, can be used to provide any common mode charge to the input capacitors. 1. A differential digital-to-analog (DAC) circuit comprising: a pair of input capacitors configured to couple to a comparator;', control operation of a first set of switches to transfer a differential residue charge from the dedicated reference capacitor to the pair of input capacitors when setting the pair of input capacitors in a differential configuration based on a decision of the comparator; and', 'control operation of a second set of switches to transfer a common-mode residue charge from a reference voltage to set the pair of input capacitors when setting the pair of input capacitors in a common-mode configuration based on a decision of the comparator., 'a dedicated reference capacitor associated with the pair of input capacitors; and a control circuit configured to], 'a capacitor array including a number of DAC units, each DAC unit including2. The differential DAC circuit of claim 1 , wherein the input capacitors are bit-trial capacitors claim 1 , and wherein the control circuit configured to control operation of the first set of switches to transfer the differential residue charge from the dedicated reference capacitor to the pair of input capacitors when setting the pair of input capacitors in the differential configuration based on the decision of the comparator is configured to:control operation of the first set of switches to directly couple or cross-couple plates of the reference capacitor to a first plate of a first one of the pair of bit-trial capacitors and a first ...

PIPELINED ANALOG-TO-DIGITAL CONVERTER

The invention provides a pipelined analog-digital converter (ADC) and pertains to the technical field of integrated circuit (IC) design. The pipelined ADC at least comprises: a sampling holder, n multiplier digital-analog converters that are connected stage by stage, a clock generator, a reference generator and a digital encoder, wherein at least the sampling holder and n multiplier digital-analog converters are substantially arranged in a loop so as to form an intermediate area in an encircling manner; the clock generator and the reference generator are disposed in the intermediate area so that the clock generator and the reference generator respectively provide corresponding signal inputs to the surrounding n multiplier digital-analog converters in a star connection. The pipelined ADC has an excellent performance and is in particular applicable to high speed/high accuracy application. 1. A pipelined analog-digital converter (ADC) , at least comprising:n multiplier digital-analog converters that are connected stage by stage,a clock generator,a reference generator, anda digital encoder;characterized in that at least n multiplier digital-analog converters are substantially arranged in a loop so as to form an intermediate area in an encircling manner; the clock generator and the reference generator are disposed in the intermediate area so that the clock generator and the reference generator respectively provide corresponding signal inputs to the surrounding n multiplier digital-analog converters in a star connection;wherein n is an integer larger than or equal to 2.2. The pipelined ADC according to claim 1 , characterized in that the pipelined ADC further comprises a power bus for supplying power claim 1 , wherein the power bus is arranged substantially in a loop so as to surround therein the sampling holder and n multiplier digital-analog converters connected stage by stage.3. The pipelined ADC according to claim 2 , characterized in that the power bus is arranged in ...

Counter circuit, analog-to-digital converter, and image sensor including the same and method of correlated double sampling

A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

Comparator for low-banding noise and cmos image sensor including the same

A comparator may include: a comparison block suitable for comparing a ramp signal and a pixel signal and outputting a comparison signal; and a gain acquisition and noise reduction block suitable for amplifying the comparison signal outputted from the comparison block to acquire a gain and reduce an occurrence of noise.

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD OF CONTROLLING ANALOG-TO-DIGITAL CONVERTER

To reduce power consumption of a sequential comparison analog-to-digital converter. An analog-to-digital converter includes a sequential conversion unit, a determination unit, and a stop control unit. The sequential conversion unit is configured to sequentially generate a predetermined number of bits of a value corresponding to an analog signal when the analog signal is input. The determination unit is configured to determine whether a value of a digital signal including the predetermined number of bits is within a predetermined range whenever the bits are generated. The stop control unit is configured to stop the sequential conversion unit in a case in which the value of the digital signal is not within the predetermined range. 1. An analog-to-digital converter comprising:a sequential conversion unit configured to sequentially generate a predetermined number of bits of a value corresponding to an analog signal when the analog signal is input;a determination unit configured to determine whether a value of a digital signal including the predetermined number of bits is within a predetermined range whenever the bits are generated; anda stop control unit configured to stop the sequential conversion unit in a case in which the value of the digital signal is not within the predetermined range.2. The analog-to-digital converter according to claim 1 , a comparator configured to compare the analog signal to a reference signal and generate the bits on a basis of a result of the comparison, and', 'a reference signal control unit configured to update a value of the reference signal whenever the bits are generated., 'wherein the sequential conversion unit includes'}3. The analog-to-digital converter according to claim 1 , further comprising:an output control unit configured to output a determination result obtained by determining whether the value of the digital signal is within the predetermined range.4. The analog-to-digital converter according to claim 3 ,wherein the output ...

CONTINUOUS-TIME OVERSAMPLING PIPELINE ANALOG-TO-DIGITAL CONVERTER

A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. 120-. (canceled)21. A pipelined analog-to-digital converter (ADC) , comprising: a delay unit to generate an analog input current signal representing a delayed version of an analog input voltage signal;', 'an encoder circuit including a plurality of encoders to generate a plurality of digital output signals based on the analog input voltage signal and a plurality of interleaved clock signals;', 'a decoder circuit including a plurality of decoders to generate a plurality of analog output current signals based on the digital output signals and the plurality of interleaved clock signals; and', 'a subtraction circuit to generate a residue signal based on the analog input current signal and at least one of the plurality of analog output current signals., 'at least one pipeline stage including22. The pipelined ADC of claim 21 , wherein the analog input current signal is delayed from the analog input voltage signal by a predetermined period of time.23. The pipelined ADC of claim 22 , wherein the predetermined period of time is based on a period of the plurality of interleaved clock signals.24. The pipelined ADC of claim 21 , wherein the analog input current signal is delayed from the analog input voltage signal by 1.5 times a period of the plurality of interleaved clock signals.25. The pipelined ADC of claim 21 , wherein each of the plurality of encoders generates a respective one of the plurality of digital output signals at a different time based on a respective different one ...

DOUBLE DATA RATE COUNTER, AND ANALOG-TO-DIGITAL CONVERTER AND CMOS IMAGE SENSOR USING THE SAME

A Double Data Rate (DDR) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an LSB control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections. 1. A Double Data Rate DDR counter , comprising:an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal; anda Least Significant Bit (LSB) control portion suitable for holding an LSB based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.2. The DDR counter of claim 1 , wherein the input clock control portion detects the state of a neighboring clock of the input clock based on a first edge of the counter enable signal and inverts or non-inverts the input clock based on a detected state of the neighboring clock.3. The DDR counter of claim 1 , wherein the input clock control portion includes:a counting section determination block suitable for receiving the input clock and the counter enable signal and determining a counting section;a clock sampling block suitable for sampling the state of the input clock based on the counter enable signal; anda first inversion/non-inversion block suitable for inverting or non-inverting an output of the counting section determination block based on a clock sampling result obtained from the clock sampling block and outputting the first clock to the LSB control portion.4. The DDR counter of claim 3 , wherein the input clock control portion further includes:a third inversion/non-inversion block suitable for inverting or non-inverting a cross-correlation double sampling output based on a control signal and outputting the counter enable signal.5. The DDR counter of claim 3 , wherein the counting section ...

DYNAMIC POWER SWITCHING IN CURRENT-STEERING DACS

Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit. 1. A method , comprising: the DAC circuit is configured to apply the conversion based on current steering; and', 'the DAC circuit is configured to incorporate use of dynamic power switching during current steering., 'applying digital-to-analog conversion to a digital input via a digital-to-analog converter (DAC) circuit, wherein2. The method of claim 1 , comprising applying the dynamic power switching via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage.3. The method of claim 2 , comprising configuring the secondary supply voltage to be less than a main supply voltage used in driving the current steering in the DAC circuit.4. The method of claim 2 , wherein the secondary section comprises at least one transistor element.5. The method of claim 4 , wherein the at least one transistor element comprises a NMOS transistor element claim 4 , PMOS transistor element claim 4 , and/or CMOS transistor element.6. The method of claim 1 , comprising applying the digital-to-analog conversion ...

ANALOG-TO-DIGITAL CONVERSION CIRCUIT, IMAGE SENSOR AND ANALOG-TO-DIGITAL CONVERSION METHOD

An analog-to-digital conversion circuit includes a first comparator, a second comparator and a counter circuit. The first comparator compares an analog signal with a ramp signal. The second comparator compares the analog signal with the ramp signal plus a predetermined offset. When a signal level of the ramp signal is less than a signal level of the analog signal, the counter circuit counts a number of clock cycles of a first clock signal to generate a first portion of a digital signal. When the signal level of the ramp signal plus the predetermined offset is greater than the signal level of the analog signal, the counter circuit counts a number of clock cycles of a second clock signal to generate a second portion of the digital signal. A frequency of the first clock signal is less than a frequency of the second clock signal. 1. An analog-to-digital conversion circuit for converting an analog signal into a digital signal , the analog-to-digital conversion circuit comprising:a first comparator, configured to compare the analog signal with a ramp signal to generate a first comparison signal;a second comparator, configured to compare the analog signal with the ramp signal plus a predetermined offset to generate a second comparison signal; anda counter circuit, coupled to the first comparator and the second comparator, wherein when the first comparison signal indicates that a signal level of the ramp signal is less than a signal level of the analog signal, the counter circuit is configured to count a number of clock cycles of a first clock signal to generate a first portion of the digital signal; when the second comparison signal indicates that the signal level of the ramp signal plus the predetermined offset is greater than the signal level of the analog signal, the counter circuit is configured to count a number of clock cycles of a second clock signal to generate a second portion of the digital signal; a frequency of the first clock signal is less than a frequency of ...

ANALOG-TO-DIGITAL CONVERSION WITH NOISE INJECTION VIA WAVEFRONT MULTIPLEXING TECHNIQUES

An analog-to-digital conversion system comprises a first processor, a bank of N analog-to-digital converters, and a second processor. The first processor is configured to receive M input signal streams, perform a wave-front multiplexing transform in analog domain on the M input signal streams and output concurrently N mixed signal streams, M and N being integers and N≧M>1. The wave-front multiplexing transform comprises a first set of wave-front vectors. The bank of N analog-to-digital converters is coupled to the first processor. The N analog-to-digital converters convert the N mixed signal streams from analog format to digital format and output concurrently N digital data streams. The second processor is coupled to the bank of N analog-to-digital converters. The second processor is configured to receive the N digital data streams, perform a wave-front de-multiplexing transform in digital domain on the N digital data streams and output concurrently N output data streams such that the N output data streams comprise M output data streams that correspond respectively to the M input signal streams. The wave-front de-multiplexing transform comprises a second set of wave-front vectors. 1. An analog-to-digital conversion system comprising:a first processor configured to receive M input signal streams, perform a wave-front multiplexing transform in analog domain on the M input signal streams and output concurrently N mixed signal streams, M and N being integers and N≧M>1, the wave-front multiplexing transform comprising first wave-front vectors;a bank of N analog-to-digital converters coupled to the first processor, the N analog-to-digital converters converting the N mixed signal streams from analog format to digital format and outputting concurrently N digital data streams; anda second processor coupled to the bank of N analog-to-digital converters, the second processor being configured to receive the N digital data streams, perform a wave-front de-multiplexing transform ...

Switched Capacitance Converter

A system includes a first capacitor group to facilitate determination of a first bit, and a second capacitor group to facilitate determination of a second bit in combination with the first capacitor group. The system further includes a delayed clock switch to engage the second capacitor group after determination of the first bit. 1. A system , comprising:a first capacitor group to facilitate determination of a first bit;a second capacitor group to, in combination with the first capacitor group, facilitate determination of a second bit; anda delayed clock switch to engage the second capacitor group after determination of the first bit.2. The system of claim 1 , where the first bit comprises a most significant bit.3. The system of claim 1 , where the second bit comprises a least significant bit.4. The system of claim 1 , where the first capacitor group comprises a first capacitor paired with a second capacitor in the second capacitor group.5. The system of claim 4 , where the first capacitor has less capacitance than the second capacitor.6. The system of claim 4 , where the first capacitor is situated in parallel with the second capacitor.7. The system of claim 4 , further comprising a latch to drive the first and second capacitors.8. The system of claim 4 , where the first capacitor comprises a set of unitary capacitors situated in parallel.9. The system of where a first ratio of the capacitance of the first capacitor to the capacitance of the first capacitor group is similar to a second ratio of the capacitance of the first and second capacitors to the capacitance of the first and second capacitor groups.10. The system of claim 4 , further comprising a split-capacitance analog-to-digital converter; andwhere the first capacitor group further comprises a third capacitor with a capacitance equal to a capacitance of the first capacitor;where the first capacitor is configured to initialize in a logical high state; andwhere the third capacitor is configured to initialize ...

Fractional-N All Digital Phase Locked Loop Incorporating Look Ahead Time To Digital Converter

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. 1. A look-ahead time to digital converter (TDC) for use in an all digital phase locked loop (ADPLL) , comprising:a plurality of controllable delay elements configured in a sequential chain configuration; anda phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a number of delay elements in said chain to function as a digital to time converter and a portion of a remainder of delay elements in said chain to function as a time to digital converter.2. The look-ahead time to digital converter according to claim 1 , wherein said plurality of controllable delay elements are operative to generate an output code representing a fractional portion of a phase error used by said ADPLL to adjust the frequency of the variable clock (CKV).3. The look-ahead time to digital converter according to claim 1 , wherein said phase prediction circuit is coupled to a fractional part of a frequency command word (FCW) signal.4. The look-ahead time to digital converter according to claim 3 , wherein said fractional part of FCW signal is accumulated at said FREF clock.5. A look-ahead time to digital converter (TDC) for use in an ...

Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit. 1. A cyclic digital to time converter and time to digital converter (DTC-TDC) circuit for use in an all digital phase locked loop (ADPLL) circuit , comprising:a plurality of controllable delay elements configured in a cyclical sequential chain configuration;a phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a starting delay element in said chain, a first number of delay elements in said chain to function as a digital to time converter (DTC) and a second number of delay elements in said chain to function as a time to digital converter (TDC); andwherein said DTC and TDC elements are dynamically selected.2. The circuit according to claim 1 , wherein said the selection of said DTC and TDC elements is randomized thereby scrambling mismatches between said delay elements with a resultant reduction in fractional frequency spurs output by said ADPLL.3. The circuit according to claim 1 , wherein said plurality of controllable delay elements comprises a cyclic chain of inverter circuits.4. The circuit according to claim 1 , further comprising a dithering circuit operative to generate FREF dithering.5. The ...

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND SENSING METHOD

In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW a comparator for determining whether the value of an analog input signal exists within a predetermined range, an AD conversion circuit for converting the analog input signal to a digital signal in response to a common activation signal, and a CPU for processing the digital signal in response to the common activation signal. When the analog input signal does not exist within the predetermined rang, the comparator generates the common activation signal. Then, the CPU stores the piece of digital information corresponding to the digital signal as well as the piece of time information from the RTC into a storage circuit. 1. A semiconductor device comprising:a timer circuit for generating a piece of time information and a first activation signal which is flowing periodically;a determination circuit for determining whether the value of an analog input signal exists within a predetermined range, in response to the first activation signal;a first conversion circuit for converting the analog input signal to a digital signal, in response to a second activation signal; anda processing circuit for processing the digital signal converted by the first conversion circuit, in response to a third activation signal,wherein, when the analog input signal does not exist within the predetermine range, the determination circuit generates the second activation signal and the third activation signal,wherein the processing circuit stores a piece of digital information corresponding to the digital signal, as well as the piece of time information from the timer circuit, into a storage circuit.2. A semiconductor device according to claim 1 ,wherein the determination circuit is supplied with its operation voltage in response to the first activation signal,wherein the second activation signal and the third activation signal are used as a common ...

DIGITAL-ANALOG CONVERTER AND DIGITAL-ANALOG CONVERSION DEVICE

The DA converter according to the present invention includes: first and second analog segment units a plurality of capacitors of sampling capacitor groups charged according to signal levels of digital signals input in a sampling phase; and a calculation unit that outputs an analog signal according to a charged voltage of each capacitor of the sampling capacitor group of the first or second analog segment unit in an integral phase, wherein, when one analog segment unit of the first and second analog segment units is in the sampling phase, the other analog segment unit is in the integral phase. 1. A digital-analog converter comprising:a first analog segment unit including a first sampling switch group and a first sampling capacitor group, a plurality of capacitors of the first sampling capacitor group charged according to a signal level of a first digital signal in a sampling phase;a second analog segment unit including a second sampling switch group and a second sampling capacitor group, a plurality of capacitors of the second sampling capacitor group charged according to a signal level of a second digital signal in the sampling phase; anda calculation unit including an operational amplifier and an integration capacitor, the calculation unit outputting an analog signal according to a charged voltage of each capacitor of the first sampling capacitor group or a charged voltage of each capacitor of the second sampling capacitor group in an integral phase,wherein, when one analog segment unit of the first and second analog segment units is in the sampling phase, the other analog segment unit is in the integral phase.2. The digital-analog converter according to claim 1 ,wherein the first sampling switch group is switched such that the first analog segment unit is connected to an input terminal inputting the first digital signal and a reference voltage in the sampling phase, and the first sampling switch group is switched such that the first analog segment unit is ...

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. 1. A method of an analog-to-digital converter , comprising:generating a digital reference code;converting the digital reference code to an analog reference voltage;comparing an analog input voltage to the analog reference voltage to obtain a comparison output;updating the digital reference code based on the comparison output; andafter repeating the converting, comparing, and updating up to a predetermined number of times, outputting the digital reference code as a digital output code representative of the analog input voltage, a first bit accuracy when the analog input voltage falls within a first voltage range, and', 'a second bit accuracy different than the first bit accuracy when the analog input voltage falls within a second voltage range., 'wherein the predetermined number of times results in the digital output code representing the analog input voltage to at least2. The method of claim 1 , wherein the predetermined number of times further results in the digital output code representing the analog voltage to at least a third bit accuracy different than the first and second bit accuracies when the analog input voltage falls within a third voltage range.3. The method of claim 1 , wherein:the first bit accuracy corresponds to a 1-LSB (least significant bit) accuracy; andthe second bit accuracy corresponds to a 2-LSB accuracy.4. The method of ...

Using a sampling switch for multiple evaluation units

In some examples, an integrated circuit device includes a sampling switch configured to sample an input signal. The integrated circuit device also includes a first evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The integrated circuit device further includes a second evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The sampling switch is configured to deliver the sampled input signal to the first evaluation unit and deliver the sampled input signal to the second evaluation unit.

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND METHOD OF ANALOG-TO-DIGITAL CONVERSION

An analog-to-digital converter includes a digital-to-analog converting circuit, a comparator, a comparator offset detector, and a signal processing circuit. The digital-to-analog converting circuit generates a reference voltage signal that changes in response to a comparator offset compensation signal, samples and holds an analog input signal, and performs a digital-to-analog conversion on digital output data to generate a hold voltage signal. The comparator compares the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal. The comparator offset detector generates the comparator offset compensation signal based on the comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. 1. An analog-to-digital converter , comprising: generate a reference voltage signal, the reference voltage signal changing in response to a comparator offset compensation signal,', 'sample and hold an analog input signal, and', 'perform a digital-to-analog conversion on digital output data to generate a hold voltage signal;, 'a digital-to-analog converting circuit configured to,'}a comparator configured to compare the hold voltage signal with the reference voltage signal in response to a clock signal to generate a comparison output voltage signal;a comparator offset detector configured to generate the comparator offset compensation signal based on the comparison output voltage signal; anda signal processing circuit configured to perform analog-to-digital conversion using a successive approximation based on the comparison output voltage signal to generate the digital output data.2. The analog-to-digital converter of claim 1 , wherein the analog-to-digital converter is configured to claim 1 ,perform an analog-to-digital conversion on a comparator offset to generate the comparator offset compensation ...

ANALOG-TO-DIGITAL CONVERTER AND CONTROL CIRCUIT WITH A LOW QUIESCENT CURRENT AT LOW LOAD

A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator. 1. A circuit , comprising:a successive approximation register;an adjustable capacitor having a set input for setting a capacitance value of the adjustable capacitor;a comparator coupled to an input terminal of the adjustable capacitor, and at least one output coupled to an input of the successive approximation register; andan analog input coupled to a terminal of the adjustable capacitor,wherein the circuit is configured to operate in a first operating mode and a second operating mode, and wherein an output of the circuit is controlled by the successive approximation register in the first operating mode and the output of the circuit is not controlled by the successive approximation register in the second operating mode, the output of the circuit being controlled by an output of the comparator in the second operating mode.2. The circuit according to claim 1 , wherein the successive approximation register is disabled during the second operating mode.3. The circuit according to claim 1 , wherein the comparator comprises a plurality of comparators including a second comparator coupled to a terminal of the adjustable capacitor claim 1 , and a first ...

ANALOG-TO-DIGITAL CONVERTER AND CLOCK GENERATION CIRCUIT THEREOF

An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal. 1. A clock generation circuit , comprising cascaded clock generation modules , the clock generation module at each stage being configured to generate a corresponding internal clock signal , and the clock generation module at each stage comprising a delay module and a logic gate module;{'sup': ['th', 'th'], '#text': 'an output terminal of a N-stage delay module being connected to an input terminal of a (N+1)-stage delay module, wherein an input terminal of a first-stage delay module is configured to input an external clock signal, and a frequency of the external clock signal is lower than a frequency of the internal clock signal;'}{'sup': ['th', 'th', 'th', 't', 'th', 'th'], '#text': 'each of the logic gate modules comprising a first input terminal, a second input terminal and an output terminal, the first input terminal of a N-stage logic gate module being connected to the output terminal of the N-stage delay module, the second input terminal of the N-stage gate module being connected to the output terminal of a (N−1)-stage logic gate module, and the output terminal of the N-stage logic gate module being configured to output a Ninternal clock signal, where N is larger than or equal to 2; and'}the first input terminal of a first-stage logic gate module being configured to input the external clock ...

ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND METHOD

An analog-to-digital conversion circuit and method are provided. At a sampling stage, the first capacitor array connects lower electrode plates of N capacitors to a first input voltage, connect lower electrode plates of the other capacitors to a common-mode voltage, and connect upper electrode plates of all the capacitors to the common-mode voltage to sample the first input voltage; in an iconversion at a conversion stage, the logic circuit controls, the lower electrode plate of an icapacitor to connect to a reference voltage or a ground voltage, a first comparison voltage output by the first capacitor array approximates a second comparison voltage; and the comparator stores a comparison result between the first and the second comparison voltage to an i+1flag bit in the logic circuit, and analog-to-digital conversion is completed when i+1 is equal to the total number of capacitors in the first capacitor array. 1. An analog-to-digital conversion circuit , comprising a first capacitor array , a logic circuit and a comparator; wherein:at a sampling stage, the first capacitor array is configured to connect lower electrode plates of N capacitors in the first capacitor array to a first input voltage, connect lower electrode plates of the other capacitors in the first capacitor array to a common-mode voltage, and connect upper electrode plates of all capacitors in the first capacitor array to the common-mode voltage to sample the first input voltage, wherein N is a positive integer less than a total number of the capacitors in the first capacitor array;{'sup': th', 'th', 'th, 'in an iconversion at a conversion stage, the logic circuit is configured to control, according to an istored flag bit, the lower electrode plate of an icapacitor in the first capacitor array to connect to a reference voltage or a ground voltage, such that a first comparison voltage output by the first capacitor array approximates a second comparison voltage, wherein i is a positive integer less than ...

LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR

In a system for converting digital data into a modulated optical signal, an electrically controllable device having M actuating electrodes provides and optical signal that is modulated in response to binary voltages applied to the actuating electrodes. A digital-to-digital converter provides a mapping of input data words to binary actuation vectors for M bits and supplies the binary actuation vectors as M bits of binary actuation voltages to the M actuating electrodes, where M is larger than the number of bits in each input data word. The digital-to-digital converter maps each digital input data word to a binary actuation vector by selecting a binary actuation vector from a subset of binary actuation vectors available to represent each of the input data words. 1. A optical modulation system , the system comprising:an input for a plurality of N digital input data bits;an input optical signal;a modulator for modulating the input optical signal responsively to the plurality of N digital input data bits to output a modulation of the input optical signal, thereby generating one or more modulated optical signal outputs for transmission over one or more optical fibers; andwherein a digital-to-digital mapping maps the plurality of N digital input data bits to a set of M digital output data bits associated with a plurality of voltage values;wherein the input optical signal is modulated based on the plurality of voltage values;wherein the digital-to-digital mapping comprises, for each digital input value included in a set of possible digital input values for the plurality of N digital input data bits, a set of corresponding output values from a set of possible digital output values;wherein, within the digital-to-digital mapping, for a first subset of successively increasing digital input values specified in the digital-to-digital mapping, deltas between numerical values of successive digital outputs in the set of digital output values corresponding respectively to the ...

HIGH-SPEED COMPARATOR FOR ANALOG-TO-DIGITAL CONVERTER

A comparator for an analog-to-digital converter is provided. The comparator includes a differential amplifier unit that receives a sampling signal and provides an output signal, based on a voltage provided by the sampling signal. The differential amplifier unit includes an input stage that receives the sampling signal and integrates a current on the integration nodes based on potentials of the sampling signal. The comparator includes a sense amplifier coupled with the integration nodes that detects a potential difference and amplifies the potential difference to generate the output signal. The comparator includes a charge injection circuit () to inject equal charges into the integration nodes. 1. An analog-to-digital comparator , comprising:a differential amplifier unit wherein the differential amplifier unit receives a sampling signal and provides an output signal based on a voltage provided by the sampling signal, wherein the differential amplifier unit includes:an input stage wherein the input stage receives the sampling signal and integrates a current on integration nodes based on potentials of the sampling signal;a sense amplifier coupled with the integration nodes wherein the sense amplifier detects a potential difference and amplifies the potential difference to generate the output signal; anda charge injection circuit wherein the charge injection circuit injects equal charges into the integration nodes.2. The comparator according to claim 1 , wherein the sense amplifier includes cross-coupled inverters.3. The comparator according to claim 2 , wherein one terminal of each of the cross-coupled inverters is coupled with a respective one of the integration nodes claim 2 , so that the voltage over the cross-coupled inverters depends on the potential on the respective integration node.4. The comparator according to claim 3 , wherein charges are selectively injected into the integration nodes before the voltage over the cross-coupled inverters reaches a value at ...

Analog-to-digital converter circuitry with offset distribution capabilities

Analog-to-digital converter (ADC) circuitry may receive multiple analog signals and output corresponding digital signals. During the conversion process, comparators may receive the analog signals and a ramp waveform and compare the two inputs to generate logic signals. The logic signals correspond to digital signals that are outputted by ADC circuitry. To enable offset distribution capabilities, offset distribution circuitry may be selectively coupled to the inputs of the comparators. The offset distribution circuitry may include switches that couples a voltage supply providing reference voltages to the comparators. The reference voltages may be conveyed via a capacitor to the comparators as offset voltages. The offset voltages may provide may be different for different ADC units to offset power consumption of different ADC units and reduce power surges in power sources coupled to ADC circuitry.

MIXED-SIGNAL CIRCUITRY

Mixed-signal circuitry, comprising: an array of ADC units configured to operate in a time-interleaved manner, and each operable in each of a series of time windows to convert an analogue input value into a corresponding digital output value, each conversion comprising a sequence of sub-conversion operations, each successive sub-conversion operation of a sequence being triggered by completion of the preceding sub-conversion operation; and a controller, wherein: at least one of the ADC units is operable to act as a reporting ADC unit and indicate, for each of one or more monitored said conversions, whether or not a particular one of the sub-conversion operations completed during the time window concerned; and the controller is operable to consider at least one such indication and to control the circuitry in dependence upon the or each considered indication. 1. Mixed-signal circuitry , comprising:an array of ADC units configured to operate in a time-interleaved manner, and each operable in each of a series of time windows to convert an analogue input value into a corresponding digital output value, each conversion comprising a sequence of sub-conversion operations, each successive sub-conversion operation of a sequence being triggered by completion of the preceding sub-conversion operation; anda controller,wherein:at least one of the ADC units is operable to act as a reporting ADC unit and indicate, for each of one or more monitored said conversions, whether or not a particular one of the sub-conversion operations completed during the time window concerned; andthe controller is operable to consider at least one such indication and to control the circuitry in dependence upon the or each considered indication.2. Mixed-signal circuitry as claimed in claim 1 , wherein the time windows for the ADC units are synchronised with one another claim 1 , and/or wherein the series of time windows for the respective ADC units are time-interleaved.3. Mixed-signal circuitry as claimed ...

METHOD AND CIRCUIT FOR NOISE SHAPING SAR ANALOG-TO-DIGITAL CONVERTER

An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a digital-to-analog (D/A) conversion circuit, a comparison circuit and a control circuit. The track-and-hold circuit is configured to output a first signal based on an input signal. The D/A conversion circuit is configured to generate a second signal based on an N-bit logical signal. The comparison circuit is configured to generate a comparison result based on the first signal and the second signal. The control circuit is configured to generate the N-bit logical signal according to N comparison results from the comparison circuit. 1. An analog-to-digital (A/D) conversion system , comprising:a track-and-hold circuit configured to output a first signal based on an input signal;a digital-to-analog (D/A) conversion circuit configured to generate a second signal based on an N-bit logical signal;a comparison circuit configured to generate a comparison result based on at least the first signal and the second signal; anda control circuit configured to generate the N-bit logical signal according to N comparison results from the comparison circuit.2. The A/D conversion system of claim 1 , further comprising:a coupling circuit configured to generate an error signal based on the first signal and the second signal.3. The A/D conversion system of claim 2 , further comprising:a loop filter configured to generate a filtered error signal based on the error signal, wherein the comparison circuit is further configured to generate the comparison result based on the first signal, the second signal and the filtered error signal.4. The A/D conversion system of claim 2 , further comprising:a switched buffer connected to the coupling circuit, the switched buffer configured to sample and hold the error signal, and the control circuit further configured to control a timing of the switched buffer.5. The A/D conversion system of claim 1 , wherein the control circuit is further configured to control a timing of the ...

VOLTAGE REGULATOR WITH LOAD COMPENSATION

A voltage regulation system provides a relatively stable voltage source without introducing the typical costs of a ground buffer. The disclosed voltage regulation system includes a voltage regulator that is operative to detect a change of the load current and regulate a current bypass mechanism to stabilize a total supply current. For example, the voltage regulator includes a current sensor and a current compensation circuit. The current sensor is configure to generate a current compensation signal based on the load current change, whereas the current compensation circuit is configured to adjust a bypass current in response to the current compensation signal. As a result, the bypass current dynamically compensates the load current change such that the ground voltage of a variable load becomes relatively stable over a range of load currents. 1. A reference voltage regulation (RVR) circuit for supplying a reference voltage across a variable load , the RVR circuit comprising:a first output node configured to deliver an output current to the variable load;a second output node configured to collect the output current from the variable load;a current compensation circuit coupled between the first and second output nodes, the current compensator circuit having a control terminal configured to receive a current compensation signal for adjusting a compensation current across the first and second output nodes via the current compensator circuit; anda current sensor coupled with the first and second output nodes to sense a change of the output current, the current sensor configured to generate the current compensation signal based on the sensed change of the output current.2. The RVR circuit of claim 1 , wherein the current sensor includes:a supply current path having a supply output node coupled with the first output node to deliver a supply current sustaining the output current and the compensation current; anda monitoring current path configured to deliver a monitoring ...

ANALOG-TO-DIGITAL CONVERTER WITH NOISE SHAPING

An analog-to-digital converter (ADC) using an amplifier-based noise shaping circuit. The amplifier-based noise shaping circuit generates a noise shaping signal. A comparator of the ADC has a first input terminal coupled to an output terminal of a capacitive data acquisition converter that captures an analog input, a second input terminal receiving the noise shaping signal, and an output terminal for observation of the digital representation of the analog input. The amplifier-based noise shaping circuit uses an amplifier to amplify a residual voltage obtained from the capacitive data acquisition converter and provides a switched capacitor network between the amplifier and the comparator for sampling the amplified residual voltage and generating the noise shaping signal. 1. An analog-to-digital converter with noise shaping , comprising:a comparator, having a first input terminal coupled to an output terminal of a capacitive data acquisition converter that captures an analog input and a second input terminal receiving a noise shaping signal, and outputting a digital representation of the analog input at an output terminal; andan amplifier-based noise shaping circuit, generating the noise shaping signal, comprising:an amplifier, for amplifying a residual voltage obtained from the capacitive data acquisition converter, wherein the amplifier is a dynamic amplifier which is silent on static current; anda switched capacitor network, coupled between the amplifier and the comparator, for sampling the amplified residual voltage and generating the noise shaping signal.2. (canceled)3. The analog-to-digital converter with noise shaping as claimed in claim 1 , wherein:the amplifier-based noise shaping circuit further comprises a finite impulse response filter comprising the amplifier and the switched capacitor network.4. The analog-to-digital converter with noise shaping as claimed in wherein:the amplifier-based noise shaping circuit further comprises an infinite impulse response ...

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD OF CONTROLLING ANALOG-TO-DIGITAL CONVERTER

To reduce power consumption of an analog-to-digital converter in which a comparator is provided. An analog-to-digital converter includes a comparator and a mode control unit. The comparator is configured to generate a comparison result by comparing an analog signal to a threshold indicating a boundary of a predetermined range in a determination mode and convert the analog signal into a digital signal in a conversion mode. The mode control unit is configured to transition the determination mode to the conversion mode in a case in which the comparison result indicating that the analog signal is not within the predetermined range is generated. 1. An analog-to-digital converter comprising:a comparator configured to generate a comparison result by comparing an analog signal to a threshold indicating a boundary of a predetermined range in a determination mode and convert the analog signal into a digital signal in a conversion mode; anda mode control unit configured to transition the determination mode to the conversion mode in a case in which the comparison result indicating that the analog signal is not within the predetermined range is generated.2. The analog-to-digital converter according to claim 1 , comprising:a digital-to-analog conversion unit configured to generate a positive-side output signal and a negative-side output signal from the analog signal and a predetermined selection signal and output the positive-side output signal and the negative-side output signal to the comparator;a sequential comparison control unit configured to generate a predetermined control signal on a basis of the digital signal in the conversion mode; anda selection unit configured to select the predetermined threshold and supply the predetermined threshold as the predetermined selection signal to the digital-to-analog conversion unit in the conversion mode and to select the predetermined control signal and supply the predetermined control signal as the predetermined selection signal to ...

SAMPLING

There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line. 1. An analogue-to-digital conversion circuit , comprising:a first node configured to receive a current signal, the current signal being configured to change in response to an input signal;a plurality of first switch circuits including a plurality of first terminals and a plurality of second terminals, each of the plurality of first terminals being coupled to the first node, the plurality of first switch circuits being configured to sample the current signal in accordance with a plurality of sinusoidal control signals and generate a plurality of sampled signals; anda plurality of analogue-to-digital converters coupled to the plurality of second terminals and configured to convert the plurality of sampled signals and generate a plurality of converted signals.2. The analogue-to-digital conversion circuit of claim 1 ,wherein the plurality of first switch circuits are configured to be sequentially selected during corresponding ones of a plurality of selection periods which occur in succession, successive selection periods of the plurality of selection periods are partially overlapped.3. The analogue-to-digital conversion circuit of claim 2 ,wherein the plurality of selection periods which occur in non-succession are non-overlapped.4. The analogue-to-digital conversion circuit of claim 1 , comprisinga digital circuit configured to generate a digital output signal on the basis of the plurality of converted signals.5. The analogue-to-digital conversion circuit of claim 1 , comprisinga plurality of demultiplexers coupled between the plurality of second terminals and the plurality of analogue-to-digital converters, each of the plurality of demultiplexers ...

Methods and apparatus for reducing timing-skew errors in time-interleaved analog-to-digital converters

A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC) WITH DYNAMIC SEARCH ALGORITHM

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage. 1. A method of an analog-to-digital converter , comprising:selecting, by the analog-to-digital converter, a reference voltage based on a probability that a magnitude of an analog input voltage has a predetermined relationship to a predetermined magnitude;comparing, by the analog-to-digital converter, the analog input voltage to the reference voltage to obtain a comparison output;updating, by the analog-to-digital converter, the reference voltage based on the comparison output; andrepeating, one or more times by the analog-to-digital converter, said comparing and said updating to obtain a digital output code representative of the analog input voltage.2. The method of claim 1 , wherein the selecting is based on the probability having a predetermined relationship to a threshold probability.3. The method of claim 2 , wherein said selecting comprises setting the reference voltage to ¼ of the full scale voltage of the analog-to-digital converter when the probability has the predetermined relationship to the threshold probability claim 2 , and setting the reference voltage to ⅛ of the full scale voltage of the analog-to-digital converter when the probability does not have the predetermined relationship to the threshold probability.4. The method of claim 1 , wherein said updating comprises updating the reference voltage based on an indication of how far ...

LOW POWER EXCESS LOOP DELAY COMPENSATION TECHNIQUE FOR DELTA-SIGMA MODULATORS

A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier. 1. A delta sigma modulator comprising:a first summation device configured to receive an analog input signal and an output signal from a first negative feedback coefficient multiplier;a first integrator configured to receive an output of the first summation device;a second summation device coupled to an output of the first integrator and configured to receive a signal from a second negative feedback coefficient multiplier;a third summation device coupled to an output of the second summation device and configured to receive a signal from a third negative feedback coefficient multiplier;a second integrator configured to receive an output of the third summation device;a quantizer configured to receive an output of the second integrator and generate a digital output signal;a delay element configured to receive the digital output signal and generate a delayed digital output signal;a first digital to analog converter (DAC) configured to provide an output signal to the first negative feedback coefficient multiplier and the second negative feedback coefficient multiplier, wherein the first DAC is configured to receive the delayed digital output signal, thereby forming a feedback loop;a second DAC ...

COMPOSABLE TRANSCEIVER USING LOW BIT COUNT INPUTS AND OUTPUTS

A radio frequency system. In some embodiments, the system includes a one-bit receiver, and the one-bit receiver includes a digital pseudo random noise generator, a one-bit digital to analog converter, a power combiner, a one-bit analog to digital converter, and a digital subtraction circuit. The digital pseudo random noise generator produces a signal added to the received signal before analog to digital conversion. After analog to digital conversion, a delayed version of the dither is subtracted from the digital signal. 1. A radio frequency system , comprising: a digital pseudo random noise generator;', 'a one-bit digital to analog converter, having an input connected to an output of the digital pseudo random noise generator;', 'a power combiner, having a first input connected to an output of the one-bit digital to analog converter and a second input connected to the radio frequency input;', 'a one-bit analog to digital converter, having an input operatively coupled to an output of the power combiner; and', 'a digital subtraction circuit, having a first input connected to an output of the one-bit analog to digital converter, a second input operatively coupled to the output of the digital pseudo random noise generator, and an output connected to the digital output of the one-bit receiver,, 'a one-bit receiver, having a radio frequency input and a digital output, and comprising the digital pseudo random noise generator,', 'the one-bit digital to analog converter,', 'the one-bit analog to digital converter, and', 'the digital subtraction circuit, 'whereinare implemented in a field programmable gate array, and 'the one-bit analog to digital converter is a serial receiver.', 'wherein2. The radio frequency system of claim 1 , further comprising an attenuator connected between the output of the power combiner and the input of the one-bit analog to digital converter.3. (canceled)4. The radio frequency system of claim 1 , wherein:the one-bit digital to analog converter is a ...

Systems and methods for controlling switching circuitry

An electronic device for controlling switching circuitry is described. The electronic device includes line voltage measuring circuitry configured to measure a line voltage to produce a line voltage measurement. The electronic device also includes load voltage measuring circuitry configured to measure a load voltage to produce a load voltage measurement. The electronic device further includes a processor coupled to the line voltage measuring circuitry and the load voltage measuring circuitry. The processor is configured to adjust a control signal for a transition of the switching circuitry based on the line voltage measurement and the load voltage measurement to minimize heat generation and electromagnetic interference creation by the switching circuitry.

Analog-to-digital converter with bandpass noise transfer function

Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

ANALOG-TO-DIGITAL CONVERTER

According to embodiments of the present invention, an analog-to-digital converter is provided. The analog-to-digital converter includes an input configured to receive an input signal, a feed-forward path connected to the input configured to feed forward the input signal, a processing path including a loop filter, wherein the loop filter includes at least one local feedback path configured to feed back an output signal of the loop filter to an input of the loop filter, a first combiner configured to combine the input signal fed forward by the feed-forward path with an output of the processing path, a quantizer configured to generate an output signal of the converter, a feed-back path configured to feed back the output signal, and a second combiner wherein the processing path is connected to the second combiner and the second combiner is configured to combine the input signal with the fed back output signal of the converter and supply the result of the combination to the processing path. 1. An analog-to-digital converter comprising:an input configured to receive an input signal;a feed-forward path connected to the input configured to feed forward the input signal;a processing path comprising a loop filter, wherein the loop filter comprises at least one local feedback path configured to feed back an output signal of the loop filter to an input of the loop filter;a first combiner configured to combine the input signal fed forward by the feed-forward path with an output of the processing path;a quantizer configured to generate an output signal of the converter;a feed-back path configured to feed back the output signal; anda second combiner wherein the processing path is connected to the second combiner and the second combiner is configured to combine the input signal with the fed back output signal of the converter and supply the result of the combination to the processing path.2. The analog-to-digital converter according to claim 1 , wherein the loop filter comprises a ...

Analog-to-digital converter for a capacitive adiabatic logic circuit

An analog-to-digital converter for an adiabatic logic circuit, including at least one variable-capacitance cell, the cell including first and second main terminals and at least one control terminal insulated from its first and second main terminals and capable of receiving a control voltage to vary the capacitance between its first and second main terminals between a low value and a high value, wherein: the cell has its first main terminal coupled to a node of application of a variable periodic converter power supply voltage; the cell has its second main terminal coupled to a node for supplying a binary output signal of the converter; and the cell receives on its first control terminal an analog input voltage of the converter.

TIME-INTERLEAVED SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER WITH GROUPED DIGITAL TO ANALOG CAPACITORS

The present invention is a system and method for providing a modified Digital-to-Analog converter (DAC) for use in a time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC), the DAC including grouping of capacitance electrodes by Bit in a DAC, thereby reducing parasitic capacitances, and substantially improving power efficiency and speed to operate at GHz frequencies. 1. A digital-to-analog converter (DAC) , said DAC comprised of:a top plate having a comb-like structure with a plurality of metallic fingers, the top plate fingers having a uniform length, and all being electrically coupled together to form an output, wherein each of the top plate fingers is of a uniform length;a plurality of bottom plates forming bottom plate bit fingers, wherein each of the bottom plate bit fingers is interleaved between two adjacent top plate fingers, wherein each of the bottom plate bit fingers may be full length or half length;an insulator disposed between the top plate fingers and each of the plurality of bottom plates to thereby create capacitance between the top plate and the plurality of bottom plates bit fingers;a plurality of dummy fingers that are interleaved between some of the bit fingers to thereby provide shielding between bit fingers;wherein the plurality of bottom plate bit fingers are inputs that represent bits, wherein the bits are formed by powers of two such that the first bit has a single bit finger, the second bit has two bit fingers, the third bit has four bit fingers, and so on until all of the bits are represented by the appropriate number of bit fingers; andwherein the bit fingers for each bit are grouped so as to be adjacent to each other in bit finger groups.2. The DAC as defined in wherein the DAC is further comprised of:a first bit finger representing the first bit and being disposed at a midpoint of the DAC, wherein the first bit finger is a half finger that is defined as a single unit capacitor;two dummy fingers on ...

ANALOG-TO-DIGITAL CONVERTER FOR IMAGE PIXELS

One or more analog-to-digital converters and methods for analog-to-digital conversion are provided. The analog-to-digital converter comprises a ramp generator and a direct current (DC) generator respectively configured to apply a ramp voltage waveform and a DC voltage waveform to a comparator. During a pixel signal level conversion, a first portion of the ramp voltage waveform is applied to the comparator. A control circuit then makes a determination regarding an output of the comparator. If the output corresponds to a first output, or first logic state, the ramp voltage generator applies a second portion of the ramp voltage waveform to the comparator. If the output corresponds to a second output, or second logic state, the DC generator adjusts the DC voltage waveform applied to the comparator. 1. A method for analog-to-digital conversion , comprising:applying a first portion of a ramp voltage waveform to a comparator;making a first determination regarding an output of the comparator responsive to the applying a first portion of a ramp voltage waveform; 'applying a second portion of the ramp voltage waveform to the comparator; and', 'when, based upon the first determination, the output corresponds to a first output 'adjusting a voltage of a direct current (DC) voltage waveform applied to the comparator.', 'when, based upon the first determination, the output corresponds to a second output different than the first output2. The method of claim 1 , comprising:making a second determination regarding the output of the comparator responsive to the adjusting; and 'applying the second portion of the ramp voltage waveform to the comparator.', 'when, based upon the second determination, the output corresponds to the first output3. The method of claim 2 , comprising: 'adjusting, again, the voltage of the DC voltage waveform.', 'when, based upon the second determination, the output corresponds to the second output4. The method of claim 1 , the applying a first portion of a ramp ...

DIGITAL TO ANALOG CONVERTER CIRCUITS, APPARATUS AND METHOD FOR GENERATING A HIGH FREQUENCY TRANSMISSION SIGNAL AND METHODS OF DIGITAL TO ANALOG CONVERSION

A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

SEMICONDUCTOR DEVICE, WIRELESS SENSOR, AND ELECTRONIC DEVICE

An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is held in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped. 1. A semiconductor device comprising:a sample-and-hold circuit including a buffer circuit, a transistor, and a capacitor;a comparator;a successive approximation register;a digital-analog converter circuit; anda timing controller,wherein one of a source and a drain of the transistor is electrically connected to the buffer circuit,wherein the other of the source and the drain of the transistor is configured to hold a charge by turning off the transistor, andwherein the semiconductor device is configured to stop supply of a power supply voltage to the buffer circuit after holding the charge.2. The semiconductor device according to claim 1 ,wherein the timing controller is configured to output a signal for controlling an on/off state of the transistor.3. The semiconductor device according to claim 1 ,wherein a channel formation region of the transistor includes an oxide semiconductor.4. An electronic device comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the semiconductor device according to ; and'}a display portion.5. A wireless sensor comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the semiconductor device ...

RELAXED DIGITIZATION SYSTEM LINEARIZATION

An approach to linearization relaxes the requirements on the digitization of the analog output signal while maintaining the benefits of a high sampling rate of the output signal. The digitization approach extracts sufficient information to characterize the output signal over a wide bandwidth without necessarily determining sufficient information to fully represent the output signal, for example, without sampling the output signal at the Nyquist sampling rate with a sufficient precision to accurately represent the signal. 1. A digital predistortion linearizer , comprising:a first input to receive an input signal representative of a desired output from a plant, the desired output having a desired output bandwidth;a configurable pre-distorter to determine a driving signal representative of an input to the plant to achieve the desired output from the plant, the driving signal having a driving signal data rate equal to a product of a driving signal sampling rate and a driving signal precision;a first output to provide an output signal representative of the driving;a second input to receive an analog sensor signal representative of an achieved output from the plant;a sampler coupled to the second input to process the analog sensor signal, wherein the sampler is responsive to components of the analog sensor signal outside the desired output bandwidth in a sensor bandwidth greater than the desired output bandwidth, the sampler includes an analog to digital converter (ADC) coupled to the second input, the ADC is to provide digital outputs at a sensor signal precision lower than the driving signal precision, and the sampler is to provide a sampled sensor signal having a sensor signal data rate smaller than the driving signal data rate; andan estimator to receive the sampled sensor signal from the sampler and the driving signal determined by the pre-distorter, and to provide configuration data for configuring the pre-distorter.20. The digital predistortion linearizer of claim ...

DAC CAPACITOR ARRAY, SAR ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR REDUCING POWER CONSUMPTION THEREOF

The present disclosure relates to a method for reducing power consumption, including: connecting one terminal of each capacitor in a first and a second capacitor array of an SAR ADC to a first reference voltage via a corresponding primary switch, connecting the other terminal of the capacitors to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array. 1. A digital-to-analog converter (DAC) capacitor array , comprising:a first capacitor array and a second capacitor array, each of the capacitor array comprises:a primary switch;a plurality of multiplexers; anda capacitor group, comprising a most-significant-bit capacitor, a least-significant-bit capacitor, a supplement-bit capacitor, and at least one second-most-significant-bit capacitor;wherein one terminal of each capacitor in the first capacitor array is connected to one input terminal of a comparator and is connected to a first reference voltage via the primary switch in the first capacitor array, and the other terminal of each capacitor in the first capacitor array is connected to a plurality of input sources via a corresponding multiplexer in the first capacitor array; andone terminal of each capacitor in the second capacitor array is connected to the other input terminal of the comparator and is connected to the first reference voltage via the primary switch in the second capacitor array, and the other terminal of each ...

AMPLIFIER CIRCUITRY, AD CONVERTER, AND WIRELESS COMMUNICATION DEVICE

Amplifier circuitry has sampling circuitry which samples an input voltage, a quantizer which quantizes an output voltage of the sampling circuitry and outputs an output code, a differential amplifier which amplifies a differential voltage between the output voltage of the sampling circuitry and a reference voltage and performs offset adjustment according to the output code of the quantizer, and a first capacitor which is connected between an output node of the differential amplifier and an output node of the sampling circuitry. 1. Amplifier circuitry comprising:sampling circuitry which samples an input voltage;a quantizer which quantizes an output voltage of the sampling circuitry and outputs an output code;a differential amplifier which amplifies a differential voltage between the output voltage of the sampling circuitry and a reference voltage and performs offset adjustment according to the output code of the quantizer; anda first capacitor which is connected between an output node of the differential amplifier and an output node of the sampling circuitry.2. The amplifier circuitry according to claim 1 , whereinthe differential amplifier comprises:an offset control terminal to which the output code of the quantizer is input; andoffset control circuitry which controls an amplification factor of the differential voltage, in accordance with the output code of the quantizer input to the offset control terminal.3. The amplifier circuitry according to claim 1 , whereinthe differential amplifier adjusts a voltage of at least one of reciprocal input terminals in accordance with the output code of the quantizer and performs the offset adjustment.4. The amplifier circuitry according to claim 3 , further comprising:a DA converter which outputs an analog voltage in accordance with the output code of the quantizer, whereinthe differential amplifier amplifies a differential voltage between the output voltage of the sampling circuitry and the analog voltage.5. The amplifier ...

RAMP DIGITAL TO ANALOG CONVERTER

A source driver for a display, including: a current source that provides an approximately constant current; and multiple channels coupled to multiple source electrodes and including multiple digital to analog converters (DAC), each DAC including: a voltage source that applies a voltage to a source electrode based on the approximately constant current provided by the current source; and a control unit having circuitry that: inputs a digital value; and terminates, based on the digital value, charging of the voltage source by the approximately constant current. 1. A source driver for a display , comprising:a current source that provides an approximately constant current; and a voltage source that applies a voltage to a source electrode based on the approximately constant current provided by the current source; and', inputs a digital value; and', 'terminates, based on the digital value, charging of the voltage source by the approximately constant current., 'a control unit comprising circuitry that], 'a plurality of channels coupled to a plurality of source electrodes and comprising a plurality of digital to analog converters (DAC), each DAC comprising2. The source driver of claim 1 , wherein the voltage source is a capacitor.3. The source driver of claim 2 , wherein the capacitor is reset to a reset voltage at a start of a display line update time.4. The source driver of claim 1 , wherein the control unit comprises a counter that is set based on the digital value and that decrements claim 1 , wherein charging is terminated in response to the counter reaching zero.5. The source driver of claim 1 , wherein the control unit comprises:a latch storing the digital value;a comparator that compares the digital value with a count; andan SR register that is cleared when then the count matches the digital value, wherein charging is terminated in response to clearing the SR register.6. The source driver of claim 1 , wherein the control unit comprises a shift register loaded based ...

Comparator and analog-to-digital converter

Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.

ANALOG-TO-DIGITAL CONVERTER FOR AN IMAGE SENSOR

An analog-to-digital converter for an image sensor comprises a counter circuit to generate a respective counter bit in response to a counter state of the counter circuit, and a storage circuit for storing a respective storage state in response the respective counter bit. The converter further comprises a comparator circuit for generating a level of a comparison signal, and a synchronization circuit to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell. The counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter circuit, and to generate the write control signal, when a second edge of the cycle of the clock signal being subsequent to the first edge of the cycle of the clock signal is applied to the synchronization circuit. 1. An analog-to-digital converter for an image sensor , comprising:a counter circuit having a counter control connection to apply a clock signal and a plurality of counter output connections to generate a respective counter bit in response to a counter state of the counter circuit,a storage circuit comprising a plurality of storage cells, wherein a respective one of the storage cells is connected to a respective one of the counter output connections for storing a respective storage state in response the respective counter bit,a comparator circuit for generating a level of a comparison signal in response to a comparison of an input signal and a reference signal,a synchronization circuit to apply the comparison signal and the clock signal and to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell,wherein the counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter control connection of the counter circuit,wherein the synchronization circuit is configured to ...

DIGITAL TO ANALOG CONVERTER

A digital to analog converter includes a reference voltage generation unit that generates a reference voltage, and a plurality of unit conversion units. A number of unit conversion units to be activated are decided in response to digital codes. An activated unit conversion unit drives a control node to a voltage level corresponding to a voltage level of the reference voltage, and a deactivated unit conversion unit substantially maintains the control node to a voltage level greater than a voltage level of a ground voltage. 1. A digital to analog converter comprising:a reference voltage generation unit that generates a reference voltage; anda plurality of unit conversion units, and a number of unit conversion units to be activated being decided in response to digital codes,wherein an activated unit conversion unit drives a control node to a voltage level corresponding to a voltage level of the reference voltage, and a deactivated unit conversion unit substantially maintains the control node to a voltage level greater than a voltage level of a ground voltage.2. The digital to analog converter according to claim 1 , wherein the deactivated unit conversion unit is configured to substantially maintain the control node to the set voltage level between a voltage level of the control node of the activated unit conversion unit and the voltage level of the ground voltage.3. The digital to analog converter according to claim 1 , wherein the deactivated unit conversion unit commonly electrically couples the control node and an output node.4. The digital to analog converter according to claim 1 , wherein each of the plurality of unit conversion units receives each bit of the digital codes and is activated when one of the bits has a specific level.5. The digital to analog converter according to claim 4 , wherein each of the plurality of unit conversion units comprises:a voltage applying section that drives the control node in response to the voltage level of the reference voltage; ...

ANALOG-TO-DIGITAL CONVERTER PROBE FOR MEDICAL DIAGNOSIS AND MEDICAL DIAGNOSIS SYSTEM

Provided is an analog-to-digital converter capable of suppressing an increase in an occupation area. The analog-to-digital converter includes a multiplying digital-to-analog conversion circuit which includes a capacitance circuit that samples and amplifies an input signal, a quantizer that quantizes the input signal, and a control circuit that determines a voltage to be supplied to the capacitance circuit in accordance with an output from the quantizer. The capacitance circuit includes a first capacitance element and a second capacitance element, each of which includes a first electrode to which a normal phase signal corresponding to the input signal is supplied and a second electrode to which an opposite phase signal is supplied when the input signal is sampled. When the input signal is amplified, an output from the control circuit is supplied to the respective second electrodes, and signals from the respective first electrodes are regarded as amplified residual error amplified signal. 1. An analog-to-digital converter comprising:at least one multiplying digital-to-analog conversion circuit that includes an input node to which an input signal is supplied, an output node which supplies an output signal, and a quantizer which quantizes the input signal based on a reference voltage,wherein the output signal of the multiplying digital-to-analog conversion circuit is supplied to the input node of the multiplying digital-to-analog conversion circuit or to the input node of the multiplying digital-to-analog conversion circuit via a different multiplying digital-to-analog conversion circuit,wherein the multiplying digital-to-analog conversion circuit includes a capacitance circuit that samples and amplifies the input signal supplied to the input node and supplies the amplified input signal to the output node, and a control circuit that determines a voltage to be supplied to the capacitance circuit in accordance with an output from the quantizer, a first capacitance element ...

Parallel Sample-and-Hold Circuit for a Pipelined ADC

A parallel sample-and-hold circuit includes a sampling switch and a hold capacitor for each of the ADC and MDAC of a converter stage for a pipelined ADC. Each sampling switch couples the analog input of the first converter stage to its hold capacitor at the time a sample is desired to be taken. After the sample is placed on the hold capacitor, the sampling switch is opened and the hold capacitor stores the sample. To compensate for mismatches in the signal paths of these sample-and-hold circuits, a compensation switch is further used. The compensation switch couples the terminals of the hold capacitors together, creating a parallel sample-and-hold circuit. The compensation switch is controlled such that it is closed after the sampling switches are opened to equalize a voltage of the samples. 1. A converter stage for a pipelined analog-to-digital converter (ADC) , comprising:an ADC configured to convert a first sample of an analog signal into a digital value, wherein the ADC comprises a first sampling switch configured to couple the analog signal to a first hold capacitor to store the first sample of the analog signal on the first hold capacitor;a multiplying digital-to-analog converter (MDAC) configured to convert the digital value into an analog value and subtract the analog value from a second sample of the analog signal to provide a residue, wherein the MDAC comprises a second sampling switch configured to couple the analog signal to a second hold capacitor to store the second sample of the analog signal on the second hold capacitor;a first compensation switch coupled between a first terminal of the first hold capacitor and a first terminal of the second hold capacitor; anda second compensation switch coupled between a second terminal of the first hold capacitor and a second terminal of the second hold capacitor.2. The converter stage of claim 1 , wherein the first compensation switch is configured to equalize a voltage of the first sample of the analog signal on ...

ANALOG TO DIGITAL CONVERTER

An analog to digital converter is disclosed herein. The analog to digital converter includes a bit conversion module and a control module. The bit conversion module is configured to generate a quantization output in accordance with an input signal. The control module is configured to control the bit conversion module, so as to make the bit conversion module operate in one of a sigma delta mode and a successive approximation mode. 1. An analog to digital converter comprising:a bit conversion module configured to generate a quantization output in accordance with a first input signal and a second input signal; anda control module configured to control the bit conversion module, so as to make the bit conversion module operate in one of a sigma delta mode and a successive approximation mode.2. The analog to digital converter of claim 1 , wherein the bit conversion module comprises a switching circuit claim 1 , the switching circuit comprises:an amplifier comprising two input terminals and two output terminals;a first reset switch electrically coupled between the two input terminals of the amplifier; anda second reset switch electrically coupled between the two output terminals of the amplifier;wherein the first reset switch and the second reset switch are turned off in accordance with a configuration of the control module when the bit conversion module operates in the sigma delta mode, and the first reset switch and the second reset switch are selectively turned on based on a first clock signal in accordance with the configuration of the control module when the bit conversion module operates in the successive approximation mode.3. The analog to digital converter of claim 2 , wherein the switching circuit comprises:a first switch configured to receive the first input signal and being selectively turned on based on the first clock signal;a second switch configured to receive the second input signal and being selectively turned on based on the first clock signal;a third ...

ANALOG/DIGITAL CONVERTER

An analog/digital converter includes: a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period; a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; and a first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and wherein the second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage. 1. An analog/digital converter comprising:a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period;a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; anda first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and whereinthe second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage.2. The analog/digital converter according to claim 1 , whereinthe second analog/digital conversion unit performs digital conversion on lower bits that follow bits on which digital conversion is performed in the first analog/digital conversion unit.3. The analog/digital converter according to claim 1 , whereinin the first time period, when the first analog/digital conversion unit executes movement ...

Activity detection

This application relates an activity detector ( 100 ) for detecting signal activity in an input audio signal (S IN ), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) 101 including a first hysteretic comparator ( 201 ) for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM ( 103 ) having a second hysteretic comparator ( 401 ) is arranged to receive a reference voltage (V MID ) and generate a clock signal (S CLK ). A time-decoding converter ( 102 ) receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor ( 104 ) is responsive to a count signal (S CT ) from the TDC 102 to determine whether the input audio signal comprises signal activity above a defined threshold.

SENSOR DEVICE INCLUDING HIGH-RESOLUTION ANALOG TO DIGITAL CONVERTER

Provided is a sensor device including: a sensor unit converting a voltage of a periodically switched capacitor into a pulse signal by referring to a clock signal to provide the pulse signal as a first sensing signal; and a high-resolution analog to digital converter (ADC) amplifying a period of the first sensing signal 2times (n is an integer), amplifying a period of the clock signal 2times, and generating a second sensing signal where a switching time of the capacitor is removed by removing the amplified clock signal from the amplified first sensing signal. 1. A sensor device comprising:a sensor unit converting a voltage of a periodically switched capacitor into a pulse signal by referring to a clock signal to provide the pulse signal as a first sensing signal; and{'sup': n', 'n−1, 'a high-resolution analog to digital converter (ADC) amplifying a period of the first sensing signal 2times (n is an integer), amplifying a period of the clock signal 2times, and generating a second sensing signal where a switching time of the capacitor is removed by removing the amplified clock signal from the amplified first sensing signal.'}2. The sensor device of claim 1 , wherein the sensor unit comprises:a first current source providing a charging current for charging the capacitor;a switch discharging the capacitor according to a switch control signal provided from the high-resolution ADC; anda comparator comparing the voltage of the capacitor with a reference voltage to output a comparison result as the first sensing signal.3. The sensor device of claim 2 , wherein the capacitor comprises a variable capacitance capacitor varying according to an external physical/chemical change.4. The sensor device of claim 2 , wherein the sensor unit comprises:a second current source providing the reference voltage; anda variable resistor providing the reference voltage according to a current provided from the second current source,wherein the capacitor is provided as a fixed capacitance ...

Ad converter

A successive approximation type AD converter includes: a comparator comparing an analog input signal and a DA-converted comparison code; and a control circuit. When an output of the comparator settles before a limit time period has passed since the comparator started a comparison operation, the control circuit updates the comparison code on the basis of the settled output of the comparator. When the limit time period has passed before the output of the comparator settles, the control circuit updates the comparison code not on the basis of the present output of the comparator.

A/D CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT

According to one embodiment, an A/D converter includes a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series. The converter includes a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series. The converter includes an encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column. 1. An A/D converter comprising:a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series;a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series; andan encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column.2. The A/D converter according to claim 1 , wherein the encoder unit is configured to encode a value which is ½ of the difference value claim 1 , in delay time of signal propagation claim 1 , between the first delay cell column and the second delay cell column claim 1 , and is configured to output an encoded value.3. The A/D converter according to claim 2 , further comprising a differential amplifier circuit configured to compare the input voltage and the reference voltage claim 2 , wherein the first and the second bias currents are generated by using two outputs of the differential amplifier circuit.4. The A/D converter according to claim 3 , further comprising:a second ...

BODY-BIASED SLICER DESIGN FOR PREDICTIVE DECISION FEEDBACK EQUALIZERS

A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC. 1. A receiver with predictive decision feedback equalization , the receiver comprising:a first differential amplifier comprising a first field effect transistor (FET) and a second FET, the first FET and the second FET being connected in a differential pair configuration;a voltage-mode digital to analog converter (DAC) comprising a first DAC output, the first DAC output being connected to a bulk terminal of the first FET; anda DAC voltage limit circuit connected to the DAC.2. The receiver of claim 1 , wherein the DAC comprises:a DAC resistor,a plurality of branches, anda bias control input;and wherein the DAC voltage limit circuit comprises:a reference voltage input connected to a common node of the first differential amplifier, anda replica circuit having a replica voltage output, the replica circuit comprising a scaled replica of a branch of the plurality of branches of the DAC.3. The receiver of claim 2 , wherein each of the plurality of branches of the DAC comprises a branch current source.4. The receiver of wherein the branch current source of a first branch of the DAC comprises a FET having a first gate width claim 3 , the gate of the FET connected to the bias control input of the DAC claim 3 , and the branch current sources of a remainder of the branches of the plurality of ...

SEMICONDUCTOR DEVICE, WIRELESS SENSOR, AND ELECTRONIC DEVICE

An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is hold in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped. 1. (canceled)2. A semiconductor device comprising:a sample-and-hold circuit including a transistor including an oxide semiconductor containing indium and oxide in a channel formation region and a capacitor;a comparator electrically connected to one of a source and a drain of the transistor and the capacitor;a successive approximation register electrically connected to the comparator;a digital-analog converter circuit electrically connected to the successive approximation register and the comparator; anda timing controller electrically connected to a gate of the transistor, the successive approximation register, and the digital-analog converter circuit,wherein the other of the source and the drain of the transistor is electrically connected to an input terminal of the sample-and-hold circuit.3. The semiconductor device according to claim 2 ,wherein the timing controller is configured to output a signal for controlling an on/off state of the transistor.4. An electronic device comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'the semiconductor device according to ; and'}a display portion.5. A wireless sensor comprising:{'claim- ...

Analog-to-digital converter

A system includes an analog-to-digital converter receiving a plurality of input signals. One particular input signal has a particular analog value and the analog-to-digital converter uses a fixed reference to convert the particular analog value to a particular digital value. The analog-to-digital converter uses the particular analog value as a reference for converting the analog values of the remaining input signals.

COMPARATOR CIRCUITS WITH LOCAL RAMP BUFFERING FOR A COLUMN-PARALLEL SINGLE-SLOPE ADC

A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter comprises a comparator, an input voltage sampling switch, a sampling capacitor arranged to store a voltage which varies with an input voltage when the sampling switch is closed, and a local ramp buffer arranged to buffer a global voltage ramp applied at an input. The comparator circuit is arranged such that its output toggles when the buffered global voltage ramp exceeds the stored voltage. Both DC- and AC-coupled comparator embodiments are disclosed. 1. A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter , said comparator circuit comprising:an input node;a comparator;an input voltage sampling switch coupled to said input node;a sampling capacitor arranged to store a voltage which varies with an input voltage applied to said input node when said sampling switch is closed; anda local ramp buffer having an associated input and arranged to buffer a global voltage ramp applied directly to said local ramp buffer's input;said comparator circuit arranged such that the output of said comparator toggles when said buffered global voltage ramp exceeds said stored voltage.2. The comparator circuit of claim 1 , wherein said stored voltage is applied at a first input terminal of said comparator and said buffered global voltage ramp is applied at said comparator's second input terminal.3. The comparator circuit of claim 2 , wherein said sampling capacitor is connected between said comparator's first input terminal and a circuit common point and said sampling switch is connected between said input voltage and said comparator's first input terminal.4. The comparator circuit of claim 3 , said comparator circuit arranged to receive timing signals which operate said sampling switch such that said voltage is stored on said sampling capacitor before said global voltage ramp starts to ramp.5. A comparator circuit suitable for use in a column- ...

MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS), APPARATUS, AND OPERATING METHODS THEREOF

A method that comprises converting a first electrical signal to a second electrical signal using a converter coupled between a micro-mechanical structure and an analog-to-digital converter (ADC). The method also comprises actuating a switch to selectively interpolate at least one datum between two neighboring converted second electrical signals based on a selected clock signal, wherein the selected clock signal is one of a plurality of clock signals, each clock signals of the plurality of clock signals has a corresponding frequency, and the selected clock signal corresponds to an operating mode of the micro-mechanical structure. 1. A method comprising:converting a first electrical signal to a second electrical signal using a converter coupled between a micro-mechanical structure and an analog-to-digital converter (ADC), andactuating a switch to selectively interpolate at least one datum between two neighboring converted second electrical signals based on a selected clock signal,wherein the selected clock signal is one of a plurality of clock signals, each clock signals of the plurality of clock signals has a corresponding frequency, and the selected clock signal corresponds to an operating mode of the micro-mechanical structure.2. The method of claim 1 , further comprising:determining if the micro-mechanical structure operates at a power saving mode, a normal mode or a high performance mode.3. The method of claim 1 , further comprising:detecting if an intermediate signal between the converter and the ADC is substantially smaller than a predetermined value for a predetermined interval.4. The method of claim 1 , wherein the operating mode of the micro-mechanical is a power saving mode if the first electrical signal is substantially smaller than a predetermined value for a predetermined interval.5. The method of claim 1 , wherein the actuating a switch to selectively interpolate the at least one datum is performed if the operating mode of the micro-mechanical structure ...

ANALOG-TO-DIGITAL CONVERSION WITH NOISE INJECTION VIA WAVEFRONT MULTIPLEXING TECHNIQUES

A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality. 1. An apparatus for processing signals , comprising:a first processor configured to receive a first signal and a second signal and generate a third signal containing information from said first and second signals;a second processor configured to apply a vector to recover information associated with said third signal into a first output associated with said first signal and a second output associated with said second signal; andan optimizer configured to adjust said vector.2. The apparatus of claim 1 , wherein said optimizer is configured to adjust said vector for recovering said information associated with said third signal into said first output associated with said first signal and said second output of substantial zero.3. The apparatus of claim 1 , wherein said optimizer is configured to adjust said vector for recovering said information associated with said third signal into said first output of substantial zero and said second output of substantial zero.4. The apparatus of claim 1 , wherein said second signal comprises a ground signal.5. The apparatus of further comprising an analog-to-digital converting block configured to sample said third signal to be in a digital format claim 1 , wherein said second processor is configured to apply said wave-front vector to recover information associated with said third signal in a digital format into said first and second outputs.6. The apparatus of claim 1 , wherein said first processor is configured to ...

SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER

Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. 1. A system for providing a pipelined Analog-to-Digital Converter , comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal;', 'at least two reference capacitors that are charged to a reference voltage;', 'at least two sampling capacitors that are charged to a sampling voltage: and', 'a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage., 'a first multiplying Digital-to-Analog Converter (MDAC) stage comprising2. The system of claim 1 , wherein the first MDAC stage further comprises a first current source coupled to a first of the at least two reference capacitors and a ...

Dac capacitor array, analog-to-digital converter, and method for reducing power consumption of analog-to-digital converter

This disclosure discloses a DAC capacitor array, which includes a plurality of sub-capacitor arrays that are connected in parallel. Each sub-capacitor array includes: a capacitor group, including N capacitors connected in parallel, N being a positive integer; and a primary switch and a plurality of multiplexers; wherein one terminal of each capacitor in the capacitor group is connected to an input terminal of a comparator, and is connected to an input source via the primary switch; and the other terminals of the capacitors in the capacitor group are connected to a plurality of input sources via corresponding multiplexers respectively. The DAC capacitor array is optimized by adjusting the reference voltage to which the capacitors in the DAC capacitor array are connected, which reduces the overall capacitance of the DAC capacitor array.

SEMICONDUCTOR INTEGRATED CIRCUIT

A semiconductor circuit includes: an analog circuit that inputs a measured signal; and a digital circuit that outputs a digital output signal. The analog circuit includes: a correction element group including one or more correction elements each for correcting an offset that is an amount of shift caused by a variation in characteristics of the analog circuit to occur in a path for transmitting the measured signal; and a test element group including one or more test elements for testing the one or more correction elements. The digital circuit tests the correction element group using the test element group. 1. A semiconductor circuit including a data converter that outputs a digital output signal corresponding to a measured signal , the semiconductor circuit comprising:an analog circuit that quantizes the measured signal inputted; anda digital circuit that outputs the digital output signal, a correction element group including one or more correction elements each for correcting nonlinearity that occurs during a process of converting the measured signal into the digital output signal in the analog circuit; and', 'a test element group including one or more test elements for testing the one or more correction elements, and, 'wherein the analog circuit includesthe digital circuit tests the correction element group using the test element group.2. The semiconductor circuit according to claim 1 , a self-diagnostic code generation circuit that generates a self-diagnostic code for (i) enabling or disabling each of the one or more correction elements included in the correction element group and (ii) enabling or disabling each of the one or more test elements included in the test element group;', 'an error detection circuit that detects, as an error signal, a difference between a quantizer output signal of the analog circuit and a predetermined threshold value, the quantizer output signal being outputted in response to the self-diagnostic code; and', 'a self-diagnostic circuit ...

POWER AMPLIFIER WITH NULLING MONITOR CIRCUIT

Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit. 1. A method of reducing an amount of distortion in an output signal of a power amplifier circuit in a wired communication network , the method comprising:receiving an input signal at a first input of the power amplifier circuit;using a distortion monitoring circuit in the power amplifier circuit, generating a distortion feedback signal resolved from an intended output signal at a first output of the power amplifier circuit; andgenerating the output signal from the intended output signal at a second output of the power amplifier circuit.2. The method of claim 1 , wherein using the distortion monitoring circuit in the power amplifier circuit claim 1 , generating the distortion feedback signal resolved from the intended output signal at the first output of the power amplifier circuit includes:cross-coupling first and second transistors that are coupled to the input of the power amplifier circuit, each of the first and second transistors including a control terminal;coupling a first resistor network between the control terminal of first transistor and a second terminal of the second transistor, and coupling a second resistor network between the control terminal of second transistor and a second terminal of the first transistor; andcoupling a first node in the first resistor network and a second node in the second ...

Successive approximation analog-to-digital converter and conversion method

The present invention discloses a successive approximation analog-to-digital converter capable of improving the accuracy of analog-to-digital conversion. An embodiment of this converter comprises: a successive approximation analog-to-digital converting circuit operable to generate M bits according to an analog input signal in which the M bits include a most significant bit (MSB) and successive M−1 bit(s) in succession to the MSB while the number M is an integer greater than one; and a multi-bit generating circuit operable to receive a capacitor array output signal and a comparison signal outputted from the successive approximation analog-to-digital converting circuit for a predetermined time after the generation of the M bits, and then generate N bits at a time accordingly in which the N bits include a least significant bit (LSB) and successive N−1 bit(s) ahead of the LSB while the number N is an integer greater than one. 1. A successive approximation analog-to-digital converter capable of improving the accuracy of analog-to-digital conversion , comprising:a successive approximation analog-to-digital converting circuit operable to generate M bits according to an analog input signal in which the M bits include a most significant bit (MSB) and successive M−1 bit(s) in succession to the MSB while M is an integer greater than one; and an accumulation signal generating circuit operable to accumulate a capacitor array output signal and a comparison signal from the successive approximation analog-to-digital converting circuit after the generation of the M bits and thereby generate an accumulation signal; and', 'a multibit analog-to-digital converting circuit operable to generate N bits according to the accumulation signal in which the N bits include a least significant bit (LSB) and successive N−1 bit(s) ahead of the LSB while N is an integer greater than one., 'a multibit generating circuit including2. The successive approximation analog-to-digital converter of claim 1 , ...

ANALOGUE-TO-DIGITAL CONVERTER

This application relates to analogue-to-digital converters (ADCs). An ADC has a first converter () for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator () for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter () receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (). A gain allocation block () generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block () may have a second PWM-to-digital modulator () which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (). 1. An analogue-to-digital converter for converting an analogue input signal into a corresponding digital output signal comprising:a first converter for receiving said analogue input signal and outputting a pulse-width-modulated (PWM) signal based on said analogue input signal and a first conversion gain setting, said first converter comprising a PWM modulator for generating said PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time,a second converter for receiving said PWM signal and outputting said digital output signal based on said PWM signal and a second conversion gain setting, said second converter comprising a first PWM-to-digital modulator; anda gain allocation block for generating said first and second conversion gain settings based on said PWM signal.2. An analogue to digital converter as claimed in wherein said gain allocation block comprises a second PWM-to-digital modulator configured to receive a version of ...

Monotonic Segmented Digital to Analog Converter

In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word. 1. (canceled)2. A method comprising:receiving an input analog signal indicative of a light output of a laser;determining an input binary word, wherein the binary word includes a plurality of most significant bits and a plurality of least significant bits;decoding the input binary word to an intermediate value including a bit width equal to or greater than a bit width of the binary word;setting a plurality of output switches according to the intermediate value, wherein the plurality of output switches includes one or more switches for states of the plurality of most significant bits and one or more switches for states of the plurality of least significant bits; andproviding an analog output signal that represents the input binary word, wherein the analog output signal is controlled by the plurality of output switches.3. The method of claim 2 , wherein the input analog signal describes a light intensity of the light output of the laser.4. The method of claim 2 , wherein the input analog signal describes a temperature of the light output of the laser.5. The method of claim 2 , further comprising:setting a plurality of current source switches according to the intermediate value, wherein the plurality of current source switches includes one or more switches for states of the plurality of most significant bits.6. The method of ...

AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE

An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal. 1. An apparatus comprising:a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal;a digital loop filter configured to generate a fine tuning signal based on the phase difference signal;a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal; anda divider configured to generate a divider frequency based on a divider control signal and the output signal,wherein the phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.2. The apparatus of claim 1 , further comprising:a phase difference detector configured to generate the phase difference signal based on a comparison of the reference frequency and the divider frequency.3. The apparatus of claim 2 , wherein the phase difference detector comprises a time-to-digital converter (TDC) circuit.4. The apparatus of claim 3 , wherein the phase difference detector further comprises an analog-to-digital converter (ADC) circuit.5. The apparatus of claim 1 , wherein the code generator comprises:a first comparator configured to generate a ...

Current amplifier circuit, integrator, and ad converter

In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.

METHOD AND CIRCUIT FOR AN ANALOG DIGITAL CAPACITY CONVERTER

A method for converting a capacitance of a sensing capacitor () to be measured into a digital signal is described, wherein according to a clocking in charging processes an integrating capacitor (), discharged before a start of conversion, of an integrator circuit is charged by an electric current which is obtained from a charging of the sensing capacitor () and in discharge processes by brief current surges in the opposite direction which are obtained from a charging of a reference capacitor (), with the result that on average no charge builds up, and the number of discharge processes occurring during a particular number of clock pulses is counted, wherein the clocking is paused after a predetermined number of cycles, a residual voltage (VA1), which the integrator circuit emits due to a residual charge of the integrating capacitor (), is converted by means of analogue-to-digital voltage conversion () into a digital value and the counted number of discharge processes and the particular number of clock pulses are combined with the digital value emitted by the analogue-to-digital voltage converter () to form a digital total result, wherein least significant bits of the total result are defined on the basis of the digital value emitted by the analogue-to-digital voltage converter () and most significant bits of the total result are defined on the basis of the counted number of discharge processes and the particular number of clock pulses. 19-. (canceled)10. An analog-to-digital capacitance converter for converting a capacitance of a sensing capacitor to be measured into a digital signal , the converter comprising: an operational amplifier including an output, an inverting input and a non-inverting input, wherein an integrating capacitor is connected between the inverting input and the output, and wherein the non-inverting input is connected to a neutral reference potential;', 'a reference capacitor, including a first electrode and a second electrode, wherein the first ...

DIFFERENTIAL VOLTAGE-TO-DELAY CONVERTER WITH IMPROVED CMRR

A voltage-to-delay converter converts input signals into delay signals, and includes: a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; and a second stage for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltage of the rail-to-rail output signals corresponds to the rail-to-rail voltage. A voltage-to-delay converter block is also described. A circuit for receiving differential input signals, generating corresponding output signals, and removing common mode signals from the output signals is also described. 1. A multi-stage voltage-to-delay converter for converting input signals into delay signals , comprising:a first stage for receiving the input signals and for generating intermediate output signals, wherein timing of the intermediate output signals corresponds to voltages of the input signals, and wherein the first stage has a voltage source for providing a rail-to-rail voltage; anda second stage, connected to the first stage, for receiving the intermediate output signals and for generating rail-to-rail output signals, wherein timing of the rail-to-rail output signals corresponds to the timing of the intermediate output signals, and wherein voltages of the rail-to-rail output signals correspond to the rail-to-rail voltage of the voltage source.2. The voltage-to-delay converter of claim 1 , further comprising an in-built threshold circuit for providing a threshold voltage claim 1 , and wherein the timing of the intermediate output signals corresponds to differences between the threshold voltage and the voltages of the input signals.3. The voltage-to-delay converter of claim 2 , ...

SAR ADCS WITH DEDICATED REFERENCE CAPACITOR FOR EACH BIT CAPACITOR

A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated). 1. A successive-approximation-register analog-to-digital converter (SAR ADC) for converting an analog input to a digital output with signal-independent bit weights , the SAR ADC comprising:first bit capacitors corresponding to a first bit weight, wherein the first bit capacitors directly sample the analog input;a first on-chip reference capacitor to share charge with the first bit capacitors during conversion phase of a first bit trial;second bit capacitors corresponding to a second bit weight, wherein the second bit capacitors directly sample the analog input; anda second on-chip reference capacitor, separate from the first on-chip reference capacitor, to share charge with the second bit capacitors during conversion phase of a second bit trial.2. The SAR ADC of claim 1 , further comprising:first sample switches to connect bottom plates of the first bit capacitors to the analog input; andsecond sample switches to connect bottom plates of the first bit capacitors to the analog input.3. The ...

LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR

In a system for converting digital data into a modulated optical signal, an electrically controllable device, including a modulator having one or more actuating electrodes, provides an analog-modulated optical signal that is modulated in response to output data bits of a digital-to-digital mapping. A digital-to-digital conversion provides the mapping of input data words to the output data bits. The mapping enables adjustments to correct for non-linearities and other undesirable characteristics, thereby improving signal quality. 1. An optical modulation system , the system comprising:an input for receiving digital input words, each digital input word comprising a plurality of input data bits;an input optical signal,wherein the optical modulation system, based on a mapping, maps a digital input word received at the input to a corresponding digital output word comprising a plurality of output data bits,wherein the mapping specifies, for each digital input word included in a set of possible digital input words for the plurality of input data bits, a corresponding digital output word from a set of possible digital output words for the plurality of output data bits,wherein, for a first subset of digital input words specified in the mapping and having increasing values, deltas between values of digital output words in the set of possible digital output words, corresponding respectively to digital input words in the first subset, decrease,wherein, for a second subset of digital input words specified in the mapping and having increasing values, deltas between values of digital output words in the set of possible digital output words, corresponding respectively to digital input words in the second subset, increase, andwherein the optical modulation system further comprises a modulator for modulating the input optical signal responsively to the digital output word mapped from the digital input word, thereby generating one or more modulated optical signal outputs for ...