УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

Группа изобретений относится к области обработки данных и может быть использована для кодирования/декодирования с использованием LDPC-кода. Техническим результатом является повышение устойчивости LDPC-кода к возникновению ошибок. LDPC-код включает в себя бит информации и бит четности. Матрица контроля четности включает в себя часть информационной матрицы, соответствующую битам информации, и часть матрицы четности, соответствующую битам четности. Часть информационной матрицы представлена таблицей начальных значений матрицы контроля четности. Таблица начальных значений матрицы контроля четности представляет собой таблицу, показывающую позиции элементов 1 части информационной матрицы каждые 360 столбцов. 12 н. и 60 з.п. ф-лы, 130 ил.

СПОСОБ И УСТРОЙСТВО ДЛЯ КАНАЛЬНОГО КОДИРОВАНИЯ И ДЕКОДИРОВАНИЯ В СИСТЕМЕ СВЯЗИ, В КОТОРОЙ ИСПОЛЬЗУЮТСЯ КОДЫ КОНТРОЛЯ ЧЕТНОСТИ С НИЗКОЙ ПЛОТНОСТЬЮ

Изобретение относится к системе связи, использующей коды Контроля Четности с Низкой Плотностью (Low-Density Parity-Check, LDPC), и, в частности, к устройству и способу канального кодирования/декодирования для генерации LDPC-кодов с разными длинами кодового слова и разными скоростями кодирования из LDPC-кода, заданного в модуляции высшего порядка. Техническим результатом является повышение производительности канального кодирования/декодирования в системе связи, где применяются LDPC-коды. Указанный результат достигается тем, что в способе кодирования определяют схему модуляции для передачи символа; определяют шаблон сокращения с учетом определенной схемы модуляции; группируют столбцы, соответствующие информационному слову в матрице контроля четности LDPC-кода в множество групп столбцов; упорядочивают группы столбцов; определяют диапазон результирующего информационного слова, который желательно получить посредством сокращения информационного слова; на основании диапазона результирующего информационного ...

УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

... 1. Устройство обработки данных, содержащее:блок кодирования, который кодирует информационный бит в LDPC-код, имеющий длину кода 16200 битов и кодовую скорость 12/15, на основании матрицы контроля четности кода разреженного контроля четности (LDPC),где LDPC-код включает в себя информационный бит и бит четности,где матрица контроля четности включает в себя информационную часть матрицы, соответствующую информационному биту, и часть матрицы четности, соответствующую биту четности,где информационная часть матрицы представлена таблицей начальных значений матрицы контроля четности игде таблица начальных значений матрицы контроля четности представляет собой таблицу, представляющую позиции элементов 1 в информационной части матрицы с интервалом 360 столбцов, и представляет собой2. Устройство обработки данных по п. 1,в котором, если строка исходной таблицы матрицы контроля четности представлена i и длина битов четности LDPC-кода представлена М,(2+360×(i-1))-й столбец матрицы контроля четности представляет ...

УЛУЧШЕННОЕ ВЫКАЛЫВАНИЕ И СТРУКТУРА КОДА С МАЛОЙ ПЛОТНОСТЬЮ ПРОВЕРОК НА ЧЕТНОСТЬ (LDPC)

Группа изобретений относится к беспроводной связи и может быть использована для улучшенного выкалывания и структуры кода с малой плотностью проверок на четность (LDPC). Техническим результатом является улучшение производительности выкалываемых LDPC кодов. Способ содержит этапы, на которых кодируют набор информационных битов на основе LDPC-кода для создания кодового слова, причем LDPC-код определен базовой матрицей, имеющей первое число переменных узлов и второе число контрольных узлов; выкалывают посредством модуля выкалывания устройства беспроводной связи согласно шаблону выкалывания биты в кодовом слове, соответствующие по меньшей мере двум из первого числа переменных узлов в базовой матрице, для создания выколотого кодового слова, причем базовая матрица включает в себя по меньшей мере один дополнительный переменный узел для упомянутых по меньшей мере двух выколотых переменных узлов, и при этом каждый дополнительный переменный узел связан с одним контрольным узлом, причем контрольный ...

СПОСОБЫ И СИСТЕМЫ КОДИРОВАНИЯ И ДЕКОДИРОВАНИЯ LDPC КОДОВ

Группа изобретений относится к технологиям мобильного радиоинтерфейса и может быть использована для кодирования и декодирования кодов с низкой плотностью проверок на четность (LDPC). Техническим результатом является создание новой матрицы для кодирования и декодирования кодового слова. Способ содержащий этапы, на которых: принимают векторстроки исходного слова 1 x K и генерируют векторкодового слова 1 x N, где G является K x N порождающей матрицей, и G получают из матрицы Hпроверки на четность, Hимеет коэффициент Z поднятия, и Hсодержит множество подматриц, причем каждая подматрица имеет размер Z x Z, при этом по меньшей мере одна подматрица имеет mдиагонали «1», где mявляется целым числом > = 2, причем K = 588, а новая матрица Hсодержит 84 строки x 672 столбца. 3 н. и 10 з.п. ф-лы, 34 ил.

СПОСОБ И УСТРОЙСТВО ГЕНЕРИРОВАНИЯ ГИБРИДНОГО ПОЛЯРНОГО КОДА

СПОСОБ И УСТРОЙСТВО ДЛЯ КАНАЛЬНОГО КОДИРОВАНИЯ И ДЕКОДИРОВАНИЯ В СИСТЕМЕ СВЯЗИ, В КОТОРОЙ ИСПОЛЬЗУЮТСЯ КОДЫ КОНТРОЛЯ ЧЕТНОСТИ С НИЗКОЙ ПЛОТНОСТЬЮ

... 1. Способ для декодирования канала с использованием кода Контроля Четности с Низкой Плотностью (LDPC), причем способ содержит этапы, на которых:демодулируют принятый сигнал;определяют позицию сокращенных информационных битов; идекодируют демодулированный сигнал, принимая во внимание определенную позицию сокращенных информационных битов,причем определение позиции сокращенных информационных битов содержитопределение числа информационных битов, которые должны быть сокращены; иопределение числа групп битов, которые должны быть сокращены на основе определенного числа информационных битов, которые должны быть сокращены; иполучают предварительно определенный порядок групп битов.2. Способ по п.1, в котором определение позиции сокращенных информационных битов дополнительно содержит:определение числа информационных битов, которые необходимо получить посредством сокращения, для определения числа информационных битов, которые должны быть сокращены.3. Способ по п.1, в котором предварительно определенный ...

СИСТЕМЫ И СПОСОБЫ ДЛЯ КОДИРОВАНИЯ НЕПОЛНОГО РАНГА

... 1. Система обработки данных, содержащая:цепь кодера, выполненную с возможностьюприема входных пользовательских данных;матричного умножения входных пользовательских данных на первый квазициклический компонент четности для получения первого промежуточного значения;матричного умножения первого промежуточного значения на обратный левый множитель-компонент нормальной формы Смита для получения второго промежуточного значения;матричного умножения второго промежуточного значения на псевдообратный диагональный множитель-компонент нормальной формы Смита для получения третьего промежуточного значения;матричного умножения третьего промежуточного значения на обратный правый множитель-компонент нормальной формы Смита для получения первой части четности;матричного умножения первой части четности на второй квазициклический компонент четности для получения четвертого промежуточного значения; ивекторного сложения первого промежуточного значения с четвертым промежуточным значением для получения второй части ...

VERFAHREN UND VORRICHTUNG ZUM REDUZIEREN VON MIKROBONDHÜGELN FÜR EINE DOUBLE-DATA RATE (DDR)-ÜBERTRAGUNG ZWISCHEN DIES

Es wird ein Regime zur Datenübertragung mit doppelter Datenrate (Double Data Rate, DDR) zwischen Dies bereitgestellt. Insbesondere verwendet das Datenübertragungsregime ein Fehlerkorrekturcode (Error Correction Code, ECC)-Codierregime, das sich die DDR-Eigenschaft zunutze macht, dass ein einzelner Mikrobondhügeldefekt nur vier mögliche Fehlerszenarien ergeben kann. Ein spezialisiertes Single Error Correcting-, Double Error Detecting- and Double Adjacent Error Correcting (SEC-DED-DAEC)-Codierregime, das mindestens vier einschränkende Bedingungen für eine Paritätsprüfungsmatrix auferlegt, kann verwendet werden. Auf diese Weise konfiguriert und betrieben, ist eine geringere Anzahl von Paritätsprüfbits erforderlich, um Datenbitfehler zu detektieren, die mit einem einzelnen defekten Mikrobondhügel verknüpft sind.

Error-correction encoding and decoding

Encoding data supplied to a data channel using a quarter product code CQ, having identical row and column codes and being reversible, whereby a codeword corresponds to a triangular sub-array of a square matrix confined between its diagonal and anti-diagonal. K input data symbols are stored for encoding. The K input data symbols are assigned to respective symbol locations in a notional square array, having n rows and n columns of symbol locations, to define a plurality of k-symbol words in respective rows of the array. The k-symbol words are encoded by encoding rows and columns of the array in dependence on a product code C having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n. This encoding is performed so as to define a codeword, having n2 code symbols corresponding to respective locations of said array, of a quarter product code CQ defined by CQ = { X − XT − (X − XT)F } where X is an (n by n)-symbol matrix defining a ...

Coding technique

Polar encoder, communication unit, integrated circuit and method therefor

A polar encoder kernal (102) is described. The polar encoder kernal (102) is configured to receive one or more bits from a kernal information block (105) having a kernal block size of N; and output one or more bits from a kernal encoded block (106) having a block size that matches the kernel block size N; wherein the polar encoder kernal (102) comprises a decomposition of a polar code graph having multiple columns (702) and where each column is further decomposed into one or more polar code sub-graphs (701) and is configured to process encoded bits one polar code subgraph (701) at a time.

Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes

Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted quasi-cyclic low-density parity-check (LDPC) codes. A method for wireless communications by a transmitting device generally includes selecting a first lifting size value Z and a first set of lifting values for generating a first lifted LDPC code (1302). The first lifted LDPC code is generated by applying the first set of lifting values to interconnect edges in Z copies of a base parity check matrix (PCM) to obtain a first lifted PCM corresponding to the first lifted LDPC code (1304). The method further includes determining a second set of lifting values for generating a second lifted PCM corresponding to a second lifted LDPC code for a second lifting size value based on the first set of lifting values (1306), encoding a set of information bits based on at least one of the first lifted LDPC code or the second lifted LDPC code to produce a code word (1308) and transmitting the code word ...

Decoding device and method and signal transmission system

Embodiments of the present invention disclose a decoding device. By performing processing in a case in which a value of an updated code element exceeds a code element quantization range in a process of updating a code word of an LDPC code, the decoding device selectively abandons an update in the case in which the updated code element exceeds the code element quantization range, which prevents the decoding device from directly quantizing an updated code word that exceeds the code element quantization range, and improves an error correction capability of the decoding device in a decoding process. Decoding device 600 Acquiring unit 602 Storage module Variable node processing unit 6042 Check node processing unit 6044 Processing unit 604 Determining unit 606 ...

MULTIPLE LOW DENSITY PARITY CHECK (LDPC) BASE GRAPH DESIGN

Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

ENCODING AND DECODING OF QC-LDPC CODES WITH PAIRWISE ORTHOGONALITY OF ADJACENT ROWS IN THEIR BASE MATRICES

Certain aspects of the present disclosure provide quasi-cyclic low-density parity-check (QC-LDPC) codes having pairwise orthogonality of adjacent rows of the corresponding base matrices, and a new decoder (e.g. layered decoder) that exploits the pairwise row orthogonality for flexible decoder scheduling without performance loss, for example by decoding sequentially row by row in the base matrix or by decoding the pairs of orthogonal rows in the base matrix at a time. An apparatus includes a receiver configured to receive a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver. The apparatus includes at least one processor coupled with a memory and comprising decoder circuitry configured to decode the codeword based on a QC-LDPC code to produce a set of information bits. The LDPC code is stored in the memory and defined by a base matrix having columns in which all adjacent rows are orthogonal in a last portion ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 7/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The technology of the present invention relates to a data processing device and a data processing method that can ensure favorable communication quality in data transmission which uses low density parity check (LDPC) code. In group-wise interleaving, the code length N is 64800 bits, and LDPC code, for which the coding rate r is 9/15, is interleaved in 360 bit bit-group units. In group-wise deinterleaving, the arrangement of LDPC code after group-wise interleaving is restored to the original arrangement. The technology of the present invention can be applied, for example, to a case where data transmission using LDPC code is carried out.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

This technology pertains to a data processing device and data processing method which are capable of providing an LDPC code having a favorable error rate. This LDPC encoder encodes at a code length of 64,800 bits and at a 2/30, 3/30, 4/30, 5/30 or 6/30 LDPC code rate. The LDPC code contains information bits and parity bits, and a check matrix (H) is configured from an information matrix section corresponding to the information bits of the LDPC code, and a parity matrix section corresponding to the parity bits. The information matrix section of the check matrix (H) is represented by a check matrix initial value table expressing the position of one element of the information matrix section for each of 360 rows. This technology can be applied in cases when conducting LDPC encoding and LDPC decoding.

DATA-PROCESSING DEVICE AND DATA PROCESSING METHOD

This technology pertains to a data-processing device and a data processing method that make it possible to ensure good communication quality when using an LDPC code to transmit data. In group-wise interleaving, an LDPC code having a code length (N) of 16,200 bits and a code rate (r) of 10/15 or 12/15 is interleaved on a per-bit-group basis, each bit group being 360 bits long. In group-wise deinterleaving, the interleaved LDPC code is restored to the original ordering thereof. This technology can be applied, for example, to data transmission or the like using an LDPC code.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

This technology pertains to a data processing device and a data processing method that make it possible to provide an LDPC code that has a good error rate. An LDPC encoder encodes using an LDPC code that has a code length of 16,200 bits and a code rate of 10/15. Said LDPC code contains information bits and parity bits, and the parity-check matrix (H) for said LDPC code comprises an information-matrix section corresponding to the information bits of said LDPC code and a parity-matrix section corresponding to the parity bits. The information-matrix section of the parity-check matrix (H) is represented by a parity-check-matrix initial-value table that represents the position of one element of said information-matrix section each 360 columns. This technology can be applied when performing LDPC encoding and LDPC decoding.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

This technology pertains to a data processing device and a data processing method that make it possible to ensure good communication quality when using an LDPC code to transmit data. In group-wise interleaving, an LDPC code having a code length of 64,800 bits and a code rate of 6/15, 7/15, 8/15, or 9/15 is interleaved on a per-bit-group basis, each bit group being 360 bits long. In group-wise deinterleaving, the interleaved LDPC code is restored to the original ordering thereof. This technology can be applied, for example, to data transmission or the like using an LDPC code.

TRANSMISSION METHOD, TRANSMISSION DEVICE, RECEPTION METHOD, AND RECEPTION DEVICE

A decoding device includes: a BP decoding unit which subjects an input signal to BP decoding; a maximum likelihood decoding unit which subjects the BP-decoded signal to maximum likelihood decoding; and a selecting unit which selects either the input signal, the BP-decoded signal, or the maximum likelihood-decoded signal. Adopting this configuration makes it possible, by causing the decoding unit to operate as appropriate in accordance with the quality of data, for example, to reduce the scale of computations that are performed, and to reduce power consumption.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

This technology pertains to a data processing device and a data processing method that make it possible to provide an LDPC code that has a good error rate. An LDPC encoder encodes using an LDPC code that has a code length of 64,800 bits and a code rate of 5/15. Said LDPC code contains information bits and parity bits, and the parity-check matrix (H) for said LDPC code comprises an information-matrix section corresponding to the information bits of said LDPC code and a parity-matrix section corresponding to the parity bits. The information-matrix section of the parity-check matrix (H) is represented by a parity-check-matrix initial-value table that represents the position of one element of said information-matrix section each 360 columns. This technology can be applied when performing LDPC encoding and LDPC decoding.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The present invention relates to a data processing device and a data processing method which can ensure excellent communication quality in data transmission using LDPC codes. In groupwise interleaving, the code length N is 64800 bits, and LDPC codes with a coding rate r of 9/15, 11/15 or 13/15 are interleaved in bit group units of 360 bits. In groupwise deinterleaving, the sequence of the LDPC codes after groupwise interleaving is returned to the original sequence. This invention can be applied for example when performing data transmission, etc., using LDPC codes.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The present invention relates to a data processing device and a data processing method which can ensure excellent communication quality in data transmission using LDPC codes. In groupwise interleaving, the code length N is 64800 bits, and LDPC codes with a coding rate r of 9/15, 11/15 or 13/15 are interleaved in bit group units of 360 bits. In groupwise deinterleaving, the sequence of the LDPC codes after groupwise interleaving is returned to the original sequence. This invention can be applied for example when performing data transmission, etc., using LDPC codes.

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 2/15 CODE RATE

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF_3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

... ²²A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC ²encoding method are disclosed. The LDPC encoder includes first memory, second ²memory, and a processor. The first memory stores an LDPC codeword having a ²length of 16200 and a code rate of 3/15. The second memory is initialized to ²0. The ²processor generates the LDPC codeword corresponding to information bits by ²performing accumulation with respect to the second memory using a sequence ²corresponding to a parity check matrix (PCM).² ...

POLAR CODE RATE MATCHING METHOD AND POLAR CODE RATE MATCHING APPARATUS

Embodiments of the present invention provide a rate matching method and rate matching apparatus for Polar codes. The method comprises: performing matrix-based BRO interleaving of non-system Polar codes output by a Polar code encoder, so as to obtain interleaved bits; and determining an output sequence of rate matching according to the interleaved bits. In the embodiments of the present invention, matrix-based BRO interleaving of non-system Polar codes is performed, and an output sequence of rate matching is obtained; in this manner, an interleaved sequence structure is more random, an FER can be reduced, HARQ performance can be improved and the reliability of data transmission can be ensured.

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING A QUASI-CYCLIC LOW DENSITY PARITY CHECK CODE IN A MULTIMEDIA COMMUNICATION SYSTEM

An apparatus and method are provided for transmitting and receiving a quasi-cyclic Low Density Parity Check (LDPC) code in a multimedia communication system. In the quasi-cyclic LDPC transmission method, a signal transmission apparatus generates a quasi-cyclic LDPC code, and transmits the quasi-cyclic LDPC code to a signal reception apparatus, wherein the quasi-cyclic LDPC code is generated by encoding an information word vector using a child parity check matrix which is generated by performing one of a scaling operation, a row separation operation and a row merge operation on a parent parity check matrix, and wherein the scaling operation is an operation in which a size of the child parity check matrix is determined, the row separation operation is an operation in which each of rows included in the parent parity check matrix is separated, and the row merge operation is an operation in which the rows included in the parent parity check matrix are merged.

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

DIGITAL COMMUNICATION SYSTEM

Methods and apparatus for use in communication systems using recursive modulation schemes with a Low Density Generator Matrix code (including an irregular repeat accumulate (IRA) code) are described that have reduced complexity and thus reduced cost compared to prior art systems. A communication system is described in which the transmitter concatenates a low density generator matrix code with an accumulator followed by a recursive modulator in order to eliminate the use of an interleaver, and in which the receiver combines the decoder for the accumulator and the soft demodulator into a single joint decoder in order reduce the number of components and complexity. Another variation is also described in which the transmitter is further simplified by eliminated the accumulator altogether, and in which the receiver is further simplified by replacing the joint decoder with a soft demodulator prior to the LDGM soft decoder.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Methods and devices for decoding and encoding data

데이터 처리 장치, 및, 데이터 처리 방법

... 본 기술은, LDPC 부호를 사용한 데이터 전송에 있어서, 양호한 통신 품질을 확보할 수 있도록 하는 데이터 처리 장치, 및, 데이터 처리 방법에 관한 것이다. 그룹 와이즈 인터리브에서는, 부호 길이 N이 64800비트이며, 부호화율 r이 11/15인 LDPC 부호가, 360비트의 비트 그룹 단위로 인터리브된다. 그룹 와이즈 디인터리브에서는, 그룹 와이즈 인터리브 후의 LDPC 부호의 배열이 원래의 배열로 복귀된다. 본 기술은, 예를 들어, LDPC 부호를 사용한 데이터 전송 등을 행하는 경우에 적용할 수 있다.

데이터 처리 장치 및 데이터 처리 방법

... 본 기술은, 양호한 에러율의 LDPC 부호를 제공할 수 있도록 하는 데이터 처리 장치 및 데이터 처리 방법에 관한 것이다. LDPC 인코더는, 부호 길이가 16200비트이고, 부호화율이 10/15인 LDPC 부호에 의한 부호화를 행한다. LDPC 부호는, 정보 비트와 패리티 비트를 포함하고, 검사 행렬 H는, LDPC 부호의 정보 비트에 대응하는 정보 행렬부와 패리티 비트에 대응하는 패리티 행렬부로 구성된다. 검사 행렬 H의 정보 행렬부는, 그 정보 행렬부의 1의 요소의 위치를 360열마다 나타내는 검사 행렬 초기값 테이블에 의해 표시된다. 본 기술은, LDPC 부호화 및 LDPC 복호를 행하는 경우에 적용할 수 있다.

INFORMATION PROCESSING METHOD AND COMMUNICATION APPARATUS

LDPC encoding and decoding of packets of variable sizes

Techniques to support low density parity check (LDPC) encoding and decoding are described. In an aspect, LDPC encoding and decoding of packets of varying sizes may be supported with a set of base parity check matrices of different dimensions and a set of lifting values of different powers of two. A base parity check matrix G of dimension mB*nB may be used to encode a packet of kB=nB-mB information bits to obtain a codeword of nB code bits. This base parity check matrix may be ''lifted'' by a lifting value of L to obtain a lifted parity check matrix H of dimension L.mB*L.nB. The lifted parity check matrix may be used to encode a packet of up to L.kB information bits to obtain a codeword of L.nB code bits. A wide range of packet sizes may be supported with the set of base parity check matrices and the set of lifting values.

CONTENTION-FREE PARALLEL PROCESSING MULTIMODE LDPC DECODER

A receiver capable of decoding encoded transmissions. The receiver includes a number of receive antennas for receiving data; a plurality of memory units for storing the received data; and a number of decoders configured to perform a Low Density Parity Check (LDPC) decoding operation. Each of the decoders further is configured to independently decode at least a portion of the received data using a portion of a decoding matrix. Each of the number of decoders coordinates the low density parity check decoding operation with other decoders. The decoders can use a parallel process, a pipeline process or a combination of a parallel and pipeline process.

METHODS AND DEVICES FOR DECODING AND ENCODING DATA

A method for decoding an input data sequence is provided. The method comprises generating a plurality of test sequences, determining an order for the plurality of test sequences, such that each test sequence differs from its adjacent test sequences by a respective predefined number of bits, and carrying out a maximum likelihood process with the ordered test sequences and the input data sequence thereby generating a maximum likelihood sequence.

APPARATUS AND METHOD FOR DECODING USING CHANNEL CODE

An encoding and decoding method and apparatus.is disclosed. The method and apparatus improves encoding and decoding performance without using a large memory capacity and also reduces the complexity of hardware for implementation. According to the method, an encoded signal is received from a transmitting side, and the received signal is decoded using the parity check matrix. The parity check matrix includes layers where nonzero elements of a specific number of layers do not overlap in column direction.

ENCODING METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CODE

The invention provides an encoding method and apparatus for Low Density Parity Check (LDPC) codes, which relate to the field of communications and are invented for resolving the problem of high complexity of LDPC code encoding in the prior art. The technical solution of the invention includes: obtaining data to be encoded; encoding the data to be encoded with an extended check matrix to obtain the encoded codeword, wherein, the generation of the extended check matrix includes: obtaining a J×L basis matrix according to a first matrix, a second matrix, a third matrix, a first random matrix and the preset forth constraint condition; performing line and column transformation and cyclic shift extension on the basis matrix to obtain the extended check matrix which is in the form of an upper triangle or a lower triangle.

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD

The present technology relates to a data processing apparatus and a data processing method that are able to secure good communication quality in data transmission using an LDPC code. One symbol is mapped to one of 16 signal points prescribed in 16APSK, with code bits of four bits of an LDPC code having a code length of 16200 bits and a code rate of 7/15 as one symbol. 16 signal points prescribed in 16APSK are four signal points on an inner circle and 12 signal points on an outer circle, and a radius ratio of the inner circle and the outer circle is 5.25. The present technology may be applied to, for example, a case of performing data transmission using an LDPC code.

PARITY GENERATION CIRCUITS FOR A PLURALITY OF ERROR CORRECTION LEVELS, MEMORY CONTROLLERS, AND MEMORY MODULES INCLUDING THE PARITY GENERATION CIRCUITS

A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.

ENCODER, TRANSMITTING APPARATUS, CODING METHOD AND TRANSMITTING METHOD

Disclosed are an encoder, a transmitting device, a coding method and a transmission method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block coding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

Overlapping sub-matrix based LDPC (low density parity check) decoder

Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

Method and device for decoding Reed-Solomon (RS) code

The embodiments of the invention disclose a method and a device for decoding an RS code, the method comprising: receiving bit reliability information of the RS code output by a channel, performing a hard decision on the bit reliability information to obtain a hard-decision result value sequence; determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code; according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determining an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and performing a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode; outputting the hard-decision result value sequence after the bit error correction as a decoding result.

APPARATUS AND METHOD FOR PROCESSING MULTI-USER TRANSMISSIONS TO DISCARD SIGNALS OR DATA CARRYING INTERFERENCE

A method for processing signals or data liable to interference arising from the sharing of channels in multi-user transmissions is applied to a base station apparatus. The base station apparatus receives a codeword from a terminal apparatus, and decodes the received codeword using a parity check matrix. The base station apparatus 110 can determine whether interference exists in a signal or data by analyzing the received codeword, and terminates a decoding of the received codeword if interference is found.

Convolutional code encoding method

An encoder and decoder using LDPC-CC (Low Density Parity Check-Convolutional Codes) is disclosed. In the encoder (200), an encoding rate setting unit (250) sets an encoding rate (s1)/s (s=z), and an information creating unit (210) sets information including from information Xs,i to information Xz1,i to zero. A first information computing unit (220-1) receives information X1,i at time point i to compute the X1(D) term of formula (1). A second information computing unit (220-2) receives information X2,i at time point i to compute the X2(D) term of formula (1). A third information computing unit (220-3) receives information X3,i at time point i to compute the X3(D) term of formula (1). A parity computing unit (230) receives parity Pi1 at time point i1 to compute the P(D) of formula (1). The exclusive OR of the results of the computation is obtained as parity Pi at time i. Ax.

Using parity data for concurrent data authentication, correction, compression, and encryption

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Detection of multiple bit errors in random access memories

In one embodiment, a method includes reading a codeword stored to a memory, computing a syndrome word based on a product of the codeword and a parity check matrix derived from a linear block code, setting a flag to a first value indicating that the codeword includes no errors in response to a first determination requiring that the syndrome word is an all-zero vector, setting the flag to a second value indicating that the codeword includes exactly one single-bit error in response to a second determination requiring that the syndrome word equals a column of the parity check matrix, setting the flag to a third value indicating that the codeword includes an odd number of multiple bit errors in response to a third determination, and setting the flag to a fourth value indicating that the codeword includes an even number of multiple bit errors in response to a fourth determination.

Methods of correcting data errors and semiconductor devices used therein

A semiconductor device correcting data errors using a hamming code is provided. The hamming code is realized by an error check matrix, and the error check matrix includes a first sub-matrix and a second sub-matrix. The first sub-matrix includes column vectors having an odd weight. The second sub-matrix includes an up matrix and a down matrix. Each of the up matrix and the down matrix includes column vectors having an odd weight.

TRANSMITTING DEVICE, RECEIVING DEVICE, TRANSMITTING METHOD, AND RECEIVING METHOD

One coding method of a plurality of coding methods including at least a first coding method and a second coding method is selected, an information sequence is encoded by using the selected coding method, and an encoded sequence obtained by performing predetermined processing on the information sequence is modulated and transmitted. The first coding method is a coding method having a first coding rate, for generating a first encoded sequence by performing puncturing processing on a generated first codeword by using a first parity check matrix. The second coding method is a coding method having a second coding rate, for generating a second encoded sequence by performing puncturing processing on a generated second codeword by using a second parity check matrix that is different from the first parity check matrix, the second coding rate after the puncturing process being different from the first coding rate. Further, a number of bits of the first encoded sequence is equal to a number of bits ...

Encoding method and system for quasi-cyclic low-density parity-check code

A method and system are provided. The method includes applying a quasi-cyclic matrix M to an input vector X− of encoded data to generate a vector Y. The method further includes applying a matrix Q to the vector Y to generate a vector Z. The method also includes recursively generating, using a processor, parity check bits P for the encoded data from the vector Z and an identity matrix variant I*. The encoded data includes quasi-cyclic low-density parity-check code. The identity matrix variant I* is composed of Toeplitz sub-matrices.

DEVICES AND METHODS IMPLEMENTING POLAR CODES

... wherein F⊗m denotes the m-times Kronecker product of the matrix F with itself and wherein the constraint matrix V comprises in addition to the constraint matrix V0 of the parent polar code the constraint matrix V1 of a first helper code C1 and the constraint matrix V2 of a second helper code C2.

Method and apparatus for power conservation in LDPC decoding

There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 64800 bits and an encoding rate r is 7/15, 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

High-speed multi-block-row layered decoder for low density parity check (LDPC) codes

High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a first result of a first computation and a second result of a second computation. A length of a “critical path” of the decoder is reduced as compared to a critical path length in which a common feedback message is computed.

METHOD FOR IMPLEMENTING TURBO EQUALIZATION COMPENSATION, TURBO EQUALIZER AND SYSTEM

Embodiments of the present application relate to a method for implementing Turbo equalization compensation. The equalizer divides a first data block into n data segments, where D bits in two adjacent data segments in the n data segments overlap, performs recursive processing on each data segment in the n data segments, before the recursive processing, merges the n data segments to obtain a second data block; and performs iterative decoding on the second data block, to output a third data block, where data lengths of the first data block, the second data block, and the third data block are all 1/T of a code length of a LDPC convolutional code.

ENCODING METHOD, DECODING METHOD

An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula.

METHOD AND DEVICE FOR PROCESSING DATA

A method for processing data includes coding a data item to obtain a coded data item that includes a predefinable number of bits, influencing maximally k many bits of the coded data item to obtain a changed data item, decoding the changed data item by using a fault-correcting code to obtain a decoded data item, and processing the decoded data item. 1. A method for processing data , the method comprising:coding a data item to obtain a coded data item that includes a predefinable number of bits;influencing bits of the coded data item to obtain a changed data item;decoding the changed data item by using a fault-correcting code to obtain a decoded data item; andprocessing the decoded data item.2. The method of claim 1 , wherein for the step of coding claim 1 , a fault-correcting code is used claim 1 , in particular a Hamming code.3. The method of claim 1 , wherein the step of influencing includes at least one of inverting and deleting bits of the coded data item.4. The method of claim 1 , wherein the step of processing includes carrying out at least a part of a cryptographic method or comparing data with predefinable reference data.5. The method of claim 1 , wherein at least one of the coded data item claim 1 , the changed data item claim 1 , and the decoded data item is stored at least temporarily.6. The method of claim 1 , wherein the influencing is carried out as a function of at least one of a deterministic process and a stochastic process.7. The method of claim 1 , wherein the decoding is carried out in such a way that a time for the decoding of the changed data item is not constant between different performances of the decoding.8. A device for processing data claim 1 , the device comprising: code a data item to obtain a coded data item that includes a predefinable number of bits;', 'influence bits of the coded data item to obtain a changed data item;', 'decode the changed data item by using a fault-correcting code to obtain a decoded data item; and', 'process the ...

TRANSMITTER APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

ENCODING AND DECODING TECHNIQUES USING LOW-DENSITY PARITY CHECK CODES

Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.

Systems and methods for out of order processing in a data retry

Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order.

ADAPTIVE DISPERSED STORAGE NETWORK (DSN) AND SYSTEM

A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and to the memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. When additional unique pillar combinations of at least read threshold number of encoded data slices (EDSs) supported by EDSs may be needed, the computing device dispersed error encodes each data segment in accordance to generate additional pluralities of EDSs and distributedly stores the additional pluralities of EDSs associated respectively with the data object across the plurality of SUs within the DSN to support the additional unique pillar combinations of the at least read threshold number of EDSs.

Decomposable forward error correction

Network communication systems may employ coding schemes to provide error checking and/or error correction. Such schemes may include parity or check symbols in a message that may add redundancy, which may be used to check for errors. For example, Ethernet may employ forward error correction (FEC) schemes using Reed-Solomon codes. An increase in the number of parity symbols may increase the power of the error-correcting scheme, but may lead to an increased in latencies. Encoders and decoders that may be configured in a manner to produce variable-length messages while preserving compatibility with network standards are described. Decoders described herein may be able to verify long codewords by checking short codes and integrating the results. Encoders described herein may be able to generate codewords in multiple formats without replicating large segments of the circuitry.

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

LOW DENSITY PARITY CHECK CODE ENCODING METHOD AND COMMUNICATION APPARATUS

This application provides an LDPC code encoding method and a communication apparatus, to meet a requirement of increasing redundant bits through retransmission in an IR-HARQ mechanism, so as to decrease a channel coding rate, and improve decoding performance of an LDPC code. In the method, a check matrix of the LDPC code is used as a basic matrix, and the basic matrix is extended to obtain a mother matrix compatible with a plurality of code rates. During LDPC encoding, a transmit device reads, from the mother matrix, a check matrix corresponding to a required code rate, and performs LDPC encoding on an information bit sequence based on the read check matrix. LDPC encoding is performed on the information bit sequence by using check matrices of different sizes, to obtain different quantities of redundant bits.

ERROR-CORRECTING CODE PROCESSING METHOD AND DEVICE

An error-correcting code processing method includes: calculating descending symbols or ascending symbols or both, and calculating, as a parity, exclusive OR of all elements of an information symbol sequence; one or both of calculating exclusive OR for each element of the descending symbols, to generate low-order n bits of the descending symbols and calculating exclusive OR for each element of the ascending symbols, to generate low-order n bits of the ascending symbols; one or both of calculating exclusive OR of elements obtained by selecting, in descending order, elements from an element sequence resulting from arranging parities, to generate a high-order m bit of the descending symbols and calculating exclusive OR of elements obtained by selecting, in ascending order, elements from the element sequence, to generate a high-order m bit of the ascending symbols; and outputting the descending symbols or the ascending symbols or both as check symbols or a syndrome.

Generation of optimized exponent matrices for multi-rate LDPC codes

Generating parity-check exponent matrixes Hexp for both coding sequences of information bits and decoding parity-check codewords, by using LDPC codes supporting different block sizes for each code-rate Rj, is optimized starting from a multi-rate random exponent table, the main table, from which sub-tables can be extracted for every requested code-rate. The generated exponent matrixes are built with random techniques, by which a first rb×rb deterministic sub-matrix accounting for a block of r redundancy bits is contiguous to a random rb×kb sub-matrix that accounts for a block of k information bits. Some constraints on the elements of the first column vector Cv of deterministic matrix, and some other distance rules on the random elements must be respected in order to simplify the encoder and prevent unwanted cycles in Tanner's graph at the decoder, as done in IEEE Std 802.16e (WiMAX). The main table is devoted to the only random matrixes plus the first column vector of deterministic matrixes ...

LDPC ENCODING AND DECODING OF PACKETS OF VARIABLE SIZES

СПОСОБ И УСТРОЙСТВО ДЕКОДИРОВАНИЯ КОДА ПОРОЖДАЮЩЕЙ МАТРИЦЫ С НИЗКОЙ ПЛОТНОСТЬЮ

Изобретение относится к области кодирования и декодирования данных, в частности к способу и устройству декодирования кода порождающей матрицы с низкой плотностью. Для принятой последовательности битов информации, переданных после кодирования LDGC, проводится декодирование, при этом способ включает в себя следующее содержание: S1: в принятой последовательности кодовых слов R заполнять известные биты в количестве L-K, а также вычеркивать символы кодового слова в R, стертые каналом, получается Re; S2: из транспонированной матрицы Gldgct порождающей матрицы LDGC вычеркивать строки, соответствующие символам кодового слова, стертым каналом, получается Ge; S3: по отношению Ge×It=Re определяется It; S4: по отношению Gldgct(0:L-1,0:L-1)×It=st определяется st, а также из st вычеркивать вышеуказанные заполненные известные биты в количестве L-K, и исходная информационная последовательность битов К получается. Технический результат обеспечивает снижение расходов памяти декодера, а также ускорение скорости ...

СПОСОБ И УСТРОЙСТВО ГЕНЕРИРОВАНИЯ ГИБРИДНОГО ПОЛЯРНОГО КОДА

Изобретение относится к технологиям генерации гибридного полярного кода. Техническим результатом является улучшение рабочих характеристик полярного кода за счет рассмотрения надежности бита и веса ряда. Предложен способ генерирования гибридного полярного кода. Способ включает в себя этап, на котором получают первую матрицу N×N и последовательность, включающую в себя N битов, при этом N рядов первой матрицы соответствуют N битам в последовательности во взаимно-однозначном соответствии, и N представляет собой положительное целое число. Далее, согласно способу, определяют надежность N битов и вес каждого ряда в N рядах первой матрицы. Кроме того, выбирают, в соответствии с надежностью N битов и весом каждого ряда в N рядах первой матрицы, и выбирают K битов среди N битов, в качестве информационных битов, или выбирают в соответствии с надежностью N битов и весом каждого ряда в N рядах первой матрицы, K рядов среди N рядов первой матрицы, для построения второй матрицы размером K×N, используемой ...

УСТРОЙСТВО ОБРАБОТКИ ДАННЫХ И СПОСОБ ОБРАБОТКИ ДАННЫХ

Изобретение относится к технике связи и предназначено для обработки данных. Технический результат – обеспечение хорошего качества связи при передаче данных с использованием LDPC-кода. Для этого в устройстве передачи при перестановке с целью сопоставления бита LDPC-кода, для которого длина кода равна 16200 битам и скорость кодирования равна 7/15, с битом символа, соответствующим любой из 8 сигнальных точек, определенных 8-позиционной PSK, когда 3 бита кода, которые сохранены в трех блоках памяти емкостью 16200/3 битов и которые побитно считаны из блоков памяти, сопоставляют одному символу, бит b, бит bи бит bпереставляют соответственно с битами y, yи y. Возвращают к исходной позицию переставленного бита кода, полученного из данных, переданных из устройства передачи. 4 н.п. ф-лы, 79 ил.

СПОСОБ СОГЛАСОВАНИЯ СКОРОСТИ ПОЛЯРНОГО КОДА И УСТРОЙСТВО СОГЛАСОВАНИЯ СКОРОСТИ ПОЛЯРНОГО КОДА

Группа изобретений относится к области кодирования и может быть использована для согласования скорости полярного кода. Техническим результатом является уменьшение частоты появления ошибок в кадре, тем самым улучшая эффективность HARQ и гарантируя надежность передачи данных. Способ включает в себя этапы, на которых: выполняют матричное перемежение с инвертированием порядка битов BRO над несистематическим полярным кодом, выводимым полярным кодером, для получения перемеженных битов и определяют, на основании перемеженных битов, выходную последовательность с согласованной скоростью. 4 н.п. ф-лы, 10 ил.

СПОСОБ И УСТРОЙСТВО ДЕКОДИРОВАНИЯ КОДА ПОРОЖДАЮЩЕЙ МАТРИЦЫ С НИЗКОЙ ПЛОТНОСТЬЮ

... 1. Способ декодирования кода порождающей матрицы с низкой плотностью для принятой последовательности битов информации, переданных после кодирования LDGC, проводится декодирование, отличающийся тем, что способ включает в себя следующее: ! S1: в принятой последовательности кодовых слов R заполнять известные биты в количестве L-K, а также вычеркивать символы кодового слова в R, стертые каналом, получается Re; ! S2: из транспонированной матрицы Gldgct порождающей матрицы LDGC вычеркивать строки, соответствующие символам кодового слова, стертым каналом, получается Ge; в данном процессе процессорные слова в количестве WNum используются для поочередного хранения полных или частичных матричных элементов с одинаковыми положениями во всех строках Ge, каждое процессорное слово хранит матричный элемент в количестве WWid Ge; ! S3: по отношению Ge·It=Re определяется It; ! S4: по отношению Gldgct(0:L-1,0:L-1)·It=st определяется st, а также из st вычеркивать указанные заполненные известные биты в количестве ...

СПОСОБ ОБРАБОТКИ ИНФОРМАЦИИ, ПРИСПОСОБЛЕНИЕ И УСТРОЙСТВО СВЯЗИ

РЕКОНФИГУРИРУЕМОЕ КОДИРОВАНИЕ ДЛЯ НЕСКОЛЬКИХ СТАНДАРТОВ СВЯЗИ

... 1. Устройство для реконфигурируемого кодирования для нескольких стандартов связи, содержащее: ! первую схему, сконфигурированную для (i) получения сигнала конфигурации, который идентифицирует текущий из множества стандартов связи и (ii) генерирования множества матричных элементов на основе вышеупомянутого сигнала конфигурации; и ! вторую схему, включающую в себя множество матриц и сконфигурированную для (i) заполнения указанных матриц матричными элементами и (ii) генерирования закодированного сигнала посредством кодирования входного сигнала с упреждающим исправлением ошибок с использованием названных матриц, где названный закодированный сигнал соответствует вышеупомянутому текущему стандарту связи. ! 2. Устройство по п.1, отличающееся тем, что названная первая схема дополнительно сконфигурирована для изменения конфигурации названной второй схемы среди названных стандартов связи в ответ на изменение вышеупомянутого сигнала конфигурации. ! 3. Устройство по п.2, отличающееся тем, что названное ...

СПОСОБ И УСТРОЙСТВО ДЛЯ КОДИРОВАНИЯ И ДЕКОДИРОВАНИЯ LDPC-КОДОВ

АППАРАТУРА, СПОСОБ ОБРАБОТКИ ИНФОРМАЦИИ И АППАРАТУРА СВЯЗИ

КОДИРОВАНИЕ И ДЕКОДИРОВАНИЕ LDPC ПАКЕТОВ ПЕРЕМЕННЫХ РАЗМЕРОВ

... 1. Устройство, содержащее !по меньшей мере один процессор, выполненный с возможностью кодирования или декодирования пакетов переменных размеров на основании множества базовых матриц контроля четности разных размеров и множества значений поднятия, равных разным степеням 2, и ! память, соединенную с по меньшей мере одним процессором и выполненную с возможностью хранения параметров для множества базовых матриц контроля четности. !2. Устройство по п.1, в котором по меньшей мере один процессор выполнен с возможностью определения размера пакета для пакета, подлежащего кодированию или декодированию, выбора значения поднятия из множества значений поднятия на основании размера пакета, выбора базовой матрицы контроля четности из множества базовых матриц контроля четности на основании размера пакета и выбранного значения поднятия, генерации поднятой матрицы контроля четности на основании выбранной базовой матрицы контроля четности и выбранного значения поднятия, и кодирования или декодирования пакета ...

Cyclic redundancy check computation circuit, communication unit, and method therefor

PRODUCTION OF AN EXPONENT TABLE FOR THE CODING AND DECODING OF LDPC CODES OF DIFFERENT LENGTH

Method and apparatus for encoding data using a polar code

Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of "ones" in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of "ones" in the binary representation of the sub-channel index (further described below). In one embodiment， candidate sub-channels that have certain row weight values are reserved for parity bit (s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N-K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits.

Information processing method and communication apparatus

An encoding method, an apparatus, a communication device and a communication system. The method comprises: using a low-density parity-check (LDPC) matrix to encode an input bit sequence, a base graph of the LDPC matrix being expressed as a matrix of m rows and n columns, m being an integer greater than or equal to 5, n being an integer greater than or equal to 27, the base graph at least comprising a sub-matrix A and a sub-matrix B, the sub-matrix A being a matrix of 5 rows and 22 columns, the sub-matrix B being a matrix of 5 rows and 5 columns, the sub-matrix B comprising a column having a weight of 3 and a sub-matrix B' having a dual-diagonal structure. The encoding method, the apparatus, the communication device and the communication system support encoding requirements for information bit sequences of various lengths.

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

MEDIA CONTENT-BASED ADAPTIVE METHOD, DEVICE AND SYSTEM FOR FEC CODING AND DECODING OF SYSTEMATIC CODE, AND MEDIUM

Provided are a media content-based adaptive method, device and system for FEC coding and decoding of a systematic code, and a medium. The method comprises: according to the importance of media content, dividing source data into N types of source data packets according to priorities; generating N types of intermediate codes according to the N types of source data packets and the priorities thereof; according to the N types of intermediate codes, setting recovery data of N types of source data according to a channel condition, and generating N types of coded symbols of systematic codes; receiving the coded symbols, and sorting and arranging the coded symbols according to decoding requirements; and according to the number of received coded symbols, decoding same to obtain intermediate codewords according to different situations, and recovering corresponding source data packets according to intermediate codewords. According to the present invention, the quality of the media content is ensured ...

MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE

... ²A modulator and a modulation method using a non-uniform 16-symbol signal ²constellation are disclosed. The modulator includes a memory and a processor. ²The ²memory receives a codeword corresponding to a low-density parity check (LDPC) ²code ²having a code rate of 4/15. The processor maps the codeword to 16 symbols of ²the non-uniform ²16-symbol signal constellation on a 4-bit basis.² ...

PROCESSING METHOD AND DEVICE FOR QUASI-CYCLIC LOW DENSITY PARITY CHECK CODING

Provided are a processing method and device for quasi-cyclic low density parity check (LDPC) coding. The processing method for quasi-cyclic LDPC coding comprises: determining a processing strategy for quasi-cyclic LDPC coding according to a data feature of an information bit sequence to be encoded (S210); and performing, according to the processing strategy, and on the basis of a fundamental matrix and a lifting value, quasi-cyclic LDPC coding on the information bit sequence and performing rate matching output (S220). The method and device can improve adaptivity and flexibility of quasi-cyclic LDPC coding.

INFORMATION PROCESSING METHOD, APPARATUS, AND COMMUNICATION APPARATUS

Disclosed in the present application are an encoding method and apparatus, a communication device and a communication system. The method comprises: using a low density parity check (LDPC) matrix to encode an input bit sequence; the LDPC matrix being obtained on the basis of a spreading factor Z and a basis matrix, the basis matrix comprising the 0th to 6th rows and the 0th to 16th columns in one of the matrices shown in figures 3b-1 to 3b-8, or the basis matrix comprising the 0th to 6th rows and some of the 0th to 16th columns in any one of the matrices shown in figures 3b-1 to 3b-8. The encoding method and apparatus, the communication device and the communication system of the present application are able to support encoding requirements of information bit sequences of various lengths.

Combined group ecc protection and subgroup parity protection

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

METHOD OF RECOVERING DATA AND MEMORY SYSTEM AND RAID STORAGE SYSTEM USING THE SAME

A method and system of recovering data includes reading reference codewords, which have code correlation with a target codeword, from a memory device when an error-correcting code (ECC) decoding process for a decoder input of the target codeword has failed. A decoder input of a corrected target codeword is generated based on an operation process using the target codeword and the reference codewords. An ECC decoding process is performed again on the decoder input of the corrected target codeword. 1. A method of recovering data , the method comprising:reading reference codewords, which have a code correlation with a target codeword, from a memory device when an error-correcting code (ECC) decoding process for a decoder input of the target codeword has failed;generating a decoder input of a corrected target codeword, based on an operation process using the target codeword and the reference codewords; andperforming the ECC decoding process again on the decoder input of the corrected target codeword.2. The method of claim 1 , wherein the reference codewords comprise codewords read from a storage region which forms the same stripe as the target codeword.3. The method of claim 1 , wherein the generating of the decoder input of the corrected target codeword comprises:performing the ECC decoding process on each of the reference codewords; andcorrecting the decoder input of the target codeword, based on the operation process according to the code correlation, by using a decoding result of a reference codeword that has succeeded in the ECC decoding process, a soft input of a reference codeword that has failed in the ECC decoding process, and a soft input of the target codeword that has failed in the ECC decoding process.4. The method of claim 3 , further comprising correcting the decoder input of the target codeword when the ECC decoding process for at least one of the reference codewords has failed claim 3 , and recovering the target codeword by using decoding results of the ...

ACCELERATED ERASURE CODING SYSTEM AND METHOD

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data. 1a processing core for executing computer instructions and accessing data from a main memory; anda non-volatile storage medium for storing the computer instructions, a data matrix for holding original data in the main memory;', 'a check matrix for holding check data in the main memory;', 'an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and', a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor; and', 'a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data., 'a thread for executing on the processing core and comprising], 'wherein the processing core, the storage medium, and the computer instructions are configured to implement an erasure coding system comprising. A system for accelerated error-correcting code (ECC) processing comprising: This application is a continuation of U.S. patent ...

THE CONSTRUCTION OF MBR (MINIMUM BANDWIDTH REGENERATING) CODES AND A METHOD TO REPAIR THE STORAGE NODES

This invention gives a coding method of MBR (Minimum Bandwidth Regenerating) codes. The related method includes the following steps: equally divide the original file of size B into k(k+1)/2 blocks, obtaining the first packets; construct a symmetrical k×k system matrix S with these first packets; generate k ID codes, wherein each ID code contains k elements; obtain the coded packet through operations between one column of the system matrix and the ID code; repeat the above steps with (n−k) different columns of the system matrix separately to get the (n−k) coded packets; construct the (n−k)×k check matrix P with the column number g which is the serial number of the ID codes in the coded packet set P; store the rows of the system matrix and coded matrix to n nodes, each node stores one row. The present invention also involves a method to repair the failed nodes of the above coding scheme. 1. A coding method of Minimum Bandwidth Regenerating codes comprising the following steps: {'br': None, 'i': c', '=b', ', b', '. . . b', ', i=', 'k', 'k+, 'sub': i', 'i,1', 'i,2', 'i,L, '1, 2, . . . , (1)/2'}, 'A) dividing the original file of size B averagely into k (k+1)/2 blocks, each of which is L bits, obtaining first packets; the first packets are denoted as'}B) constructing a symmetrical k×k system matrix S by using the first packets, wherein choosing the first packets sequentially according to their serial number, and generating the upper-triangular of the system matrix by filling up the upper-triangular with the chosen first packets line by line successively according to the order of the column, where the elements of the system matrix are;{'sub': g', 'g,1', 'g,2', 'g,k', 'g,k, 'C) generating k ID codes, each of which contains k elements; adding given number of zeros to the head or end of the first packet in a column of the system matrix in accordance with the corresponding elements of a ID code, to get k second packets; operating on the k second packets to get a coded packet; ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 17280 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 45720.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 17280 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. patent application Ser. No. 14/496,654, filed on Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106180 and 10-2014-0120014, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.The present ...

TECHNOLOGIES FOR PROVIDING EFFICIENT ERROR CORRECTION WITH HALF PRODUCT CODES

Technologies for providing efficient error correction with half product codes include an apparatus having a memory to store data and a controller to manage read and write operations of the memory. The controller is to obtain, in response to a write request, data to write to the memory. The controller is further to encode the data with a half product code to define a matrix that includes at least one matrix element based on a soft decision error correction encoder algorithm and at least one other matrix element based on a hard decision error correction encoder algorithm. Additionally, the controller is to write the half product code to the memory. 1. An apparatus comprising:a memory; and obtain, in response to a write request, data to write to the memory;', 'encode the data with a half product code to define a matrix that includes at least one matrix element based on a soft decision error correction encoder algorithm and at least one other matrix element based on a hard decision error correction encoder algorithm; and', 'write the half product code to the memory., 'a controller to manage read and write operations of the memory, wherein the controller is to2. The apparatus of claim 1 , wherein to encode the data with a half product code that includes at least one matrix element based on a soft decision error correction encoder algorithm comprises to generate the at least one matrix element with a convolutional code.3. The apparatus of claim 2 , wherein to generate the at least one matrix element with a convolutional code comprises to perform a continuous convolutional encode over a plurality of rows of the matrix without termination of a trellis until a last row of the plurality of rows is encoded.4. The apparatus of claim 2 , wherein to generate the at least one matrix element with a convolutional code comprises to perform a tail-biting convolutional encode of the data.5. The apparatus of claim 1 , wherein to encode the data with a half product code that includes at ...

INTEGRATED CIRCUIT FOR TRANSMISSION APPARATUS

Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit () searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) () switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code. 1. An integrated circuit for a transmission apparatus comprising:at least one input which, in operation, receives an input;control circuitry, which is coupled to the at least one input and which, in operation, controls:{'sub': b', 'b', 'b', 'b', 'b', 'b, 'generating a codeword sequence s having a first coding rate by performing a low density parity check (LDPC) encoding process on information bit sequence u to generate a parity bit sequence p, the codeword sequence s being made up of z×nbits, the information bit sequence u being made up of z×(n-m) bits, the parity bit sequence p being made up of z×mbits, z being an integer equal to or greater than 1, nbeing an integer equal to or greater than 1, mbeing an integer equal to or greater than 1, the codeword sequence s being a sequence having the parity bit sequence p concatenated at a latter part of the information bit sequence u, the codeword sequence s being decoded at a decoder of a communicating partner apparatus;'}{'sub': 'b', 'forming a codeword sequence sp having a second coding rate by removing one or more sets of consecutive y bits from the parity bit sequence p, by using a removing pattern indicating whether or not each set of bits from a first bit to a z×m-th bit of the parity bit ...

METHOD FOR CONSTRUCTING PARITY-CHECK CONCATENATED POLAR CODES AND APPARATUS THEREFOR

A method for constructing parity-check concatenated polar codes and an apparatus therefor are disclosed. According to an embodiment of the inventive concept, a method for constructing a polar code includes receiving a code length, a message length, and channel information, generating an information set and a parity set of polar codes based on the received code length, the received message length, and the received channel information, and generating a parity node including the information set of elements based on the generated information set and the generated parity set. 1. A method for constructing a polar code , the method comprising:receiving a code length, a message length, and channel information;generating an information set and a parity set of polar codes based on the received code length, the received message length, and the received channel information; andgenerating a parity node including the information set of elements based on the generated information set and the generated parity set.2. The method of claim 1 , wherein the generating of the parity set includes:generating indexes, each of which is not greater than a preset Hamming weight among all indexes, as a frozen set of the polar codes;generating indexes, which are selected by a preset scheme among remaining indexes other than indexes selected as the frozen set, as a parity set; andgenerating indexes other than indexes selected as the parity set among the remaining indexes, as the information set.3. The method of claim 2 , wherein the generating of the indexes as the parity set includes:calculating a Bhattacharyya parameter of a polarized channel with respect to the remaining indexes; andgenerating indexes for an upper scale having a specific number as the parity set after sorting the calculated Bhattacharyya parameter.4. The method of claim 1 , wherein the generating of the parity node includes:finding information indexes, each of which is smaller than a corresponding index of the parity set, from ...

MOBILE COMMUNICATION SYSTEM USING SUBCODING TECHNIQUES

The disclosure relates to a mobile communication system including: a first transmission path configured to transmit a message according to a first radio access technology; a second transmission path configured to transmit the message according to a second radio access technology; and an encoder configured to encode the message by a code before transmission of the message over the first transmission path and the second transmission path, wherein the code comprises at least two subcodes, and wherein the encoder is configured to encode the message intended for transmission over the first transmission path with a first subcode of the at least two subcodes and to encode the message intended for transmission over the second transmission path with a second subcode of the at least two subcodes. 125.-. (canceled)26. A mobile communication system , comprising:a first transmission path configured to transmit a message according to a first radio access technology;a second transmission path configured to transmit the message according to a second radio access technology; andan encoder configured to encode the message via a code block before transmission of the message over the first transmission path and the second transmission path,wherein the code block comprises at least a first code block portion and a second code block portion, andwherein the encoder is configured to encode the message intended for transmission over the first transmission path with the first code block portion, and to encode the message intended for transmission over the second transmission path with the second code block portion.27. The mobile communication system of claim 26 , wherein a channel code of the first radio access technology is a Low Density Parity Check (LDPC) code.28. The mobile communication system of claim 26 , wherein at least one of the first radio access technology or the second radio access technology is a millimeter wave radio access technology.29. The mobile communication system of ...

EFFICIENT GENERALIZED TENSOR PRODUCT CODES ENCODING SCHEMES

A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector of a new stage 0 binary BCH codeword over a field GF(2) that comprises Δt syndromes of length m bits, wherein the syndrome vector comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1; and multiplying by a right submatrix Ũ of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by t, wherein the new binary BCH codeword is =Ũ·. 1. A computer implemented method for generating a binary Generalized Tensor Product (GTP) codeword , comprised of N structure stages wherein N is an integer greater than 1 and each stage is comprised of at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage , the method executed by the computer comprising the steps of:{'o': {'@ostyle': 'single', 'v'}, 'sup': 'm', 'receiving new stage 0binary BCH codeword over a field (2) from a communication channel;'}{'o': [{'@ostyle': 'single', 's'}, {'@ostyle': 'single', 'y'}, {'@ostyle': 'single', 'y'}, {'@ostyle': 'single', 's'}, {'@ostyle': 'single', 'y'}], 'sub': n', '0', '0', 'n, 'receiving a syndrome vector of the new stage 0 binary BCH codeword that comprises Δt syndromes of length m bits, wherein Δt=t−t, t, is the error correction capability of the stage 0 BCH codeword, tis an error correction capability of a stage n BCH codeword to which a new binary BCH codeword will be added, wherein the syndrome vector comprises l-th Reed-Solomon (RS) symbols of Δt RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n−1, Wherein l indexes the BCH codeword to which will be added; and'}{'o': [{'@ostyle': 'single', 's'}, ...

METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM

A low density parity check (LDPC) channel encoding method is used in a wireless communications system. A communication device encodes an input bit sequence by using an LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. The base matrix may be one of eight exemplary designs. The encoding method can be used in various communications systems including fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths. 1. A method for wireless communication , comprising:obtaining, by a communication apparatus, an input sequence, wherein the input sequence comprises K bits, wherein K≥1;encoding, by the communication apparatus, the input sequence using a matrix H to obtain an encoded sequence; andoutputting, by the communication apparatus, the encoded sequence;wherein the matrix H is determined according to a base matrix and a lifting factor Z, wherein Z is a positive integer;wherein the base matrix comprises m rows and n columns, where 4≤m≤42 and 14≤n≤52;wherein each element in the base matrix corresponds to a respective row index i and a respective column index j, where 0≤i Подробнее

ACCELERATED ERASURE CODING SYSTEM AND METHOD

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data. 1a processing core for executing computer instructions and accessing data from a main memory; anda non-volatile storage medium for storing the computer instructions, a data matrix for holding original data in the main memory;', 'a check matrix for holding check data in the main memory;', 'an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and', a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor; and', 'a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data., 'a thread for executing on the processing core and comprising], 'wherein the processing core, the storage medium, and the computer instructions are configured to implement an erasure coding system comprising. A system for accelerated error-correcting code (ECC) processing comprising: This application is a continuation of U.S. patent ...

AES IMPLEMENTATION WITH ERROR CORRECTION

A method of cryptographically processing a block of data, the method comprising: receiving an encoded version of the block of data, wherein the encoded version of the block of data comprises the block of data encoded, at least in part, using an error control code; and processing the encoded version of the block of data using a predetermined function to generate an output, wherein the predetermined function is arranged so that the result of processing, with the predetermined function, a quantity of data encoded, at least in part, using the error control code equals the result of encoding, at least in part, with the error control code the result of performing encryption or decryption of the quantity of data according to the Advanced Encryption Standard, AES. 112-. (canceled)13. A method of cryptographically processing a block of data , the method comprising:receiving an encoded version of the block of data, wherein the encoded version of the block of data comprises the block of data encoded, at least in part, using an error control code; andprocessing the encoded version of the block of data using a predetermined function to generate an output, wherein the predetermined function is arranged so that the result of processing, with the predetermined function, a quantity of data encoded, at least in part, using the error control code equals the result of encoding, at least in part, with the error control code the result of performing encryption or decryption of the quantity of data according to the Advanced Encryption Standard, AES.14. The method of claim 13 , wherein the predetermined function comprises one or more sub-functions claim 13 , wherein each of the sub-functions is arranged so that the result of processing claim 13 , with that sub-function claim 13 , a quantity of data encoded claim 13 , at least in part claim 13 , using the error control code equals the result of encoding claim 13 , at least in part claim 13 , with the error control code the result of ...

LOW DENSITY PARITY CHECK DECODING METHOD PERFORMING ON GENERAL GRAPHIC PROCESSING UNIT AND DECODING APPRATUS

A low density parity check (LDPC) decoding method and a decoding apparatus are provided. The method includes following steps. Based on M edges of a Tanner graph related to a parity check matrix, each of the edges is associated with one of a plurality of threads, such that each of the threads is corresponding to one of a plurality of edge identifies. When executing one of the threads, data in a shared memory is accessed according to the edge identifier of the one of the threads, so as to update a plurality of passing massages respectively corresponding to the edges in the shared memory. Thereby, high computation parallelism and fully-coalesced data accesses can be achieved. 1. A low density parity check (LDPC) decoding method performed on a general-purpose computing on graphics processing unit (GPGPU) , wherein a streaming multiprocessor of the GPGPU comprises a plurality of thread computing cores and a shared memory , the method comprising:based on M edges of a Tanner graph related to a parity check matrix, associating each of the edges with one of a plurality of threads, such that each of the threads is corresponding to one of a plurality of edge identifiers, wherein M is an integer greater than 1, and the edges are connected between a plurality of check nodes and a plurality of bit nodes; andwhen executing one of the threads, accessing data in the shared memory according to an edge identifier of the one of the threads, so as to update a plurality of passing massages which are respectively corresponding to the edges and stored in the shared memory.2. The LDPC decoding method according to claim 1 , wherein the step of accessing the data in the shared memory according to the edge identifier of the one of the threads claim 1 , so as to update the passing massages which are respectively corresponding to the edges and stored in the shared memory comprises:reading at least one target fetch-point index from M fetch-point indexes according to the edge identifier of the one ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The transmitter of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 2160 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 3240 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10800.3. The transmitter of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 2160 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 3240 claim 2 , by the CPM size.4. The transmitter of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The transmitter of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. application Ser. No. 15/018,762, filed Feb. 8, 2016, which is divisional of U.S. application Ser. No. 14/496,304, filed Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106173 and 10-2014-0120008, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 8640 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 54360.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 8640 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. patent application Ser. No. 14/496,457, filed on Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106178 and 10-2014-0120012, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. Technical FieldThe ...

Low density parity check encoder having length of 64800 and code rate of 5/15, and low density parity check encoding method using the same

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 3240 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 11880.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 3240 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1080 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of and claims priority of U.S. application Ser. No. 14/496,356 filed Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106174 and 10-2014-0120009, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 5400 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 720 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10080.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 5400 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 720 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. application Ser. No. 14/496,432, filed Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106176 and 10-2014-0120011, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. Technical FieldThe present ...

POLAR CODE RATE MATCHING METHOD AND POLAR CODE RATE MATCHING APPARATUS

Embodiments of the present invention provide a polar code rate matching method and a polar code rate matching apparatus. The method includes: performing matrix-based BRO interleaving on a non-systematic polar code output by a polar code encoder, to obtain interleaved bits; and determining, based on the interleaved bits, a rate-matched output sequence. According to the embodiments of the present invention, matrix-based BRO interleaving is performed on a non-systematic polar code, to obtain a rate-matched output sequence, so that a sequence structure after interleaving is more random, which can reduce an FER, thereby improving HARQ performance and ensuring reliability of data transmission. 1. A polar polar code rate matching method , comprising:performing matrix-based bit reversal order (BRO) interleaving on a non-systematic polar code output by a polar code encoder, to obtain interleaved bits; anddetermining, based on the interleaved bits, a rate-matched output sequence.2. The method according to claim 1 , wherein performing matrix-based BRO interleaving on the non-systematic polar code output by the polar code encoder claim 1 , to obtain interleaved bits comprises:{'b': 1', '2', '1', '2, 'writing bits of the non-systematic polar code by row to form a first matrix of M rows×M columns wherein M and M are positive integers;'}{'b': '2', 'performing a first substitution operation on a column of the first matrix to obtain a second matrix, wherein the first substitution operation is a BRO operation with a size of M;'}{'b': '1', 'performing a second substitution operation on a row of the second matrix to obtain a third matrix, wherein the second substitution operation is a BRO operation with a size of M; and'}reading bits according to a column of the third matrix, and using the bits as the interleaved bits.3. The method according to claim 1 , wherein performing matrix-based BRO interleaving on a polar code output by a polar code encoder claim 1 , to obtain interleaved bits ...

RECEPTION APPARATUS AND ASSOCIATED METHOD OF RECEIVING ENCODED DATA

A transmission apparatus includes an encoder that codes a data sequence with a parity check matrix, wherein the data sequence includes a final information bit sequence and virtual information bits, and outputs the final information bit sequence and a parity sequence, as LDPC codes, and a transmitter that transmits the LDPC codes as a transmission data. A column length of the parity check matrix is longer than a total length of the final information bit sequence and the parity sequence, by a length of the virtual information bits that are set to “0” and are not transmitted. The total length of the final information bit sequence and the parity sequence has a sequence length corresponding to a length from a first column to a predetermined column of the parity check matrix. The encoder generates the LDPC codes by using the first column to the predetermined column among one or more column(s) of the parity check matrix. The present invention relates to an encoder, decoder and encoding method using a low-density parity-check convolutional code (LDPC-CC) supporting a plurality of coding rates.In recent years, attention has been attracted to a low-density parity-check (LDPC) code as an error correction code that provides high error correction capability with a feasible circuit scale. Because of its high error correction capability and ease of implementation, an LDPC code has been adopted in an error correction coding scheme for IEEE802.11n high-speed wireless LAN systems, digital broadcasting systems, and so forth.An LDPC code is an error correction code defined by low-density parity check matrix H. An LDPC code is a block code having a block length equal to number of columns N of parity check matrix H (e.g. see Non-Patent Literature 1, Non-Patent Literature 4, or Non-Patent Literature 11). A random-like LDPC code, array LDPC code, and QC-LDPC code (QC: Quasi-Cyclic) are proposed in Non-Patent Literature 2, Non-Patent Literature 3, and Non-Patent Literature 12, for example. ...

PARITY CHECK MATRIX GENERATING METHOD, ENCODING APPARATUS, ENCODING METHOD, DECODING APPARATUS AND DECODING METHOD USING THE SAME

A method of low density parity check (LDPC) encoding includes: receiving a plurality of information word bits; LDPC encoding the information word bits using a parity check matrix in which a sum of elements in same positions in a plurality of groups constituting the parity check matrix is less than 2; and generating LDPC codeword bits comprising the information word bits and parity bits as a result of the LDPC encoding, wherein each of the plurality of groups constituting comprises a same number of columns. 1. A method of low density parity check (LDPC) encoding , the method comprising:receiving a plurality of information word bits;LDPC encoding the information word bits using a parity check matrix in which a sum of elements in same positions in a plurality of groups constituting the parity check matrix is less than 2; andgenerating LDPC codeword bits comprising the information word bits and parity bits as a result of the LDPC encoding,wherein each of the plurality of groups constituting comprises a same number of columns.2. The method of claim 1 , wherein a number of the plurality of groups is an integer multiple of a number of bits constituting a modulation symbol to be generated from the LDPC codeword bits.3. The method of claim 2 , wherein bits among the LDPC codeword bits corresponding to different parity check equations constitute the modulation symbol claim 2 , andwherein each of the parity check equations is formed of bits corresponding to columns where 1 exists in a row in the parity check matrix.4. The method of claim 3 , wherein the bits constituting the modulation symbol are separated by a same predetermined interval in the LDPC codeword bits.5. The method of claim 1 , further comprising generating the parity check matrix by:performing row permutation and column permutation on a preset parity check matrix;dividing the parity check matrix, on which the row permutation and the column permutation are performed, into the plurality of groups according to a ...

ROW ORTHOGONALITY IN LDPC RATE COMPATIBLE DESIGN

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low-density parity check (LDPC) codes, for example, using a parity check matrix having full row-orthogonality. An exemplary method for performing low-density parity-check (LDPC) decoding includes receiving soft bits associated to an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected. 1. A method for performing low-density parity-check (LDPC) decoding , the method comprising:receiving soft bits associated to an LDPC codeword; and each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code,', 'at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and', 'the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected., 'performing LDPC decoding of the soft bits using a parity check matrix, wherein2. The method of claim 1 , wherein in each pair of consecutive rows the two punctured variable nodes alternate connections to subsequent rows.3. The method of claim 1 , wherein at least ½ of all pairs of consecutive rows of the parity check matrix have row orthogonality.4. The method of claim 3 , wherein the ½ of all pairs of consecutive rows comprises the last ½ of all rows of the parity check matrix claim 3 , and wherein the last ½ of all rows of the parity check matrix correspond to rows associated with hybrid automatic repeat request (HARQ) information ...

PROCESSING METHOD AND DEVICE FOR QUASI-CYCLIC LOW DENSITY PARITY CHECK CODING

Provided are a processing method and device for quasi-cyclic low density parity check (LDPC) coding. The processing method for LDPC coding includes: determining, according to a data feature of an information bit sequence to be encoded, a processing strategy for the quasi-cyclic LDPC coding according to a data feature of an information bit sequence to be encoded; and performing, according to the processing strategy and based on a base matrix and a lifting size, the quasi-cyclic LDPC coding and rate matching output on the information bit sequence according to the processing strategy, a base matrix and a lifting value. This technical solution is able to improve adaptability and flexibility of the quasi-cyclic LDPC coding. 184-. (canceled)85. A processing method for quasi-cyclic low density parity check (LDPC) coding , comprising:determining, according to a data feature of an information bit sequence to be encoded, a processing strategy for the quasi-cyclic LDPC coding; andperforming, according to the processing strategy and based on a base matrix and a lifting size, the quasi-cyclic LDPC coding.86. The method of claim 85 , wherein the data feature comprises at least one of a length of the information bit sequence and a modulation and coding scheme (MCS) index of the information bit sequence.87. The method of claim 85 , wherein determining the processing strategy for the quasi-cyclic LDPC coding comprises determining at least one of a maximum number of systematic columns of the base matrix claim 85 , a maximum number of systematic columns of the quasi-cyclic LDPC coding claim 85 , a minimum code rate of the base matrix at a maximum length of the information bit sequence claim 85 , and a maximum information length supported by the quasi-cyclic LDPC coding.88. The method of claim 87 , wherein the maximum number of systematic columns of the base matrix is selected from at least two integer values greater than or equal to 2 and less than or equal to 32.89. The method of ...

QC-LDPC DECODER, METHOD FOR PERFORMING LAYERED DECODING AND STORAGE DEVICE

A QC-LDPC decoder includes: a zero matrix monitoring circuit, configured to monitor whether a submatrix of a check matrix of QC-LDPC coding information is a zero matrix; a check node processing circuit, configured to calculate check message of the check node by using the check matrix according to variable message of a variable node if the submatrix is not a zero matrix; a variable node processing circuit, configured to update the variable message of the variable node according to the check message returned by the check node if the submatrix is not a zero matrix; and a check circuit, configured to determine whether the variable message satisfies a check standard or not. 1. A QC-LDPC decoder , comprising:a zero matrix monitoring circuit, configured to monitor whether a submatrix of a check matrix of QC-LDPC coding information is a zero matrix;a check node processing circuit, configured to calculate check message of the check node by using the check matrix according to variable message of a variable node if the submatrix is not a zero matrix;a variable node processing circuit, configured to update the variable message of the variable node according to the check message returned by the check node if the submatrix is not a zero matrix; anda check circuit, configured to determine the variable message as decoded information if the variable message satisfies a check standard, and determine that decoding fails if the number of updates of the variable message exceeds a predetermined threshold but the check standard is still not satisfied.2. The QC-LDPC decoder according to claim 1 , wherein the check matrix of the QC-LDPC coding information is divided into M layers claim 1 , M being a positive integer; and{'sup': 'th', 'the QC-LDPC decoder is configured to decode the QC-LDPC coding message from a first layer to an Mlayer.'}3. The QC-LDPC decoder according to claim 2 , further comprising a delay circuit; wherein{'sup': th', 'th, 'the delay circuit is arranged in a data ...

METHOD AND DEVICE FOR DECODING LOW DENSITY PARITY CHECK CODE FOR FORWARD ERROR CORRECTION IN WIRELESS COMMUNICATION SYSTEM

A method for decoding a low density parity check (LDPC) code for forward error correction by a receiver side in a wireless communication system according to an embodiment of the present invention comprises the steps of: acquiring a first reconstructed packet vector by decoding a reception packet vector encoded by an LDPC code generation matrix; determining a candidate for an error packet to be excluded form the reception packet vector when an error is detected in the first reconstructed packet vector; and acquiring a second reconstructed packet vector from the reception packet vector from which the determined candidate for the error packet has been excluded, wherein the step of acquiring the second reconstructed packet vector includes acquiring the second reconstructed packet vector through Gaussian elimination for the LDPC code generation matrix from which a row matrix corresponding to the candidate for the error packet has been excluded. 1. A method for decoding a low density parity check (LDPC) code for forward error correction (FEC) by a reception terminal of a wireless communication system , the method comprising:acquiring a first reconstructed packet vector by decoding a reception (Rx) packet vector encoded by an LDPC code generation matrix;if an error is detected in the first reconstructed packet vector, determining a candidate of an error packet to be excluded from the Rx packet vector; andacquiring a second reconstructed packet vector from the Rx packet vector from which the determined error packet candidate is excluded,wherein the acquiring the second reconstructed packet vector includesacquiring the second reconstructed packet vector through Gaussian elimination for the LDPC code generation matrix from which a row vector corresponding to the error packet candidate is excluded.2. The method according to claim 1 , wherein the determining the error packet candidate includes:determining the error packet candidate based on a weight of each row vector contained ...

METHOD AND APPARATUS FOR DATA PROCESSING WITH STRUCTURED LDPC CODES

The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding. 1. A method for wireless communication , comprising:determining a code block size for Low Density Parity Check (LDPC) coding;determining a coding expansion factor Z from a set of coding expansion factors based on the code block size and a parameter kb associated with a basic check matrix, wherein the parameter kb is an integer larger than or equal to four and smaller than or equal to 64, and wherein the coding expansion factor Z is equal to a positive integer power of two minus one or a product of a positive integer power of two and a prime number; andencoding a data sequence based on the basic check matrix and the coding expansion factor Z.2. The method of claim 1 , wherein at least one value in the set of coding expansion factors is equal to a product of a positive integer power of two and a prime number.3. The method of claim 2 , wherein the prime number comprises one of: 3 claim 2 , 5 claim 2 , 7 claim 2 , 11 claim 2 , or 13.4. The method of claim 1 , wherein at least one value in the set of coding expansion factors is equal to a product of a positive integer power of two and an odd number.5. The method of claim 1 , wherein the set of coding expansion factors includes at least 6 claim 1 , 12 claim 1 , ...

ERROR CORRECTION AND DECODING

Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors. 1. An error detection and correction apparatus , comprising:a syndrome generator configured to receive input data and to output a syndrome that indicates whether the input data includes an error;a positive edge triggered flip-flop that is configured to receive syndrome input based on the syndrome from the syndrome generator and to provide a syndrome output; andan error location decoder configured to receive the syndrome output from the positive edge triggered flip-flop.2. The error detection and correction apparatus of claim 1 , further comprising:a timing controller configured to receive a clock signal, and to delay the clock signal by a given amount of time by passing the clock signal through a delay line,wherein the positive edge triggered flip-flop is controlled by the delayed clock signal.3. The error detection and correction apparatus of claim 1 , wherein the given amount of time is configured to mimic a delay associated with a critical path of the syndrome generator.4. The error detection and correction apparatus of claim 1 , further comprising:an error detector configured to generate corrected output data,wherein the error location decoder is configured to provide, based on the syndrome output, both a single error location decoder output and a double error location decoder output to the error detector.5. The error detection and correction apparatus of claim 4 , wherein the syndrome input received at the positive edge triggered flip-flop corresponds to the syndrome that is output from the syndrome generator.6. The error detection and correction apparatus of ...

APPARATUS, SYSTEM AND METHOD OF COMMUNICATING A TRANSMISSION ENCODED ACCORDING TO A LOW-DENSITY PARITY-CHECK (LDPC) CODE

Some demonstrative embodiments include apparatus, system and method of communicating a transmission encoded according to a Low-Density Parity-Check (LDPC) code. For example, an apparatus may include logic and circuitry configured to cause a wireless station to encode a plurality of data bits into a plurality of codewords according to an LDPC code having an encoding rate of ⅞ and a codeword length of 1248 bits; and to transmit a transmission over a millimeter Wave (mmWave) frequency band based on the plurality of codewords. 1. An apparatus comprising logic and circuitry configured to cause a wireless station to:encode a plurality of data bits into a plurality of codewords according to a Low-Density Parity-Check (LDPC) code having an encoding rate of ⅞ and a codeword length of 1248 bits; andtransmit a transmission over a millimeter Wave (mmWave) frequency band based on the plurality of codewords.2. The apparatus of claim 1 , wherein a codeword of the plurality of codewords comprises 1092 data bits and 156 parity bits claim 1 , the 156 parity bits are based on the 1092 data bits.3. The apparatus of configured to cause the wireless station to determine a set of parity bits by applying a code matrix to the 1092 data bits claim 2 , the set of parity bits comprising more than 156 bits claim 2 , and to generate the codeword by appending 156 bits of the set of parity bits to the 1092 data bits.4. The apparatus of claim 3 , wherein the code matrix comprises a lifting matrix.5. The apparatus of claim 3 , wherein the set of parity bits comprises 252 parity bits.60122510110910110919697251. The apparatus of claim 5 , wherein the 252 parity bits comprise a sequence of bits denoted {p claim 5 , p claim 5 , p claim 5 , . . . claim 5 , p} claim 5 , the 1092 data bits comprise a sequence of bits denoted {S claim 5 , S claim 5 , . . . claim 5 , S} claim 5 , and the codeword comprises a sequence of the bits {S claim 5 , S claim 5 , . . . claim 5 , S claim 5 , p claim 5 , p claim 5 , . . ...

Apparatus and Method for Multi-Code Distributed Storage

Systems and techniques described herein include jointly decoding coded data of different codes, including different coding algorithms, finite fields, and/or source blocks sizes. The techniques described herein can be used to improve existing distributed storage systems by allowing gradual data migration. The techniques can further be used within existing storage clients to allow application data to be stored within diverse different distributed storage systems. 1. A method for use in a multi-code storage system , the method comprising:receiving a first set of symbols associated with a file, wherein the first set of symbols comprises a first set of source symbols or a first set of coded symbols encoded using the first set of source symbols;receiving a second set of symbols associated with the file, wherein the second set of symbols comprises a second set of source symbols or a second set of coded symbols encoded using the second set of source symbols with the first set of source symbols being different than the second set of source symbols, and wherein either the first set of symbols or the second set of symbols are a set of coded symbols; andjointly decoding the first and second symbols to recover the file.2. The method of whereinreceiving the first set of symbols includes receiving first coded symbols encoded using a first code;receiving the second set of symbols includes receiving second coded symbols encoded using a second code, wherein the first and second codes differ in at least one of generator matrices, finite fields, or block sizes, or combinations thereof; andjointly decoding the first and second symbols includes jointly decoding the first and second coded symbols.3. The method of wherein:receiving the first set of symbols comprises receiving the first set of symbols from a first distributed storage system; andreceiving the second set of symbols comprises receiving the second set of symbols from a second distributed storage system.4. The method of wherein ...

TRANSMITTER APPARATUS AND BIT INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The transmitting method of claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The transmitting method of claim 1 , wherein the interleaving further comprises:interleaving the interleaved plurality of bit groups.4. The transmitting method of claim 1 , wherein the π(j) is determined based on at least one of the code length claim 1 , a modulation method for the mapping claim 1 , and the code rate.6. The method of claim 5 , wherein each of the plurality of groups comprises 360 values.7. The method of claim 5 , wherein the π(j) is determined based on at least one of the code length claim 5 , a modulation method for the mapping claim 5 , and the code rate. This is a Continuation of U.S. application Ser. No. 16/460,305 filed Jul. 2, 2019, which is a Continuation of U.S. application Ser. No. 15/686,280 filed Aug. 25, 2017, which is a Continuation of application Ser. No. 14/716,503 filed May 19, 2015, and claims priority from U.S. Provisional Application No. 62/001,160 filed on May 21, 2014 and Korean Patent Application No. 10-2015-0069924 filed on May 19, 2015, the disclosures of which are incorporated herein by reference in their entirety.Apparatuses and methods consistent with exemplary embodiments ...

Distributed Storage System Data Management And Security

A system and method for distributing data over a plurality of remote storage nodes. Data are split into segments and each segment is encoded into a number of codeword chunks. None of the codeword chunks contains any of the segments. Each codeword chunk is packaged with at least one encoding parameter and identifier, and metadata are generated for at least one file and for related segments of the at least one file. The metadata contains information to reconstruct from the segments, and information for reconstructing from corresponding packages. Further, metadata are encoded into package(s), and correspond to a respective security level and a protection against storage node failure. A plurality of packages are assigned to remote storage nodes to optimize workload distribution. Each package is transmitted to at least one respective storage node as a function iteratively accessing and retrieving the packages of metadata and file data. 118-. (canceled)19. A method of data retrieval from remote storage nodes , the method comprising:accessing, by one or more processors configured to execute code stored in non-transitory processor readable media, file metadata references within a local cache or within remote storage nodes;receiving, by the one or more processors, a plurality of packages from remote storage nodes by metadata references, each of the packages contain file metadata;receiving, by the one or more processors, a plurality of other packages containing encoded file segments from storage nodes by data references, wherein the encoded file segments are obtained at least partly from file metadata;reconstructing, by the one or more processors, file data from the packages as a function of metadata representing parameters associated with an encoding scheme and file splitting scheme.20. The method of claim 19 , wherein file retrieval speed is enhanced by caching metadata from a plurality of client side files.2140-. (canceled)41. A system for data retrieval from remote ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

The present invention provides an apparatus of transmitting broadcast signals, the apparatus including, an encoder for encoding service data, a frame builder for building at least one signal frame by mapping the encoded service data, a modulator for modulating data in the built at lease one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signals having the modulated data. 5. An apparatus of receiving broadcast signals , the apparatus including:a receiver configured to receive the broadcast signals;a demodulator configured to demodulate the received broadcast signals including service data by an Orthogonal Frequency Division Multiplexing (OFDM) scheme; anda Low-Density Parity Check (LDPC) decoder configured to LDPC decode service data based on a matrix,wherein the service data is a codeword having information bits and parity bits, when a length of the codeword is 16200 bits and a code rate of the codeword is 7/15, the matrix is determined based on a following table:{'img': {'@id': 'CUSTOM-CHARACTER-00001', '@he': '7.53mm', '@wi': '135.93mm', '@file': 'US20200021860A1-20200116-P00999.TIF', '@alt': 'text missing or illegible when filed', '@img-content': 'character', '@img-format': 'tif'}}wherein each row of the table corresponds to each group of 360 information bits,wherein each value in the each row represents an address of a parity bit.6. The apparatus of claim 5 ,wherein the LDPC decoder decodes data being updated a parity bit of the codeword which is located in an address of j-th entry in i-th row in the table by accumulating an information bit of the codeword to the parity bit of the codeword, and updated the parity bit.7. A method of receiving broadcast signals claim 5 , the method including:receiving the broadcast signals;demodulating the received broadcast signals including service data by an Orthogonal Frequency Division Multiplexing (OFDM) scheme; andLow-Density Parity Check (LDPC) ...

USING PARITY DATA FOR CONCURRENT DATA AUTHENTICATION, CORRECTION, COMPRESSION, AND ENCRYPTION

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data. 1a processing core for executing computer instructions and accessing data from a main memory; anda non-volatile storage medium for storing the computer instructions, a data matrix for holding the original data in the first memory;', 'a check matrix for holding the ECC data in the first memory;', 'an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and', a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix; and', 'a sequencer for ordering operations through the data matrix and the encoding matrix using the Galois Field multiplier to generate the ECC data., 'a thread for executing on the processing core and comprising], 'wherein the processing core, the non-volatile storage medium, and the computer instructions are configured to implement the software ECC protection or compression of the original data using the ECC data in the first memory, the software ECC protection or compression comprising. A system for software error- ...

SYSTEMS AND METHODS FOR ERROR CORRECTION CODING

Described are methods, systems, and apparatus, including computer program products for error correction coding and decoding procedures for data storage or transfer. A plurality of data blocks is received. A plurality of checksum blocks are generated by multiplying the plurality of data blocks by a coding matrix, where the coding matrix comprises values of at least one basic interpolation polynomial and the multiplying is according to a finite field arithmetic for a finite field comprising all possible values of the plurality of data blocks and the plurality of coding blocks. The plurality of data blocks and the plurality of checksum blocks are stored in a data storage medium. 1. A computer-implemented method for systematically coding a plurality of data blocks for error detection and correction , the method comprising:receiving, by a computer system, the plurality of data blocks;generating, by the computer system, a plurality of checksum blocks by multiplying the plurality of data blocks by a coding matrix, wherein the coding matrix comprises values of at least one basic interpolation polynomial, the multiplying according to a finite field arithmetic for a finite field comprising all possible values of the plurality of data blocks and the plurality of coding blocks; andstoring, by the computer system, the plurality of data blocks and the plurality of checksum blocks in a data storage medium.2. The computer-implemented method of claim 1 , wherein the coding matrix consists of a plurality of values of a plurality of basic interpolation polynomials computed for a sequence of powers of a primitive element of the finite field.4. The computer-implemented method of claim 1 , further comprising:generating, by the computer system, the coding matrix in response to receiving the plurality of data blocks;receiving, by the computer system, a second plurality of data blocks;generating, by the computer system, a second coding matrix in response to receiving the plurality of data ...

ADAPTIVE DESATURATION IN MIN-SUM DECODING OF LDPC CODES

A system implements adaptive desaturation for the min-sum decoding of LDPC codes. Specifically, when an-above threshold proportion of messages from check nodes to variable nodes (CN-to-VN messages) are saturated to a maximum fixed-precision value, all CN-to-VN messages are halved. This facilitates the saturation of correct messages and boosts error correction over small trapping sets. The adaptive desaturation approach reduces the error floor by orders of magnitudes with negligible add-on circuits. 1. A method comprising:receiving, by an electronic device, input data; andperforming, by the electronic device, min-sum decoding of the input data using a Tanner graph to generate decoded output data, the min-sum decoding including passing messages from variable nodes (VNs) to check nodes (CNs) in VN-to-CN messages and from CNs to VNs in CN-to-VN messages, each VN and CN having a value associated therewith, the values of the VNs being updated in response to CN-to-VN messages and the values of the CNs being updated in response to VN-to-CN messages; andduring performing min-sum decoding, in response to detecting that a proportion of the values of the CNs that exceed a maximum value meets a threshold condition, halving at least one of all of the CN-to-VN messages and all of the VN-to-CN messages.2. The method of claim 1 , wherein performing min-sum decoding of the input data to generate decoded output data comprises performing algorithm 3 of Table 3.3. The method of claim 1 , wherein performing min-sum decoding of the input data to generate decoded output data comprises performing algorithm 4 of Table 4.4. The method of claim 1 , wherein performing min-sum decoding of the input data to generate decoded output data comprises iteratively performing a plurality of iterations claim 1 , each iteration including passing of VN-to-CN messages followed by CN-to-VN messages claim 1 , wherein halving at least one of all of the CN-to-VN messages and all of the VN-to-CN messages is ...

UNIFIED H-ENCODER FOR A CLASS OF MULTI-RATE LDPC CODES

A quasi-cyclic LDPC encoding apparatus is disclosed wherein a matrix H of the form [0 T; D E] is used, where T is a triangular matrix and D and E are arbitrary matrices selected to improve encoding performance. T and E vary with the size of an encoded data word whereas D is maintained constant. T and E are sparse such that encoding operations performed on them are computationally simple. Likewise D and its inverse are constant and pre-computed further reducing computation. T, E, and D and the inverse of D may be constrained to be quasi-cyclic, which reduces storage required to represent them and enables the performance of encoding operations using shift registers. 3. (canceled)4. The method of claim 1 , wherein Dis pre-computed and is identical for each input data word u regardless of length.5. The method of claim 1 , wherein D claim 1 , D claim 1 , T claim 1 , E claim 1 , Hare all quasi-cyclic for all i.6. The method of claim 1 , wherein generating claim 1 , by the electronic device claim 1 , encoded data c for each input word u further comprises storing for each of D claim 1 , Dand for T claim 1 , Efor each i a first 1 in a first row for each circulant of D claim 1 , D claim 1 , T claim 1 , E.7. The method of claim 1 , wherein determining [s claim 1 , s] claim 1 , p claim 1 , and s′ claim 1 , each comprise performing barrel shifter and circulant-wise XOR operations combined into a single cycle.8. The method of claim 1 , wherein determining pcomprises using circular shift registers for calculation of each bit of p.9. The method of claim 1 , wherein D has the following properties:(i) D approaches maximum rank;(ii) D approaches maximum girth and does not contain small trapping sets;{'sup': '−1', '(iii) a pseudo inverse of D is in simple format such that the pseudo inverse Dis quasi cyclic when D is singular.'}10. The method of claim 1 , wherein Tis an identity matrix for all i.13. (canceled)14. The system of claim 11 , further comprising a memory storing D and D; ...

Reconfigurable fec

The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

Systems and Methods for Rank Independent Cyclic Data Encoding

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding. 1. A data processing system , the data processing system comprising: receive a user data input; and', 'apply a rank independent encoding algorithm to the user data input to yield an encoded output, wherein the rank independent encoding algorithm includes multiplying an interim data set by a quasi-pseudo inverse matrix., 'a rank independent data encoding circuit operable to2. The data processing system of claim 1 , wherein the quasi-pseudo inverse matrix is part of an encoding matrix claim 1 , and wherein the encoding matrix further includes a first user matrix claim 1 , a second user matrix claim 1 , a first interim matrix claim 1 , a second interim matrix.3. The data processing system of claim 2 , wherein the interim data set is a first interim data set claim 2 , and wherein the rank independent data encoding circuit comprises:a first vector multiplier circuit operable to multiply the user data input by an inverse of the first user matrix to yield a second interim data set;a second vector multiplier circuit operable to multiply the second interim data set by the first interim matrix to yield a third interim data set;a third vector multiplier circuit operable to multiply the third interim data set by the second interim matrix to yield a fourth interim data set;a fourth vector multiplier circuit operable to multiply the user data input by the second user matrix to yield a fifth interim data set; anda fifth vector multiplier circuit operable to multiply a combination of the fourth interim data set and the fifth interim data set by the quasi-pseudo inverse matrix to yield the first interim data set.4. The data processing system of claim 3 , wherein the rank independent data encoding circuit further comprises:an adder array circuit operable to add the fourth interim data set to the fifth interim data set to yield the combination ...

CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF

An operating method of a controller includes generating a square message matrix of k×k; and generating an encoded message by encoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code, wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix, wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and wherein “α”, “β” and N have relationships represented by equations 1 and 2: 3. The operating method of claim 2 ,{'sup': th', 'th', 'th, 'wherein the message blocks included in the (i)diagonal matrix group have the sequence such that a message block included in the (i+1)diagonal matrix has a sequentially higher priority than a message block included in the (k+1−i)diagonal matrix, and such that a message block of higher row has a sequentially higher priority in a diagonal matrix, and'}{'sup': th', 'th', 'th', 'th', 'th', 'th, 'wherein the generating of the encoded message includes, when the “β” numbers of message blocks are selected from the (i)diagonal matrix group, selecting (2*(n−1)*i+1)to ((2n−1)*i)message blocks prior to ((2n−1)*i+1)to (2n*i)message blocks among message blocks included in the (i)diagonal matrix group, where “n” is an integer greater than one (1).'}5. The operating method of claim 1 ,wherein the generating of the encoded message includes generating a parity block for each row of the square message matrix, andwherein each size of the zero-padding blocks is the same as the parity block.8. The controller of claim 7 ,{'sup': th', 'th', 'th, 'wherein the message blocks included in the (i)diagonal matrix group have the sequence such that a message block included in the (i+1)diagonal matrix has a sequentially higher ...

TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame. 1. A receiving method comprising:receiving a signal from a transmitting apparatus;demodulating the signal to generate values based on 64-quadrature amplitude modulation (QAM);inserting predetermined values;splitting the values and the inserted predetermined values into a plurality of groups;deinterleaving some groups among the plurality of groups based on a permutation order to provide deinterleaved plurality of groups in which the some groups are deinterleaved; anddecoding values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 16200 bits,wherein positions of the inserted predetermined values correspond to positions of parity bits punctured in the transmitting apparatus, andwherein groups having indices of 25, 42, 34, 18, 32, 38, 23, 30, 28, 36 and 41 among the deinterleaved plurality of groups comprise at least a part of the predetermined values.2. The receiving method of claim 1 , wherein a number ...

METHOD AND APPARATUS FOR CHANNEL ENCODING/DECODING IN COMMUNICATION OR BROADCAST SYSTEM

The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data transfer rate beyond a 4G communication system, such as LTE. One embodiment of the present invention provides a method for channel encoding in a communication system, the method comprising: encoding second data, using an outer channel code; determining a value corresponding to first data; arranging the encoded second data in a block size unit corresponding to the second data, based on the determined value; and encoding the arranged second data, using an inner channel code. 1. A method of channel decoding performed by a receiver in a communication system , the method comprising:receiving a first signal and a second signal corresponding to input bits;identifying first values based on the first received signal and second values based on the second received signal;identifying groups of the first values and groups of the second values, each of the groups of the first values and the groups of the second values having a bit group size;performing quasi-cyclic shifting of the groups of the second values based on the bit group size and an integer;combining the groups of the first values and the quasi-cyclic shifted groups of the second values;performing inner decoding, based on an inner channel code, on the combined values;performing outer decoding, based on an outer channel code, on an output of the inner decoding; andidentifying the input bits that indicate first data from an output of the outer decoding,wherein the integer is identified as a difference between a first cyclic shift value applied to the groups of the first values and a second cyclic shift value applied to the groups of the second values, andwherein second data is identified based on the first cyclic shift value, in case that the outer decoding is successful.2. The method of claim 1 , wherein:the outer channel code includes at least one of cyclic redundancy check (CRC) code or Bose-Chaudhuri-Hocquenghem (BCH) ...

LOW-COMPLEXITY LDPC ENCODER

Techniques are described for encoding information data bits using a low-density parity-check matrix optimized for a Low-Density Parity-Check (LDPC) encoder. In an example, the parity-check matrix includes a first matrix and a second matrix. The second matrix is a square matrix, and is also a block diagonal matrix that includes a set of square submatrices located on the diagonal of the block diagonal matrix. An intermediate vector is generated based on the information data bits and the first matrix, and a parity vector of a codeword is generated based on the intermediate vector and the second matrix. 1. A computer-implemented method of encoding an information vector , the computer-implemented method comprising:receiving, by a computer system, the information vector to be encoded into a low-density parity-check (LDPC) codeword; the parity-check matrix includes a first matrix and a second matrix;', 'the second matrix includes a block diagonal matrix; and', 'the block diagonal matrix includes a set of square submatrices located on a diagonal of the block diagonal matrix;, 'accessing, by the computer system, a parity-check matrix, whereingenerating, by the computer system, an intermediate vector based on the information vector and the first matrix;generating a parity vector based on the intermediate vector and the second matrix; andgenerating, by the computer system, the LDPC codeword including the information vector and the parity vector.2. The computer-implemented method of claim 1 , further comprising:writing the LDPC codeword to a storage device; ortransmitting the LDPC codeword via a communication channel.3. The computer-implemented method of claim 1 , wherein generating the parity vector comprises:dividing, by the computer system, the intermediate vector into a set of intermediate sub-vectors, each intermediate sub-vector corresponding to a square submatrix of the set of square submatrices; and 'generating, by the computer system, a corresponding parity sub-vector ...

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 64800 bits and an encoding rate r is 7/15, 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code. 1. A method for generating a digital television broadcast signal , and for decreasing a signal-to-noise power ratio of the generated digital television broadcast signal , the method comprising:receiving data to be transmitted in a digital television broadcast signal; wherein the LDPC code word includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors,', 'the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,', 'the information matrix portion is represented by a parity check matrix initial value table, and', 'the parity check matrix initial value table, having each row indicating positions of elements ‘1’ in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows, 'performing low density parity check (LDPC) encoding in an LDPC encoding circuitry, on input bits of the received data according to a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 9/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of ...

Method and Apparatus for Processing Information

Provided are a method and apparatus for processing information. The apparatus includes: one or more memories, configured to store parameters of one basic parity check matrix set; and one or more processors, configured to encode information bits to be encoded or decode data to be decoded using the basic parity check matrix set Hb, wherein at least 50 percent of short loops-4 in a basic parity check matrix Hbamong all basic parity check matrices in the basic parity check matrix set Hb except Hbare the same as short loops-4 in the Hb, where j0 is a fixed positive integer between 0 and L−1, L is the number of basic parity check matrices contained in the basic parity check matrix set, and j1=0, 1, . . . , j0−1, j0+1, . . . , L−1. 1. An apparatus for processing information , comprising:one or more memories, configured to store parameters of one basic parity check matrix set; and{'sub': j1', 'j0', 'j0, 'one or more processors, configured to encode information bits to be encoded or decode data to be decoded using the basic parity check matrix set Hb, wherein at least 50 percent of short loops-4 in a basic parity check matrix Hbamong all basic parity check matrices in the basic parity check matrix set Hb except Hbare the same as short loops-4 in the Hb, where j0 is a fixed positive integer between 0 and L−1, L is the number of basic parity check matrices contained in the basic parity check matrix set, and j1=0, 1, . . . , j0−1, j0+1, . . . , L−1.'}2. The apparatus as claimed in claim 1 , wherein a dimension of each basic parity check matrix in the basic parity check matrix set is Mb×Nb claim 1 , the number of columns Nb is a fixed value nb0 claim 1 , the number of rows Mb is mbi claim 1 , and each mbi corresponds to one code rate ri claim 1 , where ri is a real number between 0 and 1 claim 1 , i=0 claim 1 , 1 claim 1 , 2 claim 1 , . . . claim 1 , L−1 claim 1 , mbi is an integer greater than 0 claim 1 , and nb0 is an integer greater than 0.3. The apparatus as claimed in claim ...

SCHEDULING STRATEGIES FOR ITERATIVE DECODERS

An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates. 1. A method comprising:receiving, by a generic row decoder unit, soft information regarding a codeword at an iterative parity check decoder that operates according to a parity check matrix arranged as a plurality of ordered rows, each ordered row corresponding to a parity constraint, and the plurality of ordered rows grouped into a plurality of subsets;performing updates of soft information at the iterative parity check decoder for a particular iteration by sequentially updating the plurality of subsets, one subset at a time using results based on previous subset updates of the particular iteration, each parity constraint in a subset being updated in parallel with the other parity constraints in the same subset; and converging on the codeword after the particular iteration.2. The method of claim 1 , wherein the generic row decoder unit includes an array of decoder boxes claim 1 , each decoder box in the array of decoder boxes configured to update a single ordered row at a time.3. The method of claim 1 , wherein the results based on previous subset updates of the particular iteration include updated soft information.4. The method of claim 2 , wherein a total quantity of the decoder boxes is equal to a total quantity of the parity constraints in a subset with the most parity constraints in the plurality of subsets.5. The method of claim 1 , further comprising:addressing, by the decoder, a particular row of the parity-check matrix for use with each update of a parity constraint.6. The method of claim 1 , further comprising:transmitting soft information after the particular iteration to a channel detector for one or more channel ...

HIERARCHICAL VARIABLE CODE RATE ERROR CORRECTION CODING

A system for hierarchical variable code rate error correction coding may include at least one circuit that is configured to identify a row of a hierarchical portion of a generator matrix that corresponds to a determined code rate, determine a number of information bits to apply to the hierarchical portion based at least on the identified row, and apply the determined number of information bits to the identified row. The circuit may be further configured to apply an output of the identified row to a subsequent row of the hierarchical portion, when the hierarchical portion includes a subsequent row, and apply an output of a last row of the hierarchical portion to a base portion of the generator matrix. The circuit may be further configured to provide a codeword output by the base portion of the generator matrix. 1. A device comprising: identify a row of a hierarchical portion of a generator matrix that corresponds to a determined code rate;', 'determine a number of information bits to apply to the hierarchical portion of the generator matrix based at least on the identified row;', 'apply the determined number of information bits to the identified row of the hierarchical portion of the generator matrix;', 'apply an output of the identified row of the hierarchical portion of the generator matrix to a subsequent row, from top to bottom, of the hierarchical portion of the generator matrix, when the hierarchical portion of the generator matrix comprises the subsequent row;', 'apply an output of a last row, from top to bottom, of the hierarchical portion of the generator matrix to a base portion of the generator matrix; and', 'provide a codeword output by the base portion of the generator matrix., 'at least one circuit configured to2. The device of claim 1 , wherein the at least one circuit is further configured to:determine the number of information bits based at least in part on a number of non-null circulants in the identified row.3. The device of claim 1 , wherein the ...

METHOD FOR PROCESSING DATA BLOCK IN LDPC ENCODER

A method for communication device processing a data block in a low-density parity-check (LDPC) encoder includes the steps of, if a size of a payload is equal to or greater than a prescribed size, performing code block segmentation, and performing encoding in a unit of a code block on code blocks according to the code block segmentation. In this case, the code block segmentation may be performed by a payload size supported by a parity check matrix (H) corresponding to a coding rate of the LDPC encoder. 1. A method for a communication device processing a data block in a low-density parity-check (LDPC) encoder , the method comprising:if a size of a payload is equal to or greater than a prescribed size, performing code block segmentation; andperforming encoding in a unit of a code block on code blocks according to the code block segmentation,wherein the code block segmentation is performed by a payload size supported by a parity check matrix (H) corresponding to a coding rate of the LDPC encoder.2. The method of claim 1 , wherein the code block segmentation is performed to minimize a number of the code block.3. The method of claim 1 , wherein the code block segmentation is performed using one of a plurality of payload sizes supported by the parity check matrix (H).4. The method of claim 1 , further comprising:if a size of an encoded bit according to the encoding is not a size defined by the parity check matrix (H) corresponding to a coding rate of the LDPC encoder, performing rate matching or shortening.5. The method of claim 4 , wherein the rate matching comprises puncturing or repetition.6. The method of claim 1 , further comprising:attaching a CRC (cyclic redundancy check) to a code block after the code block segmentation is performed.7. The method of claim 1 , wherein the payload is segmented into different payload sizes supported by the parity check matrix (H) corresponding to a coding rate of the LDPC encoder.8. A communication device for processing a data block ...

SELECTING STORAGE RESOURCES IN A DISPERSED STORAGE NETWORK

A method for execution by a dispersed storage and task (DST) client module includes determining a storage unit performance level for storage units of a set of storage units. Storage resources of the set of storage units are temporarily selected based on the storage unit performance levels to produce identities of candidate primary storage slots. Identities of candidate primary storage slots are exchanged with another DST client module. Selection of primary storage slots of the candidate primary storage slots is coordinated with the other non-transitory computer readable storage medium to produce identities of selected primary storage slots. Data stored in the set of storage units is accessed using the selected primary storage slots. 1. A method for execution by a dispersed storage and task (DST) client module that includes a processor , the method comprises:determining a storage unit performance level for storage units of a set of storage units;temporarily selecting storage resources of the set of storage units based on the storage unit performance levels to produce identities of candidate primary storage slots;exchanging identities of candidate primary storage slots with another DST client module;coordinating selection of primary storage slots of the candidate primary storage slots with the another DST client module to produce identities of selected primary storage slots; andaccessing data stored in the set of storage units using the selected primary storage slots.2. The method of claim 1 , wherein the data accessed using the selected primary storage slots includes a data segment claim 1 , and wherein the data segment was dispersed storage error encoded to produce a set of encoded data slices for storage in the selected primary storage slots.3. The method of claim 2 , wherein the identities of the candidate primary storage slots are determined such that a decode threshold number of encoded data slices of the set of encoded data slices are available from any two ...

DISTRIBUTED SECURE DATA STORAGE AND TRANSMISSION OF STREAMING MEDIA CONTENT

Disclosed is a method for the distributed storage and distribution of data. Original data is divided into fragments and erasure encoding is performed on it. The divided fragments are dispersedly stored on a plurality of storage mediums, preferably that are geographically remote from one another. When access to the data is requested, the fragments are transmitted through a network and reconstructed into the original data. In certain embodiments, the original data is media content which is steamed to a user from the distributed storage. 1. A method of processing media content , comprising the steps of:separating the media content into a plurality of file slices;generating metadata for the reassembly of media content from the file slices;erasure coding the file slices, wherein the slices are divided into discrete file slice fragments;generating metadata for the reassembly of the file slices from the file slice fragments; andsending the file slice fragments to a plurality of dispersed networked storage nodes, wherefrom the media content may be retrieved and reconstructed using the metadata.2. The method of wherein the media content is not recognizable from the erasure-coded file slice fragments.3. The method of wherein the step of erasure coding is performed across a plurality of data processors.4. The method of claim 2 , further comprising the steps of:receiving at a client decoder the file slice fragments from the networked storage nodes; andreconstructing the media content according to the metadata.5. The method of wherein the media content is one of streaming video and audio content claim 4 , and wherein the step of reconstructing the media content is performed contemporaneously during playback of the media content.6. The method of wherein the steps of receiving and reconstructing are performed in response to a client request for the media content; and/or wherein each file slice fragment is assigned a unique identifier and the metadata indicates the location of each ...

DATA STORAGE DEVICE, OPERATION METHOD THEREOF AND STORAGE SYSTEM HAVING THE SAME

A data storage device may include: a storage configured to store user data, firmware and a boot code; and a controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange, wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged to with the storage based on a second parity check matrix extracted from the firmware during a second operation mode. 1. A data storage device comprising:a storage configured to store user data, firmware and a boot code; anda controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange,wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged with the storage based on a second parity check matrix extracted from the firmware during a second operation mode.2. The data storage device of claim 1 , wherein the first operation mode comprises an input and output mode for user data.3. The data storage device of claim 2 , wherein the second operation mode is decided among operation modes excluding the first operation mode.4. The data storage device of claim 1 , wherein the second operation mode comprises an update mode for the boot code.5. The data storage device of claim 1 , wherein the firmware comprises a set of parity check matrix codes for respective code rates of an ECC code used in the ECC engine.6. The data storage device of claim 5 , wherein the storage stores firmware which is updated as any of the parity check matrix codes is changed or another ...

TRANSMISSION METHOD AND RECEPTION DEVICE

The present technology relates to a transmission method and a reception device capable of ensuring good communication quality in data transmission by using an LDPC code. In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of bit groups of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code after the group-wise interleaving is returned to an original arrangement. The present technology can be applied, for example, to the case of performing data transmission by using an LDPC code or the like. The present technology relates to a transmission method and a reception device, and more particularly, to a transmission method and a reception device that can ensure good communication quality, for example, in data transmission using an LDPC code.Low density parity check (LDPC) codes have high error correction capability, and in recent years, have been widely adopted in transmission schemes such as digital broadcasting, for example, digital video broadcasting (DVB)-S.2, or DVB-T.2, DVB-C.2, in Europe or the like or advanced television systems committee (ATSC) 3.0 or the like in the United States or the like (refer to, for example, Non-Patent Document 1).With recent researches, it has been found that, similarly to turbo codes and the like, in LDPC codes, performance close to the Shannon limit is obtained as the code length is increased. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, features that a block error probability characteristic is good and so-called error floor phenomenon observed in a decoding characteristic of turbo code or the like hardly occurs are also mentioned as an advantage.In data transmission using an LDPC code, for example, the LDPC code becomes a symbol of quadrature modulation (digital modulation) such as quadrature phase shift keying (QPSK) (that is, the LDPC code is symbolized), and the symbol is mapped to a signal point of ...

SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES WITH SELF-GENERATED LLR

Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, recording a number of flip(s) for each bit of the codeword, generating reliability information for each bit based on the number of flip(s) for each bit respectively, determining to switch to soft decision decoding according to a switching rule and performing a soft decision decoding on the codeword using the reliability information for each bit. 1. A method , comprising:performing a hard decision decoding on a codeword;recording a number of flip(s) for each bit of the codeword;generating reliability information for each bit based on the number of flip(s) for each bit respectively;determining to switch to soft decision decoding according to a switching rule; andperforming a soft decision decoding on the codeword using the reliability information for each bit.2. The method of claim 1 , wherein the switching rule comprises a threshold number for a total number of flips for all bits of the codeword accumulated in a current decoding session.3. The method of claim 2 , wherein the current decoding session is an iteration claim 2 , one or more layers claim 2 , or one or more columns based on a configuration of the hard decision decoding.4. The method of claim 2 , wherein the threshold number is configured based on a shape and/or characteristic of a parity check matrix used for checking the codeword.5. The method of claim 4 , wherein the threshold number is configured based on simulation for the parity check matrix.6. The method of claim 1 , wherein the switching rule comprises a threshold number based on an instant syndrome value.7. The method of claim 1 , further comprising switching to the hard decision decoding when the soft decision decoding does not decrease a syndrome value.8. An apparatus claim 1 , comprising:a decoder core configured to perform decoding in a hard decision decoding mode and a soft decision ...

METHOD AND APPARATUS FOR ENCODING AND DECODING LOW DENSITY PARITY CHECK CODES

An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column. 2. The transmitting method of claim 1 , wherein the information sub matrix comprises column groups claim 1 ,wherein the positions represent positions of weight-1 in a first column of each column group, andwherein positions of weight-1 in subsequent columns of the each column group are cyclic-shifted by a coding parameter from previous columns of the each column group, respectively.4. The receiving method of claim 3 , wherein the information sub matrix comprises column groups claim 3 ,wherein the positions represent positions of weight-1 in a first column of each column group, andwherein positions of weight-1 in subsequent columns of the each column group are cyclic-shifted by a coding parameter from previous columns of the each column group, respectively. This is a continuation of U.S. application Ser. No. 16/421,910 filed May 24, 2019 which is a continuation of U.S. application Ser. No. 14/716,324 filed May 19, 2015. The disclosure of the aforementioned prior application is hereby incorporated by reference in its entirety.Apparatuses and methods consistent with the exemplary embodiments of the inventive concept relate to encoding and decoding Low Density Parity Check (LDPC) codes, and more particularly, to encoding and decoding LDPC codes which perform LDPC encoding and decoding based on a parity-check matrix.In a communication/broadcasting system, link performance may ...

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

A data processing device including an encoding unit configured to encode an information bit into an LDPC code with a code length of 64800 bits and an encoding rate of 2/30, based on a parity check matrix of an LDPC (Low Density Parity Check) code. The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit. The information matrix part is shown by a parity check matrix initial value table. The parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part every 360 columns. 1. A data processing device comprising:an encoding unit configured to encode an information bit into an LDPC code with a code length of 64800 bits and an encoding rate of 2/30, based on a parity check matrix of an LDPC (Low Density Parity Check) code, whereinthe LDPC code includes an information bit and a parity bit,the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit,the information matrix part is shown by a parity check matrix initial value table, andthe parity check matrix initial value table is a table showing positions of elements of 1 of the information matrix part every 360 columns and is expressed as follows30 251 2458 3467 9897 12052 12191 15073 15949 16328 16972 17704 20672 22200 22276 25349 26106 28258 29737 30518 30951 32440 43031 46622 47113 52077 52609 52750 54295 55384 56954 57155 57853 599426985 7975 8681 10628 10866 13223 14882 18449 19570 24418 24538 24556 25926 26162 26947 28181 30049 33678 35497 37980 41276 43443 44124 48684 50382 51223 53635 57661 58040 59128 59300 59614 60200 603291896 5169 7347 10895 14434 14583 15125 15279 17169 18374 20805 25203 29509 30267 30925 33774 34653 34827 35707 36868 38136 38926 42690 43464 44624 46562 50291 50321 51544 56470 56532 58199 58398 ...

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

In group-wise interleaving, interleaving of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15 is performed in a unit of a bit group of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code that has undergone group-wise interleaving is returned to an original arrangement. The technology can be applied to a case of transmitting data using the LDPC code. The data processing device and data processing method can ensure excellent communication quality in data transmission using an LDPC code. 1. (canceled)2. A data processing method comprising:an encoding step of performing LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15;a group-wise interleaving step of performing group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits; anda mapping step of mapping the LDPC code to any one of four signal points decided using a modulation method in a unit of 2 bits,wherein, in the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46, 10, 91, 133, 69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25, 77, 122, 49, 14, 125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151, 84, 167, 35, 127, 156, 55, 82, 85, 66, 114, 8, 147, 115, 113, 5, 31, 100, 106, 48, 52, 67, 107, 18, 126, 112, 50, 9, 143, 28, 160, 71, 79, 43, 98, 86, 94, 64, 3, 166, 105, 103, 118, 63, 51, 139, 172, 141, 175, 56, 74, 95, 29, 45, 129, 120, 168, 92, 150, 7, 162, 153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37, 70, 134, 40, 21, 149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12, 170, 54, 155, 99, 22, 123, 72, 177, 131, 116, 44, 158, 73, 11, 65, 164, 119, 174, 34, 83, 53, 24, 42, 60, 26, 161, 68, 178, 41, 148, 109, 87, 144, 135, 20, 62, 81, 169, 124, 6, 19 ...

DEVICES AND METHODS FOR DATA RECOVERY OF CONTROL CHANNELS IN WIRELESS COMMUNICATIONS

Aspects of the present disclosure provide an apparatus and methods for recovering data from a control channel in wireless communications. An apparatus decodes a CRC appended codeword to obtain a decoded codeword, and computes a first syndrome of the decoded codeword utilizing a parity check matrix. If the first syndrome is non-zero. The apparatus determines a location S and a length K of an error pattern in bits of the decoded codeword, an index set ε based on the values of S and K. A linear system is formed based on the parity check matrix and the error pattern in accordance with the index set ε. The apparatus determines a solution of the linear system, wherein the solution includes an estimated error pattern. A recovered codeword can be determined by removing the estimated error pattern from the decoded codeword. 1. A method of recovering a codeword in wireless communications , comprising:receiving a cyclic redundancy check (CRC) appended codeword from a wireless channel;decoding the CRC appended codeword to obtain the decoded codeword;computing a first syndrome of the decoded codeword utilizing a parity check matrix;if the first syndrome is non-zero, determining a location S and a length K of an error pattern in bits of the decoded codeword;determining an index set ε based on the values of S and K;forming a linear system based on the parity check matrix and the error pattern in accordance with the index set ε;determining a solution of the linear system, wherein the solution comprises an estimated error pattern; anddetermining a recovered codeword by removing the estimated error pattern from the decoded codeword.2. The method of claim 1 , wherein the wireless channel comprises a high-speed shared control channel (HS-SCCH).3. The method of claim 1 , wherein the forming the linear system comprises:determining a sub-matrix of the parity check matrix based on the index set;determining a sub-vector of the error pattern based on the index set; andforming the linear ...

METHOD AND APPARATUS FOR REDUCING IDLE CYCLES DURING LDPC DECODING

There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel. 1. A method of decoding codewords in conjunction with a low-density parity-check (LDPC) code , the method comprising:receiving a first codeword and a second codeword over a data channel, wherein a first code matrix is configured to be used to decode the first codeword, and wherein a second code matrix is configured to be used to decode the second codeword; and during a first time period, reading a first layer of the first code matrix, and', 'during a second time period, (i) updating the first layer of the first code matrix and (ii) reading a first layer of the second code matrix,, 'decoding the first codeword and the second codeword, wherein decoding the first codeword and the second codeword comprises'}wherein the first layer of the first code matrix is updated at least in part simultaneously with reading the first layer of the second code matrix such that the first codeword and the second codeword are decoded at least in part in parallel.2. The method of claim 1 , further comprising:receiving a third codeword, wherein a third code matrix is configured to be used to decode the third codeword; and 'during a third time period, (i) updating the first layer of the second code matrix and (ii) reading a first layer of the third code matrix.', 'decoding the second codeword and the third codeword, wherein decoding the second codeword and the third codeword comprises'}3. The method of claim 2 , further comprising:receiving a fourth codeword, wherein a fourth code ...

APPARATUS AND METHOD FOR DECODING LDPC CODE

The present disclosure relates to a pre-5-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4-Generation (4G) communication system such as Long Term Evolution (LTE). Disclosed is an apparatus for performing an iteration decoding scheme for a Low Density Parity Check (LDPC) code. The apparatus includes a receiver configured to receive an encoded signal based on a parity matrix set for a plurality of variable nodes including a first variable node with a first degree and a second variable node with a second degree. The apparatus further includes a processor configured to determine at least one variable node based on a first threshold determined according to the first degree and a second threshold determined according to the second degree among the plurality of variable nodes and to generate decoded data from the signal based on the at least one determined variable node. 1. A method of operating an apparatus for performing an iteration decoding scheme for a Low Density Parity Check (LDPC) code , the method comprising:receiving an encoded signal based on a parity matrix set for a plurality of variable nodes including a first variable node with a first degree and a second variable node with a second degree;determining at least one variable node based on a first threshold determined according to the first degree and a second threshold determined according to the second degree among the plurality of variable nodes; andgenerating decoded data from the encoded signal based on the at least one determined variable node.2. The method of claim 1 , wherein the generating of the decoded data comprises:{'sup': 'th', 'updating at least one ivariable node calculation value transmitted from first variable nodes corresponding to a first layer of the parity matrix to first check nodes included in the first layer based on the at least one determined variable node;'}{'sup': 'th', 'updating at least one icheck node calculation value ...

On-line self-checking hamming encoder, decoder and associated method

An on-line self-checking Hamming encoder is disclosed. The on-line self-checking Hamming encoder includes: a Hamming encoder, used to convert a received data vector into a Hamming codeword; and an error check unit, coupled to the Hamming encoder and used to generate a syndrome data vector of the Hamming codeword; wherein the on-line self-checking Hamming encoder generates an on-line self-checking result according to the syndrome. An on-line self-checking Hamming decoder and an associated method are also disclosed.

Distributed storage data recovery

Processing data in a distributed data storage system generates a sparse check matrix correlating data elements to data syndromes. The system receives notification of a failed node in the distributed data storage system, accesses the sparse check matrix, and determines from the sparse check matrix a correlation between a data element and a syndrome. The system processes a logical operation on the data element and the syndrome and recovers the failed node.

Low density parity check encoder having length of 16200 and code rate of 2/15, and low density parity check encoding method using the same

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b, a bit b, and a bit b are interchanged with a bit y, a bit y, and a bit y, respectively. A position of the interchange code hit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example. 130-. (canceled)31. A data processing device comprising:a reverse interchanging unit configured to perform reverse interchange processing for returning a position of an interchanged code bit obtained from data transmitted from a transmitting device to an original position; and an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15, and', 'an interchanging unit configured to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK,, 'a decoding unit configured to decode an LDPC code obtained by the reverse interchange processing, the transmitting device including'}wherein, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and the interchanging unit interchanges{'b': 0', ' ...

ENCODING METHOD, DECODING METHOD

An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula. This application is based on application No. 2011-164262 filed in Japan on Jul. 27, 2011, on application No. 2011-250402 filed in Japan on Nov. 16, 2011, and on application No. 2012-009455 filed in Japan on Jan. 19, 2012, the content of which is hereby incorporated by reference.The present invention relates to an encoding method, a decoding method, an encoder, and a decoder using low-density parity check convolutional codes (LDPC-CC) supporting a plurality of coding rates.In recent years, attention has been attracted to a low-density parity-check (LDPC) code as an error correction code that provides high error correction capability with a feasible circuit scale. Because of its high error correction capability and ease of implementation, an LDPC code has been adopted in an error correction coding scheme for IEEE802.11n high-speed wireless LAN systems, digital broadcasting systems, and so forth.An LDPC code is an error correction code defined by low-density parity check matrix H. Furthermore, the LDPC code is a block code having the same block length as the number of columns N of check matrix H (see Non-Patent Literature 1, Non-Patent Literature 2, Non-Patent Literature 3). For example, random LDPC code, QC-LDPC code (QC: Quasi-Cyclic) are proposed.However, a characteristic of many ...

METHOD AND APPARATUS OF LDPC ENCODER IN 10GBASE-T SYSTEM

A method of data encoding is disclosed. A communications device receives a set of information bits to be encoded into a codeword (c), which includes the set of information bits and a set of parity bits. A first bit value is assigned to a first parity bit in the set of parity bits. The remaining parity bits are then encoded based, at least in part, on the first bit value assigned to the first parity bit. The device may encode the remaining parity bits using the set of information bits and a parity check matrix (H) for a low density parity check (LDPC) code. The device may also generate a new parity check matrix (H) based on linearly independent rows of the parity check matrix H, and iteratively evaluate each of the remaining parity bits based on the equation: Hc=0. The device may then determine whether the encoded codeword c is a valid codeword given the LDPC code, and change one or more bit values of the codeword if c is not a valid codeword. 1. A method of data encoding comprising:receiving a set of information bits to be encoded into a codeword (c), wherein the codeword includes the set of information bits and a set of parity bits;assigning a first bit value to a first parity bit in the set of parity bits; and 'determining whether the codeword is a valid codeword for a given LDPC code; and', 'encoding remaining parity bits in the set of parity bits based, at least in part, on the first bit value assigned to the first parity bit, wherein encoding the remaining parity bits compriseschanging one or more bit values of the codeword if the codeword is not a valid codeword.2. The method of claim 1 , wherein the remaining parity bits are encoded using the set of information bits and a parity check matrix (H) for a low density parity check (LDPC) code.3. The method of claim 2 , further comprising:{'sub': '0', 'generating a new parity check matrix (H) using linearly independent rows of the parity check matrix.'}4. The method of claim 3 , wherein encoding the remaining ...

APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM

This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z≥K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices. 3. The device according to claim 2 , wherein in obtaining the encoding matrix H by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns claim 2 , the processor is configured to:replace each element of value 0 in the LDPC base graph with an all zero matrix of Z rows×Z columns; and{'sub': i,j', 'i,j', 'i,j', 'i,j', 'i,j', 'i,j', 'i,j', 'i,j, 'replace a {row index i, column index j} element of value 1 in the LDPC base graph by a circular permutation matrix I(P) of Z rows×Z columns, wherein the circular permutation matrix I(P) is obtained by circularly shifting an identity matrix of Z rows×Z columns to the right Ptimes, wherein P=mod (V, Z), Vis a shift value corresponding to a lifting factor set index of Z, Vis an integer, and V≥0.'}4. The device according to claim 1 , wherein K=22×Z.5. The device according to claim 1 , wherein the input sequence is c={c claim 1 ,c claim 1 ,c claim 1 , . . . claim 1 ,c} claim 1 , the encoded sequence is d={d claim 1 , d claim 1 , d claim 1 , . . . claim 1 , d} claim 1 , wherein c(i=0 claim 1 , 1 claim 1 , . . . K−1) are information bits claim 1 , d(j=0 claim 1 , 1 claim 1 , . . . N−1) are encoded bits claim 1 , N is a positive integer claim 1 , and N=66×Z.7. The ...

Method and Apparatus for Encoding Quasi-Cyclic Low-Density Parity Check Codes

This disclosure presents a method and the corresponding hardware apparatus for encoding low-density parity check codes whose parity check matrices are composed of circulant blocks. The encoder operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput. 1. A encoding method comprising:receiving as input a set of information bits;computing a first set of temporary parity check bits using the set of information bits and a first submatrix of a first region of a parity check matrix of a quasi-cyclic, low-density parity check (LDPC) code, the first submatrix composed of columns of a first subset of the parity check matrix;computing a second set of temporary parity check bits and a first set of redundancy bits using the first set of temporary parity check bits and a second submatrix of a second region of the parity check matrix, the second submatrix composed of columns of a second subset of the parity check matrix;computing a second set of redundancy bits using the second set of temporary parity check bits from the second region and a third submatrix of a third region of the parity check matrix, the third submatrix composed of columns of a third subset of the parity check matrix;combining the set of information bits, the first set of redundancy bits and the second set of redundancy bits to form a codeword of the quasi-cyclic LDPC code; andoutputting said codeword.2. The encoding method of claim 1 , wherein the first submatrix of the first region is organized into generalized layers claim 1 , where a number of the generalized layers is at least equal to the maximum block-column degree of the parity check matrix claim 1 , the method further comprising:recursively accumulating the first set of temporary parity check bits and storing the first set of temporary bits in a number of separate memories, the number of separate memories equal to the number of generalized layers.3. The ...

METHOD FOR LDPC DECODING, LDPC DECODER AND STORAGE DEVICE

A LDPC decoder includes: a coded information receiving circuit, configured to receive coded information and initialize bit information of a variable node; a check node processing circuit, configured to receive first reliability information, and perform check node processing and output second reliability information; a variable node processing circuit, configured to receive the second reliability information, and perform variable node processing to update the bit information of the variable node; a decoding decision circuit, configured to perform a decoding decision for the bit information of the variable node; and a scaling circuit configured to scale the first reliability information transmitted, the second reliability information and the bit information of the variable node. 1. A method for LPDC decoding , comprising:initializing,processing several loop iterations, wherein the loop iteration is consist of processing of a check node, processing of a variable node and decoding decision;scaling a first reliability information transmitted from the variable node to the check node and a second reliability information transmitted from the check node to the variable node and bit information of the variable node, in one or more loop iterations.2. The method according to claim 1 , scaling the first reliability information claim 1 , the second reliability information and the bit information in a shifting manner.3. The method according to claim 1 , further comprising:determining whether the loop iteration satisfies a predetermined execution condition; andscaling the first reliability information, the second reliability information and the bit information if the predetermined execution condition is satisfied.4. The method according to claim 3 , wherein the determining whether the loop iteration satisfies a predetermined execution condition comprises:determining whether the bit information of the variable information is less than a predetermined threshold;determining that the ...

DATA SENDING METHOD AND APPARATUS

The present invention discloses a data sending method and apparatus, which resolves a problem that performance of a high coding rate LDPC code obtained in an existing puncturing manner based on a variable node degree distribution is relatively poor. The method includes: encoding, by using an LDPC code check matrix, an information bit that needs to be sent, to obtain a codeword sequence; determining a puncturing priority of each parity bit in the codeword sequence according to row destruction and/or cycle destruction, on the LDPC code check matrix, of a variable node corresponding to each parity bit; puncturing the codeword sequence according to the puncturing priority of each parity bit in the codeword sequence; and generating a bit sequence according to the punctured codeword sequence, and sending the bit sequence. In this way, performance of an obtained high coding rate LDPC code is improved. 1. A data sending method , wherein the method comprises:encoding, by using a low density parity check (LDPC) code check matrix, an information bit that needs to be sent, to obtain a codeword sequence, wherein the codeword sequence comprises the information bit and parity bits;determining a puncturing priority of each parity bit in the codeword sequence according to at least one of row destruction and cycle destruction, on the LDPC code check matrix, of a variable node corresponding to each parity bit;puncturing the codeword sequence according to the puncturing priority of each parity bit in the codeword sequence; andgenerating a bit sequence according to the punctured codeword sequence, and sending the bit sequence, whereinthe row destruction is used to measure impact of the variable node in the LDPC code check matrix on correct decoding of variable nodes adjacent to the variable node, wherein the adjacent variable nodes are variable nodes that are adjacent to the variable node and that are of variable nodes connected to check nodes connected to the variable node; and the ...

DATA ENCODING BY EFFICIENT INVERSION OF A PARITY-CHECK SUB-MATRIX

A method for data encoding includes receiving a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H. An intermediate vector is produced by multiplying the data vector by a data sub-matrix Hof the parity-check matrix H. A parity part of the code word is derived by applying a sequence of operations to the intermediate vector based on a decomposition of a parity sub-matrix Hof the matrix H using matrices A, C, U and V, in which decomposition A is a block triangular matrix that has the same size as H, C is matrix that is smaller than H, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation H=A+UCV. 1. A method for data encoding , comprising:receiving, via an interface of a data encoder, a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H;{'o': {'@ostyle': 'single', 's'}, 'sub': 's', 'producing, by encoding circuitry of the data encoder, an intermediate vector by multiplying the data vector by a data sub-matrix Hof the parity-check matrix H; and'}{'o': {'@ostyle': 'single', 's'}, 'sub': p', 'p', 'p', 'p, 'deriving, by the encoding circuitry, a parity part of the code word by applying a sequence of operations to the intermediate vector based on a decomposition of a parity sub-matrix Hof the matrix H using matrices A, C, U and V, wherein A is a block triangular matrix that has the same size as H, C is matrix that is smaller than H, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation H=A+UCV.'}2. The method according to claim 1 , wherein applying the sequence of operations is equivalent to multiplying the vector by an inverse of the parity sub-matrix claim 1 , H.3. The method according to claim 1 , wherein applying the sequence of operations comprises solving an equation of a form A·= using a back-substitution process.4. The method according to claim ...

TRANSMISSION METHOD, RECEPTION METHOD, TRANSMISSION DEVICE AND RECEPTION DEVICE

One coding method is selected from a plurality of coding methods per data symbol group, an information sequence is encoded by using the selected coding method. The plurality of coding methods includes at least a first coding method and a second coding method. The first coding method is a coding method with a first coding rate for generating a first codeword as a first encoded sequence by using a first parity check matrix. The second coding method is a coding method with a second coding rate different from the first coding rate and obtained after puncturing processing, where a second encoded sequence is generated by performing the puncturing processing on a second codeword by using a second parity check matrix different from the first parity check matrix. A number of bits of the first encoded sequence is equal to a number of bits of the second encoded sequence. 1. A transmission method using a plurality of coding methods , comprising:selecting one coding method from the plurality of coding methods per data symbol group, encoding an information sequence by using the selected coding method to obtain an encoded sequence;modulating the encoded sequence to obtain data symbols; andtransmitting a transmission frame that includes a plurality of data symbol groups, each of the plurality of data symbol groups including the obtained data symbols,whereinthe plurality of coding methods includes at least a first coding method and a second coding method,the first coding method is a coding method with a first coding rate for generating a first codeword as a first encoded sequence by using a first parity check matrix,the second coding method is a coding method with a second coding rate that is different from the first coding rate and is a coding rate after puncturing processing, in which a second encoded sequence is generated by performing the puncturing processing on a second codeword by using a second parity check matrix that is different from the first parity check matrix, anda ...

LOW DENSITY PARITY CHECK CODE FOR TERRESTRIAL CLOUD BROADCAST

Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density Parity Check) includes receiving information and encoding the input information with an LDPC codeword using a parity check matrix, wherein the parity check matrix may have a structure obtained by combining a first parity check matrix for an LDPC code having a higher code rate than a reference value with a second parity check matrix for an LDPC code having a lower code rate than the reference value. 1. A method of decoding an LDPC (Low Density Parity Check) code by an LDPC decoder , the method comprising:receiving an LDPC codeword; anddecoding the LDPC codeword corresponding to a parity check matrix, wherein the parity check matrix includes a dual diagonal matrix and an identity matrix.2. The method of claim 1 , wherein the LDPC codeword includes a systematic part corresponding to input information claim 1 , a first parity part corresponding to the dual diagonal matrix claim 1 , and a second parity part corresponding to the identity matrix.3. The method of claim 2 , wherein the LDPC codeword is generated by performing:obtaining the first parity part using accumulation corresponding to the dual diagonal matrix based on the input information; andobtaining the second parity part using the identity matrix based on the calculated first parity part.4. The method of claim 3 , wherein the LDPC codeword is generated by further performingpuncturing the LDPC codeword corresponding to predetermined locations of at least one of the first parity part and the second parity part for a target code rate.5. The method of claim 4 , wherein the puncturing corresponds to the identity matrix in the parity check matrix.6. An LDPC (Low Density Parity Check) decoder comprising:a receiving unit configured to receive an LDPC codeword; anda decoding unit configured to decode the LDPC codeword corresponding to a parity check matrix, wherein the ...

Updating an encoded data slice

A distributed storage (DS) processing unit distributes an initial set of encoded data slices and an initial parity slice, for storage in multiple DS units. The initial parity slice is associated with an initial encoded data slice stored in a first DS unit. The DS processing unit transmits an updated encoded data slice reflecting changes to the initial encoded data slice, and obtains, from the first DS unit, delta parity information associated with a delta parity slice. The delta parity slice reflects differences between parity values calculated using the updated data slice and the initial data slice. An updated parity slice is generated by performing an exclusive OR (XOR) operation on the initial parity slice and the delta parity slice. A message transmitted to a second DS unit, which currently stores the initial parity slice, directs the second DS unit to store the updated parity slice.

Low Density Parity Check Decoder

A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order. 1. A low density parity check (LDPC) code decoder , comprising: 'a control unit that controls processing by the decoding circuitry, the control unit configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order,', 'decoding circuitry configured to process blocks of an LDPC matrix, the decoding circuitry comprising an R new update substep that provides an R new message, wherein the R new message is produced for a block of a different layer of the matrix from a layer containing a block currently being processed;', 'an R old update substep that provides an R old message, wherein the R old message is produced for a layer of the matrix currently being processed;', 'a P message substep that generates updated P messages;', 'a Q message substep that computes variable node messages (Q messages); and', 'a check node partial state processing substep that updates partial state of the layer based on Q messages computed for the block., 'wherein the control unit is configured to cause the decoding circuitry to process each block of the LDPC matrix in processing substeps comprising2. The LDPC code decoder of claim 1 , wherein the decoding circuitry is configured to generate a Q message by combining an R message with a P message.3. The LDPC code decoder of claim 1 , wherein the decoding circuitry further comprises a permuter configured to permute a P message.4. The LDPC code decoder of claim 3 , wherein the permuter is configured to permute the P message by a difference of ...

Transmission apparatus and error correction method

A transmission apparatus includes, a receiving circuit that receives a reception signal indicating a coded bit string, a decoding circuit that decodes and corrects the bit string by using a spatially-coupled low density parity check code constituted by arranging element matrixes stepwise in a diagonal direction, a parity check matrix of the spatially-coupled low density parity check code including at least one element matrix having at least one of a number of rows and a number of columns different from a number of rows and a number of columns of other element matrixes when each sparse matrix constituting the parity check matrix is regarded as an element matrix, and outputs the corrected bit string.

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The interleaving method of claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The interleaving method of claim 1 , wherein π(j) is determined based on at least one of the code length claim 1 , a modulation method for the mapping claim 1 , and the code rate. This application is a Continuation of U.S. application Ser. No. 14/716,132 filed May 19, 2015, which issued as U.S. Pat. No. 9,800,269 on Oct. 24, 2017, and which claims priority from U.S. Provisional Application No. 62/001,155 filed on May 21, 2014 and Korean Patent Application No. 10-2015-0000697 filed on Jan. 5, 2015, the disclosures of which are incorporated herein by reference in their entirety.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as high quality digital televisions, portable multimedia players and portable broadcasting equipment are increasingly used in recent years, there is an increasing demand for methods for supporting ...

METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM

Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths. 2. The method according to claim 1 , further comprising:determining, by the communication apparatus, the lifting factor Z; anddetermining, by the communication apparatus, the base matrix according to a set index of the lifting factor Z.3. The method according to claim 1 , wherein lifting factor Z is one of 5 claim 1 , 10 claim 1 , 20 claim 1 , 40 claim 1 , 80 claim 1 , 160 claim 1 , or 320.4. The method according to claim 1 , wherein the base matrix comprises m rows and n columns claim 1 , where m and n are positive integers claim 1 , and n=m+10.5. The method according to claim 4 , wherein 7≤m≤42 claim 4 , and 17≤n≤52.6. The method according to claim 1 , wherein the matrix H is determined according to a transformed matrix of the base matrix claim 1 , and wherein the transformed matrix is obtained by performing one or more of row transformation or column transformation on the base matrix.7. The method according to claim 1 , further comprising:receiving a signal, the signal comprising information that is based on low density parity check (LDPC) encoding; andperforming demodulating, deinterleaving, and rate de-matching on the signal to obtain the input sequence.9. The apparatus according to claim 8 , wherein the at least one processor is further configured to: ...

RECEIVER AND METHOD FOR PROCESSING A SIGNAL THEREOF

A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal. 1. A receiver for receiving a superposition-coded signal , the receiver comprising:a first decoder configured to decode data of the superposition-coded signal to generate information bits corresponding to a first layer signal of the superposition-coded signal based on at least a part of a parity check matrix of a low density parity check (LDPC) code;an encoder configured to encode the information bits and first parity bits to generate second parity bits based on at least the part of the parity check matrix;an interleaver configured to interleave bits of a codeword comprising the information bits, the first parity bits and the second parity bits;a mapper configured to map the interleaved bits of the codeword to constellation points; anda second decoder configured to decode the data of the superposition-coded signal to generate bits corresponding to a second layer signal of the superposition-coded signal,wherein the second layer signal is obtained by removing a signal which is based on the constellation points, from the superposition-coded signal, andwherein the parity check matrix comprises a dual diagonal matrix corresponding to the first parity ...

HIGH PERFORMANCE, FLEXIBLE, AND COMPACT LOW-DENSITY PARITY-CHECK (LDPC) CODE

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity. 1. A method for wireless communication , comprising:determining a low-density parity-check (LDPC) code base graph associated with a plurality of LDPC codes for a plurality of code rates and blocklengths, the LDPC base graph having a number of base graph columns corresponding to a maximum number of base information bits;determining a lifting size value for generating a lifted LDPC parity check matrix (PCM);generating the lifted LDPC PCM based on the base graph and the lifting size value; andgenerating an LDPC code based on the lifted LDPC PCM and an all zero vector, wherein the LDPC code was shortened by either (i) removing one or more of the base graph columns or (ii) removing one or more lifted LDPC PCM columns, and wherein the shortening was based on at least one of: a desired code rate, lifting size value, or blocklength for a transmission.2. The method of claim 1 , wherein the step of determining the lifting size value for generating the lifted LDPC PCM determines the number of base graph columns or the lifted LDPC PCM columns that may be removed to shorten the LDPC code.3. The method of claim 1 , further comprising transmitting the LDPC code over a wireless channel.4. The method of claim 1 , wherein the plurality of LDPC codes are associated with different numbers of base graph columns claim 1 , equal to or less than the number of ...

System and method for designing and using multidimensional constellations

A method for generating a codebook includes applying a unitary rotation to a baseline multidimensional constellation to produce a multidimensional mother constellation, wherein the unitary rotation is selected to optimize a distance function of the multidimensional mother constellation, and applying a set of operations to the multidimensional mother constellation to produce a set of constellation points. The method also includes storing the set of constellation points as the codebook of the plurality of codebooks.

POLAR CODING WITH DYNAMIC FROZEN BITS

The present application concerns an encoding device comprising a FC configured to generate m FC-output-bit-sequences by executing m polar encoding steps upon m FC-input-bit-sequences that comprise frozen and unfrozen bits, wherein m≥2. In an i-th polar encoding step of the m polar encoding steps at least one frozen bit is based on at least one unfrozen bit. The present application also concerns a decoding device comprising a processor configured to decode successively a polar-coded-bitstream comprising m-polar decoding steps, wherein m≥2. In an i-th polar decoding step of the m polar decoding steps at least one frozen bit is based on at least one unfrozen bit. Further, the present application concerns also correspondingly arranged encoding and decoding methods. 11. An encoding device () comprising:{'b': 11', '31', '41, 'a first encoder, FC (, , ), configured togenerate m FC-output-bit-sequences by executing m polar encoding steps upon m FC-input-bit-sequences that comprise frozen and unfrozen bits,wherein m≥2, andwherein in an i-th polar encoding step of the m polar encoding steps at least one frozen bit is based on at least one unfrozen bit.21. The encoding device () of claim 1 , wherein in the i-th polar encoding step at least one frozen bit of an i-th FC-input-bit-sequence is based on a j-th FC-input-bit-sequence claim 1 , wherein j Подробнее

COMMUNICATION METHOD AND APPARATUS USING POLAR CODES

A communication device includes: an encoder that encodes an input vector to output a codeword using a generator matrix of polar code; a memory that stores a frozen set including frozen bit indices and a non-frozen set including non-frozen bit indices; and a controller that is configured to: a) select at least one check bit index from the frozen set in descending order of row weights of the generator matrix and in descending order of index reliabilities of the input vector; b) select at least one non-frozen bit index from the non-frozen set to compute at least one check bit from at least one bit of information bits at the at least one non-frozen bit index; and c) put the at least one check bit at the at least one check bit index. 1. A communication apparatus comprising:an encoder that encodes an input vector to output a codeword using a generator matrix of polar code;a memory that stores a frozen set including frozen bit indices and a non-frozen set including non-frozen bit indices; and a) select at least one check bit index from the frozen set in the descending order of row weights of the generator matrix and in descending order of index reliabilities of the input vector;', 'b) select at least one non-frozen bit index from the non-frozen set to compute at least one check bit from at least one bit of information bits at the at least one non-frozen bit index; and', 'c) put the at least one check bit at the at least one check bit index., 'a controller that is configured to2. The communication apparatus according to claim 1 , wherein the controller is configured to select a set of check bit indices in a) bya.1) selecting at least one index with a highest row weight from the frozen set;a.2) responsive to selecting a plurality of indices with the highest row weight within the frozen set, selecting one index among the plurality of indices that has a lowest decoding error probability; anda.3) repeating the a.1) and a.2) for a predetermined number of times to obtain the set ...

METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM

Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths. 2. The method according to claim 1 , wherein N is equal to 50×Z.3. The method according to claim 1 , wherein the input sequence c is represented as c={c claim 1 , c claim 1 , c claim 1 , . . . claim 1 , c} claim 1 , and the encoded sequence d is represented as d={d claim 1 , d claim 1 , d claim 1 , . . . claim 1 , d} claim 1 , wherein in encoding the input sequence c using the matrix H claim 1 , an element c(k=0 claim 1 , 1 claim 1 , 2 claim 1 , . . . claim 1 , K−1) in the input sequence c and an element do (n=0 claim 1 , 1 claim 1 , 2 claim 1 , . . . claim 1 , N−1) in the encoded sequence d satisfy:for k=2Z to K−1,{'sub': k', 'k−2z', 'k, 'if cis not a filling bit, d=c; and'}{'sub': k', 'k', 'k−2Z, 'if cis a filling bit, c=0, and dis a filling bit.'}5. The method according to claim 4 , wherein the parity sequence w has N+2Z−K bits and the parity sequence w is represented as w={w claim 4 , w claim 4 , w claim 4 , . . . claim 4 , w}.6. The method according to claim 5 , wherein in encoding the input sequence c using the matrix H claim 5 , an element in the parity sequence w and an element in the encoded sequence d satisfy:for k=K to N+2Z−1,{'sub': k−2z', 'k−K, 'd=w.'}7. The method according to claim 1 , wherein Z is a minimum value that satisfies K×Z≥K claim 1 ...

METHODS AND APPARATUS FOR COMPACTLY DESCRIBING LIFTED LOW-DENSITY PARITY-CHECK (LDPC) CODES

Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word. 1. A method for wireless communications , comprising:determining a first set of cyclic lifting values associated with a set of lifting size values and a base parity check matrix (PCM) associated with a base graph;selecting a lifting size value from the set of lifting size values;determining a second set of cyclic lifting values by computing a modulo of each of the first set of cyclic lifting values with respect to the selected lifting size value;determining a lifted PCM for generating a lifting low density parity code (LDPC) code by applying the second set of cyclic lifting values to interconnect edges in copies of the base graph; andat least one of: encoding a set of information bits to produce one or more codewords for transmission or decoding one or more codewords to obtain a set of information bits.2. The method of claim 1 , wherein:computing the modulo of the second set of cyclic lifting values with respect to the selected lifting size value comprises, for each cyclic lifting value in the second set of cyclic lifting values, performing a modulo operation;the selected lifting size value is a divisor in the modulo operation; anda corresponding cyclic ...

RECOVERING DATA IN A DISPERSED STORAGE NETWORK

A method for execution by a dispersed storage and task (DST) client module includes issuing a read threshold number of read slice requests are issued to storage units of the set of storage units. One or more encoded slices of a selected read threshold number of encoded slices are received. When a next encoded data slice of a decode threshold number of encoded data slices is received within a response timeframe, outputting of the next encoded data slice is initiated. When the next encoded data slice is not received within the response timeframe, receiving of another decode threshold number of encoded slices of the set of encoded slices is facilitated. The other decode threshold number of encoded slices are decoded to produce recovered encoded data slices, where the recovered encoded data slices includes at least a recovered next encoded data. 1. A method for execution by a dispersed storage and task (DST) client module that includes a processor , the method comprises:determining a selected read threshold number of encoded slices of each set of encoded slices of a plurality of sets of encoded slices stored in a set of storage units, wherein each set of the a plurality of sets of encoded slices corresponds to one of a plurality of data segments;issuing a read threshold number of read slice requests to storage units of the set of storage units, where the read threshold number of read slice requests includes identities of the selected read threshold number of encoded slices;receiving one or more encoded slices of the selected read threshold number of encoded slices;for each data segment of the plurality of data segments, when a next encoded data slice of a decode threshold number of encoded data slices is received within a response timeframe, initiating outputting of the next encoded data slice;when the next encoded data slice is not received within the response timeframe, facilitating receiving of another decode threshold number of encoded slices of the set of encoded ...

UTILIZING FAST MEMORY DEVICES TO OPTIMIZE DIFFERENT FUNCTIONS

A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. A computing device receives a data access request for an encoded data slice (EDS) associated with a data object. The computing device compares a slice name of the data access request with slice names stored within RAM. When the data access request slice name compares unfavorably with those stored slice names, the computing device transmits an empty data access response that includes no EDS to the other computing device without needing to access a hard disk drive (HDD) that stores EDSs. Alternatively, the computing device transmits a data access response that includes the EDS. 1. A computing device comprising:an interface configured to interface and communicate with a dispersed storage network (DSN);memory that stores operational instructions; and transmit, to a storage unit (SU), a data access request for an encoded data slice (EDS) associated with a data object, wherein the data access request includes a data access request slice name for the EDS associated with the data object, wherein the SU includes another memory that includes random access memory (RAM) and a hard disk drive (HDD); and', 'receive, from the SU, an empty data access response that includes no EDS based on an unfavorable comparison, as performed by the SU, of the data access request slice name with a plurality of slice names stored within the RAM, wherein the plurality of slice names are respectively associated with a plurality of encoded data slices (EDSs) stored within the HDD of the SU., 'a processing module operably coupled to the interface and to the memory, wherein the processing module, when operable ...

METHOD AND APPARATUS FOR DATA DECODING IN COMMUNICATION OR BROADCASTING SYSTEM

The disclosure relates to a communication technique for converging a 5G communication system for supporting a higher data transfer rate beyond a 4G system with an IoT technology, and a system therefor. The disclosure may be applied to intelligent services (for example, smart home, smart buildings, smart cities, smart cars or connected cars, health care, digital educations, retail business, security and safety-related services, etc.) based on a 5G communication technology and an IoT-related technology. The disclosure provides an apparatus and a method for efficiently decoding a low-density parity-check (LDPC) code in a communication or broadcasting system. Further, the disclosure provides an LDPC decoding device and method for improving decoding performance without increasing the decoding complexity by applying suitable decoding scheduling according to the structural or algebraic characteristics of the LDPC code in a process of decoding the LDPC code using layered scheduling or a scheme similar thereto. Further, a method of a low density parity check (LDPC) decoding performed by a receiving device in a wireless communication system is provided, the method comprising: receiving, from a transmitting device, a signal corresponding to input bits; performing demodulation based on the signal to determine values corresponding to the input bits; identifying a number of the input bits based on the signal; identifying a base matrix and a lifting size based on the number of the input bits; identifying a parity check matrix based on the base matrix; identifying an index corresponding to the values; determining a number of layers based on the index and the lifting size; determining an order for LDPC decoding based on the number of layers and a predetermined sequence; and performing LDPC decoding to determine the input bits based on the values, the parity check matrix and the order. 112-. (canceled)13. A method for low density parity check (LDPC) decoding performed by a receiving ...

PRECOMPUTED REDUNDANCY CODE MATRICES FOR HIGH-AVAILABILITY DATA STORAGE

Techniques described and suggested herein include systems and methods for precomputing regeneration information for data archives (“archives”) that have been processed and stored using redundancy coding techniques. For example, regeneration information, such as redundancy code-related matrices (such as inverted matrices based on, e.g., a generator matrix for the selected redundancy code) corresponding to subsets of the shards, is computed for each subset and, in some embodiments, stored for use in the event that one or more shards becomes unavailable, e.g., so as to more efficiently and/or quickly regenerate a replacement shard. 1. A computer-implemented method , comprising: receiving a first request to store an archive;', 'encoding, using a redundancy code, original data of the archive into a plurality of shards;', 'determining, from the plurality of shards and the redundancy code, at least one regeneration set, the regeneration set consisting of a subset of the plurality of shards and having a number of members equal to or greater than a minimum quorum of the plurality of shards sufficient to regenerate the original data;', 'computing one or more matrices for the regeneration set, the one or more matrices capable of being used with the corresponding subset of the plurality of shards to regenerate the original data;', 'storing the computed matrices and the plurality of shards;', 'in response to a second request, retrieving a matrix of the stored matrices that corresponds to a regeneration set associated with the second request; and', 'regenerating one or more shards associated with the second request using the retrieved matrix and the corresponding regeneration set., 'under the control of one or more computer systems configured with executable instructions,'}2. The computer-implemented method of claim 1 , wherein the one or more matrices are computed by inverting at least a portion of a generator matrix used by the redundancy code claim 1 , the portion ...

ENCODING METHOD, DECODING METHOD

An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula. This application is based on application No. 2011-164262 filed in Japan on Jul. 27, 2011, on application No. 2011-250402 filed in Japan on Nov. 16, 2011, and on application No. 2012-009455 filed in Japan on Jan. 19, 2012, the content of which is hereby incorporated by reference.The present invention relates to an encoding method, a decoding method, an encoder, and a decoder using low-density parity check convolutional codes (LDPC-CC) supporting a plurality of coding rates.In recent years, attention has been attracted to a low-density parity-check (LDPC) code as an error correction code that provides high error correction capability with a feasible circuit scale. Because of its high error correction capability and ease of implementation, an LDPC code has been adopted in an error correction coding scheme for IEEE802.11n high-speed wireless LAN systems, digital broadcasting systems, and so forth.An LDPC code is an error correction code defined by low-density parity check matrix H. Furthermore, the LDPC code is a block code having the same block length as the number of columns N of check matrix H (see Non-Patent Literature 1, Non-Patent Literature 2, Non-Patent Literature 3). For example, random LDPC code, QC-LDPC code (QC: Quasi-Cyclic) are proposed.However, a characteristic of many ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

The present invention provides an apparatus of transmitting broadcast signals, the apparatus including, an encoder for encoding service data, a frame builder for building at least one signal frame by mapping the encoded service data, a modulator for modulating data in the built at lease one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signals having the modulated data. 14-. (canceled)6. The apparatus of claim 5 ,wherein the LDPC decoding decodes data being updated a parity bit of the codeword which is located in an address of j-th entry in i-th row in the table by accumulating an information bit of the codeword to the parity bit of the codeword, and updated the parity bit.8. The method of claim 7 ,wherein the LDPC decoding decodes data being updated a parity bit of the codeword which is located in an address of j-th entry in i-th row in the table by accumulating an information bit of the codeword to the parity bit of the codeword, and updated the parity bit. The present invention relates to an apparatus for transmitting broadcast signals, an apparatus for receiving broadcast signals and methods for transmitting and receiving broadcast signals.As analog broadcast signal transmission comes to an end, various technologies for transmitting/receiving digital broadcast signals are being developed. A digital broadcast signal may include a larger amount of video/audio data than an analog broadcast signal and further include various types of additional data in addition to the video/audio data.That is, a digital broadcast system can provide HD (high definition) images, multi-channel audio and various additional services. However, data transmission efficiency for transmission of large amounts of data, robustness of transmission/reception networks and network flexibility in consideration of mobile reception equipment need to be improved for digital broadcast.An object of the present invention is to ...

CODING/DECODING METHOD, APPARATUS, AND DEVICE

The present disclosure relates to coding/decoding methods, apparatus, and devices. One example method includes obtaining, by a sending device, positions of information bits, positions of fixed bits, and positions of assistant bits, allocating the information bits, the fixed bits, and the assistant bits in a to-be-coded sequence based on the obtained positions, obtaining a scrambling sequence, obtaining a scrambling sequence, scrambling a bit in a to-be-scrambled bit set based on the scrambling sequence to obtain a scrambled sequence, and performing polar coding to obtain a coded sequence for sending. 1. A coding method , wherein the method comprises:obtaining, by a sending device, positions of information bits, positions of fixed bits, and positions of assistant bits;allocating, by the sending device, the information bits, the fixed bits, and the assistant bits in a to-be-coded sequence based on the positions of the information bits, the positions of the fixed bits, and the positions of the assistant bits;obtaining, by the sending device, a scrambling sequence;scrambling, by the sending device, a bit in a to-be-scrambled bit set based on the scrambling sequence to obtain a scrambled sequence, wherein the to-be-scrambled bit set is determined based on at least one of the fixed bits or the assistant bits;performing, by the sending device, polar coding on the scrambled sequence to obtain a coded sequence; andsending, by the sending device, the coded sequence.2. The method according to claim 1 , wherein the scrambling sequence is a radio network temporary identifier (RNTI) sequence of the sending device.3. The method according to claim 1 , wherein the to-be-scrambled bit set comprises one or more assistant bits.4. The method according to claim 1 , wherein the to-be-scrambled bit set comprises any one of the following sets:a set comprising at least one of the fixed bits in descending order of reliability, starting from the highest;a set comprising at least one of the ...

LOW DENSITY PARITY CHECK CODE FOR TERRESTRIAL CLOUD BROADCAST

Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density Parity Check) includes receiving information and encoding the input information with an LDPC codeword using a parity check matrix, wherein the parity check matrix may have a structure obtained by combining a first parity check matrix for an LDPC code having a higher code rate than a reference value with a second parity check matrix for an LDPC code having a lower code rate than the reference value. 1. A method of encoding input information based on an LDPC (Low Density Parity Check) , the method comprising:receiving information; andencoding the input information to an LDPC codeword using a parity check matrix,wherein the parity check matrix includes a dual diagonal matrix, and an identity matrix.2. The method of claim 1 , wherein the encoded LDPC codeword includes a systematic part corresponding to the input information claim 1 , a first parity part corresponding to the dual diagonal matrix claim 1 , and a second parity part corresponding to the identity matrix.3. The method of claim 2 , wherein said encoding comprises:calculating the first parity part using accumulation corresponding to the dual diagonal matrix based on the input information; andcalculating the second parity part using the identity matrix based on the calculated first parity part.4. The method of claim 3 , further comprisingperforming puncturing the LDPC codeword corresponding to predetermined locations of at least one of the first parity part and the second parity part for a target code rate.5. The method of claim 4 , wherein the puncturing corresponds to the identity matrix in the parity check matrix.6. An LDPC encoder comprising:an input unit receiving information; andan encoding unit encoding the input information to an LDPC codeword using a parity check matrix,wherein the parity check matrix includes a dual diagonal matrix, and an identity ...

Transmitter, receiver, communication system, method for changing code rate, control circuit and non-transitory storage medium

A transmitter according to the disclosure includes: an encoding unit that generates a code word by performing coding with a low-density parity-check code using a check matrix, the encoding unit being capable of switching the check matrix for use in generating the code word, between a first check matrix with a first code rate and a second check matrix with a second code rate smaller than the first code rate, the first check matrix containing a plurality of cyclic permutation matrices, the encoding unit generating the second check matrix by masking the cyclic permutation matrix at a predetermined position in the first check matrix and adding a row with a column weight equal to or less than a threshold; and a transmission unit that transmits the code word.

Low density parity check decoder

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

REBUILDING SLICES IN A DISPERSED STORAGE NETWORK

A method for use in a dispersed storage network operates to select a recovery of selected ones of one or more first sets of encoded data slices in response to detecting a storage error associated with the selected ones of the one or more first sets of encoded data slices; issue requests for a second decode threshold number of encoded data slices of selected ones of one or more second sets of encoded data slices corresponding to the selected ones of the one or more first sets of encoded data slices; decode the second decode threshold number of encoded data slices to produce recovered data in response to receiving the second decode threshold number of encoded data slices; encode the recovered data utilizing first IDA parameters associated with the first IDA to produce one or more rebuilt encoded data slices corresponding to the selected ones of the one or more first sets of encoded data slices; and facilitate storage of the one or more rebuilt encoded data slices. 1. A method for execution by a processing system of a dispersed storage and task (DST) integrity processing unit that includes a processor , the method comprises:detecting a storage error associated with the selected ones of the one or more first sets of encoded data slices, wherein data is stored as the one or more first sets of encoded data slices in a plurality of dispersed storage and task execution (DSTE) units, the one or more first sets of encoded data slices encoded utilizing a first information dispersal algorithm (IDA) having a first decode threshold number, wherein the data is also stored as one or more second sets of encoded data slices in a subset of the plurality of DSTE units, the one or more second sets of encoded data slices encoded utilizing a second IDA having a second decode threshold number;issuing requests for a second decode threshold number of encoded data slices of selected ones of the one or more second sets of encoded data slices corresponding to the selected ones of the one or ...

CYCLING OUT DISPERSED STORAGE PROCESSING UNITS FROM ACCESS POOLS TO PERFORM EXPENSIVE OPERATIONS

A method includes identifying, by a dispersed storage (DS) processing unit of a plurality of DS processing units of a dispersed storage network (DSN), a DSN operation to be performed that will adversely interfere with processing of DSN access requests. The method further includes sending, by the DS processing unit, a suspension request to a process balancing module of the DSN where the suspension request is for temporarily suspending processing of DSN access requests. The method further includes determining, by the process balancing module, whether sufficient processing resources of active DS processing units of the plurality of DS processing units are available for processing DSN access requests on behalf of the DS processing unit. When determined that sufficient processing resources are available, the method further includes granting the suspension request, and allocating DSN access requests of the DS processing unit to one ore of the active DS processing units. 1. A method comprises:identifying, by a dispersed storage (DS) processing unit of a plurality of DS processing units of a dispersed storage network (DSN), a DSN operation to be performed that will adversely interfere with processing of DSN access requests;sending, by the DS processing unit, a suspension request to a process balancing module of the DSN, wherein the suspension request is for temporarily suspending processing of DSN access requests;determining, by the process balancing module, whether sufficient processing resources of active DS processing units of the plurality of DS processing units are available for processing DSN access requests on behalf of the DS processing unit; and granting, by the process balancing module, the suspension request; and', 'allocating, by the process balancing module, DSN access requests of the DS processing unit to one or more of the active DS processing units., 'when determined that sufficient processing resources are available2. The method of further comprises: ...

PROXYING READ REQUESTS WHEN PERFORMANCE OR AVAILABILITY FAILURE IS ANTICIPATED

A method includes receiving, by a read threshold number of storage units of a dispersed storage network (DSN), the read threshold number of read requests regarding the read threshold number of encoded data slices of a set of encoded data slices. The method further includes determining, by each storage unit of the read threshold number of storage units, whether the storage unit is capable of processing a respective read request. When a particular storage unit is not capable of processing the respective read request, the method further includes sending, by the particular storage unit, a proxy read request to another storage unit that is not in the read threshold number of storage units. The method further includes determining, by the other storage unit, whether the other storage unit is capable of processing the proxy read request and, when it is, processing the proxy read request. 1. A method comprises:identifying, by a computing device of a dispersed storage network (DSN), a read threshold number of storage units of a set of storage units, wherein other storage units in the set of storage units are available as proxy storage units;sending, by the computing device, a read threshold number of read requests regarding a read threshold number of encoded data slices of a set of encoded data slices to the read threshold number of storage units, wherein a data segment of a data object is dispersed storage error encoded into the set of encoded data slices, wherein the set of encoded data slices is stored in the set of storage units, and wherein the read threshold number is less than a total number of encoded data slices in the set of encoded data slices and is equal to or greater than a decode threshold number;determining, by a storage unit of the read threshold number of storage units, whether the storage unit is capable of processing a respective read request of the read threshold number of read requests; sending, by the storage unit, a proxy read request to one of the ...

APPORTIONING STORAGE UNITS AMONGST STORAGE SITES IN A DISPERSED STORAGE NETWORK

A method of apportioning storage units in a dispersed storage network (DSN) includes generating storage unit apportioning data indicating a mapping of a plurality of desired numbers of storage units to a plurality of storage sites based on site reliability data. The mapping includes a first desired number of storage units corresponding to a first one of the plurality of storage sites that is greater than a second desired number of storage units corresponding to a second one of the plurality of storage sites in response to the site reliability data indicating that a first reliability score corresponding to the first one of the plurality of storage sites is more favorable than a second reliability score corresponding to the second one of the plurality of storage sites. A plurality of storage units are allocated to the plurality of storage sites based on the storage unit apportioning data. 1. A method of apportioning storage units in a dispersed storage network (DSN) , the method comprising:generating storage unit apportioning data indicating a mapping of a plurality of desired numbers of storage units to a plurality of storage sites based on site reliability data, wherein the storage unit apportioning data represents each of the plurality of desired numbers of storage units is a numerical value, wherein when the site reliability data includes a first reliability score for the first one of the plurality of storage sites and a second reliability score for the second one of the plurality of storage sites and the first reliability score is more favorable than the second reliability score, the mapping includes a first desired number of storage units mapped to to a first one of the plurality of storage sites that is greater than a second desired number of storage units mapped to a second one of the plurality of storage sites; andallocating a plurality of storage units to the plurality of storage sites based on the storage unit apportioning data, wherein each of the ...

APPARATUS AND METHOD FOR ENCODING AND DECODING CHANNEL IN COMMUNICATION OR BROADCASTING SYSTEM

The present invention related to a 5G or pre-5G communication system to be provided to support a higher data transmission rate since 4G communication systems like LTE. The present invention relates to a method and an apparatus for encoding a channel in a communication or broadcasting system supporting parity-check matrices having various sizes are provided. The method for encoding a channel includes determining a block size of the parity-check matrix; reading a sequence for generating the parity-check matrix, and transforming the sequence by applying a previously defined operation to the sequence based on the determined block size. 1. A method performed by an apparatus for processing a low-density parity-check (LDPC) code , the method comprising:identifying a parity check matrix;encoding a code block based on the parity check matrix; andtransmitting at least a part of the encoded code block,wherein the parity check matrix includes an information part and a parity part,wherein the parity part including:a first part (B) including a plurality of first permutation matrices,a second part (D) including a second permutation matrix,a third part (T) including a plurality of identity matrices arranged diagonally within the third part and a plurality of third permutation matrices arranged below the plurality of identity matrices, anda fourth part (E) including a fourth permutation matrix,wherein the third part (T) is in a form of a square matrix, and{'sup': '−1', 'wherein a matrix according to (E)(T)(B)+D corresponds to a circulant permutation matrix which is not an identity matrix.'}2. The method of claim 1 , wherein one of the first permutation matrices is arranged in the first block of the first part (B) claim 1 , andwherein the fourth permutation matrix is arranged in the last block of the fourth part (E).3. The method of claim 2 , wherein the one of the first permutation matrix claim 2 , the second permutation matrix claim 2 , the plurality of third permutation matrices ...