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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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28-03-2024 дата публикации

SEMICONDUCTOR DEVICE INCLUDING INSULATING ELEMENT AND METHOD OF MAKING

Номер: US20240107750A1

Автор: Chin-Shan WANG, Shun-Yi LEE

Принадлежит:

A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode, and the insulating layer extends above a top-most surface of the substrate.

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Номер записи: 1

11-06-2024 дата публикации

Apparatuses including capacitors and related systems

Номер: US0012010827B2

Автор: William M. Brewer, Christopher Locke, Kyle B. Campbell

Принадлежит: Micron Technology, Inc.

An apparatus includes fin structures comprising individual levels of a conductive material having elongated portions extending in a first horizontal direction, first conductive lines extending in a second horizontal direction transverse to the first horizontal direction, and second conductive lines extending in a vertical direction transverse to each of the first horizontal direction and the second horizontal direction. At least portions of the first conductive lines are aligned vertically. The apparatus also includes horizontal capacitor structures comprising the conductive material of the fin structures and access devices proximate intersections of the first conductive lines and the second conductive lines. The access devices comprise the conductive material of the fin structures. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

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Номер записи: 2

22-02-2024 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

Номер: US20240064954A1

Автор: Mengmeng YANG

Принадлежит:

A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a substrate; and a plurality of capacitor structures arranged on a surface of the substrate. Each of the plurality of capacitor structures extends in a first direction. The first direction is parallel to the surface of the substrate. Each of the plurality of capacitor structures includes a lower electrode layer, a capacitor dielectric layer and an upper electrode layer. The lower electrode layer is provided with a U-shaped groove. The U-shaped groove is at least completely filled with the capacitor dielectric layer and the upper electrode layer. The capacitor dielectric layer is arranged between the lower electrode layer and the upper electrode layer.

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Номер записи: 3

15-02-2024 дата публикации

MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Номер: US20240057325A1

Автор: Yanhong Wang, Wei Liu, Yaqin Liu, Shiqi Huang, Liang Chen

Принадлежит:

A memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with the second side of the first peripheral circuit away from the memory array structure.

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Номер записи: 4

11-06-2024 дата публикации

Semiconductor memory device and method of fabricating the same

Номер: US0012010828B2

Автор: Seungjae Jung, Kwang-Ho Park

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory device includes a substrate and a stack including word lines and interlayer insulating patterns alternatingly stacked on the substrate. The word lines extend in a first direction. Semiconductor patterns cross the word lines and have longitudinal axes parallel to a second direction. The semiconductor patterns are spaced apart from each other in the first direction and a third direction. Bit lines extend in the third direction and are spaced apart from each other in the first direction. Each of the bit lines contacts first side surfaces of the semiconductor patterns spaced apart from each other in the third direction. Data storage elements, which are respectively provided between vertically adjacent interlayer insulating patterns and contact second side surfaces opposite to the first side surfaces, and substrate impurity layers provided in portions of the substrate at both sides of the stack, are included.

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Номер записи: 5

15-03-2023 дата публикации

STACKED MEMORY STRUCTURE WITH DUAL-CHANNEL TRANSISTOR

Номер: EP4149231A1

Автор: MA, Sean T., SHARMA, Abhishek Anil, LILAK, Aaron D., YOO, Hui Jae, CLENDENNING, Scott B., LE, Van H., TRONIC, Tristan A., ALAAN, Urusa

Принадлежит:

A memory structure includes a spacer between a first side of a wordline conductor and a bitline conductor. A semiconductor material has horizontal portions extending from the bitline conductor along a top and bottom of the wordline conductor and has a contact portion extending along a second side of the wordline conductor between and connecting the horizontal portions. A high-κ dielectric is between the semiconductor material and the wordline conductor. A capacitor has a first conductor, a second conductor, and an insulator between the first and second conductors, where the first conductor contacts the contact portion of the semiconductor material along the first side of the wordline conductor, and the second conductor connects to a ground terminal.

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Номер записи: 6

07-05-2024 дата публикации

CMOS over array of 3-D DRAM device

Номер: US0011980021B2

Автор: Sony Varghese, Fred Fishburn

Принадлежит: Applied Materials, Inc.

Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

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Номер записи: 7

14-03-2024 дата публикации

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREFOR

Номер: US20240090196A1

Автор: Liutao Zhou, Shuo Pan

Принадлежит:

A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a substrate, where a plurality of capacitor contact structures arranged at intervals are formed on the substrate; an isolation structure, where the isolation structure is disposed on the substrate and between adjacent capacitor contact structures, and a top surface of the isolation structure is not higher than a top surface of each capacitor contact structure; and an isolation groove, where the isolation groove extends from the top surface of the isolation structure to an interior of the isolation structure, and a spacing is provided between the isolation groove and the capacitor contact structure.

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Номер записи: 8

13-03-2025 дата публикации

반도체 소자

Номер: KR102780360B1

Автор: 김희중, 이명동, 한성희, 허인경

Принадлежит: 삼성전자주식회사

... 본 발명의 실시예에 따른 반도체 소자는, 활성 영역들을 포함하는 기판, 상기 기판 상에서 제1 방향으로 서로 이격되고 상기 제1 방향과 교차하는 제2 방향으로 연장되며, 상기 활성 영역들과 전기적으로 연결되는 비트 라인들, 상기 비트 라인들 상에 배치되며, 상기 활성 영역들과 전기적으로 연결되는 캐패시터들, 및 상기 캐패시터들과 상기 활성 영역들의 사이에서, 상기 캐패시터들과 상기 활성 영역들을 전기적으로 연결하는 스토리지 노드 콘택들을 포함하고, 상기 스토리지 노드 콘택들 각각은, 상기 활성 영역과 접촉되며 상기 제2 방향을 따라 제1 폭을 갖는 제1 영역 및 상기 제1 영역의 상부에 배치되며 상기 제2 방향을 따라 상기 제1 폭보다 큰 제2 폭을 갖는 제2 영역을 포함한다.

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Номер записи: 9

05-09-2023 дата публикации

3D DRAM structure with high mobility channel

Номер: US0011749315B2

Автор: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu

Принадлежит: Applied Materials, Inc.

Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

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Номер записи: 10

12-03-2024 дата публикации

Dynamic random access memory capacitor and preparation method therefor

Номер: US0011930630B2

Автор: Zhuo Chen, Ying-Chih Wang, Shih-Shin Wang

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A Dynamic Random Access Memory (DRAM) capacitor and a preparation method therefor are provided. The DRAM capacitor includes a dielectric layer, and the dielectric layer includes a high dielectric material layer, and low dielectric loss material layers provided on both side surfaces of the high dielectric material layer.

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Номер записи: 11

27-07-2023 дата публикации

VERTICAL CONTACTS FOR SEMICONDUCTOR DEVICES

Номер: US20230240067A1

Автор: Byung Yoon Kim, Sangmin Hwang, Kyuseok Lee

Принадлежит:

Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

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Номер записи: 12

14-05-2024 дата публикации

Semiconductor memory device, manufacturing method thereof and electronic device

Номер: US0011985811B2

Автор: Zhengyong Zhu, Bokmoon Kang, Guilei Wang, Chao Zhao

Принадлежит: Beijing Superstring Academy of Memory Technology

A semiconductor memory device and a manufacturing method thereof, a reading/writing method, an electronic device and a memory circuit are provided. A transistor is provided in each memory cell in the semiconductor memory device. A gate electrode and an auxiliary electrode are provided in the transistor, and the auxiliary electrode is electrically connected to a drain electrode. During a writing operation, a first voltage is applied to the gate electrode through a word line, and an electrical signal is applied to a source electrode through a bit line according to the external input data. During a reading operation, a second voltage is applied to the auxiliary electrode through the word line by using the influence of the voltage on the auxiliary electrode on the threshold voltage of the transistor (the size of the second voltage is between the threshold voltage of the transistor when storing “1” and the threshold voltage of the transistor when storing “0”), and then the data is read by detecting ...

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Номер записи: 13

02-01-2024 дата публикации

Semiconductor memory device

Номер: US0011864374B2

Автор: Jin Sun Cho

Принадлежит: SK hynix Inc.

A semiconductor memory device includes: an active layer spaced apart from a substrate wherein the active layer extends in a direction parallel to the substrate, and includes a channel; a bit line extending in a direction perpendicular to the substrate and coupled to a first end of the active layer; a capacitor coupled to a second end of the active layer; and a double word line including a pair of dual work function electrodes that extend in a direction crossing the active layer with the active layer interposed therebetween, wherein each of the dual work function electrodes includes: a high work function electrode which is adjacent to the bit line; and a low work function electrode which is adjacent to the capacitor and having a lower work function than the high work function electrode.

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Номер записи: 14

12-12-2023 дата публикации

Semiconductor device and method for fabricating the same

Номер: US0011844206B2

Автор: Seung Hwan Kim

Принадлежит: SK hynix Inc.

The present invention provides a highly integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, the semiconductor device comprises: a plurality of active layers vertically stacked over a substrate; a plurality of bit lines connected to first ends of the active layers, respectively, and extended parallel to the substrate; line-shape air gaps disposed between the bit lines; a plurality of capacitors connected to second ends of the active layers, respectively; and a word line and a back gate facing each other with each of the active layers interposed therebetween, wherein the word line and the back gate are vertically oriented from the substrate.

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Номер записи: 15

12-03-2025 дата публикации

반도체 구조의 제조 방법

Номер: KR102778795B1

Автор: 리안 팅, 리우 위헝, 푸 윤페이, 쾅 딩동

Принадлежит: 창신 메모리 테크놀로지즈 아이엔씨

... 본 발명의 실시예는 반도체 기술분야에 관한 것으로, 반도체 구조의 제조 방법을 제공하고, 베이스를 제공하는 단계; 베이스에 반도체 층을 형성하는 단계; 반도체 층에 대해 P형 도핑을 수행하고, 반도체 층을 초기 마스크 층으로 전환하는 단계; 초기 마스크 층에 대해 제1 패터닝 처리를 수행하여, 개구부를 구비한 마스크 층을 형성하는 단계; 및 마스크 층을 마스크로 사용하고, 에칭 공정을 사용하여 베이스에 대해 제2 패터닝 처리를 수행하는 단계를 포함하고, 에칭 공정이 기판에 대한 에칭 레이트는 마스크 층에 대한 에칭 레이트보다 크다. 본 발명의 실시예는 적어도 초기 마스크 층 및 베이스의 패터닝 처리의 정밀도를 향상시키는데 유리하다.

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Номер записи: 16

18-05-2023 дата публикации

3-D DRAM STRUCTURES AND METHODS OF MANUFACTURE

Номер: US20230157004A1

Автор: Chang Seok Kang, Tomohiko Kitajima, Nitin K. Ingle, Sung-Kwan Kang

Принадлежит: Applied Materials, Inc.

Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

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Номер записи: 17

14-03-2024 дата публикации

METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE

Номер: US20240090191A1

Автор: Yi TANG

Принадлежит:

Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate; forming, on a surface of the substrate, stacked structures arranged at intervals in a first direction and a first isolation layer located between adjacent stacked structures, the stacked structure including a first interlayer dielectric layer, an initial active layer, and a second interlayer dielectric layer; etching a portion of the initial active layer to form a first trench; forming a metal conductive layer in the first trench, the metal conductive layer being in contact connection with the remained initial active layer; and etching a portion of the metal conductive layer to form lower electrode structures arranged in an array in the first direction and a second direction, where the first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate.

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Номер записи: 18

06-03-2025 дата публикации

반도체 소자의 제조 방법

Номер: KR102776045B1

Автор: 김태중

Принадлежит: 주식회사 에이치피에스피

... 본 발명은 반도체 소자의 제조 방법에 관한 것이다. 일 실시예에 따른 반도체 소자의 제조 방법은, 기판 상에 복수의 절연층 및 복수의 희생층을 적층하는 단계, 상기 복수의 절연층 및 상기 복수의 희생층을 관통하는 개구를 형성하는 단계, 상기 희생층을 제거하여 트렌치를 형성하는 단계, 상기 트렌치 내부에 배리어층을 적층하는 단계, 상기 배리어층 상에 제1 전극층을 적층하는 단계, 상기 제1 전극층 상에 유전체층을 적층하는 단계, 상기 유전체층에 대한 열처리를 수행하는 단계, 상기 유전체층 상에 제2 전극층을 적층하는 단계를 포함할 수 있다.

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Номер записи: 19

29-08-2023 дата публикации

Method of manufacturing photomask set for forming patterns

Номер: US0011740553B2

Автор: Hungbae Ahn, Sangoh Park, Sunggon Jung

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of manufacturing a photomask set includes: preparing a mask layout, the mask layout including a plurality of first layout patterns apart from one another in a first region, wherein distances between center points of three first layout patterns adjacent to one another from among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns, in which a distance between two first layout patterns adjacent to each other does not have a smallest value, and splitting the mask layout pattern into at least two mask layouts; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in each of the mask layout patterns split into at least two mask layouts.

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Номер записи: 20

02-01-2024 дата публикации

Semiconductor device including insulating element and method of making

Номер: US0011864376B2

Автор: Chin-Shan Wang, Shun-Yi Lee

Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A method of making a semiconductor device includes forming a first transistor on a substrate, wherein forming the first transistor comprises forming a first source/drain electrode in the substrate. The method further includes forming a second transistor on the substrate, wherein forming the second transistor comprises forming a second source/drain electrode. The method further includes forming an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode, a top surface of the insulating layer is above a top surface of the substrate.

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Номер записи: 21

27-06-2024 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20240215216A1

Автор: Seung Hwan KIM, Kang Sik CHOI

Принадлежит:

A method for fabricating a semiconductor device includes: forming a semiconductor layer pattern over a lower structure; forming a gate dielectric layer to cover surfaces of the semiconductor layer pattern; forming a conductive layer over the gate dielectric layer to surround the semiconductor layer pattern, the conductive layer including a first edge portion and a second edge portion that are facing each other; and forming a pair of horizontal conductive lines vertically overlapping the semiconductor pattern by horizontally recessing the first edge portion and the second edge portion of the conductive layer.

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Номер записи: 22

22-08-2023 дата публикации

DRAM with a hydrogen-supply layer and a high-capacitance embedded capacitor with a cylindrical storage node

Номер: US0011737256B2

Автор: Jun-Won Lee, Hyuk-Woo Kwon, Ik-Soo Kim, Byoung-Deog Choi

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.

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Номер записи: 23

24-10-2023 дата публикации

Methods for forming openings in conductive layers and using the same

Номер: US0011798837B2

Автор: Tsuyoshi Tomoyama, Keisuke Otsuka

Принадлежит: Micron Technology, Inc.

Methods for forming openings in conductive layers and using the same are described. An example method includes: forming a conductive layer; forming a first hard mask on the conductive layer; forming a second hard mask on the first hard mask; providing an opening through the first and second masks; and removing a surface of the conductive layer under the opening. The first hard mask may have hardness greater than hardness of the second hard mask.

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Номер записи: 24

22-02-2024 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME, AND MEMORY

Номер: US20240064970A1

Автор: YU-CHENG LIAO, Muyu Chen

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

The disclosure relates to the field of semiconductor technologies, and to a semiconductor structure and a method for forming the same, and a memory. The semiconductor structure of the disclosure includes a substrate, a word line structure, a conductive contact structure and a buffer layer. The substrate includes an active area; the active area includes a channel area, and a source area and a drain area that are respectively distributed on two sides of the channel area; the channel area has a word line groove; the word line structure is located in the word line groove; the conductive contact structure is connected to a top of the drain area; and the buffer layer is located between the conductive contact structure and the word line structure.

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Номер записи: 25

28-12-2023 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR

Номер: US20230422477A1

Автор: Meng HUANG

Принадлежит:

A semiconductor structure includes: a bit line, a transistor structure, and a capacitor structure arranged in sequence in a first direction, the capacitor structure extending in the first direction, both the transistor structure and the capacitor structure including a portion of a semiconductor layer, and the semiconductor layer extending in the first direction; and a bit line contact layer on an end surface of the semiconductor layer that is away from the capacitor structure, the bit line contact layer and the semiconductor layer including the same semiconductor material, and the bit line covering an end surface of the bit line contact layer that is away from the semiconductor layer and covering at least a portion of a sidewall of the bit line contact layer that extends in the first direction.

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Номер записи: 26

11-06-2024 дата публикации

Memory cell and semiconductor memory device with the same

Номер: US0012010829B2

Автор: Seung Hwan Kim

Принадлежит: SK hynix Inc.

A semiconductor memory device and method for making the same. The semiconductor device includes a transistor laterally extending in a direction parallel to a substrate and including an active layer over the substrate, the active layer having a first end and a second end; bit line contact nodes formed on an upper surface and a lower surface of the first end of the active layer, respectively; a bit line side-ohmic contact vertically extending and connecting to the first end of the active layer and the bit line contact nodes; a bit line extending in a vertical direction to the substrate and connected to the bit line side-ohmic contact; and a capacitor connected to the second end of the active layer.

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Номер записи: 27

07-03-2024 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Номер: US20240081041A1

Автор: Daohuan FENG, Xiaojie Li

Принадлежит:

A semiconductor structure includes a substrate and a stack structure located on the substrate. The stack structure includes a plurality of memory units arranged at intervals in a first direction. Each memory unit includes a transistor structure. The transistor structure includes an active structure and a gate layer. At least part of the active structure is distributed around a periphery of part of the gate layer, and the projection of the active structure on a top surface of the substrate is in the shape of a U which opens toward a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects with the second direction. A method for forming the semiconductor structure is also provided.

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Номер записи: 28

13-03-2025 дата публикации

반도체 장치 제조 방법

Номер: KR102780784B1

Автор: 장석화, 김강욱, 노현석, 박용신, 선상규, 이선영, 이소향, 이홍준, 정호선, 진정민, 최정희, 최진서, 홍세라

Принадлежит: 삼성전자주식회사

... 반도체 장치 제조 방법을 제공한다. 이 방법은 복수의 트랜지스터들을 포함하는 하부 구조물을 형성하고; 상기 하부 구조물 상에 도전성 층을 형성하고; 상기 도전성 층 상에 제1 예비 패드 마스크 패턴들 및 배선 마스크 패턴들을 형성하고; 상기 배선 마스크 패턴들을 보호하면서, 상기 제1 예비 패드 마스크 패턴들을 패터닝하여 패드 마스크 패턴들을 형성하고; 패드 패턴들 및 배선 패턴들을 형성하기 위해서 상기 패드 마스크 패턴들 및 상기 배선 마스크 패턴들을 식각 마스크로 이용하는 식각 공정을 이용하여 상기 도전성 층을 식각하는 것을 포함한다.

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Номер записи: 29

23-01-2024 дата публикации

Electronic devices comprising memory cells comprising channel materials

Номер: US0011882685B2

Автор: Gurtej S. Sandhu

Принадлежит: Micron Technology, Inc.

A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

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Номер записи: 30

06-02-2024 дата публикации

Method for manufacturing semiconductor structure

Номер: US0011894236B2

Автор: Qiang Wan, Jun Xia, Kangshu Zhan, Tao Liu, Penghui Xu, Sen Li, Yanghao Liu

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.

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Номер записи: 31

30-04-2024 дата публикации

Replacement channel process for three-dimensional dynamic random access memory

Номер: US0011974423B2

Автор: Fredrick Fishburn, Arvind Kumar, Sony Varghese

Принадлежит: Applied Materials, Inc.

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

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Номер записи: 32

04-06-2024 дата публикации

Semiconductor equipment regulation method and semiconductor device fabrication method

Номер: US0012002689B2

Автор: Xifei Bao, Runsheng Shen

Принадлежит: Changxin Memory Technologies, Inc., CHANGXIN MEMORY TECHNOLOGIES, INC.

The present application relates to a semiconductor equipment regulation method, including: providing a simulated wafer; placing the simulated wafer in an etching chamber, and conditioning a temperature in the chamber by using a temperature control device while the simulated wafer is etched by using an etching gas; during the etching process, forming a polymer layer on a surface of each etch hole; acquiring a thickness distribution map of the polymer layer in the entire simulated wafer; comparing the acquired thickness distribution map with a target thickness distribution map; and adjusting a temperature control effect through using the temperature control device on each region of the simulated wafer according to a result of the comparison, so as to adjust thickness uniformity of the polymer layer in the entire wafer.

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Номер записи: 33

07-03-2025 дата публикации

반도체 메모리 소자 및 그 제조 방법

Номер: KR102775697B1

Автор: 최민수, 이명동, 장현우, 김근남, 신수호, 황유상

Принадлежит: 삼성전자주식회사

... 본 발명은 반도체 메모리 소자 및 그 제조 방법에 관한 것으로서, 보다 상세하게는, 제1 활성 패턴을 갖는 기판, 상기 제1 활성 패턴은 제1 소스/드레인 영역 및 제2 소스/드레인 영역을 포함하며; 상기 제1 활성 패턴을 가로지르며 제1 방향으로 연장되는 게이트 전극, 상기 게이트 전극은 상기 제1 및 제2 소스/드레인 영역들 사이를 가로지고; 상기 제1 활성 패턴을 가로지르며 제2 방향으로 연장되는 비트 라인, 상기 비트 라인은 상기 제1 소스/드레인 영역과 전기적으로 연결되고; 상기 비트 라인의 일 측벽 상의 스페이서; 상기 제2 소스/드레인 영역에 접속하는 제1 콘택, 상기 제1 콘택은 상기 스페이서를 사이에 두고 상기 비트 라인과 이격되며; 상기 제1 콘택 상의 랜딩 패드; 및 상기 랜딩 패드 상의 정보 저장 요소를 포함한다. 상기 제2 소스/드레인 영역은, 상면, 상부 측벽, 및 상기 상면으로부터 상기 상부 측벽까지 연장되는 리세스된 상면을 갖고, 상기 제1 콘택은 상기 리세스된 상면 및 상기 상부 측벽과 접촉한다.

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Номер записи: 34

07-03-2025 дата публикации

반도체 장치 및 그 제조 방법

Номер: KR20250032527A

Автор: 김승환, 최강식

Принадлежит:

... 본 기술은 고집적화된 메모리 셀들을 구비한 반도체 장치 및 그 제조 방법에 관한 것으로, 본 기술에 따른 반도체 장치는, 제1 방향을 따라 수직하게 연장된 커먼 도전 라인; 상기 커먼 도전 라인을 공유하면서 상기 제1 방향을 따라 수직하게 적층된 복수의 수평층들을 포함하는 메모리 셀 어레이; 및 상기 커먼 도전 라인에 접속된 셀렉터 구조물을 포함하고, 상기 셀렉터 구조물은 상기 제1 방향을 따라 수직하게 적층된 복수의 셀렉터 레벨 트랜지스터; 및 상기 셀렉터 레벨 트랜지스터들에 공통으로 접속된 셀렉터를 포함할 수 있다.

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Номер записи: 35

11-07-2023 дата публикации

Semiconductor memory device

Номер: US0011700723B2

Автор: Seungjae Jung, Kwangho Park, Jaehoon Kim

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor memory device, including a first semiconductor pattern, and a second semiconductor pattern separated from the first semiconductor pattern in a vertical direction; a first bit line electrically connected to a first source/drain region of the first semiconductor pattern, and a second bit line electrically connected to a first source/drain region of the second semiconductor pattern; a word line structure in contact with the first semiconductor pattern and the second semiconductor pattern; and a first data storage element electrically connected to a second source/drain region of the first semiconductor pattern, and a second data storage element electrically connected to a second source/drain region of the second semiconductor pattern, wherein the first semiconductor pattern and the second semiconductor pattern are monocrystalline, and wherein a crystal orientation of the first semiconductor pattern is different from a crystal orientation of the second semiconductor pattern.

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Номер записи: 36

27-06-2023 дата публикации

Semiconductor devices having landing pad patterns and methods of manufacturing the same

Номер: US0011688687B2

Автор: Sangoh Park, Dongjun Lee, Keunnam Kim, Seunghune Yang

Принадлежит: Samsung Electronics Co., Ltd.

A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

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Номер записи: 37

09-04-2024 дата публикации

Memory and manufacturing method thereof, and electronic device

Номер: US0011956943B2

Автор: Zhengyong Zhu, Bokmoon Kang, Guilei Wang, Chao Zhao

Принадлежит: Beijing Superstring Academy of Memory Technology

A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.

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Номер записи: 38

14-05-2024 дата публикации

반도체 장치의 제조 방법 및 반도체 장치

Номер: KR20240066096A

Автор: 이케지리, 마사히로, 데라바야시, 마사키, 마에카와, 고지, 아키야마, 고지

Принадлежит:

... 산화물계 고유전율막을 사용한 커패시터의 저 CET화를 실현할 수 있는 반도체 장치의 제조 방법 및 반도체 장치를 제공한다. 반도체 장치의 제조 방법은, 기판 상에 Ti 함유막으로 이루어지는 하부 전극을 형성하는 공정과, 하부 전극 상에 니오븀 산화막을 형성하는 공정과, 니오븀 산화막 상에 산화물계 고유전율막을 형성하는 공정과, 산화물계 고유전율막 상에 상부 전극을 형성하는 공정과, 어닐을 행하는 공정을 갖고, 산화물계 고유전율막을 형성하는 공정과, 상부 전극을 형성하는 공정과, 어닐을 행하는 공정을 거침으로써, 니오븀 산화막을, Nb2O5보다 산화수가 작은 니오븀 산화물을 주체로 하는 저산화수 니오븀 산화막으로 개질한다.

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Номер записи: 39

18-04-2024 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20240130101A1

Автор: Takanori MATSUZAKI, Toshihiko SAITO, Shunpei YAMAZAKI

Принадлежит:

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor, a capacitor, and a first insulating layer. The first insulating layer is provided over a first conductive layer and a second conductive layer and includes a first opening reaching the first conductive layer and a second opening reaching the second conductive layer. The transistor is a vertical transistor in which a channel formation region is provided along the side wall of the first opening. The capacitor is a vertical capacitor in which a pair of electrodes and a dielectric are provided along the side surface of the second opening.

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Номер записи: 40

21-12-2023 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20230413516A1

Автор: Teruhisa SONOHARA, Shunichi SENO, Hiroki TOKUHIRA, Fumitaka ARAI

Принадлежит: Kioxia Corporation

A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

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Номер записи: 41

27-06-2024 дата публикации

VERTICAL HETEROSTRUCTURE SEMICONDUCTOR MEMORY CELL AND METHODS FOR MAKING THE SAME

Номер: US20240215217A1

Автор: Gerben DOORNBOS, Marcus Johannes Henricus VAN DAL

Принадлежит:

A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.

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Номер записи: 42

20-12-2023 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

Номер: EP4294145A1

Автор: SHAO, Guangsu, XIAO, Deyuan

Принадлежит:

Disclosed belong to the technical field of semiconductor manufacturing, and in particular, relate to a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes a first capacitive structure located on a substrate and first support columns. A plurality of first support columns are disposed on the substrate in parallel and spaced apart from each other, and are located in a same plane parallel to the substrate. The first capacitive structure includes a first lower electrode layer, a first dielectric layer and a first upper electrode layer. The semiconductor structure further includes a plurality of first segmentation trenches. The first segmentation trenches divide the first capacitive structure into a plurality of capacitors. A first insulation layer is disposed between the corresponding first lower electrode layers of the adjacent capacitors. The corresponding first upper electrode layers of the adjacent capacitors are electrically ...

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Номер записи: 43

05-03-2025 дата публикации

반도체 소자

Номер: KR20250030709A

Автор: 유종명, 김지원

Принадлежит:

... 반도체 소자는, 기판 상에, 상부로부터 하부까지 순차적으로 제1 부위, 제2 부위 및 제3 부위를 포함하고, 상기 제2 부위는 측방으로 돌출되는 첨점 부위를 포함하고, 내부가 채워진 기둥 형상을 가지고, 금속 물질을 포함하는 제1 전극이 구비된다. 상기 제1 전극의 표면을 덮고, 상기 제2 부위 상에서 상대적으로 얇은 두께를 가지는 절연막이 구비된다. 상기 절연막 상에 구비되고, 금속 물질을 포함하는 제2 전극이 구비된다. 상기 반도체 소자는 높은 신뢰성을 가질 수 있다.

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Номер записи: 44

15-08-2023 дата публикации

Methods of forming an apparatus including laminate spacer structures

Номер: US0011729964B2

Автор: Silvia Borsari, Stian E. Wood, Haoyu Li, Yiping Wang

Принадлежит: Micron Technology, Inc.

An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.

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Номер записи: 45

18-01-2024 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20240023318A1

Автор: Junhyeok Ahn

Принадлежит:

A semiconductor device includes an active region between portions of a device isolation layer on a substrate, a self-aligned pad layer on a first region of the active region, a bit line that is electrically connected to a second region of the active region, and a contact structure on a side surface of the bit line and electrically connected to the self-aligned pad layer. The self-aligned pad layer includes a pad protrusion that extends along an upper portion of a side surface of the first region of the active region, and a side of the self-aligned pad layer is in contact with the device isolation layer.

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Номер записи: 46

21-02-2023 дата публикации

반도체 장치 및 그 제조 방법

Номер: KR20230024569A

Автор: 김준식

Принадлежит:

... 본 기술은 고집적화된 메모리셀 및 그를 구비한 반도체 장치를 제공하며, 본 기술에 따른 반도체 장치는, 기판으로부터 이격되어 상기 기판의 표면에 평행하는 방향을 따라 연장되는 채널을 포함하는 활성층; 상기 활성층 상에 형성된 게이트 절연층; 및 상기 게이트 절연층 상에서 상기 활성층에 대향하도록 수평하게 배향된 수평하게 배향되며, 저일함수전극 및 상기 저일함수 전극에 평행하는 고일함수 전극을 포함하는 워드라인; 및 상기 고일함수 전극과 저일함수 전극 사이에 위치하는 절연성 캡핑층을 포함할 수 있다.

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Номер записи: 47

24-04-2023 дата публикации

반도체 장치 및 그 제작 방법

Номер: KR20230054388A

Автор: 야마자키 슌페이, 테즈카 사치아키, 바바 하루유키, 에기 유지, 진보 야스히로, 사쿠라다 유지로, 아오키 타케시

Принадлежит:

... 특성의 편차가 적은 반도체 장치를 제공한다. 누설 전류가 저감된 용량 소자를 가지는 반도체 장치의 제작 방법으로서, 제 1 도전체를 형성하고, 제 1 도전체 위에 제 2 절연체를 형성하고, 제 2 절연체 위에 제 3 절연체를 형성하고, 제 3 절연체 위에 제 2 도전체를 형성하고, 제 2 도전체 및 제 3 절연체 위에 제 4 절연체를 성막하고, 가열 처리를 수행함으로써 제 3 절연체에 포함되는 수소가 제 2 절연체로 확산 및 흡수되고, 제 1 도전체는 용량 소자의 한쪽 전극이고, 제 2 도전체는 용량 소자의 다른 쪽 전극이고, 제 2 절연체 및 제 3 절연체는 용량 소자의 유전체이다.

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Номер записи: 48

03-02-2023 дата публикации

배선 형성 방법 및 이를 이용한 반도체 장치의 제조 방법

Номер: KR20230016854A

Автор: 이현철, 김기정, 김종천, 신동휘, 홍현실

Принадлежит:

... 배선 형성 방법에서, 기판 상에 저유전 물질을 포함하는 층간 절연막을 형성할 수 있다. 상기 층간 절연막 상에 제1 식각 마스크를 형성할 수 있다. 상기 제1 식각 마스크를 사용하는 제1 식각 공정을 통해 상기 층간 절연막을 관통하는 제1 개구를 형성할 수 있다. 상기 제1 식각 마스크를 제거할 수 있다. 상기 제1 개구의 저면 및 측벽에 보호 패턴을 형성할 수 있다. 상기 보호 패턴 및 상기 층간 절연막 상에 제2 식각 마스크를 형성할 수 있다. 상기 제2 식각 마스크를 사용하는 제2 식각 공정을 통해 상기 층간 절연막을 관통하는 제2 개구를 형성할 수 있다. 상기 제2 식각 마스크를 제거할 수 있다. 상기 보호 패턴을 제거할 수 있다. 상기 각 제1 및 제2 개구들 내에 배선을 형성할 수 있다.

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Номер записи: 49

06-04-2023 дата публикации

반도체 장치 제조 방법

Номер: KR20230047060A

Автор: 김동우, 김준관, 배온유, 신용진, 우경민

Принадлежит:

... 배선 패턴들이 열화되는 것을 방지하여, GIDL 특성이 개선된 반도체 장치 제조 방법이 제공된다. 상기 반도체 장치 제조 방법은 셀 영역 및 셀 영역을 둘러싸는 페리 영역을 포함하는 기판을 제공하고, 기판 상에, 기판과 연결된 컨택 플러그를 형성하고, 기판의 셀 영역에, 컨택 플러그와 연결되고, 수직 방향으로 연장된 하부 전극을 형성하고, 하부 전극 상에 커패시터 유전막을 형성하고, 커패시터 유전막 상에, 커패시터 유전막의 적어도 일부를 감싸는 상부 전극을 형성하고, 상부 전극 측벽 및 상부 전극 상면을 덮는 제1 층간 절연막을 중수소 분위기에서 형성하고, 기판의 페리 영역에, 제1 층간 절연막을 관통하는 컨택을 형성하고, 제1 층간 절연막 상에 제2 층간 절연막을 형성하고, 제2 층간 절연막 내에 컨택과 연결된 제1 배선 패턴을 형성하는 것을 포함한다.

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Номер записи: 50

03-02-2023 дата публикации

반도체 장치 및 그 제조 방법

Номер: KR20230016875A

Автор: 김태원, 김형준, 탁용석, 김유림, 이공수

Принадлежит:

... 성능 및 신뢰성이 향상된 반도체 장치 및 그 제조 방법이 제공된다. 반도체 장치는, 기판 상에, 제1 방향으로 연장되는 도전 라인, 도전 라인 상에, 제1 금속 원소를 포함하는 제1 결정성 산화물 반도체 물질을 포함하는 제1 산화물 반도체막, 도전 라인 상에, 제1 산화물 반도체막과 접촉하며, 도전 라인과 접속되는 제2 산화물 반도체막, 제2 산화물 반도체막의 측면 상에, 제1 방향과 교차하는 제2 방향으로 연장되는 게이트 전극, 및 제2 산화물 반도체막 및 게이트 전극 상에, 제2 산화물 반도체막과 접속되는 커패시터 구조체를 포함하되, 제2 산화물 반도체막은, 제1 금속 원소 및 제1 금속 원소와 다른 제2 및 제3 금속 원소를 포함하는 제2 결정성 산화물 반도체 물질을 포함한다.

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Номер записи: 51

14-09-2023 дата публикации

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20230290727A1

Автор: Sangoh Park, Dongjun Lee, Keunnam Kim, Seunghune Yang

Принадлежит:

A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

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Номер записи: 52

26-12-2023 дата публикации

Semiconductor structure and preparation method thereof

Номер: US0011855131B2

Автор: Xifei Bao, Yaoyao Chu

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A preparation method of a semiconductor structure includes: providing a substrate, and forming a groove on the substrate by etching; forming a first dielectric layer on a side wall of the groove; forming a first electrode on the bottom of the groove and on an inner surface of the first dielectric layer; forming a second dielectric layer on a surface of the first electrode; and forming a second electrode on a surface of the second dielectric layer.

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Номер записи: 53

22-02-2024 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE HAVING CHANNEL LAYER WITH REDUCED APERTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20240064961A1

Автор: YU XIAO

Принадлежит:

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a word line, a channel layer, and a bit line. The word line is disposed on the substrate. The channel layer is surrounded by the word line. The bit line is disposed on the channel layer. The channel layer has a first portion in the substrate and a second portion over the substrate. A first width of the first portion is greater than a second width of the second portion along a first direction.

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Номер записи: 54

18-06-2024 дата публикации

Semiconductor device and method for forming the same

Номер: US0012016174B2

Автор: Min-Teng Chen

Принадлежит: Fujian Jinhua Integrated Circuit Co., Ltd.

A semiconductor device includes a substrate, a plurality of bit lines, a plurality of contacts, a plurality of storage node pads, a capacitor structure and a plurality of first interface layers. The bit lines and the contacts are disposed on the substrate, and the contacts are alternately and separately disposed with the bit lines. The storage node pads are disposed on the contacts and the bit lines, and are respectively aligned with the contacts. The capacitor structure is disposed on the storage node pads. The first interface layers are disposed between the storage node pads and the capacitor structure, and the first interface layers include a metal nitride material. The first interface layers may improve the granular size of the storage node pads, and reduce the surface roughness thereof, and further improve the electrical connection between the storage nodes and transistor components below.

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Номер записи: 55

18-06-2024 дата публикации

Method for preparing semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing lining layer

Номер: US0012014986B2

Автор: Chin-Te Kuo

Принадлежит: NANYA TECHNOLOGY CORPORATION

The present disclosure provides a method for preparing a semiconductor device structure. The method includes preparing a substrate having a pattern-dense region and a pattern-loose region; forming a first conductive layer disposed over the substrate; forming a first dielectric layer disposed over the first conductive layer; etching the first dielectric layer to form a first opening and a second opening exposing the first conductive layer; forming a first lining layer and a first conductive plug in the first opening and a second conductive plug in the second opening, wherein the first lining layer comprises manganese (Mn), the first conductive plug comprises copper (Cu), and the first conductive plug and the second plug are surrounded by the first lining layer; and forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer, wherein the second conductive layer comprises copper (Cu).

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Номер записи: 56

18-03-2025 дата публикации

Semiconductor device and method of fabricating the same

Номер: KR102782256B1

Автор: 정규호, 박영림, 안창무, 송홍선, 신유경

Принадлежит: 삼성전자주식회사

Disclosed are semiconductor devices and fabrication methods for the same. The semiconductor devices may include a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked on a semiconductor substrate. The bottom electrode includes a first doping region in contact with the dielectric layer, a main region spaced apart from the dielectric layer by the first doping region intervening therebetween, and a second doping region between the first doping region and the main region. Each of the first and second doping regions includes oxygen and a doping metal. In some embodiments, the second doping region may include nitrogen. The main region may be devoid of the doping metal. An amount of oxygen in the second doping region is less than an amount of oxygen in the first doping region.

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Номер записи: 57

10-02-2023 дата публикации

3D DRAM을 위한 선택적 실리사이드 증착

Номер: KR20230020365A

Автор: 브릴, 니콜라스, 강, 창 석

Принадлежит:

... 저-저항 콘택을 유발하는 금속 실리사이드를 갖는 메모리 디바이스들이 설명된다. 메모리 디바이스를 형성하는 방법들이 설명된다. 방법들은 메모리 스택 상의 반도체 재료 층 상에 금속 실리사이드 층을 형성하는 단계를 포함하며, 반도체 재료 층은 커패시터 측 및 비트 라인 측을 갖는다. 그런 다음, 금속 실리사이드 층의 커패시터 측에 커패시터가 형성되고, 금속 실리사이드 층의 비트 라인 측에 비트 라인이 형성된다.

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Номер записи: 58

09-05-2024 дата публикации

실리사이드 층들을 가진 컨택 플러그들을 포함하는 반도체 소자들 및 그 제조 방법들

Номер: KR20240062326A

Автор: 윤영광

Принадлежит:

... 기판 상의 층간 절연층; 및 상기 층간 절연층을 수직으로 관통하여 상기 기판의 제1 활성 영역과 연결된 제1 컨택 플러그 구조 및 상기 기판의 제2 활성 영역과 연결된 제2 컨택 플러그 구조를 포함하는 반도체 소자가 설명된다. 상기 제1 컨택 플러그 구조는 제1 금속 실리사이드 층; 상기 제1 금속 실리사이드 층 상의 제1 컨택 배리어 층; 및 상기 제1 컨택 배리어 층 상의 제1 컨택 플러그를 포함한다. 상기 제2 금속 플러그 구조는 제2 금속 실리사이드 층; 상기 제2 컨택 실리사이드 층 상의 제2 컨택 배리어 층; 및 상기 제2 컨택 배리어 층 상의 제2 컨택 플러그를 포함한다. 상기 제1 금속 실리사이드 층과 상기 제2 금속 실리사이드 층은 서로 다른 금속 실리사이드들을 포함한다. 상기 제1 금속 실리사이드 층은 상기 제2 금속 실리사이드 층보다 넓은 수평 폭 및 큰 수직 높이를 갖는다.

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Номер записи: 59

07-03-2025 дата публикации

반도체 장치 및 그 제조 방법

Номер: KR20250031384A

Автор: 성민철

Принадлежит:

... 본 기술은 고집적화된 메모리 셀들을 구비한 반도체 장치 및 그 제조 방법에 관한 것으로, 본 기술에 따른 반도체 장치 제조 방법은 하부 구조물 상부에 더미 채널 패턴 및 복수의 몰드층을 포함하는 셀 몰드를 형성하는 단계; 상기 더미 채널 패턴을 가로지르는 수평 도전 라인을 형성하는 단계; 상기 더미 채널 패턴을 트리밍하여 더미 채널층을 형성하는 단계; 상기 더미 채널층의 일측에 접속되는 데이터 저장 요소를 형성하는 단계; 상기 더미 채널층을 채널층으로 치환하는 단계; 및 상기 채널층의 타측에 접속되는 수직 도전 라인을 형성하는 단계를 포함할 수 있다.

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Номер записи: 60

10-03-2025 дата публикации

배선 구조물, 그 형성 방법, 및 상기 배선 구조물을 포함하는 반도체 장치

Номер: KR102778068B1

Автор: 임현석, 조민혁, 변경은, 신현진, 야마모토 카오루, 윤정수, 이소영, 정근오

Принадлежит: 삼성전자주식회사

... 배선 구조물은, 기판 상에 형성되며, 불순물이 도핑된 폴리실리콘을 포함하는 제1 도전 패턴, 상기 제1 도전 패턴 상에 형성되며 금속 실리사이드를 포함하는 오믹 콘택 패턴, 상기 오믹 콘택 패턴 상에 형성되며 금속 실리콘 질화물을 포함하는 산화 방지 패턴, 상기 산화 방지 패턴 상에 형성되며 그래핀을 포함하는 확산 배리어, 및 상기 확산 배리어 상에 형성되며 금속을 포함하는 제2 도전 패턴을 구비할 수 있다.

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Номер записи: 61

18-01-2024 дата публикации

METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE

Номер: US20240021518A1

Автор: Jingwen LU

Принадлежит:

Embodiments are a method for fabricating a semiconductor structure. The method includes: providing a substrate; etching the substrate to form bit line grooves extending along a first direction; sequentially forming a first isolation layer, a bit line metal line layer, a bit line conductive connection layer and a first insulating layer to obtain a bit line structure; etching to form a substrate of the bit line structure, and to obtain a plurality of active area structures arranged at intervals and a first groove, the bit line structure intersecting with the active area structures; filling the first groove with a second isolation layer to obtain a first structure; etching the first structure to form word line grooves extending along a direction perpendicular to the first direction; and sequentially forming a third isolation layer, a word line conductive connection layer and a second insulating layer in the word line groove.

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Номер записи: 62

09-05-2024 дата публикации

반도체장치 및 그 제조 방법

Номер: KR102664275B1

Автор: 김승묵

Принадлежит: 에스케이하이닉스 주식회사

... 본 기술은 신뢰성이 개선된 캐패시터를 구비하는 반도체장치 및 그 제조 방법을 제공하며, 본 기술에 따른 캐패시터는, 복수의 하위 하부전극; 상기 하위 하부전극들의 일부를 지지하며, 복수의 하위 서포터오프닝을 포함하는 하위 서포터; 상기 하위 하부전극들 상에 각각 형성된 상위 하부전극들; 및 상기 상위 하부전극들의 일부를 지지하며, 복수의 상위 서포터오프닝을 포함하는 상위 서포터를 포함하고, 상기 하위 서포터오프닝들과 상위 서포터오프닝들은 수직하게 비-오버랩될 수 있다.

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Номер записи: 63

22-02-2024 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE HAVING CHANNEL LAYER WITH REDUCED APERTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20240064963A1

Автор: YU XIAO

Принадлежит:

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a word line, a channel layer, and a bit line. The word line is disposed on the substrate. The channel layer is surrounded by the word line. The bit line is disposed on the channel layer. The channel layer has a first portion in the substrate and a second portion over the substrate. A first width of the first portion is greater than a second width of the second portion along a first direction.

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Номер записи: 64

16-02-2023 дата публикации

반도체 장치 및 그 제조 방법

Номер: KR20230022752A

Автор: 정성진, 박석한, 선우예지, 유보원, 손영웅

Принадлежит:

... 반도체 장치는, 셀 영역과 상기 셀 영역의 적어도 일 측에 배치되는 주변 회로 영역을 포함하는 기판; 상기 기판의 상기 셀 영역 상에 배치되는 복수의 셀 트랜지스터; 상기 기판의 상기 주변 회로 영역에 배치되는 주변 회로; 상기 기판의 상기 셀 영역과 상기 주변 회로 영역 상에 배치되며, 상기 셀 영역 상에 배치되는 제1 부분과 상기 주변 회로 영역 상에 배치되는 제2 부분을 포함하는 식각 정지막; 상기 기판의 상기 셀 영역 상에 배치되는 커패시터 구조물로서, 상기 식각 정지막의 상기 제1 부분을 관통하여 상기 복수의 셀 트랜지스터에 각각 연결되며 상기 기판의 상면에 평행한 제1 방향을 따라 제1 피치로 배열되는 복수의 하부 전극을 포함하는, 커패시터 구조물을 포함하고, 상기 식각 정지막의 상기 제2 부분은 상기 제1 방향을 따라 상기 제1 피치와 동일한 제2 피치로 배열되는 복수의 리세스를 포함한다.

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Номер записи: 65

16-11-2023 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20230371236A1

Автор: Juanjuan HUANG, Weiping BAI

Принадлежит:

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a capacitor structure. The base is provided with a capacitive contact structure. The capacitor structure is connected to the capacitive contact structure, and the capacitor structure includes a plurality of capacitor units stacked in a direction vertical to the capacitive contact structure.

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Номер записи: 66

11-07-2023 дата публикации

Method for fabricating semiconductor device with alleviation feature

Номер: US0011699617B2

Автор: Tse-Yao Huang

Принадлежит: NANYA TECHNOLOGY CORPORATION

The present application provides a method for fabricating a semiconductor device including providing a substrate, concurrently forming a first conductive line and a bottom contact on the substrate, concurrently forming a first conductive line spacer on a sidewall of the first conductive line and a bottom contact spacer on a sidewall of the bottom contact, forming a first insulating layer over the substrate and concurrently forming an air gap between the first conductive line spacer and the bottom contact spacer.

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Номер записи: 67

11-04-2024 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING 3D MEMORY STRUCTURE

Номер: US20240121940A1

Автор: SHIH-FAN KUAN, HSU-CHENG FAN, JIANN-JONG WANG, CHUNG-HSIN LIN, YU-TING LIN

Принадлежит:

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.

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Номер записи: 68

12-03-2025 дата публикации

반도체 메모리 소자 및 그 제조 방법

Номер: KR102779204B1

Автор: 김희중, 안준혁, 윤재현, 이명동, 이석환, 한성희, 허인경

Принадлежит: 삼성전자주식회사

... 본 발명은 반도체 메모리 소자 및 그 제조 방법에 관한 것으로서, 보다 상세하게는 제1 활성 패턴을 갖는 기판, 상기 제1 활성 패턴은 제1 소스/드레인 영역 및 제2 소스/드레인 영역을 포함하며; 상기 제1 활성 패턴을 가로지르며 제1 방향으로 연장되는 게이트 전극, 상기 게이트 전극은 상기 제1 및 제2 소스/드레인 영역들 사이를 가로지고; 상기 제1 활성 패턴을 가로지르며 제2 방향으로 연장되는 비트 라인, 상기 비트 라인은 상기 제1 소스/드레인 영역과 전기적으로 연결되고; 상기 비트 라인의 일 측벽 상의 스페이서; 상기 제2 소스/드레인 영역에 전기적으로 연결되는 콘택, 상기 콘택은 상기 스페이서를 사이에 두고 상기 비트 라인과 이격되며; 상기 제2 소스/드레인 영역과 상기 콘택 사이에 개재된 계면막, 상기 계면막은 상기 제2 소스/드레인 영역과 상기 콘택간의 오믹 콘택을 형성하고; 및 상기 콘택 상의 정보 저장 요소를 포함한다. 상기 계면막과 접촉하는 상기 콘택의 바닥은 상기 기판의 상면보다 낮으며, 상기 콘택은, 금속, 도전성 금속 질화물 및 이들의 조합 중 적어도 하나로 이루어진다.

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Номер записи: 69

21-03-2024 дата публикации

SINGLE GATE THREE-DIMENSIONAL (3D) DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICES

Номер: US20240098971A1

Автор: Chang Seok KANG, Sung-Kwan KANG

Принадлежит: Applied Materials, Inc.

A memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including an active region, a cell transistor having a single gate above the active region in the first direction, and a cell capacitor having a bottom electrode layer that is electrically connected to the active region.

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Номер записи: 70

05-03-2024 дата публикации

Apparatuses including elongate pillars of access devices

Номер: US0011925014B2

Автор: Song Guo, Sanh D. Tang, Shen Hu, Yan Li, Nicholas R. Tapias

Принадлежит: Micron Technology, Inc.

A method of forming an apparatus comprises forming pillar structures extending from a base material. Upper portions of the pillar structures may exhibit a lateral width that is relatively greater than a lateral width of lower portions of the pillar structures. The method also comprises forming access lines laterally adjacent to the lower portions of the pillar structures and forming digit lines above upper surfaces of the pillar structures. Memory devices and electronic systems are also described.

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Номер записи: 71

04-10-2023 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: EP4255147A1

Автор: CHOI, Hyungeun, LEE, Kiseok, LEE, Haejoon, JUNG, Seungjae

Принадлежит:

A semiconductor memory device may include a lower layer including a first region and a second region, the lower layer extending in a first direction and a second direction perpendicular to the first direction, and a stack including word lines and interlayer insulating patterns, which are alternatingly stacked in a third direction perpendicular to the first direction and the second direction, the stack having a staircase structure on the second region. The word lines may extend from the first region to the second region in the first direction. Each of the word lines may include sub-gate electrodes, which extend parallel to each other in the first region, and a word line pad, which is connected in common to the sub-gate electrodes in the second region.

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Номер записи: 72

25-01-2024 дата публикации

MANUFACTURING METHOD FOR CAPACITOR STRUCTURE, CAPACITOR STRUCTURE AND MEMORY

Номер: US20240032313A1

Автор: Xingsong SU, Weiping BAI, Mengkang YU, Lianhong WANG

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A capacitor structure includes two electrodes arranged oppositely and a dielectric layer located between the two electrodes, wherein the dielectric layer includes at least two perovskite layers stacked; an amorphous layer is provided between every two adjacent perovskite layers; two outermost perovskite layers of the at least two perovskite layers are in contact with the two electrodes, respectively.

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Номер записи: 73

09-01-2024 дата публикации

Memory device

Номер: US0011871556B2

Автор: Il Do Kim, Dong Sun Sheen, Seung Hwan Kim

Принадлежит: SK hynix Inc.

A memory device includes a substrate, an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction and including an opened first side, a closed second side, and a channel layer between the first side and the second side, and a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer.

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Номер записи: 74

28-05-2024 дата публикации

Capacitor array, method for manufacturing the same and memory

Номер: US0011996440B2

Автор: Xiaoyu Yang, Liang Zhao

Принадлежит: Changxin Memory Technologies, Inc., CHANGXIN MEMORY TECHNOLOGIES, INC.

The present disclosure provides a method for manufacturing capacitor array, including: forming, on an upper surface of the substrate, a laminated structure including sacrificial layers and support layers; forming a patterned mask layer on an upper surface of the laminated structure; etching the laminated structure based on the patterned mask layer to form a through hole, wherein after the through hole is formed, the patterned mask layer is retained on the upper surface of the laminated structure, and the through hole penetrates through the patterned mask layer and the laminated structure; forming a first electrode on a sidewall and at a bottom of the through hole; forming, in the patterned mask layer and the laminated structure, and removing the sacrificial layer based on the opening; forming a capacitor dielectric layer on a surface of the first electrode; and forming a second electrode on a surface of the capacitor dielectric layer.

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Номер записи: 75

08-08-2023 дата публикации

Memory cell and memory device with the same

Номер: US0011723186B2

Автор: Seung Wook Ryu, Kyoung Ryul Yoon

Принадлежит: SK hynix Inc.

A memory device including a substrate; a bit line laterally oriented to be parallel to the substrate; a transistor including two channels that are laterally oriented from the bit line and a word line that is vertically oriented and surrounds the two channels; and a capacitor laterally oriented from the transistor.

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Номер записи: 76

18-01-2024 дата публикации

MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Номер: US20240023320A1

Автор: Yaqin Liu, Yanhong Wang, Wei Liu

Принадлежит:

A memory device includes a memory array structure including a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor, a first peripheral circuit coupled to a first surface of the memory array structure, and a second peripheral circuit coupled to a second surface of the memory array structure opposite to the first surface. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body.

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Номер записи: 77

25-06-2024 дата публикации

Semiconductor device and method for fabricating the same

Номер: US0012022646B2

Автор: Seung Hwan Kim

Принадлежит: SK hynix Inc.

A semiconductor device includes: a plurality of active layers stacked in a first direction perpendicular to a substrate and laterally oriented in a second direction intersecting with the first direction; a plurality of bit lines each of which is coupled to one side of each of the active layers and laterally oriented in a direction intersecting with the first direction and the second direction; a plurality of capacitors each of which is coupled to another side of each of the active layers; and a word line vertically oriented penetrating the active layers in the first direction.

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Номер записи: 78

19-03-2025 дата публикации

Semiconductor memory device

Номер: KR102784573B1

Автор: 박재홍, 박재화, 김문근, 황정하

Принадлежит: 삼성전자주식회사

A semiconductor memory device may include at least one semiconductor pattern including a horizontal portion extending in a second direction parallel to a top surface of a semiconductor substrate and a vertical portion extending in the first direction, at least one gate electrode on the horizontal portion of the at least one semiconductor pattern and extending in a third direction different from the first direction and the second direction, and at least one information storage element connected to the vertical portion of the at least one semiconductor pattern, wherein a thickness of the horizontal portion of the at least one semiconductor pattern in the first direction is smaller than a thickness of the vertical portion of the at least one semiconductor pattern in the first direction.

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Номер записи: 79

03-10-2023 дата публикации

Semiconductor memory device

Номер: US0011778808B2

Автор: Teruhisa Sonohara, Shunichi Seno, Hiroki Tokuhira, Fumitaka Arai

Принадлежит: Kioxia Corporation

A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

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Номер записи: 80

29-08-2023 дата публикации

Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating

Номер: US0011742022B2

Автор: Yuniarto Widjaja

Принадлежит: Zeno Semiconductor Inc., Zeno Semiconductor, Inc.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

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Номер записи: 81

30-05-2023 дата публикации

Memory device with vertical field effect transistor and method for preparing the same

Номер: US0011665881B2

Автор: Ming-Hung Hsieh

Принадлежит: NANYA TECHNOLOGY CORPORATION

The present disclosure relates to a memory device with a vertical field effect transistor (VFET) and a method for preparing the memory device. The memory device includes a capacitor contact disposed in a first semiconductor substrate, and a channel structure disposed over a top surface of the first semiconductor substrate. The memory device also includes a first gate structure disposed on a first sidewall of the channel structure, and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is opposite to the first sidewall of the channel structure. The memory device further includes a bit line contact disposed over the channel structure. The channel structure is electrically connected to a capacitor and a bit line through the capacitor contact and the bit line contact.

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Номер записи: 82

26-10-2023 дата публикации

MEMORY DEVICE

Номер: US20230345702A1

Автор: Ki Hong LEE

Принадлежит:

A memory cell comprising a substrate, a bit line vertically oriented from the substrate along a first direction, a nanosheet transistor including at least one nanosheet horizontally oriented from the bit line along a second direction perpendicular to the first direction, and a capacitor horizontally oriented from the nanosheet transistor along the second direction.

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Номер записи: 83

21-12-2023 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20230413522A1

Автор: Jungmin PARK, Hanjin LIM, Hyungsuk JUNG

Принадлежит: Samsung Electronics Co., Ltd.

A semiconductor device including a substrate, a plurality of lower electrodes on the substrate, a dielectric layer stack covering the lower electrodes, and an upper electrode covering the dielectric layer stack may be provided. The dielectric layer stack may include a first dielectric layer on the plurality of lower electrodes, the first dielectric layer including a material having anti-ferroelectricity or paraelectricity, and a second dielectric layer between the first dielectric layer and the upper electrode, the second dielectric layer including a material having ferroelectricity. The upper electrode may include a first upper electrode layer including an N-type impurity.

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Номер записи: 84

09-04-2024 дата публикации

Vertical heterostructure semiconductor memory cell and methods for making the same

Номер: US0011956940B2

Автор: Gerben Doornbos, Marcus Johannes Henricus Van Dal

Принадлежит: Taiwan Semiconductor Manufacturing Company Limited

A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.

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Номер записи: 85

25-06-2024 дата публикации

Method of forming an electrode on a substrate and a semiconductor device structure including an electrode

Номер: US0012020938B2

Автор: Moataz Bellah Mousa, Peng-Fu Hsu, Ward Johnson, Petri Raisanen

Принадлежит: ASM IP Holding B.V.

A method of forming an electrode on a substrate is disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a titanium tetraiodide (TiI4) precursor; contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and depositing a titanium nitride layer over a surface of the substrate thereby forming the electrode; wherein the titanium nitride layer has an electrical resistivity of less than 400 μΩ-cm. Related semiconductor device structures including a titanium nitride electrode deposited by the methods of the disclosure are also provided.

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Номер записи: 86

09-05-2023 дата публикации

Semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing liner having different thicknesses

Номер: US0011646268B2

Автор: Chin-Te Kuo

Принадлежит: NANYA TECHNOLOGY CORPORATION

The present disclosure provides a semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing lining layer and a method for preparing the same. The semiconductor device structure includes a substrate having a pattern-dense region and a pattern-loose region; a first conductive layer disposed over the substrate; a first dielectric layer disposed over the first conductive layer; a first conductive plug and a second conductive plug disposed in the first dielectric layer; wherein the first conductive plug and the second conductive plug comprises copper (Cu) and are separated from the first dielectric layer by the a first lining layer comprising manganese (Mn); wherein the first conductive plug and the second conductive plug have different aspect ratios.

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Номер записи: 87

31-08-2023 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICES

Номер: US20230276614A1

Автор: Seokho SHIN, Taegyu KANG, Byeungmoo KANG, Joongchan SHIN

Принадлежит:

A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

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Номер записи: 88

04-07-2023 дата публикации

3D pitch multiplication

Номер: US0011696433B2

Автор: Nitin K. Ingle, Fredrick Fishburn

Принадлежит: Applied Materials, Inc.

Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.

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Номер записи: 89

25-01-2024 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR

Номер: US20240032282A1

Автор: Meng HUANG

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A semiconductor structure includes: a substrate; a stacked structure, contact structures, and storage nodes. The stacked structure is located on the substrate and includes semiconductor layers extending in a first direction and arranged in a spaced manner in a second direction and in a third direction, wherein the first direction and the second direction are directions parallel to a plane where the substrate is located, the first direction is perpendicular to the second direction, and the third direction is a direction perpendicular to the plane where the substrate is located. The contact structures include a first end and a second end in the first direction, wherein the first ends of the contact structures are connected to the semiconductor layers, and a material of the contact structures includes metal silicide. The storage nodes extend in the first direction and are connected to a second end of respective contact structures.

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Номер записи: 90

02-05-2024 дата публикации

SEMICONDUCTOR MEMORY DEVICES

Номер: US20240147695A1

Автор: Jaecheon YONG, Daehong KO

Принадлежит: Samsung Electronics Co., Ltd., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY

A semiconductor memory device including a semiconductor layer including a source area, a channel area, and a drain area arranged in a first horizontal direction on a substrate, a cell capacitor extending in the first horizontal direction on the substrate and including a lower electrode layer, a capacitor dielectric film, and an upper electrode layer connected to the source area, a bit line extending in a vertical direction on the substrate and connected to the drain area, and a gate structure covering the channel area, and the gate structure including a gate dielectric film on the channel area and a gate electrode film on the gate dielectric film, wherein in the vertical direction, a first thickness of an end of the channel area facing the source area is greater than a second thickness of another end of the channel area facing the drain area may be provided.

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Номер записи: 91

21-12-2023 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Номер: US20230413507A1

Автор: Kang YOU

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first isolation groove extending in a first direction and a plurality of active columns arranged in an array along the first direction and a third direction, the substrate being divided into a first area and a second area by the first isolation groove along a second direction, the active columns being supported through support structures; forming semi-capacitor structures located in the first area and gate-all-around structures located in the second area in gaps between the active columns; processing the active columns and the semi-capacitor structures in the first area to form capacitor structures extending in the second direction; and forming first connecting structures connecting the gate-all-around structures and the capacitor structures in the first isolation groove.

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Номер записи: 92

27-06-2024 дата публикации

MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES, AND ELECTRONIC SYSTEMS

Номер: US20240215221A1

Автор: Fatma Arzum Simsek-Ege

Принадлежит:

A microelectronic device includes first memory array region and second memory array regions, each comprising vertical stacks of dynamic random access memory (DRAM) cells. A staircase region is between the first memory array region and the second memory array region and comprises a staircase structure comprising a vertical stack of first conductive structures horizontally extending through the staircase region in a first direction, the first conductive structures configured to be in contact with the DRAM cells of the first memory array region and DRAM cells of the second memory array region, and sub-staircase structures individually comprising second conductive structures horizontally extending from the vertical stack of first conductive structures in a second direction. Horizontally neighboring sub-staircase structures are substantially evenly horizontally spaced from one another in the first direction. Related microelectronic devices, memory devices, and electronic systems are also described ...

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Номер записи: 93

11-01-2024 дата публикации

MEMORY AND MANUFACTURING METHOD THEREOF

Номер: US20240015954A1

Автор: CHIH-CHENG LIU

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A memory includes a substrate; a plurality of bit lines on the substrate, which are parallel to each other and extend in a first direction; a plurality of active pillars on the bit lines, bottom ends of which are connected to the bit lines; a plurality of word lines parallel to each other and extending in a second direction, which surround outer sidewalls of the active pillars, and expose top ends of the active pillars, the active pillars and the word lines jointly constitute vertical memory transistors of the memory; and a plurality of capacitors and a plurality of connecting pads, each of the capacitors is located on each of the active pillars, each of the connecting pads is located between the active pillar and the capacitor.

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Номер записи: 94

27-06-2024 дата публикации

Semiconductor Structure and Method of Making the Same

Номер: US20240215226A1

Автор: Tieh-Chiang Wu, Lingxin Zhu

Принадлежит:

A semiconductor structure and a method making it are disclosed. The method includes: providing a substrate, and sequentially forming a bitline contact structure and a bitline on the substrate; the bitline includes a connection layer connected to the bitline contact structure. The bitline contact structure and the sidewalls of the connection layer are etched back. A first silicide layer covering the sidewalls of the bitline contact structure, and a second silicide layer covering the sidewalls of the connection layer are formed. This structure can reduce the contact resistance between the bitline contact structure and the bitline, as well as the parasitic capacitance between the bitline contact structure and the adjacent conductive structures, thereby improving the electrical performance and reliability of the semiconductor structure and improving the semiconductor yield.

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Номер записи: 95

27-06-2024 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20240215227A1

Автор: Dong Yean OH, Jin Sun CHO

Принадлежит:

A semiconductor device includes a horizontal layer spaced apart from a lower structure to extend in a direction parallel to the lower structure; a vertical conductive line extending in a direction perpendicular to the lower structure and coupled to a first-side end of the horizontal layer; a data storage element coupled to a second-side end of the horizontal layer; and a horizontal conductive line including a first horizontal conductive line and a second horizontal conductive line that are vertically asymmetrical with the horizontal layer interposed therebetween.

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Номер записи: 96

20-06-2024 дата публикации

HYBRID GATE DIELECTRIC ACCESS DEVICE FOR VERTICAL THREE-DIMENSIONAL MEMORY

Номер: US20240206152A1

Автор: Kamal M. Karda, Haitao Liu, Scott E. Sills, Si-Woo Lee

Принадлежит:

Systems, methods and apparatus are provided for a hybrid gate dielectric access device for vertical three-dimensional (3D) memory. The memory cell has a first horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. The first access device is operatively controlled by a first gate. A hybrid gate dielectric separates the gate from the channel region and a horizontally oriented storage node coupled to the second source/drain region of the access device.

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Номер записи: 97

20-06-2024 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Номер: US20240206153A1

Автор: Shuxian Wu, Huihuang Tang

Принадлежит: Fujian Jinhua Integrated Circuit Co., Ltd.

The invention discloses a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, storage node pads, a capacitor structure and a supporting structure. The storage node pads are disposed on the substrate. The capacitor structure is disposed on the storage node pads and includes a plurality of capacitors. The capacitor structure includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer from bottom to top, wherein the top portion of the bottom electrode layer is provided with a recess. The supporting structure includes a plurality of first supporting layers and a plurality of second supporting layers from bottom to top, and the supporting structure connects two adjacent capacitors, wherein the recesses face each second supporting layer respectively.

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Номер записи: 98

19-12-2023 дата публикации

3D 1T1C stacked DRAM structure and method to fabricate

Номер: US0011849572B2

Автор: Aaron Lilak, Sean T. Ma, Abhishek Sharma

Принадлежит: Intel Corporation

Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.

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Номер записи: 99

11-01-2024 дата публикации

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20240015946A1

Автор: Kyooho JUNG, Wonsik CHOI

Принадлежит: Samsung Electronics Co., Ltd.

A method of manufacturing an integrated circuit device includes forming a plurality of lower electrodes above a substrate, forming a dielectric film on the plurality of lower electrodes, forming a doped upper interface film on the dielectric film, and forming an upper electrode on the doped upper interface film, wherein the doped upper interface film includes a dopant, and the dopant includes one selected from tin (Sn), molybdenum (Mo), niobium (Nb), tantalum (Ta), and aluminum (Al).

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Номер записи: 100

05-01-2012 дата публикации

Semiconductor Constructions

Номер: US20120001299A1

Автор: Todd Jackson Plum

Принадлежит: Micron Technology Inc

Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.

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Номер записи: 101

26-01-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120018799A1

Автор: Hyung Jin Park

Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.

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Номер записи: 102

26-01-2012 дата публикации

Pillar type capacitor of semiconductor device and method for forming the same

Номер: US20120019980A1

Автор: Cheol Hwan Park, Dong Kyun Lee, Ho Jin Cho

Принадлежит: Hynix Semiconductor Inc

An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.

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Номер записи: 103

02-02-2012 дата публикации

System with logic and embedded mim capacitor

Номер: US20120025285A1

Автор: Jeong Y. Choi

Принадлежит: Mosys Inc

An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the logic region than in the memory region

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Номер записи: 104

01-03-2012 дата публикации

A dram cell structure with extended trench and a manufacturing method thereof

Номер: US20120049262A1

Автор: Jing Chen, Miao Zhang, Xi Wang, Xiaolu Huang

Принадлежит: Shanghai Institute of Microsystem and Information Technology of CAS

A DRAM cell structure with extended trench, the DRAM cell structure comprises: a NMOS transistor and a trench capacitor connected with the source electrode of the NMOS transistor; the trench capacitor comprises: a semiconductor substrate; a multilayer structure as the bottom plate of the trench capacitor, formed over the semiconductor substrate, which is composed of N-type SiGe layers and N-type Si layers arranged alternatively; a trench formed through the multilayer structure deeply into the semiconductor substrate, whose sidewall cross section is serrate-shaped; a dielectric layer formed on the inner face of the trench; a first polycrystalline silicon layer which is filled in the trench as the top plate of the trench capacitor; and a P-type Si layer formed over the multilayer structure. The present invention adopts doping epitaxial growth process to fabricate a multilayer structure composed of N-type SiGe layers and N-type Si layers arranged alternatively as the bottom plate of the trench capacitor. Compared with the traditional buried plate, the fabricating process is simplified. In addition, the present invention adopts selective etching process to form a sidewall having a serrate-shaped cross section. This improved structure increases capacitor plate area and thus even thick dielectric layer will achieve required capacitance.

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Номер записи: 105

01-03-2012 дата публикации

Method for fabricating semiconductor device

Номер: US20120052643A1

Автор: Baek-Mann Kim

Принадлежит: Individual

A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.

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Номер записи: 106

15-03-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120064690A1

Автор: Takakazu Kiyomura, Toshiyuki Hirota

Принадлежит: Elpida Memory Inc

A method for manufacturing a semiconductor device includes at least forming a lower electrode made of titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide, in which at least the uppermost layer of the dielectric film is formed by an atomic layer deposition (ALD) method on the lower electrode, forming a first protective film on the dielectric film without exceeding the film forming temperature of the ALD method over 70° C., and forming an upper electrode made of a titanium nitride on the first protective film.

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Номер записи: 107

29-03-2012 дата публикации

Semiconductor Device

Номер: US20120074473A1

Автор: Sang Don Lee

Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on the partial-insulated substrate.

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Номер записи: 108

12-04-2012 дата публикации

Method of manufacturing vertical semiconductor device

Номер: US20120088343A1

Автор: Jong-Hyuk Kang, Jong-wook Lee, Yong-Hoon Son

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

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Номер записи: 109

19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091518A1

Автор: Mitsunari Sukekawa

Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate having a first groove, a word line in the first groove, and a buried insulating film in the first groove. The buried insulating film covers the word line. The buried insulating film comprises a silicon nitride film.

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Номер записи: 110

19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091520A1

Автор: Nobuyuki Nakamura

Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

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Номер записи: 111

03-05-2012 дата публикации

Semiconductor Device Having Island Type Support Patterns

Номер: US20120104559A1

Автор: Hyun-Chul Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a plurality of cylindrical structures arranged in a first direction and a second direction, and a plurality of unit regions formed in the first direction and the second direction, each of the plurality of unit regions including an island type support pattern supporting the plurality of cylindrical structures contacting side surfaces of the plurality of cylindrical structures and an open region exposing the side surfaces of the plurality of cylindrical structures.

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Номер записи: 112

10-05-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120112269A1

Автор: Suk Min Kim

Принадлежит: Hynix Semiconductor Inc

A technology is a semiconductor device and a method of manufacturing the same, capable of reducing capacitance with a storage node contact plug while maintaining a height and resistance of a bit line, by thickly forming a spacer between a bit line and the storage node contact plug. A semiconductor device includes a device isolation layer defining a plurality of active regions formed in a semiconductor substrate, a storage node contact hole exposing two neighboring active regions, a storage node contact plug material provided in the storage node contact hole, a bit line region that divides the storage node contact plug material into two parts and that has a convex portion at a lower portion of a sidewall, a spacer formed over a sidewall of the bit line region including the convex portion and a bit line formed in the bit line region.

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Номер записи: 113

10-05-2012 дата публикации

Methods of manufacturing semiconductor devices

Номер: US20120115293A1

Автор: Hun-Hyeong Lim, Jin-Gyun Kim, Jin-Tae Noh, Ki-Hyun Hwang, Sang-Ryol Yang

Принадлежит: SAMSUNG ELECTRONICS CO LTD

In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.

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Номер записи: 114

31-05-2012 дата публикации

Semiconductor device and method of forming the same

Номер: US20120132971A1

Автор: Noriaki Mikasa

Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

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Номер записи: 115

31-05-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120135601A1

Автор: Bok-yeon Won, Jong-Chul Park, Sang-Sup Jeong

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.

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Номер записи: 116

07-06-2012 дата публикации

1t mim memory for embedded ram application in soc

Номер: US20120139022A1

Автор: Chen-Jong Wang, Chien-Hua Huang, Chun-Yao Chen, Chung S. Wang, Kun-Lung Chen, PING Yang, Shou-Gwo Wuu, Yi-Ching Lin

Принадлежит: Individual

Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

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Номер записи: 117

21-06-2012 дата публикации

Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit

Номер: US20120153431A1

Автор: Andres Bryant, Brent A. Anderson, Edward J. Nowak, Herbert L. Ho

Принадлежит: International Business Machines Corp

Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).

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Номер записи: 118

21-06-2012 дата публикации

Method for fabricating semiconductor device with buried gate

Номер: US20120156869A1

Автор: Jong-Han Shin, Kyung-Bo Kim

Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming an isolation layer for defining an active region by using the hard mask pattern, forming a buried gate in and across the active region and the isolation layer over the substrate, forming an inter-layer dielectric layer over the substrate, forming a storage node contact hole that exposes the hard mask pattern by selectively etching the inter-layer dielectric layer, extending the storage node contact hole to expose the active region by removing the hard mask pattern exposed under the storage node contact hole, and forming a storage node contact plug that fills the extended storage node contact hole.

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Номер записи: 119

28-06-2012 дата публикации

Rectangular capacitors for dynamic random access memory (dram) and dual-pass lithography methods to form the same

Номер: US20120161215A1

Автор: Nick Lindert

Принадлежит: Intel Corp

A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective.

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Номер записи: 120

12-07-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120175734A1

Автор: Sang Ho Sohn

Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. The semiconductor device includes a first storage node contact plug and a second storage node contact plug formed over a semiconductor substrate, wherein the second storage node contact plug is arranged at a height different from that of the first storage node contact plug, and a lower electrode formed over the first storage node contact plug and the second storage node contact plug.

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Номер записи: 121

19-07-2012 дата публикации

Semiconductor device

Номер: US20120181660A1

Автор: Naonori Fujiwara

Принадлежит: Elpida Memory Inc

A semiconductor device comprises a capacitor, the capacitor including a lower electrode, a dielectric film containing crystalline zirconium oxide formed on the lower electrode, and an upper electrode containing a titanium nitride film contacting to the dielectric film, wherein the dielectric film comprises an amorphous film on an interface with the titanium nitride film, thereby preventing the reduction of the thickness of the titanium nitride film formed on the dielectric electrode with a low leakage current and a high dielectric constant.

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Номер записи: 122

26-07-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120187535A1

Автор: Un Hee LEE

Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.

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Номер записи: 123

09-08-2012 дата публикации

Semiconductor memory device and method for manufacturing the same

Номер: US20120199842A1

Автор: Yasuhiko Takemura

Принадлежит: Semiconductor Energy Laboratory Co Ltd

A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F 2 .

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Номер записи: 124

16-08-2012 дата публикации

Semiconductor device including capacitor and double-layer metal contact and fabrication method thereof

Номер: US20120205733A1

Автор: Chun Soo Kang

Принадлежит: Hynix Semiconductor Inc

Disclosed are a semiconductor device comprising a capacitor and a double-layer metal contact and a method fabricating the same. The method comprising: forming a gate of a peripheral transistor for a peripheral circuit; forming a first contact and a first peripheral circuit wiring layer pattern on a first interlayer insulating layer; forming a second contact and a second peripheral circuit wiring layer pattern; selectively removing a portion of the second interlayer insulating layer in a cell region; forming a mold layer covering the second peripheral circuit wiring layer pattern; forming storage nodes passing through the mold layer; removing the mold layer; forming a dielectric layer and a plate node, which cover the storage nodes; forming a third interlayer insulating layer; and forming third contacts passing through the third interlayer insulating layer.

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Номер записи: 125

23-08-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120211830A1

Автор: Min Soo Yoo

Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method of fabricating the same are provided, in which a full overlap between a storage node contact and an active region to solve an overlay in an etching process and an etching width of a storage node is increased to improve a processing margin. The semiconductor device includes a main gate and a device isolation structure disposed in a semiconductor device, an isolation pattern disposed over the device isolation structure, and contact plugs disposed at each side of the isolation pattern.

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Номер записи: 126

23-08-2012 дата публикации

Method for obtaining extreme selectivity of metal nitrides and metal oxides

Номер: US20120214306A1

Автор: Kevin R. Shea

Принадлежит: Micron Technology Inc

Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H 2 F 2 . The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.

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Номер записи: 127

13-09-2012 дата публикации

Methods of fabricating a semiconductor device having metallic storage nodes

Номер: US20120231601A1

Автор: Byoung-Yong Gwak, Inseak Hwang, Mongsup Lee, Sang-Jun Lee, Sukhun Choi

Принадлежит: Individual

The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven.

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Номер записи: 128

27-09-2012 дата публикации

Semiconductor device having cell capacitors

Номер: US20120241830A1

Автор: Hiroyuki Uchiyama

Принадлежит: Elpida Memory Inc

A semiconductor device including: a bit line being arranged on top surfaces of first and second contact plugs via a first insulation layer and extending in a direction connecting a first impurity diffusion layer and a second impurity diffusion layer; a bit line contact plug being formed through the first insulation layer and electrically connecting the bit line to the first contact plug; a first cell capacitor having a first lower electrode beside one of side surfaces of the bit line; a first insulation film insulating the bit line and the first lower electrode from each other; and a first contact conductor electrically connecting a bottom end of the first lower electrode to a side surface of the second contact plug.

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Номер записи: 129

04-10-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120252186A1

Автор: Young Man Cho

Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.

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Номер записи: 130

25-10-2012 дата публикации

Method of Fabricating Isolated Capacitors and Structure Thereof

Номер: US20120267754A1

Автор: Dominic J. Schepis, Junedong Lee, Oh-Jung Kwon, Paul C. Parries

Принадлежит: International Business Machines Corp

A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

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Номер записи: 131

01-11-2012 дата публикации

Semiconductor cell and method for forming the same

Номер: US20120273919A1

Автор: Song Hyeuk Im

Принадлежит: Hynix Semiconductor Inc

A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.

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Номер записи: 132

29-11-2012 дата публикации

SOI Trench Dram Structure With Backside Strap

Номер: US20120302020A1

Автор: Ali Khakifirooz, Bruce B. Doris, Ghavam G. Shahidi, Kangguo Cheng, Pranita Kulkarni

Принадлежит: International Business Machines Corp

In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.

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Номер записи: 133

06-12-2012 дата публикации

High density memory cells using lateral epitaxy

Номер: US20120305998A1

Автор: Byeong Kim, Chengwen Pei, David M. Fried, Geng Wang, Joseph Ervin, Kangguo Cheng, Ravi M. Todi, Roger A. Booth, Jr.

Принадлежит: International Business Machines Corp

In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

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Номер записи: 134

20-12-2012 дата публикации

Method of Forming Conductive Contacts on a Semiconductor Device with Embedded Memory and the Resulting Device

Номер: US20120322225A1

Автор: Peter Baars, Till Schloesser

Принадлежит: Globalfoundries Inc

A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.

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Номер записи: 135

24-01-2013 дата публикации

Semiconductor device

Номер: US20130020570A1

Автор: Shunpei Yamazaki

Принадлежит: Semiconductor Energy Laboratory Co Ltd

An object of the present invention is to provide a semiconductor device in which stored data can be held even when power is not supplied for a certain time. Another object is to increase the degree of integration of a semiconductor device and to increase the storage capacity per unit area. A semiconductor device is formed with a material capable of sufficiently reducing off-state current of a transistor, such as an oxide semiconductor material that is a wide-bandgap semiconductor. With the use of a semiconductor material capable of sufficiently reducing off-state current of a transistor, the semiconductor device can hold data for a long time. Furthermore, a wiring layer provided under a transistor, a high-resistance region in an oxide semiconductor film, and a source electrode are used to form a capacitor, thereby reducing the area occupied by the transistor and the capacitor.

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Номер записи: 136

14-02-2013 дата публикации

Film forming method, manufacturing method of semiconductor device using the same, film forming apparatus, and semiconductor device

Номер: US20130037873A1

Автор: Keisuke Suzuki, Kentaro Kadonaga, Yuichiro Morozumi

Принадлежит: Tokyo Electron Ltd

Provided is a semiconductor device capable of preventing destruction of an electrode having a pillar shape and densely arranged. The semiconductor device having a field-effect transistor and a capacitor having a pillar shape, the semiconductor device includes: a first electrode having a pillar shape and electrically connected to an impurity diffusion region of the field-effect transistor; a dielectric film formed at least on a side of the first electrode; a second electrode formed on the dielectric film; and a support film extending in a direction crossing a length direction of the first electrode having the pillar shape, and formed by a boron-added silicon nitride film connected to the first electrode by penetrating through at least a part of the second electrode.

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Номер записи: 137

28-02-2013 дата публикации

Integrated circuits that include deep trench capacitors and methods for their fabrication

Номер: US20130049089A1

Автор: Peter Baars, Till Schloesser

Принадлежит: Globalfoundries Inc

Methods are provided for fabricating an integrated circuit that includes a deep trench capacitor. One method includes fabricating a plurality of transistors on a semiconductor substrate, the plurality of transistors each including gate structures, source and drain regions, and silicide contacts to the source and drain regions. A trench is then etched into the semiconductor substrate in proximity to the drain region of a selected transistor. The trench is filled with a layer of metal in contact with the semiconductor substrate, a layer of dielectric material overlying the layer of metal, and a second metal overlying the layer of dielectric material. A metal contact is then formed coupling the second metal to the silicide contact on the drain region of the selected transistor. A bit line is formed contacting the source region of the selected transistor and a word line is formed contacting the gate structure of the transistor.

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Номер записи: 138

28-02-2013 дата публикации

Semiconductor device having a reduced bit line parasitic capacitance and method for manufacturing the same

Номер: US20130052788A1

Автор: Jeong Hoon Park

Принадлежит: Hynix Semiconductor Inc

A semiconductor device having a reduced bit line parasitic capacitance and a method of making same is presented. The semiconductor device includes a first, second, third, and fourth interlayer dielectric layers, first and second bit lines, first and second landing plug and first and second storage node contacts. An optional capacitor may be added to complete a CMOS configuration for the semiconductor device. The storage node contacts traverse through the interlayer dielectric layer and are electrically coupled to their respective landing plug contacts. The storage node contacts are deliberately offset, relative to the center of the corresponding landing plug contacts, at a predetermined distance in a direction away from the first bit line. This offsetting aids reducing the parasitic capacitance between the bit line and a storage node.

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Номер записи: 139

07-03-2013 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20130056850A1

Автор: Hiroki Shirai, Hiroyuki Kunishima, Ippei Kume, Kenichiro Hijioka, Manabu Iguchi, Naoya Inoue

Принадлежит: Renesas Electronics Corp

To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.

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Номер записи: 140

21-03-2013 дата публикации

Memory cells, semiconductor devices, systems including such cells, and methods of fabrication

Номер: US20130069052A1

Автор: Gurtej S. Sandhu

Принадлежит: Micron Technology Inc

A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

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Номер записи: 141

21-03-2013 дата публикации

Semiconductor storage device

Номер: US20130069132A1

Автор: Takashi Okuda, Tomoaki Atsumi

Принадлежит: Semiconductor Energy Laboratory Co Ltd

Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.

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Номер записи: 142

21-03-2013 дата публикации

Electrode Treatments for Enhanced DRAM Performance

Номер: US20130069202A1

Автор: Edward Haywood, Hanhong Chen, Kenichi Koyanagi, Naonori Fujiwara, Sandra G. Malhotra, Takakazu Kiyomura, Takashi Arao, Toshiyuki Hirota, Xiangxin Rui

Принадлежит: Elpida Memory Inc, Intermolecular Inc

A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO 2 ) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.

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Номер записи: 143

11-04-2013 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20130089964A1

Автор: Kana Shimizu, Takamasa Itou, Takayuki Iwaki

Принадлежит: Renesas Electronics Corp

A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.

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Номер записи: 144

18-04-2013 дата публикации

Deposited Material and Method of Formation

Номер: US20130093048A1

Автор: Cheng-Yuan Tsai, Hsing-Lien Lin, Yao-Wen Chang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

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Номер записи: 145

18-04-2013 дата публикации

Methods Of Forming Circuit Structures Within Openings And Methods Of Forming Conductive Lines Across At Least A Portion Of A Substrate

Номер: US20130095655A1

Автор: Sanh D. Tang, Sony Varghese

Принадлежит: Micron Technology Inc

A method of forming circuit structures within openings includes forming pairs of spaced projections that project elevationally relative to a support material on opposing sides of respective openings formed into the support material. At least two of the spaced projections of different of the pairs are received between immediately adjacent of the openings. Conductive metal is formed elevationally over the projections and into and overfilling the openings. The metal is of a composition different from that of at least elevationally outermost portions of the projections. The metal is removed from being elevationally over the projections and at least some of the metal between the projections is removed. Other embodiments and aspects are disclosed.

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Номер записи: 146

25-04-2013 дата публикации

Method for fabricating single-sided buried strap in a semiconductor device

Номер: US20130102123A1

Автор: Hsien-Wen Liu, Tzu-Ching Tsai, Yi-Nan Chen

Принадлежит: Nanya Technology Corp

A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.

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Номер записи: 147

16-05-2013 дата публикации

Adsorption Site Blocking Method for Co-Doping ALD Films

Номер: US20130119513A1

Автор: Hanhong Chen, Hiroyuki Ode, Sandra Malhotra, Toshiyuki Hirota, Wim Deweerd

Принадлежит: Elpida Memory Inc, Intermolecular Inc

A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

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Номер записи: 148

23-05-2013 дата публикации

Band Gap Improvement In DRAM Capacitors

Номер: US20130127015A1

Автор: Hanhong Chen, Hiroyuki Ode, Sandra Malhotra, Wim Deweerd

Принадлежит: Intermolecular Inc

A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO 2 and ZrO 2 and further comprises a dopant of Al 2 O 3 . In some embodiments, the compound high k dielectric material comprises an admixture of TiO 2 and HfO 2 and further comprises a dopant of Al 2 O 3 .

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Номер записи: 149

23-05-2013 дата публикации

Method for manufacturing semiconductor device with first and second gates over buried bit line

Номер: US20130130453A1

Автор: Hyung Jin Park

Принадлежит: SK hynix Inc

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.

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Номер записи: 150

30-05-2013 дата публикации

Polysilicon/metal contact resistance in deep trench

Номер: US20130134491A1

Автор: Brian W. Messenger, Chengwen Pei, Geng Wang, Paul C. Parries, Yanli Zhang

Принадлежит: International Business Machines Corp

A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

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Номер записи: 151

06-06-2013 дата публикации

Capacitor Forming Methods

Номер: US20130140271A1

Автор: Mark Kiehlbauch

Принадлежит: Micron Technology Inc

A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.

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Номер записи: 152

13-06-2013 дата публикации

Method for forming buried bit line, semiconductor device having the same, and fabricating method thereof

Номер: US20130146958A1

Автор: Jin-Ki Jung, You-Song Kim

Принадлежит: Individual

A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.

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Номер записи: 153

13-06-2013 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20130147013A1

Автор: Hiroyuki Ode

Принадлежит: Elpida Memory Inc

A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.

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Номер записи: 154

13-06-2013 дата публикации

Integrated circuit devices including electrode support structures and methods of fabricating the same

Номер: US20130147048A1

Автор: Bong-Jin Kuh, Byung-hong Chung, Han-mei Choi, Jong-Sung Lim, Sang-Ryol Yang, Soon-Wook Jung, Young-Sub You

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.

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Номер записи: 155

27-06-2013 дата публикации

Methods Of Forming Capacitors

Номер: US20130164902A1

Автор: Joseph Neil Greeley, Niraj B. Rana, Prashant Raghu

Принадлежит: Micron Technology Inc

A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.

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Номер записи: 156

04-07-2013 дата публикации

Memory capacitor having a robust moat and manufacturing method thereof

Номер: US20130168812A1

Автор: Chung-Lin Huang, Ron-Fu Chu, Tzung-Han Lee

Принадлежит: Inotera Memories Inc

A manufacturing method for memory capacitor having a robust moat, comprising the steps of: providing a substrate; forming a patterned sacrificial layer on the substrate having a moat to separate a cell area and a peripheral area; forming a supporting layer on the sacrificial layer and filling the moat to form a annular member, wherein the supporting layer and the sacrificial layer arranged in alignment to form a stack structure; forming a plurality row of capacitor trenches on the substrate, wherein the capacitor trenches are formed at intervals in the stack structure; and forming a conducting layer on the supporting layer and covering the substrate and the inner surface of the stack structure defining the capacitor trenches.

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Номер записи: 157

11-07-2013 дата публикации

Integrated circuit including dram and sram/logic

Номер: US20130175594A1

Автор: Ali Khakifirooz, Bruce B. Doris, Chun-Chen Yeh, Kangguo Cheng, Pranita Kulkarni, Tenko Yamashita, Terence B. Hook, Veeraraghavan S. Basker

Принадлежит: International Business Machines Corp

An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

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Номер записи: 158

29-08-2013 дата публикации

Semiconductor device

Номер: US20130221356A1

Автор: Kensuke Yoshizumi, Shunpei Yamazaki

Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

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Номер записи: 159

05-09-2013 дата публикации

Semiconductor memory devices and methods of forming the same

Номер: US20130230961A1

Автор: Byoung-Yong Gwak, Hyong-Soo Kim, Kukhan Yoon

Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes.

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Номер записи: 160

17-10-2013 дата публикации

Formation of dram capacitor among metal interconnect

Номер: US20130271938A1

Автор: Joseph M. Steigerwald, Kanwal Jit Singh, Nick Lindert

Принадлежит: Intel Corp

Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

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Номер записи: 161

24-10-2013 дата публикации

Capacitors and semiconductor devices including the same

Номер: US20130277724A1

Автор: Jong-ryul JUN

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A capacitor includes a lower electrode having a curved surface, a first seed on a sidewall of the lower electrode, which the first seed includes a metal silicide and has a shape corresponding to the curved surface of the lower electrode, a dielectric layer on the lower electrode, the dielectric layer covering the first seed, and an upper electrode on the dielectric layer.

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Номер записи: 162

07-11-2013 дата публикации

Semiconductor device and method of fabricating

Номер: US20130292794A1

Автор: Chih-Yang Pai, Chung-Yen Chou, Kuo-Chi Tu, Wen-Chuan Chiang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.

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Номер записи: 163

14-11-2013 дата публикации

Capacitor and method for fabricating the same

Номер: US20130299942A1

Автор: Jong-Kook Park, Yong-Tae Cho

Принадлежит: Individual

A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.

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Номер записи: 164

05-12-2013 дата публикации

Semiconductor device with air gap and method for fabricating the same

Номер: US20130320549A1

Автор: Hyo-Seok Lee, Seung-Jin Yeom

Принадлежит: Individual

A method for fabricating a semiconductor device includes forming, over a substrate, a plurality of first conductive structures which are separated from one another; forming multi-layered dielectric patterns including a first dielectric layer which covers upper ends and both sidewalls of the first conductive structures; removing portions of the first dielectric layer starting from lower end portions of the first conductive structures to define air gaps, and forming second conductive structures which are filled between the first conductive structures.

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Номер записи: 165

12-12-2013 дата публикации

Spacer isolation in deep trench

Номер: US20130328157A1

Автор: Chengwen Pei, Geng Wang, Joseph Ervin, Kangguo Cheng, Ravi M. Todi

Принадлежит: International Business Machines Corp

A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

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Номер записи: 166

23-01-2014 дата публикации

Dram with dual level word lines

Номер: US20140021523A1

Автор: Babar A. Khan, Effendi Leobandung

Принадлежит: International Business Machines Corp

A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

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Номер записи: 167

23-01-2014 дата публикации

Process-compatible decoupling capacitor and method for making the same

Номер: US20140021584A1

Автор: Kuo-Chi Tu, Wen-Ting Chu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

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Номер записи: 168

30-01-2014 дата публикации

Method of manufacturing semiconductor device having cylindrical lower capacitor electrode

Номер: US20140030865A1

Автор: Satoru Isogai, Takahiro Kumauchi

Принадлежит: Elpida Memory Inc

To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.

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Номер записи: 169

06-02-2014 дата публикации

Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer

Номер: US20140038384A1

Автор: Chih-Hsun Lin, Kuan-Chi Tsai, Kun-Mao Wu, Yu-Lung Yeh

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.

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Номер записи: 170

13-02-2014 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20140042554A1

Автор: Ahn Sook YOON

Принадлежит: SK hynix Inc

A semiconductor device is formed by depositing a nitride material having a lower etch rate than an oxide material over or between buried gates when forming a metal contact at an end portion of a cell region, to prevent a lower substrate from being etched during an etching process forming a metal contact hole. The semiconductor device includes at least one buried gate formed in a device isolation film of a semiconductor substrate, an etch stop film formed over and between the buried gates, and a metal contact formed perpendicular to the buried gate in the etch stop film.

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Номер записи: 171

27-02-2014 дата публикации

Arrays of Vertically-Oriented Transistors, And Memory Arrays Including Vertically-Oriented Transistors

Номер: US20140054718A1

Автор: Kamal M. Karda, Sanh D. Tang, Shyam Surthi, Wolfgang Mueller

Принадлежит: Micron Technology Inc

An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed.

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Номер записи: 172

02-01-2020 дата публикации

Semiconductor memory device

Номер: US20200006231A1

Автор: Jiyoung Kim, Jungwoo Song, Kwangmin Kim, Kwangtae HWANG, Ye-Ro Lee, Yong Kwan Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

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Номер записи: 173

02-01-2020 дата публикации

Elevationally-Elongated Conductive Structure Of Integrated Circuitry, Method Of Forming An Array Of Capacitors, Method Of Forming DRAM Circuitry, And Method Of Forming An Elevationally-Elongated Conductive Structure Of Integrated Circuitry

Номер: US20200006472A1

Автор: Kuo-Chen Wang, Sanh D. Tang

Принадлежит: Micron Technology Inc

A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias. Conductive material is formed directly above and directly against the conductive vias. The conductive material has an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section. The conductive material has a second sidewall that is not directly above the individual conductive vias. Covering material is formed directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias. The covering material comprises a composition different from that of at least some of the conductive material. Etching is conducted completely through at least some of the covering material that is directly above the individual upper surfaces to the conductive material directly there-below and etching is conducted into said conductive material. The covering material that is against the individual first sidewalls masks the individual first sidewalls from being etched during said etchings. Structure that may be independent of method is disclosed.

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Номер записи: 174

20-01-2022 дата публикации

Semiconductor structure and method of manufacturing same

Номер: US20220020751A1

Автор: Jia Fang, Zhongming Liu

Принадлежит: Changxin Memory Technologies Inc

The present application relates to a semiconductor structure and a method of manufacturing the same. The method includes: providing a substrate; forming a bitline contact hole located in the substrate, and a non-metal conductive layer with which a surface of the substrate is covered and the bitline contact hole is filled, the non-metal conductive layer provided with a first opening therein, the first opening aligned with the bitline contact hole; forming a metal conductive layer, with which a surface of the non-metal conductive layer is covered; forming an insulation layer, with which a surface of the metal conductive layer surface is covered; and etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form a bitline structure.

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Номер записи: 175

11-01-2018 дата публикации

Capacitor structures, decoupling structures and semiconductor devices including the same

Номер: US20180012955A1

Автор: Eun A Kim, Jong-Min Lee, Jongryul Jun, Jung-Bum Lim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

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Номер записи: 176

14-01-2021 дата публикации

Semiconductor device including capacitor

Номер: US20210013319A1

Автор: Hanjin Lim, Kyuho Cho, Sunmin Moon, Young-Lim Park

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.

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Номер записи: 177

19-01-2017 дата публикации

Methods of manufacturing semiconductor devices including isolation layers

Номер: US20170018453A1

Автор: Seok-Han Park

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a semiconductor device comprising the steps of: forming a trench at an upper portion of a semiconductor substrate forming a preliminary filling insulation layer by coating a siloxane composition on the semiconductor substrate to fill the trench performing a low temperature curing process at a temperature in a range from about 50° C. to about 150° C. such that the preliminary filling insulation layer is transformed into a filling insulation layer including polysiloxane and forming an isolation layer by planarizing the filling insulation layer.

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Номер записи: 178

03-02-2022 дата публикации

Semiconductor devices and methods of manufacturing the same

Номер: US20220037251A1

Автор: Dongjun Lee, Keunnam Kim, Sangoh PARK, Seunghune YANG

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

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Номер записи: 179

03-02-2022 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20220037335A1

Автор: Bong Hyun Kim, Dae Young Moon, Ja Min Koo, Jin Won MA, Kyu Wan Kim, Young Seok Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device includes a substrate including an element separation film and an active region defined by the element separation film, a bit line structure on the substrate, a trench in the element separation film and the active region, the trench on at least one side of the bit line structure and including a first portion in the element separation film and a second portion in the active region, a bottom face of the first portion placed above a bottom face of the second portion, a single crystal storage contact filling the trench, and an information storage element electrically connected to the single crystal storage contact.

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Номер записи: 180

16-01-2020 дата публикации

Semiconductor device with air gap and method for fabricating the same

Номер: US20200020697A1

Автор: Chan-bae Kim, Sang-Soo Park, Tae-Hyeok Lee

Принадлежит: SK hynix Inc

A method for fabricating a semiconductor device includes: forming a first conductive structure over a substrate; forming a multi-layer spacer including a non-conformal sacrificial spacer on both sidewalls of the first conductive structure; forming a second conductive structure adjacent to the first conductive structure with the multi-layer spacer therebetween; forming an air gap by removing the non-conformal sacrificial spacer; forming a capping layer covering the second conductive structure and the air gap; forming an opening that exposes a top surface of the second conductive structure by etching the capping layer; and forming a conductive pad coupled to the second conductive structure in the opening.

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Номер записи: 181

16-01-2020 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20200020780A1

Автор: Beom-Yong Kim

Принадлежит: SK hynix Inc

A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

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Номер записи: 182

21-01-2021 дата публикации

Semiconductor device including capacitor and method of forming the same

Номер: US20210020735A1

Автор: Cheol Seong Hwang, Han Jin Lim, Kyu Ho Cho, Sang Yeol Kang

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

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Номер записи: 183

23-01-2020 дата публикации

Semiconductor device

Номер: US20200027947A1

Автор: Byoungdeog Choi, Ha-Young YI, Hyukwoo KWON, Seongmin CHOO

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a substrate, a bottom electrode on the substrate, a first support layer on the substrate next to a sidewall of the bottom electrode, a dielectric layer covering the sidewall and a top surface of the bottom electrode, and a top electrode on the dielectric layer. The bottom electrode includes a first part having a plurality of protrusions that protrude from a sidewall of the first part. The first part of the bottom electrode may be on the first support layer.

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Номер записи: 184

17-02-2022 дата публикации

Semiconductor memory device and method of manufacturing the same

Номер: US20220052057A1

Автор: Bongsoo Kim, Hoju Song, Hyeran Lee, Jinhyung Park, Seokhyun Kim, Sungwoo KIM, Youngjun Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

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Номер записи: 185

01-05-2014 дата публикации

Capacitor of semiconductor device and method of fabricating the same

Номер: US20140120683A1

Автор: Dongkyun PARK, Hojun KWON, Hyongsoo Kim, Jin-Su Lee, Jiseung LEE, Young-Seok Choi

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes.

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Номер записи: 186

01-05-2014 дата публикации

Methods of Forming Capacitors

Номер: US20140120684A1

Автор: Gurpreet Lugani, Kevin J. Torek

Принадлежит: Micron Technology Inc

A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

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Номер записи: 187

30-01-2020 дата публикации

Insulating structure and method of forming the same

Номер: US20200035685A1

Автор: Li-Wei Feng

Принадлежит: Fujian Jinhua Integrated Circuit Co Ltd, United Microelectronics Corp

A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.

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Номер записи: 188

04-02-2021 дата публикации

Semiconductor memory device and method of manufacturing the same

Номер: US20210035983A1

Автор: Bongsoo Kim, Hoju Song, Hyeran Lee, Jinhyung Park, Seokhyun Kim, Sungwoo KIM, Youngjun Kim

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

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Номер записи: 189

11-02-2016 дата публикации

Non-volatile memory device employing a deep trench capacitor

Номер: US20160043088A1

Автор: DongHun Kang, Eduard A. Cartier, Herbert L. Ho

Принадлежит: International Business Machines Corp

A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

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Номер записи: 190

08-02-2018 дата публикации

Semiconductor memory device

Номер: US20180040561A1

Автор: Bong-Soo Kim, Daeik Kim, Eunjung Kim, Hui-jung Kim, Keunnam Kim, Yoosang Hwang

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

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Номер записи: 191

24-02-2022 дата публикации

Method for fabricating semiconductor device

Номер: US20220059448A1

Автор: Tse-Yao Huang

Принадлежит: Nanya Technology Corp

The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate comprising a central array area and a marginal array area surrounding the central array area; concurrently forming a first bit line above the central array area and a first dummy bit line above the marginal array area; and concurrently forming a second bit line above the central array area and a second dummy bit line above the marginal array area. The second bit line is higher than and offset from the first bit line and the second dummy bit line is directly above the first dummy bit line.

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Номер записи: 192

24-02-2022 дата публикации

Method of manufacturing semiconductor device

Номер: US20220059541A1

Автор: Chia-Lin Chang

Принадлежит: Nanya Technology Corp

A semiconductor includes a semiconductor substrate and pillar type capacitors. The semiconductor substrate includes first connecting pads and second connecting pads. The second connecting pads are disposed on the first connecting pads respectively, and the pillar type capacitors are disposed on the second connecting pads respectively. A first ends of the pillar type capacitors are connected to the second connecting pads respectively, and a second ends of the pillar type capacitors area at the opposite side of the first ends. The distance between the first end and the second end of each of the pillar type capacitors is from 1 micrometer to 1.8 micrometer. A manufacturing method is also provided.

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Номер записи: 193

07-02-2019 дата публикации

Semiconductor structure with capacitor landing pad and method of make the same

Номер: US20190043865A1

Автор: Chieh-Te Chen, Feng-Yi Chang, Fu-Che Lee, Yi-Ching Chang

Принадлежит: Fujian Jinhua Integrated Circuit Co Ltd, United Microelectronics Corp

The present invention discloses a semiconductor structure with capacitor landing pad and a method for fabricating a capacitor landing pad. The semiconductor structure with capacitor landing pad includes a substrate having a plurality of contact structures, a first dielectric layer disposed on the substrate and the contact structures, and a plurality of capacitor landing pads, each of the capacitor landing pads being located in the first dielectric layer and electrically connected to the contact structure, wherein the capacitor landing pads presents a shape of a wide top and a narrow bottom and a top surface of the capacitor landing pads have a concave shape.

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Номер записи: 194

06-02-2020 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20200043933A1

Автор: Dong-Su Park, Jae-Min Lee, Jeong-yeop Lee, Jong-Bum Park, Jun-Soo JANG, Kee-Jeung Lee, Sang-Do Lee

Принадлежит: SK hynix Inc

A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

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Номер записи: 195

06-02-2020 дата публикации

Semiconductor memory device

Номер: US20200043941A1

Автор: Hui-jung Kim, Keunnam Kim, Kiseok LEE, Yoosang Hwang

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device may include a stack structure that includes a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes that vertically extend to penetrate the stack structure. Each of the plurality of layers may include a plurality of semiconductor patterns that extend in parallel along a first direction, a bit line that is electrically connected to the semiconductor patterns and extends in a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element that is electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.

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Номер записи: 196

15-02-2018 дата публикации

Deep trench capacitors with a diffusion pad

Номер: US20180047807A1

Автор: Byeong Y. Kim, Herbert L. Ho, Joyce C. Liu

Принадлежит: Globalfoundries Inc

Device structures for a deep trench capacitor and methods of fabricating device structures for a deep trench capacitor. A dielectric layer is formed on a substrate and an opening is formed that extends from a top surface of the dielectric layer through the dielectric layer. A deep trench is formed in the substrate and is aligned with the opening in the dielectric layer. A plate of a deep trench capacitor is formed that is located at least partially inside the deep trench and at least partially inside the opening in the dielectric layer. A diffusion pad is formed that arranged at the top surface of the dielectric layer relative to the opening such that the diffusion pad is coupled with the plate of the deep trench capacitor.

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Номер записи: 197

26-02-2015 дата публикации

Multi-Material Structures, Semiconductor Constructions and Methods of Forming Capacitors

Номер: US20150054127A1

Автор: Duane M. Goodner, Joseph Neil Greeley, Prashant Raghu, Vassil N. Antonov, Vishwanath Bhat

Принадлежит: Micron Technology Inc

Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.

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Номер записи: 198

03-03-2022 дата публикации

Three-dimensional semiconductor memory device

Номер: US20220068859A1

Автор: Eun-ji Kim, Han-Sik Yoo, Hyoungyol MUN, Hyungeun CHOI, Jong-Ho Moon, Kiseok LEE, Sangyeon HAN, Seungjae Jung, Taehyun An, Yoosang Hwang

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.

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Номер записи: 199

03-03-2022 дата публикации

Channel formation for vertical three dimensional (3d) memory

Номер: US20220068927A1

Автор: Haitao Liu, Kamal M. Karda

Принадлежит: Micron Technology Inc

Systems, methods and apparatus are provided for depositing alternating layers of dielectric material and sacrificial material in repeating iterations to form a vertical stack, forming a plurality of vertical openings through the vertical stack to form elongated vertical, pillar columns with sidewalls in the vertical stack, patterning the pillar columns to expose a location to form a channel region, selectively removing a portion of the sacrificial material to form first horizontal openings in the first horizontal direction in the sidewalls of the elongated vertical, pillar columns, and depositing a channel material in the first horizontal openings to form the channel region within the sidewalls for the horizontally oriented access devices.

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Номер записи: 200