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Применить Всего найдено 10. Отображено 10.
28-09-2017 дата публикации

IONIC BARRIER FOR FLOATING GATE IN VIVO BIOSENSORS

Номер: US20170273608A1
Принадлежит:

An ion-sensitive sensor includes a dielectric layer comprising Al2O3 having a functionalized surface configured to bond with an analyte. The ion-sensitive sensor is immersed in an electrolytic solution containing a concentration of alkali ions. An electrode is arranged to apply an electric potential to the functionalized surface of the ion-sensitive sensor. In some embodiments the ion-sensitive sensor is an ion-sensitive silicon FET. In some embodiments the ion-sensitive sensor is an ion-sensitive polymer FET. In some embodiments, the electrode comprises a perforated gate metal layer disposed on the gate dielectric layer of an ion-sensitive FET, and the functionalized surface is disposed in openings of the perforated gate metal layer. In some embodiments the dielectric layer comprises a multi-layer dielectric stack including at least one Al2O3 layer. In some embodiments the dielectric layer is deposited by atomic layer deposition (ALD).

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11-05-2017 дата публикации

DEVICES AND METHODS FOR THE RAPID AND ACCURATE DETECTION OF ANALYTES

Номер: US20170131267A1
Принадлежит:

Disclosed are field effect transistor-based (FET-based) sensors for the rapid and accurate detection of analytes both in vivo and in vitro. The FET-based sensors can include a substrate, a channel disposed on the substrate, a source electrode and a drain electrode electrically connected to the channel, and a recognition element for an analyte of interest immobilized on the surface of the channel via a linking group. The distance between the recognition element and the channel can be configured such that association of the analyte of interest with the recognition element induces a change in the electrical properties of the channel. In this way, an analyte of interest can be detected by measuring a change in an electrical property of the channel. Also provided are devices, including probes and multi-well plates, incorporating the FET-based sensors. 1. A sensor comprising:a) a substrate:b) a channel disposed on the substrate, wherein the channel is substantially impermeable to ions under physiological conditions;c) a source electrode and a drain electrode electrically connected to the channel, wherein the source electrode and the drain electrode are formed to be separate such that the channel forms a path for current flow between the source electrode and the drain electrode; andd) a recognition element for an analyte of interest immobilized on the surface of the channel;wherein the distance between the recognition element and the channel is configured such that association of the analyte of interest with the recognition element induces a change in the electrical properties of the channel.2. The sensor of claim 1 , wherein the substrate is selected from the group consisting of Si claim 1 , SiC claim 1 , AlO claim 1 , Group III-nitrides claim 1 , ZnO claim 1 , MgZnO claim 1 , glass claim 1 , diamond claim 1 , and combinations thereof.3. The sensor of claim 2 , wherein the channel comprises a Group III-nitride heterojunction claim 2 ,wherein the Group III-nitride ...

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10-04-2018 дата публикации

Tunneling field effect transistors and transistor circuitry employing same

Номер: US0009941117B2

A p-channel tunneling field effect transistor (TFET) is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy. An n-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The n-channel TFET includes an n-type region, a p-type region with a p-type delta doping, and a channel region disposed between and spacing apart the n-type region and the p-type region. The p-channel TFET and the n-channel TFET may be electrically connected to define a complementary field-effect transistor element. TFETs may be fabricated from a silicon-germanium TFET layer structure grown by low temperature molecular beam epitaxy at a growth temperature at or below 500° C.

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09-08-2012 дата публикации

SILICON-BASED TUNNELING FIELD EFFECT TRANSISTORS AND TRANSISTOR CIRCUITRY EMPLOYING SAME

Номер: US20120199814A1
Автор: Berger Paul R.
Принадлежит: The Ohio State University

A p-channel tunneling field effect transistor (TFET) is selected from a group consisting of (i) a multi-layer structure of group IV layers and (u) a multi-layer structure of group III-V layers. The p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy. An n-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (u) a multi-layer structure of group III-V layers. The n-channel TFET includes an n-type region, a p-type region with a p-type delta doping, and a channel region disposed between and spacing apart the n-type region and the p-type region. The p-channel TFET and the n-channel TFET may be electrically connected to define a complementary field-effect transistor element. TFETs may be fabricated from a silicon-germanium TFET layer structure grown by low temperature (500 degrees Centigrade) molecular beam epitaxy. 1. An electronic device or circuit comprising:a p-channel tunneling field-effect transistor (p-channel TFET) selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers;wherein the p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy.2. The electronic device or circuit as set forth in claim 1 , wherein the p-channel TFET comprises a multi-layer structure of group III-V layers and includes a channel region comprising a ternary III-V alloy.3. The electronic device or circuit as set forth in claim 2 , wherein the p-channel TFET comprises a multi-layer structure of indium-gallium-arsenide III-V layers and includes a channel rcgion comprising a ternary InGaAs alloy.4. The electronic device or circuit as set forth in claim 1 , wherein the p-channcl TFET comprises a multi-layer structure of group IV layers and includes a channel region comprising a silicon- ...

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20-06-2013 дата публикации

IONIC BARRIER FOR FLOATING GATE IN VIVO BIOSENSORS

Номер: US20130158378A1
Принадлежит: The Ohio State University

An ion-sensitive sensor includes a dielectric layer comprising AlOhaving a functionalized surface configured to bond with an analyte. The ion-sensitive sensor is immersed in an electrolytic solution containing a concentration of alkali ions. An electrode is arranged to apply an electric potential to the functionalized surface of the ion-sensitive sensor. In some embodiments the ion-sensitive sensor is an ion-sensitive silicon FET. In some embodiments the ion-sensitive sensor is an ion-sensitive polymer FET. In some embodiments, the electrode comprises a perforated gate metal layer disposed on the gate dielectric layer of an ion-sensitive FET, and the functionalized surface is disposed in openings of the perforated gate metal layer. In some embodiments the dielectric layer comprises a multi-layer dielectric stack including at least one AlOlayer. In some embodiments the dielectric layer is deposited by atomic layer deposition (ALD). 1. A system comprising:{'sub': 2', '3, 'an ion-sensitive sensor that includes a dielectric layer including AlO;'}an electrolytic solution in which the ion-sensitive sensor is immersed, the electrolytic solution containing a concentration of alkali ions, a surface of the dielectric layer of the ion-sensitive sensor being in contact with the electrolytic solution; andan electrode arranged to apply an electric potential to the surface of the dielectric layer in contact with the electrolytic solution.2. The system of claim 1 , wherein the surface of the dielectric layer in contact with the electrolytic solution is a functionalized surface configured to bond with an analyte.3. The system of claim 2 , wherein the ion-sensitive sensor is an ion-sensitive silicon field effect transistor (FET) and the dielectric layer in contact with the electrolytic solution is the gate dielectric layer of the ion-sensitive silicon FET.4. The system of claim 3 , wherein the electrode comprises a perforated gate metal layer disposed on the gate dielectric layer of ...

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08-08-2013 дата публикации

DEVICES AND METHODS FOR THE RAPID AND ACCURATE DETECTION OF ANALYTES

Номер: US20130204107A1
Принадлежит: The Ohio State University

Disclosed are field effect transistor-based (FET-based) sensors for the rapid and accurate detection of analytes both in vivo and in vitro. The FET-based sensors can include a substrate, a channel disposed on the substrate, a source electrode and a drain electrode electrically connected to the channel, and a recognition element for an analyte of interest immobilized on the surface of the channel via a linking group. The distance between the recognition element and the channel can be configured such that association of the analyte of interest with the recognition element induces a change in the electrical properties of the channel. In this way, an analyte of interest can be detected by measuring a change in an electrical property of the channel. Also provided are devices, including probes and multi-well plates, incorporating the FET-based sensors. 1. A sensor comprising:a) a substrate;b) a channel disposed on the substrate, wherein the channel is substantially impermeable to ions under physiological conditions;c) a source electrode and a drain electrode electrically connected to the channel, wherein the source electrode and the drain electrode are formed to be separate such that the channel forms a path for current flow between the source electrode and the drain electrode; andd) a recognition element for an analyte of interest immobilized on the surface of the channel;wherein the distance between the recognition element and the channel is configured such that association of the analyte of interest with the recognition element induces a change in the electrical properties of the channel.2. The sensor of claim 1 , wherein the substrate is selected from the group consisting of Si claim 1 , SiC claim 1 , AlO claim 1 , Group III-nitrides claim 1 , ZnO claim 1 , MgZnO claim 1 , glass claim 1 , diamond claim 1 , and combinations thereof3. The sensor of claim 2 , wherein the channel comprises a Group III-nitride heterojunction claim 2 ,wherein the Group III-nitride ...

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24-01-2019 дата публикации

GALLIUM NITRIDE CROSS-GAP LIGHT EMITTERS BASED ON UNIPOLAR-DOPED TUNNELING STRUCTURES

Номер: US20190027644A1
Принадлежит: WRIGHT STATE UNIVERSITY

Gallium nitride based devices and, more particularly to the generation of holes in gallium nitride based devices lacking p-type doping, and their use in light emitting diodes and lasers, both edge emitting and vertical emitting. By tailoring the intrinsic design, a wide range of wavelengths can be emitted from near-infrared to mid ultraviolet, depending upon the design of the adjacent cross-gap recombination zone. The innovation also provides for novel circuits and unique applications, particularly for water sterilization. 1. A solid-state device , comprising:a bottom n-type layer;a top n-type layer;a middle layer inserted between the top layer and bottom layer, where the middle layer comprises at least two materials provided between the top and bottom layers which serve as heterojunction tunnel barriers;and where the top layer and the middle layer form an interband tunnel barrier to generate holes by Zener tunneling across the potential barrier of the forbidden energy gap, and where the middle layer forms at least one intraband tunnel barrier to control electron flow.2. The device of claim 1 , wherein the top claim 1 , middle and bottom layers are comprised of gallium nitride claim 1 , aluminum nitride claim 1 , indium nitride or alloys and combinations of III-nitride semiconductors or III-nitride compatible semiconductors.3. The device of claim 2 , wherein the heterojunction interband tunnel barrier is formed by the polarization effects at III-nitride heterojunctions.4. The device of claim 1 , wherein the middle layer forms at least two intraband tunnel barriers claim 1 , wherein the at least two intraband tunnel barriers form a quantum well within the middle layer.5. The device of claim 1 , wherein the middle layer forms at least two intraband tunnel barriers claim 1 , wherein the at least two intraband tunnel barriers form a double barrier resonant tunneling diode.6. The device of claim 1 , wherein the middle layer is either undoped or doped less than the top ...

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24-03-2016 дата публикации

TUNNELING FIELD EFFECT TRANSISTORS AND TRANSISTOR CIRCUITRY EMPLOYING SAME

Номер: US20160086800A1
Автор: Berger Paul R.
Принадлежит:

A p-channel tunneling field effect transistor (TFET) is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The p-channel TFET includes a channel region comprising one of a silicon-germanium alloy with non-zero germanium content and a ternary III-V alloy. An n-channel TFET is selected from a group consisting of (i) a multi-layer structure of group IV layers and (ii) a multi-layer structure of group III-V layers. The n-channel TFET includes an n-type region, a p-type region with a p-type delta doping, and a channel region disposed between and spacing apart the n-type region and the p-type region. The p-channel TFET and the n-channel TFET may be electrically connected to define a complementary field-effect transistor element. TFETs may be fabricated from a silicon-germanium TFET layer structure grown by low temperature molecular beam epitaxy at a growth temperature at or below 500° C. 1. A method for fabricating a tunneling field-effect transistor (TFET) , the method comprising:growing a silicon-germanium TFET layer structure by LT-MBE at a growth temperature at or below 500° C.; andprocessing the silicon-germanium TFET layer structure to form a TFET device.2. The method as set forth in claim 1 , wherein the growing is at a growth temperature at or below 400° C.3. The method as set forth in claim 1 , wherein the method further comprises:annealing the silicon-germanium TFET layer structure at a temperature of at least 600° C.;wherein the processing to form a TFET device is performed before or after the annealing.4. The method as set forth in claim 3 , wherein the annealing is at a temperature of at least 800° C. This application is a divisional of U.S. Ser. No. 13/496,542 filed Apr. 20, 2012 which is a national stage entry of PCT/US10/48610 filed Sep. 13, 2010 which claims the benefit of U.S. Provisional Application No. 61/243,368 filed Sep. 17, 2009 naming inventor Paul R. Berger ...

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10-03-2020 дата публикации

Devices and methods for the rapid and accurate detection of analytes

Номер: US10585092B2
Принадлежит: Ohio State Innovation Foundation

Disclosed are field effect transistor-based (FET-based) sensors for the rapid and accurate detection of analytes both in vivo and in vitro. The FET-based sensors can include a substrate, a channel disposed on the substrate, a source electrode and a drain electrode electrically connected to the channel, and a recognition element for an analyte of interest immobilized on the surface of the channel via a linking group. The distance between the recognition element and the channel can be configured such that association of the analyte of interest with the recognition element induces a change in the electrical properties of the channel. In this way, an analyte of interest can be detected by measuring a change in an electrical property of the channel. Also provided are devices, including probes and multi-well plates, incorporating the FET-based sensors.

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04-12-2007 дата публикации

Method of making interband tunneling diodes

Номер: US7303969B2
Принадлежит: Ohio State University

Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.

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