Package substrate and semiconductor package including the same

Disclosed are package substrates and semiconductor packages including the same. A package substrate may have a plurality of corner regions; a core layer having a first surface and a second surface; an upper layer, which includes a plurality of first wiring structures and a plurality of first dielectric layers; and a lower layer, which includes a plurality of second wiring structures and a plurality of second dielectric layers. Additionally, an area proportion of top surfaces of the first wiring structures in the upper layer relative to a top surface of the upper layer on each of the corner regions is less than an area proportion of top surfaces of the second wiring structures in the lower layer relative to a top surface of the lower layer on each of the corner regions.

Single-signal receiver including active inductor continuous time linear equalizer and reference voltage selection equalizer, and method for operating the same

A single-signal receiver including an active inductor continuous time linear equalizer and a reference voltage selection equalizer is provided. The single-signal receiver includes a continuous time linear equalizing unit to receive a single signal, and compensate for distortion of the single signal to generate an output, and a reference voltage selection equalizing unit to select one of a first reference voltage value and a second reference voltage value based on a previous output from a comparator, and sample the output from the continuous time linear equalizing unit, based on the one of the first reference voltage value and the second reference voltage value.

CMOS skewed static logic and method of synthesis

A new CMOS skewed static logic gate is provided having a logic function circuit and a positive feedback or accelerator circuit. The skewed gate uses a plurality of transistors matched and joined as a plurality of separate gate inputs to form the logic function circuit and the accelerator circuit. The accelerator circuit, which connects to an output of the logic function circuit, provides acceleration to the evaluation performed by the logic function circuit. The logic function circuit includes an evaluation path connected to a set of output transistors that connect to transistors of the accelerator circuit. The evaluation path includes a stacked set of low threshold voltage (V t ) transistors, which have a lower V t than the set of output transistors. The output transistors are configured to receive a first input signal to precharge an output of the CMOS skewed static logic gate prior to the skewed gate receiving a second input signal.

Apparatus and method for measurement of temperature using oscillators

A temperature sensor includes: a first oscillator that generates a first frequency signal; a second oscillator that generates a second frequency signal; a multiplexer that selectively passes the first frequency signal and the second frequency signal; and a frequency-to-digital converter that converts a frequency difference between the first frequency signal and the second frequency signal into a digital code.

HYBRID SUBSTRATES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS FOR FABRICATING SEMICONDUCTOR PACKAGES

Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.

Semiconductor package

A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, and a plurality of underfills between the package substrate and the semiconductor chip. The package substrate includes a trench formed in the package substrate and a plurality of dams on both sides of the trench, respectively. The top surfaces of the plurality of dams may be positioned at a lower level than the bottom surface of the semiconductor chip in a cross-sectional view of the semiconductor package with the package substrate providing a base reference level.

Semiconductor package including a substrate having two silicon layers formed on each other

A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

CMOS sequential logic configuration for an edge triggered flip-flop

A CMOS sequential logic circuit for an edge triggered flip-flop to lower power consumption in very large scale integrated (VLSI) circuit designs is disclosed. The circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a data-sampling front end and a data-transferring back end to provide an output based on an input signal fed to a pair of transistor gates. Outputs from the pair of transistor gates charge and discharge internal nodes which connect the data-sampling front end to the data-transferring back end. The internal nodes also include a first latch that connects to a first internal node, and a second latch that connects to a second internal node. The latches prevent a floating voltage state for each of the first and second internal nodes and reduce power consumption during flip-flop transitions.

Transceiver using multi-level braid signaling and method of operating the same

A transceiver includes a transmitter modulating a data signal into code information in a modulation section unit and individually supplying a common mode current to a plurality of transmission lines and a receiver detecting the code information according to a voltage level of each of the transmission lines and outputting the data signal.

DLL-based multiphase clock generator

The present invention relates to a delay-locked loop-based multiphase clock generator that generates a plurality of multiphase clocks from an input clock signal using a voltage controlled delay line including a plurality of dummy cells. The delay-locked loop-based multiphase clock generator includes an anti-harmonic lock circuit that receives an input clock and a reference clock of multiple clocks, determines whether a pulse signal derived from the input clock is within a normal locking range of the reference clock, and outputs a compulsory control signal to compulsorily control an output signal of a phase detector if it is determined that the pulse signal is not within the normal locking range.

Tape wiring substrates and packages including the same

Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, the chip mounting area further including an inner area and a peripheral area, the film further including a lower surface, and vias penetrating the film, the vias being located in the inner area, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film. Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, a lower surface, and vias penetrating the film, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film, the vias being located outside of the chip mounting area. Example embodiments are directed to packages including tape wiring substrates.

Semiconductor package with thermal interface material for improving package reliability

A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

CMOS skewed static logic and method of synthesis

A new CMOS skewed static logic gate is provided having a logic function circuit and a positive feedback or accelerator circuit. The skewed gate uses a plurality of transistors matched and joined as a plurality of separate gate inputs to form the logic function circuit and the accelerator circuit. The accelerator circuit, which connects to an output of the logic function circuit, provides acceleration to the evaluation performed by the logic function circuit. The logic function circuit includes an evaluation path connected to a set of output transistors that connect to transistors of the accelerator circuit. The evaluation path includes a stacked set of low threshold voltage (Vt) transistors, which have a lower Vt than the set of output transistors. The output transistors are configured to receive a first input signal to precharge an output of the CMOS skewed static logic gate prior to the skewed gate receiving a second input signal.

Signal receiver and operation method thereof

A signal receiver includes a data sampler receiving a differential input signal having first and second input signals and determining bit values of the differential input signal based on first and second reference voltages, and a reference voltage generator performing a pre-tuning operation and a post-tuning operation to generate the reference voltages. The reference voltage generator performs the pre-tuning operation by generating first and second initial voltages and adjusting one of the initial voltages to generate third and fourth voltages. After the pre-tuning operation, the reference voltage generator performs the post-tuning operation by increasing or decreasing the third voltage to generate the first reference voltage and decreasing or increasing the fourth voltage to generate the second reference voltage based on a comparison result between the third voltage and the first input signal and a second comparison result between the fourth voltage and second input signal.

Transmitter, receiver and system including the same

A system includes a transmitter including: an aligner configured to align the phases of an input clock signal and data signal; and a transmission circuit configured to generate a transmission signal of which the phase and amplitude are controlled according to the aligned clock signal and the aligned data signal. The system may also include a receiver including: a clock extraction circuit configured to extract a temporary clock signal from the transmission signal; a data extraction circuit configured to extract a temporary data signal from the transmission signal; a clock delay selector configured to generate the clock signal by delaying the temporary clock signal according to a value of the temporary data signal; and a data recovery circuit configured to sample the temporary data signal according to the clock signal outputted from the clock delay selector and output a data signal.

Differential signal processing device using advanced braid clock signaling

A differential signal processing device is described which includes an encoder configured to encode input data into one or more differential signals and a transmitter configured to sequentially transmit the one or more differential signals using a plurality of transmission lines. The encoder converts a plurality of bits, corresponding to a transmission time interval, among the input data into an encoding code array in the transmission time interval obtained by increasing an encoding unit time, encoded for each of the one or more differential signals, by an integer multiple.

Touch sensor with modular shape and display device including the same

A display device includes a first touch panel on which a first touch sensing unit including a plurality of coils is disposed, a second touch panel on which a second touch sensing unit including a plurality of sensing nodes coupled to the plurality of coils in a coupling manner with a one-to-one correspondence, and a display panel disposed between the first and second touch panels and displays an image, and the plurality of sensing nodes is formed in a divided structure grouped into first and second node groups based on a touch event detected by the first touch sensing unit.

Delay locked loop clock generator

A delay locked loop (DLL) clock generator circuit is provided for generating a clock signal Clk according to a pair of input signals to the circuit. One of the input signals is a reference signal, and the second input signal is a feedback signal of a voltage controlled delay line circuit. The DLL circuit includes a phase detector that can be reset to expand the locking range for detecting a phase difference between the reference signal and the feedback signal. Based on the detected phase difference, the phase detector provides an output signal that is further processed by the DLL circuit to generate a number of delayed signals to a frequency multiplier. Using the delayed signals, the frequency multiplier generates a frequency multiplied clock signal having a frequency that is a multiple of the frequency of the reference signal.

Impedance-controlled pseudo-open drain output driver circuit and method for driving the same

An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

Apparatus for dispensing droplet and method for dispensing droplet

An apparatus for dispensing droplet may include a droplet discharging member, a stage and a control member. The droplet discharging member may include a plurality of nozzles arranged in a first direction by a constant interval. The stage may receive a substrate including a plurality of regions for forming a plurality of pixels of a same size disposed in the first direction and a second direction substantially perpendicular to the first direction. The control member may control the droplet discharging member such that amounts of droplets may be substantially identical in the regions of the substrate for the pixels if the numbers of the nozzles of the droplet discharging member with respect to sides of the regions of the substrate for the pixels are different in the first direction. The control member may identify patterns of discharged droplets in the regions of the substrate for the pixels and adjusts the amounts of the droplets form the nozzles of the droplet discharging member by controlling operation of each of nozzles of the droplet discharging member.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, and a plurality of underfills between the package substrate and the semiconductor chip. The package substrate includes a trench formed in the package substrate and a plurality of dams on both sides of the trench, respectively. The top surfaces of the plurality of dams may be positioned at a lower level than the bottom surface of the semiconductor chip in a cross-sectional view of the semiconductor package with the package substrate providing a base reference level.

Electronic device for identifying touch position, touch system including electronic device, and operation method thereof

Disclosed is electronic device for identifying touch position, touch system including electronic device, and operation method thereof.

Pulse amplitude modulation-3 transceiver and operation method thereof

According to an embodiment of the inventive concept, a device for PAM-3 signaling includes an encoder selecting one of first to ninth transitions in first and second unit intervals that are successive and mapping data of three bits by using a remaining eight transitions other than the one selected among the first to ninth transitions, and an output driver receiving an output signal of the encoder via an input and generating a multi-level signal having an output voltage of first to third levels. The data of three bits is transmitted to a receiver terminal through the multi-level signal having the output voltage of the first to third levels during the first and second unit intervals that are successive. The device for PAM-3 signaling according to an embodiment of the inventive concept may transmit three bits during two unit intervals and may allow a receiver terminal to detect a windowing phenomenon.

Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages

Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.

Duty cycle correction circuit including a reference clock generator

A duty cycle correction circuit includes a first duty cycle detecting circuit configured to detect a duty cycle of a clock signal with a first resolution; a reference clock generating circuit configured to generate a reference clock signal by adjusting a phase of the clock signal; a second duty cycle detecting circuit configured to detect a duty cycle of the clock signal with a second resolution according to the reference clock signal and the clock signal, the second resolution being finer than the first resolution; a first duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more first control signals output from the first duty cycle detecting circuit; and a second duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more second control signals output from the second duty cycle detecting circuit.

Open-loop slew-rate controlled output driver

A slew-rate controlled output driver for use in a semiconductor device includes a PVT variation detection unit having a delay line for receiving a reference clock in order to detect a delay amount variation of the delay line determined according to process, voltage and temperature (PVT) variation; a selection signal generation unit for generating a driving selection signal which corresponds to a detection signal generated by the PVT variation detection unit; and an output driving unit having a plurality of driver units controlled by an output data and the driving selection signal for driving an output terminal with a driving strength which corresponds to the PVT variation.

SEMICONDUCTOR PACKAGE FOR IMPROVING PACKAGE RELIABILITY

A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

DLL-Based Multiplase Clock Generator

The present invention relates to a delay-locked loop-based multiphase clock generator that generates a plurality of multiphase clocks from an input clock signal using a voltage controlled delay line including a plurality of dummy cells. The delay-locked loop-based multiphase clock generator includes an anti-harmonic lock circuit that receives an input clock and a reference clock of multiple clocks, determines whether a pulse signal derived from the input clock is within a normal locking range of the reference clock, and outputs a compulsory control signal to compulsorily control an output signal of a phase detector if it is determined that the pulse signal is not within the normal locking range.

Capacitively coupled continuous-time delta-sigma modulator and operation method thereof

According to an exemplary embodiment, a capacitively coupled continuous-time delta-sigma modulator includes an instrumentation amplifier amplifying an input voltage to an output voltage of a predetermined magnitude, a delta-sigma modulator outputting a bit signal quantized depending on a sampling frequency based on the output voltage and to convert the bit signal into a digital-to-analog conversion voltage, and a ripple reduction loop unit generating a demodulation voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency to feed the demodulation voltage back to the instrumentation amplifier. The RRL operating frequency is equal to the sampling frequency.

Semiconductor package and method of fabricating the same

A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

Apparatus for discharging chemical liquid and method of discharging chemical liquid

An apparatus for discharging chemical liquid may include an ink jet head, a gantry and a control member. The ink jet head may include a plurality of nozzles capable of discharging chemical liquid onto a substrate. The gantry may hold the ink jet head to place the ink jet head over the substrate. The control member may control the ink jet head such that discharge times of the chemical liquid from the nozzles of the ink jet head may be changed.

Method and electronic device for playing audio data using dual speaker

An electronic device, method, and non-transitory computer-readable recording medium are provided. Electronic device includes first speaker and second speaker arranged in electronic device, processor operatively connected with first speaker and second speaker, and memory operatively connected to the processor, wherein the memory is configured to store instructions executed to enable the processor to detect an orientation or attitude of the electronic device while playing first channel audio data and second channel audio data via the first speaker and the second speaker, and based on at least part of the detected orientation or attitude of the electronic device, keep outputting a first frequency component of the first channel audio data and a second frequency component of the second channel audio data via the first speaker and the second speaker and switch a second frequency component of the first channel audio data and a first frequency component of the second channel audio data.

TAPE WIRING SUBSTRATES AND PACKAGES INCLUDING THE SAME

Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, the chip mounting area further including an inner area and a peripheral area, the film further including a lower surface, and vias penetrating the film, the vias being located in the inner area, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film. Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, a lower surface, and vias penetrating the film, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film, the vias being located outside of the chip mounting area. Example embodiments are directed to packages including tape wiring substrates.

Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages

Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.

Method and apparatus for determining search range for adaptive motion vector for use in video encoder

The video encoder in accordance with the present invention divides input image signal into macro blocks, estimates motion vectors of each macro block and finally encodes the input image signal. The encoder determines the number of macro blocks adjacent to a current macro block. If the number of adjacent macro blocks is equal to or more than two, the encoder calculates a motion vector of the adjacent macro blocks and selects a macro block that has the largest motion vector. Then it defines a least search area that the current adaptive motion vector can have, and compares the least search area with the motion vector of the largest adjacent macro block, and finally determines the largest value as the search area of the adaptive motion vector. Next, the encoder compares the search area of the adaptive motion vector with the search area of the user-defined motion adaptive vector to thereby determine the least value as the search area of the final adaptive motion vector.

Thermometer code generator, and frequency-locked loop including the same

A thermometer code generator includes n bit storing stages that are coupled to each other, where n is an integer greater than 1, and the n bit storing stages store a thermometer code, and are adapted to increase the stored thermometer code by 1 in synchronization with a clock signal when an up signal is active, to decrease the stored thermometer code by 1 in synchronization with the clock signal when a down signal is active, and to maintain the stored thermometer code in synchronization with the clock signal when both of the up signal and the down signal are inactive.

Circuit and related method for synchronizing data signals to a core clock

The present invention discloses, in one aspect, a synchronizing circuit for synchronizing transmitted data. In one embodiment, the synchronization technique comprises a subsystem configured to compare positive and negative transitions of a core clock signal with positive and negative transitions of a source clock signal to determine a relationship between the transitions of the core clock signal and positions of the negative transitions of the source clock signal. The synchronization circuit also comprises logic circuitry coupled to the subsystem and configured to generate a final sampling signal based on the relationship. In addition, the synchronization circuit comprises a data sampler coupled to the logic circuitry and configured to sample a source data signal synchronized with the source clock signal using the final sampling signal, and to generate a core data signal synchronized with the core clock signal based on the sampling. Also disclosed is a method of synchronizing a data stream, and a data transfer assembly incorporating the synchronization circuit and the method.

APPARATUS AND METHOD FOR CLOCK GENERATION WITH PIECEWISE LINEAR MODULATION

An apparatus and method for generating a clock using piecewise linear modulation are provided. The apparatus includes: a modulation profile generator for outputting an M-bit digital profile obtained by quantizing a piecewise linear modulation profile consisting of two or more linear signals; a delta-sigma modulator for receiving the M-bit digital profile and outputting a K-bit profile obtained by delta-sigma modulating the M-bit digital profile, K being a smaller number than M; a phase-frequency comparator for outputting up and down pulses having the same phase difference as that between a reference clock and a feedback clock; a charge pump for outputting a predetermined current for a time corresponding to the phase difference between the up and down pulses; a loop filter for outputting a control voltage corresponding to the predetermined current; a voltage controlled oscillator (VCO) for outputting a multi-phase clock having a frequency corresponding to a level of the control voltage; ...

Impedance-controlled pseudo-open drain output driver circuit and method for driving the same

An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

Thermometer code generator, and frequency-locked loop including the same

A thermometer code generator includes n bit storing stages that are coupled to each other, where n is an integer greater than 1, and the n bit storing stages store a thermometer code, and are adapted to increase the stored thermometer code by 1 in synchronization with a clock signal when an up signal is active, to decrease the stored thermometer code by 1 in synchronization with the clock signal when a down signal is active, and to maintain the stored thermometer code in synchronization with the clock signal when both of the up signal and the down signal are inactive.

Charge pumping apparatus for low voltage and high efficiency operation

A charge pump (CP) that operates at low input voltage with high power conversion efficiency is disclosed. A first embodiment provides a negative CP used for controlling load switches of a voltage doubler. Using a negative CP extends the operating region below ground to relieve the power delivery limitation of the CP. A second embodiment provides a low power adaptive dead-time circuit, which has several dead-time signals having different lengths of dead-times and selects one according to the input voltage level. A low input voltage detector in the adaptive dead-time circuit is used to determine which dead-time should be used. A third embodiment provides a switching body bias used for the low input voltage CP. The switching body bias uses both forward and reverse body bias applied to the CP to minimize reverse current and maximize power transfer. The first, second, and third embodiments can be used together or independently.

Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages

Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.

CMOS parallel dynamic logic and speed enhanced skewed state logic

A new CMOS dynamic logic family is based on parallel dynamic logic concept, avoiding stacked evaluation transistors. The basic configuration for the logic family is a pair of clock transistors including a NMOS and a PMOS transistor having parallel logic transistors connected between the NMOS and PMOS clock transistors. The parallel-connected transistors have gates for logic inputs and an output originating from one of a commonly connected source or drain. The family may provide NOR, NAND, OR, and AND. The family also includes BUF and INV. The BUF logic gate is realized with opposing NMOS and PMOS and an INV, while the INV uses either a single NMOS or PMOS transistor in place of the parallel-connected transistors. A speed enhanced skewed static logic gate is also provided. The speed enhanced gate uses a plurality of PMOS transistors and a plurality of NMOS transistors matched and joined as a plurality of separate gate inputs. An output from the gate is provided, and the size of PMOS and NMOS transistors are skewed. Positive feedback transistors are connected to the output. A noise suppression transistor is also connected to the output. A precharge transistor connected to the positive feedback transistors is fed from a clock signal from an associated circuit. The speed enhanced skewed state logic gate is preferably used to solve cascading problems, such as those in CD domino or the present parallel dynamic logic, and the speed enhanced static gates may be used instead of clock delay.

Apparatus and method for clock generation with piecewise linear modulation

An apparatus and method for generating a clock using piecewise linear modulation are provided. The apparatus includes: a modulation profile generator for outputting an M-bit digital profile obtained by quantizing a piecewise linear modulation profile consisting of two or more linear signals; a delta-sigma modulator for receiving the M-bit digital profile and outputting a K-bit profile obtained by delta-sigma modulating the M-bit digital profile, K being a smaller number than M; a phase-frequency comparator for outputting up and down pulses having the same phase difference as that between a reference clock and a feedback clock; a charge pump for outputting a predetermined current for a time corresponding to the phase difference between the up and down pulses; a loop filter for outputting a control voltage corresponding to the predetermined current; a voltage controlled oscillator (VCO) for outputting a multi-phase clock having a frequency corresponding to a level of the control voltage; ...

APPARATUS AND METHOD FOR MEASUREMENT OF TEMPERATURE USING OSCILLATORS

A temperature sensor includes: a first oscillator that generates a first frequency signal; a second oscillator that generates a second frequency signal; a multiplexer that selectively passes the first frequency signal and the second frequency signal; and a frequency-to-digital converter that converts a frequency difference between the first frequency signal and the second frequency signal into a digital code.

SEMICONDUCTOR PACKAGES

A semiconductor package includes a substrate including a wiring, a semiconductor chip structure on the substrate, and electrically connected to the wiring, an underfill resin in a space between the substrate and the semiconductor chip structure, and a stiffener surrounding the semiconductor chip structure, on the substrate, wherein the stiffener includes a conductive frame having a cavity and an insulating filler in the cavity.

Semiconductor package and method of manufacturing semiconductor package

A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions.

Successive approximated register analog-to-digital converter and conversion method thereof

A Successive Approximated Register Analog-to-Digital Converter (“SARADC”) is provided that includes: a bootstrapping unit that receives and samples analog signals; and an Analog-to-Digital Conversion Unit (“ADCU”) that converts the analog signals into digital signals and outputs the digital signals. ADCU has a resolution increasing in response to an intentionally injected offset voltage. In this case, ADCU includes Capacitor Arrays (“CAs”) having: a differential structure each including reference voltage application capacitors having different capacitances and an Offset Voltage Injection Capacitor (“OVIC”); a delay cell that operates CAs in an asynchronous mode; Reference Transfer Switch Units (“RTSUs”) that apply a reference voltage to CAs; a comparator that compares output voltages of CAs; and Successive Approximated Register Logics (“SARLs”). SARLs control operations of RTSUs in response to an output signal of the comparator and perform control so that a reference voltage is applied to OVICs when the output of the comparator is abnormal.

Data transmitting and receiving device

A transmitter and a receiver are provided. The transmitter includes a processing unit configured to receive a clock signal and a data signal, set a value of a consecutive identical digit (CID) value related to the data signal and generate a modulation signal during a unit interval (UI) based on the data signal and the CID value, and a transmitter driver configured to output output signals having different voltage levels during the unit interval by receiving the modulation signal.

Open-loop slew-rate controlled output driver

A slew-rate controlled output driver for use in a semiconductor device includes a PVT variation detection unit having a delay line for receiving a reference clock in order to detect a delay amount variation of the delay line determined according to process, voltage and temperature (PVT) variation; a selection signal generation unit for generating a driving selection signal which corresponds to a detection signal generated by the PVT variation detection unit; and an output driving unit having a plurality of driver units controlled by an output data and the driving selection signal for driving an output terminal with a driving strength which corresponds to the PVT variation.

Semiconductor package with heat dissipation member

A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.

Continuous-time delta-sigma modulator

A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.

Electronic device for inputting characters and method of operation of same

Various embodiments of the present invention relate to an electronic device for inputting characters and a method of operation of same. At this time, the electronic device comprises a display, at least one processor, and a memory operatively connected to the processor, wherein the memory may store instructions that, when executed, cause the at least one processor to: detect at least one input word; determine a priority of a plurality of categories for a content on the basis of the at least one input word; determine at least one recommendation category on the basis of the determined priority of the plurality of categories; and control the display so as to display at least one content corresponding to the at least one determined recommendation category as at least one recommendation content for the at least one input word. Other embodiments may also be possible.

Circuit and related method for synchronizing data signals to a core clock

The present invention discloses, in one aspect, a synchronizing circuit for synchronizing transmitted data. In one embodiment, the synchronization technique comprises a subsystem configured to compare positive and negative transitions of a core clock signal with positive and negative transitions of a source clock signal to determine a relationship between the transitions of the core clock signal and positions of the negative transitions of the source clock signal. The synchronization circuit also comprises logic circuitry coupled to the subsystem and configured to generate a final sampling signal based on the relationship. In addition, the synchronization circuit comprises a data sampler coupled to the logic circuitry and configured to sample a source data signal synchronized with the source clock signal using the final sampling signal, and to generate a core data signal synchronized with the core clock signal based on the sampling. Also disclosed is a method of synchronizing a data stream ...

Apparatus and system for tracking data speed automatically

An apparatus and a system for automatically tracking data speed are disclosed. An embodiment of the invention provides a transmitting apparatus for automatically tracking data speed that includes: an encoder configured to convert parallelized input data according to a preset signal rule into a first signal and a second signal, where the input data is inputted as a unit of n bits, the encoder outputs the first signal and the second signal such that, if the input data includes identical bit values consecutively, one of the first signal and the second signal is converted to include transition information instead of following a differential rule with respect to the other signal; a serializer configured to serialize the first signal and the second signal; and a transmitting part configured to transmit the serialized first signal and second signal.

Electronic device including capacitive sensor driven by stylus excited by magnetic field, touch system including the same, and operating method thereof

Disclosed is an electronic device, which includes a plurality of driving coils that are sequentially arranged in a first direction in a plan view, a plurality of sensing electrodes that are spaced and insulated from the plurality of driving coils and are sequentially arranged in a second direction orthogonal or pseudo-orthogonal to the first direction in a plan view, and a processor that is electrically connected with the plurality of driving coils and the plurality of sensing electrodes. At least one of the plurality of sensing electrodes is electrically coupled with a stylus excited by a magnetic field generated by the plurality of driving coils. The processor applies a driving signal to the plurality of driving coils, receives a response signal to the driving signal from the plurality of sensing electrodes, and identifies a contact location of the stylus based on the response signal.

Delay locked loop clock generator

A delay locked loop (DLL) clock generator circuit is provided for generating a clock signal Clk according to a pair of input signals to the circuit. One of the input signals is a reference signal, and the second input signal is a feedback signal of a voltage controlled delay line circuit. The DLL circuit includes a phase detector that can be reset to expand the locking range for detecting a phase difference between the reference signal and the feedback signal. Based on the detected phase difference, the phase detector provides an output signal that is further processed by the DLL circuit to generate a number of delayed signals to a frequency multiplier. Using the delayed signals, the frequency multiplier generates a frequency multiplied clock signal having a frequency that is a multiple of the frequency of the reference signal.

Serial transceiver and communication method used by the serial transceiver

A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.

Hierarchical time to digital converter

A time to digital converter having a hierarchical structure is provided. The time to digital converter includes: a plurality of delay stages for sequentially delaying a first signal for a specific delay time; a plurality of flip-flops for comparing delay signals of the first signal delayed by the delay stages with a second signal, and generating different outputs before and after a phase difference between the delay signals of the first signal and the second signal becomes smaller than a resolution of the phase detector; a selection signal generator for generating a selection signal for selecting a signal most similar to the second signal among the delay signals of the first signal from the outputs of the flip-flops; and a Multiplexer (MUX) for receiving the delay signals of the first signal and the selection signal, and outputting the signal most similar to the second signal among the delay signals of the first signal.

TRANSMITTER, RECEIVER AND SYSTEM INCLUDING THE SAME

A system includes a transmitter including: an aligner configured to align the phases of an input clock signal and data signal; and a transmission circuit configured to generate a transmission signal of which the phase and amplitude are controlled according to the aligned clock signal and the aligned data signal. The system may also include a receiver including: a clock extraction circuit configured to extract a temporary clock signal from the transmission signal; a data extraction circuit configured to extract a temporary data signal from the transmission signal; a clock delay selector configured to generate the clock signal by delaying the temporary clock signal according to a value of the temporary data signal; and a data recovery circuit configured to sample the temporary data signal according to the clock signal outputted from the clock delay selector and output a data signal. 1. A transmitter comprising:an aligner configured to align a phase of an input clock signal and a phase of a data signal and output an aligned clock signal and an aligned data signal; anda transmission circuit configured to generate a transmission signal, wherein a phase of the transmission signal is controlled according to the aligned clock signal and an amplitude of the transmission signal is controlled according to the aligned data signal.2. The transmitter of claim 1 , wherein the transmission circuit comprises:a first driver configured to generate the transmission signal using the aligned clock signal;a second driver configured to control the amplitude of the transmission signal according to the aligned data signal; anda third driver configured to control a swing timing of the transmission signal according to the aligned data signal.3. The transmitter of claim 2 , wherein:when the aligned data signal has a first value, the second driver controls the transmission signal such that the amplitude of the transmission signal becomes a first level, andwhen the aligned data signal has a ...

CMOS sequential logic configuration for an edge triggered flip-flop

A CMOS sequential logic circuit for an edge triggered flip-flop to lower power consumption in very large scale integrated (VLSI) circuit designs is disclosed. The circuit includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS and NMOS transistors are matched and joined as a data-sampling front end and a data-transferring back end to provide an output based on an input signal fed to a pair of transistor gates. Outputs from the pair of transistor gates charge and discharge internal nodes which connect the data-sampling front end to the data-transferring back end. The internal nodes also include a first latch that connects to a first internal node, and a second latch that connects to a second internal node. The latches prevent a floating voltage state for each of the first and second internal nodes and reduce power consumption during flip-flop transitions.

APPARATUS FOR DISPENSING DROPLET AND METHOD FOR DISPENSING DROPLET

An apparatus for dispensing droplet may include a droplet discharging member, a stage and a control member. The droplet discharging member may include a plurality of nozzles arranged in a first direction by a constant interval. The stage may receive a substrate including a plurality of regions for forming a plurality of pixels of a same size disposed in the first direction and a second direction substantially perpendicular to the first direction. The control member may control the droplet discharging member such that amounts of droplets may be substantially identical in the regions of the substrate for the pixels if the numbers of the nozzles of the droplet discharging member with respect to sides of the regions of the substrate for the pixels are different in the first direction. The control member may identify patterns of discharged droplets in the regions of the substrate for the pixels and adjusts the amounts of the droplets form the nozzles of the droplet discharging member by controlling operation of each of nozzles of the droplet discharging member.

CMOS parallel dynamic logic and speed enhanced static logic

A new CMOS dynamic logic family is based on parallel dynamic logic concept, avoiding stacked evaluation transistors. The basic configuration for the logic family is a pair of clock transistors including a NMOS and a PMOS transistor having parallel logic transistors connected between the NMOS and PMOS clock transistors. The parallel-connected transistors have gates for logic inputs and an output originating from one of a commonly connected source or drain. The family may provide NOR, NAND, OR, and AND. The family also includes BUF and INV. The BUF logic gate is realized with opposing NMOS and PMOS and an INV, while the INV uses either a single NMOS or PMOS transistor in place of the parallel-connected transistors. A speed enhanced skewed static logic gate is also provided. The speed enhanced gate uses a plurality of PMOS transistors and a plurality of NMOS transistors matched and joined as a plurality of separate gate inputs. An output from the gate is provided, and the size of PMOS and ...

Method of maintaining an ink jet head and printing method using an ink jet head

In a printing method using an ink jet head, a chemical liquid may be discharged onto a substrate from a plurality of nozzles of the ink jet head. Discharging numbers of the chemical liquid from the plurality of nozzles may be identified and a cumulative discharging number of the chemical liquid from the plurality of nozzles may be calculated. The cumulative discharging number of the chemical liquid may be compared with a previously set limit discharging number of the ink jet head. A replacement time of the ink jet head may be determined if the cumulative discharging number of the chemical liquid exceeds the previously set limit discharging number.

Method and Apparatus for Determining Search Range for Adaptive Motion Vector for Use in Video Encoder

The video encoder in accordance with the present invention divides input image signal into macro blocks, estimates motion vectors of each macro block and finally encodes the input image signal. The encoder determines the number of macro blocks adjacent to a current macro block. If the number of adjacent macro blocks is equal to or more than two, the encoder calculates a motion vector of the adjacent macro blocks and selects a macro block that has the largest motion vector. Then it defines a least search area that the current adaptive motion vector can have, and compares the least search area with the motion vector of the largest adjacent macro block, and finally determines the largest value as the search area of the adaptive motion vector. Next, the encoder compares the search area of the adaptive motion vector with the search area of the user-defined motion adaptive vector to thereby determine the least value as the search area of the final adaptive motion vector.

METHOD AND APPARATUS FOR DISPLAYING KEYPAD IN TERMINAL HAVING TOUCH SCREEN

A method and an apparatus thereof display a key pad and solve the trouble and difficulty of a user in selecting the key pad displayed in a terminal having a touch screen. The method detects a touch gesture with respect to the touch screen; determines whether the detects touch gesture is zoom-out; displays thumbnails representing key pads, respectively, when the detected touch gesture is the zoom-out; and displays a key pad of a selected thumbnail when one of the displayed thumbnails is selected by a user. 1. A method for displaying a specific key pad in a terminal having a touch screen , the method comprising:detecting a touch gesture with respect to the touch screen;determining whether the detected touch gesture is a zoom-out gesture;displaying thumbnails representing key pads, respectively, when the detected touch gesture is the zoom-out gesture; anddisplaying the specific key pad corresponding to a selected thumbnail when one of the displayed thumbnails is selected by a user.2. The method of claim 1 , wherein the zoom-out gesture is a touch gesture in which the user reduces an interval between two fingers in a touched state on the touch screen.3. The method of claim 2 , further comprising:computing a speed of the zoom-out gesture;comparing the computed speed of the zoom-out gesture with a first preset value; andreducing a displayed size of the specific key pad when the computed speed of the zoom-out gesture is less than or equal to the first preset value,wherein the displaying of the thumbnails is performed when the computed speed of the zoom-out gesture is greater than the first preset value.4. The method of claim 1 , further comprising:reducing a displayed size of the specific key pad when the detected touch gesture is the zoom-out gesture;computing a pinch of the zoom-out gesture while reducing the displayed size of the specific key pad; andcomparing the pinch of the zoom-out gesture with a second preset value,wherein the displaying of the thumbnails is ...

Pulse amplitude modulation-3 transceiver and operation method thereof

According to an embodiment of the inventive concept, a device for PAM-3 signaling includes an encoder selecting one of first to ninth transitions in first and second unit intervals that are successive and mapping data of three bits by using a remaining eight transitions other than the one selected among the first to ninth transitions, and an output driver receiving an output signal of the encoder via an input and generating a multi-level signal having an output voltage of first to third levels. The data of three bits is transmitted to a receiver terminal through the multi-level signal having the output voltage of the first to third levels during the first and second unit intervals that are successive. The device for PAM-3 signaling according to an embodiment of the inventive concept may transmit three bits during two unit intervals and may allow a receiver terminal to detect a windowing phenomenon.

PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Disclosed are package substrates and semiconductor packages including the same. A package substrate may have a plurality of corner regions; a core layer having a first surface and a second surface; an upper layer, which includes a plurality of first wiring structures and a plurality of first dielectric layers; and a lower layer, which includes a plurality of second wiring structures and a plurality of second dielectric layers. Additionally, an area proportion of top surfaces of the first wiring structures in the upper layer relative to a top surface of the upper layer on each of the corner regions is less than an area proportion of top surfaces of the second wiring structures in the lower layer relative to a top surface of the lower layer on each of the corner regions. 1. A semiconductor package , comprising:a package substrate which includes a plurality of corner regions; anda first semiconductor chip on the package substrate, a core layer having a first surface and a second surface opposite the first surface;', 'an upper layer, which includes a plurality of first wiring structures and a plurality of first dielectric layers, on the first surface of the core layer; and', 'a lower layer, which includes a plurality of second wiring structures and a plurality of second dielectric layers, on the second surface of the core layer,, 'wherein the package substrate further includeswherein an area proportion of top surfaces of the first wiring structures in the upper layer relative to a top surface of the upper layer on each of the corner regions is less than an area proportion of top surfaces of the second wiring structures in the lower layer relative to a top surface of the lower layer on each of the corner regions.2. The semiconductor package of claim 1 , wherein each of the corner regions has a triangular shape when viewed in plan view.3. The semiconductor package of claim 1 , whereinthe package substrate further includes a first lateral surface that extend parallel to a ...

METHOD OF MAINTAINING AN INK JET HEAD AND PRINTING METHOD USING AN INK JET HEAD

In a printing method using an ink jet head, a chemical liquid may be discharged onto a substrate from a plurality of nozzles of the ink jet head. Discharging numbers of the chemical liquid from the plurality of nozzles may be identified and a cumulative discharging number of the chemical liquid from the plurality of nozzles may be calculated. The cumulative discharging number of the chemical liquid may be compared with a previously set limit discharging number of the ink jet head. A replacement time of the ink jet head may be determined if the cumulative discharging number of the chemical liquid exceeds the previously set limit discharging number. 1. A method of maintaining an ink jet head , which comprises:identifying discharging numbers of the chemical liquid discharged from the ink jet head onto an object;calculating a cumulative discharging number of the chemical liquid from the ink jet head;comparing the cumulative discharging number of the chemical liquid with a previously set limit discharging number of the ink jet head; anddetermining a replacement time of the ink jet head based on the comparison of the cumulative discharging number and previously set limit discharging number.2. The method of maintaining an ink jet head according to claim 1 , wherein the discharging numbers of the chemical liquid are obtained by counting operating numbers of piezoelectric elements of the ink jet head.3. The method of maintaining an ink jet head according to claim 2 , wherein the cumulative discharging number of the chemical liquid is calculated by accumulatively counting the operating numbers of the piezoelectric elements of the ink jet head.4. The method of maintaining an ink jet head according to claim 1 , the determining of the replacement time of the ink jet head is performed if the cumulative discharging number of the chemical liquid exceeds the previously set limit discharging number.5. The method of maintaining an ink jet head according to claim 1 , wherein the ...

Apparatus and system for tracking data speed automatically

An apparatus and a system for automatically tracking data speed are disclosed. An embodiment of the invention provides a transmitting apparatus for automatically tracking data speed that includes: an encoder configured to convert parallelized input data according to a preset signal rule into a first signal and a second signal, where the input data is inputted as a unit of n bits, the encoder outputs the first signal and the second signal such that, if the input data includes identical bit values consecutively, one of the first signal and the second signal is converted to include transition information instead of following a differential rule with respect to the other signal; a serializer configured to serialize the first signal and the second signal; and a transmitting part configured to transmit the serialized first signal and second signal.

Mold

A mold includes a core in which a molded product is formed, the core comprises a cored body and a sliding core on the core body, separable from the core body in a first direction with respect to the core body, and an ejector to press the sliding core in the first direction to separate the molded product formed in the core from the core. The ejector includes a driver positioned below the core and movable toward a lower surface of the core in the first direction or away from the lower surface of the core in a direction opposite to the first direction, and a rod movable in the first direction to press the sliding core to be separated from the driver or movable in the direction opposite to the first direction to couple the sliding core with the driver, and the rod is movable further in the first direction than the driver.

Method for performing task and electronic device supporting the same

A method for performing a task in an electronic device includes: detecting a deformation of at least a part of the electronic device; identifying information on a task which is performed in the electronic device; and restoring the at least a part of the electronic device from which the deformation is detected based on at least the identified information on the task.

Transceiver using multi-level braid signaling and method of operating the same

A transceiver includes a transmitter modulating a data signal into code information in a modulation section unit and individually supplying a common mode current to a plurality of transmission lines and a receiver detecting the code information according to a voltage level of each of the transmission lines and outputting the data signal.

CHARGE PUMPING APPARATUS FOR LOW VOLTAGE AND HIGH EFFICIENCY OPERATION

A charge pump (CP) that operates at low input voltage with high power conversion efficiency is disclosed. A first embodiment provides a negative CP used for controlling load switches of a voltage doubler. Using a negative CP extends the operating region below ground to relieve the power delivery limitation of the CP. A second embodiment provides a low power adaptive dead-time circuit, which has several dead-time signals having different lengths of dead-times and selects one according to the input voltage level. A low input voltage detector in the adaptive dead-time circuit is used to determine which dead-time should be used. A third embodiment provides a switching body bias used for the low input voltage CP. The switching body bias uses both forward and reverse body bias applied to the CP to minimize reverse current and maximize power transfer. The first, second, and third embodiments can be used together or independently. 1. A charge pump circuit , comprising:two or more unit charge pumps arranged in series, wherein each unit charge pump includes:a first pumping capacitor,a second pumping capacitor,two cross-coupled NMOS switches, wherein the first pumping capacitor is coupled to the source of a first cross-coupled NMOS switch and the gate of the second cross-coupled NMOS switch, and the second pumping capacitor is coupled to the source of the second cross-coupled NMOS switch and the gate of the first cross-coupled NMOS switch, andfour PMOS switches for switching body biasing applied to the two cross-coupled NMOS switches.2. The charge pump according to claim 1 , further comprising:an adaptive dead-time circuit that includes dead-time circuits with different lengths of dead-times and an input voltage detector.3. The charge pump according to claim 2 , wherein each unit charge pump doubles an input voltage of the unit charge pump by using overlapping clock signals claim 2 , wherein the overlapping clock signals are generated by the adaptive dead-time circuit.4. The ...

HYBRID SUBSTRATES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS FOR FABRICATING SEMICONDUCTOR PACKAGES

Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer. 1. A method for fabricating a semiconductor package , the method comprising:providing a substrate, the substrate having a first layer and a second layer on the first layer, the first layer including a conductive pattern with a first pitch and a second pitch greater than the first pitch and the second layer having a circuit pattern with the second pitch, the circuit pattern being connected to the conductive pattern;providing a semiconductor chip on the substrate, the semiconductor chip including a plurality of chip pads having the first pitch;connecting the chip pads to the conductive pattern to electrically connect the semiconductor chip to the substrate;forming a molding layer on the semiconductor chip; andforming an external terminal connected to the circuit pattern.2. The method of claim 1 , wherein the providing the substrate comprises:providing a support plate;sequentially forming the first and second layers on the support plate; andremoving the support plate.3. The method of claim 2 , whereinforming the first layer includes forming an inorganic insulation layer on the support plate, the inorganic ...

METHOD AND ELECTRONIC DEVICE FOR PLAYING AUDIO DATA USING DUAL SPEAKER

An electronic device, method, and non-transitory computer-readable recording medium are provided. Electronic device includes first speaker and second speaker arranged in electronic device, processor operatively connected with first speaker and second speaker, and memory operatively connected to the processor, wherein the memory is configured to store instructions executed to enable the processor to detect an orientation or attitude of the electronic device while playing first channel audio data and second channel audio data via the first speaker and the second speaker, and based on at least part of the detected orientation or attitude of the electronic device, keep outputting a first frequency component of the first channel audio data and a second frequency component of the second channel audio data via the first speaker and the second speaker and switch a second frequency component of the first channel audio data and a first frequency component of the second channel audio data. 1. An electronic device , comprising:a first speaker and a second speaker arranged in the electronic device;a processor operatively connected with the first speaker and the second speaker; anda memory operatively connected to the processor, wherein the memory is configured to store instructions executable to enable the processor to:detect an orientation or attitude of the electronic device while playing first channel audio data and second channel audio data via the first speaker and the second speaker, andbased on at least part of the detected orientation or attitude of the electronic device, keep outputting a first frequency component of the first channel audio data and a second frequency component of the second channel audio data via the first speaker and the second speaker, and switch a second frequency component of the first channel audio data and a first frequency component of the second channel audio data.2. The electronic device of claim 1 , wherein the memory is further configured to ...

SIGNAL RECEIVER AND OPERATION METHOD THEREOF

A signal receiver includes a data sampler receiving a differential input signal having first and second input signals and determining bit values of the differential input signal based on first and second reference voltages, and a reference voltage generator performing a pre-tuning operation and a post-tuning operation to generate the reference voltages. The reference voltage generator performs the pre-tuning operation by generating first and second initial voltages and adjusting one of the initial voltages to generate third and fourth voltages. After the pre-tuning operation, the reference voltage generator performs the post-tuning operation by increasing or decreasing the third voltage to generate the first reference voltage and decreasing or increasing the fourth voltage to generate the second reference voltage based on a comparison result between the third voltage and the first input signal and a second comparison result between the fourth voltage and second input signal.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer. 1. A semiconductor package , comprising:a package substrate;a first interposer substrate mounted on the package substrate;a second interposer substrate disposed on the first interposer substrate; anda semiconductor chip mounted on the second interposer substrate, a first base layer;', 'a second base layer disposed on the first base layer, a top surface of the first base layer contacting a bottom surface of the second base layer;', 'a first pad exposed on the top surface of the first base layer and connected to a first interconnection pattern which is in the first base layer;', 'a second pad exposed on the bottom surface of the second base layer; and', 'a third pad exposed on a top surface of the second base layer,, 'wherein the first interposer substrate compriseswherein the first pad and the second pad are connected to each other, at an interface between the first base layer and the second base layer,wherein a second interconnection pattern of the second interposer substrate is connected to the third pad, at an interface between the second base layer of the first interposer substrate and the second interposer substrate, andwherein the first base layer and the second base layer are each formed of silicon (Si).2. The semiconductor package of claim 1 , wherein the first pad and the second pad constitute a single body formed of the same material as each other.3. The ...

DIFFERENTIAL SIGNAL PROCESSING DEVICE USING ADVANCED BRAID CLOCK SIGNALING

A differential signal processing device is described which includes an encoder configured to encode input data into one or more differential signals and a transmitter configured to sequentially transmit the one or more differential signals using a plurality of transmission lines. The encoder converts a plurality of bits, corresponding to a transmission time interval, among the input data into an encoding code array in the transmission time interval obtained by increasing an encoding unit time, encoded for each of the one or more differential signals, by an integer multiple. 1. A differential signal processing device comprising:an encoder configured to encode input data into one or more differential signals; anda transmitter configured to sequentially transmit the one or more differential signals using a plurality of transmission lines,wherein the encoder converts a plurality of bits, corresponding to a transmission time interval, among the input data into an encoding code array in the transmission time interval obtained by increasing an encoding unit time, encoded for each of the one or more differential signals, by an integer multiple.2. The differential signal processing device of claim 1 , wherein the encoder converts the encoding code array into the one or more differential signals according to advanced braid clock signaling claim 1 , andthe advanced braid clock signaling comprises a single braid code, a single mapping code, and a single index code, corresponding to a single differential signal.3. The differential signal processing device of claim 1 , wherein the encoder adjusts the integer multiple based on the plurality of bits claim 1 , corresponding to the transmission time interval claim 1 , among the input data.4. The differential signal processing device of claim 2 , wherein the encoder determines a number of the plurality of bits claim 2 , corresponding to the transmission time interval according to the integer multiple claim 2 , based on a number of ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer. 1. A semiconductor package , comprising:a package substrate;a first interposer substrate mounted on the package substrate; anda first semiconductor chip disposed on the first interposer substrate,wherein the first interposer substrate comprises:a first base layer;a second base layer disposed on the first base layer;circuit patterns provided in each of the first base layer and the second base layer; andan integrated device embedded in the first base layer and connected to at least one of the circuit patterns, andwherein a top surface of the first base layer contacts a bottom surface of the second base layer.2. The semiconductor package of claim 1 , wherein the circuit patterns comprise:a first interconnection pattern provided in the first base layer; anda through electrode provided in the second base layer to vertically penetrate the second base layer,wherein the first interconnection pattern and the through electrode are connected to each other, at an interface between the first base layer and the second base layer.3. The semiconductor package of claim 2 , wherein the first interconnection pattern and the through electrode constitute a single body formed of the same material as each other.4. The semiconductor package of claim 3 , wherein the first interconnection pattern and the through electrode comprise a metallic material.5. The semiconductor package of claim 2 , wherein ...

HYBRID SUBTRATES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS FOR FABRICATING SEMICONDUCTOR PACKAGES

Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer. 19-. (canceled)10. A semiconductor package including a plurality of external terminals , the semiconductor package comprising:a semiconductor chip including a plurality of chip pads, the chip pads having a first pitch; a plurality of first conductive patterns on a bottom surface of the first layer, the first conductive patterns having a second pitch, the first conductive patterns connected to the chip pads,', 'a plurality of second conductive patterns on a top surface of the first layer, the second conductive patterns having a third pitch, the third pitch being greater than the first pitch, and', 'a plurality of circuit patterns connecting the first conductive patterns with the second conductive patterns;, 'a first layer on the semiconductor chip, the first layer formed of a first organic material, the first layer including,'} a plurality of first vias penetrating the second layer, and', 'a plurality of third conductive patterns on a top surface of the second layer, the first was connecting the second conductive patterns with the third conductive patterns; and, 'a second layer on the first layer, the second ...

Apparatus for discharging chemical liquid and method of discharging chemical liquid

An apparatus for discharging chemical liquid may include an ink jet head, a gantry and a control member. The ink jet head may include a plurality of nozzles capable of discharging chemical liquid onto a substrate. The gantry may hold the ink jet head to place the ink jet head over the substrate. The control member may control the ink jet head such that discharge times of the chemical liquid from the nozzles of the ink jet head may be changed.

Capacitively coupled continuous-time delta-sigma modulator and operation method thereof

According to an exemplary embodiment, a capacitively coupled continuous-time delta-sigma modulator includes an instrumentation amplifier amplifying an input voltage to an output voltage of a predetermined magnitude, a delta-sigma modulator outputting a bit signal quantized depending on a sampling frequency based on the output voltage and to convert the bit signal into a digital-to-analog conversion voltage, and a ripple reduction loop unit generating a demodulation voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency to feed the demodulation voltage back to the instrumentation amplifier. The RRL operating frequency is equal to the sampling frequency.

Touch sensor with modular shape and display device including the same

A display device includes a first touch panel on which a first touch sensing unit including a plurality of coils is disposed, a second touch panel on which a second touch sensing unit including a plurality of sensing nodes coupled to the plurality of coils in a coupling manner with a one-to-one correspondence, and a display panel disposed between the first and second touch panels and displays an image, and the plurality of sensing nodes is formed in a divided structure grouped into first and second node groups based on a touch event detected by the first touch sensing unit.

CONTINUOUS-TIME DELTA-SIGMA MODULATOR

A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal. 1. A continuous-time delta-sigma modulator , comprising:a loop filter which integrates a difference between an input signal and a feedback signal;a quantizer which quantizes a signal output from the loop filter to convert the quantized signal into a digital signal;a finite impulse response (FIR) filter which performs a FIR filtering process on the digital signal output from the quantizer; anda digital to analog converter which converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal;wherein the loop filter is implemented by at least one Gm-C integrator, and a transconductor which generates differential output currents through a plus output terminal and a minus output terminal in accordance with a difference of input voltages input to a plus input terminal and a minus input terminal; and', 'first and second capacitors which receive the differential output current to charge charges and generate an integrated voltage., 'wherein the at least one Gm-C integrator includes2. (canceled)3. The continuous-time delta-sigma modulator according to claim 1 , further comprising:a chopper circuit which is located at a front-end or a rear-end of the transconductor and removes a low frequency noise of the Gm-C integrator.4. The continuous-time delta-sigma modulator according to claim 3 , wherein the chopper ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions. 1. A semiconductor package , comprising:a package substrate;an interposer on the package substrate, the interposer including individual mounting regions on a first surface thereof and a plurality of first bonding pads in the individual mounting regions respectively;a plurality of semiconductor devices in the individual mounting regions on the first surface of the interposer, respectively, the plurality of semiconductor devices each having chip pads electrically connected to the plurality of first bonding pads;first conductive connection members between the plurality of first bonding pads and the chip pads; anda molding member on the interposer, the molding member covering the plurality of semiconductor devices and filling gaps between the first surface of the interposer and the plurality of semiconductor devices,wherein at least one of the individual mounting regions includes a pad-free region with a cross shape and a plurality of pad regions defined by the pad-free region, and the plurality of first bonding pads are in the plurality of pad regions.2. The semiconductor package of claim 1 , ...

Method and electronic device for playing audio data using dual speaker

Method for performing task and electronic device supporting the same

Phase-digital converter having hierarchical structure

A time to digital converter having a hierarchical structure is provided. The time to digital converter includes: a plurality of delay stages for sequentially delaying a first signal for a specific delay time; a plurality of flip-flops for comparing delay signals of the first signal delayed by the delay stages with a second signal, and generating different outputs before and after a phase difference between the delay signals of the first signal and the second signal becomes smaller than a resolution of the phase detector; a selection signal generator for generating a selection signal for selecting a signal most similar to the second signal among the delay signals of the first signal from the outputs of the flip-flops; and a Multiplexer (MUX) for receiving the delay signals of the first signal and the selection signal, and outputting the signal most similar to the second signal among the delay signals of the first signal.

Method and apparatus for displaying a keypad on a terminal having a touch screen

Method and electronic device for playing audio data using dual speaker

An electronic device, method, and non-transitory computer-readable recording medium are provided. Electronic device includes first speaker and second speaker arranged in electronic device, processor operatively connected with first speaker and second speaker, and memory operatively connected to the processor, wherein the memory is configured to store instructions executed to enable the processor to detect an orientation or attitude of the electronic device while playing first channel audio data and second channel audio data via the first speaker and the second speaker, and based on at least part of the detected orientation or attitude of the electronic device, keep outputting a first frequency component of the first channel audio data and a second frequency component of the second channel audio data via the first speaker and the second speaker and switch a second frequency component of the first channel audio data and a first frequency component of the second channel audio data.

Mold

Semiconductor package and method of fabricating the same

A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

Pam-4 receiver using pattern-based clock and data recovery circuitry

Disclosed in a PAM-4 receiver using pattern-based clock and data recovery circuitry, which includes an analog front end that receives an external signal and recovers channel loss to output a refined PAM-4 signal, a comparison unit that receives the PAM-4 signal and compares the PAM-4 signal with a reference voltage to generate a recovery signal, and a recovery unit that receives the recovery signal and recovers data and a clock. The analog front end includes an equalizer that matches amplitudes of all frequency components of the external signal and an amplifier that amplifies an output signal of the equalizer.

Halbleiter-Package

Ein Halbleiter-Package (10) enthält ein Package-Substrat (100), einen Halbleiterchip (200) auf dem Package-Substrat (100) und eine Unterfüllung (300) zwischen dem Package-Substrat (100) und dem Halbleiterchip (200). Das Package-Substrat (100) enthält einen im Package-Substrat (100) ausgebildeten Graben (150) und eine Mehrzahl an Dämmen (110) jeweils auf beiden Seiten des Grabens. Die Deckflächen der Mehrzahl an Dämmen (110) können auf einer niedrigeren Ebene positioniert sein als die Bodenoberfläche des Halbleiterchips (200) in einer Querschnittsansicht des Halbleiter-Packages (10) mit dem Package-Substrat (100), das eine Basisbezugsebene vorsieht.

Time domain analog-to-digital converter and analog-to-digital converting method

In analog-to-digital conversion, a plurality of stages configured in a sequence to sequentially decide a plurality of bits in successive-approximation, each of the plurality of stages configured to operate in response to a corresponding clock among a plurality of clocks, and decide a corresponding bit among the plurality of bits from a corresponding positive pulse among a plurality of positive pulses and a corresponding negative pulse among a plurality of negative pulses; and a plurality of clock generating circuits respectively corresponding to a plurality of first stages among the plurality of stages, each of the plurality of clock generating circuit configured to generate the corresponding clock of a corresponding stage among the plurality of first stages based on an operation of a previous stage among the plurality of stages, the previous stage being before the corresponding stage in the sequence.

Chemical liquid removing unit, device for supplying chemical liquid and method of removing chemical liquid

A chemical liquid removing unit may remove a remaining chemical liquid from an ink jet head. The chemical liquid removing unit may include a surface tension providing part configured to remove the remaining chemical liquid from a nozzle face of the ink jet head using a surface tension, a driving part configured to move the surface tension providing part relative to the nozzle face the ink jet head, and a control part configured to control the driving part such that the surface tension providing part contacts the remaining chemical liquid whereas the surface tension providing part does not contact the nozzle face of the ink jet head.

Semiconductor package and method of manufacturing semiconductor package

A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions.

Semiconductor device

A semiconductor device is provided. The semiconductor device includes: an equalizer circuit configured to output a first control signal corresponding to a first bit of original two-bit data and a second control signal corresponding to a second bit of the original two-bit data; and a driver circuit including a plurality of pull-up transistors connected between an output node and a first power node configured to provide a first power supply voltage, and a plurality of pull-down transistors connected between the output node and a second power node configured to provide a second power supply voltage, wherein the second power supply voltage is lower than the first power supply voltage, and the driver circuit is connected to the equalizer circuit in series. The plurality of pull-up transistors includes a first pull-up transistor and a second pull-up transistor connected to each other in parallel, between the first power node and the output node, and a third pull-up transistor and a fourth pull-up transistor connected to each other in series, between the first power node and the output node.

Receiver including a pulse amplitude modulation decoder, and a memory device including the same

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

Gas management system

Disclosed herein a gas management system includes a natural gas liquefied line configured to receive natural gas to liquefy; a first medium circulation line through which a first cooling medium circulates; a second medium circulation line through which a second cooling medium circulates; and a heat exchanger provided between the natural gas liquefied line, and the first medium circulation line and the second medium circulation line; wherein the heat exchanger includes first to third heat exchange areas divided based on heat exchange temperature ranges, and the second medium circulation line is configured to rejoin after branching into a first branch line passing through the first heat exchange area and a second branch line passing through the first and second heat exchange areas.

Semiconductor device and memory system

A semiconductor device includes a multilevel receiver including a signal determiner receiving a plurality of multilevel signals and outputting a result of mutual comparison of the plurality of multilevel signals as an N-bit signal, where N is a natural number equal to or greater than 2. A decoder restores a valid signal among the N-bit signals from the signal determiner to an M-bit data signal, where M is a natural number less than N. A clock generator receives a reference clock signal, generates an input clock signal using the reference clock signal, inputs the input clock signal to the signal determiner, and determines a phase of the input clock signal based on an occurrence probability of an invalid signal not restored to the M-bit data signal among the N-bit signals.

Semiconductor packages

A semiconductor package includes a substrate including a wiring, a semiconductor chip structure on the substrate, and electrically connected to the wiring, an underfill resin in a space between the substrate and the semiconductor chip structure, and a stiffener surrounding the semiconductor chip structure, on the substrate, wherein the stiffener includes a conductive frame having a cavity and an insulating filler in the cavity.

Method and apparatus for determining search range for adaptive motion vector for use in video encoder

Successive approximation analog-to-digital conversion device skipping comparison results and its operating method

Disclosed is an analog-to-digital conversion device. The analog-to-digital conversion device includes a signal generating unit that generates a plurality of comparison voltages based on an analog input voltage and generates a plurality of comparison results of the plurality of comparison voltages based on a sampling period, a calculation unit that skips a comparison result generated by a comparison voltage having a smallest difference between the analog input voltages among the plurality of comparison voltages from the plurality of comparison results and generates an end of comparison based on a remaining plurality of comparison results, and a SAR logic unit that generates a digital signal corresponding to the end of comparison and stores information for each bit of the digital signal.

Semiconductor package and method of manufacturing semiconductor package

A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions.

Method and apparatus for displaying keypad in terminal having touch screen

A method and an apparatus thereof display a key pad and solve the trouble and difficulty of a user in selecting the key pad displayed in a terminal having a touch screen. The method detects a touch gesture with respect to the touch screen; determines whether the detects touch gesture is zoom-out; displays thumbnails representing key pads, respectively, when the detected touch gesture is the zoom-out; and displays a key pad of a selected thumbnail when one of the displayed thumbnails is selected by a user.