SEPARATORS FOR HANDLING, TRANSPORTING, OR STORING SEMICONDUCTOR WAFERS

Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators. 1. A semiconductor wafer separator , comprising: an outer edge defining a periphery of the circular ring, and', 'an inner edge defining a central opening of the circular ring;, 'a circular ring including 'wherein the first right-angled recess extends downward from a top surface of the circular ring; and', 'a first right-angled recess configured to receive a semiconductor wafer,'}a second right-angled recess configured to maintain a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess.2. The semiconductor wafer separator of claim 1 , further comprising:a first interlock component disposed along the top surface of the circular ring; anda second interlock component disposed along a bottom surface of the circular ring.3. The semiconductor wafer separator of claim 2 , wherein the first interlock component is a recess adapted to engage a corresponding second interlock component of an upwardly-adjacent wafer separator.4. The semiconductor wafer separator of claim 2 , wherein the second interlock component is a ...

SEPARATORS FOR HANDLING, TRANSPORTING, OR STORING SEMICONDUCTOR WAFERS

Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.

Flat-type single phase brushless DC motor

A flat-type single phase brushless direct current (BLDC) motor includes a rotor rotatably fixed to a shaft and having a permanent magnet attached to a lower side thereof; a stator plate installed below the rotor; a plurality of stator cores installed on the stator plate to face the permanent magnet, the stator cores including soft magnetic powder and arranged to be asymmetric with respect to a rotation radial direction of the rotor so as to determine a rotational direction of the rotor; and a multiplicity of coils each being wounded around corresponding one of the stator cores to form a magnetic field toward the permanent magnet.

SEPARATORS FOR HANDLING, TRANSPORTING, OR STORING SEMICONDUCTOR WAFERS

Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.

Separators for handling, transporting, or storing semiconductor wafers

Introduced here is a wafer separator configured to carry a semiconductor wafer with improved efficiency, protection, and reduced costs when utilized in the handling, transport, or storage of semiconductor components. The wafer separator may include a circular ring having an outer edge defining a periphery of the circular ring. The circular ring may include an inner edge defining a central opening of the circular ring. The wafer separator may include a first-right angled recess for receiving a semiconductor wafer that extends downward from a top surface of the circular ring. The wafer separator may also include a second right-angled recess for maintaining a gap beneath the semiconductor wafer when the semiconductor wafer is set within the first right-angled recess. In some embodiments, the wafer separator also includes interlock components for connecting the wafer separator to adjacent wafer separators.

SEMICONDUCTOR DEVICE

The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate. 1. A semiconductor device , comprising:a second conductive-type deep well configured over a substrate;a first conductive-type well configured over the second conductive-type deep well;a second conductive-type anti-diffusion region configured in the second conductive-type deep well to contact a sidewall of the first conductive-type well; and a gate electrode configured to simultaneously cross the first conductive-type well, the second conductive-type anti-diffusion region, and the second conductive-type deep well over the substrate.2. The semiconductor device of claim 1 , wherein an impurity doping concentration of the anti-diffusion region is higher than impurity doping concentrations of the second conductive-type deep well and the first conductive-type well.3. The semiconductor device of claim 1 , further comprising:a device isolation layer configured over the substrate; a second conductive-type source region configured over the first conductive-type well at one end of one side of the gate electrode; anda second conductive-type drain region configured over the second conductive-type deep well and spaced apart from one end of another side of the gate electrode by a predetermined distance.4. The semiconductor device of claim 3 , wherein the second conductive-type anti-diffusion region is fully depleted based on a voltage supplied to the second conductive-type drain region.5. The semiconductor device of claim 3 , wherein the ...

METHOD FOR SUPPORTING COEXISTENCE CONSIDERING WHILE SUBCHANNEL ALLOCATION IN A BROADBAND WIRELESS ACCESS SYSTEM

A method for supporting coexistence in a mobile station configured for supporting a coexistence mode of a primary wireless communication system and a secondary wireless communication system. The method comprises transmitting to a base station, via the mobile station, a registration request (REG-REQ) message comprising coexistence capability information, receiving a registration response (REG-RSP) message comprising information about support of the coexistence mode in response to the REG-REQ message, and transmitting to the base station, via the mobile station, a sleep mode request (MOB_SLP-REQ) message comprising first coexistence information for requesting a band adaptive modulation and coding (AMC) for adjacent subcarrier permutation. 1. A method for supporting coexistence in a mobile station configured for supporting a coexistence mode of a primary wireless communication system and a secondary wireless communication system , the method comprising:transmitting to a base station, via the mobile station, a registration request (REG-REQ) message comprising coexistence capability information;receiving a registration response (REG-RSP) message comprising information about support of the coexistence mode in response to the REG-REQ message; andtransmitting to the base station, via the mobile station, a sleep mode request (MOB_SLP-REQ) message comprising first coexistence information for requesting a band adaptive modulation and coding (AMC) for adjacent subcarrier permutation.2. The method of claim 1 , wherein subcarriers of an uppermost frequency band or a lowermost frequency band are allocated to the mobile station via the adjacent subcarrier permutation based on a bit value of the first coexistence information.3. The method of claim 1 , further comprising receiving claim 1 , from the base station claim 1 , a sleep mode response (MOB_SLP-RSP) message comprising second coexistence information in response to the MOB_SLP-REQ message.4. The method of claim 1 , further ...

Identity Verification Device

Provided is an apparatus for identifying person's identity. User's eyeballs may be precisely located in an operation region of the apparatus for identifying the person's identity, i.e., a photograph region in which an iris image of a user to be identified by the camera can be photographed using an indicator provided by the apparatus for identifying the person's identity. Also, a limitation in which the user's eyeballs are located at positions different from each other due to person's parallaxes different from each other even though the indicator is provided at the same position may be solved to locate the eyeballs of the user to be identified using the apparatus for identifying the person's identity at the same position. 1. An apparatus which collects body information of a user to identify user's identity , the apparatus comprising:an indication part providing an indicator to only one eye of user's two eyes;a mirror part by which a body of the user aligned with respect to the indicator is mirrored;a collection part collecting the body information from the aligned body of the user; anda control part controlling an operation of the apparatus for identifying the user's identity.2. The apparatus according to claim 1 , wherein the indication part comprises:a light source having a predetermined width and spaced a predetermined distance from the mirror part; anda light path restriction part extending from the light source toward the mirror part to restrict a path of light emitted from the light source.3. The apparatus according to claim 2 , wherein the light path restriction part is inclined at a predetermined angle with respect to a plane of the mirror part.4. The apparatus according to claim 2 , wherein the light path restriction part is formed of an opaque light-absorbing material.5. The apparatus according to claim 2 , wherein the more a distance from the light source to the mirror part is decreased claim 2 , the more a width of the light source is decreased.6. The ...

PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF

A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. 1. A method of manufacturing a phase change memory device , comprising the steps of:forming a bottom electrode contact hole to expose a switching device on a semiconductor substrate;forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact hole by using an insulating compound having materials of different atomic sizes; andforming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.2. The method of claim 1 , wherein the step of forming an insulating layer comprises repeatedly depositing a plurality of insulating materials having different atomic sizes at least one or more times in a pre-arranged order.3. The method of claim 1 , wherein the insulating compound comprises a germanium compound.4. The method of claim 3 , wherein the germanium compound comprises silicon-germanium.5. The method of claim 4 , wherein the step of forming an insulating layer comprises repeatedly depositing a silicon layer and a germanium layer at least one or more times in a pre-arranged order.6. The method of claim 4 , wherein the insulating layer is a Ge-rich insulating layer.7. The method of claim 4 , wherein the insulating layer is a Si-rich insulating layer.8. The method of claim 3 , wherein the germanium compound comprises silicon-germanium-nitride.9. The method of claim 8 , wherein the step of forming an insulating layer comprises repeatedly depositing each of a silicon layer claim 8 , a germanium layer and a nitride layer at least one or more time in a pre-arranged order.10. The method of claim 9 , wherein after forming the silicon layer claim 9 , the germanium layer and the nitride layer claim 9 , further carrying out purge processes claim 9 , respectively claim 9 ,wherein ...

METHOD FOR INTERFERENCE ALIGNMENT IN WIRELESS NETWORK

A method for interference alignment in wireless network having 3 transmitters and 3 receivers which are equipped with M antennas is provided. The method comprising: transmitting, performed by each of the 3 transmitters, a pilot signal known to the 3 receivers; estimating, performed by each of the 3 receivers, each channel from transmitter; transmitting, performed by each of the 3 receivers, feedback information to target transmitter; and determining, performed by transmitter 2 and transmitter 3, a precoding vector; wherein a degree of freedom(DoF) of a transmitter 1 is (M/2−α), a DoF of the transmitter 2 or the transmitter 3 is M/2. 1. A method for interference alignment in wireless network having 3 transmitters and 3 receivers which are equipped with M antennas , the method comprising:transmitting, performed by each of the 3 transmitters, a pilot signal known to the 3 receivers;estimating, performed by each of the 3 receivers, each channel from transmitter;transmitting, performed by each of the 3 receivers, feedback information to target transmitter; anddetermining, performed by transmitter 2 and transmitter 3, a precoding vector; wherein a degree of freedom(DoF) of a transmitter 1 is (M/2−α), a DoF of the transmitter 2 or the transmitter 3 is M/2.2. The method of claim 1 , wherein first (M/2−α) beams at the transmitter 2 and the transmitter 3 are aligned with beams of the transmitter 1.3. The method of claim 1 , wherein last a beams of the transmitter 2 and the transmitter 3 are aligned at a receiver 1.4. The method of claim 1 , wherein a transmitter 1 uses a predetermined precoder which is known to the 3 receivers.5. The method of claim 4 , wherein the predetermined precoder is (M×(M/2−α)) matrix.7. The method of claim 6 , wherein first (M/2−α) beams at the transmitter 2 and the transmitter 3 is determined by below equation.{'br': None, 'i': V', 'H', 'H', 'V, 'sub': [1, . . . , M/2−α]', '[1, . . . , M/2−α], 'sup': [2]', '[32]', '−1', '[31]', '[1], 'img': {'@id': ...

POWER CONTROL METHOD FOR INTERFERENCE ALIGNMENT IN WIRELESS NETWORK

A power control method for interference alignment in wireless network having K transmitters and K receivers is provided. The method comprising: receiving, performed by receiver n (n is an integer, 1≦n≦K−1), a power indication signal of transmitter n+1 from the transmitter n+1; determining, performed by the receiver n, power of transmitter n; and transmitting, performed by the receiver n, a power indication signal of transmitter n to the transmitter n, wherein the power of transmitter n is determined based on a residual interference of the receiver n, and the power indication signal of transmitter n indicates a minimum transmission power or a maximum transmission power of transmitter n. 1. A power control method for interference alignment in wireless network having K transmitters and K receivers , the method comprising:receiving, performed by receiver n (n is an integer, 1≦n≦K−1), a power indication signal of transmitter n+1 from the transmitter n+1;determining, performed by the receiver n, power of transmitter n; andtransmitting, performed by the receiver n, a power indication signal of transmitter n to the transmitter n,wherein the power of transmitter n is determined based on a residual interference of the receiver n, and the power indication signal of transmitter n indicates a minimum transmission power or a maximum transmission power of transmitter n.2. The method of claim 1 , further comprising:determining, performed by the receiver K, power of transmitter K based on a residual interference of the receiver K; andtransmitting, performed by the receiver K, a power indication signal of transmitter K to the transmitter K.3. The method of claim 1 , the power indication signal of transmitter n includes 1 bit which indicates the minimum transmission power or the maximum transmission power of transmitter n.4. The method of claim 1 , wherein K is 4 and each of the K transmitters and the K receivers has 3 antennas.5. The method of claim 1 , wherein the residual ...

FEEDBACK METHOD FOR INTERFERENCE ALIGNMENT IN WIRELESS NETWORK

A feedback method for interference alignment in wireless network having K transmitters and K receivers is provides. The method comprising: transmitting, performed by transmitter n−1, a precoding vector of transmitter n−1 (n is a integer between 2 and K−1) to receiver n+1; calculating, performed by the receiver n+1, a precoding vector of transmitter n using the precoding vector of transmitter n−1; and transmitting, performed by the receiver n+1, the precoding vector of transmitter n to transmitter n. 1. A feedback method for interference alignment in wireless network having K transmitters and K receivers , the method comprising:transmitting, performed by transmitter n−1, a precoding vector of transmitter n−1(n is a integer between 2 and K−1) to receiver n+1;calculating, performed by the receiver n+1, a precoding vector of transmitter n using the precoding vector of transmitter n−1; andtransmitting, performed by the receiver n+1, the precoding vector of transmitter n to transmitter n.2. The method of claim 1 , further comprising;{'b': '1', 'transmitting, performed by transmitter K−1, a precoding vector of transmitter K−1 to receiver ;'}{'b': '1', 'calculating, performed by the receiver , a precoding vector of transmitter K; and,'}{'b': '1', 'transmitting, performed by receiver , its own precoding vector to transmitter K'}3. The method of claim 1 , further comprising:{'b': '1', 'transmitting, performed by transmitter K−1, a precoding vector of transmitter K−1 to receiver ;'}{'b': '1', 'calculating, performed by the receiver , a precoding vector of transmitter K; and,'}{'b': '1', 'transmitting, performed by the receiver , the precoding vector of the transmitter K.'}4. The method of claim 1 , wherein K is 4 and each of the K transmitters and the K receivers has 3 antennas.5. A feedback method for the interference alignment in wireless network having K(K is integer larger than 1) transmitters and K receivers claim 1 , the method comprising:transmitting, performed by ...

PHASE-CHANGE MEMORY DEVICE HAVING MULTI-LEVEL CELL AND A METHOD OF MANUFACTURING THE SAME

A phase change memory device including a multi-level cell and a method of manufacturing the same are provided. The device includes a first phase-change material layer to which a current is provided from a heating electrode, and a second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from a heating electrode. 1. A phase-change memory device , comprising:a first phase-change material layer to which a current is provided from a heating electrode; anda second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from a heating electrode.2. The device of claim 1 , wherein the second phase-change material layer is disposed on the first phase-change material layer.3. The device of claim 2 , wherein a width of the first phase-change material layer is smaller than that of the second phase-change material layer.4. The device of claim 1 , wherein the first and second phase-change material layers are configured to be buried within spaces having different diameters claim 1 , respectively.5. The device of claim 1 , wherein the first phase-change material layer is formed to be buried within a constant space and the second phase-change material layer is in contact with the first phase-change material layer and extends on the first phase-change material layer in a line shape.6. The device of claim 1 , wherein the first and second phase-change material layers include the same material.7. The device of claim 1 , wherein the first and second phase-change material layers include different materials from each other.8. A phase-change memory device claim 1 , comprising:a first phase-change region having a first caliber and phase-changed by a first condition; anda second phase-change region ...

METHOD AND DEVICE FOR GENERATING PRECODING MATRIX IN WIRELESS COMMUNICATION SYSTEM

Provided is a method and a device for generating a precoding matrix in a wireless communication system. The method for generating the precoding matrix comprises a step of receiving from a terminal feedback including information on the error angle θ of channel direction information (CDI), which indicates the direction of a channel direction vector, and a step of generating the precoding matrix based on the information on the error angle θ of the CDI, wherein the error angle θ of the CDI indicates the angle between the channel direction vector and a quantized channel direction vector, and includes at least one of a channel quantization error component, a channel feedback delay error component, and a channel estimation error component. 1. A method of generating a precoding matrix in a wireless communication system , the method comprising:receiving a feedback including information on an error angle θ of channel direction information (CDI) which indicates a direction of channel direction vector from a terminal, andgenerating a precoding matrix based on the information on the error angle θ of the CDI,wherein the error angle θ of the CDI indicates an angle between the channel direction vector and a quantized channel direction vector, andwherein the error angle θ of the CDI includes at least one of a channel quantization error component, a channel feedback delay error component and a channel estimation error component.2. The method of claim 1 , wherein the information on the error angle θ of the CDI is cosθ calculated per each feedback period in which the feedback is transmitted claim 1 , andwherein the cos θ is transmitted per each feedback period.4. The method of claim 1 , wherein the information on the error angle θ of the CDI is an average value of cosθ over a long period longer than a feedback period in which the feedback is transmitted claim 1 , andwherein the average value of cosθ is transmitted per the long period.6. The method of claim 1 , wherein the channel ...

METHOD AND DEVICE FOR PRECODING IN WIRELESS COMMUNICATION SYSTEM

Provided is a method and a device for precoding in a wireless communication system. The method for precoding comprises the following steps: generating a first precoding matrix, W, for deciding the transmission power of one transmission antenna from a plurality of transmission antennas as the maximum power per antenna; generating a zero forcing (ZF) precoding matrix, T, which does not influence the transmission antenna having the power which is decided as the maximum power per antenna, based on the (i−1)precoding matrix W(i=2,3, . . . ); determining a constant which has the transmission power of one transmission antenna from the rest of the transmission antennas, which do not have the transmission power as the maximum power per antenna, based on the T; and generating the 1. A method of precoding in a wireless communication system , the method comprising:{'sub': '1', '(a) generating a first precoding matrix, W, for deciding transmit power of one transmission antenna among a plurality of transmission antennas as maximum power per antenna;'}{'sub': i', 'i−1, '(b) generating a zero forcing (ZF) precoding matrix, T, which does not affect the transmission antennas whose transmit powers are decided as the maximum power per antenna, based on (i−1)th precoding matrix W(i=2,3, . . . );'}{'sub': i', 'i, '(c) determining a constant αwhich decides transmit power of one transmission antenna from the remaining transmission antennas whose transmit power are not determined as the maximum power per antenna, based on the T; and'}{'sup': 'th', 'sub': i', 'i', 'i, '(d) generating iprecoding matrix Wbased on the Tand the α,'}{'sub': 't', 'wherein the steps from (b) to (d) are repeated by incrementing i by one until a condition i=N−K+1 is satisfied,'}{'sub': 't', 'where Nis the number of the plurality of transmission antennas, and K is a number of total users using a single reception antenna.'}2. The method of claim 1 , wherein the maximum power per antenna is determined as P/N claim 1 , ...

ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME

A method of fabricating an array substrate includes forming a first metal layer, a gate insulating material layer and an oxide semiconductor material layer on a substrate; heat-treating the substrate having the oxide semiconductor material layer at a temperature of about 300 degrees Celsius to about 500 degrees Celsius; patterning the oxide semiconductor material layer, the gate insulating material layer and the first metal layer, thereby forming a gate electrode, a gate insulating layer and an oxide semiconductor layer; forming a gate line connected to the gate electrode and made of low resistance metal material; forming source and drain electrodes, a data line and a pixel electrode, the source and drain electrodes and the data line having a double-layered structure of a transparent conductive material layer and a low resistance metal material layer, the pixel electrode made of the transparent conductive material layer. 1. A method of fabricating an array substrate , comprising:sequentially forming a first metal layer, a gate insulating material layer and an oxide semiconductor material layer on a substrate including a pixel region having a switching region;heat-treating the substrate having the oxide semiconductor material layer at a temperature from about 300 degrees Celsius to about 500 degrees Celsius;patterning the oxide semiconductor material layer, the gate insulating material layer and the first metal layer, thereby forming a gate electrode in a switching region having an island shape, and a gate insulating layer and an oxide semiconductor layer which are on the gate electrode, expose an end part of the gate electrode, and have an island shape;forming a gate line which overlaps the end part of the gate electrode, is at a boundary of the pixel region and is made of low resistance metal material;forming an inter-layered insulating film on the gate line and having a first opening that exposes a center portion of the oxide semiconductor layer;forming source and ...

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first type semiconductor layer doped with an N type ion, a second type semiconductor layer formed over the first type semiconductor layer, and a silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer. 1. A semiconductor device , comprising:a first type semiconductor layer doped with an N type ion;a second type semiconductor layer formed over the first type semiconductor layer; anda silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer.2. The semiconductor device of claim 1 , wherein the first type semiconductor layer and the SiGe layer are crystallized by a spike rapid thermal annealing (RTA) process.3. The semiconductor device of claim 2 , further comprising a diffusion barrier layer interposed between the first type semiconductor layer and the second type semiconductor layer.4. The semiconductor device of claim 1 , wherein Ge content of the SiGe layer is in a range of 5% to 50%.5. The semiconductor device of claim 1 , wherein a top doping concentration of the P type ion in the SiGe layer is in a range of 1E19 atoms/cmto 1E22 atoms/cm.6. The semiconductor device of claim 1 , wherein a bottom doping concentration of the N type ion in the first type semiconductor layer is in a range of 1E19 atoms/cmto 1E22 atoms/cm.7. The semiconductor device of claim 1 , wherein the second type semiconductor layer is an intrinsic semiconductor layer.8. The semiconductor device of claim 1 , further comprising a diffusion barrier layer interposed between the first type semiconductor layer and the second type semiconductor layer.9. A method of fabricating a semiconductor device claim 1 , the method comprising:forming a first type semiconductor layer doped with an N type ion over a semiconductor substrate;forming a second type semiconductor layer over the first type semiconductor layer; ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface. 1. A semiconductor device , comprising:a second conductive-type deep well configured above a substrate to include a first ion implantation region and a first diffusion region;a first conductive-type first well configured in the second conductive-type deep well to contact the first diffusion region; anda gate electrode configured above the substrate to extend across portions of both the first ion implantation region and the first diffusion region, the gate electrode having one end portion thereof overlapped with a portion of the first conductive-type first well,wherein the first diffusion region has impurity doping concentration that is the highest at an interface between the first ion implantation region and the first diffusion region, and that decreases as moving farther away from the interface between the first ion implantation region and the first diffusion region.2. The semiconductor device of claim 1 , further comprising:a second conductive-type buried impurity layer configured below the second conductive-type deep well, the second conductive-type buried impurity layer having a uniform impurity doping concentration.3. The semiconductor device of claim 2 , wherein the uniform impurity doping concentration of the second ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface. 1. A semiconductor device , comprising:a second conductive-type deep well configured above a first conductive-type substrate;a second conductive-type buried impurity layer configured below the second conductive-type deep well to include an ion implantation region and a diffusion region;a first conductive-type first well configured in the diffusion region of the second conductive-type deep well;a gate electrode configured above the substrate to extend across portions of both the first ion implantation region and the first diffusion region, the gate electrode having one end portion thereof overlapped with a portion of the first conductive-type first well,wherein the diffusion region has impurity doping concentration that is the highest at an interface between the ion implantation region and the diffusion region, and that decreases as moving farther away from the interface between the ion implantation region and the diffusion region.2. The semiconductor device of claim 1 , wherein the ion implantation region has impurity doping concentration that is higher than that of the second conductive-type deep well.3. The semiconductor device of claim 1 , further comprising:a first conductive-type bulk pick-up region configured in the first ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode. 1. A semiconductor device , comprising:a second conductive-type well configured over a substrate;a first conductive-type body region configured over the second conductive-type well;a gate electrode which overlaps a portion of the first conductive-type body region; anda first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode,wherein the first conductive-type channel extension region is formed in the second conductive-type well in contact with the first conductive-type body region.2. A semiconductor device , comprising:a second conductive-type well configured over a substrate;a first conductive-type body region configured over the second conductive-type well;a gate electrode which overlaps a portion of the first conductive-type body region; anda first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.wherein the first conductive-type channel extension region is formed in the second conductive-type well and is spaced apart from the first conductive-type body region.3. A semiconductor device , comprising:a second conductive-type well configured over a substrate;a first conductive-type body region configured over the second conductive-type well;a gate electrode which overlaps a portion of the first conductive-type body region; and a device isolation layer configured over the substrate to define an active region;', 'a first conductive-type pickup region disposed in the first conductive-type body region;', 'a second conductive-type source region disposed ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region. 1. A method for fabricating a semiconductor device , the method comprising:forming an active region configured in or over a substrate to include a first conductive-type first deep well and a second conductive-type second deep well that form a junction therebetween;forming a first conductive-type first impurity region in the first conductive-type first deep well;forming a gate insulation layer over the substrate;forming a gate electrode extending over the junction and over a portion of the first conductive-type first deep well and a portion of the second conductive-type second deep well; andforming a second conductive-type source region in the first conductive-type first deep well on one side of the gate electrode and a second conductive-type drain region in the second conductive-type second deep well on another side of the gate electrode,wherein the first conductive-type first impurity region extends toward the junction in such a manner forming a overlap region in which the first conductive-type first impurity region overlaps with a portion of the gate ...

SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer. 1. A semiconductor memory device , comprising:{'i': 'ate;', 'an access device formed in a pillar shape on a semiconductor subs'}a first conductive layer formed over the access device;a protection layer formed on an edge of the first conductive layer to a predetermined thickness; anda lower electrode connected to the first conductive layer.2. The semiconductor memory device of claim 1 , further comprising a spacer formed on the protection layer to surround an outer circumference of the lower electrode.3. The semiconductor memory device of claim 2 , wherein the protection layer is comprised of substantially the same material as the spacer.4. The semiconductor memory device of claim 2 , wherein the protection layer includes a material having the same or similar etching properties as the protection layer.5. A method of fabricating a semiconductor memory device claim 2 , the method comprising:sequentially forming an access device, a first conductive layer, a protection layer, and a sacrificial layer on a semiconductor substrate;patterning, in a pillar shape, the sacrificial layer, the protection layer, the first conductive layer, and the access device, burying an insulating layer between pillar type structures, and performing planarization on the insulating layer to expose a surface of the sacrificial layer;removing the sacrificial layer; andremoving the protection layer.6. The method of claim 5 , wherein removing the protection layer further includes forming a spacer ...

ROTOR OF MOTOR

A rotor of a motor according to the present invention comprises: a shaft; a rotor core having a shaft insertion hole, into which the shaft is inserted and coupled; a magnet coupled to the outer peripheral surface of the rotor core; and a rotor cover comprising an upper cap and a lower cap, which cover the upper and lower portions of the rotor core and of the magnet, respectively, wherein the outer periphery of the rotor core comprises a first corner portion and a second corner portion, and the inner periphery of the magnet comprises a first inner peripheral portion, which corresponds to the first corner portion, and a second inner peripheral portion, which corresponds to the second corner portion. 1. A rotor of a motor , comprising:a shaft;a rotor core having a shaft insertion hole, into which the shaft is inserted and coupled;a magnet coupled to an outer peripheral surface of the rotor core; anda rotor cover comprising an upper cap and a lower cap, which cover upper and lower portions of the rotor core and of the magnet, respectively,wherein the outer periphery of the rotor core comprises a first corner portion and a second corner portion, and the inner periphery of the magnet comprises a first inner peripheral portion, which corresponds to the first corner portion, and a second inner peripheral portion, which corresponds to the second corner portion.2. The rotor of a motor of claim 1 , wherein the upper cap and the lower cap are connected by a first upper portion and lower portion connector which is formed along a side surface groove formed on the outer periphery surface of the rotor core.3. The rotor of a motor of claim 1 , wherein the upper cap and the lower cap are connected by a second upper portion and lower portion connector which is formed along an inner hole formed around the shaft insertion hole of the rotor core.4. The rotor of a motor of claim 1 , wherein the upper cap has an upper inclined surface with a height which gets shorter from a center of the ...

CATHODE ACTIVE MATERIAL HAVING CORE-SHELL STRUCTURE AND PRODUCING METHOD THEREOF

Disclosed is a cathode active material having a core-shell structure. The core-shell cathode active material includes a core including a lithium transition metal oxide with excellent electrochemical properties and a shell formed by coating the surface of the core with a transition metal oxide. The formation of the shell by coating a transition metal oxide on the surface of the core comprising a lithium transition metal oxide prevents the structure of the lithium transition metal oxide from collapsing and inhibits the dissolution of manganese ions, enabling the fabrication of a hybrid capacitor with improved energy density and rate characteristics. Also disclosed is a method for producing the cathode active material. 1. A core-shell cathode active material comprising a core comprising a lithium transition metal oxide and a shell formed by coating the surface of the core with a transition metal oxide.2. The core-shell cathode active material according to claim 1 , wherein the lithium transition metal oxide is selected from the group consisting of LiCoO claim 1 , LiMnO claim 1 , LiMnO claim 1 , LiNiO claim 1 , LiNiCoO(0 Подробнее

COMPOSITIONS AND METHODS FOR INHIBITING DKK-1

The present invention provides compositions and methods for inhibiting Dkk-1 for treating or preventing an inflammatory or inflammatory-related disease or disorder. 1. A composition for treating or preventing type 2 inflammation comprising an inhibitor of Dkk-1.2. The composition of claim 1 , wherein the inhibitor of Dkk-1 is at least one selected from the group consisting of a protein claim 1 , a peptide claim 1 , a peptidomemetic claim 1 , an antibody claim 1 , a ribozyme claim 1 , a small molecule chemical compound claim 1 , a nucleic acid claim 1 , a vector claim 1 , and an antisense nucleic acid molecule.3. The composition of claim 1 , wherein the inhibitor of Dkk-1 is a small molecule chemical compound.5. The composition of claim 1 , wherein the inhibitor of Dkk-1 is an anti-Dkk-1 antibody.6. The composition of claim 1 , wherein the composition further comprises a glucocorticoid.7. The composition of claim 1 , wherein the type 2 inflammation is associated with a disease or disorder.8. The composition of claim 7 , wherein the disease or disorder is selected from the group consisting of a parasite infection claim 7 , cutaneous leishmaniasis claim 7 , and asthma.9. A method for treating or preventing type 2 inflammation or a type 2 inflammation-related disease or disorder the method comprising administering a composition comprising an inhibitor of Dkk-1 to a subject in need thereof.10. The method of claim 9 , wherein the inhibitor of Dkk-1 is at least one selected from the group consisting of a chemical compound claim 9 , a protein claim 9 , a peptide claim 9 , a peptidomemetic claim 9 , an antibody claim 9 , a ribozyme claim 9 , a small molecule chemical compound claim 9 , a nucleic acid claim 9 , a vector claim 9 , and an antisense nucleic acid molecule.11. The method of claim 9 , wherein the type 2 inflammation-related disease or disorder is selected from the group consisting of a parasite infection claim 9 , cutaneous leishmaniasis claim 9 , and asthma.12. ...

Peptide analogues with an excellent moisturizing effect and use thereof

The present invention relates to a peptide analogue or a pharmaceutically acceptable salt thereof with excellent moisturizing effect, and use thereof for moisturization. More specifically, the present invention relates to a novel peptide analogue or a pharmaceutically acceptable salt thereof, a method for preparation thereof, a moisturizing cosmetic composition comprising the same as an active ingredient, and a pharmaceutical composition for prevention and treatment of xeroderma.

3D SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar. 1. A method of manufacturing a semiconductor integrated circuit device , the method comprising:forming an active pillar in a semiconductor substrate;forming an interlayer insulating layer over the interlayer insulating layer;forming a hole by etching the interlayer insulating layer so that an upper surface of the active pillar is exposed by the hole;forming a space extending from the hole down to between an upper sidewall of the active pillar and the interlayer insulating layer;forming a silicon material layer in the space; andforming an ohmic contact layer in the silicon material layer and in the active pillar.2. The method of claim 1 , wherein the forming of the silicon material layer includes:forming a polysilicon layer which fills in the space and extends over the upper surface of the active pillar.3. The method of claim 2 , wherein forming the polysilicon layer includes:performing chemical mechanical polishing against the polysilicon layer to expose an upper surface of the interlayer insulating layer, wherein the upper surface of the interlayer insulating layer is located at a level higher than the upper surface of the active pillar; andadditionally etching back the ...

COMPOSITION FOR PREVENTING OR TREATING CELL DAMAGE INCLUDING YOUNGIA DENTICULATA EXTRACT

Provided is Youngia denticulata extract being effective for prevention and treatment of diseases caused by an environmental pollution substance, and capable of protecting cell damage. 14-. (canceled)5. A composition comprising an extract of Youngia denticulata as an effective component.6. The composition according to claim 5 , which is a functional food composition.7. The composition according to claim 5 , which is a pharmaceutical composition.8. The composition according to claim 5 , which is a cosmetic composition.9. A method for treating an inflammation or reducing an inflammatory response of a subject claim 5 , comprising administering the composition of into the subject.10. The method of claim 9 , wherein the inflammation or inflammatory response is caused by a polycyclic aromatic hydrocarbon-based environmental pollution substance.11. The method of claim 10 , wherein the composition is a food composition.12. The method of claim 10 , wherein the composition is a pharmaceutical composition.13. A method for treating an inflammation or reducing an inflammatory response of a subject claim 5 , comprising applying externally the composition of on the subject.14. The method of claim 13 , wherein the composition is an external application composition for skin or hair.15. A method for detoxifying heavy metals of a subject claim 5 , comprising administering the composition of to the subject.16. The method of claim 15 , wherein the composition is a food composition. This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2016-0104925, filed on Aug. 18, 2016 and Application No. 10-2017-0096844, filed on Jul. 31, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.The following disclosure relates to a composition including Youngia denticulata extract capable of preventing or treating cell damage or generic material damage by an environmental pollution substance.As the ...

BIOTIN-CONJUGATED HEXAPEPTIDE-2 DERIVATIVE AND USE THEREOF

The present invention relates to a biotin-conjugated hexapeptide-2 derivative or a pharmaceutically acceptable salt thereof and use thereof. More particularly, the present invention relates to a biotin-conjugated hexapeptide-2 derivative or a pharmaceutically acceptable salt thereof, a preparation method thereof, a composition including the same as an active ingredient, and a method for improving wrinkles and inhibiting skin aging using the same. 2. A cosmetic composition for improving wrinkles and preventing skin aging claim 1 , comprising the peptide derivative or the pharmaceutically acceptable salt thereof of .3. The cosmetic composition according to claim 2 , wherein the cosmetic composition has a function of promoting collagen biosynthesis.4. The cosmetic composition according to claim 2 , wherein the cosmetic composition has a formulation selected from the group consisting of skin softener claim 2 , astringent lotion claim 2 , nutrient lotion claim 2 , nutrient cream claim 2 , massage cream claim 2 , eye cream claim 2 , eye essence claim 2 , essence claim 2 , cleansing cream claim 2 , cleansing lotion claim 2 , cleansing foam claim 2 , cleansing water claim 2 , pack claim 2 , powder claim 2 , body lotion claim 2 , body cream claim 2 , body essence claim 2 , body wash claim 2 , sunscreen cream claim 2 , hair dye claim 2 , shampoo claim 2 , rinse claim 2 , toothpaste claim 2 , oral refresher claim 2 , hair conditioner claim 2 , hair tonic claim 2 , lotion claim 2 , ointment claim 2 , gel claim 2 , cream claim 2 , patch and spray.5. A pharmaceutical composition for improving wrinkles and preventing skin aging claim 1 , comprising the peptide derivative or the pharmaceutically acceptable salt thereof of .6. The pharmaceutical composition according to claim 5 , wherein the pharmaceutical composition has a function of promoting collagen biosynthesis. The present invention relates to a biotin-conjugated hexapeptide-2 derivative or a pharmaceutically acceptable salt ...

PHASE-CHANGE MEMORY DEVICE HAVING PHASE-CHANGE REGION DIVIDED INTO MULTI LAYERS AND OPERATING METHOD THEREOF

A phase-change memory device including a phase-change region divided into multi layers and an operation method thereof are provided. The device includes a first phase-change layer to which a current is provided from a heating electrode, and a second phase-change layer formed with continuity to the first phase-change layer and having a different width from the first phase-change layer, and to which a current is provided from the heating electrode. The first and second phase-change layers include materials selected from a first group consisting of GeTe, GST415, GST315, GST225, GST124, GST147, and GST172 or a second group consisting of InSbSe, SnGeSe, GST, SnSbSe, and SiSbSe. The second phase-change layer includes a material different from the first phase-change layer, which is selected from the same group as the first phase-change layer and has smaller resistivity than the first phase-change layer. 1. A phase-change memory device , comprising:a first phase-change layer to which a current is provided from a heating electrode; anda second phase-change layer formed with continuity to the first phase-change layer and having a different width from the first phase-change layer, and to which a current is provided from the heating electrode,wherein the first and second phase-change layers include materials selected from a first group consisting of GeTe, GST(GeSbTe)415, GST315, GST225, GST124, GST147, and GST172 or a second group consisting of InSbSe, SnGeSe, GST, SnSbSe, and SiSbSe, andwherein the second phase-change layer includes a material different from the first phase-change layer, which is selected from the same group as the first phase-change layer and has smaller resistivity than the first phase-change layer.2. The device of claim 1 , wherein the second phase-change layer is disposed on the first phase-change layer.3. The device of claim 1 , wherein a width of the first phase-change layer is smaller than that of the second phase-change layer.4. The device of claim 1 , ...

Semiconductor device

A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end portion thereof extending over the isolation layer.

HIGH-STRENGTH STEEL HAVING EXCELLENT FRACTURE INITIATION RESISTANCE AND FRACTURE PROPAGATION ARRESTABILITY AT LOW TEMPERATURE AND METHOD OF MANUFACTURING THE SAME

An aspect of the present invention relates to a high-strength steel, having excellent fracture initiation resistance and fracture propagation arrestability at low temperature. 1. A high-strength steel having excellent fracture initiation resistance and fracture propagation arrestability at low temperature , the high-strength steel material comprising:by wt %, 0.02 to 0.09% of C, 0.005 to 0.3% of Si, 0.5 to 1.7% of Mn, 0.001 to 0.035% of Sol.Al, 0.03% or less of Nb, excluding 0%, 0.01% or less of V, excluding 0%, 0.001 to 0.02% or Ti, 0.01 to 0.1% of Cu, 0.01 to 2.0% of Ni, 0.01 to 0.5% of Cr, 0.001 to 0.5% of Mo, 0.0002 to 0.005% of Ca, 0.001 to 0.006% of N, 0.02% or less of P, excluding 0%, 0.003% or less of S, excluding 0%, 0.002% or less of 0, excluding 0%, and a balance of Fe and inevitable impurities, {'br': None, '5*C+Si+10*sol.Al≤0.6 \u2003\u2003Relational Expression 1'}, 'wherein the high-strength steel satisfies Relational Expression 1 below,'}where each element symbol indicates a content of each element by wt %, andwherein a microstructure comprises a sum of polygonal ferrite and acicular ferrite of 50 area % or higher, and comprises a martensite-austenite multiphase, an MA phase, of 3.5 area % or lower.2. The high-strength steel of claim 1 , wherein an average size of the MA phase measured in equivalent circular diameter is 2.5 μm or less.3. The high-strength steel of claim 1 , wherein the steel comprises inclusions claim 1 , and a number of inclusions having a size of 10 μm or greater is 11 count/cmor lower.4. The high-strength steel of claim 1 , wherein polygonal ferrite and acicular ferrite are not process-hardened by a hot-rolling process.5. The high-strength steel of claim 1 , wherein the steel has yield strength of 355MPa or higher claim 1 , an impact energy value of 300J or higher at −60° C. claim 1 , and a CTOD value of 0.3 mm or higher at −40° C.6. The high-strength steel of claim 1 , wherein the steel has tensile strength of 450 MPa or higher.7. ...

3D SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar. 124-. (canceled)25. A semiconductor integrated circuit device comprising:an active pillar extending upward from a substrate;a gate electrode provided over a lower sidewall of the active pillar;a drain region formed in an upper portion of the active pillar;a source region formed in the substrate between a bottom portion of the active pillar and a bottom portion of a neighboring active pillar;a gate insulating layer located between the active pillar and the gate electrode;a contact extension region extending from the gate insulating layer to over an upper sidewall of the active pillar; andan ohmic contact layer formed in the contact extension region.26. The semiconductor integrated circuit device of claim 25 , wherein the contact extension region surrounds the active pillar.27. The semiconductor integrated circuit device of claim 26 , wherein the ohmic contact layer is in electrical contact with the active pillar.28. The semiconductor integrated circuit device of claim 25 , wherein the contact extension region is in a cap shape covering the upper sidewall of the active pillar and an upper surface of the active pillar.29. The semiconductor integrated circuit device of claim ...

ANTI-SIALYL TN CHIMERIC ANTIGEN RECEPTORS

The invention provides improved compositions for adoptive cell therapies for cancers that express the glycoepitope STn on TAG-72. 1. A chimeric antigen receptor (CAR) comprising: an extracellular domain that comprises:a) an anti-sialyl Tn (STn) antibody or antigen binding fragment thereof that binds one or more epitopes of an STn antigen expressed on a glycoprotein, wherein the anti-STn antibody or antigen binding fragment thereof comprises a variable light chain sequence comprising CDRL1-CDRL3 sequences set forth in SEQ ID NOs: 1-3, 9-11, or 17-19, and a variable heavy chain sequence comprising CDRH1-CDRH3 sequences set forth in SEQ ID NOs: 4-6, 12-14, or 20-22;b) a transmembrane domain;c) one or more intracellular co-stimulatory signaling domains; andd) a primary signaling domain.2. The CAR of claim 1 , wherein the STn antigen is expressed on a glycoprotein selected from the group consisting of mucins or mucin-like glycoproteins.3. The CAR of claim 1 , wherein the STn antigen is expressed on a mucin selected from the group consisting of: mucin 1 and mucin 16.4. The CAR of claim 1 , wherein the STn antigen is expressed on a mucin-like protein.5. The CAR of claim 1 , wherein the STn antigen is expressed on tumor-associated glycoprotein 72 (TAG-72).6. The CAR of claim 1 , wherein the anti-STn antibody or antigen binding fragment is selected from the group consisting of: a Camel Ig claim 1 , Ig NAR claim 1 , Fab fragments claim 1 , Fab′ fragments claim 1 , F(ab)′2 fragments claim 1 , F(ab)′3 fragments claim 1 , Fv claim 1 , single chain Fv antibody (“scFv”) claim 1 , bis-scFv claim 1 , (scFv)2 claim 1 , minibody claim 1 , diabody claim 1 , triabody claim 1 , tetrabody claim 1 , disulfide stabilized Fv protein (“dsFv”) claim 1 , and single-domain antibody (sdAb claim 1 , Nanobody).7. The CAR of claim 1 , wherein the anti-STn antibody or antigen binding fragment is an scFv.8. The CAR of claim 1 , wherein the anti-STn antibody or antigen binding fragment thereof ...

HIGH-STRENGTH STEEL MATERIAL HAVING ENHANCED RESISTANCE TO CRACK INITIATION AND PROPAGATION AT LOW TEMPERATURE AND METHOD FOR MANUFACTURING THE SAME

An aspect of the present disclosure relates to a high-strength steel material having enhanced resistance to crack initiation and propagation at low temperature. 1. A high-strength steel material , having enhanced resistance to crack initiation and propagation at low temperature , comprising , by weight , carbon (C): 0.01% to 0.07% , silicon (Si): 0.002% to 0.2% , manganese (Mn): 1.7% to 2.5% , Sol. aluminum (Sol.Al): 0.001% to 0.035% , niobium (Nb): 0.03% or less (not including 0%) , vanadium (V): 0.01% or less (not including 0%) , titanium (Ti): 0.001% to 0.02% , copper (Cu): 0.01% to 1.0% , nickel (Ni): 0.01% to 2.0% , chromium (Cr): 0.01% to 0.5% , molybdenum (Mo): 0.001% to 0.5% , calcium (Ca): 0.0002% to 0.005% , nitrogen (N): 0.001% to 0.006% , phosphorus (P): 0.02% or less (not including 0%) , sulfur (S): 0.003% or less (not including 0%) , oxygen (O): 0.0025% or less (not including 0%) , a balance of iron (Fe) , and inevitable impurities , and satisfying relational expression (1) , {'br': None, '5*C+Si+10*sol.Al≤0.5\u2003\u2003Relational expression (1), 'wherein a microstructure of the high-strength steel material comprises polygonal ferrite and acicular ferrite in a total amount of 30 area % or more, and comprises a martensite-austenite composite phase (MA phase) in an amount of 3.0 area % or lesswhere each symbol of the element refers to a value indicating each element content in weight %.2. The high-strength steel material according to claim 1 , wherein the MA phase has an average size of 2.5 μm or less claim 1 , when measured at an equivalent circular diameter.3. The high-strength steel material according to claim 1 , wherein the steel material comprises inclusions claim 1 , wherein inclusions having a size of 10 μm or more claim 1 , among the inclusions claim 1 , has 11/cmor less.4. The high-strength steel material according to claim 1 , wherein the polygonal ferrite and the needle-shaped ferrite are not hardened by hot-rolling.5. The high-strength ...

Variable resistive memory device having a phase change structure and method of manufacturing the same

A variable resistive memory device may include a phase change region, a phase change layer, a gap-filling layer and an upper electrode. The phase change region may have a sidewall and a bottom surface. The phase change layer may have a linear shape extended along the bottom surface and the sidewall of the phase change region. The gap-filling layer may be formed in a portion of the phase change region surrounded by the phase change layer. The upper electrode may be formed on the phase change layer and the gap-filling layer.

GRAPHENE-BASED LAMINATE, METHOD OF PREPARING THE SAME, AND TRANSPARENT ELECTRODE AND ELECTRONIC DEVICE EACH INCLUDING THE GRAPHENE-BASED LAMINATE

Provided are a graphene-based laminate, a method of preparing the same, and a transparent electrode and an electronic device each including the graphene-based laminate. The graphene-based laminate includes a substrate, a graphene layer including graphene and disposed on at least one surface of the substrate, and a metal oxide layer disposed on at least one surface of the graphene layer, wherein the metal oxide layer includes a metal oxide having a greater work function than that of the graphene, and the metal oxide layer includes the metal oxide in an amount of 1 μg to 1 mg per unit area of 1 cmof the graphene layer. 1. A graphene-based laminate comprising:a substrate;a graphene layer comprising graphene, and disposed on at least one surface of the substrate; anda metal oxide layer disposed on at least one surface of the graphene layer,wherein the metal oxide layer comprises a metal oxide having a greater work function than that of the graphene, and{'sup': '2', 'wherein the metal oxide layer comprises the metal oxide in an amount of 1 μg to 1 mg per unit area of 1 cmof the graphene layer.'}2. The graphene-based laminate of claim 1 , wherein a thickness of the metal oxide layer is from 1 nm to 200 nm.3. The graphene-based laminate of claim 1 , wherein the metal oxide layer occupies an area of 3% to 100% of a total area of the graphene layer.4. The graphene-based laminate of claim 1 , wherein the metal oxide comprises MoO claim 1 , VO claim 1 , CrO claim 1 , NiO claim 1 , WO claim 1 , or a combination thereof.5. The graphene-based laminate of claim 1 , wherein the graphene layer is a single layer.6. The graphene-based laminate of claim 1 , wherein the substrate comprises polyethylene terephthalate claim 1 , polycarbonate claim 1 , polyimide claim 1 , polyethylene naphthalate claim 1 , or a glass substrate.7. The graphene-based laminate of claim 1 , wherein the graphene-based laminate has a sheet resistance reduction ratio of 10% or greater claim 1 , and {'br': None, ' ...

FIXED AND ROTATING CART CASTER

The present invention relates to a fixed and rotating cart caster that is installed on each of the edges of a bottom surface of a manned and unmanned cart to carry a product through a rolling motion, and more particularly, to a fixed and rotating cart caster that is automatically converted into a fixed or rotating caster according to a forward/backward traveling direction of a cart to ensure safe travel and thereby easily carry a product and improve work conditions. According to the present invention, since the fixed and rotating cart caster is automatically converted into a fixed or rotating caster by an operation of a fixed and rotating unit including an auxiliary wheel that is closely attached to a wheel according to the forward/backward movement of the cart so as to rotate in only one direction and a fixing pin inserted into a coupling hole of a fixing plate, safe travel may be ensured in order to easily carry a product and improve work conditions. 1. A fixed and rotating cart caster comprising:a fixing plate fixedly installed at a bottom surface of the cart, wherein a combination section is formed at the middle of the bottom surface and a coupling recess is formed at one side of the combination section;a bracket formed at an upper surface thereof with a combination shaft rotationally combined with the combination section formed at the fixing plate, and formed at one side thereof with an inserting hole positioned at the same vertical line as the coupling recess;a wheel eccentrically combined to a lower side of inside of the bracket so as to perform a rolling motion; anda fixing and rotating unit comprising:a rotating plate installed at an upper side of the inside of the bracket via a rotating shaft so as to be able to perform seesaw motion;a fixing pin installed at one side of the rotating plate and inserted in the coupling recess of the fixing plate by upwardly penetrating the inserting hole of the bracket so as to restrain the rotation of the fixing plate and ...

WINDOW HAVING A RAINWATER GUIDE DEVICE ATTACHED THERETO

A rainwater guide device is coupled to an outer side of the rail portion to be adjacent to the rainwater drainage hole, wherein the rainwater guide device includes a rainwater receiving portion defined at one closed side end thereof to receive the rainwater from the drainage hole and having an open top, and a rainwater outlet defined at the other open side end thereof, wherein the bottom plate includes a tilted plate tilted downwards from the rainwater receiving portion to the rainwater outlet in a longitudinal direction thereof, and two rainwater guide plates, each guide plate having a first side coupled to the tilted plate and a second side coupled to a corresponding longitudinal side plate, wherein each of the rainwater guide plates is tilted downwardly from the second side to the first side. 1wherein the widow includes a window frame having a rail portion having a rainwater drainage hole formed in a side face thereof,wherein the rainwater guide device is coupled to an outer side of the rail portion to be adjacent to the rainwater drainage hole,wherein the rainwater guide device includes a horizontally elongate bottom plate, and two parallel facing-away longitudinal plates and a single transverse plate, all of the side plates being coupled to the bottom plate,wherein the rainwater guide device includes a rainwater receiving portion defined at one closed side end thereof to receive the rainwater from the drainage hole and having an open top, and a rainwater outlet defined at the other open side end thereof, through which the rainwater may flow out of the device,wherein the bottom plate includes a tilted plate tilted downwards from the rainwater receiving portion to the rainwater outlet in a longitudinal direction thereof, and two rainwater guide plates, each guide plate having a first side coupled to the tilted plate and a second side coupled to a corresponding longitudinal side plate, wherein each of the rainwater guide plates is tilted downwardly from the second ...

PHASE CHANGE MEMORY DEVICE HAVING SELF-ALIGNED BOTTOM ELECTRODE AND FABRICATION METHOD THEREOF

A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer. 14-. (canceled)5. A method of fabricating a semiconductor memory device , the method comprising:sequentially forming an access device, a first conductive layer, a protection layer, and a sacrificial layer on a semiconductor substrate;patterning, in a pillar shape, the sacrificial layer, the protection layer, the first conductive layer, and the access device, burying an insulating layer between pillar type structures, and performing planarization on the insulating layer to expose a surface of the sacrificial layer;removing the sacrificial layer; andremoving the protection layer.6. The method of claim 5 , wherein removing the protection layer further includes forming a spacer insulating layer on the semiconductor substrate in which the sacrificial layer is removed claim 5 , and spacer-etching the spacer insulating layer.7. The method of claim 6 , wherein the spacer insulating layer is formed using substantially the same material as the protection layer.8. The method of claim 6 , wherein the spacer insulating layer is formed using a material having the same or similar etching properties as the protection layer.9. The method of claim 5 , further comprising forming a lower electrode to be connected to the first conductive layer after the removing of the protection layer.10. The method of claim 5 , wherein the protection layer is formed using a material resistant to a material used in removing the sacrificial layer.11. The method of claim 5 , further comprising forming a ...

Positive Electrode Active Material for Lithium Secondary Battery and Lithium Secondary Battery

Provided is a lithium secondary battery which includes a positive electrode, a negative electrode, a separator interposed between the positive electrode and the negative electrode, and an electrolyte, wherein the positive electrode includes a lithium composite transition metal oxide powder having a layered structure and a nickel content accounting for 85 atm % or more of total transition metals, and wherein the lithium composite transition metal oxide powder undergoes a 3% or less change in lithium-oxygen (Li—O) interlayer spacing in a state-of-charge (SOC) range of 58% to 72%. 1. A lithium secondary battery comprising:a positive electrode;a negative electrode;a separator interposed between the positive electrode and the negative electrode; andan electrolyte,wherein the positive electrode includes, as a positive electrode active material, a lithium composite transition metal oxide powder having a layered structure and a nickel content accounting for 85 atm % or more of total transition metals,wherein the lithium composite transition metal oxide powder undergoes a 3% or less change in lithium-oxygen (Li—O) interlayer spacing in a state-of-charge (SOC) range of 58% to 72%.2. The lithium secondary battery of claim 1 , wherein the lithium composite transition metal oxide powder undergoes a 1% or less change in the Li—O interlayer spacing in the SOC range of 58% to 72%.3. The lithium secondary battery of claim 1 , wherein claim 1 , in the lithium composite transition metal oxide powder claim 1 , a Li—O interlayer spacing at 100% SOC is greater than or equal to a Li—O interlayer spacing at 0% SOC.4. The lithium secondary battery of claim 1 , wherein the lithium composite transition metal oxide is represented by Chemical Formula 1:{'br': None, 'sub': x', 'a', 'b', 'c', 'd', '2, 'Li[NiCoMnM]O\u2003\u2003[Chemical Formula 1]'}wherein, in Chemical Formula 1,M is one or more elements selected from the group consisting of W, Cu, Fe, V, Cr, Ti, Zr, Zn, Al, In, Ta, Y, La, Sr, Ga, ...

PHASE-CHANGE MEMORY DEVICE HAVING PHASE-CHANGE REGION DIVIDED INTO MULTI LAYERS AND OPERATING METHOD THEREOF

A phase-change memory device including a multi-level cell and an operation method thereof are provided. The device includes a first phase-change material layer to which a current is provided from a heating electrode, and a second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from the heating electrode. The second phase-change material layer includes a material having smaller resistivity and a lower crystallization rate than the first phase-change material layer. 1. A phase-change memory device , comprising:a first phase-change material layer to which a current is provided from a heating electrode; anda second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from the heating electrode,wherein the second phase-change material layer includes a material having smaller resistivity and a lower crystallization rate than the first phase-change material layer.2. The device of claim 1 , wherein the second phase-change material layer is disposed on the first phase-change material layer.3. The device of claim 2 , wherein a width of the first phase-change material layer is smaller than that of the second phase-change material layer.4. The device of claim 1 , wherein the first and second phase-change material layers are configured to be buried within spaces having different diameters claim 1 , respectively.5. The device of claim 1 , wherein the first phase-change material layer is formed to be buried within a constant space and the second phase-change material layer is in contact with the first phase-change material layer and extends on the first phase-change material layer in a line shape.6. A phase-change memory device claim 1 , comprising:a first phase-change region having a ...

MEMORY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME

A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern. 1. A memory device , comprising:a first memory cell disposed at an intersection of first and second conductive lines, the first and the second conductive lines extending in first and second directions, respectively;a second memory cell spaced apart from the first memory cell by a first distance in the first direction;a third memory cell spaced apart from the first memory cell by a second distance in the second direction;a first insulating pattern disposed between the first memory cell and the second memory cell; anda second insulating pattern disposed between the first memory cell and the third memory cell, the second insulating pattern having a lower thermal conductivity than the first insulating pattern.2. The memory device of claim 1 , wherein the second memory cell has a first thermal resistance with respect to the first memory cell claim 1 , andwherein the third memory cell has a second thermal resistance with respect to the first memory cell, the second distance being shorter than the first distance, the second thermal resistance being equal to or greater than the first thermal resistance.3. The memory device of claim 1 , wherein the second and the third memory cells are provided adjacent to the first memory cell claim 1 , ...

ADENOVIRUS PRODUCING NOVEL CELL LINE AND THE USE THEREOF

The present invention relates to a cell line in which an expression construct is introduced into a genomic DNA, the expression construct including: (a) a promoter operable in animal cells and heterologous to adenoviruses; and (b) a modified adenovirus E1 coding gene sequence of SEQ ID NO:1 operatively linked to the promoter. According to the present invention, the cell line of the present invention is a novel cell line which is less likely to produce a replication competent adenovirus (RCA). The adenovirus producing cell line of the present invention has a low possibility of producing RCA due to homologous recombination, when compared with conventional cell lines. Therefore, this makes it possible to regulate the required amount of virus during gene therapy using the adenovirus and prevent tissue damage and toxic effects caused by overproduction of the adenovirus. Also, the cell line of the present invention shows superior adenovirus producing ability, as compared with an HEK293 cell which is one of conventional adenovirus producing cell lines. Thus, it is possible to produce a time and cost-saving replication incompetent adenovirus. Therefore, the cell line of the present invention effectively produces a replication incompetent adenovirus and provides a safe and effective dose of adenovirus during gene therapy. 1. A cell line in which an expression construct is introduced into a genomic DNA , the expression construct including: (a) a promoter operable in animal cells and heterologous to adenoviruses; and (b) a modified adenovirus E1 coding gene sequence operatively linked to the promoter , wherein the modified adenovirus E1 coding gene sequence is deficient in an E1a TATA signal and an E1b polyadenylation signal from a sequence of the native E1 gene and includes an E1a coding sequence , an E1a polyadenylation signal , an E1b TATA signal , an E1b 19K coding sequence , and an E1b 55K coding sequence.2. The cell line of claim 1 , wherein the cell line is derived from ...

SYSTEM AND METHOD FOR EVALUATING PERFORMANCE OF INFRASTRUCTURE

Disclosed herein are a system and method for evaluating the performance of infrastructure, in which a condition rating according to a result of a survey targeting experts is expressed as a sequentially distributed probability distribution function using a fuzzy membership function and a comprehensive performance measure score is more accurately expressed as a probability distribution function, thereby accurately evaluating a comprehensive performance measure rating. Also, a utility value is derived using a utility function and usable and functional evaluation measures for each facility of the infrastructure are collected, thereby comprehensively determining subjective performance evaluation measures of the infrastructure. 1. A system for evaluating the performance of infrastructure which comprises roads , railways , harbors , dams , bridges , airports , rivers , water supplies , and fishing ports , the system comprising:{'b': '110', 'a comprehensive facility performance measure setting unit () which selects a comprehensive performance measure for each facility, which is defined according to customer value items preset for each facility of the infrastructure;'}{'b': '120', 'a facility performance measure setting unit () which defines a facility performance measure which quantitatively indicates the comprehensive facility performance measure for each facility of the infrastructure using a fuzzy membership function according to properties of the comprehensive facility performance measure;'}{'b': '130', 'a facility performance measure utility function determination unit () which determines a utility function for each facility performance measure corresponding to an effect value selectively given within a range from 0% to 100% utilizing an expert survey through normalization using a utility theory;'}{'b': '140', 'a facility performance measure weight determination unit () which assigns a weight for each facility performance measure using an analytic hierarchy process ( ...

DIGITIZER AND FLEXIBLE DISPLAY DEVICE COMPRISING THE SAME

A flexible digitizer comprising a flexible substrate and a first and a second electrodes having thicknesses of 2000 Å to 1 μm is provided. The digitizer according to the present invention has sufficient flex resistance for application to a flexible display device with superior electrical characteristics and visibility. 1. A flexible digitizer comprising:a flexible substrate;a first electrode disposed on the flexible substrate and having a thickness of 2000 Å to 1 μm;a first insulation layer disposed on the first electrode and having a through hole exposing the first electrode; anda second electrode disposed on the first insulation layer to be electrically connected to the first electrode via the through hole and having a thickness of 2000 Å to 1 μm.2. The flexible digitizer of claim 1 , wherein the thicknesses of the first and the second electrodes are 3000 to 5000 Å.3. The flexible digitizer of claim 1 , wherein the first and the second electrodes have line widths of 3 to 30 μm.4. The flexible digitizer of claim 3 , wherein the first and the second electrodes have line widths of 3 to 10 μm.5. The flexible digitizer of claim 1 , wherein the first and the second electrodes are formed by sputtering.6. The flexible digitizer of claim 1 , further comprising a second insulation layer disposed on the second electrode.7. The flexible digitizer of claim 1 , further comprising a protective layer disposed on the flexible substrate claim 1 , wherein the first electrode is disposed on the protective layer.8. The flexible digitizer of claim 1 , wherein the total thickness of the digitizer is less than or equal to 50 μm.9. A flexible display device comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a digitizer according to ; and'}a display layer disposed under the digitizer.10. A flexible display device comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'a digitizer according to ; and'}a display layer disposed under the digitizer.11. A flexible display device ...

DIGITIZER AND METHOD OF PREPARING THE SAME

A digitizer in which a touch sensing electrode of a self-capacitive type touch sensor and a first electrode of the digitizer are formed on the same layer is provided. The digitizer according to the present invention has a high level of pressure sensing and a simplified manufacturing process. 1. A digitizer comprising:a substrate;a touch sensing electrode and a first digitizer electrode disposed on the substrate;an insulation layer formed on the touch sensing electrode and the first digitizer electrode and having a through hole exposing the first digitizer electrode;a second digitizer electrode formed on the insulation layer and a first digitizer electrode bridge formed on the insulation layer to be electrically connected to the first digitizer electrode via the through hole; anda passivation layer formed on the second digitizer electrode and the first digitizer electrode bridge.2. The digitizer of claim 1 , wherein the substrate is a flexible substrate.3. The digitizer of claim 1 , wherein the second digitizer electrode and the first digitizer electrode bridge are made of a metal.4. The digitizer of claim 1 , wherein the second digitizer electrode does not overlap with the touch sensing electrode.5. The digitizer of claim 1 , further comprising a touch sensor trace disposed on the substrate.6. The digitizer of claim 1 , wherein the second digitizer electrode is formed in a direction of a short axis of the digitizer.7. The digitizer of claim 1 , wherein the second digitizer electrode is formed to have two or more loops in a longitudinal direction.8. A display device comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a digitizer according to ; and'}a display layer disposed under the digitizer.9. A method of preparing a digitizer comprising the steps of:forming a touch sensing electrode and a first digitizer electrode on a substrate;forming an insulation layer having a through hole exposing the first digitizer electrode on the touch sensing electrode and the ...

Digitizer and method of preparing the same

A digitizer in which a second electrode of the digitizer is formed in a non-patterned portion of a touch sensing electrode of a mutual-capacitive type touch sensor is provided. The digitizer according to the present invention has a high level of pressure sensing, a simplified manufacturing process, and excellent visibility.

METHOD FOR FABRICATING SEMICONDUCTOR APPARATUS

A method for fabricating a semiconductor apparatus includes setting a semiconductor substrate in a process chamber, increasing an internal temperature of the process chamber to a predetermined temperature for pyrolyzing a source gas, supplying the source gas to the inside of the process chamber and pyrolyzing ions of the source gas to remain on the semiconductor substrate, and forming the ohmic contact layer by supplying a reaction gas to the inside of the process chamber, wherein the reaction gas is reacted with non-metal ions pyrolyzed from source gas. 1. A method for fabricating a semiconductor apparatus including an ohmic contact layer , the method comprising:setting a semiconductor substrate in a process chamber;increasing an internal temperature of the process chamber to a predetermined temperature for pyrolyzing a source gas;remaining pyrolyzed ions of the source gas on the semiconductor substrate by supplying the source gas to the process chamber and pyrolyzing ions of the source gas; andforming the ohmic contact layer by supplying a reaction gas to the process chamber and supplying an inert gas to the process chamber to form a plasma atmosphere, wherein the reaction gas reacts with non-metal ions pyrolyzed from the source gas in a plasma atmosphere.2. The method of claim 1 , wherein the semiconductor substrate includes a switching device layer.3. The method of claim 1 , wherein the predetermined temperature includes temperatures from 450° C. to 1000° C.4. The method of claim 1 , further comprising:supplying a purge gas to the process chamber.5. The method of claim 4 , further comprising:repeatedly increasing of the temperature of the process chamber, the supplying of the source gas, the forming of the ohmic contact layer, and the supplying of the purge gas to form the ohmic contact layer with a predetermined thickness.6. The method of claim 1 , wherein the source gas includes a metal ion to be formed as the ohmic contact layer.7. The method of claim 6 , ...

PHOTOSENSITIVE RESIN COMPOSITION AND ORGANIC INSULATING FILM PREPARED THEREFROM

Disclosed herein are a photosensitive resin composition and an organic insulating film prepared therefrom. By optimizing the weight average molecular weight of a copolymer, and using a specific solvent in the photosensitive resin composition, a coated film obtained therefrom may have high planarity property and patterns with high resolution. Accordingly, the photosensitive resin composition may be used as a material for an organic insulating film simultaneously functioning as white pixels. 1. A photosensitive resin composition , comprising:(1) a copolymer having a weight average molecular weight of 3,000 to 7,000;(2) a polymerizable unsaturated compound;(3) a photopolymerization initiator; and(4) a solvent comprising a high boiling point solvent having a boiling point of 180° C. or higher in an atmospheric pressure.2. The photosensitive resin composition of claim 1 , wherein the high boiling point solvent is at least one selected from the group consisting of gamma butyrolactone claim 1 , diethylene glycol monomethyl ether claim 1 , diethylene glycol monobutyl ether claim 1 , propylene glycol diacetate claim 1 , diethylene glycol monoethyl ether claim 1 , diethylene glycol monoethyl ether acetate claim 1 , and diethylene glycol monobutyl ether acetate.3. The photosensitive resin composition of claim 1 , wherein the high boiling point solvent is comprised in an amount of 5 to 60 wt % on the basis of a total amount of the solvent.4. The photosensitive resin composition of claim 1 , wherein the high boiling point solvent is comprised in an amount of 15 to 40 wt % on the basis of a total amount of the solvent.5. The photosensitive resin composition of claim 1 , wherein the copolymer (1) comprises (1-1) a structural unit derived from an ethylenically unsaturated carboxylic acid claim 1 , an ethylenically unsaturated carboxylic anhydride claim 1 , or a mixture thereof claim 1 , and (1-2) a structural unit derived from an ethylenically unsaturated compound containing an ...

COSMETIC COMPOSITION FOR ANTI-AGING OR ALLEVIATING SKIN REDNESS, AND MEDICINAL COMPOSITION FOR PREVENTING AND TREATING SKIN INFLAMMATORY DISEASES, CONTAINING COMPOUND INDUCING INCREASE IN EXPRESSION OF ADIPONECTIN

Provided are a cosmetic composition for anti-aging or alleviating skin redness, and a medicinal composition for treating and preventing skin inflammatory diseases caused by light, containing a compound inducing an increase in expression of adiponectin or a pharmaceutically acceptable salt thereof. 3. The cosmetic composition of claim 1 , wherein the compound inducing an increase in expression of adiponectin or the pharmaceutically acceptable salt thereof is contained in a content of 0.0001 to 10 wt %.4. The cosmetic composition of claim 1 , further comprising one or two or more selected from a perfume claim 1 , a colorant claim 1 , a disinfectant claim 1 , an anti-oxidant claim 1 , a preservative claim 1 , a moisturizer claim 1 , a stabilizer claim 1 , an emulsifier claim 1 , a thickener claim 1 , a liquid crystal membrane reinforcing agent claim 1 , a pigment claim 1 , an excipient claim 1 , a diluent claim 1 , inorganic salts claim 1 , and a synthetic polymer material.5. The cosmetic composition of claim 1 , wherein the cosmetic composition is used to prevent or improve wrinkles claim 1 , skin-aging claim 1 , or skin redness caused by photo-aging.6. The cosmetic composition of claim 1 , wherein a formulation of the cosmetic composition is a suspension claim 1 , an emulsion claim 1 , a paste claim 1 , a gel claim 1 , a cream claim 1 , a lotion claim 1 , a powder claim 1 , a soap claim 1 , a surfactant-containing cleansing formulation claim 1 , an oil claim 1 , a powder foundation claim 1 , emulsion foundation claim 1 , a wax foundation claim 1 , or a spray.9. The cosmetic composition of claim 7 , wherein the compound inducing an increase in expression of adiponectin or the pharmaceutically acceptable salt thereof is contained in a content of 0.0001 to 10 wt %.10. The cosmetic composition of claim 7 , further comprising one or two or more selected from a perfume claim 7 , a colorant claim 7 , a disinfectant claim 7 , an anti-oxidant claim 7 , a preservative claim 7 ...

PHOTOSENSITIVE RESIN COMPOSITION AND ORGANIC INSULATING FILM PREPARED THEREFROM

Disclosed herein are a photosensitive resin composition and an organic insulating film prepared therefrom. By optimizing the weight average molecular weight of an alkali-soluble resin and the amount of each component in the photosensitive resin composition, a coated film obtained therefrom may have high planarity property and patterns with high resolution. Accordingly, the photosensitive resin composition may be used as a material for an organic insulating film simultaneously functioning as white pixels in a liquid crystal display. 1. A photosensitive resin composition , comprising:(1) an alkali-soluble resin having a weight average molecular weight of 1,000 to 5,000;(2) a photopolymerizable compound; and(3) a photopolymerization initiator;wherein the components (1), (2), and (3) are included in amounts of 3 to 48 wt %, 50 to 95 wt %, and 0.5 to 15 wt %, respectively, based on a total solid content of the photosensitive resin composition.2. The photosensitive resin composition of claim 1 , wherein the alkali-soluble resin (1) is a copolymer comprising (1-1) a structural unit derived from an ethylenically unsaturated carboxylic acid claim 1 , an ethylenically unsaturated carboxylic anhydride claim 1 , or a mixture thereof claim 1 , and (1-2) a structural unit derived from an ethylenically unsaturated compound containing an aromatic ring.3. The photosensitive resin composition of claim 1 , wherein the alkali-soluble resin (1) has a weight average molecular weight of 3 claim 1 ,000 to 5 claim 1 ,000.4. The photosensitive resin composition of claim 1 , wherein the photosensitive resin composition comprises the components (1) claim 1 , (2) claim 1 , and (3) in amounts of 8 to 38 wt % claim 1 , 60 to 90 wt % claim 1 , and 1 to 10 wt % claim 1 , respectively claim 1 , based on a total solid content of the photosensitive resin composition.5. The photosensitive resin composition of claim 1 , wherein the photopolymerization initiator is an oxime compound.6. An organic ...

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material. 1. An electronic device comprising a semiconductor memory , wherein the semiconductor memory comprises:a plurality of memory cells each including a variable resistance layer;a substituted dielectric layer filling a space between the plurality of memory cells; andan unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells,wherein the unsubstituted dielectric layer includes a flowable dielectric material.2. The electronic device of claim 1 , wherein the substituted dielectric layer includes Si—O bonds claim 1 , and the unsubstituted dielectric layer includes Si—N bonds claim 1 , Si—H bonds claim 1 , or both claim 1 , andwherein the space between the plurality of memory cells includes a plurality of trenches, each of the trenches being disposed between neighboring memory cells.3. The electronic device of claim 1 , wherein the substituted dielectric layer includes SiO claim 1 , and the unsubstituted dielectric layer includes silazane ((SiHNH)).4. The electronic device of claim 1 , wherein each of the plurality of memory cells includes a material having a variable resistance characteristic claim 1 , the material being a phase-change material or including a metal oxide.5. The electronic device of claim 1 , wherein each of the memory cells further includes a selection element layer controlling access to the variable resistance layer.6. The electronic device of claim 1 , wherein the semiconductor memory further includes a capping layer disposed ...

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both. 1. An electronic device comprising a semiconductor memory , wherein the semiconductor memory comprises:a substrate including a first portion in a first region and a second portion in a second region;a plurality of memory cells disposed over the first portion of the substrate;a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; anda second insulating layer disposed over the first insulating layer, andwherein the first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.2. The electronic device according to claim 1 , wherein a thickness of the first insulating layer in the second region is smaller than that of the first insulating layer in the first region.3. The electronic device according to claim 1 , wherein a thickness of the first insulating layer in the second region is smaller than a thickness of the second insulating layer.4. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:a contact plug penetrating the second ...

CHIMERIC ANTIGEN RECEPTOR COMPRISING ANTI C-MET ANTIBODY OR ANTIGEN BINDING FRAGMENT THEREOF, AND USE THEREOF

The present invention relates to a chimeric antigen receptor comprising a c-Met binding domain, and a use thereof. The chimeric antigen receptor comprising a c-Met domain, of the present invention, can be effectively usable as an agent for treating various diseases associated with c-Met expression.

A process of preparing microspheres for sustained release having improved dispersibility and syringeability

Method for embedding and extracting digital data in images and video

A method for digital watermarking and, in particular, for digital data hiding of significant amounts of data in images and video. The method employs a discrete wavelet transform for embedding gray scale images which can be as great as 25% of the host image data. A simple control parameter is used that can be tailored to either hiding or watermarking purposes, and is robust to operations such as JPEG compression. The method also uses noise-resilient channel codes based on multidimensional lattices which can provide for embedding signature data such as gray-scale or color images. Furthermore, embedded image data can be recovered in the absence of the original host image by inserting the data into the host image in the DCT domain by encoding the signature DCT coefficients using a lattice coding scheme before embedding, checking each block of host DCT coefficients for its texture content, and appropriately inserting the signatured codes depending on a local texture measure. The method further provides for source coding the signature data by vector quantization, where the indices are embedded in the host by perturbing it using orthogonal transform domain vector perturbations. The transform coefficients of the parent data are grouped into vectors, and the vectors are perturbed using noise-resilient channel codes derived from multidimensional lattices. The perturbations are constrained by a maximum allowable mean-squared error that can be introduced in the host. Also, speech can be hidden in video by wavelet transforming the host video frame by frame, and perturbing vectors of coefficients using lattice channel codes to represent hidden vector quantized speech. The embedded video is subjected to H.263 compression before retrieving the hidden speech.

Adenovirus producing novel cell line and the use thereof

Method for Preparing Positive Electrode Active Material for Lithium Secondary Battery and Positive Electrode Active Material Prepared Thereby

A positive electrode material, a positive electrode including the same, a lithium battery including the same, and a method of preparing the same are disclosed herein. In some embodiments, a method of preparing a positive electrode active material including forming a first coating layer on a surface of a lithium transition metal oxide represented by Formula 1 using a basic aqueous solution containing a coating element M1 (where M1 includes at least one selected from sodium (Na) and aluminum (Al)), dry-mixing the lithium transition metal oxide having the first coating layer formed on a surface thereof, and a raw material containing a coating element M2 (where M2 includes boron (B)) and heat treating the mixture to form a second coating layer.

Photonic crystal fiber coupler and fabricating method thereof

Disclosed is a photonic crystal-fiber coupler that can distribute light while maintaining the inherent optical properties of photonic crystal fibers. The inventive photonic crystal-fiber coupler comprises at least two photonic crystal fibers and at least one coupling region longitudinally formed along the part of each photonic crystal fiber. Each photonic crystal fiber has a core portion and a cladding portion and includes a plurality of longitudinal holes formed in such a manner to surround the core portion.

LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME

Procédé de fabrication d'un affichage à cristaux liquides consistant à : fournir un premier substrat ; former une électrode de grille (121) et une ligne de grille (116) sur le premier substrat ; former une première couche isolante sur le premier substrat ; former un motif actif, une couche de contact ohmique et une couche de prévention de diffusion au niveau d'une partie supérieure de l'électrode de grille (121) par le biais d'une gravure à sec, et former des électrodes de source (122) et de drain (123) sur la couche de prévention de diffusion en utilisant une gravure humide ; former une seconde couche isolante sur le premier substrat ; former un trou de contact (140) en éliminant une partie de la seconde couche isolante et exposer une partie de l'électrode de drain (123); former une électrode de pixel (118) connectée électriquement à l'électrode de drain (123) via le trou de contact (140); et fixer les premier et second substrats, la couche de prévention de diffusion comprenant une pointe métallique formé en saillie par rapport aux électrodes de source (122) et de drain (123) par le biais d'une gravure à sec. A method of manufacturing a liquid crystal display comprising: providing a first substrate; forming a gate electrode (121) and a gate line (116) on the first substrate; forming a first insulating layer on the first substrate; forming an active pattern, an ohmic contact layer and a diffusion prevention layer at an upper portion of the gate electrode (121) by dry etching, and forming source electrodes ( 122) and drain (123) on the diffusion prevention layer using wet etching; forming a second insulating layer on the first substrate; forming a contact hole (140) by removing a portion of the second insulating layer and exposing a portion of the drain electrode (123); forming a pixel electrode (118) electrically connected to the drain electrode (123) via the contact hole (140); and affixing the first and second substrates, the diffusion ...

LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME

A liquid crystal display device including a gate electrode and a gate line formed on a first substrate, a first insulating layer formed on the first substrate, an active pattern, an ohmic-contact layer, and a diffusion preventing layer formed on the gate electrode, a data line to cross source and drain electrodes and the gate line formed on the diffusion preventing layer to define a pixel area, a second insulating layer formed on the first substrate, a contact hole formed by removing a portion of the second insulating layer and exposing a portion of the drain electrode, a pixel electrode electrically connected with the drain electrode via the contact hole, and a second substrate attached with the first substrate in a facing manner, wherein the diffusion preventing layer comprises a metal tip protruded to the side of the source and drain electrodes.

Anti-sialyl Tn chimeric antigen receptors

The invention provides improved compositions for adoptive cell therapies for cancers that express the glycoepitope STn on TAG-72.

Method for representing description language and data structure to update ipmp tool, ipmp tool updating method and client apparatus using the same

The present invention relates to a language representation method and data structure for updating an IPMP tool, a method for updating an IPMP tool using the same and a client apparatus using the same in protection and management of multimedia contents, by which the IPMP tool can be represented dynamically in order to provide convenience to users. In the language representation method for updating an IPMP tool in an MPEG-21 multimedia framework, an update element, which describes update information of the IPMP tool, is defined as a higher level element; and a location element, which has information on a location allowing the IPMP tool to be carried thereto, is described as a lower level element of the update element.

Iris recognition system

The present invention relates to an iris recognition system which can extract an iris image of the user, by upwardly and downwardly rotating around a hinge bracket in order to be exactly rapidly controlled to a position of the user's eyes. The conventional iris recognition system has disadvantages in that the system size is huge, the time for obtaining the iris image is quite long, and the system is difficult to handle. Accordingly, the iris recognition system includes: an optical imager for obtaining an iris image of the user at an optimal state, an inner casing at which the optical imager is disposed, an outer casing for supporting the inner casing, and surrounding surfaces of the inner casing, except for the front surface thereof, a control unit for receiving iris images outputted from the optical imager, and controlling the optical imager and a hinge bracket disposed at both side portions of the outer casing, for supporting the inner casing, and enabling the inner casing to upwardly and downwardly rotate. As a result, the system size is small, and the iris image can be easily rapidly precisely obtained.

Composition and microsphere for controlled-release of exendin, and method of preparing the same

A controlled-release composition and controlled-release microspheres containing an exendin as an active ingredient, and a method of preparing the same are provided. More specifically, a controlled-release composition containing an exendin as an active ingredient, a biodegradable polymer with a specific viscosity, and coating materials, having high bioavailability and showing sustained release of the active ingredient in an effective concentration for a certain period without an excessive initial burst of the active ingredient; controlled-release microspheres containing a core including an exendin as an active ingredient and a biodegradable polymer, and a coating layer coating the core; and a method of preparing controlled-release microspheres including the steps of mixing an exendin, a biodegradable polymer, and a solvent, removing the solvent from the mixture to prepare hardened microspheres, and coating the hardened microspheres to form a coating layer on the surface of each microsphere, are provided.

High-strength steel material having enhanced resistance to brittle crack propagation and break initiation at low temperature and method for manufacturing same

An aspect of the present invention relates to a high-strength steel material, having enhanced resistance to brittle crack propagation and break initiation at a low temperature, which comprises in weight % 0.01-0.07% of C, 0.002-0.2% of Si, 1.7-2.5% of Mn, 0.001-0.035% of Sol.Al, 0.03% or less of Nb (not including 0%), 0.01% or less of V (not including 0%), 0.001-0.02% of Ti, 0.01-1.0% of Cu, 0.01-2.0% of Ni, 0.01-0.5% of Cr, 0.001-0.5% of Mo, 0.0002-0.005% of Ca, 0.001-0.006% of N, 0.02% or less of P (not including 0%), 0.003% or less of S (not including 0%) and 0.0025% or less of O (not including 0%) with a balance of Fe, and inevitable impurities, satisfies relational expression (1) below, has a microstructure comprising polygonal ferrite and needle-shaped ferrite of the total of 30 area % or greater, and comprises 3.0 area % or less of a martensite-austenite (MA) composite. Relational expression (1): 5 ∗ C + Si + 10 ∗ sol.Al # 0.5 (In relational expression (1), each symbol for the element is a value indicating each element content in weight %.)

Compositions and methods for inhibiting Dkk-1

The present invention provides compositions and methods for inhibiting Dkk-1 for treating or preventing an inflammatory or inflammatory-related disease or disorder.

Display device of operation limit angle and distance in iris recognition system

The present invention relates to a display device of a focal angle and distance in an iris recognition system, in which the device includes: a distance measurer for measuring a distance between a user and an iris recognition camera, and an indicator for quantitatively indicating a forward-backward distance and a right and left or up and down direction the user should move, in accordance with the distance measured by the distance measurer.

Anti-sialyl tn chimeric antigen receptors

The invention provides improved compositions for adoptive cell therapies for cancers that express the glycoepitope STn on TAG-72.

Composition and microsphere for controlled release of exendin, and method for its preparation

Una microesfera de liberación controlada con una capa de recubrimiento que comprende un núcleo que contiene una exendina como principio activo, y un polímero biodegradable, y una capa de recubrimiento que recubre el núcleo con un material de recubrimiento, en el que el polímero biodegradable es un polímero seleccionado del grupo constituido por poliláctido (PLA), poliglicólido (PGA), poli(láctido-co-glicólido) (PLGA), poliortoéster, polianhídrido, ácido polihidroxibutírico, policaprolactona, y polialquilcarbonato, un copolímero o una mezcla simple de dos o más seleccionados del grupo polimérico; un copolímero del polímero y polietilenglicol (PEG), o un complejo de polímero-azúcar en el que un azúcar se acopla al polímero o al copolímero, el material de recubrimiento es uno o más seleccionado del grupo constituido por aminoácidos básicos, polipéptidos, y compuestos orgánicos de nitrógeno, en el que el aminoácido básico es uno o más seleccionado del grupo constituido por arginina, lisina, e histidina, el polipéptido comprende de 2 a 10 aminoácidos en el que están comprendidos uno o más aminoácidos básicos seleccionados del grupo constituido por arginina, lisina, e histidina, y el número de aminoácidos básicos es superior al de aminoácidos ácidos, y el compuesto orgánico de nitrógeno es uno o más seleccionado del grupo constituido por creatina, creatinina, y urea. A controlled release microsphere with a coating layer comprising a core containing an exendin as an active ingredient, and a biodegradable polymer, and a coating layer that coats the core with a coating material, in which the biodegradable polymer is a polymer selected from the group consisting of polylactide (PLA), polyglycolide (PGA), poly (lactide-co-glycolide) (PLGA), polyortoester, polyanhydride, polyhydroxybutyric acid, polycaprolactone, and polyalkylcarbonate, a copolymer or a simple mixture of two or more selected from the polymer group; a copolymer of the polymer and polyethylene glycol (PEG), or a ...

Array substrate and method of fabricating the same

A method of fabricating an array substrate includes forming a first metal layer, a gate insulating material layer and an oxide semiconductor material layer on a substrate; heat-treating the substrate having the oxide semiconductor material layer at a temperature of about 300 degrees Celsius to about 500 degrees Celsius; patterning the oxide semiconductor material layer, the gate insulating material layer and the first metal layer, thereby forming a gate electrode, a gate insulating layer and an oxide semiconductor layer; forming a gate line connected to the gate electrode and made of low resistance metal material; forming source and drain electrodes, a data line and a pixel electrode, the source and drain electrodes and the data line having a double-layered structure of a transparent conductive material layer and a low resistance metal material layer, the pixel electrode made of the transparent conductive material layer.

Method for supporting coexistence considering while subchannel allocation in a broadband wireless access system

A method for supporting coexistence in a mobile station configured for supporting a coexistence mode of a primary wireless communication system and a secondary wireless communication system. The method comprises transmitting to a base station, via the mobile station, a registration request (REG-REQ) message comprising coexistence capability information, receiving a registration response (REG-RSP) message comprising information about support of the coexistence mode in response to the REG-REQ message, and transmitting to the base station, via the mobile station, a sleep mode request (MOB_SLP-REQ) message comprising first coexistence information for requesting a band adaptive modulation and coding (AMC) for adjacent subcarrier permutation.

Liquid crystal display and method of making the same

Ein Verfahren zum Herstellen einer Flüssigkristallanzeige weist auf: Bereitstellen eines ersten Substrates; Ausbilden einer Gate-Elektrode und einer Gate-Leitung auf dem ersten Substrat; Ausbilden einer ersten Isolierschicht auf dem ersten Substrat; Ausbilden einer aktiven Struktur, einer ohmschen Kontaktschicht und einer diffusionsverhindernden Schicht auf einem oberen Abschnitt auf der Gate-Elektrode unter Verwendung von Trockenätzen, und Ausbilden von Source-Elektrode und Drain-Elektrode auf der diffusionsverhindernden Schicht durch Verwenden von Nassätzen; Ausbilden einer zweiten Isolierschicht auf dem ersten Substrat; Ausbilden eines Kontaktloches durch Entfernen eines Abschnittes der zweiten Isolierschicht und Freilegen eines Abschnittes der Drain-Elektrode; Ausbilden einer Pixel-Elektrode, elektrisch verbunden mit der Drain-Elektrode mittels des Kontaktloches; und Befestigen des ersten Substrats mit dem zweiten Substrat, wobei die diffusionsverhindernde Schicht eine Metallspitze aufweist, die verglichen mit der Source-Elektrode und der Drain-Elektrode hervorsteht, gebildet durch Trockenätzen. A method of manufacturing a liquid crystal display comprises: providing a first substrate; Forming a gate electrode and a gate line on the first substrate; Forming a first insulating layer on the first substrate; Forming an active structure, an ohmic contact layer and a diffusion preventing layer on an upper portion on the gate electrode using dry etching, and forming source electrode and drain electrode on the diffusion preventing layer by using wet etching; Forming a second insulating layer on the first substrate; Forming a contact hole by removing a portion of the second insulating layer and exposing a portion of the drain electrode; Forming a pixel electrode electrically connected to the drain electrode by means of the contact hole; and attaching the first substrate to the second substrate, wherein the diffusion-preventing layer has a metal tip protruding compared ...

Composition and microsphere for controlled-release of exendin,and method of preparing the same

Recombinant peptide vector comprising the gene for treatment for autoimmune diseases.

The present invention provides a recombinant peptide vector comprising a leader peptide, linker DNAs and a DNA construct formed by operably linking expression control sequences with a therapeutic gene encoding a fusion protein where the extracellular domain of CTLA4 is bound to the Fc fragment of immunoglobulin, wherein the leader peptide is linked to both ends of the DNA construct by the linker DNAs. Also, the present invention provides a method for preparing the recombinant peptide vector, and a pharmaceutical composition for the treatment of autoimmune diseases, which comprises a pharmaceutically effective amount of the recombinant peptide vector, and a pharmaceutically acceptable carrier.

Method and apparatus for transmitting receipt confirmation reply in wireless communication system

【課題】上りリンクサブフレームを下りリンクサブフレームへと用途変更して用いる場合に受信確認応答を送信する方法を提供する。 【解決手段】本発明の一実施例は、無線通信システムにおいて端末が上りリンク受信確認応答を送信する方法であって、サブフレームｎで下りリンク信号を受信するステップと、下りリンク信号に対する受信確認応答を、下りリンク信号が受信されたサブフレームからｋ番目のサブフレームで送信するステップとを有し、ｋ番目のサブフレームで受信確認応答のためのリソースは、第１タイムラインに従う場合にｋ番目のサブフレームで受信確認応答を送信すべき下りリンクサブフレーム及び第２タイムラインに従う場合にｋ番目のサブフレームで受信確認応答を送信すべき下りリンクサブフレームのうち共通する、第１グループのサブフレームに優先的に割り当てられる、受信確認応答送信方法である。 【選択図】図１５

Method for supporting coexistence with wireless local area network

A method for supporting coexistence with a wireless personal area network (WPAN) is provided. A method for supporting coexistence with a WPAN in a mobile station which periodically receives a beacon signal for local wireless communication includes, at the mobile station, calculating the numbers of uplink frames which overlap with the beacon signal, configuring a bitmap using the calculated frame numbers, and transmitting coexistence information including the bitmap to a base station. Accordingly, when a broadband wireless access system and WiMedia or ZigBee are simultaneously used, a beacon signal of WiMedia or ZigBee can be efficiently protected from the interruption of the broadband wireless access system and thus WiMedia or ZigBee can be normally operated.

High-strength steel material having enhanced resistance to brittle crack propagation and break initiation at low temperature and method for manufacturing same

A method for interference alignment in wireless network

A method for interference alignment in wireless network having 3 transmitters and 3 receivers which are equipped with M antennas is provided. The method comprising : transmitting, performed by each of the 3 transmitters, a pilot signal known to the 3 receivers; estimating, performed by each of the 3 receivers, each channel from transmitter; transmitting, performed by each of the 3 receivers, feedback information to target transmitter; and determining, performed by transmitter 2 and transmitter 3, a precoding vector; wherein a degree of freedom(DoF) of a transmitter 1 is (M/2 - α), a DoF of the transmitter 2 or the transmitter 3 is M/2.

Display apparatus

Anti-Sialyl Tn chimeric antigen receptors

The invention provides improved compositions for adoptive cell therapies for cancers that express the glycoepitope STn on TAG-72.

Array substrate for organic electroluminescent display device and method of fabricating the same

A method of fabricating an array substrate for an organic electroluminescent display device includes forming a semiconductor layer, a semiconductor dummy pattern, a first storage electrode and a first gate insulating layer on a substrate; forming a second gate insulating layer on the semiconductor layer and the first storage electrode; forming a gate electrode and a second storage electrode on the second gate insulating layer; forming ohmic contact layers by doping impurities into both sides of the semiconductor layer; forming an inter insulating layer on the gate electrode and the second storage electrode; forming source and drain electrodes and a third storage electrode on the inter insulating layer; forming a passivation layer on the source and drain electrodes and the third storage electrode; forming a first electrode and a fourth storage electrode on the passivation layer; and forming a spacer and a bank on the first electrode.

Capacitor with nanotubes and method for fabricating the same

Method for supporting coexistence considering while subchannel allocation in a broadband wireless access system

Method and device for precoding in wireless communication system

Provided is a method and a device for precoding in a wireless communication system. The method for precoding comprises the following steps: generating a first precoding matrix, W 1 , for deciding the transmission power of one transmission antenna from a plurality of transmission antennas as the maximum power per antenna; generating a zero forcing (ZF) precoding matrix, T i , which does not influence the transmission antenna having the power which is decided as the maximum power per antenna, based on the (i−1) th precoding matrix W i−1 (i=2, 3, . . . ); determining α i , a constant which has the transmission power of one transmission antenna from the rest of the transmission antennas, which do not have the transmission power as the maximum power per antenna, based on the T i ; and generating the i th precoding matrix W i based on the T i and the α i .

Composition and microsphere for controlled-release of exendin, and method of preparing the same

A controlled-release composition and controlled-release microspheres containing an exendin as an active ingredient, and a method of preparing the same are provided. More specifically, a controlled-release composition containing an exendin as an active ingredient, a biodegradable polymer with a specific viscosity, and coating materials, having high bioavailability and showing sustained release of the active ingredient in an effective concentration for a certain period without an excessive initial burst of the active ingredient; controlled-release microspheres containing a core including an exendin as an active ingredient and a biodegradable polymer, and a coating layer coating the core; and a method of preparing controlled-release microspheres including the steps of mixing an exendin, a biodegradable polymer, and a solvent, removing the solvent from the mixture to prepare hardened microspheres, and coating the hardened microspheres to form a coating layer on the surface of each microsphere, are provided.

Oxide semiconductor thin film transistor and method of forming the same

An oxide semiconductor thin film transistor and a method of forming the oxide semiconductor thin film transistor are provided. The oxide semiconductor thin film transistor can include a semiconductor layer including a channel region, a source region and a drain region; a first gate insulating layer on the semiconductor layer; a gate electrode on the first gate insulating layer; a second gate insulating layer on the gate electrode; an auxiliary electrode on the second gate insulating layer; an interlayer insulating layer on the auxiliary electrode; and a source electrode and a drain electrode on the interlayer insulating layer, wherein the source region and the drain region being disposed at both sides of the channel region, wherein the gate electrode overlapping with the channel region, and the auxiliary electrode overlapping with the gate electrode.

3D semiconductor integrated circuit device and method of manufacturing the same

A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.

Liquid crystal display device and fabrication method thereof

Face recognition system and method capable of updating registered face templates

This invention relates to a face recognition system and method capable of updating a registered face template. The system comprises: a registered template DB in which registered face templates are stored; an authenticated template DB for storing authenticated face templates; and a controller for storing the authenticated face template in the authenticated template DB according to the user's face authentication, obtaining a similarity degree between each of a plurality of the authenticated face templates by using the plurality of the authenticated face templates stored in the authenticated template DB after a predetermined period has elapsed, obtaining the value of an average similarity degree for each of the plurality of authenticated face templates by using the values of the similarity degree, selecting as a new registered face template the authenticated face template having the value of the largest average similarity degree among the values of the average similarity degree and updating the registered face template by storing the new registered face template in the registered template DB.

Method for supporting coexistence considering while subchannel allocation in a broadband wireless access system

A method for supporting coexistence in a mobile station for supporting a coexistence mode of WiMAX and secondary wireless communication system while considering subchannel allocation, the method comprises, requesting a band adaptive modulation and coding (AMC) for adjacent subcarrier permutation to a base station by transmitting first coexistence information, after the secondary wireless communication is turned on, and requesting a release of the adjacent subcarrier permutation to the base station by transmitting second coexistence information, if the secondary wireless communication system is turned off. Accordingly, it is possible to provide simultaneity of different wireless communications when a sleep mode is used and improve simultaneity of different wireless communications even when the sleep mode is not used.

Sustained release formulation of protein and preparation method thereof

Power control method for interference alignment in wireless network

A power control method for interference alignment in wireless network having K transmitters and K receivers is provided. The method includes: receiving, performed by receiver n (n is an integer, 1≦n≦K−1), a power indication signal of transmitter n+1 from the transmitter n+1; determining, performed by the receiver n, power of transmitter n; and transmitting, performed by the receiver n, a power indication signal of transmitter n to the transmitter n, wherein the power of transmitter n is determined based on a residual interference of the receiver n, and the power indication signal of transmitter n indicates a minimum transmission power or a maximum transmission power of transmitter n.

Feedback method for interference alignment in wireless network

A feedback method for interference alignment in wireless network having K transmitters and K receivers is provides. The method comprising : transmitting, performed by transmitter n-1, a precoding vector of transmitter n-1 (n is a integer between 2 and K-1) to receiver n+1; calculating, performed by the receiver n+1, a precoding vector of transmitter n using the precoding vector of transmitter n-1; and transmitting, performed by the receiver n+1, the precoding vector of transmitter n to transmitter n.

Method for supporting coexistence considering while subchannel allocation in a broadband wireless access system

A method for supporting coexistence in a mobile station for supporting a coexistence mode of WiMAX and secondary wireless communication system while considering subchannel allocation, the method comprises, requesting a band adaptive modulation and coding (AMC) for adjacent subcarrier permutation to a base station by transmitting first coexistence information, after the secondary wireless communication is turned on, and requesting a release of the adjacent subcarrier permutation to the base station by transmitting second coexistence information, if the secondary wireless communication system is turned off. Accordingly, it is possible to provide simultaneity of different wireless communications when a sleep mode is used and improve simultaneity of different wireless communications even when the sleep mode is not used.

Biomolecule transduction motif sim-2-btm and the use thereof

Process of preparing microspheres for sustained release having improved dispersibility and syringeability

Disclosed is a process of preparing sustained release microspheres, containing a biodegradable polymer as a carrier and a drug, using spray drying. The process comprises preparing a solution, suspension or emulsion containing a biodegradable polymer, a drug and a solvent; spray drying the solution, suspension or emulsion; and suspending spray-dried microspheres in an aqueous solution containing polyvinyl alcohol to remove the residual solvent and increase the hydrophilicity of the microsphere surface. The process enables the preparation of microspheres having high drug encapsulation efficiency, almost not having a toxicity problem due to the residual solvent, and having good syringeability. The microspheres prepared according to the present invention release an effective concentration of a drug in a sustained manner for a predetermined period when administered to the body, and are thus useful in the treatment of diseases.

Method for preparing positive electrode active material, and positive electrode active material

The present invention relates to a method of preparing a positive electrode active material which includes steps of (A) preparing a pre-sintered product by mixing a positive electrode active material precursor containing 70 mol% or more of nickel (Ni) among total metals and a lithium-containing raw material and performing primary sintering, (B) preparing a lithium transition metal oxide by mixing the pre-sintered product and an aluminum-containing raw material and performing secondary sintering in an oxygen atmosphere containing 20 vol% to 100 vol% of oxygen, and (c) mixing the lithium transition metal oxide and a boron-containing raw material and performing a heat treatment to form a coating layer, wherein the secondary sintering is performed while reducing an oxygen concentration according to sintering time, a positive electrode active material prepared by the above preparation method, and a positive electrode for a lithium secondary battery and a lithium secondary battery which include the positive electrode active material.

Positive electrode active material, method for manufacturing same, positive electrode material comprising same, positive electrode, and lithium secondary battery

Chimeric antigen receptor comprising anti c-met antibody or antigen binding fragment thereof, and use thereof

Das biomolekültransduktionsmotiv mph-1-btm und dessen verwendung