ARM-based flat wheel detection and control system

The invention relates to a face cam test and control system, which is based on the ARM. The system mainly comprises a power supply, a crystal, a reset circuit, an ARM, consisting of JTAG ports and working as an embedded CPU which is connected with FLASH and SDRAM; the invention also comprises a power-supply module, a buzzer, indicators, an eight-section nixietube and a system expansion bus, which are all connected with the embedded CPU. By using the distinctive features of the technology used in embedded products, the invention has self advantages of in size and power consumption. The invention does not have the problems such as crashes and upgrades, but has simpler and more convenient operation interfaces and operation manners, and relatively long lifecycle.

Pyrazoline pyridine-fluorescent coumarin dye derivant, synthesis and uses thereof

The invention belongs to the field of fluorescent dye and laser dye, and relates to coumarin fluorescent dye and laser dye, in particular to pyrazoline naphthyridine coumarin fluorescent dye derivative, and a synthetic method and an application thereof. The pyrazoline naphthyridine coumarin fluorescent dye derivative has very high fluorescent efficiency with the quantum yield of fluorescence of nearly 100 percent; meanwhile, the fluorescent material has excellent heat, light and electricity chemical stability, and can be used as fluorescent dye, laser dye, organic electroluminescent material, fluorescent marking material, fluorescent chemical sensitive material and the other. The pyrazoline naphthyridine coumarin fluorescent dye derivative has structure as seen in formula I or formula II.

Single crawler type wall climbing robot based on electrostatic absorption principle

The invention discloses a single-crawler type wall climbing robot based on the electrostatic adherence theory, and relates to a wall climbing robot. The invention aims to provide a wall climbing robot which has the advantages of large range adapting to wall surface materials, low noise, smaller volume, small electrostatic adherence device self weight and high moving speed. Flexible aluminum plated film crawlers are adopted as a walking device and an adherence device of the robot. One end of a slide base plate is overlapped with one end of a slide guide plate, and the base plate is connected with an end part of the slide guide plate. One end of a spring is connected with a guiding and positioning rod piece, while the other end is connected with an end part of the slide guide plate. The other end of the slide base plate is perpendicularly connected with the middle part of a driving wheel supporting frame main body of a driving wheel supporting frame, and the other end of the slide guide plate ...

Low dielectric constant medium and copper interconnection structure and integration method thereof

The invention belongs to the technical field of a semiconductor device, in particular to a low dielectric constant medium and copper interconnection structure and an integration method thereof. The integration method comprises the following structure: lowering capacitance by combination of copper interconnection and an air gap; and supporting a copper conductor with a specific support structure so as to remove the medium and maintain the shape of the copper conductor. The invention has the advantage that a full air-gap structure can be realized on the premise of preventing the copper conductor from short circuit or disconnection, and the full air-gap structure of a longer conductor also can be realized, thus reducing the remote control (RC) delay.

Three-roll-type skew rolling mill of open-type stand

The invention discloses a three-roll-type skew rolling mill of an open-type stand, solving the problems of complicated structure, great operation and maintenance load and high equipment cost in the prior art and the particularly serious problems of a large-scale rolling mill. The three-roll-type skew rolling mill of the open-type stand comprises an upper stand (1), a roll screwdown transmission and balance mechanism (2), a roll box (3), a roll assembly (4), a quick-open cylinder (5), a lower stand (6), a stand-locking device (7) and a base (8), wherein a screwdown screw at the outlet side of the roll screwdown transmission and balance mechanism (2) contacts with the roll box (3) together through a sphere (9), and a screwdown screw at the inlet side of the roll screwdown transmission and balance mechanism (2) contacts with the roll box (3) together through a sphere (10). When the quick open cylinder acts, the invention can ensure that the roll assembled can rotate at any space angle around ...

Bamboo compound material wind mill blade and its vacuum infusion process

The invention discloses a bamboo-made composite material wind power vane and a vacuum infusion technique. According to the technique scheme provided by the invention, the bamboo-made composite material wind power vane comprises a vane body which is composed of a vane-shaped upper vane and lower vane, wherein the vane root is arranged at the root part of the vane body, the top end of the vane body is a vane tip, the upper and the lower vanes are adhered into an integral by mold adhesive bar and makes the periphery form a cavity, a bamboo cordwood is filled in the vane root and/or upper vane and/or lower vane, a vane root premolding part is arranged on the bottom end corner of the vane outer-boundary of the vane body. The vane is prepared by each procedure such as preparing equipment material, preparing mould, paving each kind of material, laying out tube, infusing, doing subsequent process and the like. The vane is low in preparation cost, short in preparation period, which is beneficial ...

Intermittent transmitting mechanism high in motion-stand ratio

The invention discloses an intermittent transmitting mechanism high in motion-stand ratio. The intermittent transmitting mechanism high in motion-stand ratio comprises an eccentric mechanism, two sets of synchronous belt wheels and a divider. The output shaft speed ratio of the eccentric mechanism is 1:1.33. Speed reduction is achieved through the two sets of synchronous belt wheels. The eccentric mechanism is completed by a transmission shaft, a sliding groove block, a cam follower, a cam follower support, a bearing and a bearing block. Due to changes in the output speed ratio of the eccentric mechanism and speed reduction transmission of the two sets of synchronous belt wheels, the motion-stand ratio of transmission of the divider is 1:3, the motion-stand ratio of intermittent transmitting is 1:7, and therefore the intermittent transmitting, with the motion-stand ratio of 1:7, required during work is achieved.

Tunneling transistor using source electrode made of narrow forbidden-band gap material and manufacturing method thereof

The invention belongs to the microelectronic technical field and particularly discloses a tunneling field effect transistor (TFET) using a source electrode made of narrow forbidden-band gap material and a preparation method thereof. The source electrode of the tunneling field effect transistor adopts the narrow forbidden-band gap material and is of the U-shaped groove structure. Due to the adoption of the narrow forbidden-band gap material, the driving current of the TFET is increased; meanwhile, due to the adoption of the U-shaped groove structure, the leakage current of the TFET is also inhibited. The TFET manufactured in the invention has the advantages of low leakage current, high driving current, high integrated level and the like; therefore, an integrated circuit in the TFET is capable of reducing the static power consumption and increasing the integrated level.

Method for preparing molecular sieves dryer special used for pneumatic braking system

The present invention relates to a manufacturing method for molecular sieve desiccant special for pneumatic brake system, which comprises the steps of that: the molecular sieve initial powder and clay are mixed to a scale, and then are bonded by liquid silicate binder to form granule which is dried or baked at 200~700 DEG C to produce the desiccant product. Compared with the prior art, the present invention has the advantages of short procedure, simple operation, energy saving, non discharging of the three wastes; besides, the product can be used as braking device for high speed train, heavy duty car, truck and ordinary automobiles.

Feeding angle adjusting device of three-roller skew rolling mill

The invention discloses a feeding angle adjusting device of a three-roller skew rolling mill, which solves the problem of the prior art that the adjustment of the feeding angles of three rollers cannot be synchronized with the same accuracy. The feeding angle adjusting device comprises a dual-output shaft driving motor (6) and three worm lifts, wherein the dual-output shaft driving motor (6) and the three worm lifts are fixed on a frame (1) respectively; the dual-output shaft driving motor (6) is connected with the input shafts of the three worm lifts through three couplings in turn respectively; the three worm lifts are connected with three drum devices through respective swing bars and hinges respectively; and three sets of swing devices synchronously swing in set directions. According to the invention, synchronous and centralized adjustment of the feeding angle of the three-roller skew rolling mill can be realized.

Semiconductor memory device, semiconductor memory array and read-in method

The invention discloses a semiconductor device, which comprises a source electrode, a drain electrode, a floating boom area, a control grid, a sunken groove area and a grid control p-n junction diode for connecting the floating boom area and the drain electrode. The floating boom area of the semiconductor device is used for storing charge and can be charged or discharged through the grid control p-n junction diode. The invention also discloses a semiconductor memory array which consists of a plurality of the semiconductor memory devices, a plurality of word lines, a plurality of bit lines anda plurality of source lines, as well as a method that one of the plurality of semiconductor memory devices can be selected to be written in. The semiconductor device, the semiconductor memory array and the method can realize rapid access and have small unit size and strong data retentiveness.

Anisotropic magnetic powder and manufacturing method thereof

The invention provides a high-performance bonded rare earth permanent magnet powder and a preparation method thereof. Raw material compositions and the preparation method of the rare earth permanent magnet powder are as follows: an alloyed casting strip, the composition ratio of which is R1-xNdx8 to 20MyFebalB4 to 12(atm%), is prepared to be high-performance bonded anisotropic magnet powder through a heat treatment (or untreated process), a hydrogenation and dehydrogenation process and fragmentation. The preparation method comprises the following steps: a rare-iron-boron alloyed casting strip is prepared through a strip casting process, the thickness of the rare-iron-boron alloyed casting strip is 0.1 mm to 1.0 mm; and finally the bonding rare earth permanent magnet powder with high coercive force and high oxidation resistance are prepared through the processes of hydrogenation and dehydrogenation. Compared with the magnet powder taking the traditional cast ingot as the raw material, the ...

Asymmetric Support Technology Using Rock And Cable Bolts For Gob-Side Entry Driven Under Gob Edge With Internally Split-Level Longwall Layout In Mining Of Inclined Extra-Thick Coal Seams

Abstract The invention relates to an asymmetric support technology using rock and cable bolts for a gob-side entry driven under a gob edge with an internally split-level longwall layout in mining of inclined extra-thick coal seams. The asymmetric support technology comprises the steps of in an internally split-level longwall layout mode, designing an asymmetric support pattern according to the thickness change of roof coal and the lithology change of two sidewalls by adjusting an internally split-level distance and retaining roof coal with a sufficient thickness (at least greater than the lengths of rock and cable bolts). Short rock bolts are adopted for a thin part of the roof coal, long rock bolts are adopted for a thick part of the roof coal, glass fiber reinforced plastic rock bolts are adopted for coal sidewalls, and rebar bolts which are one less than the rock bolts for the coal sidewalls are adopted for rock below roof coal. The asymmetric support technology using the rock and cable ...

Inductive loop formed by interconnecting silicon through holes

The invention discloses an inductive loop formed by interconnecting silicon through holes. A silicon through hole interconnecting technique is adopted to perform special interconnection on the silicon through holes, and a formed inductive element has the advantages of large inductance value, high density and the like. Besides, a silicon through hole interconnecting integration process for forming the inductive element is compatible with a conventional silicon through hole interconnecting integration process and needs no more processing steps, and the technological process is simple and stable. The inductive loop is suitable for packaging and manufacturing the silicon through holes of various chips, and is particularly suitable for packaging and manufacturing a power control chip and a radio frequency chip.

Storage unit of flash memory and preparation method thereof

The invention belongs to the technical field of semiconductor storage devices, and in particular discloses a storage unit of a flash memory and a preparation method thereof. The storage unit comprises a semiconductor substrate, a source, a drain, a gate, a floating gate region and an active region. In the storage unit of the flash memory, the gate, the source and the drain of a transistor are formed by using an autoregistration metallic silicide process, and ion injection and high-temperature thermal annealing treatment after the ion injection are not needed, thus the technological process is simple, cost is low and the performance of the device is greatly improved.

Supercritical carbon dioxide extraction technology for pleuromutilin

The invention relates to extraction technologies for microorganism-sourced compounds, in particular to a supercritical carbon dioxide extraction technology for pleuromutilin. The technology comprises the following steps: separating mycelium from pleuromutilin producing strain fully-fermented liquor, drying, smashing, screening, baking to obtain baked mycelium with total water content less than 5%for stand-by application, putting the baked mycelium in a supercritical extraction kettle to carry out supercritical carbon dioxide extraction under extraction pressure of 12-24Mpa and at extraction temperature of 35-55 DEG C and carbon dioxide flow rate of 25kg/h for 60-100min, and collecting extract to obtain the pleuromutilin. The technology has the advantages of stable and easy operation, short extraction time and low production cost and requires small amount of solvents; and moreover, the products has little impurities.

Quality and regulation control method and system for chill station of central air conditioner

The present invention relates to a quality regulation control method of central air-conditioning refrigerating station and its system. It belongs to a method for controlling operation of central air-conditioning refrigerating station and its system. Said system includes internal weather parameter monitoring portion, central air-conditioning system operation parameter monitoring portion, quality regulation control main machine, cold water machine unit control unit for controlling water supply temperature for refrigeration, cooling tower frequency conversion control unit for controlling cooling tower outlet temperature, refrigerating water pump frequency conversion control unit and cooling water pump frequency conversion control unit. Besides, said invention also provides the concrete steps of its quality regulation control method.

Zirconium alloy for nuclear power

Improved NiO-based resistive random access memory (RRAM) and manufacturing method thereof

The invention belongs to the technical field of integrated circuits and particularly relates to an improved NiO-based resistive random access memory (RRAM) and a manufacturing method thereof. A memory unit comprises a substrate and a metal-insulator-metal (MIM) structure; a top electrode is a metal membrane which is made of copper, aluminum and the like and can be used in an interconnecting process; and a variable-resistance insulator is an Al2O3/NiO/Al2O3 medium membrane with a nano laminated structure. The MIM structure in the invention presents stable double-resistance state transition and memory characteristic under the condition of direct current voltage continuous scanning excitation; and compared with the memory unit of an RRAM which adopts a medium membrane only with a NiO single-medium layer structure, the memory unit has a larger memory window and higher resistance value stability. The memory unit has good prospect in practical application to a NiO material RRAM. The invention ...

State machine processing method and device based on message driving

The present invention provides a condition machine processing method and device based on message driven, the method includes the following steps: referred each resource sharing and /or equipment arrangement of process flow process initialized set a flag bit without configured; after first condition machine in condition machine receiving message; analyzing message to obtain indication about demanddistribute resource and/or configure equipment; demand configure according to indication setting resource and/or equipment flag bit; checking resource or equipment, if inspected flag bit of resource or equipment is demand configure, then distributing resource or configuring equipment; setting flag bit is configure success or configure failure according to configure success or not; keeping on moving towards second condition machine in condition machine or back to first condition machine. The present invention collects process flow, improving code complexing capacity, thereby improving efficiency.

Synthetic method of beet alkali and beet alkali hydrochlorate

The invention provides a synthesis method of betaine and betaine hydrochloride salt, comprising the steps as follows: strong alkali negative ion resin is selected as a carrier and is treated into a hydroxide radical type; elution is carried out by using a chloroactic acid solution; cycle elution is carried out using a trimethylamine solution; scrubbing is carried out by using distilled water, andcleaning solution is combined with cycle eluent, then vacuum distillation is carried out so as to achieve vicidity, and the vacuum distillation is continued until powder or small flake white betaine with water is obtained; the betaine with water is dissolved using absolute ethyl alcohol and is carried out vacuum distillation to obtain betaine anhydrous, with yield of more than 93 percent and purity of more than 98.5 percent; the sticky matter after the vacuum distillation is added with hydrochloric acid and stirred then subjected to the vacuum distillation so as to obtain the powder or small flake ...

<100> Fe-Ga magnetostriction material on axial orientation and method of preparing the same

The invention discloses a <, a 100>, an axial orientation Fe-Ga magnetostriction material and the preparation method thereof. The material composites are Fe1-x-yGaxAly; wherein, x is between 16 per cent and 21 per cent or 25 per cent and 28 per cent; y is between 0 per cent and 10 per cent; the rest part is iron. The preparation method is that the raw material is melted under the protection of the inert gas, and the improved percy williams bridgman method is adopted to prepare the Fe-Ga magnetostriction material through the directional solidification; The heat treatment conditions are that the material is preserved at 1100 DEG C. to 1200 DEG C. for 0.5 hours to 24 hours, cooled with the furnace till 900 DEG C. to 750 DEG C. for 0.5 hours to 24 hours temperature preservation and then quenched or cooled by air to room temperature; or the material is preserved at 1100 DEG C. to 1200 DEG C. temperature for 0.5 hours to 24 hours and is cooled with the furnace till 500 to 700 DEG C..

Nonparametric regression method

The invention discloses a nonparametric regression method, which relates to the field of forecast methods. The method of the invention comprises the following steps: determining a forecast quantity according to a forecast object; acquiring the properties P1-Pn of the forecast quantity from the forecast object, and using the properties P1-Pn as each component of the forecast object state, wherein n is the number of properties; collecting patterns; constructing a pattern library by a KD tree data structure according to the collected patterns; collecting parameters of the state of the forecast object, composing the current state vectors of the forecast object by the parameters, searching for k numbered patterns similar to the current state vectors in the pattern library according to a predetermined criterion, and acquiring the values y1-yn of the quantities to be forecasted corresponding to the k numbered patterns; substituting the acquired values y1-yn of the quantities to be forecasted into ...

Portable soil heavy metal analyser

Monocrystalline silicon slice with ultra-hydrophobicity nano silicone linear arrays on surface and preparation method thereof

The invention discloses a monocrystalline silicon slice with ultra-hydrophobicity nano silicone linear arrays on the surface and a preparation method thereof. The monocrystalline silicon slice comprises a monocrystalline silicon slice as a substrate and nano silicone linear arrays positioned on the surface of the monocrystalline silicon slice. In the preparation method, a conductive monocrystalline silicon slice is used as a precursor, gold nanoparticles sputtered on the surface of the silicon slice by a magnetic-control ion sputtering device are used as catalysts, and then the nano silicone linear arrays with the preset area are prepared by using an electrolysis method. The method can obtain the nano silicone linear arrays with different diameters and length ranges through the adjustment on the thickness and the electrolyzing time of gold nanoparticle film layers. The nano silicone linear arrays have hierarchic nano and micron rough surfaces which express favorable ultra-hydrophobicity ...

System for data acquisition and signal treatment of testing flat wheel

The invention provides a flat wheel detection data acquisition and signal processing system, which consists of seven parts, namely a power module, an AD sampling input front end conditioning module, an AD sampling conversion module, a data program memory module, an interruption management module, a high speed communication module and a reset module. The invention applies a high speed floating point DSP chip, a high speed low consumption double 12-bit parallel A/D converter, a dual-ported RAM chip and a complicated programmable logic device to the flat wheel detection data acquisition and signal processing system, develops a data acquisition and processing system taking the high speed floating point DSP as a core processor, and improves the speed, accuracy and stability of flat wheel detection data acquisition and processing (in addition, the system control, communication and monitoring is handled by ARM-VxWORK, and communication takes a form of network card.), thereby improving the performance ...

Zirconium alloy for nuclear power reactor core

Disclosed is a zirconium alloy material for a nuclear power reactor core, falling within the technical field of special alloy materials, and comprising the following components in percentage by weight: 0.4-0.8 percent of Sn, 0.75-1.1 percent of Nb, 0.20-0.50 percent of Fe + Cr, 0.20-0.35 percent of Fe/(Fe + Nb), 0.01-0.1 percent of Cu or Bi or Ge, 0.002-0.02 percent of Si or S, 0.06-0.15 percent of O, less than 0.008 percent of C, less than 0.006 percent of N, and the balance being Zr. On the basis of a Zr-Sn-Nb system alloy, other components for improving the performance of the alloy are added, not only improving the corrosion resistance of the alloy, but also improving the mechanical properties and radiation resistance of the alloy, so that the requirements of high burnup of the nuclear power reactor on the structural materials of the core are met.

Fluorescent probe for detecting heparin content in blood as well as synthetic method and application

The invention relates to a high-selectivity and high-sensitivity fluorescent probe fordetecting heparin, particularly detecting the heparin content in blood as well as a synthetic method and application. The synthetic method comprises the following steps of: dissolving tertiary amine with substituent groups R1, R2 and R3 or tertiary diamine with the substituent groups R1, R2, R3 and R4 into an organic solvent, and adding halogenated alkyl aromatic, wherein the mol ratio of the halogenated alkyl aromatic to the tertiary amine with the substituent groups R1, R2 and R3 or the tertiary diamine with the substituent groups R1, R2, R3 and R4 is 0.01-50; reacting for 0.5-60 hours at the reaction temperature of 30-100 DEG C, and obtaining a compound with an (A) structure or a (B) structure by utilizing silica gel column chromatography after solution concentration. The fluorescent probe has good selectivity for the heparin, has no toxic or side effect per se, can reach the detection limit for the ...

Micro-miniature directional cradle head

The invention provides a micro-miniature directional cradle head, which relates to a robot cradle head and aims to solve the problems that the prior detection cradle head carried by a detection wall-climbing robot cannot ensure that the detection direction is unchanged while a detection camera extends out and the influence on the detection effect caused by glass reflection of light cannot be eliminated. The input end of a first driving shaft is arranged in a worm wheel center hole of in a first worm wheel driving device, one end of a connecting rod is fixedly arranged on the first driving shaft, while the other end is arranged on a second driving shaft, the lower end of a supporting sleeve is connected with the second driving shaft, a second warm wheel driving device is arranged at the front end of an inner cavity of the supporting sleeve, one end of a driving swing stem and one end of a driven swing stem are connected with a worm wheel shaft and a supporting shaft respectively, while the ...

Non-volatile storage and manufacturing method thereof

The invention belongs to the technical field of a non-volatile storage below 50 nanometers, particularly to a non-volatile storage and a manufacturing method thereof. In the non-volatile storage, a collision ionization type metal-oxide-semiconductor field effect transistor (MOSFET) with a floating gate is used as a basic structure. By utilizing the non-volatile storage provided by the invention, the short channel effect can be overcome, and the driving current is improved while the subthreshold is restricted. The invention also provides the manufacturing method of the non-volatile storage. The non-volatile storage provided by the invention is very applicable to manufacture of integrated circuit chips, especially the manufacture of chips with low power consumption.

Zirconium alloy for nuclear power reactor core

MIS (metal-insulator-semiconductor) and MIM (metal-insulator-metal) device provided with gate

The invention belongs to the technical field of semiconductor devices less than 10 nanometers, in particular relates to a metal-insulator-semiconductor (MIS) and metal-insulator-metal (MIM) device provided with a gate. In the invention, a gate voltage is applied on the side wall of the MIM or MIS device to regulate an electric field, thus FN (faecal nitrogen) tunnelling current in the MIM or MIS structure and the on-off of the device is controlled. The channel of the MIM and MIS device provided with the gate in the invention can be short, extremely low leakage current can be achieved, and the power consumption is low, thus the device is applicable to a rear-end process of an integrated circuit and manufacturing of various chips.

Complementary grid-controlled PNPN field effect transistor and preparation method thereof

The invention belongs to the technical field of semiconductor devices and particularly relates to a complementary grid-controlled PNPN field effect transistor (FET) and a preparation method thereof. The complementary grid-controlled PNPN FET consists of an N grid-controlled PNPN FET and a P grid-controlled PNPN FET with the source being a narrow-energy-gap recessed channel, wherein the recessed channels of the FET can suppress the leakage current; meanwhile, by using the narrow-energy-gap materials, the FET can increase the drive current. The invention further discloses a method for manufacturing the FET. The FET provided by the invention has the advantages of low leakage current, high drive current, low energy consumption and high integration level.

Nanolithographic method applied to manufacture of graphene-based field effect tube

The invention belongs to the technical field of manufacture of carbon-based integrated circuits, and particularly discloses to a nanolithographic method applied to the manufacture of a graphene-based field effect tube, which comprises the following steps of: performing controlled reduction on graphene oxides on any substrate by adopting a contact probe thermal reduction method; and performing thecontrolled reduction on the components of the graphene oxides by controlling the temperature of a probe so as to control the restivity of a channel. The method has the advantages of realizing a lithographic manufacturing process for the graphene-based field effect tube and reducing the preparation complexity of the graphene-based field effect tube so as to reduce the degree of difficulty in the execution of the process by directly writing the graphene-based field effect tube on the graphene oxides by utilizing the monatomic thermal contact probe. Through the technology of directly writing thegraphene-based ...

Coolant natural circulation type unit air-conditioning set

The invention provides a refrigerant natural circulation parallel unit typed air conditioning unit, comprising a compressor, a condenser, a throttling device, an evaporator, a gas connecting pipe, a liquid connecting pipe and a liquid pipe electromagnetic valve. The invention is technically characterized in that the liquid connecting pipe between the condenser and the liquid pipe electromagnetic valve is provided with a high pressure liquid storage device; the gas inlet pipe of the condenser is provided with a three-way valve; furthermore, the air inlet pipe of the compressor is provided with a gas/liquid separator. The refrigerant natural circulation parallel unit typed air conditioning unit reduces damageable parts, reduces the failure rate of the unit, has obvious energy-saving effect by arranging the high pressure liquid storage device, the gas/liquid separator and a check valve in the system, can avoid the liquid impact or oil impact phenomenon, and ensures the safe and reliable operation ...

Structure for interconnecting medium with low dielectric constant and copper and integration method

The invention relates to a structure for interconnecting a medium with low dielectric constant and copper and an integration method, belonging to the technical field of the semiconductor chip of an integrated circuit. The interconnecting structure comprises at least one metal conducting wire and insulator support structures positioned below the metal conducting wires, wherein holes are arranged between the metal conducting wires; holes are also arranged between the insulator support structures to form an air gap structure. The invention lowers the capacitance by interconnecting copper and combining air gaps together; specific support structures are used for supporting copper conducting wires so as to maintain the shapes of the copper conducting wires after a medium is removed. The invention has the advantages of realizing a complete air gap structure without the short circuit or disconnection of the copper conducting wires, realizing the complete air gap structure of longer conductingwires ...

Method for optimizing regulating and controlling efficiency coefficient of board shape controlling actuator of cold rolling mill

The invention discloses a method for optimizing the regulating and controlling efficiency coefficient of a board shape controlling actuator of a cold rolling mill, which comprises the following steps of: building a board shape regulating and controlling power coefficient priori value table under different rolling work points, wherein in the table, one set of band steel width value and a rolling force value correspond to one rolling work point; defining a boundary work point of the table according to the position of the practical rolling work point in the table; setting a weight factor according to the similarity level between a boundary work point parameter and a practical rolling work point parameter; and stacking the priori power coefficient of a boundary point in a weighting way to obtain the board shape regulating and controlling power coefficient under the practical rolling work point. By continuously improving the precision of the board shape regulating and controlling power coefficient ...

Spherical robot driven by double eccentric mass blocks

The invention discloses a spherical robot driven by double eccentric mass blocks and relates to a spherical robot. The invention aims at solving the problems that as an existing eccentric mass block driving way is that two motors are adopted to control one eccentric mass block, and the drive capacity of the motors can not be sufficiently used; therefore, the power performance of a robot drive unit is poorer, and eccentric force and inertia force can not be provided. In the spherical robot driven by the double eccentric mass blocks, a plurality of airborne power supplies are fixedly arranged on a support disc; a sensor module is fixedly arranged on a support bracket; a system controller is fixedly arranged on another support bracket; direct current servo motors are symmetrically arranged at two sides of the support disc; the direct current servo motors are fixedly arranged in motor sleeves; the motor sleeves are fixedly connected with a star-shape bracket; the eccentric mass blocks are connected ...

Zirconium alloy for nuclear power

Disclosed is a zirconium alloy material for a nuclear power reactor core, falling within the technical field of special alloy materials, and comprising the following components in percentage by weight: 0.60-1.00% of Sn, 0.80-1.10% of Nb, 0.10-0.40% of Fe, 0-0.1% of Cu or Bi or Ge, 0-0.03% of Si or S, 0.06-0.15% of O, less than 0.008% of C, less than 0.006% of N and the balance being Zr. Based on a Zr-Sn-Nb system alloy, other components used for improving the performance of the alloy are added, and appropriate component contents thereof are selected, so that the performance of the alloy provided meets the requirements of high burnup of the nuclear power reactor on the structural materials of the core. A product prepared from this alloy improves uniform corrosion resistance in ex-core pure water, especially in a lithium hydroxide aqueous solution, and improves nodular corrosion resistance in high-temperature steam.

Method for preparing adsorption drying filter element

The invention relates to a method for preparing an absorption drying filtration element, comprising the following steps: kaolin, molecular screen raw powder and alkali metal solution are mixed according to 40-60wt%, 20-30wt% and 10-30wt% respectively, pressed and squeezed into irregular granules; the concentration of the alkali metal solution is 5-25wt%; the granules are parched at the temperature of 60-150 DEG C, and after being roasted at the temperature of 550-780 DEG C, the granules are put and dipped into 25-45 DEG C and 1-3mol/L alkali metal solution for 1-3 hours, and after being parched at the temperature of 80-100 DEG C for 1-2 hours, the granules are cohered and formed into block material by adhesive; and then the block material is dried or roasted at the temperature of 200-700 DEG C, thus finished product is obtained. Compared with the prior art, the principal raw material of the invention is kaolin, the cost is low, the operation is easy, and the resources and energies can be ...

Quick and accurate self-leveling level

A quick and accurate self-leveling level comprises a first base, a second base, a third base, a fourth base and a fifth base; three telescopic spiral pins are arranged between the first base and the second base, and a reflector or a refractor is suspended under the third base and the fourth base by a cross movable joint or a movable joint quadrilateral respectively; when the reflector is suspended, a laser transmitter and an optical signal receiver consisting of CCD linear arrays are both arranged on the same base above or under the reflector; when the refractor is suspended, the laser transmitter and the optical signal receiver consisting of the CCD linear arrays are arranged on different bases at upper and lower sides of the refractor respectively; the laser transmitter is positioned in the center of the base, wherein one CCD linear array is X axis, the other CCD linear array is Y axis, and the X axis is mutually vertical to the Y axis; and an instrument is placed on the fifth base. The ...

Method for matching electronic map in urban geographic information system

The invention discloses a method for matching an electronic map in an urban geographic information system and relates to the field of geographic information system. Through the method, the road section which is required to be calculated for matching the electronic map can be reduced to less than 50% of the whole road section required to be calculated before being pretreated by pre-treating the electronic map, the road section which is required to be calculated is further reduced to 1/N (N is the quantity of grids) of the whole road section based on a map storing structure of square grids, and the speed for matching the electronic map can be increased to 1/2N and the accuracy rating can be increased to above 90%.

Silicon slice alignment method for silicon through hole interconnection

The invention belongs to the technical field of high-integration encapsulation, and particularly discloses a silicon slice alignment method for silicon through hole interconnection. The method comprises that: stacked and interconnected upper and lower silicon slices are aligned and corrected by adopting an electric method when a plurality of silicon slices are stacked and interconnected, so the alignment precision of the silicon slices can be improved and the interconnected resistance can be reduced. The integrated circuit chip manufactured by the method has the performance of high speed and low power consumption.

Method for optimizing roll shifting process of middle roll of six-roll cold mill

The invention discloses a method for optimizing a roll shifting process of a middle roll of a six-roll cold mill in the production process of cold-rolled strip steel. The roll shifting position of the middle roll is set optimally in a fully continuous cold rolling flying gauge change process so as to reduce the frequent roll shifting, abrasion and the influence of axial force on equipment, such as a roller, a bearing and the like. When the roll shifting of the middle roll is carried out, a roll shifting speed model of the middle roll is established by performing theoretical analysis on a rolling load and the axial force under the condition of different roll shifting speeds, and the influence of the axial force is reduced during the roll shifting of the middle roll. Through the process andthe controlling and optimizing method, the abrasion of the equipment, such as the roller, the bearing and the like can be reduced, and the production capacity of the six-roll cold mill is increased on the ...

A method for making horizontal dual pervasion field effect transistor

The invention discloses a method for manufacturing a laterally dual-diffused FET (field effect transistor), belonging to FET manufacturing field, the method is achieved by using the method for manufacturing LDMOS according to standard CMOS manufacturing processes, to realize LDMOS via chart design as following: defining a active layout to form a body extracting area, a source area, a drain area, a channel area, a drift area and a grid area of a LDMOS element; the source area, grid area and drain area are formed according to a re-doping injection layout; the drift area is disposed between the drain area and the channel area; both of the body extracting area and the source area are in grounding connection; using a N well layout to form a low-doping drift area of a N type LDMOS, or using P well layout to form a P type low-doping drift are of a P type LDMOS; using anti-silicification board to prevent the drift area from being silicified; the design of the source area, the drain area and the ...

Collision ionization type field effect transistor of sinking channel and manufacture method thereof

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a collision ionization type field effect transistor of a sinking channel and a manufacture method thereof. The collision ionization type field effect transistor comprises a semiconductor substrate, a drain region positioned at the bottom of the substrate and provided with a first doping type, a groove structure positioned in the substrate, a grid electrode covering in the groove, a dielectric layer positioned between the grid electrode and the semiconductor substrate, a source region positioned at both sides of the groove and the top of the substrate and provided with a second doping type, and an insulation dielectric layer positioned between the groove and the source region. The use of the sinking type channel structure and the collision ionization working principle ensures that the transistor can improve drive current while inhibiting a subthreshold oscillation range so as to further ...

Manufacturing method of groove-type power MOS (Metal Oxide Semiconductor) transistor

The invention discloses a manufacturing method of a groove-type metal-oxide-semiconductor (MOS) transistor using a side wall grid electrode. Metal or an alloy grid material is adopted in the MOS transistor so that the resistance of the grid is reduced; and simultaneously, when the MOS transistor is prepared, the grid is firstly etched and then a silicon substrate is etched in a self-aligning manner so that the parasitic capacitance between the grid electrode and the drain electrode is reduced. The grid resistance of the MOS transistor is reduced so that the signal delay can be reduced and the working speed can be increased; moreover, the parasitic capacitance between the small grid electrode and the drain electrode can reduce the energy consumption, and the efficiency of using the chip of the MOS transistor is improved.

Method for manufacturing PLC (Programmable Logic Controller) device

The invention belongs to the technical field of planar optic splitters, and particularly relates to a method for manufacturing an optic waveguide. The method comprises the steps of: forming a layer of photoresist on a glass substrate; carrying out photoetching to form a graph; forming an optic waveguide core layer with high refractive index in a groove between the photoresist; stripping the photoresist; and forming an upper film coating layer with low refractive index. The method for manufacturing the optic waveguide is simple in technological process, low in requirements of raw materials andproduction equipment, low in production cost and easy for realizing industrialized scale production.

Collagen-based interpenetrating polymer network tissue engineering cornea substitute and preparation method thereof

The invention relates to a collagen-based interpenetrating polymer network tissue engineering cornea substitute and a preparation method thereof. The cornea substitute is mainly prepared by taking collagen and 3-(methacrylamide)propyl-dimethyl(3-sulfopropyl)amide (MPDSAH) as raw materials and water as a solvent which react in the presence of a crosslinking agent and a photo initiator and are subjected to a pouring film forming processing process, and the composition and mixture ratio comprise that: the molar ratio range of carbodiimide to collagen amino group (calculated by the number of amino groups on collagen molecules) is 0.3-5.0:1; the molar ratio of the carbodiimide to N-hydroxyl succinimide is 1:1; the molar ratio of N,N'-bi(acryl)acystamine and the 3-(methacrylamide)propyl-dimethyl(3-sulfopropyl)amide is 0.01-0.10:1; and the molar ratio of the photo initiator Irgacure2959 to the 3-(methacrylamide)propyl-dimethyl(3-sulfopropyl)amide is 0.01-0.10:1. The cornea substitute has good ...

Method for selecting state vector in nonparametric regression short-time traffic flow prediction

The invention discloses a method for selecting the state vector in the nonparametric regression short-time traffic flow prediction, relating to the technical field of short-time traffic flow prediction. At four conditions comprising peak hours, even hours, low hours and all the day, by using the method provided by the invention, the forecast accuracy, the stability, the speed and the transportability are improved, and the operation time is shortened, thus verifying the effectiveness and the necessity of the method provided by the invention.

Dynamic substitution regulating method for excessive bending of working roll of cold rolling mill

The invention discloses a dynamic substitution regulating method for the excessive bending of the working roll of a cold rolling mill, which belongs to the technical field of cold rolled steel strips. The method comprises the following steps: determining parameters in a plate profile regulating efficiency coefficient matrix; determining an execution mechanism for realizing substitution regulation; 3, computing the regulation amount of every plate profile regulating mechanism; 4, making two substituting working roll bending control modes; 5, computing the bending of the working roll, the translation of an intermediate roll, the bending of the intermediate roll, and the output of a rolling mill inclination regulating mechanism in one substituting mode; and 6, computing the bending of the working roll, the translation of the intermediate roll, the bending of the intermediate roll, and the output of the rolling mill inclination regulating mechanism in the other substituting mode. The method ...

Depression channel type transistor made of ferroelectric material and manufacturing method thereof

The invention belongs to the technical field of high-speed switching, and in particular relates to a depression channel type transistor made of a ferroelectric material and a manufacturing method thereof. In the invention, a source electrode is made of materials with width of a narrow band gap, and a gate dielectric is a laminate of ferroelectric material and silicon oxide or high-k material. On one hand, the source electrode material with narrow band gap raises the drive current of the transistor; on the other hand, the use of a depression channel inhibits the addition of leakage current. Meanwhile, the ferroelectric material of the gate dielectric reduces the swing of subthreshold voltage and increases the switching speed of device. Furthermore, the invention also discloses a manufacturing method of the semiconductor field effect transistor.

Method for depositing high k gate dielectrics on atomic layer on graphene surface by adopting electric field induction

The invention belongs to the technical field of carbon-based integrated circuit manufacturing and in particular relates to a method for depositing high k gate dielectrics on an atomic layer on the graphene surface by adopting electric field induction. The method has the following beneficial effects: induced by the electric field, the delocalized extended pi bond on the graphene surface is damaged and the electron distribution orientation changes, so the uniform high k gate dielectrics can be directly deposited on the atomic layer on the graphene surface, without depositing a buffer layer in advance, thus simplifying the process; and the electrical properties of the graphene devices are improved.

Restraint device for bamboo-wood parting machine

A restraint device for a bamboo-wood parting machine comprises an upper restraint device and lower restraint devices, wherein the upper restraint device is installed on an upper panel of the parting machine, with height adjustable; the lower restraint devices are fixedly installed below the upper panel of the parting machine; the upper and lower restraint devices all comprise a restraint axle; the restraint axle is installed on an upper support and a lower support; restraint sleeves are installed on the restraint axle; restraint blocking pieces for restricting the parted bamboos are sleeved on the restraint sleeves at intervals; and the restraint blocking pieces corresponding to the upper and lower restraint devices are positioned on the same vertical plane. The device has the following advantages: when the higher bamboo panels (with height being more than 55mm) are parted, the upper and lower restraint devices are arranged at the end of the parting machine, thus ensuring dislocation of ...

Method for dyeing fluorescent microballons

This invention relates to a method for dyeing polymer microspheres to obtain fluorescent polymer microspheres. The method comprises: uniformly mixing fluorescein 0.01-80%, polymer microspheres 0.1-80%, emulsifier 0-10%, tackifier 0-10%, and solvent (one or more of good solvents and poor solvents) 18.9-99.89%, dyeing under 1-101 kPa in dark for 1-720 h, taking out the dyed polymer microspheres, and washing repeatedly. The obtained fluorescent polymer microspheres have such advantages as simple process, high fluorescent brightness, wide fluorescent spectrum range, uniform particle size distribution and low relative standard deviation, and can be used as absolute counting microspheres of flow cytometry, fluoroimmunoassay microspheres, biosensor, microfluidic chip, and calibrator of fluorescence microscope.

Process for producing gardening base material by mixing fermentation of corn stalk powder and peanut shell powder

The invention provides a method for making horticultural substrate by means of the mixed fermentation of corn stalk powder and peanut shell powder. The method carries out production according to the following steps of: (1) materials mixing; (2) high-temperature fermentation; (3) intermediate-temperature fermentation; (4) after ripening fermentation; (5) drying and packaging. The method takes corn stalk powder and peanut shell powder as fermentation raw materials, and has easily obtained raw materials and low cost which is reduced more than 40 percent as compared with grass carbon substrate; meanwhile, the method adopts staged temperature-control fermentation with the high-temperature fermentation stage beneficial to sterilization and the intermediate-temperature fermentation stage propitious to quicken up the decomposition of pectin, starch and saccharide while reducing the decomposition of lignin, hemicellulose and cellulose, thereby maintaining the particle diameter and the mechanical ...

Organic electroluminescent material as well as synthetic method and application thereof

The invention particularly relates to polyaryl-substituted pyridine derivative, a synthetic method thereof and the application of the polyaryl-substituted pyridine derivative to preparation of organic electroluminescent devices, belonging to the field of electroluminescent material. According to molecular design, large substitutional groups with rigid structures are introduced, so that the derivative has small possibility of forming the exciplex, the crystallization process of the derivative is inhibited, the film forming property of the derivative is improved, and the electric charge transmission property of the derivative is improved. Meanwhile, the modular coplanarity is damaged to cause emission peak hypochromatic shift, and the purpose of improving device property is achieved. The polyaryl-substituted pyridine derivative comprises the following structure.

Bamboo composite material wind-driven generator blade root preformation indoctrination technique

The invention relates to an instillation process for pro-forming a blade root of a blade of a wind turbine with bamboo compound material belonging to a technical field of the process of blade of the wind turbine, which is characterized in that a die is cleaned; a sealed belt is bonded around a flange surface and demoulding cloth is laid on the die; a bamboo sheet layer is laid on the demoulding cloth and compactly laid in the die side by side; after the bamboo sheet layer is laid, a layer of demoulding cloth is laid and then a vacuum bag is sealed outside a ply and the ply is sealed inside the vacuum bag by the sealed belt to form a vacuum sealed space; at last, resin is instilled in the die and after curing, demoulding and surface process, the ply is sealed in the vacuum bag to form an intermediate product of the pre-forming blade root. The intermediate product of the pre-forming blade root is laid in the corresponding position of the blade root in instillation of whole blade and at the ...

Resistance random memory based on columbium oxide film and preparation method thereof

The invention relates to a resistance random memory based on a columbium oxide film and a preparation method thereof, belonging to the technical field of memories. The memory unit comprises a substrate and a metal-insulation layer-metal (MIM) structure unit, wherein a top electrode of the MIM structure unit is metal films, such as titanium nitride and the like, the insulation layer is a columbiumoxide film, and a lower electrode adopts Pt or Au. The MIM structure in the invention represents excellent transformation and memory properties between high and low resistance states under the continuous scanning excitation of direct-current voltage. Further, the invention also provides the preparation method of the memory unit. The method comprises the preparation of a substrate material, the lower electrode, a dielectric film and an upper electrode and the like.

PRESSURE-DIFFERENCE TYPE CONTINUOUS LIQUID DENSITY MEASURING INSTRUMENT

This pressure difference type of liquid density continuous measurer is composed of measuring element, computer, and display meter. The influence of pressure, flow, flow regime and other properties of liquid to liquid density measurement is eliminated, so this instrument has correct measured value. It may be directly put in tank or connected to the pipeline with different pressures and flows to perform continuous measurement of liquid density. Its advantages include simple structure, reliable operation, and good shock, block-, vibration-and corrosion-resistances.

Device of self-recording and transmitting parameters of electric power

Method for preparing nanocrystal lithium iron phosphate anode material through co-precipitation

The invention discloses a method for preparing a nanocrystal lithium iron phosphate anode material through co-precipitation, which comprises the following steps of: 1, mixing crude materials, and stirring at high speed to obtain a precursor solution; 2, standing the precursor solution, cleaning, filtering and drying to obtain precursor powder; 3, adding an organic carbon source into the precursor powder and uniformly blending, and drying obtain the precursor powder which is coated by the organic carbon source; 4, roasting and cooling to obtain the organic carbon-coated nanocrystal lithium iron phosphate anode material; 5, mixing an inorganic carbon source with an anode material, adding adhesive and uniformly stirring to obtain an anode sizing agent; and 6, coating the anode sizing agent onto an aluminum foil substrate, drying and pressing to obtain a carbon-coated nanocrystal lithium iron phosphate anode material. With the adaption of the carbon-coated nanocrystal lithium iron phosphate ...

Method for smelting first heat after fetting of converter

The invention relates to a method for smelting first heat after fetting of a converter, which is characterized in that: when the first heat is smelted, 12 to 13 percent of waste steel is added, the dosage of light-burnt dolomite is 18 to 24kg/l, the dosage of active lime is 36 to 44kg/l, and proper amount of algam balls and laterite are added. The method greatly reduces the probability of the overproof of end point phosphorus and ensures the product quality and production efficiency of the converter in the production process through measures such as adjusting heat balance, improving the addition scheme of auxiliary materials and the like.

SEMI-FLOATING-GATE POWER DEVICE AND MANUFACTURING METHOD THEREFOR

The disclosure belongs to the technical field of semiconductor power devices, specifically relates to a semi-floating-gate power device, and comprises the gallium nitride high-electron-mobility transistor, the diode and the capacitor; the anode of the diode is connected with the gate of the gallium nitride high-electron-mobility transistor and the cathode of the diode is connected with the source or the channel area of the gallium nitride high-electron-mobility transistor; one end of the capacitor is connected with the gate of the gallium nitride high-electron-mobility transistor and the other end of the capacitor is connected with the external voltage signal. The semi-floating-gate power device has a simple structure, is easy to manufacture, adapts to high-voltage and high-speed operation and has very high reliability, can increase the threshold voltage of the gallium nitride high-electron-mobility transistor in the working state, so that the transistor can serve as the power switch tube better. 1. A semi-floating-gate power device comprises the gallium nitride high-electron-mobility transistor , and:a diode whose anode is connected with the gate of the gallium nitride high-electron-mobility transistor and whose cathode is connected with the source or the channel area of the gallium nitride high-electron-mobility transistor;a capacitor whose one end is connected with the gate of the gallium nitride high-electron-mobility transistor and whose other end is connected with an external voltage signal.2. The semi-floating-gate power device as claimed in claim 1 , wherein the diode is a Schottky diode.3. The semi-floating-gate power device as claimed in claim 2 , wherein the semi-floating-gate power device comprises a semiconductor substrate claim 2 , and a gallium nitride barrier layer is arranged on the semiconductor substrate claim 2 , a gallium nitride channel layer is arranged on the gallium nitride barrier layer claim 2 , and a gallium nitride aluminum isolation ...

Semiconductor memory structure and manufacturing method thereof

The invention belongs to the technical field of non-volatile semiconductor memories and in particular discloses a semiconductor memory structure. The semiconductor memory structure comprises at least one semiconductor substrate, a storage cell for storing information and a tunnel transistor structure, wherein the tunnel transistor is used for performing control of erase-write operation and read operation on the semiconductor memory. The invention also discloses a method for manufacturing the semiconductor memory structure by using the self aligned technology. Meanwhile, a grid mask of the tunnel transistor can be manufactured only by making a contact point of a word line at a word line terminal. The manufacturing method simplifies the manufacturing technology of the semiconductor memory, makes the manufacturing process more stable, and is applied to the manufacture of a memory chip.

Integrated circuit of recessed channel-type PNPN field effect transistor and manufacturing method thereof

The invention belongs to the technical field of integrated circuits, particularly discloses a semiconductor integrated circuit. The semiconductor integrated circuit comprises a grid control PNPN transistor and an MOS transistor. Both the grid control PNPN transistor and the MOS transistor adopt a recessed type channel structure, thereby increasing the driving current, inhibiting increasing of the leakage current, reducing the power consumption of a chip and improving the performance of the chip. The invention also discloses a manufacturing method of the semiconductor integrated circuit. The semiconductor integrated circuit is particularly suitable for manufacturing integrated circuit chips with low power consumption.

Organic electronic transmission and/or hole barrier materials, synthesis method and use thereof

The invention belongs to the field of organic electronic transmission and/or hole barrier materials in organic electroluminescent devices, in particular relates to polyaryl substituted pyridine derivatives for the organic electronic transmission and/or hole barrier materials, a synthetic method thereof, and use for preparing the organic electroluminescent devices by using the polyaryl substituted pyridine derivatives. Through molecular design in the invention, large substituent groups with rigid structures are introduced so that exciplexes can not be easily formed by the material, the course of crystallization of the material is inhibited, the film formation of the material is improved, and the charge transmission performance of the material is increased. Synchronously, the emission peak of the material has blue shift due to the damage of molecular coplanarity so that the purpose of improving the performances of the devices is achieved. The polyaryl substituted pyridine derivatives of the ...

Method for etching copper

The invention belongs to the technical field of microelectronics, and in particular discloses a method for etching copper. The method comprises the following steps of: etching the copper by adopting a wet etching method and the technology of facilitating electrochemical etching by using optical irradiation; and then filling a low-k medium on the copper. Because of the anisotropy property of light, the wet etching method provided by the invention also has the anisotropy property so as to realize the anisotropic etching of the copper and various other metals and solve the problems of the low-k etching, holes and the like in the copper interconnection of integrated circuits at the same time.

Metal modified molecular screen and preparation method thereof

The invention provides a metal modified molecular sieve, the anhydrous chemical expression of a reaction system of the raw materials of which is shown as the following formula (I): 1R question mark mF question mark nMe question mark (SiAlP)O2, (I); wherein, R refers to an organic amine template agent, I refers to the mole number of R and is equal to 0.03 to 0.6, F refers to fluorion, m refers to the mole number of the fluorion and is equal to 0.03 to 0.6, Me refers to metal heteroatom existing in the molecular sieve, n refers to the mole number of Me and is equal to 0.02 to 0.60, andx, y and z are the mole number of Si, Al and P respectively, with the respective value range of: x: 0.01 to 0.98, y: 0.01 to 0.7 and z: 0.01 to 0.6 and meeting: x plus y and plus z is equal to 1. Theinvention provides a Si-Al-P crystalloid molecular sieve catalyst with high efficiency and small particle size, the acid amount and the acidity of which can be regulated simultaneously.

Method for preparing dry filter core for refrigerating system

The invention relates to a new formula of drying filter core for refrigeration system use. It mixes one or several of the molecular sieve raw powder, powder alumina, clay, powder active C, and uses liquid silicate cohesive agent to cohere them to grains, and dry the mixture in 100-300 Deg. C, and then add P aluminate cohesive agent to mix evenly with the grain materials, and press to form, at last activate in 200-600 Deg. C to get dried block filter core product. The method has short technique flow, simple operation, low energy consumption and cost. It is an environmental protection method. The filter core of the invention has strong capability of water absorbing to ensure the cleanness of the refrigeration system.

Method for connecting strip section for blades of wind driven generator

The invention relates to blades of a wind driven generator. A main structural material of the blades is strip bamboo and strip glass fiber reinforced plastic pultrusion sections, and the strip bamboo is connected with the strip glass fiber reinforced plastic pultrusion sections by adopting a special beveling mode.

Transverse and longitudinal diffusion type field effect transistor of depressed channel and manufacturing method thereof

The invention belongs to the technical field of semiconductor power devices and specifically discloses a transverse and longitudinal diffusion type field effect transistor of a depressed channel. By adopting the depressed channel and a longitudinal diffusion process, the field effect transistor greatly reduces the sizes of the devices, inhibits short-channel effects, also reduces the parasitic capacitances of grid leaks in device structures when inhibiting the potential barrier lowering of drain induced source end, and improves the response frequencies of the devices, i.e. the response frequencies of the devices are enhanced when improving the integrated levels of chips. The invention also discloses a manufacturing method of the transverse and longitudinal diffusion type field effect transistor of the depressed channel.

Open-rack three-roller oblique rolling extender

The invention discloses an open-rack three-roller oblique rolling extender, which solves the problem that axial positions of three rollers are unadjusted and the problem that the offset, generated by assembling and wearing, at the axial position of a roller shoulder is difficult to correct in the prior art. The open-rack three-roller oblique rolling extender comprises an extender base (12), a lower rack (5), left and right lower roller screw-down drive and balance mechanisms and a roller assembly arranged on the lower rack (5), wherein an upper rack (1) is provided with an upper roller screw-down drive and balance mechanism (2), an upper roller box (3) and an upper roller assembly (4); the upper rack (1) is provided with a left upper guide plate mechanism (13) and a right upper guide plate mechanism (14) respectively, and the lower rack (5) is provided with a lower guide plate mechanism (15); and four wedge blocks are arranged on the lateral surface of the upper roller box (3) respectively ...

Metal modified molecular screen and preparation method thereof

The invention provides a metal modified molecular sieve, the anhydrous chemical expression of a reaction system of the raw materials of which is shown as the following formula (I): 1R question mark mF question mark nMe question mark (SiAlP)O2, (I); wherein, R refers to an organic amine template agent, I refers to the mole number of R and is equal to 0.03 to 0.6, F refers to fluorion, m refers to the mole number of the fluorion and is equal to 0.03 to 0.6, Me refers to metal heteroatom existing in the molecular sieve, n refers to the mole number of Me and is equal to 0.02 to 0.60, and x, y and z are the mole number of Si, Al and P respectively, with the respective value range of: x: 0.01 to 0.98, y: 0.01 to 0.7 and z: 0.01 to 0.6 and meeting: x plus y and plus z is equal to 1. The invention provides a Si-Al-P crystalloid molecular sieve catalyst with high efficiency and small particle size, the acid amount and the acidity of which can be regulated simultaneously.

Watertight building structure system

The invention provides a watertight building structure system which comprises an outer wall and an inner wall, wherein the outer wall comprises a reinforced concrete structure wall and a brickwork filling wall; the reinforced concrete structure wall and the brickwork filling wall are stuck through concrete; and the inner wall adopts a reinforced concrete structure wall or the combination of the reinforced concrete structure wall and the brickwork filling wall. In the watertight building structure system provided by the invention, the reinforced concrete structure wall of the outer wall has high watertight reliability, and the building cost is reduced in combination with the brickwork filling wall. Furthermore, through the reinforced concrete structure wall adopted by the inner wall, the water tightness is greatly reinforced.

Autoregistration semiconductor memory structure and manufacturing method thereof

The invention belongs to the technical field of non-volatile memory devices, particularly discloses an autoregistration semiconductor memory structure. The autoregistration semiconductor memory structure adopts a tunneling transistor to control the rewrite operation, reading operation and the like of a phase change memory or a resistance change memory, and a vertical grid-controlled diode structure in the tunneling transistor not only can satisfy the requirements on writing in the heavy current of the resistance change memory and the phase change memory, but also can improve the array density of the memory devices. Meanwhile, the invention further discloses a method for manufacturing the semiconductor memory structure, which simplifies the manufacturing process of the memory device, makes the manufacture procedure stabler, and is particularly applicable to manufacturing memory chips.

Method for integrating copper and materials with low dielectric coefficient

The invention belongs to the technical field of a semiconductor, in particular to a method for integrating copper and materials with the low dielectric coefficient. The method comprises the following steps: using a wet method for etching; using light irradiation for promoting the copper etching by the electrochemical etching technology; and then, filling media with the low dielectric coefficient on the copper for forming the interconnection of the copper and low-k media. Because of the feature of the anisotropic property of light, the invention can realize the anisotropic property etching of the copper and various other metals, and at the same time, the filling of the low-k media is carried out after the copper etching, so the low-k material etching problem in the copper interconnection of integrated circuits and the problems caused by holes in the media are solved.

Method for preparing vacuum film-coating zinc sulfide

SILICON-BASED OPTICAL ANTENNA WITH REFLECTIVE LAYER AND PREPARATION METHOD THEREFOR

Embodiments of the present disclosure provide a silicon-based optical antenna with a reflective layer and a preparation method therefor. The silicon-based optical antenna comprises: an SOI substrate, the SOI substrate at least comprises a bottom silicon layer, a buried oxide layer, and a top silicon layer, the buried oxide layer is located between the bottom silicon layer and the top silicon layer, the top silicon layer is etched to form a row of waveguides, spacings between the waveguides in the row of the waveguides are in an uneven distribution, each waveguide of the row of the waveguides is etched with gratings, the bottom silicon layer is formed with a groove directly reaching a surface of the buried oxide layer facing the bottom silicon layer, and the surface of the buried oxide layer in the groove is formed with a metal reflective layer. 1. A silicon-based optical antenna with a reflective layer , wherein the optical antenna comprises: a silicon-on-insulator (SOI) substrate , the SOI substrate at least comprises a bottom silicon layer , a buried oxide layer , and a top silicon layer , the buried oxide layer is located between the bottom silicon layer and the top silicon layer , the top silicon layer is etched to form a row of waveguides , spacings between the waveguides in the row of the waveguides are in an uneven distribution , each waveguide of the row of the waveguides is etched with gratings , the bottom silicon layer is formed with a groove directly reaching a surface of the buried oxide layer facing the bottom silicon layer , and the surface of the buried oxide layer in the groove is formed with a metal reflective layer.2. The optical antenna according to claim 1 , wherein a region where the metal reflective layer is located corresponds to a region where the gratings are located and is larger than the region where the gratings are located.3. The optical antenna according to claim 1 , wherein a thickness of the metal reflective layer corresponds to a ...

Service cluster and energy-saving method and device thereof

The invention provides a service cluster and an energy-saving method and device thereof. The method comprises the following steps of: acquiring loads corresponding to preset quantity of nodes in the server cluster; and in the preset quantity of nodes, if the load of the first node is less than or equal to the resource surplus of the second node, migrating a process corresponding to the operation on the first node to the second node for operating. By applying the technical scheme provided by the invention, the loads of the nodes and the load surplus resources are acquired; when the load surplus resources of other nodes can satisfy the load requirement on one node, the operation on one node can be migrated to other nodes, and the node subjected to operation migration is in an idle state and even can be closed; and therefore, the electricity consumption of the whole server cluster is reduced, and the operation cost is saved.

Semiconductor memory device and manufacturing method thereof

The invention discloses a semiconductor memory device, which comprises a source, a drain, two floating gate regions, a control gate, and a substrate pole, and the floating gate regions of the semiconductor memory device are used for storing charges. The invention further discloses a manufacturing method of the semiconductor memory device. The manufactured semiconductor memory device has the advantages of small unit area, simple manufacturing process and the like, and the use of the invention can reduce the manufacturing cost of a memory chip and improve the storage density.

Method for preparing massive dryer for refrigeration system

Mobile hydrogen-generating hydrogen-storing integrated device and hydrogen supplying method thereof

The invention relates to a movable integrated device for generation and storage of hydrogen and a hydrogen supply method, which belongs to the hydrogen preparation technical field. The movable integrated device for generation and storage of hydrogen comprises a hydrogen generator and a hydrogen storage tank. The device is characterized in that: the hydrogen generator is connected with a gas-water separator through a pipeline, and the gas-water separator is connected with a hydrogen purifier through a pipeline; the hydrogen purifier is connected with the hydrogen storage tank through a pipeline, and the hydrogen storage tank is provided with a temperature controlling apparatus. The hydrogen supply method is that: chemical reaction happens in the hydrogen generator to produce hydrogen, and the water and the hydrogen are separated by the gas-water separator; then purified by the hydrogen purifier, the hydrogen is stored into the storage tank after temperature regulated; while the hydrogen ...

Nanowire MOS transistor based on III-V element and preparation method thereof

The invention belongs to the technical field of micro-electronics, particularly disclosing a nanowire MOS transistor and a preparation method thereof. The nanowire MOS transistor uses metallic nickel to serve as the drain and source diffusion material of III-V semiconductor nanowire and utilizes the nickel diffusion mechanism under high temperature to ensure that metallic nickel diffuses to III-V material; formed low-resistance Ni-III-V alloy serves as the drain and source diffusion material of the III-V semiconductor nanowire MOS pipe so as to realize ohmic contact between the drain and source material and channel material. The MOS transistor disclosed by the invention has the advantages of simple structure, convenient manufacture, small contact resistance and the like, can effectively lower the possibility of producing parasitic capacitance and effectively lowers the cut-off current of the MOS transistor. Meanwhile, the invention also discloses a preparation method of the nanowire MOS ...

Surface modification method for silicon quantum dots

The invention discloses a surface water-solubility modification method for silicon quantum dots. The method comprises the following steps: firstly, dissolving silicon quantum dots in an organic solvent and then adding superoxide; secondly, heating the above-got solution under a water-free and oxygen-free condition, and purifying to obtain the finished products. The invention has the advantage of simple technical operation, controllable reaction conditions and short reaction time so as to realize a quick modification of a mass of silicon quantum dots.

Method for matching electronic map in urban geographic information system

The invention discloses a method for matching an electronic map in an urban geographic information system and relates to the field of geographic information system. Through the method, the road section which is required to be calculated for matching the electronic map can be reduced to less than 50% of the whole road section required to be calculated before being pretreated by pre-treating the electronic map, the road section which is required to be calculated is further reduced to 1/N (N is the quantity of grids) of the whole road section based on a map storing structure of square grids, andthe speed for matching the electronic map can be increased to 1/2N and the accuracy rating can be increased to above 90%.

Method for preparing small-crystal-size SAPO-34 zeolite

The invention relates to a method for preparing small-crystal-size SAPO-34 zeolite, which comprises the following steps that: the small-crystal-size SAPO-34 zeolite can be obtained through hydrothermal synthesis gelling and aging treatment, hydrogen peroxide oxidation treatment, ultrasonic dispersion and vacuum drying. Compared with the prior art, the invention has simple preparation process, easy condition control and lower raw material cost, the crystal size of the small-crystal-size SAPO-34 zeolite is 300-500nm, and the distribution of crystals is uniform; and the zeolite can be used for reactions which utilize the conversion of methanol to prepare ethylene, propylene and other low-carbon olefins.

Preparation method of self-aligned tunneling field effect transistor

The invention belongs to the field of microelectronic technique, in particular discloses a preparation method of a tunneling field effect transistor (TFET). The invention uses a self-aligned technology to form the TFET. The preparation method of the TFET has simple technology, the technology for forming the TFET has a self-aligned characteristic, and the forming processes of a source electrode and a drain electrode of the TFET can be separated, thus a source electrode structure different from a substrate material can be formed easily.

Accumulator charging and discharging control method for smoothening power fluctuation of wind power station

The invention provides an accumulator charging and discharging control method for smoothening the power fluctuation of a wind power station, belonging to the technical field of wind power generation control. The control method comprises the following steps of: charging the accumulator when the capacity of the accumulator satisfies the operation requirement and the active power is larger than a permissible upper limit value of a power grid; and discharging the accumulator when the active power is smaller than a permissible lower limit value of the power grid, or else enabling the accumulator to exit the operation. The invention estimates the residual capacity of the accumulator by detecting the active power output by the system and the charge state of the accumulator to control the operation mode of the accumulator and achieve the aim of smoothening the output power fluctuation of the wind power station; and the reactive loss of a converter is reduced by adopting a PWM (Pulse Width Modulation ...

High pressure resistant lateral direction bilateral diffusion MOS transistor

The present invention discloses a transversal bilateral diffusion MOS transistor with high pressure resistant, which belongs to micro-electronics semi-conductor device field. The device includes a gate region, a source area, a drain region, a tagma, a gate medium and a drift region, the setting drift region is placed between the tagma and the drain region, and the doping type is opposite to the tagma, an insulating medium region and a doping region which is opposite to the doping type of the drift region are equipped in the drift region, and the doping concentration of the doping region is higher than that of the drift region, the doping region is adjacent to the tagma, however the insulating medium region is adjacent to the drain region. Because the insulating medium region and the doping region are inducted into the drift region at the same time, the effective depth of the drift region is reduced effectively to make the electric field more uniform and increase the equivalent length of ...

Semiconductor memory structure and control method thereof

The invention belongs to the technical field of semiconductor nonvolatile memories, and particularly discloses a semiconductor memory structure and a control method thereof. The semiconductor memory structure provided by the invention comprises a memory cell used for storing information and a tunneling field effect transistor connected with the memory cell, wherein the tunneling field effect transistor is used for controlling the semiconductor memory, for example, performing rewriting operations and reading operations. A plurality of semiconductor memory structures form a semiconductor memory array. The control method provided by the invention comprises resetting, setting and reading steps. A vertical grid-controlled diode structure in the tunneling field effect transistor can meet requirements on high current in the writing of a resistive random access memory and a phase change memory and increase the density of the memory array, and is suitable for manufacturing a semiconductor memory ...

Prediction method of city water-requirement time series-exponent smoothing model

The invention discloses a prediction method of a city water-requirement time series-exponent smoothing model, which comprises the steps of: defining the time series of historical data based on the historical data of city water consumption; calculating the T4253H smoothing series of a water-consumption historical data-time series by utilizing a smoothing processing method so as to reject data abnormal values and finish the smoothing processing of the historical data; for the data in each period of T4253H smoothing series from the current period, establishing an index smooth model by reducing the weighing of each period according to the index law; and predicting the water consumption of the city in future. The prediction method has the advantages of stable performance, clear principle, simple and convenient prediction process and high prediction result precision. Moreover, prediction errors can meet the water supply planning of cities, and the scheduling and the application of water works ...

Bamboo composite material wind-driven generator blade root preformation indoctrination technique

The invention relates to an instillation process for pro-forming a blade root of a blade of a wind turbine with bamboo compound material belonging to a technical field of the process of blade of the wind turbine, which is characterized in that a die is cleaned; a sealed belt is bonded around a flange surface and demoulding cloth is laid on the die; a bamboo sheet layer is laid on the demoulding cloth and compactly laid in the die side by side; after the bamboo sheet layer is laid, a layer of demoulding cloth is laid and then a vacuum bag is sealed outside a ply and the ply is sealed inside the vacuum bag by the sealed belt to form a vacuum sealed space; at last, resin is instilled in the die and after curing, demoulding and surface process, the ply is sealed in the vacuum bag to form an intermediate product of the pre-forming blade root. The intermediate product of the pre-forming blade root is laid in the corresponding position of the blade root in instillation of whole blade and atthe ...

Method for correcting cold-rolled strip steel shape control target value

The invention discloses a method for correcting a cold-rolled strip steel shape control target value. In the method, a basic shape target value curve model is made according to the requirement of subsequent processes on the convexity of the strip steel and strip instability model criterion; and four compensating curves of coiled shape, recoiling machine mounted geometric error, strip steel transverse temperature difference and strip steel side reduction and two manually adjusted shape additional curves are formed according to adverse effects of temperature, coiled shape, equipment mounting error and the like on shape measurement. An actual shape measurement point is interpolated into a plurality of characteristic points along a width direction, and the data processing process is simplified. When the convexity of the strip steel is effectively controlled, the shape control effect is guaranteed, and the requirements of the subsequent processes on the convexity of the strip steel and theshape ...

Pyrazolopyridine coumarin dye derivative, and synthesis method and application thereof

The invention belongs to the fields of fluorescent dyes and laser dyes, and in particular, relates to a pyrazolopyridine coumarin dye derivative, and a synthesis method and application thereof. The pyrazolopyridine coumarin dye derivative in the invention has extremely high fluorescent quantum yield. Simultaneously, the coumarin dye derivative in the invention has superior thermal, light and electrochemical stabilities, and can be used as a fluorescent dye, a laser dye, an organic electroluminescence material, a fluorescent labeling material, a fluorescent chemosensitive material and the like. The pyrazolopyridine coumarin dye derivative in the invention has the structure described in the specification.

Process for producing composite silicophosphoaluminate molecular sieve by in situ synthesis

The invention relates to a method for in situ synthesizing a composite type silicon-phosphorus-aluminum molecular sieve, which comprises the following steps: taking kaolin as a raw material, preparing kaolin microspheres by spraying and drying, obtaining active kaolin microspheres after activating treatment, taking the active kaolin microspheres as a carrier, and preparing the silicon-phosphorus-aluminum molecular sieve using the in situ synthesizing technique together with an aluminum source, a phosphorus source, a silicon source, deionized water and an organic template agent. Compared with the prior art, the method for in situ synthesizing a composite type silicon-phosphorus-aluminum molecular sieve has reasonable technique, adopts the active kaolin microspheres carrier to disperse the active components, improves the intensity of the catalyst, intensifies the wear resistance of the catalyst, lowers the production cost, and simplifies the preparation process of the catalyst. The prepared ...

Renewable fluorescent probe for selectively detecting bioactive sulfydryl compound in cell and synthetic method and application thereof

The present invention relates to a renewable fluorescent probe for selectively detecting bioactive sulfydryl compound in cells and a synthetic method and the application thereof. Coumarin-3-sulfydryl compound with R1, R2, R3, R4 and R5 substituents is dissolved in dry organic solvent; thiosulfate semicarbazide which is dissolved in organic solvent and provided with an R6 substituent is dripped slowly under refluxing stirring for reaction; the mixture is filtered to remove the organic solvent and then is dried in vacuum to obtain a ligand; the ligand is dissolved in the dry organic solvent; HgX2 which is dissolved in the organic solvent is dripped slowly under refluxing stirring for reaction so as to obtain solid precipitate; the mixture is filtered and then the solid precipitate is dried in vacuum to obtain the fluorescent probe of formula I. The fluorescent probe can be used for detecting the bioactive sulfydryl compound in a biosystem, analyzing and detecting the bioactive sulfydryl compound ...

Semiconductor photosensitization device, production method and application thereof

The invention discloses a semiconductor photosensitization device which comprises a source electrode, a drain electrode, a control grid, a floating grate region, a substrate, and a p-n node diode for connecting a floating gate region and a drain electrode. The floating grate region of the semiconductor photosensitization device is used for storing charges, and the floating grate potential of the semiconductor photosensitization device is related to light exposure intensity and time, thus, the invention can be used as a semiconductor photosensitization device. The invention also discloses production methods of the semiconductor photosensitization device and an image sensor, as well as an image sensor formed by arrays formed by the semiconductor photosensitization device. The semiconductor photosensitization device can simplify the design of a single pixel unit in a traditional image sensor and reduce the area occupied by the single pixel unit, thereby improving the pixel density of theimage ...

Short-term traffic flow prediction system

The invention discloses a short-term traffic flow prediction system, belonging to the field of traffic flow prediction system. A data processing subsystem receives traffic flow data from a traffic information collection platform through the Socket communication, and maintains a location table of the prediction subsystem; the data processing subsystem looks up the prediction subsystem that corresponds to the code in the location table of the prediction subsystem in accordance with the code of the road to be predicted and sends the calculating data to the prediction subsystem after calculating the data of the road to be predicted during the prediction cycle; the data processing subsystem receives the calculating data and maintains the location table of the prediction module on a mainframe; the data processing subsystem looks up in the location table of the prediction module in accordance with the code of the road to be predicted and predicts the road to be predicted; the data processing subsystem ...

Concentration evaporation method for producing glucose

The invention belongs to the technical field of glucose production, and particularly relates to a concentration evaporation method for producing glucose. The method mainly solves the technical problems of high cost, short service life and narrow concentration range of the concentration evaporation method in conventional glucose production. The invention adopts the technical scheme that: steam is conveyed to an effect I evaporator, an effect II evaporator and an effect III evaporator through outer pipes; the secondary gas generated in the effect I evaporator, the effect II evaporator and the effect III evaporator is separated from syrup through an effect I separation chamber, an effect II separation chamber and an effect III separation chamber; and the separated secondary gas is sequentially compressed in two turbine compression fans and heated to form secondary steam, and the secondary steam is recycled in the effect I, II and III evaporators and provides heat for the effect I, II and III ...

Power Device Using Photoelectron Injection to Modulate Conductivity and the Method Thereof

The present invention belongs to the technical field of semiconductor devices, and discloses a power device using photoelectron injection to modulate conductivity and the method thereof. The power device comprises at least one photoelectron injection light source and a power MOS transistor. The present invention uses photoelectron injection method to inject carriers to the drift region under the gate of the power MOS transistor, thus modulating the conductivity and further decreasing the specific on-resistance of the power MOS transistor. Moreover, as the doping concentration of the drift region can be decreased and the blocking voltage can be increased, the performance of the power MOS transistor can be greatly improved and the application of power MOS transistor can be expanded to high-voltage fields. 1. A power device using photoelectron injection to modulate conductivity comprises at least one photoelectron injection light source and a power MOS transistor.2. The power device using photoelectron injection to modulate conductivity of claim 1 , wherein the photoelectron light source is a light emitting diode.3. The power device using photoelectron injection to modulate conductivity of claim 1 , wherein the power MOS transistor is a planar power MOS transistor claim 1 , or a trench-gate power MOS transistor.4. The power device using photoelectron injection to modulate conductivity of claim 1 , wherein the anode of the photoelectron injection light source are connected with the gate of the power MOS transistor; the cathode of the photoelectron injection light source are connected with the source of the power MOS transistor.5. The power device using photoelectron injection to modulate conductivity of claim 1 , wherein the cathode of the photoelectron injection light source are connected with the gate and source of the power MOS transistor; the anode of the photoelectron injection light source are connected with the source of the power MOS transistor.6. The power ...

GATE CONTROLLED PN FIELD-EFFECT TRANSISTOR AND THE CONTROL METHOD THEREOF

The present invention belongs to the technical field of semiconductor devices, and more specifically, relates to a gate-controlled PN field-effect transistor and the control method thereof The gate-controlled PN field-effect transistor disclosed by the present invention comprises a semiconductor substrate region, a drain region and a source region on the left and right sides of the substrate region, and gate regions on the upper and lower sides of the substrate region. The gate-controlled PN field-effect transistor works in the positive bias state of the source-drain PN junction and is conducted from the middle of the substrate region. The gate-controlled PN field-effect transistor provided by the present invention decreases the leakage current and increases the drive current at the same time, namely decreases the chip power consumption and improves the chip performances at the same time. The present invention further discloses a method for controlling the gate-controlled PN field-effect transistor, including cut-off and conduction operation. 1. A gate-controlled PN field-effect transistor comprising:a semiconductor substrate region;a source region and a drain region on the left and right sides of the semiconductor substrate region;gate dielectric layers on the upper and lower sides of the semiconductor substrate region;a gate covering the gate dielectric region.2. The gate-controlled PN field-effect transistor of claim 1 , wherein the semiconductor substrate is made of single-crystalline or polycrystalline silicon.3. The gate-controlled PN field-effect transistor of claim 1 , wherein the semiconductor substrate is with a thickness no more than 20 nm.4. The gate-controlled PN field-effect transistor of claim 1 , wherein the gate dielectric layers are one of SiO claim 1 , SiNand high k materials or the combination of some of them.5. The gate-controlled PN field-effect transistor of claim 1 , wherein the gate is made of gate materials such as TiN claim 1 , TaN claim 1 ...

Open multi-strand cord

A steel cord ( 10 ) adapted for the reinforcement of rubber products, comprises a core strand ( 12 ) and six peripheral strands ( 14 ) concentrically surrounding the core strand ( 12 ). Each of the core and peripheral strands ( 12, 14 ) comprises a centre of two or more centre filaments ( 16 ) and two layers of filaments surrounding the centre. The core strand ( 12 ) has a diameter D 1 which is greater than the diameter D 2 of the peripheral strands ( 14 ). All the filaments ( 18, of each layer have substantially the same diameter and a radially outer layer has a twist angle which is greater than a twist angle of a radially inner layer of the same strand. Each of the strands ( 12, 14 ) in the cord is composed of no more than twenty-six filaments ( 16, 18, 20 ) being twisted together.

MICROELECTRONIC DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF

The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well. 1. A Semiconductor device which is a tunneling field effect transistor type semiconductor device , in which the source material is characterized as narrow band-gap material; meanwhile , there is a u-groove channel.2. The semiconductor device of claim 1 , the said narrow band-gap material is SiGe.3. The semiconductor device of claim 1 , the said tunneling field effect transistor is the complementary tunneling field effect transistor claim 1 , composed by the n-type and p-type TFET which have source regions made of narrow band-gap materials.4. The semiconductor device of claim 3 , the said narrow band-gap material of the said n-type TFET is SiGe or Ge.5. The semiconductor device of claim 3 , the said narrow band-gap material of the said p-type TFET is made of InGaAs or AlGaAs.6. A method of making the semiconductor device of claim 1 , containing the following processes:providing a semiconductor substrate,forming the drain doping region with a first conductivity type,etching a U-groove channel recessed into the said semiconductor substrate,depositing oxide dielectric layer and high-k layer in sequence,forming the gate structure,etching out part of the said high-k material, oxide dielectric layer and substrate,growing ...

RESISTIVE RANDOM ACCESS MEMORY WITH ELECTRIC-FIELD STRENGTHENED LAYER AND MANUFACTURING METHOD THEREOF

This invention belongs to the technical field of memories and specifically relates to a resistive random access memory structure with an electric-field strengthened layer and a manufacturing method thereof. The resistive random access memory in the present invention can include a top electrode, a bottom electrode and a composite layer which is placed between the top electrode and the bottom electrode and have a first resistive switching layer and a second resistive switching and electric-field strengthened layer; the second resistive switching and electric-field strengthened layer cab be adjacent to the first resistive switching layer and have a dielectric constant lower than that of the first resistive switching layer. The electric-field distribution in the RRAM unit is adjustable. 1. A resistive random access memory comprises a top electrode , a bottom electrode and a composite layer which is placed between the top electrode and the bottom electrode and consists of a first resistive switching layer and a second resistive switching and electric-field strengthened layer;the second resistive switching and electric-field strengthened layer is adjacent to the first resistive switching layer and has a dielectric constant lower than that of the first resistive switching layer.2. The resistive random access memory of claim 1 , wherein the second resistive switching and electric-field strengthened layer is made of SiO claim 1 , or AlO.3. The resistive random access memory of claim 1 , wherein the first resistive switching layer is made from HfO claim 1 , ZrO claim 1 , NbOor mixtures thereof.4. The resistive random access memory of claim 1 , wherein the bottom electrode is made of a metal material such as Pt/Ti claim 1 , Au/Ti claim 1 , TiN claim 1 , Ru or Cu.5. The resistive random access memory of claim 1 , wherein the top electrode is made from a metal material such as Al claim 1 , Pt claim 1 , Ru claim 1 , TiN claim 1 , or TaN.6. A method for manufacturing the resistive ...

NiO-based Resistive Random Access Memory and the Preparation Method Thereof

The present invention belongs to the technical field of memory storage and specially relates to a NiO-based resistive random access memory system (RRAM) and a preparation method thereof. The RRAM is comprised of a substrate and a metal-insulator-metal (MIM) structure, wherein the electrodes are metal films, such as copper, aluminum, etc., capable of being applied to the interconnection process, and the resistive switching insulator is an AlO/NiO/AlOlaminated dielectric film. The MIM structure in the invention shows stable switching between the bi-stable resistance states as well as memory features; compared with the RRAM that only uses a single NiO-based dielectric film, the storage window is increased, and the resistance stability is improved. Therefore, the NiO-based RRAM has a good prospect in actual application. The present invention further provides a method for preparing the abovementioned memory storage system. 1. A NiO-based resistive random access memory characterized in that , comprising a metal-insulator-metal structure , wherein the metals form metal films as top and bottom electrodes and the insulator layer has an AlO/NiO/AlOlaminated structure.2. The resistive random access memory of claim 1 , wherein the top and bottom electrodes are made of copper claim 1 , aluminum claim 1 , gold claim 1 , titanium claim 1 , titanium nitride or tantalum nitride.3. The resistive random access memory of claim 1 , in the AlO/NiO/AlOlaminated structure claim 1 , the AlOlayer is prepared by atomic layer deposition claim 1 , while the NiO layer is prepared by physical vapor deposition or atomic layer deposition.4. The preparation method of the resistive random access memory of is as follows:{'sub': '2', '1) grow a SiOdielectric layer on a Si substrate by thermal oxidation or chemical vapor deposition, to reduce the parasitic effect and prevent Si and the bottom electrode from forming an alloy;'}2) prepare the bottom electrode by electroplating, steaming or sputtering;{' ...

SILICON WAFER ALIGNMENT METHOD USED IN THROUGH-SILICON-VIA INTERCONNECTION

A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance. 15-. (canceled)6. A method of silicon wafer alignment used in through-silicon-via interconnection , the method comprising:providing two or more silicon wafers with a completed through-silicon-via structure;forming interconnected microscale solder joints on a front face and a back face of each of the silicon wafers;stacking and electrically interconnecting the silicon wafers; andaligning and calibrating the stacked and interconnected silicon wafers.7. The method of claim 6 , wherein the through-silicon-via structure comprises a conductive layer and an insulating layer positioned to separate the conductive layer from the through-silicon-via surface.8. The method of claim 7 , wherein the insulating layer is made of silicon dioxide claim 7 , silicon nitride or the insulating substance of their combination.9. The method of claim 7 , wherein the insulating layer is formed of silicon dioxide claim 7 , silicon nitride or a combination thereof.10. The method of claim 7 , wherein the conductive layer comprises aluminum claim 7 , copper or doped polycrystalline silicon.11. The method of claim 6 , wherein the aligning and calibrating the silicon wafers comprises forming a Wheatstone bridge circuit.12. The method of claim 6 , wherein the aligning and calibrating the silicon wafers comprises:positioning an upper silicon wafer and a lower silicon wafer such that the solder joints on the back face of the upper silicon wafer contact the solder joints on the front face of the lower silicon wafer and ...

OPEN OFF-THE-ROAD CORD WITH PREFORMED FILAMENTS

A steel cord () for reinforcing rubber product comprises at least one core strand () and outer strands (), the outer strands () are helically twisted around at least one core strand (). Each of the strands () comprises core steel filaments () with the number of m and outer steel filaments with the number of n. The diameter of the core steel filaments in the core strand is Dcc, the diameter of the outer steel filaments in the core strand is Doc, the diameter of the core steel filament in the outer strand is Dco, and the diameter of the outer steel filament in the outer strand is Doo. The ratio of Dcc/Doc is not less than 1.04, the ratio of Dco/Doo is not less than 1.03, and the ratio of Doc/Dco is not less than 1. The core steel filaments and outer steel filaments are polygonally preformed before being twisted into strands. The steel cord is used for reinforcing off-the-road tire. 1. A steel cord for reinforcing rubber products comprising core strands and outer strands , said outer strands being helically twisted around said core strands ,each of said strands comprising core steel filaments with the number of m and outer steel filaments with the number of n, the carbon content of said steel filaments being not less than 0.7%, said outer steel filaments being helically twisted around said core steel filaments,the diameter of said core steel filament in said core strand being Dec, the diameter of said outer steel filament in said core strand being Doc, the diameter of said core steel filament in said outer strand being Dco, the diameter of said outer steel filament in said outer strand being Doo,characterized in that the ratio of said Dec/Doc is not less than 1.04, the ratio of said Dco/Doo is not less than 1.03, the ratio of said Doc/Dco is not less than 1, said core steel filaments and outer steel filaments are polygonally preformed before being twisted into strands.2. A steel cord for reinforcing rubber product as claimed in claim 1 , characterized in that said ...

INDUCTIVE LOOP FORMED BY THROUGH SILICON VIA INTERCONNECTION

The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips. 1. An inductive loop used to form through silicon via interconnections , comprising:a semiconductor substrate;two or more (more than two) silicon wafers with finished through silicon via structures;interconnection joints formed on the front and back of the silicon wafers;an inductive element formed on the semiconductor substrate, which is used to stack and interconnect the silicon wafers.2. The inductive loop used to form through silicon via interconnections of claim 1 , wherein the semiconductor substrate is made of monocrystalline or polycrystalline silicon or silicon on insulators (SOI).3. The inductive loop used to form through silicon via interconnections of claim 1 , wherein the through silicon via structures of the silicon wafers comprises at least a conductive layer and an insulation layer isolating the conductive layer from the through silicon via surface.4. The inductive loop used to form through silicon via interconnections of claim 3 , wherein the insulation layer is made of silicon dioxide claim 3 , or silicon nitride or the insulation substance of their combination.5. The inductive loop used to form through silicon via interconnections of claim 3 , wherein the conductive layer is made of aluminium claim 3 , or ...

Method for Manufacturing Semiconductor Substrate of Large-power Device

The invention belongs to the technical field of high-voltage, large-power devices and in particular relates to a method for manufacturing a semiconductor substrate of a large-power device. According to the method, the ion implantation is carried out on the front face of a floating zone silicon wafer first, then a high-temperature resistant metal is used as a medium to bond the back-off floating zone silicon wafer, and a heavily CZ-doped silicon wafer forms the semiconductor substrate. After bonding, the floating zone silicon wafer is used to prepare an insulated gate bipolar transistor (IGBT), and the heavily CZ-doped silicon wafer is used as the low-resistance back contact, so the required amount of the floating zone silicon wafers used is reduced, and production cost is lowered. Meanwhile, the back metallization process is not required after bonding, so the processing procedures are simplified, and the production yield is enhanced. 1. A method for manufacturing the semiconductor substrate of the large-power device adopts the processing procedures of bonding the floating zone silicon wafer and a heavily CZ-doped silicon wafer to form the semiconductor substrate , comprising:Step 1: process the required floating zone silicon wafer, which comprises the procedures of:Providing a silicon substrate;Performing hydrogen ion (H+) injection and annealing on the silicon substrate to form a heavily H-doped layer in the silicon wafer;Performing phosphorous or boron ion injection to form a first doping type of the buffer layer between the heavily H-doped layer and the silicon wafer surface;If the first doping type uses phosphorous ions, performing boron ion injection to form a second doping type of a heavily doped region on the silicon wafer surface and on the upper part of the first doping type of the buffer layer, wherein the depth is smaller than that of the first doping type of the buffer layer; if the first doping type uses boron ions, performing the phosphorous ion ...

METHOD FOR MANUFACTURING A FLEXIBLE TRANSPARENT 1T1R STORAGE UNIT BASED ON A COMPLETELY LOW-TEMPERATURE PROCESS

The present invention belongs to the technical field of low temperature atomic layer deposition technology, and specifically relates to a method for manufacturing a flexible transparent 1T1R storage unit. In the present invention, a fully transparent 1T1R storage unit is developed on a flexible substrate through a completely low-temperature process, including an oxide layer dielectric, a transparent electrode and a transparent substrate which are deposited together through a low-temperature process, thus realizing a fully transparent device capable of achieving the functions of nontransparent devices. The present invention can be applied to the manufacturing of flexible low-temperature storage units in the future, as well as changing the packaging and existing modes of devices, which will make foldable and bendable portable storage units possible. 1. A method for manufacturing a flexible transparent 1T1R storage unit , characterized in that it includes the following steps:provide a flexible substrate;form a gate electrode on the flexible substrate;cover the gate electrode to form a gate oxide layer;form a transparent oxide channel on the gate oxide layer;form a source and drain electrodes on both sides of the oxide channel;form an oxide resistive storage layer on the drain electrode;form a top-electrode on the oxide resistive storage layer.2. The method for manufacturing a flexible transparent 1T1R storage unit according to claim 1 , characterized in that the flexible substrate is formed from polyethylene terephthalate claim 1 , polyimide claim 1 , metal or ceramic materials.3. The method for manufacturing a flexible transparent 1T1R storage unit according to claim 1 , characterized in that the gate electrode is formed from indium oxide doped with tin.4. The method for manufacturing a flexible transparent 1T1R storage unit according to claim 1 , characterized in that the gate oxide layer is formed from silicon dioxide claim 1 , silicon nitride and other high ...

METHOD FOR MANUFACTURING A COPPER-DIFFUSION BARRIER LAYER USED IN NANO INTEGRATED CIRCUIT

The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for manufacturing a copper-diffusion barrier layer. In the present invention, a proper reaction precursor has been selected and the atomic layer deposition (ALD) technology has been adopted to develop Co or Ru on a TaN layer to obtain a diffusion barrier layer used in the interconnection for process nodes no more than 32 nm, which overcomes the insufficiency of the PVD deposition Ta/TaN double-layer structure as the copper-diffusion barrier layer in step coverage and conformity, and also effectively solves various serious problems in the Cu/low-k dual damascene process, such as the generation of voids in grooves and through-holes, and electromigration stability. 1. A method for manufacturing a copper-diffusion barrier layer , characterized in that it is comprised of the following steps:form interconnected through-holes on a first metal interconnection layer;form a first metal film;adopt the atomic layer deposition (ALD) technology to form a second metal film;form a copper interconnection structure.wherein, the atomic layer deposition process of the second metal film is:{circle around (1)} put a base plate into an atomic layer deposition reaction chamber, and heat the reaction chamber to the process temperature;{circle around (2)} introduce the metallorganic precursor of the second layer of metal;{circle around (3)} introduce inert gas to bring out the residual metallorganic precursor;{circle around (4)} introduce an oxidant vapor;{circle around (5)} introduce the inert gas once again to bring out the residual oxidant vapor;{circle around (6)} repeat Steps {circle around (2)}-{circle around (5)} until achieving the required film thickness;{circle around (7)} introduce a reducing gas to obtain the required metal film.2. The method for manufacturing a copper-diffusion barrier layer according to claim 1 , wherein the first layer of metal is TaN.3. The ...

Method for improving the electromigration resistance in the copper interconnection process

The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi 3 , CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.

METHOD FOR CLEANING & PASSIVATING GALLIUM ARSENIDE SURFACE AUTOLOGOUS OXIDE AND DEPOSITING AL2O3 DIELECTRIC

The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning & passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an AlOdielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the AlOALD with the GaAs surface, and then deposit high-quality AlOdielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices. 1. A method for cleaning & passivating gallium arsenide (GaAs) surface autologous oxide and depositing AlOdielectric , characterized in that it is comprised of the following steps:(1) after regular chemical cleaning, immediately put the GaAs sample into the prepared sulfur passivation solution which is made of 1-5 g of thioacetamide, 1-4 ml of absolute ethyl alcohol and 1-4 ml of ammonia water, the temperature of passivation reaction is 25□-60□, and the passivation time is 5-30 minutes;(2) after passivation, rinse the GaAs sample for 10-60 seconds with deionized water, then purge the sample for 5-15 seconds with high-purity nitrogen, and then immediately put it into the atomic layer deposition (ALD) reaction chamber.(3) before developing the alumina film dielectric, conduct trimethyl aluminum (TMA) pretreatment of the GaAs sample first, and the pretreatment conditions are: introduce the TMA gas to the ALD reaction chamber for 2-8 minutes, and purge for 10-60 seconds with the nitrogen.{'sub': 2', '3, '(4) develop a ...

NANOWIRE TUNNELING FIELD EFFECT TRANSISTOR WITH VERTICAL STRUCTURE AND A MANUFACTURING METHOD THEREOF

The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly. 1. A nanowire tunneling field effect transistor (TFET) with vertical structure , characterized in that , comprising:a heavily-doped p-type semiconductor substrate;a seed crystal layer formed on the substrate;a nanowire with vertical structure formed on the seed crystal layer;a gate dielectric layer which is located around the nanowire channel formed by covering the seed crystal layer;a heavily-doped polycrystalline silicon gate formed by covering the gate dielectric layer;the top of the nanowire used as the drain of the device, which is extracted as metal electrode by contacting with metal; the heavily-doped semiconductor substrate used as the source.2. The nanowire TFET with vertical structure according to claim 1 , characterized in that the substrate is of silicon claim 1 , silicon on insulator or polyimide.3. The nanowire TFET with vertical structure according to claim 1 , characterized in that the nanowire channel consists of ZnO nanowire.4. A method for manufacturing a nanowire TFET with vertical structure claim 1 , comprising the following steps:provide a heavily-doped p-type semiconductor substrate;develop a ZnO gate seed crystal layer on a ...

Method for Seperating Carbon Nanotubes with Different Conductive Properties

This invention belongs to the technical field of integrated circuit manufacturing and specifically relates to a method for separating carbon nanotube materials with different conductive properties. The method is comprised of: immersing an integrated circuit material containing metallic carbon nanotubes and semiconductor carbon nanotubes into fluid; introducing the fluid into the same container from the same inlet; on the four sides of the container, forming an electric field and arranging a pair of magnetic poles generating magnetic lines vertical to the electric field; changing the direction and intensity of the electric lines of the electric field and those of the magnetic fields to separate the metallic carbon nanotubes from the semiconductor carbon nanotubes. By means of the method of this invention, the purity of the obtained semiconductor carbon nanotubes and the metallic carbon nanotubes is high, so the product yield of the integrated circuit containing the semiconductor carbon nanotubes is capable of being greatly enhanced. This method is simple, easy, low in cost and capable of greatly reducing the manufacturing cost of high-purity carbon nanotubes. 1. A method for separating the carbon nanotube materials with different conductive properties is specifically comprised of the following steps:a) soaking an integrated circuit material in fluid, wherein the integrated circuit material at least comprises a mixture of metallic carbon nanotubes and semiconductor carbon nanotubes; the fluid is non-conductive or high-resistance;b) pouring the fluid into a container;c) setting an electric field and a pair of magnetic poles which form magnetic lines and are vertical to the electric field around the container, wherein both the magnetic lines of the pair of magnetic poles and the electric lines of the electric field penetrate the container;d) changing the directions and lengths of the electric lines of the electric field and those of the magnetic lines, wherein the ...

METHOD FOR MANUFACTURING A TUNNELING FIELD EFFECT TRANSISTOR WITH A U-SHAPED CHANNEL

The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree. 1. A method for manufacturing a tunneling field effect transistor with a U-shaped channel , wherein it comprises the following steps:provide a semiconductor substrate;form a first doping region of a first doping type in the semiconductor substrate;form a first kind of insulation film on the semiconductor substrate;etch the first kind of insulation film and the semiconductor substrate to form a pattern;deposit a second kind of insulation film and etch the second kind of insulation film to form a sidewall;form a third kind of insulation film on the substrate exposed through oxidation;remove the second kind of insulation film;etch the substrate along the sidewalls of the first and second kinds of insulation film to form a groove;cover the groove to form a fourth kind of insulation film;cover the fourth kind of insulation film to form a first kind of conductive film;etch the first kind of conductive film to form a device gate conductive layer;cover the gate conductive layer to form a gate protection layer;etch the fourth and third kinds of insulation film to expose the substrate;etch the substrate exposed to form a region for the subsequent development;form a second doping region of the first doping type in the semiconductor substrate;cover the second doping region of the first doping type to form a ...

METHOD FOR MANUFACTURING VERTICAL-CHANNEL TUNNELING TRANSISTOR

The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost. 1. A method for manufacturing a vertical-channel tunneling transistor , wherein , comprising the following steps:provide a semiconductor substrate;form a first kind of insulation film on the semiconductor substrate;etch the first kind of insulation film to form a pattern;form a doping region of a first doping type in the semiconductor substrate;etch the semiconductor substrate to form a groove;cover the groove and the first kind of insulation film to form a second kind of insulation film;cover the second kind of insulation film to form a first kind of conductive film;etch the first kind of conductive film and the second kind of insulation film to form the device gate structure;cover the gate structure to form a gate protection layer;etch the first kind of insulation film to expose the substrate;etch the substrate exposed to form a region for the subsequent development;develop a layer of narrow band gap material selectively;conduct a second type of doping to the narrow band gap material through ion implantation;etch the gate protection layer to form a gate sidewall;deposit a third kind of insulation film to form a device passivation layer;etch the third kind of insulation film to form a contact hole;deposit a second kind of conductive film;etch the second kind of conductive film to form electrodes.2. The method for manufacturing a tunneling transistor according to claim 1 , wherein the ...

Brightness-adjustable Light-emitting Device and Array and the Manufacturing Methods Thereof

The present invention belongs to the technical field of semiconductor devices and relates to a brightness-adjustable illuminator and an array and the manufacturing methods thereof. The illuminator is comprised of a semiconductor substrate, a MOSFET and a light-emitting diode that are located on the semiconductor substrate. The light-emitting diode (LED) and the control element (MOSFET) thereof are integrated on the same chip, so a single chip is capable of realizing the image transmission. An illuminator array may consist of a plurality of illuminators. Meanwhile, the invention also discloses a method for manufacturing the illuminator. Therefore, the projection equipment manufactured by the technology of the present invention has the advantages of small size, portability, low power consumption, etc. Furthermore, the use of the integrated circuit chip greatly simplifies the system of the projection equipment, reduces the production cost and greatly enhances the pixel quality and brightness. 1. A brightness-adjustable illuminator comprising a semiconductor substrate , a metal-oxide-semiconductor field effect transistor (MOSFET) and a light-emitting diode (LED) formed on the semiconductor substrate , wherein:the LED is comprised of a luminous layer, a p-type region located above the luminous layer and an n-type region located below the luminous layer;the MOSFET is comprised of a silicon substrate, a gate region located on the silicon substrate, and a source region and drain region that are located in the silicon substrate and on the two sides of the gate region;the silicon substrate of the MOSFET is isolated from the LED and the semiconductor substrate by a partition; andthe source region of the MOSFET and the p-type region of the LED are connected by a metal, and the MOSFET controls the LED to emit light from the metal.2. The brightness-adjustable illuminator of claim 1 , wherein claim 1 , the semiconductor substrate is a semiconductor selected from GaN claim 1 , GaP ...

Method for manufacturing a gate-control diode semiconductor device

This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate is of n-type and the device is of a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate, and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The method features capacity of manufacturing gate-control diode devices able to reduce chip power consumption through the advantages of high driving current and small sub-threshold swing. The present invention using a low temperature process production is especially applicable to the manufacturing of semiconductor devices based on flexible substrates and reading & writing devices that have a flat panel display and phase change memory.

METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR DEVICE

This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates. 1. A method for manufacturing a gate-control diode semiconductor device , characterized in that it includes the following steps:provide a heavily-doped n-type silicon substrate;form a first kind of insulation film on the n-type silicon substrate;form a ZnO layer on the first kind of insulation film;etch the ZnO layer to form an active region;form a second kind of insulation film on the ZnO dielectric layer;etch the second kind of insulation film to form a window located at one end of the ZnO active region;coat the second kind of insulation film through spin coating with a layer of spin-coating dielectric of the first doping type which makes contact with the ZnO at the window of the second kind of insulation film;form a doping region (namely a source region) of the first doping type at the window of the second kind of insulation film in the ZnO dielectric layer through the high-temperature diffusion process, wherein the other parts of the ZnO are not doped due to the barrier of the second kind of insulation film;remove the residual spin-coating dielectric of the ...

METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR MEMORY DEVICE

This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. This invention is applicable to semiconductor devices manufacturing based on flexible substrate and flat panel displays and floating gate memories, etc. 1. A method for manufacturing the gate-control diode semiconductor memory device , characterized in that it includes the following steps:provide a heavily-doped n-type silicon substrate;form a first kind of insulation film on the n-type silicon substrate;form a ZnO layer on the first kind of insulation film;etch the ZnO layer to form an active region;cover the active region to form a NiO layer doped with p-type impurity ions;photoetch a pattern, etch the NiO layer and preserve the NiO layer on one side of the ZnO active region to form a device source;deposit a second kind of insulation film on the exposed NiO and ZnO surfaces;deposit device floating gate conductive material on the surface of the second kind of insulation film;define the pattern of the floating gate region thereof though photoetching and etching, wherein the floating gate region located between the NiO material on the ZnO active region and the edge of the other end of the ZnO, is in a square ...

Structure for interconnecting copper with low dielectric constant medium and the integration method thereof

The present invention belongs to the technical field of semiconductor devices, and discloses a structure for interconnecting a medium of low dielectric constant with copper and the integration method thereof. It includes: using a combination of copper interconnections and air gaps to reduce capacity, and a special structure to support copper conductors so as to maintain the shape of copper conductors after removing the medium. The advantage of the present invention is that it can realize the complete air gap structure without short circuit or disconnection of copper conductors as well as the complete air gap structure with long conductors, thus reducing RC delay.

METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR DEVICE

The present invention belongs to the technical field of semiconductor device manufacturing, and specifically relates to a method for manufacturing a gate-control diode semiconductor device. The present invention manufactures gate-control diode semiconductor devices through a low-temperature process, features a simple process, low manufacturing cost, and capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor device proposed by the present invention is especially applicable to the manufacturing of reading & writing devices having flat panel displays and phase change memory, and semiconductor devices based on flexible substrates. 1. A method for manufacturing a gate-control diode semiconductor device , characterized in that it includes the following steps:form a first kind of insulation film on a p-type silicon substrate;etch the first kind of insulation film to form an active region window;deposit a layer of n-type material on the first insulation film and the active region window as an active region which makes contact with the p-type substrate at the active region window;cover the n-type active region to form a second kind of insulation film;etch the first and second kinds of insulation film, form a drain contact window and a source contact window on both sides of the active region window respectively, thus the p-type substrate at the drain contact hole and the n-type active region at the source contact hole are exposed;form a first kind of conductive film through deposition and etch it to form a drain electrode, a gate electrode and a source electrode, wherein the drain electrode is located on and fills the drain contract hole, the source electrode is located on and fills the source contact hole, the gate electrode is between the source electrode and the active region window located between ...

METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR MEMORY DEVICE

The present invention belongs to the technical field of semiconductor device manufacturing, and specifically discloses a method for manufacturing a gate-control diode semiconductor storage device. The present invention manufactures gate-control diode semiconductor memory devices through a low-temperature process featuring a simple process, low manufacturing cost and capacity of manufacturing gate-control diode memory devices with a high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor memory device proposed by the present invention is especially applicable to the manufacturing of flat panel displays and phase change memories and memory devices based on flexible substrate. 1. A method for manufacturing a gate-control diode semiconductor memory device , characterized in that it includes the following steps:form a first kind of insulation film on a p-type silicon substrate;etch the first kind of insulation film to form an active region window;deposit a layer of n-type material on the first insulation film and the active region contact hole as an active region which contacts with the p-type subtract at the active region window;form a second kind of insulation film on the n-type active region;deposit a first kind of conductive material on the second kind of insulation film and etch it to form a device floating gate;cover the floating gate to form a third kind of insulation film;etch the first, second and third kinds of insulation film, form a drain contact window and a source contact window on the two sides of the active region window respectively, thus the p-type subtract at the drain contact hole and the n-type active region at the source contact hole are exposed;form a second kind of conductive film through deposition and etch it to form a drain electrode, a gate electrode and a source electrode, wherein the drain electrode is located on and fills the drain contract hole, the source electrode is located on ...

MULTI-STRAND STEEL CORD WITH WAVED CORE STRAND

A steel cord () adapted for the reinforcement of elastomeric products comprises a core strand () and a layer of outer strands () arranged around the core strand (). The core strand () comprises a core and at least a layer arranged around the core. The core further comprises one to three core filaments and the layer further comprises three to nine layer filaments. The core strand () has a first wave form and each filament of the outer strands () has a second wave form such that the first wave form is substantially different from the second wave form. This allows to guarantee full rubber penetration. 1. A steel cord adapted for the reinforcement of elastomeric products , said steel cord comprising a core strand and a layer of outer strands arranged around said core strand , said core strand comprising a core and at least a layer arranged around said core , said core comprising one to three core filaments , said layer comprising three to nine layer filaments , each of said outer strands comprising outer strand filaments lying at the radially external side of said outer strands , said core strand having a first wave form , each of said outer strand filaments having a second wave form , said first wave form being substantially different from said second wave form.2. A steel cord according to wherein said first wave form has a first amplitude and said second wave form has a second amplitude claim 1 , said first amplitude being substantially different from said second amplitude.315.-. (canceled)16. A steel cord according to wherein said first wave form has a first wave pitch and said second wave form has a second wave pitch claim 1 , said first wave pitch being substantially different from said second wave pitch.17. A steel cord according to wherein said second wave form is spatial.18. A steel cord according to wherein said first wave form is substantially planar.19. A steel cord according to wherein said first wave form is substantially spatial.20. A steel cord according ...

THIN FILM TRANSISTOR MEMORY AND ITS FABRICATING METHOD

The invention relates to a thin film transistor memory and its fabricating method, This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown AlOfilm. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulting layer and the second layer metal nanocrystals grown by ALD method. in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO/HfO/SiOor AlO/HfO/AlOfilm grown. by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method. The TFT memory in this invention has the advantage with large P/E window, good data retention, high P/E speed, stable threshold voltage and simple fabricating process. 1200201. A thin film transistor memory characterized in that the gate electrode of the memory is used as substrate () , and the said memory contains a charge blocking layer () , a charge storage layer , a charge tunneling laver , an active region of the memory and source/drain electrodes in sequence from bottom to up ,{'b': '201', 'sub': 2', '3, 'wherein, the said charge blocking layer () is an AlOfilm grown by the ALD method,'}{'b': 202', '203', '204', '202', '204, 'sub': x', 'x, 'the said charge storage layer has a two layer metal nanocrystals structure, which includes the following components grown by ALD technology in sequence from bottom to up: a first layer metal nanocrystals (), an insulating layer () and a second layer metal nanocrystals (), wherein the first layer metal nanocrystals () and the second layer metal nanocrystals () can be one of the RuOand Pt nanocrystals, and wherein, the mentioned RuOnanocrystals are a kind of ...

CHARGING AND POWER SUPPLYING CIRCUIT, METHOD AND APPLICATION DEVICE

Embodiments of the present invention provide a charging and power supplying circuit, method and application device, which relate to the field of smart charging, so as to improve efficiencies of battery charging and system power supplying. The charging and power supplying circuit includes a power supplying tributary and a charging tributary. An end of the power supplying tributary is connected to a power supply, and another end is connected to a system. An end of the charging tributary is connected to the power supply, and another end is connected to a battery. A first transistor, a second transistor, a third transistor, a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first comparator, a second comparator, a charging controller, a logical switch, an adder and a first control module are connected to the power supplying tributary and the charging tributary. 1. A charging and power supplying circuit , comprising: a power supplying tributary and a charging tributary , wherein an end of the power supplying tributary is connected to a power supply , and another end is connected to a system; an end of the charging tributary is connected to the power supply , and another end is connected to a battery;a first transistor is connected to the power supplying tributary, and a source and a drain of the first transistor are connected to the power supplying tributary, and a gate of the first transistor is connected to a line selection end of a logical switch;a second transistor is connected to the charging tributary, and a source and a drain of the second transistor are connected to the charging tributary, and a gate of the second transistor is connected to an output end of a charging controller;a source and a drain of a third transistor are connected to the battery and the system respectively, and a gate of the third transistor is connected to a first control module;two signal input ends of the logical switch are connected to an output end of a first ...

METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND THE MANUFACTURING METHODS THEREOF

The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor faults a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. 1. A field effect transistor structure integrated with a resistance random access memory (RRAM) , comprising:A semiconductor substrate;A field effect transistor and a RRAM formed on said semiconductor substrate;Characterized in that:A gate dielectric layer of said field effect transistor extends to the surface of a drain region of said field effect transistor;And the part of the gate dielectric layer on the surface of the drain region of the field effect transistor forms a resistance-variable storage layer of said RRAM.2. The field effect transistor structure integrated with a RRAM according to claim 1 , characterized in that said semiconductor substrate is silicon or silicon on an insulator.3. The field effect transistor structure integrated with a RRAM according to claim 1 , characterized in that the gate dielectric layer of said field effect transistor is made of a resistance-variable material with a high dielectric constant.4. A method for ...

TUNNEL TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND A MANUFACTURING METHOD THEREOF

The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. 1. A tunnel transistor structure integrated with a resistance random access memory (RRAM) , comprising:A semiconductor substrate;A tunnel transistor and a RRAM formed on said semiconductor substrate,Characterized in that:A gate dielectric layer of said tunnel transistor extends to the surface of a drain region of said tunnel transistor;And the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms a resistance-variable storage layer of said RRAM.2. The tunnel transistor structure integrated with a RRAM according to claim 1 , characterized in that said semiconductor substrate is silicon or silicon on an insulator.3. The tunnel transistor structure integrated with a RRAM according to claim 1 , characterized in that ...

Semiconductor memory structure and control method thereof

The present invention belongs to the technical field of non-volatile semiconductor memories, and relates to a semiconductor memory structure and a control method thereof. The semiconductor memory structure in the present invention comprises a memory unit for storing information and a tunneling field-effect transistor connected with the memory unit. The tunneling field-effect transistor is used for controlling the semiconductor memory's operations such as erasing, writing, and reading. A plurality of semiconductor memory structures compose a semiconductor memory array. The control method provided by the present invention comprises steps of resetting, setting, and reading. A vertical gate-controlled diode structure in a tunneling field-effect transistor is capable of providing a large current for writing a resistive random access memory and a phase change memory and improving the density of the memory array and therefore is very suitable for use in manufacturing of semiconductor memory chips; besides, the control method and the control circuit thereof are simple.

Semiconductor memory structure and its manufacturing method thereof

The present invention belongs to the technical field of microelectronic devices, specifically relates to a semiconductor memory structure and its manufacturing method thereof. The semiconductor memory structure which carries out erasing, writing and reading operation on the phase change memory or the resistance change memory through a tunneling field-effect transistor is formed, for one hand, the high current passed through the tunneling field-effect transistor when the p-n junction the biased positively, meeting the high current requirements for erasing of and writing of the phase change memory and the resistance change memory, and on the other hand, Vertical structure of the field-effect transistor can greatly improve the density of memory devices arrays. The present invention also discloses a method, which is very suitable for the memory chips, for the manufacturing of the semiconductor memory structure using self-aligned process.

COMPOUND DIELECTRIC ANTI-COPPER-DIFFUSION BARRIER LAYER FOR COPPER CONNECTION AND MANUFACTURING METHOD THEREOF

The disclosure belongs to the field of manufacturing and interconnection of integrated circuits, and in particular relates to compound dielectric anti-copper-diffusion barrier layer for copper interconnection and a manufacturing method thereof The disclosure uses compound dielectric (oxide & metal) as the anti-copper-diffusion barrier layer. First, it can enhance the capable of metal for anti-copper-diffusion efficiently, and prevent the barrier layer for valid owing to oxidized and prolong the life of the barrier layer. Second, it can reduce the effective dielectric constant of the interconnection circuits and furthermore reduce the RC delay of the whole interconnection circuits. Besides, the alloy is firmly adhered to the copper, and the metal copper can be directly electroplated without growing a layer of seed crystal copper. The method is simple and feasible and is expected to be applied to manufacturing of the anti-copper-diffusion barrier layers for copper interconnections. 1. A compound dielectric anti-copper-diffusion barrier layer for copper connections , which comprises a low dielectric constant dielectric layer formed on a semiconductor substrate , interconnection through-hole formed in the low dielectric constant dielectric layer , which characterized in that ,a oxide layer covering the side walls of said interconnection through-hole and formed on the top of said low dielectric constant dielectric layer,a metal layer covering the said oxide layer and the bottom wall of said interconnection through-hole,and, the oxide & metal compound dielectric anti-copper-diffusion barrier layer are constituted by the said oxide layer and said metal layer.2. The compound dielectric anti-copper-diffusion barrier layer for copper connections according to which characterized in that claim 1 ,said oxide layer is silicon carbonitride, silicon nitride, metal oxides or metal oxynitride.3. The compound dielectric anti-copper-diffusion barrier layer for copper connections ...

STEEL CORD COMPRISING FLAT WIRES

A steel cord () comprises a plurality of steel filaments () arranged in parallel to the longitudinal axis of the steel cord () without twisting. The steel cord () further comprises a wrapping filament () twisted around the steel cord (). Each of said steel filaments () is a flat wire having flat surfaces. The steel filament () near the center of the steel cord () has a bigger width than the steel filaments () further away from the center of the steel cord () such that the cross-section of said steel cord () approximates an oval shape with the bending stiffness around the shorter axis of the oval shape being greater than the bending stiffness around the longer axis. In a tire, the steel cord being used as a reinforcement, the longer axis being arranged perpendicular to the radial direction of the tire. 112-. (canceled)13. A steel cord comprising a plurality of steel filament arranged in parallel without twisting , said steel cord further comprising a wrapping filament twisted around said filaments , said plurality of steel filaments being flat wires having flat surfaces , said plurality of steel filaments being in contact with each other along said flat surfaces , characterized in that the cross-section of said steel cord is substantially round , the lateral bending stiffness (in a horizontal plane) is greater than the radial bending stiffness (in a vertical plane).14. A steel cord as claimed in claim 13 , characterized in that the ratio of said lateral bending stiffness to said radial bending stiffness to said radial bending stiffness is not less than 1.8.15. A steel cord as claimed in claim 14 , characterized in that the ratio of said lateral bending stiffness to said radial bending stiffness to said radial bending stiffness is not less than 2.0.16. A steel cord as claimed in claim 13 , characterized in that said steel filaments have different cross-sectional area.17. A steel cord as claimed in claim 16 , characterized in that said steel filament near the centre of ...

BATTERY MODULE

A battery module includes a cell assembly, where a cell in the cell assembly includes a cell body and a tab; and the battery module further includes: a first fastening band, configured to enclose the cell assembly in a thickness direction of the cell; and a second fastening band, configured to enclose the cell assembly in the thickness direction of the cell, where in a length direction of the cell, a distance between a projection location of the first fastening band and a first end of the cell body is less than or equal to L/4, a distance between a projection location of the second fastening band and a second end of the cell body is less than or equal to L/4, and L is length of the cell body. 1. A battery module , comprising:a cell assembly and a plurality of fastening bands;wherein a cell in the cell assembly comprises a cell body and a tab; andthe plurality of fastening bands comprises a first fastening band configured to enclose the cell assembly in a thickness direction of the cell and a second fastening band configured to enclose the cell assembly in the thickness direction of the cell;wherein, in a length direction of the cell, a distance between a projection location of the first fastening band and a first end of the cell body is less than or equal to L/4, a distance between a projection location of the second fastening band and a second end of the cell body is less than or equal to L/4, and L is length of the cell body.2. The battery module according to claim 1 , wherein the distance between the projection location of the first fastening band and the first end of the cell body is greater than or equal to 2 L/25.3. The battery module according to claim 1 , wherein the distance between the projection location of the second fastening band and the second end of the cell body is greater than or equal to 2 L/25.4. The battery module according to claim 3 , further comprising a housing claim 3 , wherein the housing comprises a casing claim 3 , the casing is provided ...

A RADIO FREQUENCY POWER DEVICE FOR IMPLEMENTING ASYMMETRIC SELF-ALIGNMENT OF THE SOURCE, DRAIN AND GATE AND THE PRODUCTION METHOD THEREOF

The present disclosure relates to the technical field of radio frequency power devices, and more specifically, to a radio frequency power device for implementing the self-position alignment of asymmetric source, drain and gate and the production method thereof. In the radio frequency power device for implementing asymmetric self-alignment of the source, drain and gate according to the present disclosure, gate sidewalls are utilized to implement the self-position alignment of the source, drain and gate, thereby reducing parameter drift of products; besides, the source and drain of the device can be formed by the alloying process, the iron implanting process or epitaxy process after formation of the gate since the gate is protected by the passivating layer, featuring a simple technological process while reducing the parasitic source-drain resistances and enhancing the electrical properties of the radio is frequency power device. 1. A radio frequency power device for implementing asymmetric self-alignment of the source , drain and gate , comprising:an AlGaN buffer layer, a GaN channel layer and an AlGaN isolating layer formed in turn on the substrate;a gate dielectric layer formed on the AlGaN isolating layer;wherein, said device also comprises:a gate stack region formed on the gate dielectric layer, including a gate and a passivating layer on the gate;a first gate sidewall formed on either side of the gate stack region;a drain and a source formed respectively on the outer side of the first gate sidewalls on both sides of the gate stack region;a second gate sidewall formed between the first gate sidewall close to one side of the drain and the drain.2. The radio frequency power device for implementing asymmetric self-alignment of the source claim 1 , drain and gate as claimed in claim 1 , wherein a field plate is formed on the first gate sidewall close to the drain claim 1 , wherein the field plate is connected with the source and extends over the second gate sidewall ...

PHASED ARRAY LIDAR TRANSMITTING CHIP OF MIXED MATERIALS, MANUFACTURING METHOD THEREOF, AND LIDAR DEVICE

The present disclosure provides a phased array LiDAR transmitting chip of mixed materials, a manufacturing method thereof, and a LiDAR device. The phased array LiDAR transmitting chip of mixed materials includes: a first material structure layer and an SOI silicon waveguide structure layer, the first material structure layer is optically connected to the SOI silicon waveguide structure layer through a coupling connection structure; the first material structure layer is configured to couple input light into the chip; the coupling connection structure is configured to split a light wave coupled to the chip, and couple each of split light waves into a corresponding silicon waveguide in the SOI silicon waveguide structure layer; where a non-linear refractive index of the first material in the first material structure layer is lower than a non-linear refractive index of silicon material. 1. A phased array light detection and ranging (LiDAR) transmitting chip of mixed materials , comprising: a first material structure layer and an SOI silicon waveguide structure layer , wherein an overlapping region of a rear end of the first material structure layer and a front end of the SOI silicon waveguide structure layer forms a coupling connection structure;the first material structure layer is optically connected to the SOI silicon waveguide structure layer through the coupling connection structure;the first material structure layer is configured to couple input light to the chip;the coupling connection structure is configured to split a light wave coupled into the chip, and couple each of split light waves into a corresponding silicon waveguide in the SOI silicon waveguide structure layer; anda non-linear refractive index of a first material in the first material structure layer is lower than a non-linear refractive index of a silicon material.2. The phased array LiDAR transmitting chip of mixed materials according to claim 1 , wherein the SOI silicon waveguide structure layer ...

NATURAL SAPONIN-BASED SYNTHETIC IMMUNOADJUVANTS

The present disclosure encompasses QS-21-based structurally-defined adjuvants to address the need for stronger, safer, and easier-to-access adjuvants. The new compositions can provide tools for addressing long-standing mechanistic questions concerning saponin immune-potentiation through structure-activity-relationship (SAR) studies. Most advantageously, the compounds of the disclosure may be formulated into pharmaceutically acceptable compositions, including vaccines that may be delivered to a subject human or animal subject. The compounds can then act as, for example, an adjuvant to augment an immunological response to a vaccine immunogen. 2. The QS-21 derivative according to claim 1 , wherein Ris H claim 1 , apiose or xylose.3. The QS-21 derivative according to claim 1 , wherein Ris H or glucose.7. A pharmaceutically acceptable composition comprising at least one of the compounds according to .8. The pharmaceutically composition according to claim 7 , wherein the composition is formulated as a vaccine. This application claims priority to U.S. Provisional Patent Application Ser. No. 61/614,744 entitled “NATURAL SAPONIN-BASED SYNTHETIC IMMUNOADJUVANTS” and filed Mar. 23 2012, the entirety of which is hereby incorporated by reference.This invention was made with government support under NIH Grant No. R03AI099407 awarded by the U.S. National Institutes of Health of the United States government. The government has certain rights in the invention.The present disclosure is generally related to novel synthetic saponin-based immunoadjuvants.Vaccination is one of the most successful medical practices since its invention 200 years ago, and has been successful in eradicating many severe infectious diseases (Plotkin S A (2005) 11, S5-S11; Mortellaro & Ricciardi-Castagnoli (2011) 89, 332-339). However, the current state of vaccine development is not adequate to meet some emerging, re-emerging or persistent challenges. Infectious diseases are still responsible for one-fifth of ...

CURRENT-LIMITING CIRCUIT AND APPARATUS

Embodiments of the present invention relate to the field of electronic technologies, and provide a current-limiting circuit and apparatus to reduce costs of the current-limiting circuit and an occupied PCB board area. The circuit comprises a detecting resistor, a current-limiting resistor, a precise current unit, a power metal oxide MOS transistor, an operational amplifier OP and an input voltage end. 1. A current-limiting circuit , comprising a detecting resistor , a current-limiting resistor , a precise current unit , a power metal oxide semiconductor MOS transistor , an operational amplifier OP and an input voltage end , wherein the OP comprises a non-inverting input end , an inverting input end and an output end;the input voltage end is configured to receive an input voltage;one end of the detecting resistor is connected to the input voltage end, and the other end of the detecting resistor is connected to the non-inverting input end of the OP, and the detecting resistor is provided with at least one resistance value, and a resistance value of the detecting resistor may be adjusted to one resistance value among the at least one resistance value;one end of the current-limiting resistor is connected to the input voltage end, and the other end of the current-limiting resistor is connected to the inverting input end of the OP;the precise current unit is connected to the other end of the detecting resistor and is configured to adjust a proportional error between the current-limiting resistor and the detecting resistor by outputting a precise reference current; andthe power MOS transistor comprises a gate electrode, a source electrode and a drain electrode, wherein the gate electrode is connected to the output end of the OP, the source electrode is connected to the other end of the current-limiting resistor, and the drain electrode outputs a current-limiting current corresponding to one resistance value.2. The circuit according to claim 1 , wherein the detecting ...

METHOD FOR RECOGNIZING MULTIPLE CAPACITIVE STYLUSES, TOUCH CONTROL UNIT, TOUCH PANEL AND SYSTEM

The present invention discloses a method for recognizing multiple active capacitive styluses, a touch control unit, a touch panel, and a touch system. The method includes the steps of: obtaining recognization signals sent by multiple active capacitive styluses, and recognizing coordinates of each active capacitive stylus and its report point removing ghost point coordinates from the report point coordinates in a mutual capacity mode of a work cycle of a touch panel, to obtain actual coordinates of each active capacitive stylus. The present invention accurately recognizes the specific positions of the multiple active capacitive styluses by eliminating the coordinates of the ghost points and has the advantages of high positioning accuracy and strong user experience. 1. A method for recognizing multiple active capacitive styluses , wherein the method comprises the steps of:obtaining recognization signals sent by multiple active capacitive styluses, and recognizing coordinates of each active capacitive stylus and its report point;removing ghost point coordinates from the report point coordinates in a mutual capacity mode of a work cycle of a touch panel, to obtain actual coordinates of each active capacitive stylus.2. The method for recognizing multiple active capacitive styluses of claim 1 , wherein the recognization signals sent by the multiple active capacitive styluses are obtained by controlling a transmit electrode or a receive electrode of the touch panel.3. The method for recognizing multiple active capacitive styluses of claim 1 , wherein before the step of removing the ghost point coordinates from the report point coordinates in the mutual capacity mode of the work cycle of the touch panel claim 1 , to obtain the actual coordinates of each active capacitive stylus claim 1 , the method further comprises:enabling the mutual capacity mode of the touch panel.4. The method for recognizing multiple active capacitive styluses of claim 1 , wherein after the step of ...

IMAGE SENSOR FOR REAL TIME CALIBRATION OF DARK CURRENT AND CALIBARATION METHOD

The present invention discloses an image sensor for real-time calibration of dark current, including a pixel array comprises at least a pixel unit, the pixel unit includes a pixel photosensitive portion, a pixel dark shielding portion and a subtraction circuit, photodiodes in the pixel photosensitive portion and the pixel dark shielding portion are isolated by deep trench isolations, the pixel dark shielding portion are covered by a dark shielding layer; both of the pixel photosensitive portion and the pixel dark shielding portion adopt a same voltage and sequential control, a light ambient voltage signal and a non-light ambient voltage signal are generated and connected to both ends of a subtraction circuit to realize subtraction and dark current calibration. The present invention discloses an image sensor for real-time calibration of dark current, which can make the dark current calibration completed directly within the pixel, and can better cover the dark pixel part, so as to make calibration value of dark current and dark noise more accurate. 1. An image sensor for real-time calibration of dark current , comprising a pixel array composed of at least one pixel unit , wherein: the pixel unit comprises a pixel photosensitive portion , a pixel dark shielding portion and a subtraction circuit , each of the pixel photosensitive portion and the pixel dark shielding portion includes a photodiode , a transfer transistor , a floating diffusion (FD) node , a reset transistor and a source follower transistor , the photodiodes in the photosensitive part and the pixel dark shielding portion are isolated by a deep trench isolation , the surface of the pixel dark shielding portion is covered with a dark shielding layer for shielding external incident light; both of the pixel photosensitive portion and the pixel dark shielding portion are controlled by a same voltage and sequential control , a light ambient voltage signal and a non-light ambient voltage signal are generated and ...

A METHOD OF WATER FLOW EROSION FOR MARINE GAS HYDRATE EXPLOITATION

The present invention provides a method of water flow erosion for marine gas hydrate exploitation. Based on the characteristics of higher permeability around gas hydrate exploitation well, controlling the seawater flow process by the pressure difference between hydrate reservoir and gas hydrate exploitation well. And the chemical potential difference between hydrate phase and water phase is the main driving factor for promoting the hydrate decomposition. Meanwhile, the salinity will increase and then the phase equilibrium temperature of hydrate will increase during seawater flow process. The water flow erosion accelerates the heat and mass transfer in hydrate reservoir to promote the efficient and complete decomposition and collection of hydrate. And the method of water flow erosion can decrease the risk of the geographical destruction caused by the large pressure drop. The present invention also provides the combination modes of water flow erosion with depressurization, thermal injection and other methods. 1. A method of water flow erosion for marine gas hydrate exploitation , wherein it comprises the following steps:(1) drilling location selection: drilling multiple gas hydrate exploitation channels, there will be two pressure control channels and one gas collection channel for one set of gas hydrate exploitation channel; drilling multiple water storage channels between adjacent exploitation channels in gas hydrate reservoir to interlink the pressure control channel with gas collection channel, which is used to storage seawater;(2) for each gas hydrate exploitation channels, a middle channel is chose to be the gas collection channel, which is used to control the pressure of gas hydrate reservoir and the difference pressure between different gas hydrate exploitation channels; the seawater flowing process is controlled by the difference pressure between different gas hydrate exploitation channels, and the hydrate decomposition is induced by chemical potential ...

NEAR-INFRARED-VISIBLE LIGHT ADJUSTABLE IMAGE SENSOR

The disclosure belongs to the field of semiconductor photoreceptors, in particular to a near-infrared-visible light adjustable image sensor. By adding a transfer transistor, the disclosure integrates a silicon-based photoelectric diode and a silicon germanium-based photoelectric diode on the same chip to realize that the silicon-based photoelectric diode and a silicon germanium-based photoelectric diode are controlled by the same readout circuit at different time, thus widening the spectrum response scope of the photoreceptor, realizing high integration and multifunction of the chip and reducing the manufacturing cost of the chip. The disclosure is applicable for intermediate and high-end products with low power consumption and photoreceptors for specific wave bands, in particular to military, communicative and other special fields. 1. A near-infrared-visible light adjustable image sensor , comprising:a p-type doped silicon substrate;a silicon-based photoelectric diode formed on side silicon substrate;a silicon germanium-based photoelectric diode formed on side silicon substrate;a first transistor and a second transistor formed in said silicon substrate and between said silicon-based photoelectric diode and said silicon germanium-based photoelectric diode;and a conductive floating node formed on said silicon substrate and between said first and second transistors and serving as a charge storage node.2. The near-infrared-visible light adjustable image sensor according to claim 1 , characterized in that the source region of said first transistor is connected with the n-type doped region of said silicon-based photoelectric diode.3. The near-infrared-visible light adjustable image sensor according to claim 1 , characterized in that the source region of said second transistor is connected with the n-type doped region of said silicon germanium-based photoelectric diode.4. The near-infrared-visible light adjustable image sensor according to claim 1 , characterized in that ...

SEMICONDUCTOR PHOTOSENSITIVE UNIT AND SEMICONDUCTOR PHOTOSENSITIVE UNIT ARRAY THEREOF

The present invention relates to a semiconductor photosensitive unit and a semiconductor photosensitive unit array thereof, including a floating gate transistor, a gating MOS transistor and a photodiode that are disposed on a semiconductor substrate. An anode or a cathode of the photodiode is connected to a floating gate of the floating gate transistor through the gating MOS transistor, and the corresponding cathode or anode of the photodiode is connected to a drain of the floating gate transistor or connected to an external electrode. After the gating MOS transistor is switched on, the floating gate is charged or discharged through the photodiode; and after the gating MOS transistor is switched off, charges are stored in the floating gate of the floating gate transistor. Advantages like a small unit area, low surface noise, long charge storage time of the floating gate, and large dynamic range of an operating voltage are achieved. 1. A semiconductor photosensitive unit , comprising , in a semiconductor substrate of a first conductivity type , a photodiode provided with a first end of the first conductivity type and a second end of a second conductivity type; and a floating gate transistor provided with a first source and a first drain of the second conductivity type , a floating gate of the first conductivity type that controls the switch-on or switch-off of a first current channel region between the first source and the first drain , and a first control gate having a capacitive coupling effect on the floating gate , wherein a gating MOS transistor is disposed between the photodiode and the floating gate transistor , the gating MOS transistor is provided with a second source and a second drain of the first conductivity type and a second control gate for controlling the switch-on or switch-off of a second current channel region between the second source and the second drain , the second drain of the gating MOS transistor is connected to the first end of the ...

INGENOL COMPOUNDS AND USE THEREOF IN ANTI-HIV LATENCY TREATMENT

Provided in the present invention are ingenol compounds and a use thereof in preparing an anti-HIV latency drug. In particular, provided in the present invention is a use of ingenol compounds and pharmaceutically acceptable salts thereof for preparing a drug for: (a) intervening with HIV viral latency; (b) activating an HIV virus that has been integrated into mammalian genomes; and/or (c) inducing the expression of the dormant HIV provirus in infected cells. The compounds of the present invention may also be used in combination with antiretroviral drugs to accelerate the removal of latent viral reservoirs. 1. (canceled)69.-. (canceled)11. The method of claim 5 , wherein the method further comprises the step of activating a latent HIV virus.12. The method of claim 5 , wherein the method further comprises the step of inhibiting and/or killing a latent HIV virus. The present invention relates to the field of the medicine, in particular, to ingenol compounds and use thereof in anti-HIV latency treatment.Acquired immunodeficiency syndrome (AIDS) is a contagious disease that seriously endangers people's life and health caused by HIV infection. According to WHO statistics, there are more than 40 million AIDS patients worldwide, with 5 million new patients each year, while about 3 million deaths each year. At present, the main clinical treatment of AIDS is Highly active antiretroviral therapy (HAART), which not only effectively controls HIV replication, but also rebuilds the immune function of AIDS patients, thereby opening the door of hope for the treatment of AIDS. People have hoped that HAART can completely eliminate HIV in vivo, thereby achieving the goal of completely curing AIDS. However, subsequent practice has shown that although HAART can inhibit viral replication in patients at the largest extent, and reduce plasma viral load to levels not detected by conventional detection methods, there are still viruses in the infected body. Once drug treatment is stopped, the ...

SELF-ALIGNED VERTICAL NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, Including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFETs) sharing one gate and one drain, the drain region current of each of the TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process. The memory chip using the present invention is of low manufacturing cost and high storage density. 1. A self-aligned vertical nonvolatile semiconductor memory device , characterized in that , including:{'b': '107', 'a semiconductor substrate ();'}{'b': '108', 'a drain region of a first doping type ();'}{'b': 101', '101', '106, 'i': a', 'b, 'two source regions of a second doping type (, ); a channel region () between the two source regions;'}{'b': 104', '103', '102', '105, 'a stacked gate used to capture electrons, of which the structure includes a first dielectric (), a second dielectric (), a third dielectric () and a metal gate () in turn;'}wherein, the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFET) sharing one gate and one drain; in addition, the drain region current of each TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons; the drain region is buried in the semiconductor substrate, ...

STEEL CORD FOR EXTRUSION PROCESS, AN APPARATUS AND METHOD AND USE OF SAID STEEL CORD

A steel cord () for an extrusion process, where a steel wire () is connected to the leading end of the steel cord (). The steel wire () is easy to insert through an extruder head () and leads the steel cord () through the extruder head (), to facilitate the change-over of steel cord () on an extruder () to reduce the change-over time. Also an apparatus (), a change-over process, and the use of the steel cord () for an extrusion process is disclosed. 113.-. (canceled)14. A steel cord , characterized in that a steel wire is connected to the leading end of said steel cord.15. A steel cord according to claim 14 , wherein the steel wire is welded to the leading end of said steel cord.16. A steel cord according to claim 14 , wherein the diameter of the steel wire is not greater than the diameter of the steel cord.17. A steel cord according to claim 16 , wherein the diameter of the steel wire is between 60% to 100% of the diameter of the steel cord.18. A steel cord according to claim 17 , wherein the diameter of the steel wire is between 90% to 98% of the diameter of the steel cord.19. A steel cord according to claim 14 , wherein the surface of the steel wire is harder than zinc.20. A steel cord according to claim 19 , wherein the steel wire is a stainless steel wire.21. A steel cord according to claim 19 , wherein the steel wire is coated with a coating harder than zinc.22. A steel cord according to claim 21 , wherein the coating is a copper coating claim 21 , a brass-coating claim 21 , a nickel coating claim 21 , or a chromium coating.23. A steel cord according to claim 14 , wherein the leading end of the steel wire is chamfered or rounded.24. Use of a steel cord according to for extrusion process.25. An assembly of a steel cord according to and an extruder claim 14 , said extruder having an extruder head claim 14 , wherein the length of the steel wire is greater than the length of extruder head.26. A process of change steel cord on an extruder claim 14 , characterized ...

BATTERY PRESENCE DETECTING METHOD, APPARATUS AND CHARGING SYSTEM

Embodiments of the present invention provide a battery presence detecting apparatus, including: a detection triggering module, configured to detect a charging current on a battery terminal and trigger a logic control module when the charging current is less than a preset current threshold; the logic control module, configured to turn off a battery charging system and instruct a charging and discharging balancing module to perform a charging operation and then a discharging operation on the battery terminal; and a detection determining module, configured to detect a voltage on the battery terminal when the discharging operation is performed and determine whether the voltage on the battery terminal is less than a preset detection voltage, and if the voltage on the battery terminal is less than the preset detection voltage, determine that the battery is absent, and otherwise, determine that the battery is present. 1. A battery presence detecting apparatus , applied in a battery charging system , the apparatus comprising a detection triggering module , a logic control module , a charging and discharging balancing module , and a detection determining module , wherein:the detection triggering module is connected to a battery terminal in the battery charging system, is configured to detect a charging current on the battery terminal, and send a triggering signal to the logic control module when the charging current is less than a preset current threshold;the logic control module is configured to send a charging closing instruction to the battery charging system and send a first operation instruction to the charging and discharging balancing module after the triggering signal is received;the charging and discharging balancing module is configured to perform a charging operation and then a discharging operation on the battery terminal according to the first operation instruction, and send a first detection instruction to the detection determining module when the discharging ...

REGENERABLE HYDROGEN SULFIDE ADSORBENT AND PREPARATION METHOD THEREOF AND APPLICATION THEREOF

The present invention relates to a regenerable hydrogen sulfide adsorbent and a preparation method thereof. The preparation method specifically includes: 1) combining meta-aluminate as an active component with activated alumina as a carrier in a manner of impregnation, spray coating or solid phase mixing to obtain a precursor; 2) aging and drying the precursor, and finally performing roasting to obtain the adsorbent; and 3) processing the adsorbent to present a specific size and shape through shaping measures to meet industrial application requirements. Compared with the prior art, the adsorbent obtained according to the present invention can achieve an efficient removal effect on hydrogen sulfide gas at a material inlet, with a concentration adaption range of 0 to 1000 ppm and an effective removal precision of 0.1 ppm or below. 1. A regenerable hydrogen sulfide adsorbent , consisting of two parts: an active component and a carrier , wherein the active component is meta-aluminate , and the carrier is activated alumina.2. The regenerable hydrogen sulfide adsorbent according to claim 1 , wherein a weight ratio of the meta-aluminate is 0.5 to 40% claim 1 , and a weight ratio of the activated alumina is 60 to 99.5%.3. The regenerable hydrogen sulfide adsorbent according to claim 1 , wherein the activated alumina is chi-phase alumina claim 1 , rho-phase alumina claim 1 , eta-phase alumina claim 1 , gama-phase alumina or a mixed phase thereof.4. The regenerable hydrogen sulfide adsorbent according to claim 1 , wherein the meta-aluminate is a metal salt compound of a “AlO” atomic group and a metal element M and/or hydrogen element claim 1 , and the metal element M is selected from one or a combination of more of alkali metal and/or alkaline earth metal elements.5. The regenerable hydrogen sulfide adsorbent according to claim 4 , wherein the metal element M is one or a mixture of Na and K.6. The regenerable hydrogen sulfide adsorbent according to claim 4 , wherein in the ...

Power Conversion Circuit and Related Apparatus and Terminal Device

A power conversion circuit includes a first switch branch, a second switch branch, a third switch branch, a filter branch, and a first capacitor. A first terminal of the first capacitor is connected to a power source through the first switch branch, and a second terminal of the first capacitor is grounded through the second switch branch. The filter branch includes a filter inductor and a filter capacitor. A first terminal of the filter inductor is connected to the first terminal of the first capacitor, and a second terminal of the filter inductor is connected to a first terminal of the filter capacitor. A second terminal of the filter capacitor is grounded, and the filter capacitor is connected in parallel with the load. The third switch branch is connected between the second terminal of the first capacitor and the second terminal of the filter inductor. 1. A power conversion circuit , comprising:a first switch branch comprising a first switch;a second switch branch comprising a second switch, wherein the second switch branch is coupled to the first switch branch;a third switch branch comprising a third switch, wherein the third switch branch is coupled to the first switch branch and the second switch branch; a filter inductor comprising a first terminal and a second terminal; and', 'a filter capacitor comprising a third terminal and a fourth terminal;, 'a filter branch comprising a fifth terminal coupled to a power source through the first switch branch; and', 'a sixth terminal coupled to ground through the second switch branch, wherein the filter inductor is coupled in series to the filter capacitor, wherein the first terminal is coupled to the fifth terminal, wherein the second terminal is coupled to the third terminal, wherein the fourth terminal is grounded, and wherein the, 'a first capacitor comprisingthird switch branch is coupled between the second terminal and the second terminal; anda load coupled to filter branch, wherein the filter capacitor is coupled ...

PHASED ARRAY LIDAR TRANSMITTING CHIP OF MULTI-LAYER MATERIALS, MANUFACTURING METHOD THEREOF, AND LIDAR DEVICE

A phased array LiDAR transmitting chip of multi-layer materials includes: a first material structure layer and an SOI silicon waveguide structure layer, a rear end of the first material structure layer and a front end of the SOI silicon waveguide structure layer form a coupling connection structure. The first material structure layer includes an input coupler and a beam splitter. The input coupler is optically connected to the beam splitter. The beam splitter is optically connected to the SOI silicon waveguide structure layer through the coupling connection structure. The input coupler couples input light to the chip. The beam splitter split a light wave coupled to the chip. The coupling connection structure couples each split light wave to a silicon waveguide in the SOI silicon waveguide structure layer. A non-linear refractive index of a first material in the first material structure layer is lower than that of a silicon material. 1. A phased array light detection and ranging (LiDAR) transmitting chip of multi-layer materials , comprising: a first material structure layer and an SOI silicon waveguide structure layer , wherein an overlapping region of a rear end of the first material structure layer and a front end of the SOI silicon waveguide structure layer forms a coupling connection structure , and the first material structure layer comprises: an input coupler and a beam splitter;the input coupler is optically connected to the beam splitter; and the beam splitter is optically connected to the SOI silicon waveguide structure layer through the coupling connection structure;the input coupler is configured to couple input light to the chip;the beam splitter is configured to split a light wave coupled to the chip;the coupling connection structure is configured to couple each of split light waves to a corresponding silicon waveguide in the SOI silicon waveguide structure layer; anda non-linear refractive index of a first material in the first material structure layer ...

Power Conversion Circuit, and Charging Apparatus and System

A power conversion circuit includes a first end of a first switch element coupled to an input power supply; a second end of the first switch element coupled to a first end of a first energy storage element, and a first end of a second switch element; a second end of the first energy storage element coupled to ground through a third switch element, and a first end of a fourth switch element; a second end of the second switch element coupled and connected to a battery; a first end of a second energy storage element coupled to two ends of the first energy storage element through a fifth switch element and a sixth switch element; a second end of the second energy storage element coupled to the battery; and a second end of the fourth switch element coupled to the battery. 1. A power conversion circuit , comprising:a first switch element comprising a first end and a second end, wherein the first end is a first external connection end of the power conversion circuit, and wherein the first end is configured to couple to an input power supply;a second switch element comprising a third end and a fourth end, wherein the third end is coupled to the second end, wherein the fourth end is a second external connection end of the power conversion circuit, and wherein the fourth end is configured to couple to a battery;a third switch element comprising a fifth end and a sixth end, wherein the sixth end is coupled to ground;a fourth switch element comprising a seventh end and an eighth end, wherein the eighth end is coupled to the second external connection end;a fifth switch element comprising a ninth end and a tenth end;a sixth switch element comprising a eleventh end and a twelfth end, wherein the twelfth end is coupled to the tenth end;a first energy storage element comprising a thirteenth end and a fourteenth end, wherein the fourteenth end is coupled to the fifth end, the seventh end, and the eleventh end; anda second energy storage element comprising a fifteenth end and a ...

PICTURE LOADING APPARATUS AND METHOD

The invention discloses a picture loading apparatus comprising: a first judgment module configured to judge whether it is needed to request a server for downloading a picture; a request module configured to request the server for downloading a picture when the first judgment module determines that it is needed to request the server for downloading a picture; and a loading module configured to receive a picture downloaded from the server and load it to a browser. In addition, the invention further provides a picture loading method. By utilizing the picture loading apparatus and method of the invention, it can request downloading and loading a picture when it is judged that a user needs to view the picture, without the need for downloading all the pictures on a webpage, thereby reducing the interaction with the server and reducing the occupancy of CPU resources. Further, when a picture being downloaded or loaded is being scrolled away from a current display interface, the downloading or loading of the picture may be cancelled, thereby further reducing the interaction with the server and the occupancy of the CPU resources. 1. A picture loading apparatus comprising:a memory having instructions stored thereon;a processor configured to execute the instructions to perform following operations:judging whether it is needed to request a server for downloading a picture;requesting the server for downloading a picture when it is needed to request the server for downloading a picture; andreceiving a picture downloaded from the server and loading it to a browser.2. The apparatus as claimed in claim 1 , whereinthe step of judging whether it is needed to request the server for downloading a picture comprises: judging whether to request the server for downloading a picture according to the dwell time of the picture on the current display interface of the browser.3. The apparatus as claimed in claim 2 , whereinthe step of judging whether to request the server for downloading a ...

PHOTO DETECTOR CONSISTING OF TUNNELING FIELD-EFFECT TRANSISTORS AND THE MANUFACTURING METHOD THEREOF

The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors. 18-. (canceled)9. The method for manufacturing a photo detector consisting of a tunneling field-effect transistor having a semiconductor substrate; a tunneling field-effect transistor formed on the semiconductor substrate and a fiber and reflection layer formed on the tunneling field-effect transistor; the tunneling field-effect transistor having a vertical channel structure , comprising a drain region of a first doping type formed underneath the vertical channel , a source region of a second doping type formed above the vertical channel , and gate regions formed on two sides of the vertical channel; and , wherein the angle between the reflection layer and the surface of the semiconductor substrate is between 30 and 60 degrees , and the light rays in the fiber are able to pass through the reflection layer and then reach the source region of the tunneling field-effect transistor , so that the photon-generated carriers are produced , comprising the following steps:providing a semiconductor substrate;performing ion injection to form a doped region of the first doping type in the semiconductor substrate;forming a hard mask layer;exposing and etching the semiconductor substrate and the hard mask layer to form the vertical channel structure;forming a first insulating film layer;forming a first conductive film layer;exposing and etching the first conductive film layer to form a gate electrode;performing ion injection to form a drain region of the second doping type;etching part of the first insulating film layer and etching to remove the remaining hard mask;forming a second insulating film layer and etching the second insulating film layer;forming a third insulating film layer and etching the second insulating film layer to form a contact hole;forming a second conductive film ...

POWER CONVERSION CIRCUIT, AND CHARGING APPARATUS AND SYSTEM

The invention provides a charging circuit, comprising a power conversion circuit, and an information collection and signal control circuit. The power conversion circuit is coupled to a voltage source and configured to provide a charging current to a battery. The power conversion circuit comprises a plurality of switch elements, and at least two storage elements, the at least two storage elements are selectively coupled to the voltage source and the output port through the plurality of switch elements. The information collection and signal control circuit is configured to collect information from the voltage source and battery, and control the plurality of switch elements to have the power conversion circuit work under different charging modes. 1. A charging apparatus , comprising:a first energy storage element; a first end coupled to an input power supply and', 'a second end coupled to a first end of the first energy storage element;, 'a first switch element having a first end coupled to the second end of the first switch element, and', 'a second end is coupled to an output end of the charging apparatus;, 'a second switch element having a first end coupled to a second end of the first energy storage element, and', 'a second end of the third switch element is grounded;, 'a third switch element having a first end coupled to a first end of the third switch element and the second end of the first energy storage element, and', 'a second end coupled to the output end;, 'a fourth switch element having a first end coupled to the first external connection end, and', 'a second end is coupled to a first end of the second energy storage element;, 'a fifth switch element having a first end coupled to the second end of the fifth switch element, and', 'a second end is coupled to ground; and, 'a sixth switch element having a first end coupled to the first end of the sixth switch element: and', 'a second end coupled to the output end., 'a second energy storage element having2. The ...

METHOD AND DEVICE FOR CARRYING OUT GROUTING BETWEEN ADJACENT GATEROADS IN INTERNAL-STAGGERED SPLIT-LEVEL COAL MINING

A method for carrying out grouting between adjacent gateroads in internal-staggered split-level coal mining. A return air gateroad of a stoping face and an inlet air gateroad of a heading face are not on the same level. The return air gateroad of the stoping face is arranged along a roof of a coal seam. The inlet air gateroad of the heading face is arranged along a floor of the coal seam. There is a height difference between the return air gateroad and the inlet air gateroad in a vertical direction. During the construction process, the inlet air gateroad is excavated at a delay distance of 180-200 meters from the return air gateroad. The drilling and grouting are performed while excavating the roadway, where grouting holes are arranged in a single row. A device for implementing the method is also provided. 1. A method for carrying out grouting between adjacent gateroads in internal-staggered split-level coal mining , the method comprising:excavating a roadway;drilling grouting holes; andperforming grouting through the grouting holes while excavating the roadway;wherein a stoping coal seam is a thick coal seam; a return air gateroad of a stoping face and an inlet air gateroad of a heading face are not on the same level; the return air gateroad of the stoping face is arranged along a roof of the stoping coal seam; the inlet air gateroad of the heading face is arranged along a floor of the stoping coal seam; there is a height difference between the return air gateroad of the stoping face and the inlet air gateroad of the heading face in a vertical direction; and during construction, the inlet air gateroad of the heading face is excavated at a delay distance of 180-200 m from the return air gateroad of the stoping face such that an inlet air gateroad of a next heading face is excavated after the return air gateway of the stoping face is stable.2. The method of claim 1 , wherein rock bolts of a roof of the inlet air gateroad and rock bolts of a floor of the return air ...

Device And Circuit For Protecting Controlled Loads, And Apparatus For Switching Between Loads

The disclosure relates to a device and a circuit for protecting controlled loads, and an apparatus for switching between the loads. The device includes: a plurality of load switches, comprising at least first and second load switches, wherein the first and second load switches are respectively in series connection with first and second controlled loads to form first and second controlled load branches in parallel connection, and each load switch is turned on when a switch control terminal is in a first voltage/current interval and turned off when the switch control terminal is in a second voltage/current interval; and a signal control module, including a signal control element, wherein the signal control element is switched between the switch control terminals of the first and second load switches for connection, and the signal control element enables, when being connected to the switch control terminal, the corresponding switch control terminal to be in the second voltage/current interval, and enables, when being disconnected from the switch control terminal, the corresponding control terminal to be in the first voltage/current interval. 1. A device for protecting controlled loads , comprising:a plurality of load switches, comprising at least a first load switch and a second load switch, wherein the first load switch is in series connection with a first controlled load to form a first controlled load branch, the second load switch is in series connection with a second controlled load to form a second controlled load branch, the first controlled load branch is in parallel connection with the second controlled load branch, and each of the first load switch and the second load switch comprises a switch control terminal, and is turned on when a potential/current of a corresponding switch control terminal is in a first voltage/current interval and turned off when the potential/current of the corresponding switch control terminal is in a second voltage/current interval; ...

SEMI-FLOATING-GATE DEVICE AND ITS MANUFACTURING METHOD

The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain. 1. A semi-floating-gate device , the device comprising:a semiconductor substrate of a first doping type;a perpendicular channel region formed in the semiconductor substrate;wherein a bottom of the perpendicular channel region is connected with a source region of a second doping type and a top of the perpendicular channel region is connected with a drain region of the second doping type;a first layer of insulation film which covers the source region, the drain region, and the perpendicular channel region;a floating gate opening region formed in the first layer of insulation film which covers the perpendicular channel region and is disposed above the semiconductor substrate;a floating gate of the first doping type which covers the first layer of the insulation film and the floating gate opening region, the floating gate being used as a charge storage node; wherein, through the floating gate opening region, a p-n junction diode is formed between the floating gate and the drain region; and wherein the floating gate covers the first layer of insulation film of the perpendicular channel region, controlling a current of the perpendicular channel region by controlling an electric field;a second layer of insulation film which covers the source region, the floating gate, and the p-n junction diode; anda control ...

INFORMATION FILTERING

This application discloses an information filtering method and an information processing apparatus. Shared information that is shared by a user account of an online service is obtained. A credibility reference rating associated with the user account is obtained. The credibility reference rating indicates account credibility of the user account. Whether the shared information satisfies a filtering condition is determined based on the credibility reference rating. Further, the shared information is filtered when the shared information is determined to satisfy the filtering condition. 1. An information filtering method , comprising:obtaining, by an information processing apparatus, shared information that is shared by a user account of an online service;obtaining a credibility reference rating associated with the user account, the credibility reference rating indicating account credibility of the user account;determining, by processing circuitry of the information processing apparatus, whether the shared information satisfies a filtering condition based on the credibility reference rating; andfiltering, by the processing circuitry of the information processing apparatus, the shared information when the shared information is determined to satisfy the filtering condition.2. The method according to claim 1 , wherein the filtering condition includes a preset credibility rating and the determining whether the shared information satisfies the filtering condition includes:determining whether the credibility reference rating is less than the preset credibility rating; andwhen the credibility reference rating is determined to be less than the preset credibility rating, determining that the shared information satisfies the filtering condition.3. The method according to claim 1 , wherein the filtering condition includes a first threshold and the determining whether the shared information satisfies the filtering condition includes:determining first quality information based on the ...

METHOD AND DEVICE FOR PROCESSING PHOTORESIST COMPONENT

The present disclosure provides a method for processing a photoresist component, including steps of: placing a photoresist component to be processed on a heating device comprising a plurality of heating components; and controlling, based on a heating parameter, each of the plurality of heating components associated with the heating parameter to heat the photoresist component to be processed. The heating parameter is determined based on a photoresist component parameter of the photoresist component to be processed and a process parameter of forming the photoresist component. The present disclosure further provides a device for processing a photoresist component. 1. A method for processing a photoresist component , comprising steps of:placing a photoresist component to be processed on a heating device comprising a plurality of heating components; andcontrolling, based on a heating parameter, each of the plurality of heating components associated with the heating parameter to heat the photoresist component to be processed.2. The method according to claim 1 ,wherein the heating parameter is determined based on a photoresist component parameter of the photoresist component to be processed and a process parameter of forming the photoresist component.3. The method according to claim 2 ,wherein the heating parameter comprises a heating temperature, and the photoresist component parameter comprises a size of the photoresist component and a position of the photoresist component on a substrate.4. The method according to claim 3 ,wherein the process parameter comprises at least one of an exposure process parameter and a development process parameter, andwherein the method further comprises a step of determining the heating parameter based on the photoresist component parameter and at least one of the exposure process parameter and the development process parameter.5. The method according to claim 4 ,wherein the exposure process parameter comprises an illumination distribution ...

PREPARATION METHOD OF HETEROATOM DOPED MULTIFUNCTIONAL CARBON QUANTUM DOT AND APPLICATION THEREOF

The present invention discloses a method for preparing heteroatom doped carbon quantum dot, and application thereof in fields of biomedicine, catalysts, photoelectric devices, etc. The various kinds of heteroatom doped carbon quantum dots are obtained by using a conjugated polymer as a precursor and through a process of high temperature carbonization. These carbon quantum dots contain one or more heteroatoms selected from the group consisting of N, S, Si, Se, P, As, Ge, Gd, B, Sb and Te, the absorption spectrum of which ranges from 300 to 850 nm, and the fluorescence emission wavelength of which is within a range of 350 to 1000 nm. The carbon quantum dot has a broad application prospect in serving as a new type photosensitizer, preparing drugs for photodynamic therapy of cancer and sterilization, photocatalytic degradation of organic pollutants, photocatalytic water-splitting for hydrogen generation, organic polymer solar cell and quantum dot-sensitized solar cell. 134-. (canceled)35. A method for preparing a heteroatom doped multifunctional carbon quantum dot , the method comprising:1) adding to a conjugated polymer, 0-1 M aqueous solution of acids or bases with the mass of 0.01-1000 times as many as the mass of the conjugated polymer, mixing uniformly and obtaining a reaction solution;2) heating the reaction solution up to 100° C.-500° C., and reacting for 1-24 hours;3) free cooling after the reaction, collecting the reaction solution, separating and purifying to obtain heteroatom doped multifunctional carbon quantum dots.37. The method according to claim 35 , wherein claim 35 , in step 1) claim 35 , the acid is one or more selected from the group consisting of hydrochloric acid claim 35 , hypochlorous acid claim 35 , perchloric acid claim 35 , hydrobromic acid claim 35 , hypobromous acid claim 35 , hyperbromic acid claim 35 , iodic acid claim 35 , hypoiodous acid claim 35 , periodic acid claim 35 , hydrofluoric acid claim 35 , boric acid claim 35 , nitric acid ...

DROP HAMMER HEIGHT ADJUSTING DEVICE FOR HIGH STRAIN DETECTION OF PILE FOUNDATION

The invention provides a drop hammer height adjusting device for high strain detection of a pile foundation, the device comprises: a cross beam support frame, an avoiding hole is opened in the middle of the surface of the cross beam support; a track extending through the avoiding hole, a tooth group is arranged on each of two surfaces of the track bar, and abutting sliding blocks are further arranged at two sides of the track bar. The abutting sliding block is cooperated with the tooth group to limit the position of the track bar. The invention overcomes the significant disadvantages of the existing detection devices, the efficiency of obtaining qualified test signals is improved by the rapid and accurate height adjustment and test, and the precision and efficiency of high strain detection of a foundation pile are greatly improved. 1. A drop hammer height adjusting device for high strain detection of a pile foundation , comprising:a cross beam support frame, an avoiding hole being opened in the middle of the cross beam support;a track extending through the avoiding hole, a tooth group being arranged on each of two surfaces of the track bar, and an abutting sliding block being further provided at each side of the track ;wherein the abutting sliding block is cooperated with the tooth group to limit the position of the track bar.2. The drop hammer height adjusting device for high strain detection of a pile foundation as claimed in claim 1 , wherein the tooth groups are arranged symmetrically on the two surfaces of the track bar.3. The drop hammer height adjusting device for high strain detection of a pile foundation as claimed in claim 1 , wherein one end of the abutting sliding block is provided at a side of the track bar claim 1 , the other end of the abutting sliding block is connected with a telescopic shaft claim 1 , the telescopic shaft extending through a fixed baffle claim 1 , a spring being sleeved on the telescopic shaft between the fixed baffle and the ...

Method of making a dynamic random access memory array

The present invention is related to microelectronic technologies, and discloses specifically a method of making a dynamic random access memory (DRAM) array. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices.

SURFACE PLASMON RESONANCE SENSOR CHIP, AND PREPARATION METHOD AND APPLICATION THEREOF

Disclosed is a surface plasmon resonance sensor chip, comprising a glass substrate layer, a gold film layer and a probe molecule layer. The gold film layer is disposed on the glass substrate layer and the probe molecule layer is disposed on the gold film layer. Also disclosed is a method for preparing the surface plasmon resonance sensor chip. By means of a surface plasmon resonance spectrum generated by the surface of the gold film disposed on the glass substrate, the content of lipopolysaccharide in an aqueous solution is detected in a fast, simple, quantitative and ultra-sensitive way. 2. The surface plasmon resonance sensor chip of claim 1 , wherein the thickness of the gold film layer is in the range of 10-60 nm; the thickness of the probe molecule layer is in the range of 1-100 nm; the coverage rate of the probe molecule layer on the gold film layer is in the range of 5%-100%.3. A method for preparing the surface plasmon resonance sensor chip of claim 1 , comprising the following steps:1) plating Au on the surface of the glass substrate;2) soaking the glass substrate obtained from step 1) completely in a probe molecule solution with a concentration of 0.01-1000 mg/mL, for 5 minutes-24 hours;3) taking the glass substrate out of the probe molecule solution and washing it repeatedly with water to obtain the surface plasmon resonance sensor chip.4. The method for preparing the surface plasmon resonance sensor chip of claim 3 , wherein the thickness of the gold film is in the range of 10-60 nm.5. The method for preparing the surface plasmon resonance sensor chip of claim 3 , wherein the solvent of the probe molecule solution is selected from:physiological saline, (2-hydroxyerhyl) piperazine-1-erhaesulfonic acid (HEPES) buffer solution or phosphate buffer solution; orone solvent selected from the group consisting of methanol, ethanol, methyl cyanide, dichloromethane, chloroform, tetrahydrofuran, methyl-sulfoxide, N,N-dimethyl formamide, and N,N-dimethyl acetamide or ...

POWER MOS TRANSISTOR AND MANUFACTURING METHOD THEREFOR

The present invention discloses a power Metal Oxide Semiconductor (MOS) transistor, wherein a second U-shaped trench is formed below a first U-shaped trench, so that a field oxidation stress transition region can be extended, so a s to greatly reduce current leakage caused by the field oxidation stress and improve the reliability of the device; and a charge compensation region is provided in a drift region at the bottom of the second U-shaped trench, and a super-junction structure is formed between the charge compensation region and the drift region to improve the breakdown voltage of the power device. According to the present invention, the second U-shaped trench and the charge compensation region are formed by a self-aligning process, so that the technical process is simple, reliable and easy to control, and can reduce the manufacturing cost of the power MOS transistor and improve its yield. 112-. (canceled)13. A power Metal Oxide Semiconductor (MOS) transistor , comprising:a drain region of a first doping type in a semiconductor substrate, a drift region of the first doping type, a channel region of a second doping type, a source region of the first doping type and a first U-shaped trench, wherein the drain region is provided at the bottom of the semiconductor substrate, the drift region is provided above the drain region, the channel region is provided on both sides of side walls of the first U-shaped trench and above the drift region, the bottom of the first U-shaped trench extends into the drift region, a gate oxide layer covering the channel region is provided on the both side walls of the first U-shaped trench, and the source region is provided at the top of the semiconductor substrate and above the channel region;a channel region contact region is provided in the channel region, the doping type of the channel region contact region is the same as that of the channel region, and a doping concentration of the channel region contact region is greater than that ...

SEMICONDUCTOR SUPER-JUNCTION POWER DEVICE AND MANUFACTURING METHOD THEREFOR

The present disclosure relates to the technical field of semiconductor power devices, and in particular relates to a semiconductor super-junction power device and a manufacturing method therefor. The super-junction power device of the present disclosure includes a termination region and a cell region; the cell region includes a substrate epitaxial layer and a drain region at a bottom of the substrate epitaxial layer, the substrate epitaxial layer has a plurality of pillar epitaxial doped regions and a plurality of JFET regions, a body region is arranged at a top of each of the plurality of pillar epitaxial doped regions; the body regions have at least two unequal widths; two source regions are arranged in each of the body regions; a gate oxide layer is arranged on the body regions and the JFET regions; and a gate is arranged on the gate oxide layer. 1. A semiconductor super-junction power device , comprising a termination region and a cell region , the cell region comprises a substrate epitaxial layer and a drain region at a bottom of the substrate epitaxial layer , the substrate epitaxial layer has a plurality of pillar epitaxial doped regions and a plurality of Junction Field-effect Transistor (JFET) regions , a body region is arranged at a top of each of the plurality of pillar epitaxial doped regions , wherein the body regions have at least two unequal widths , two source regions are arranged in each of the body regions , a gate oxide layer is arranged on the body regions and the JFET regions , and a gate is arranged on the gate oxide layer.2. The semiconductor super-junction power device according to claim 1 , wherein widths of the body regions are sequentially set as one of the following: C claim 1 , C+1D claim 1 , C claim 1 , C+1D claim 1 , C . . . ; C claim 1 , C+1D claim 1 , . . . claim 1 , C+nD claim 1 , C+(n−1)D claim 1 , C claim 1 , C+1D claim 1 , . . . claim 1 , C+nD claim 1 , C+(n−1)D claim 1 , . . . claim 1 , C claim 1 , . . . ; C claim 1 , C+1D claim ...

METHOD OF FORMING AN INTEGRATED INDUCTOR BY DRY ETCHING AND METAL FILLING

The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips. 1. A process for creating an inductive element comprising:a) applying a specific current between a first set of measurement nodes;b) forming an electromagnetic field around a metal conductor; andc) creating an inductive element between a second set of measurement nodes.2. The process as in claim 1 , wherein said step of creating an inductive element comprises providing at least one semiconductor.3. The process as in claim 1 , wherein said step of providing at least one semiconductor comprises:stacking and interconnecting a plurality of silicon wafers alternatively on a semiconductor substrate.4. The process as in claim 3 , wherein said step of providing at least one semiconductor comprises providing at least one monocrystalline silicon or monocrystalline silicon on an insulator.5. The process as in claim 3 , wherein said step of providing at least one semiconductor comprises providing at least one polycrystalline silicon or polycrystalline silicon on an insulator.6. A process for creating an inductive loop comprising:a) connecting a first set of measurement nodes in a short circuit method;b) forming a closed loop around a metal conductor to form an inductive element;c) forming mutual inductance with said inductive element ...

METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND THE MANUFACTURING METHODS THEREOF

The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor forms a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. 1. A method for manufacturing a field effect transistor structure integrated with a RRAM comprising a field effect transistor structure integrated with a resistance random access memory (RRAM) , comprising:a semiconductor substrate;a field effect transistor and a RRAM formed on said semiconductor substrate; 'the part of the gate dielectric layer on the surface of the drain region of the field effect transistor forms a resistance-variable storage layer of said RRAM;', 'a gate dielectric layer of said field effect transistor extends to the surface of a drain region of said field effect transistor; and'}, 'whereincomprising:forming a primary insulating film on the surface of a semiconductor substrate of a primary doping type;etching said primary insulating film to expose positions of a source region and a drain region of a field effect transistor;forming a source region and a drain region of a second doping type in said semiconductor substrate;etching to ...

TOUCH PANEL AND DISPLAY DEVICE

A touch panel includes a transparent substrate and a sensing pattern formed on the transparent substrate. The sensing pattern is in the form of a mesh structure. The mesh structure includes a plurality of conductive wires intersecting with each other to form a plurality of grids and a plurality of nodes connected between the grids. The grids are formed by the conductive wires intersecting with each other, and the nodes are formed at the intersection points of the conductive wires. The node has an annular shape with a center hole being defined in a center portion of the node. Due to the nodes having an annular shape, the surface resistance at the nodes is decreased and the signal attenuation is accordingly reduced. The conductive wires are connected firmly without the risk of breakage after the sensing pattern is formed. 1. A touch panel , comprising:a transparent substrate; anda sensing pattern formed on the transparent substrate, the sensing pattern being in the form of a mesh structure, the mesh structure including a plurality of conductive wires intersecting with each other to form a plurality of grids and a plurality of nodes connected between the grids, the grids being formed by the conductive wires intersecting with each other, the nodes being formed at the intersection points of the conductive wires, the node having an annular shape with a center hole being defined in a center portion of the node.2. The touch panel according to claim 1 , wherein the annular shape of the node is one of square shape claim 1 , circular shape claim 1 , polygonal shape claim 1 , and rectangular shape.3. The touch panel according to claim 1 , wherein the sensing pattern comprises sensing electrodes claim 1 , driving electrodes claim 1 , and lead lines claim 1 , the sensing electrodes claim 1 , the driving electrodes and the lead lines are each in the form of the mesh structure.4. The touch panel according to claim 3 , wherein the touch panel has an active region and a peripheral ...

SEMICONDUCTOR MEMORY WITH U-SHAPED CHANNEL

A semiconductor memory with a U-shaped channel comprises: a U-shaped channel region arranged in a semiconductor substrate, a source region, a drain region, a first layer of insulation film arranged on the U-shaped channel region, a floating gate provided with a notch, a second layer of insulation film, a control gate, a p-n junction diode arranged between the floating gate and the drain region, and a gate controlled diode formed by the control gate, the second layer of insulation film, and the p-n junction diode and using the control gate as a gate. Under the precondition of not increasing the manufacturing cost and difficulty of the semiconductor memory with a U-shaped channel and not affecting the performance of the semiconductor memory with a U-shaped channel, the dimension of a semiconductor storage device is further reduced and the chip density is increased by arranging the notch in the floating gate. 1. A U-shaped channel semiconductor memory , comprising:a semiconductor substrate of a first doping type provided with a U-shaped channel region;a source region and a drain region both of a second doping type provided in the semiconductor substrate, the U-shaped channel region being provided between the source region and the drain region;a first layer of insulating film disposed on the U-shaped channel region, the first layer of insulating film extending to a horizontal surface of the drain region;a floating gate opening region provided in the first layer of insulating film, the floating gate opening region being located on a side wall of the drain region on a top of the U-shaped channel region;a floating gate of the first doping type covering the first layer of insulating film and the floating gate opening region; anda p-n junction diode between the floating gate and the drain region;wherein the U-shaped channel semiconductor memory further comprises:a notch of the floating gate provided between a top of the floating gate and the source region, and a second layer ...

FILE TRANSFER METHOD, DEVICE, AND SYSTEM

Disclosed is a file transfer device, which runs on a computing device, and is configured to transfer a file on the computing device to a server and browse and/or download a file stored on the server. The file transfer device comprises: an upload controller, configured to transfer a local file of the computing device to the server and generate a corresponding file transfer record; and a download controller, configured to receive a download request for downloading data from the server, and determine, according to the file transfer record generated by the upload controller, whether the data in the download request is associated with the local file of the computing device, and if yes, acquire the data from the local file of the computing device, or if not, download the data from the server. Also disclosed are a corresponding file transfer method and corresponding network storage system. 1. A computing device , being configured to transfer a file on the computing device to a server and browse or download the file stored on the server , wherein the computing device comprises:a memory having instructions stored thereon;a processor configured to execute the instructions to perform operations, comprising:transferring the local file of the computing device to the server and generate a corresponding file transfer record;receiving a download request for downloading data from the server, and determining whether the data in the download request is associated with the local file of the computing device according to the file transfer record generated by the upload controller, and if yes, obtaining the data from the local file of the computing device, if not, downloading the data from the server.2. The computing device according to claim 1 , wherein the processor is further configured to perform:generating the download request which downloads data from the server when the download request requests to download the file from the server.3. The computing device according to claim 1 , ...

SEMI-FLOATING-GATE DEVICE AND ITS MANUFACTURING METHOD

The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain. 1. A semi-floating-gate device , wherein comprising:a semiconductor substrate with the first doping type;a perpendicular channel region formed in the semiconductor substrate;the bottom of the perpendicular channel region is connected with a source region with the second doping type, and the top of the perpendicular channel region is connected with a drain region with the second doping type;a first layer of insulation film formed due to covering the source region, the drain region and the perpendicular channel region;a floating gate opening region formed in the first layer of insulation film which covers the perpendicular channel region and lies above the semiconductor substrate;a floating gate with the first doping type which covers the first layer of the insulation film and the floating gate opening region, and the floating gate is used as the charge storage node; and through the floating gate opening region a p-n junction diode formed between floating gate and the drain region; and the floating gate covers the first layer of the insulation film of the perpendicular channel region, controlling the current of the perpendicular channel region by controlling the electric field;a second layer of insulation film formed due to covering the source region, the floating gate and the p-n junction diode;a control ...

A HIGH ELECTRON MOBILITY DEVICE BASED ON THE GATE-FIRST PROCESS AND THE PRODUCTION METHOD THEREOF

The present disclosure belongs to the technical field of radio frequency power devices, and more specifically, to a high electron mobility device based on the gate-first process and the production method thereof. The high electro mobility device is made by adopting the gate-first process according to the present disclosure, wherein gate dielectric sidewalls are utilized to implement the self-alignment of the gate and source; besides, the source and drain of the device can be formed directly by use of the alloying process, the iron implanting process or epitaxy process after formation of the gate since the gate is protected by the passivating layer, featuring a simple technological process while reducing parameter shift of products and enhancing the electrical properties of high electron mobility devices.

MONOSUBSTITUTED OR POLYSUBSTITUTED AMPHIPHILIC HYPOCRELLIN DERIVATIVE, AND PREPARATION METHOD AND APPLICATION THEREOF

The invention discloses a monosubstituted or polysubstituted amphiphilic hypocrellin derivative, and a preparation method and application thereof. The amphiphilic hypocrellin derivative substituted by a group containing PEG, a quaternary ammonium salt or the like prepared according to the invention has an obvious red shift in its absorption spectrum and a significantly enhanced molar extinction coefficient, compared with the parent hypocrellin, can efficiently produce singlet state oxygen and other reactive oxygen species under photosensitive conditions; has different amphiphilicities and increased biocompatibility with cells or tissues by regulating its hydrophilicity and hydrophobicity; can meet the requirements of different clinical drugs, and solves the requirements of different drug delivery methods for different drug hydrophilicity and lipophilicity. Under identical conditions, the amphiphilic hypocrellin derivative photosensitizer according to the invention has higher ability to photodynamically inactivate tumor cells than the first and second generation commercial photosensitizers. 8. A method for preparing the monosubstituted or polysubstituted amphiphilic hypocrellin derivative according to claim 1 , comprising the following steps:mixing hypocrellin B and a corresponding substituted amino derivative at a molar ratio of 1:5-50 in an organic solvent, which is one or more of acetonitrile, tetrahydrofuran, pyridine, methanol and ethanol, keeping the resulting solution in dark at a reaction temperature of 20-100° C. under the protection of an inert gas for 6-18 h, and purifying the product by separation to obtain the amphiphilic hypocrellin derivative in formula (IV) or formula (V).9. A method for preparing the monosubstituted or polysubstituted amphiphilic hypocrellin derivative according to claim 1 , comprising the following steps:mixing hypocrellin B or deacetylated hypocrellin B and a corresponding substituted thioethylamine derivative at a molar ratio of 1 ...

INFORMATION PROCESSING METHOD, CLIENT, SERVER AND COMPUTER-READABLE STORAGE MEDIUM

An information processing method, which is applied to a server, includes: a public message is transmitted to a first client, the public message being a message issued to the first client by the server, the public message carrying first information and a second information set including N pieces of second information, with N being a positive integer, the first information is information only allowed to be gotten by the first client and the second information is information only allowed to be gotten by a client in a sharing relationship with the first client; and a request for getting the second information is received from a second client, it is verified whether the second client is in the sharing relationship with the first client, and after the second client is determined to be in the sharing relationship with the first client, the second client is allowed to get the second information. 1. An information processing method , applied to a server , the method comprising:transmitting a public message to a first client, the public message being a message issued to the first client by the server, the public message carrying first information and a second information set, wherein the second information set comprises N pieces of second information, with N being a positive integer, the first information is information only allowed to be gotten by the first client and the second information is information only allowed to be gotten by a client in a sharing relationship with the first client; andreceiving a request for getting the second information from a second client, verifying whether the second client is in the sharing relationship with the first client, and after the second client is determined to be in the sharing relationship with the first client, allowing the second client to get the second information.2. The information processing method according to claim 1 , further comprising: after transmitting the public message to the first client and before receiving the ...

PROCESS FOR CONTINUOUSLY PRODUCING POLYOXYMETHYLENE DIMETHYL ETHERS AT LOW TEMPERATURE

The disclosure relates to a process for continuously producing polyoxymethylene dimethyl ethers at low temperature, pertains to the technical field of polyoxymethylene dimethyl ether preparation processes, and solves the technical problem of continuous production of polyoxymethylene dimethyl ether. A membrane separation element with precisely controlled pores in membrane is used to realize a direct separation of the feedstocks from the catalyst within the reactor, and effectively reduce the permeation resistance of the separation membrane tube. By oppositely switching the flowing direction of liquid reaction materials, the adhesion of the catalyst to the separation membrane tube is inhibited, and some particles stuck in separation membrane tube are removed, which ensures the continuous operation of the reaction process and allows a molecular sieve catalyst to exhibit its advantage of long catalytic life. 1. A process for continuously producing polyoxymethylene dimethyl ether at low temperature , characterized by comprising the following steps:{'b': 1', '3', '16', '2', '3', '16', '1', '3', '16', '5', '4, 'S1. A barrel pump () is in communication with a first dispenser () and a second dispenser () respectively through a DMM preheater (); the first dispenser () and the second dispenser () are both charged with trioxymethylene; the barrel pump () alternately pumps preheated dimethoxymethane into the first dispenser () or the second dispenser () to form uniform mixture; and the uniform mixture is pumped into a material tank () through a first feed pump (); wherein the molar ratio of dimethoxymethane to trioxymethylene is (2-10):1;'}{'b': 10', '5', '14', '7', '7', '11', '12', '11', '12', '10, 'sup': '−1', 'S2. A solid catalyst is added in a reactor (), and the reaction materials in the material tank () are pumped by a second feed pump () into the reactor through a four-way channel valve (). The two radially opposite ports of the four-way channel valve () are respectively ...

Arrays of Intersecting Double Stranded Nucleic Acid Helices

This disclosure relates to intersecting double stranded nucleic acid helices with flexible intersections that form antijuction units. In a typical embodiment, the configuration of the intersecting double stranded nucleic acid helices can be altered by hybridization with an added single stranded segment or trigger strand reconfiguring the conformation of the array in a directional manor. In certain embodiments, the dynamic antijunction unit contains four nucleic double-helix domains, typically of approximately equal length and four dynamic nicking or intersecting flex points providing an array with the capability of switching between two or more stable conformations, e.g., through an intermediate open conformation. 1. A double helix array of nucleic acids comprising intersections of four double stranded arms ,wherein a first double stranded arm and a second double stranded arm share a first polynucleotide strand,wherein the second double stranded arm and a third double stranded arm share a second polynucleotide strand,wherein the third double stranded arm and a fourth double stranded arm share a third polynucleotide strand, andwherein the fourth double stranded arm and the first double strand arm share a fourth polynucleotide strand; andwherein the first double stranded arm and the second double stranded arm form a first ring, and the third double stranded arm and the fourth double stranded arm form a second ring.2. The double helix array of claim 1 , wherein the second ring comprises a segment that is single stranded.3. The double helix array of claim 2 , wherein the second ring is on the boundary of the array.4. The double helix array of claim 1 , wherein the second double stranded arm and the third double stranded arm form a third ring claim 1 , and the first double stranded arm and the fourth double stranded arm form a fourth ring.5. The double helix array of claim 4 , wherein the boundary of the array comprises terminal 5′ single stranded polynucleotide sequence ...

Voltage Converter, Method for Controlling Voltage Converter, and Voltage Conversion System

A voltage converter includes a third switch element and a second energy storage element, and an energy storage circuit comprising a first switch element, a second switch element, and a first energy storage element. In a time period, the first switch element is in an on state, the second switch element and the third switch element are in an off state, and a voltage source coupled to the voltage converter charges the first energy storage element and the second energy storage element, and in a following time period, the first switch element is in an off state, the second switch element and the third switch element are in an on state, the first energy storage element and the second energy storage element discharge to a load coupled to the voltage converter. 1. A voltage converter , comprising: a first terminal; and', 'a second terminal, wherein the second terminal of the third switch is grounded;, 'a third switch comprising a first terminal; and', 'a second terminal coupled to a second external terminal of the voltage converter; and, 'a second energy storage comprising [ a first terminal coupled to a first external terminal of the voltage converter; and', 'a second terminal;, 'a first switch comprising, a first terminal coupled to the second terminal of the first switch; and', 'a second terminal coupled to the second external terminal of the voltage converter;', 'a first energy storage comprising:', 'a first terminal coupled to the second terminal of the first switch; and', 'a second terminal coupled to the first terminal of the third switch and the, 'a second switch comprising, 'first terminal of the second energy storage,, 'an energy storage circuit comprisingwherein, in a first time period, the first switch is configured to be in an on state, the second switch and the third switch are configured to be in an off state, and wherein the first energy storage and the second energy storage are configured to receive a charge from a voltage source coupled to the voltage ...

METHOD FOR IDENTIFYING AND SERVING SIMILAR WEB CONTENT

Aspects of the subject disclosure may include, for example, a method comprising receiving a request for content; retrieving the first portion of the content from an original source; retrieving an alternative portion, the alternative portion being a substitute for a second portion of the content; assembling an alternative presentation by combining the first portion and the alternative portion; and presenting the alternative presentation in response to receiving the request for content. Other embodiments are disclosed. 1. A method comprising:receiving, by a processing system comprising a processor, a request for content, the content including a first portion and a second portion, wherein the content is associated with an origin source of both the first portion and the second portion;retrieving, by the processing system, the first portion;retrieving, by the processing system, an alternative portion, the alternative portion being a substitute for the second portion;assembling, by the processing system, an alternative presentation by combining the first portion and the alternative portion; andpresenting, by the processing system, the alternative presentation in response to the receiving the request for content.2. The method of claim 1 , wherein the retrieving the first portion comprises retrieving the first portion from the origin source and wherein retrieving the alternative portion comprises retrieving the alternative portion from an alternative source claim 1 , and wherein the alternative source is not the origin source.3. The method of claim 2 , wherein the alternative portion is different from the second portion.4. The method of claim 1 , wherein the first portion is textual and retrieved from the origin source such that the first portion presented as part of the alternative presentation is the first portion of the content requested in the request for content.5. The method of claim 1 , wherein the second portion is graphical claim 1 , wherein the alternative portion ...

Distributed device and method for detecting groundwater based on nuclear magnetic resonance

A distributed device and method for detecting groundwater based on nuclear magnetic resonance are provided. The device includes an excitation apparatus, multiple polarization apparatuses, an aerial reception apparatus, and a control apparatus. The aerial reception apparatus includes an array cooled coil sensor. For each of the multiple polarization apparatuses, a position analysis module determines, together with a second position analysis module of the polarization apparatus, a position of the array cooled coil sensor relative to a polarization coil in the polarization apparatus. A polarization transmitter in the polarization apparatus switches to a mode of waiting for output in a case that the array cooled coil sensor is in coverage of the polarization coil. The polarization transmitter in the polarization apparatus remains in a standby mode in a case that the array cooled coil sensor is beyond coverage of the polarization coil.

OTA DIFFERENTIAL UPGRADE METHOD AND SYSTEM OF MASTER-SLAVE ARCHITECTURE

The invention relates to the filed of the Internet of Things, and in particular, to an OTA differential upgrade method and system of a master-slave architecture. The method comprises: Step S1, obtaining an upgrade scheme, and determining a master-slave connection relationship and an upgrade manner according to the upgrade scheme; Step S2, downloading a differential upgrading file; Step S3, determining a processing mode of a master node according to the upgrading manner of a slave node; if the upgrading manner of the slave node is a first manner, the node flashes and restores the differential upgrading file and sends the differential upgrading file to the slave node, so that the slave node completes upgrading; if the upgrading manner of the slave node is a second manner, the master node flashes and restores the differential upgrading file and sends the differential upgrading file to the slave node for upgrading. 1. An OTA differential upgrade method of a master-slave architecture , comprising a server and a plurality of nodes to be upgraded , wherein the plurality of nodes to be upgraded comprise a root node;the OTA differential upgrade method comprises:Step S1, obtaining, by the root node, a preset upgrade scheme from the server, and determining a master-slave connection relationship between every two of the plurality of nodes to be upgraded and an upgrading manner for each of the plurality of nodes to be upgraded according to the upgrade scheme;Step S2, downloading, by the root node, a differential upgrading file from the server according to the upgrade scheme;Step S3, for every two of the plurality of nodes to be upgraded having the master-slave connection relationship, determining a processing mode of a master node according to the upgrading manner of a slave node;if the upgrading manner of the slave node is a first manner, then turn to Step S4;if the upgrading manner of the slave node is a second manner, then turn to Step S5;Step S4, the master node flashes and ...

Organic compound having electron-transporting and/or hole-blocking performance and its use and OLEDs comprising the compound

Disclosed herein are several organic compounds having electron-transporting and/or hole-blocking performance and their preparation method and use and the OLEDs comprising the organic compound. The organic compounds exhibit high ionization potential (IP), electron affinity (Ea), glass transition temperature (Tg) and high electron mobility, and are a kind of good electron-transporting material with good hole-blocking ability. The devices comprising these compounds as one of the emitting layer, electron-transporting layer (ETL) and hole-blocking layer (HBL) show improved efficiency and better color purity.

CATHODE MATERIAL AND METHOD FOR PREPARING CATHODE MATERIAL, CATHODE, LITHIUM ION BATTERY AND VEHICLE

The present disclosure provides a cathode material and a method for preparing the cathode material, a cathode, a lithium ion battery and a vehicle. The cathode material comprises a matrix particle, wherein the matrix particle is a monocrystal particle comprising nickel lithium manganate and nickel cobalt lithium manganate. A position in the matrix particle close to a surface layer is provided with a buffer layer. A content of at least one of elements Ni, Co and Mn in the buffer layer is lower than contents thereof in other positions of the matrix particle. The cathode material has at least one of advantages of relatively high specific capacity, cycling stability, better safety performance and the like, and the buffer layer can alleviate erosion by an electrolyte and inhibit separation of active oxygen.

Organic electroluminescence device

An electroluminescence device has an anode, a cathode and an emitting layer located between the anode and the cathode. The emitting layer contains a compound selected from a group consisting of neutral red and its derivatives.

Tunnel transistor structure integrated with a resistance random access memory (RRAM) and a manufacturing method thereof

The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient.

Method for identifying and serving similar web content

Aspects of the subject disclosure may include, for example, a method comprising receiving a request for content; retrieving the first portion of the content from an original source; retrieving an alternative portion, the alternative portion being a substitute for a second portion of the content; assembling an alternative presentation by combining the first portion and the alternative portion; and presenting the alternative presentation in response to receiving the request for content. Other embodiments are disclosed.

Potent neutralizing antibodies against sars-cov-2, generation and uses thereof

The subject matter described herein relates to potent monoclonal and bispecific antibodies capable of neutralizing a SARS-CoV-2 viruses and methods of generating the antibodies.

Portable intelligent human body three-dimensional scanning equipment

本实用新型涉及三维扫描技术领域，且公开了一种便携式智能人体三维扫描设备，包括底板和三维扫描仪本体，所述底板顶部的两侧分别固定安装有基座和套筒，所述套筒的顶部插接有支撑套管，所述支撑套管的顶端活动套接有支撑杆，所述支撑杆上套接有活动块，所述活动块靠近基座的一侧固定安装有数量为两个的固定片，两个所述固定片之间活动套接有螺纹杆，所述螺纹杆的中部螺纹套接有位于两个固定片之间的连接板。本实用新型结构简单，拆装方便，便于折叠运输和携带，提高了携带便捷性，再通过底板和滚轮的设计，提高了该设备的移动便捷性，便于在各个工作场合之间移动和运输，有利于提高便携性。

Method and device for processing photoresist component

The present disclosure provides a method for processing a photoresist component, including steps of: placing a photoresist component to be processed on a heating device comprising a plurality of heating components; and controlling, based on a heating parameter, each of the plurality of heating components associated with the heating parameter to heat the photoresist component to be processed. The heating parameter is determined based on a photoresist component parameter of the photoresist component to be processed and a process parameter of forming the photoresist component. The present disclosure further provides a device for processing a photoresist component.

Method for manufacturing vertical-channel tunneling transistor

The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost.

Open multi-strand cord

A steel cord ( 10 ) adapted for the reinforcement of rubber products, comprises a core strand ( 12 ) and six peripheral strands ( 14 ) concentrically surrounding the core strand ( 12 ). Each of the core and peripheral strands ( 12, 14 ) comprises a center of two or more center filaments ( 16 ) and two layers of filaments surrounding the center. The core strand ( 12 ) has a diameter D 1 which is greater than the diameter D 2 of the peripheral strands ( 14 ). All the filaments ( 18, 20 ) of each layer have substantially the same diameter and a radially outer layer has a twist angle which is greater than a twist angle of a radially inner layer of the same strand. Each of the strands ( 12, 14 ) in the cord is composed of no more than twenty-six filaments ( 16, 18, 20 ) being twisted together.

Lithium nickel manganese oxide composite material, preparation method thereof and lithium ion battery

Provided are a lithium nickel manganese oxide composite material, a preparation method thereof and a lithium ion battery. The preparation method includes: a first calcining process is performed on a nano-oxide and a nickel-manganese precursor, to obtain an oxide-coated nickel-manganese precursor; and a second calcining process is performed on the precursor and a lithium source material, to obtain the lithium nickel manganese oxide, and a temperature of the first calcining process is lower than the second calcining process. At a lower temperature, the nano-oxide may be melted, a denser nano-oxide coating layer is formed on the surface of the precursor, so the oxide-coated nickel-manganese precursor is obtained. At a higher temperature, the nano-oxide, a nickel-manganese material and a lithium element may be more deeply combined. A problem that the nano-oxide layer is easy to fall off is solved, and cycle performance of the lithium nickel manganese oxide is greatly improved.

CIRCONY ALLOY MATERIAL FOR THE NUCLEUS OF A NUCLEAR ENERGY REACTOR AND MATERIAL PREPARATION METHOD

Reivindicación 1: Un material de aleación de circonio para el núcleo de un reactor de energía nuclear, caracterizado por contener, en porcentaje por peso, los componentes siguientes: Sn: 0,60 - 1,00, Nb: 0,80 - 1,10, Fe: 0,10 - 0,40, Cu o Bi o Ge: 0 - 0,1, Si o S: 0 - 0,03, O: 0,06 - 0,15, C: menos de 0,008, N: menos de 0,006, el contenido residual es circonio. Reivindicación 10: Un método de preparación del material de aleación de circonio según alguna de las reivindicaciones precedentes, caracterizado por los pasos siguientes: (1) se hace la dosificación según el coeficiente de la fórmula de todos los tipos de componentes de la aleación del circonio; (2) se implementa la fundición en el horno de arco del electrodo consumible del vacío para fabricar los lingotes de molde fundido de la aleación; (3) se fraguan los lingotes de molde fundido de la aleación a las materiales en las formas requeridas en la zona de la Fase b dentro la temperatura de 950ºC - 1080ºC; (4) se realiza la calefacción uniforme y el tratamiento de endurecimiento en la zona de la Fase b dentro la temperatura de 1000ºC - 1100ºC; (5) se realiza el tratamiento térmico de los materiales de lingote en la zona de la Fase a dentro la temperatura de 600ºC - 650ºC después del tratamiento de endurecimiento; (6) se realiza el tratamiento frío de los materiales de lingote después del tratamiento térmico, y se realiza el recocido intermedio dentro la temperatura de 550ºC - 620ºC; (7) se realiza el tratamiento de endurecimiento para eliminar la tensión y el tratamiento de recocido de la recristalización dentro la temperatura de 460ºC - 600ºC para obtener los materiales de la aleación del circonio. Claim 1: A zirconium alloy material for the core of a nuclear power reactor, characterized by containing, in percentage by weight, the following components: Sn: 0.60-1.00, Nb: 0.80-1, 10, Fe: 0.10-0.40, Cu or Bi or Ge: 0-0.1, Si or S: 0-0.03, O: 0.06-0.15, C: less than 0.008, N: less than 0.006, the residual content ...

Power conversion circuit, and charging apparatus and system

A power conversion circuit and a charging apparatus are disclosed, to support a plurality of charging modes and increase a battery charging rate. The circuit includes: A first end of a first switch element is coupled and connected to an input power supply through a first external connection end of the power conversion circuit, a second end of the first switch element is separately coupled to a first end of a first energy storage element and a first end of a second switch element, a second end of the first energy storage element is separately coupled to a first end of a third switch element and a first end of a fourth switch element, a second end of the second switch element is coupled and connected to a battery through a second external connection end of the power conversion circuit, a second end of the fourth switch element is coupled to the second external connection end, a second end of the third switch element is grounded, a first end of a fifth switch element is coupled to the first external connection end, a second end of the fifth switch element is separately coupled to a first end of a second energy storage element and a first end of a sixth switch element, a second end of the second energy storage element is coupled to the second external connection end, and a second end of the sixth switch element is grounded.

Touch panel and display device

A touch panel includes a transparent substrate and a sensing pattern formed on the transparent substrate. The sensing pattern is in the form of a mesh structure. The mesh structure includes a plurality of conductive wires intersecting with each other to form a plurality of grids and a plurality of nodes connected between the grids. The grids are formed by the conductive wires intersecting with each other, and the nodes are formed at the intersection points of the conductive wires. The node has an annular shape with a center hole being defined in a center portion of the node. Due to the nodes having an annular shape, the surface resistance at the nodes is decreased and the signal attenuation is accordingly reduced. The conductive wires are connected firmly without the risk of breakage after the sensing pattern is formed.

Cobalt-free single crystal composite material, and preparation method therefor and use thereof

A cobalt-free single crystal composite material, and a preparation method therefor and a use thereof. The cobalt-free single crystal material is of a core-shell structure, the core layer is the cobalt-free single crystal material, and the shell layer is prepared from TiNb 2 O 7 and conductive lithium salt. The TiNb 2 O 7 and the conductive lithium salt are selected as materials of the shell layer to coat the cobalt-free single crystal material, thereby improving the lithium ion conductivity of the cobalt-free single crystal material, and further improving the capacity and the first effect of the material.

Monosubstituted or polysubstituted amphiphilic hypocrellin derivative, preparation method therefor, and uses thereof

The invention discloses a monosubstituted or polysubstituted amphiphilic hypocrellin derivative, and a preparation method and application thereof. The amphiphilic hypocrellin derivative substituted by a group containing PEG, a quaternary ammonium salt or the like prepared according to the invention has an obvious red shift in its absorption spectrum and a significantly enhanced molar extinction coefficient, compared with the parent hypocrellin, can efficiently produce singlet state oxygen and other reactive oxygen species under photosensitive conditions; has different amphiphilicities and increased biocompatibility with cells or tissues by regulating its hydrophilicity and hydrophobicity; can meet the requirements of different clinical drugs, and solves the requirements of different drug delivery methods for different drug hydrophilicity and lipophilicity. Under identical conditions, the amphiphilic hypocrellin derivative photosensitizer according to the invention has higher ability to photodynamically inactivate tumor cells than the first and second generation commercial photosensitizers.

Process for continuously producing polyoxymethylene dimethyl ethers at low temperature

The disclosure relates to a process for continuously producing polyoxymethylene dimethyl ethers at low temperature, pertains to the technical field of polyoxymethylene dimethyl ether preparation processes, and solves the technical problem of continuous production of polyoxymethylene dimethyl ether. A membrane separation element with precisely controlled pores in membrane is used to realize a direct separation of the feedstocks from the catalyst within the reactor, and effectively reduce the permeation resistance of the separation membrane tube. By oppositely switching the flowing direction of liquid reaction materials, the adhesion of the catalyst to the separation membrane tube is inhibited, and some particles stuck in separation membrane tube are removed, which ensures the continuous operation of the reaction process and allows a molecular sieve catalyst to exhibit its advantage of long catalytic life. The present process is simple and gives high product selectivity at mild conditions. It also greatly reduces the cost and energy consumption for synthesis of DMM n , and thus, has broad and potential industrial application prospects.