SYSTEMS, METHODS AND APPARATUSES FOR MANUFACTURING DOSAGE FORMS

Systems, methods and apparatuses for manufacturing dosage forms, and to dosage forms made using such systems, methods and apparatuses are provided. Novel compression, thermal cycle molding, and thermal setting molding modules are disclosed. One or more of such modules may be linked, preferably via novel transfer device, into an overall system for making dosage forms. 1. A method of preparing a compressed dosage form comprising the steps of:(i) placing a supply of powder in flow communication with a die, said die comprising a die cavity therein;(ii) applying suction to said die cavity so as to cause powder to flow into said die cavity; and(iii) compressing said powder in said die cavity so as to form a compressed dosage form.2. The method of according to claim 1 , wherein said compressed dosage form comprises a first medicant.3. The method according to claim 1 , wherein said method is performed while said mold cavity is traveling along a circular path.4. The method according to claim 1 , wherein said method is performed while said mold cavity is traveling along a helical path.5. The method according to claim 1 , wherein said compressed dosage form comprises an insert embedded therein.6. The method according to claim 5 , wherein said insert comprises a thermal-setting material.7. The method of claim 5 , wherein said insert comprises a second medicant.8. The method according to claim 1 , wherein said flowable material comprises a third medicant. This application is a divisional of U.S. Ser. No. 10/911,263 filed Aug. 4, 2004, which is a continuation of U.S. Ser. No. 09/966,497 filed Sep. 28, 2001, now U.S. Pat. No. 7,122,143, the complete disclosures of which are hereby incorporated by reference herein for all purposes.This invention relates generally to systems, methods and apparatuses for manufacturing dosage forms, and to dosage forms made using such systems, methods and apparatuses.A variety of dosage forms, such as tablets, capsules and gelcaps are known in the ...

Lighting Apparatus and Light Emitting Diode Device Thereof

The present invention provides a light emitting diode (LED) device. The LED device include a driver, a first LED coupled in series with the driver, and an impedance-providing component coupled in parallel with the first LED and in series with the driver. The impedance-providing component provides a shunt impedance having a value that varies in positive proportion with a variation in an ambient temperature. The driver is respectively coupled in series with the first LED and the at least one impedance-providing component. The driver provides a drive current divided to flow through the first LED and the at least one impedance-providing component according to the shunt impedance and the internal impedance. 1. A light emitting diode (LED) device , comprising:a first LED having an internal impedance and configured to emit light of a first wavelength;at least one impedance-providing component coupled in parallel with the first LED, the at least one impedance-providing component providing a shunt impedance having a value that varies in positive proportion with a variation in an ambient temperature; anda driver respectively coupled in series with the first LED and the at least one impedance-providing component, the driver providing a drive current divided to flow through the first LED and the at least one impedance-providing component according to the shunt impedance and the internal impedance.2. The LED device as recited in claim 1 , wherein the at least one impedance-providing component comprises a plurality of impedance-providing components each of which providing a respective shunt impedance having a respective value that varies in positive proportion with the variation in the ambient temperature.3. The LED device as recited in claim 1 , wherein the at least one impedance-providing component comprises a semiconductor component claim 1 , a thermistor claim 1 , a transistor claim 1 , or a diode having a positive temperature coefficient.4. The LED device as recited in claim ...

TOUCH SENSING METHOD

A touch sensing method for a touch panel is provided. The touch sensing method includes following steps. First, a plurality of sensing values of a plurality of sensing points are received so as to calculate a plurality of sensing difference values according to the sensing values. Next, a touch threshold value is determined according to at least one (e.g., a maximum one) of the sensing difference values. Then, the sensing difference values are compared with the touch threshold value to determine the coordinates of the touched ones of the sensing points according to the comparison result. 1. A touch sensing method , adapted to a touch panel , and the touch sensing method comprising:receiving a plurality of sensing values of a plurality of sensing points to calculate a plurality of sensing difference values according to the sensing values;determining a touch threshold value according to at least one of the sensing difference values; andcomparing the sensing difference values with the touch threshold value, and determining which one in the sensing points is touched according to a comparison result.2. The touch sensing method as claimed in claim 1 , wherein the step of determining the touch threshold value according to at least one of the sensing difference values comprises determining the touch threshold value according to a maximum sensing difference value of the sensing difference values.3. The touch sensing method as claimed in claim 2 , wherein the step of determining the touch threshold value according to the maximum sensing difference value of the sensing difference values comprises:comparing the maximum sensing difference value with a predetermined value; anddetermining the touch threshold value according to a comparison result.4. The touch sensing method as claimed in claim 3 , wherein the step of determining the touch threshold value according to the comparison result comprises:increasing the touch threshold value when the maximum sensing difference value is ...

Noise Filtering Method

The present invention discloses a noise filtering method for a touch control display device. The noise filter method includes retrieving a plurality of touch signals, wherein the plurality of touch signals correspond to a plurality of touch points of the touch control display device, selecting a plurality of environmental sensing signals from the plurality of the touch signals according to a touch threshold value, calculating a peak-to-peak value of the plurality of the environmental sensing signals, comparing the peak-to-peak value with a noise threshold value to generate a comparison result, and determining a filtering coefficient according to the comparison result in order to perform a noise filtering procedure accordingly. 1. A noise filtering method for a touch control display device , comprising:retrieving a plurality of touch signals, wherein the plurality of touch signals correspond to a plurality of touch points of the touch control display device;selecting a plurality of environmental sensing signals from the plurality of the touch signals according to a touch threshold value;calculating a peak-to-peak value of the plurality of the environmental sensing signals;comparing the peak-to-peak value with a noise threshold value to generate a comparison result; anddetermining a filtering coefficient according to the comparison result in order to perform a noise filtering procedure accordingly.2. The noise filtering method of claim 1 , wherein the step of retrieving the plurality of touch signals comprises:simultaneously retrieving touch signals sensed by the plurality of touch points of the touch control display device to be the plurality of touch signals.3. The noise filtering method of claim 1 , wherein the step of selecting the plurality of environmental sensing signals from the plurality of touch signals according to the touch threshold value comprises:comparing the plurality of touch signals with the touch threshold value; andselecting the plurality of touch ...

Multi-touch Positioning Method

A multi-touch positioning method for a touch control device is disclosed. The touch control device includes a plurality of sensing channels, and each of the plurality of sensing channels is interlaced by a first sensing electrode and a second sensing electrode. The multi-touch positioning method includes retrieving a first touch sensing value and a second touch sensing value respectively corresponding to the first sensing electrode and the second sensing electrode, adding the first touch sensing value and the second touch sensing value to generate a sensing sum value, determining a touch sensing channel having a local maximum value according to the plurality of sensing sum values of the plurality of sensing channels, so as to define a touch point on the touch sensing channel, and calculating a coordinate of the touch point according to the touch sensing channel and its neighboring sensing channels. 1. A multi-touch positioning method for a touch control device , the touch control device comprising a plurality of sensing channels , each of the plurality of sensing channels being interlaced by a first sensing electrode and a second sensing electrode , the multi-touch positioning method comprising:retrieving a first touch sensing value and a second touch sensing value respectively corresponding to the first sensing electrode and the second sensing electrode of each of the sensing channels;adding the first touch sensing value and the second touch sensing value to generate a sensing sum value corresponding to each sensing channel;determining a touch sensing channel having a local maximum value according to the plurality of sensing sum values of the plurality of sensing channels, so as to define a touch point on the touch sensing channel; andcalculating a coordinate of the touch point according to the first touch sensing value, the second touch sensing value, the sensing sum value and a coordinate according to the touch sensing channel and its neighboring sensing channels ...

Lighting Apparatus And Light Emitting Diode Device Thereof

A lighting emitting diode (LED) device includes a first adjust module and a second adjust module. The first adjust module includes at least one first LED and has a first internal impedance having a first characteristic curve. A range covered by the first characteristic curve includes a first incomplete conduction region and a first conduction region. As the current increases from zero value and up, the first internal impedance decreases exponentially in the first incomplete conduction region, is approximately linear in the first conduction region. The second adjust module includes an impedance-providing component and an electronic component coupled in series. The second adjust module is coupled in parallel with the first adjust module. The second adjust module has a second internal impedance having a second characteristic curve. The first characteristic curve and the second characteristic curve match one another.

METHOD FOR DATA MANAGEMENT

A method for data management includes providing a data management platform with a plurality of data folders for storing data; the data management platform receiving and storing a plurality of data objects in the plurality of data folders, the plurality of data objects including uniform resource locator links, document files, audio/video streaming files and/or application software files; the data management platform capturing and storing opening page snapshots of the data objects when being opened; and when a terminal device links to the data management platform via a network for accessing a first data folder of the plurality of data folders, the terminal device displaying opening page snapshots of data objects stored in the first data folder. 1. A method for data management , comprising:providing a data management platform with a plurality of data folders for storing data;the data management platform receiving and storing a plurality of data objects in the plurality of data folders, the plurality of data objects comprising uniform resource locator (URL) links, document files, audio/video streaming files and/or application software files;the data management platform capturing and storing opening page snapshots of the data objects when being opened; andwhen a terminal device links to the data management platform via a network for accessing a first data folder of the plurality of data folders, the terminal device displaying opening page snapshots of data objects stored in the first data folder.2. The method of further comprising:the terminal device selecting an opening page snapshot of a first data object stored in the first data folder; andopening the first data object.3. The method of claim 2 , wherein when the first data object is a URL link claim 2 , opening the first data object is opening a web page indicated by the URL link.4. The method of claim 2 , wherein when the first data object is a document file claim 2 , an audio/video streaming file claim 2 , or an ...

EMBEDDING VISUAL INFORMATION IN A TWO-DIMENSIONAL BAR CODE

A two dimensional barcode containing encoded information can be embedded with an image with a high visual quality. The encoded information within the barcode is meaningful to machines, while the image is meaningful to humans. The two dimensional barcode embedded with the image is designed such that machines can decode the information encoded within the two dimensional barcode even with the distortion from the image. The subject application describes various systems, methods and devices that can facilitate embedding the image within the two dimensional barcode, detecting the two dimensional barcode embedded with the image within a practical environment, and decoding the encoded information from the two dimensional barcode even with the distortion from the image. 1. A system , comprising:a memory to store computer-executable instructions; and encode a message within a two dimensional barcode;', 'embed a gray scale image into the two dimensional barcode to form a watermarked barcode via a watermarking that employs at least two tiling patterns; and', 'add a finder pattern with markings at all four corners of the finder pattern to the watermarked barcode., 'a processor that executes or facilitates execution of the computer-executable instructions to at least2. The system of claim 1 , wherein the watermarking comprises:extraction of a block that is determined to represent at least one bit of data from the gray scale image;comparison of the block to one of the at least two tiling patterns based on a value of the at least one bit of data represented by the block; andsetting a gray scale value for first pixels within the block based on the comparison between the first pixels within the block to second pixels within the one of the at least two tiling patterns.3. The system of claim 2 , wherein the comparison further comprises a pixel by pixel comparison between the first pixels within the block the second pixels within the one of the at least two tiling patterns claim 2 , ...

SUPPORT FOR AFFINITY CHROMATOGRAPHY AND METHOD FOR ISOLATING IMMUNOGLOBULIN

Provided are a support for affinity chromatography which has excellent alkali resistance, and a method for isolating immunoglobulin. A support for affinity chromatography, containing an immobilized protein ligand represented by the following formula (1): 14-. (canceled)5. A support for affinity chromatography , comprising an immobilized protein ligand represented by the following formula (I):{'br': None, 'sup': '2', 'R—R\u2003\u2003(1)'}wherein R represents a polypeptide consisting of 4 to 30 amino acid residues containing an amino acid sequence represented by ATK or ASK;{'sup': '2', 'and wherein Rrepresents a polypeptide consisting of 50 to 500 amino acid residues that contains an immunoglobulin-binding domain consisting of an amino acid sequence represented by SEQ ID NO: 1 or SEQ ID NO: 2, or consisting of an amino acid sequence having 90% or more identity to the amino acid sequence represented by SEQ ID NO: 1 or SEQ ID NO: 2;'}{'sup': '2', 'with the proviso that a terminus at which Rbinds to R is C-terminus or N-terminus of the immunoglobulin-binding domain.'}6. The support for affinity chromatography according to claim 5 , wherein the amino acid sequence having 90% or more identity to the amino acid sequence represented by SEQ ID NO: 1 or SEQ ID NO: 2 is an amino acid sequence represented by SEQ ID NO: 3.7. The support for affinity chromatography according to claim 5 , wherein the R contains an amino acid sequence represented by the combination of ATK and ASK.8. The support for affinity chromatography according to claim 6 , wherein the R contains an amino acid sequence represented by the combination of ATK and ASK.9. The support for affinity chromatography according to claim 7 , wherein the R contains an amino acid sequence represented by ATKASK or ASKAKT.10. The support for affinity chromatography according to claim 8 , wherein the R contains an amino acid sequence represented by ATKASK or ASKAKT.11. The support for affinity chromatography according to any one ...

Sense Device and Capacitive Touch Control Display

A sense device for a capacitive touch control display is disclosed. The sense device includes a plurality of sense channels paralleled to each other, each of the sense channel including a first sense electrode having a first geometric figure for outputting a first sense signal, a second sense electrode having a second geometric figure for outputting a second sense signal, and a third sense electrode formed between the first sense electrode and the second sense electrode for outputting a third sense signal. An operation unit of the capacitive touch control display determines a plurality of touch positions according to the first sense signal, the second sense signal and the third sense signal. 1. A sense device for a capacitive touch control display comprisinga plurality of sense channels paralleled to each other, each of the sense channel comprising:a first sense electrode having a first geometric figure for outputting a first sense signal;a second sense electrode having a second geometric figure for outputting a second sense signal; anda third sense electrode formed between the first sense electrode and the second sense electrode for outputting a third sense signal;wherein an operation unit of the capacitive touch control display determines a plurality of touch positions according to the first sense signal, the second sense signal and the third sense signal.2. The sense device of claim 1 , wherein the first geometric figure and the second geometric figure are the same.3. The sense device of claim 2 , wherein the first geometric figure is an equilateral triangle.4. The sense device of claim 2 , wherein the first geometric figure is formed by connecting a plurality of equilateral triangles side by side.5. The sense device of claim 1 , wherein the first geometric figure and the second geometric figure are different.6. The sense device of claim 5 , wherein the first geometric figure is an equilateral triangle.7. The sense device of claim 5 , wherein the second geometric ...

CAPACITIVE TOUCH DEVICE AND DETECTION METHOD THEREOF

A detection method for a capacitive touch device is provided. The detection method includes steps of: driving an Mdriving line among an m driving lines of the capacitive touch device, wherein M is a natural number smaller than or equal to m and greater than 1; selecting a plurality of sensing lines among n sensing lines; obtaining a plurality of sensing values by detecting voltage changes at the selected sensing lines; determining whether to perform a noise reduction operation on the sensing values; if yes, calculating respective differences between the sensing values and a baseline value, and generating a noise correction value corresponding to the sensing values by performing a statistical computation on the differences; and correcting the differences according to the noise correction value. 1. A capacitive touch device , comprising:a capacitive touch panel, comprising a sensing point matrix formed by m driving lines and n sensing lines, m and n being positive integers;a driving control unit, coupled to the m driving lines, for sequentially providing m driving signals to the m driving lines in m corresponding driving periods, respectively;a conversion unit, coupled to the n sensing lines, for obtaining n sensing values through conversion with reference to voltages at a plurality of sensing points corresponding to the n sensing lines in the m corresponding driving periods, respectively; anda processing unit, coupled to the conversion unit, for receiving the m×n sensing values in each of the m driving periods, and dividing the m×n sensing values into a plurality of sensing value sets with reference to conversion time sequences of the m×n number of sensing values; the sensing values in each of the sensing value sets being substantially obtained at a substantially same time point through the conversion unit;wherein, the processing unit identifies a plurality of noise correction values for the sensing value sets on basis of the sensing value sets, respectively, and ...

NOVEL ALKALI-RESISTANT VARIANTS OF PROTEIN A AND THEIR USE IN AFFINITY CHROMATOGRAPHY

The present invention relates to immunoglobulin (Ig)-binding proteins with alkali-resistance properties. In one embodiment, the present invention provides for a variant of an Ig-binding protein, the variant comprising the Ig-binding protein having at least one asparagine residue substituted with a histidine, a serine, an aspartic acid or a threonine residue. The at least one substitution may confer to the variant Ig-binding protein an increased stability in alkaline solutions when compared to the wild-type Ig-binding. The present invention relates also to matrices for affinity separation of immunoglobulins comprising the Ig-binding proteins of the present invention, and to methods of using the Ig-binding proteins of the present invention to separate immunoglobulins from mixture compositions. 1. A variant of an immunoglobulin (Ig)-binding protein , said variant comprising the Ig-binding protein having at least one asparagine (Asn) residue in the Ig-binding protein substituted with a histidine (His) , a serine (Ser) , an aspartic acid (Asp) or a threonine (Thr) residue , wherein said at least one substitution confers the variant with increased alkali stability properties when compared to the Ig-binding protein.2. The variant Ig-binding protein of claim 1 , characterized in that said Ig-binding protein is protein A.3. The variant Ig-binding protein of claim 1 , characterized in that said Ig-binding protein comprises an amino acid sequence of SEQ ID NO: 1.4. The variant Ig-binding protein of claim 3 , characterized in that said variant comprises the Ig-binding protein having an Asn3His (asparagine residue at position 3 of SEQ ID. NO: 1 substituted with a histidine residue) substitution or an Asn3Ser substitution.5. The variant Ig-binding protein of claim 3 , characterized in that said variant comprises the Ig-binding protein having an Asn6Asp substitution.6. The variant Ig-binding protein of claim 3 , characterized in that said variant comprises the Ig-binding protein ...

METHOD FOR LOCALIZATION OF BONE MARROW WHITE BLOOD CELLS BASED ON SATURATION CLUSTERING

A saturation clustering-based method for positioning bone marrow white blood cells: first, pre-processing a bone marrow white blood cell image to eliminate partial noise points and simultaneously smooth the image; using K-means clustering to cluster saturation channels of the bone marrow white blood cell image, and select the type of the white blood cells according to a decision tree algorithm; next, eliminating irrelevant areas in a binary image of the white blood cells by means of a morphology processing algorithm, and simultaneously filling in point holes in the white blood cells; and finally, positioning the white blood cells. The present method is simple and effective, and is suitable for a wide range of applications compared to existing threshold-based algorithms, while rendering a final result more accurate by integrating the decision tree algorithm. 1. A method for locating bone marrow white blood cells , comprising the steps of:(1) median filtering a bone marrow white blood cell image to remove some noise;(2) color-converting the median-filtered bone marrow white blood cell image from an RGB (red, green and blue) channel to an HSV (color, saturation, brightness) channel;(3) applying a K-means algorithm to an S-saturation channel, dividing the color-converted image into three parts, and selecting a first part or a first part and a second part to obtain a white blood cell area;(4) calculating average values (H1, H2) of an H channel in the first part and the second part obtained in step (3), and calculating the area ratio of the first part and the second part according to mean points (S1, S2) of the first part and the second part;(5) performing a statistical analysis on multiple images to identify first parts and second parts where white blood cells are included, and recording the values of H1−H2, S1−S2, and area ratios of the identified first parts and the second parts;(6) according to the recorded results in step (5), applying a decision tree algorithm to ...

GATE PAD LAYOUT PATTERNS OF STANDARD CELL HAVING DIFFERENT GATE PAD PITCHES

A layout design usable for manufacturing a standard cell includes a first gate pad layout pattern, a first set of channel structure layout patterns overlapping the first gate pad layout pattern, a second gate pad layout pattern, and a second set of channel structure layout patterns overlapping the second gate pad layout pattern. The first gate pad layout pattern extends along a first direction. The second gate pad layout pattern extends along a second direction. The first set of channel structure layout patterns is arranged into a first number of columns each aligned along the first direction. The second set of channel structure layout patterns is arranged into a second number of columns each aligned along the first direction. The first number and the second number are different. 1. A layout design usable for manufacturing a standard cell , comprising:a first gate pad layout pattern extending along a first direction;a first set of channel structure layout patterns overlapping the first gate pad layout pattern, the first set of channel structure layout patterns being arranged into a first number of columns each aligned along the first direction;a second gate pad layout pattern extending along a second direction; anda second set of channel structure layout patterns overlapping the second gate pad layout pattern, the second set of channel structure layout patterns being arranged into a second number of columns each aligned along the first direction,the first number and the second number being different.2. The layout design of claim 1 , wherein the first number is 2 claim 1 , and the second number is 1.3. The layout design of claim 1 , further comprising:a third gate pad layout pattern extending along the second direction;the first gate pad layout pattern and the third gate pad layout pattern being spaced apart along a second direction, a spacing therebetween being sized sufficient to accommodate a reference gate pad layout pattern, the reference gate pad layout pattern ...

Advanced Metal Connection With Metal Cut

Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. 1. A method for fabricating a conductive interconnection layer of an integrated circuit , comprising:patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit;cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the conductive connector portion at one or more locations between the semiconductor structures; andfabricating a plurality of polysilicon structures comprising patterned polysilicon lines that provide gate structures for a semiconductor device.2. The method of claim 1 , wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit.3. The method of claim 2 , wherein the different layer of the integrated circuit is a polysilicon layer that includes a plurality of polysilicon structures that are separated by a predetermined polysilicon pitch claim 2 , and wherein the conductive connector portion is patterned to extend across multiple polysilicon structures in the polysilicon ...

METHODS FOR PROTEIN TYROSINE PHOSPHORYLATION PROFILING WITH VARIANT SH2 DOMAINS

There is provided method of profiling protein tyrosine phosphorylation of a sample, the method comprising: contacting the sample with an SH2 Superbinder in order to bind pTyr-including peptides contained in the sample with the SH2 Superbinder; isolating the bound pTyr-including peptides from the sample; and identifying the isolated pTyr-including peptides. 1. A method of profiling protein tyrosine phosphorylation of a test sample , the method comprising:contacting the test sample with an SH2 Superbinder in order to bind pTyr-including peptides contained in the test sample with the SH2 Superbinder;isolating the bound pTyr-including peptides from the test sample; andidentifying the isolated pTyr-including peptides.2. The method according to claim 1 , further comprising quantifying the isolated pTyr-including peptides.3. (canceled)4. (canceled)5. The method of claim 1 , wherein the SH2 Superbinder is a variant of a mammalian SH2 domain.6. The method of claim 1 , wherein the SH2 Superbinder is a variant of a Src claim 1 , Grb2 or Fyn SH2 domain.7. The method of claim 1 , wherein the SH2 Superbinder is a triple mutant SH2 variant or a quadruple mutant SH2 domain.8. (canceled)9. The method of claim 1 , wherein the SH2 Superbinder comprises the sequence of SEQ ID NO: 5 claim 1 , 7 claim 1 , 9 claim 1 , 11 claim 1 , 12 claim 1 , 13 claim 1 , 14 or 15.10. The method of claim 1 , wherein the SH2 Superbinder is contained within a fusion protein that comprises one or more additional SH2 Superbinders.11. The method of claim 1 , wherein the SH2 Superbinder is immobilized on a solid support.12. (canceled)13. The method of claim 1 , wherein the sample is obtained from a subject.14. (canceled)15. The method of claim 13 , wherein the sample is serum claim 13 , plasma claim 13 , urine claim 13 , blood claim 13 , tissue or a tissue extract.16. The method of claim 13 , wherein the subject is to be diagnosed with cancer claim 13 , or is known to have cancer.17. The method of claim 16 , ...

INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT

An IC structure includes a first and a second active region, a first multi-gate structure, a first and a second rail. The first and second active region extend in a first direction and are located at a first level. The second active region is separated from the first active region in a second direction. The first multi-gate structure extends in the second direction, overlaps the first active region and the second active region, and is located at a second level different from the first level. The first rail extends in the first direction, overlaps a portion of the first active region, is configured to supply a first supply voltage, and is located at a third level. The second rail extends in the first direction, is located at the third level, is separated from the first rail in the second direction, and is configured to supply a second supply voltage. 1. An integrated circuit structure comprising:a first active region extending in a first direction and being located at a first level;a second active region extending in the first direction, being located at the first level, and being separated from the first active region in a second direction different from the first direction;a first multi-gate structure extending in the second direction, overlapping the first active region and the second active region, and being located at a second level different from the first level;a first rail extending in the first direction, overlapping a portion of the first active region, being configured to supply a first supply voltage, and being located at a third level different from the first level and the second level; anda second rail extending in the first direction, being located at the third level, being separated from the first rail in the second direction, and being configured to supply a second supply voltage different from the first supply voltage.2. The integrated circuit structure of claim 1 , whereinthe first active region has a first width in the second direction, andthe ...

Touch display device and method for sensing capacitance thereof

A touch display device and a method for sensing capacitance thereof are provided. The touch display device includes a display panel having a plurality of liquid crystal pixels, a source driver, a touch panel having a plurality of touch areas, a touch sensing circuit and a crosstalk compensation unit. The source driver writes a plurality of pixel voltages into the liquid crystal pixels according to a plurality of display data. The touch panel is disposed and overlapped with the display panel. The touch sensing circuit senses a capacitance variation amount corresponding to each of the touch areas. The crosstalk compensation unit is coupled to the touch sensing circuit to receive the capacitance variation amount corresponding to each of the touch areas and corrects the capacitance variation amounts according to a plurality of capacitance crosstalk values corresponding to the liquid crystal pixels so as to provide a plurality sensing signals.

RESISTIVE RANDOM ACCESS MEMORY

A resistive random access memory (RRAM) including a substrate, a conductive layer, a resistive switching layer, a copper-containing oxide layer, and an electron supply layer is provided. The conductive layer is disposed on the substrate. The resistive switching layer is disposed on the conductive layer. The copper-containing oxide layer is disposed on the resistive switching layer. The electron supply layer is disposed on the copper-containing oxide layer. 1. A resistive random access memory , comprising:a substrate;a conductive layer disposed on the substrate;a resistive switching layer disposed on the conductive layer;a copper-containing oxide layer disposed on the resistive switching layer; andan electron supply layer disposed on the copper-containing oxide layer, wherein a material of the electron supply layer comprises a copper-titanium alloy, copper titanium nitride, a copper-aluminum alloy, a copper-tungsten alloy, a copper-iridium alloy, copper iridium oxide, a copper-ruthenium alloy, a copper-tantalum alloy, copper tantalum nitride, a copper-nickel alloy, a copper-molybdenum alloy, a copper-zirconium alloy, or indium tin copper oxide.2. The resistive random access memory of claim 1 , wherein the conductive layer comprises a single-layer structure or a multi-layer structure.3. The resistive random access memory of claim 1 , wherein a thickness of the conductive layer is 1 nanometer to 500 nanometers.4. The resistive random access memory of claim 1 , wherein a thickness of the resistive switching layer is 1 nanometer to 100 nanometers.5. The resistive random access memory of claim 1 , wherein a deposition temperature range of the resistive switching layer is 100° C. to 500° C.6. The resistive random access memory of claim 1 , wherein a material of the copper-containing oxide layer comprises copper titanium oxide claim 1 , copper tantalum oxide claim 1 , copper aluminum oxide claim 1 , copper cobalt oxide claim 1 , copper tungsten oxide claim 1 , copper ...

SYSTEM AND METHOD FOR PROVIDING AN INTERFACE FOR A BLOCKCHAIN CLOUD SERVICE

In accordance with an embodiment, described herein is a system and method for implementing a distributed ledger a blockchain cloud service. The blockchain cloud service can include nodes of the distributed ledger and a management console component. The management console component can include a web application running in a script runtime environment, a plurality of backend of APIs for communicating with various nodes of the blockchain cloud service, and a plurality of client APIs configured to be invoked by a client application. The plurality of client APIs uses one or more of the plurality of backend APIs in provisioning the distributed ledger as a blockchain cloud service, and in managing the managing the blockchain cloud service.

ENGINEERING CHANGE ORDER CELL STRUCTURE HAVING ALWAYS-ON TRANSISTOR

A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections. 1. A semiconductor cell structure comprising:a first-type active zone and a second-type active zone each extending in a first direction that is perpendicular to a second direction;a first transistor having a first channel region between two active regions in the first-type active zone;a second transistor having a second channel region between two active regions in the second-type active zone;a third transistor having a third channel region between two active regions in the first-type active zone;a fourth transistor having a fourth channel region between two active regions in the second-type active zone;a first gate-strip, extending in the second direction, intersecting the first-type active zone over the first channel region and intersecting the second-type active zone over the second channel region;a second gate-strip, extending in the second direction, intersecting the first-type active zone over the third channel region and intersecting the second-type active zone over the fourth channel region; a first pair of conductive segments each intersecting the first-type active zone over a corresponding one of the two active regions of the first transistor, a first conductive segment in the first pair being configured to have a first supply voltage;', 'a ...

Advanced Metal Connection With Metal Cut

Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. 1. A method for fabricating a conductive interconnection layer of an integrated circuit , comprising:patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit; andcutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the conductive connector portion at one or more locations between the semiconductor structures.2. The method of claim 1 , wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit.3. The method of claim 2 , wherein the different layer of the integrated circuit is a polysilicon layer that includes a plurality of polysilicon structures that are separated by a predetermined polysilicon pitch claim 2 , and wherein the conductive connector portion is patterned to extend across multiple polysilicon structures in the polysilicon layer.4. The method of claim 3 , further comprising:fabricating via interconnections between the conductive interconnection layer and the ...

Method for generating a layout diagram of a semiconductor device including power-grid-adapted route-spacing

A method of generating a layout diagram of a semiconductor device includes populating a conductive layer M(h) with segment patterns representing corresponding conductive segments in the semiconductor device. The segment patterns including first and second power grid (PG) patterns and first routing patterns, where h is an integer and h≥1. Arranging long axes of the first and second PG patterns and the first routing patterns to extend in a first direction. Arranging the first and second PG patterns to be separated, relative to a second direction, by a PG gap having a midpoint. The second direction being substantially perpendicular to the first direction. Distributing the first routing patterns between the first and second PG patterns and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

INTERCONNECT STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device includes a gate electrode extending in a first direction in a first layer over an active region, a first conductive line extending in the first layer adjacent to the gate electrode, a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer, a second conductive line arranged in a third layer over the second layer, and a conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line. The conductive via is electrically insulated from the first power rail. 1. A semiconductor device , comprising:a gate electrode extending in a first direction in a first layer over an active region;a first conductive line extending in the first layer adjacent to the gate electrode;a first power rail extending in a second direction perpendicular to the first direction in a second layer over the first layer;a second conductive line arranged in a third layer over the second layer; anda conductive via extending through the first power rail and electrically connecting the second conductive line to one of the gate electrode and the first conductive line, wherein the conductive via is electrically insulated from the first power rail.2. The semiconductor device according to claim 1 , further comprising a spacer layer electrically insulating the conductive via from the first power rail.3. The semiconductor device according to claim 2 , wherein spacer layer extends from the first conductive line to the second conductive line.4. The semiconductor device according to claim 2 , wherein the spacer layer is at least partially laterally surrounded by the first power rail.5. The semiconductor device according to claim 1 , further comprising a second power rail arranged in the second layer and parallel to the first power rail.6. The semiconductor device according to claim 5 , wherein the second power rail is ...

Advanced Metal Connection With Metal Cut

Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. 1. A method for fabricating a conductive interconnection layer of a circuit , comprising:patterning a conductive connector portion on the conductive interconnection layer of the circuit; andcutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing a conductive material from the conductive connector portion at at least one locations between a plurality of semiconductor structures.2. The method of claim 1 , wherein the conductive connector portion is patterned to extend across multiple the plurality of semiconductor structures in a different layer of the circuit.3. The method of claim 2 , wherein the different layer of the circuit is a polysilicon layer that includes a plurality of polysilicon structures that are separated by a predetermined polysilicon pitch claim 2 , and wherein the conductive connector portion is patterned to extend across multiple polysilicon structures in the polysilicon layer.4. The method of claim 3 , further comprising:fabricating a plurality of polysilicon structures comprising patterned polysilicon lines that provide gate ...

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The integrated circuit has a first gate. Generating the layout design includes generating a set of gate layout patterns, generating a cut feature layout pattern and generating a first via layout pattern. The cut feature layout pattern extends in a first direction, is located on the first layout level and overlaps at least a first gate layout pattern. The set of gate layout patterns extends in a second direction and is located on a first layout level. The first via layout pattern is over the first gate layout pattern, and is separated in the second direction from the cut feature layout pattern by a first distance. The first distance satisfies a first design rule. 1. A method of forming an integrated circuit , the method comprising: generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction by a first pitch, the set of gate layout patterns extending in a second direction different from the first direction and being located on a first layout level;', 'generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction, being located on the first layout level and overlapping at least a first gate layout pattern of the set of gate layout patterns; and', 'generating a first via layout pattern, the first via layout pattern being over the first gate layout pattern of the set of gate layout patterns, and the first via layout pattern being separated in the second direction from the cut feature ...

Monolithic Base Of LED Lighting Module And Lamp Having The Same

Various examples of an LED lighting module and a lamp having the LED lighting module are described. An LED lighting module may include an LED lighting member, configured to emit light and including at least one LED, and a monolithic base that is substantially cylindrically shaped with a cavity therein. The monolithic base may include a first distal end, a second distal end opposite the first distal end, a top surface located at the first distal end and including a hole intercommunicating with the cavity, and an exterior surface disposed between the first and the second distal ends. The LED lighting member may be disposed on the top surface. The exterior surface may include one or more screw threads thereon. 1. A light-emitting diode (LED) lighting module , comprising:an LED lighting member, configured to emit light and comprising at least one LED; and a first distal end;', 'a second distal end opposite the first distal end;', 'a top surface located at the first distal end and comprising a hole intercommunicating with the cavity,', 'wherein the LED lighting member is disposed on the top surface; and', 'an exterior surface disposed between the first and the second distal ends and including one or more screw threads thereon., 'a monolithic base that is substantially cylindrically shaped with a cavity therein, the monolithic base comprising2. The LED lighting module of claim 1 , wherein the monolithic base is made of metal or ceramic.3. The LED lighting module of claim 1 , wherein the exterior surface of the monolithic base further comprises a plurality of fins configured to dissipate heat from the monolithic base claim 1 , wherein the one or more screw threads are disposed near the first distal end and the plurality of fins are disposed near the second distal end.4. The LED lighting module of claim 1 , wherein the one or more screw threads on the exterior surface are disposed near the first distal end or across the exterior surface between the first distal end and the ...

CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES

A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track. 1. A cell on an integrated circuit , comprising:a fin structure;an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; anda first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track, wherein a first power supply terminal is connected to the first intermediate gate connection metal track, wherein the first intermediate gate connection metal track extends in a first direction, and wherein the first intermediate gate connection metal track extends outside the cell and is connected to a power connecting cell, the power connecting cell being a first neighboring cell of the cell in the first direction.2. The cell of claim 1 , further comprising:a plurality of metal tracks disposed in a first metal (M1) layer above the intermediate gate connection metal layer, wherein no power supply terminal is connected to the plurality of metal tracks.3. The cell of claim 2 , wherein the ...

METHOD AND SYSTEM FOR PIN LAYOUT

A method performed by at least one processor includes selecting a pin in a cell, determining a type of the pin, assigning a first pin access and a second pin access of the pin to a same patterning group at different patterning tracks when the pin is determined to be a cross-track pin, determining whether a pin access of a first pin and a pin access of a second pin disposed adjacent to the first pin in the cell are on a same patterning track, separating the first pin and the second pin from each other by a first predetermined distance when the pin accesses are determined to not be on a same patterning track, and separating the first pin and the second pin from each other by a second predetermined distance when the pin accesses are determined to be on a same patterning track. 1. A method , performed by at least one processor , comprising:selecting a pin in a cell;determining a type of the pin;assigning a first pin access and a second pin access of the pin to a same patterning group at different patterning tracks when the pin is determined to be a cross-track pin;determining whether a pin access of a first pin and a pin access of a second pin disposed adjacent to the first pin in the cell are on a same patterning track;separating the first pin and the second pin from each other by a first predetermined distance when the pin accesses are determined to not be on a same patterning track; andseparating the first pin and the second pin from each other by a second predetermined distance when the pin accesses are determined to be on a same patterning track, the second predetermined distance being smaller than the first predetermined distance.2. The method according to claim 1 , wherein the determining a type of the pin comprises:determining whether the pin extends along a single patterning track; anddetermining the pin to be a cross-track pin when the pin is determined to be extending across more than one patterning tracks.3. The method according to further comprising: ...

INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT

An IC structure includes a cell, a first rail and a second rail. The cell includes a first and a second active region and a first gate structure. The first and second active region extend in a first direction and is located at a first level. The second active region is separated from the first active region in a second direction. The first gate structure extends in the second direction, overlaps the first and second active region, and is located at a second level. The first rail extends in the first direction, overlaps the first active region, is configured to supply a first supply voltage, and is located at a third level. The second rail extends in the first direction, overlaps the second active region, is located at the third level, separated from the first rail in the second direction, and is configured to supply a second supply voltage. 1. An integrated circuit structure comprising: a first active region extending in a first direction and being located at a first level;', 'a second active region extending in the first direction, being located at the first level, and being separated from the first active region in a second direction different from the first direction, and', 'a first gate structure extending in the second direction, overlapping the first active region and the second active region, and being located at a second level different from the first level;, 'a first cell comprisinga first rail extending in the first direction, overlapping the first active region, being configured to supply a first supply voltage, and being located at a third level different from the first level and the second level, anda second rail extending in the first direction, overlapping the second active region, being located at the third level, being separated from the first rail in the second direction, and being configured to supply a second supply voltage different from the first supply voltage.2. The integrated circuit structure of claim 1 , wherein the first cell further ...

ENGINEERING CHANGE ORDER CELL STRUCTURE HAVING ALWAYS-ON TRANSISTOR

A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections. 1. A semiconductor cell structure comprising:a first-type active zone and a second-type active zone each extending in a first direction that is perpendicular to a second direction;a first transistor having a first channel region between two active regions in the first-type active zone;a second transistor having a second channel region between two active regions in the second-type active zone;a third transistor having a third channel region between two active regions in the first-type active zone;a fourth transistor having a fourth channel region between two active regions in the second-type active zone;a first gate-strip, extending in the second direction, intersecting the first-type active zone over the first channel region and intersecting the second-type active zone over the second channel region;a second gate-strip, extending in the second direction, intersecting the first-type active zone over the third channel region and intersecting the second-type active zone over the fourth channel region; a first pair of conductive segments each intersecting the first-type active zone over a corresponding one of the two active regions of the first transistor, a first conductive segment in the first pair being configured to have a first supply voltage;', 'a ...

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The generating of the layout design includes generating a set of active region layout patterns extending in a first direction, generating a set of gate layout patterns extending in a second direction, and generating a cut feature layout pattern extending in the first direction, overlapping at least a first gate layout pattern of the set of gate layout patterns, being separated from the set of active region layout patterns in the second direction by at least a first distance. The first distance satisfying a first design rule of the set of design rules. 1. A system for designing an integrated circuit , the system comprises:a non-transitory computer readable medium configured to store executable instructions; anda processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for: placing a set of gate layout patterns on a first layout level, the set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction, the set of gate layout patterns extending in a second direction different from the first direction;', 'placing a cut feature layout pattern over the set of gate layout patterns, the cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns;', 'placing a first conductive feature layout pattern on a second layout level different from the first layout ...

SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN CONTACT HAVING HEIGHT BELOW GATE STACK

A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region. 1. A method , comprising:arranging a first gate structure extending continuously above a first active region and a second active region of a substrate;arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; andarranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.2. The method of claim 1 , further comprising:arranging a second separation spacer disposed on a second gate structure to isolate an electronic signal transmitted through a third gate via and a fourth gate via that are disposed on the second gate structure.3. The method of claim 2 , wherein the first to fourth gate via are disposed outside a non-active region arranged between the first active region and the ...

Sacubitril intermediate and preparation method thereof

The present invention relates to a sacubitril intermediate and a preparation method thereof. The sacubitril intermediate disclosed herein can be prepared by a deprotection reaction of a compound. In addition, the intermediate can be used as a raw material to synthesize sacubitril.

TOUCH PANEL

A touch panel includes a substrate and an electrode layer. The substrate includes a first substrate region. The electrode layer includes a plurality of first repetitive units sequentially arranged in a first direction on the first substrate region of the substrate. Each of the first repetitive units corresponds to integral pairs of channels of plural pairs of channels and includes a first electrode and a second electrode. The first electrode and the second electrode are electrically independent from each other. The first electrode includes a plurality of first branch regions, and the second electrode includes at least one second branch region. The first branch regions and the at least one second branch region are alternately arranged on the first substrate region of the substrate. Two edges of each of the first repetitive units in the first direction respectively belong to the first branch regions. 1. A touch panel comprising:a substrate comprising a first substrate region; andan electrode layer comprising a plurality of first repetitive units sequentially arranged in a first direction on the first substrate region of the substrate,wherein each of the first repetitive units corresponds to integral pairs of channels of plural pairs of channels and includes a first electrode and a second electrode independent from each other,wherein the first electrode includes a plurality of first branch regions, the second electrode includes at least one second branch region, and the first branch regions and the at least one second branch region are alternately arranged on the first substrate region of the substrate,wherein two edges of each of the first repetitive units in the first direction respectively belong to the first branch regions.2. The touch panel according to claim 1 , wherein each of the first repetitive units comprises one of a first-type repetitive unit corresponding to one pair of the channels and a second-type repetitive unit corresponding to two pairs of the ...

SEMICONDUCTOR DEVICE HAVING FIN STRUCTURE

A method for forming a semiconductor device includes: forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; and forming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure. 1. A method for forming a semiconductor device , comprising:forming a fin structure protruding from a substrate of the semiconductor device;forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a first recess and a second recess;forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the first recess, wherein the first conductive line extends across the fin structure and wraps a portion of the fin structure; andforming a second conductive line in the same layer as the first conductive rail by filling a second conductive material into the second recess, wherein the second conductive line extends across the fin structure and contacts another portion of the fin structure.2. The method of claim 1 , further comprising:forming a second conductive rail on the first conductive rail; andelectrically connecting the second conductive rail to a reference voltage.3. The method of claim 2 , wherein a portion the first conductive line formed within the first recess is covered by the second conductive rail.4. The method of claim 2 , wherein a portion the ...

METHOD FOR DIGITIZING BONE MARROW SMEAR

A method includes: obtaining relevant information of the bone marrow smear; generating a global image; generating a to-be-digitized region, an amount of nucleated cells to be collected, and an amount of megakaryocytes to be classified; digitally labeling the bone marrow smear; scanning the to-be-digitized region by low magnification, labeling and identifying a target observation object; generating a switched image of the scanned region; scanning megakaryocytes by low magnification, and labeling and identifying the scanned megakaryocytes, the amount of the scanned megakaryocytes being the same as the amount of megakaryocytes to be classified; generating images of the scanned megakaryocytes; scanning nucleated cells by oil mirror scanning, and labeling and identifying the scanned nucleated cells, the amount of the scanned nucleated cells being the same as the amount of nucleated cells to be collected; generating images of the scanned nucleated cells; and generating a digital smear of the bone marrow smear. 1. A method for digitizing a bone marrow smear , comprising the steps of:(1) obtaining medical record information related to a bone marrow physical smear;(2) generating a global image of the bone marrow physical smear;(3) generating a to-be-digitized region of the bone marrow physical smear, an amount of nucleated cells to be collected, and an amount of megakaryocytes to be classified;(4) generating a digital label of the bone marrow physical smear;(5) printing and pasting the digital label on a specific area of the bone marrow physical smear that corresponds to the digital label;(6) repeating steps (1) to (5) until all digital labels of the bone marrow physical smear are generated and pasted;(7) loading the bone marrow physical smear with the digital label into a slide box;(8) loading the slide box into an entrance of a bone marrow cell scanning device;(9) transferring the slide box to a loading position of the bone marrow cell scanning device;(10) confirming and ...

INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT

An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region. 1. An integrated circuit structure comprising: a first active region having a first dopant type, extending in a first direction and being located at a first level;', 'a second active region having a second dopant type, extending in the first direction, being located at the first level, and being separated from the first active region in a second direction different from the first direction;', 'a first gate structure extending in the second direction, overlapping at least the first active region or the second active region, and being located at a second level different from the first level;', 'a second gate structure extending in the second direction, overlapping at least a first edge of the first active region or the second active region, and being located at the second level; and', 'a third gate structure extending in the second direction, overlapping at least a second edge of the first active region or the second active region, and being located at the second level;, 'a first cell comprisinga first rail extending in the first direction, overlapping a middle portion of the first active region, being ...

Liquid-phase Oxidative Digestion Method for Radioactively Contaminated Carbon-containing Material

Disclosed is a liquid-phase oxidative decomposition method for radioactively contaminated carbonaceous material, providing a method of oxidizing carbon into a gas in liquid phase to treat radioactively contaminated carbonaceous material. The method comprises the following steps: ball milling a mixture of a molybdenum-containing substance and a carbonaceous material, thermally treating the ball milled mixture, and performing liquid-phase oxidation of the thermally treated mixture. The thermal treatment causes carbon to enter space between molybdenum atoms so as to reduce the particle size of carbon and improve the chemical reactivity of carbon, and an oxidant is then used to oxidize the carbon in the space between molybdenum atoms into a gas in liquid phase, while the molybdenum-containing moiety is converted into a water-soluble substance. The method of has technical effects of mild reaction conditions, low energy consumption, high operation safety, and facilitates the recovery of elements attached to carbonaceous material. 1. A method of oxidative digestion of a radioactively contaminated carbonaceous material in liquid phase , comprising steps of:a) milling a mixture of a molybdenum-containing substance and a carbonaceous material by using a planetary ball mill at a fixed ball mill revolution speed to provide first-stage powders;b) placing the first-stage powders obtained in Step a) into a heating furnace, performing a thermal treatment to the first-stage powders under a flowing gas, and then naturally cooling the first-stage powders to provide second-stage powders; andc) adding the second-stage powders to water, and adding an oxidant, such that such that carbon contained therein is oxidized into a gas, and molybdenum-containing moiety is converted into a water-soluble substance.2. The method of oxidative digestion of a radioactively contaminated carbonaceous material in liquid phase according to claim 1 , wherein a component ratio between the carbonaceous ...

SYSTEM AND METHOD FOR MANAGING A BLOCKCHAIN CLOUD SERVICE

In accordance with an embodiment, described herein is a system and method for implementing a distributed ledger a blockchain cloud service. The blockchain cloud service can include nodes of the distributed ledger and a management console component. The management console component can include a web application running in a script runtime environment, a plurality of backend of APIs for communicating with various nodes of the blockchain cloud service, and a plurality of client APIs configured to be invoked by a client application. The plurality of client APIs uses one or more of the plurality of backend APIs in provisioning the distributed ledger as a blockchain cloud service, and in managing the managing the blockchain cloud service. 1. A system for managing a blockchain cloud service , comprising:a container runtime service; anda distributed ledger and a management console component in the container runtime service; a plurality of client application programming interfaces (APIs) configured to be invoked by a client application, and', 'a plurality of backend APIs for communicating with a plurality of nodes of the distributed ledger,, 'wherein the management console component includeswherein the plurality of client APIs use one or more of the plurality of backend APIs in provisioning the distributed ledger as a blockchain cloud service and in managing the blockchain cloud service.2. The system of claim 1 , wherein the distributed ledger is a Hyperledger Fabric.3. The system of claim 1 , wherein the management console component is implemented as a web application running in a script runtime environment.4. The system of claim 1 , wherein information from one or more of the plurality of nodes is populated into a view object in the management console component claim 1 , wherein the view object is invoked by one or more of the plurality of client APIs to display the information to the client application.5. The system of claim 1 , wherein the client application is one of a ...

SYSTEM AND METHOD FOR PROVIDING AN INTERFACE FOR A BLOCKCHAIN CLOUD SERVICE

In accordance with an embodiment, described herein is a system and method for implementing a distributed ledger a blockchain cloud service. The blockchain cloud service can include nodes of the distributed ledger and a management console component. The management console component can include a web application running in a script runtime environment, a plurality of backend of APIs for communicating with various nodes of the blockchain cloud service, and a plurality of client APIs configured to be invoked by a client application. The plurality of client APIs uses one or more of the plurality of backend APIs in provisioning the distributed ledger as a blockchain cloud service, and in managing the managing the blockchain cloud service. 1. A system for providing an interface for a blockchain cloud service , comprising:at least one instance of a container runtime service; a peer container,', 'an ordering container, and', 'a chaincode container;, 'a distributed ledger component in the at least one instance of the container runtime service, wherein the distributed ledger is provisioned as a blockchain cloud service, the blockchain cloud service comprising;'}wherein the peer container maintains a blockchain ledger;wherein the ordering container orders transactions within the blockchain ledger; andwherein the chaincode container comprises a chaincode execution unit that encodes assets in the ledger;and wherein the at least one instance of the container runtime service is configured to receive an incoming call from a client application, the incoming call requesting an entry into the blockchain ledger.2. The system of claim 1 , wherein the blockchain ledger is a Hyperledger fabric.3. The system of claim 1 , wherein the at least one instance of the container runtime service is associated with a front end load balancer; andwherein the incoming call, prior to being received at the at least one instance of the container runtime service, is passed through the front end load ...

SYSTEM AND METHOD FOR PROVIDING A REPRESENTATIONAL STATE TRANSFER PROXY SERVICE FOR A BLOCKCHAIN CLOUD SERVICE

In accordance with an embodiment, described herein are systems and methods for implementing a distributed ledger a blockchain cloud service. The blockchain cloud service can include nodes of the distributed ledger and a REST proxy service component. The REST proxy service uses a service development kit for the distributed ledger to communicate with the distributed ledger, and can provide REST APIs for use by client applications to query through chaincodes, synchronously or asynchronously invoke transactions through the chaincodes, get transaction statuses, and get BCS proxy versions. The REST proxy service component can authenticate REST calls, and translate the REST calls into remote procedural calls, for use in interfacing with the distributed ledger. The REST proxy service component can further provide REST APIs that support the same functions which are provided by the BCS management console component, and provide a user interface for client applications to consume the BCS instance. 1. A system for providing a representational state transfer (REST) proxy service in a blockchain cloud service , the system comprising:a container runtime service; anda distributed ledger in the container runtime service, wherein the distributed ledger is provisioned as a blockchain cloud service in the container runtime service;a REST proxy service executing in a container of the container runtime service;wherein the REST proxy service includes a plurality of REST application programming interfaces (APIs), which are configured to translate REST calls from client applications into remote procedural calls, for use by the client applications in communicating with the distributed ledger2. The system of claim 1 , wherein the plurality of REST APIs are further configured to enable the client applications to perform one or more of:querying through chaincodes,synchronously or asynchronously invoking transactions through the chaincodes,getting transaction statuses, orgetting version ...

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks. 1. An integrated circuit layout , comprising:a P-type active region and an N-type active region;a plurality of trunks, each trunk of the plurality of trunks is formed substantially side-by-side and is substantially in parallel with each other;a first metal connection; anda second metal connection, the first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region;', 'the second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region;', 'an axis of the first metal connection is substantially in parallel with an axis of the second metal connection;', 'each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection;', 'each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal ...

STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD

A cell, in a semiconductor device, including: first and second active areas in a semiconductor substrate on opposite sides of the first axis; first, third and fifth, and correspondingly collinear second, fourth and sixth, having long axes in a second direction perpendicular to the first direction; the (A) first, third and fifth, and (B) second, fourth and sixth, conductive structures correspondingly overlapping the second active area; the first and second conductive structures correspondingly being centered between the (C) third and fifth, and (D) fourth and sixth, conductive structures; and a seventh conductive structure; the fourth conductive structure being located over first and second gaps between corresponding ones of the third through sixth, conductive structures; and the fourth conductive structure occupying an area which substantially overlaps one of the first and second conductive structures and a corresponding one of the first and second gaps. 1. A semiconductor device , comprising an array of cells , each of the cells in the array comprising: 'the first and second active areas being located on opposite sides of the first axis of symmetry;', 'first and second active areas, in a semiconductor substrate, having corresponding long axes arranged in a first direction parallel to a first axis of symmetry;'} the long axes of corresponding ones of the first through sixth conductive structures being substantially collinear;', '(A) the first, third and fifth conductive structures, and (B) the second, fourth and sixth conductive structures, correspondingly overlapping the first and second active areas;', 'the first and second conductive structures correspondingly being centered between (C) the third and fifth conductive structures, and (D) the fourth and sixth conductive structures; and, 'first, third and fifth, and corresponding second, fourth and sixth, conductive structures having corresponding long axes in a second direction perpendicular to the first direction ...

SYSTEM AND METHOD FOR PROVIDING A REPRESENTATIONAL STATE TRANSFER PROXY SERVICE FOR A BLOCKCHAIN CLOUD SERVICE

In accordance with an embodiment, described herein are systems and methods for implementing a distributed ledger a blockchain cloud service. The blockchain cloud service can include nodes of the distributed ledger and a REST proxy service component. The REST proxy service uses a service development kit for the distributed ledger to communicate with the distributed ledger, and can provide REST APIs for use by client applications to query through chaincodes, synchronously or asynchronously invoke transactions through the chaincodes, get transaction statuses, and get BCS proxy versions. The REST proxy service component can authenticate REST calls, and translate the REST calls into remote procedural calls, for use in interfacing with the distributed ledger. The REST proxy service component can further provide REST APIs that support the same functions which are provided by the BCS management console component, and provide a user interface for client applications to consume the BCS instance. 1. A system for providing a representational state transfer (REST) proxy service in a blockchain cloud service , the system comprising:a computer including one or more microprocessors;a container runtime service running on the computer; anda distributed ledger in the container runtime service, wherein the distributed ledger is provisioned as a blockchain cloud service in the container runtime service;a REST proxy service executing in a container of the container runtime service, wherein the REST proxy service provides access to one or more smart contracts provided within the blockchain cloud service.2. The system of claim 1 , wherein the REST proxy service comprises a plurality of application programming interfaces (APIs).3. The system of claim 2 , wherein each of the one or more smart contracts comprise chaincode deployed on one or more peer nodes of the blockchain cloud service.5. The system of claim 4 ,wherein the interaction with the smart contract is performed synchronously with ...

BULLET SCREEN KEY CONTENT JUMP METHOD AND BULLET SCREEN JUMP METHOD

The present disclosure provides techniques for presenting information associated with bullet screens. The techniques comprise receiving trigger information comprising information of identifying a bullet screen and information of identifying a user who performed a trigger event for the bullet screen; determining a list of jump links associated with the bullet screen based on the information of identifying the bullet screen; determining a tag associated with the user based on the information of identifying the user; selecting a target jump link from the list of jump links based on the tag associated with the user; and transmitting information associated with the bullet screen and comprising the target jump link for display of at least one part of the information in a preset area associated with the bullet screen. 1. A method of presenting information associated with bullet screens , comprising:playing a bullet screen in a predetermined area of a screen, wherein the bullet screen comprises a comment moving across the screen;determining whether a trigger event associated with the bullet screen occurs in the predetermined area of the screen;generating trigger information based on the trigger event and the bullet screen in response to determining that the trigger event occurs, wherein the trigger information comprises information of identifying the bullet screen and information of identifying a user who performed the trigger event;sending the trigger information to a server computing device;obtaining information associated with the bullet screen from the server computing device, wherein the information comprises a target jump link associated with the bullet screen, and the target jump link is determined based on the information of identifying the bullet screen and the information of identifying the user; anddisplaying the information associated with the bullet screen in a preset area associated with the bullet screen, wherein the preset area associated with the bullet ...

RADIO FREQUENCY POWER AMPLIFIER AND DEVICE

A radio frequency power amplifier and a device are disclosed. A first microstrip line and a second microstrip line are coupled, one end of the second microstrip line is an open stub and another end of the second microstrip line is grounded; and the first microstrip line having a first width is connected to a first transmission line having a second width which is wider than the first width. Therefore, some harmonic bands suppression can be implemented independently. Furthermore, the harmonic termination is independent and may not impact one or more fundamental components during matching a network. In addition, it may not take up more space and is sufficiently compact. Furthermore, sufficient wide harmonic response bandwidth can be provided. 1. A radio frequency power amplifier , comprising a harmonic control circuit which comprises at least one edge-coupling resonator;wherein the edge-coupling resonator at least comprises a first microstrip line, a second microstrip line and a first transmission line; the second microstrip line and the first microstrip line are coupled; andone end of the second microstrip line is an open stub and another end of the second microstrip line is grounded; and the first microstrip line having a first width is connected to the first transmission line having a second width which is wider than the first width.2. The radio frequency power amplifier according to claim 1 , wherein the harmonic control circuit is comprised in a conducting pattern; the radio frequency power amplifier further comprises:a planar dielectric substrate;a first conducting layer disposed on a first side of the planar dielectric substrate, anda second conducting layer disposed on a second side of the planar dielectric substrate;wherein the first conducting layer has the conducting pattern; the second conducting layer acts as a ground plane; and the second side of the planar dielectric substrate is opposite to the first side of the planar dielectric substrate.3. The radio ...

METHODS AND COMPOSITIONS FOR TARGETING TGF-ß SIGNALING IN CD4+ HELPER T CELLS FOR CANCER IMMUNOTHERAPY

The present disclosure provides fusion proteins that specifically inhibit transforming growth factor-β (TGF-β) signaling in CD4+ helper T cells, and engineered CD4+ helper T cells that are deficient in TGF-β signaling, to counteract tumor-induced immune tolerance and promote anti-tumor immunity. The fusion proteins and engineered CD4+ helper T cells of the present technology are useful in methods for treating cancer, and enhancing the efficacy of other therapeutic agents against refractory cancer cells. 1. A fusion protein comprising a CD4 targeting moiety fused with an immunomodulatory moiety , wherein:{'sub': H', 'L, 'claim-text': [{'sub': H', 'H', 'H', 'H, '(a) the Vcomprises a V-CDR1 sequence of GYTFTSYVIH (SEQ ID NO: 6), a V-CDR2 sequence of YINPYNDGTDYDEKFKG (SEQ ID NO: 7), and a V-CDR3 sequence of EKDNYATGAWFAY (SEQ ID NO: 8), and'}, {'sub': L', 'L', 'L', 'L', 'H', 'L, '(b) the Vcomprises a V-CDR1 sequence of KSSQSLLYSTNQKNYLA (SEQ ID NO: 2), a V-CDR2 sequence of WASTRES (SEQ ID NO: 3), and a V-CDR3 sequence of QQYYSYRT (SEQ ID NO: 4), optionally wherein the Vcomprises an amino acid sequence that is at least 80%, at least 85%, at least 95%, or 100% identical to SEQ ID NO: 5; and/or the Vcomprises an amino acid sequence that is at least 80%, at least 85%, at least 95%, or 100% identical to SEQ ID NO: 1; and'}], 'the CD4 targeting moiety comprises a heavy chain immunoglobulin variable domain (V) and a light chain immunoglobulin variable domain (V), whereinthe immunomodulatory moiety comprises an amino acid sequence of TGF-β receptor II (TGF-βRII) selected from the group consisting of SEQ ID NOs: 11-12 and 15-17.2. The fusion protein of claim 1 , wherein the CD4 targeting moiety comprises an antibody or an antigen binding fragment that specifically binds a CD4 epitope optionally whereinthe antibody or antigen binding fragment further comprises a Fc domain of an isotype selected from the group consisting of IgG1, IgG2, IgG3, IgG4, IgA1, IgA2, IgM, IgD, and IgE; ...

Semiconductor device including source/drain contact having height below gate stack

Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure are arranged. At least one local interconnect over the non-active region and between two of the gate structures is selectively arranged, to couple at least one of contacts that is arranged above the first active region to at least one of the contacts that is arranged above the second active region.

PHOTOVOLTAIC INVERTER SYSTEM

A photovoltaic inverter system is provided, in which multiple independent inverter units are arranged in a housing, and each of the independent inverter units has independent MPPT function, such that the PV inverter system have multiple MPPT control. In the complex scene such as hills, a maximum power generation of each photovoltaic string can be realized to ensure system energy yield in a case of partial shading or inconsistent orientation. Since independent inverter units are all arranged in the housing, it is convenient for the installation, operation and maintenance. 1. A photovoltaic inverter system , comprising:a transformer,an alternating current combiner device,a communication device,a plurality of independent inverter units, anda multi-channel direct current combiner device, wherein,input terminals of the multi-channel direct current combiner device are connected with a plurality of photovoltaic strings in one-to-one correspondence;the plurality of independent inverter units are arranged in a housing;input terminals of the plurality of independent inverter units are connected with output terminals of the multi-channel direct current combiner device in one-to-one correspondence;output terminals of the plurality of independent inverter units are all connected with an input terminal of the alternating current combiner device;an output terminal of the alternating current combiner device is connected with a low voltage side of the transformer; andone terminal of the communication device is a communication terminal of the photovoltaic inverter system and the other terminal is connected with control terminals of the plurality of independent inverter units.2. The photovoltaic inverter system according to claim 1 , wherein the housing is a box-type casing claim 1 , a house or a container for enclosing the plurality of independent inverter units.3. The photovoltaic inverter system according to claim 1 , wherein the housing is a one-piece platform claim 1 , the one- ...

COORDINATE CALCULATING METHOD AND TOUCH MODULE FOR SINGLE-LAYER CAPACITIVE TOUCH DEVICE

A coordinate calculating method includes acquiring a plurality of first end capacitances and a plurality of second end capacitances corresponding to a plurality of sensing channels of a single-layer capacitive touch device. Differences between the plurality of first end capacitances and a plurality of first baselines are calculated for acquiring a plurality of first differences and calculating differences between the plurality of second end capacitances and a plurality of second baselines for acquiring a plurality of second differences The first difference and the second difference of each sensing channel are added for acquiring a plurality of total capacitances. Whether the single-layer capacitive touch device is pressed is determined according to the plurality of total capacitances and a threshold. A coordinate of at least one touch point is outputted when determining the single-layer capacitive touch device is pressed. 1. A coordinate calculating method for a single-layer capacitive touch device having a plurality of sensing channels , wherein each sensing channel corresponds to at least one sensing pad pair , a first end and a second end , the coordinate calculating method comprising:acquiring a plurality of first end capacitances and a plurality of second end capacitances corresponding to the plurality of sensing channels;calculating differences between the plurality of first end capacitances and a plurality of first baselines for acquiring a plurality of first differences and calculating differences between the plurality of second end capacitances and a plurality of second baselines for acquiring a plurality of second differences;adding the first difference and the second difference corresponding to each sensing channel, for acquiring a plurality of total capacitances; anddetermining whether the single-layer capacitive touch device is pressed according to the plurality of total capacitances and a threshold, and outputting coordinate of at least one touch point ...

Standard cell layout, semiconductor device having engineering change order (eco) cells and method

A method of generating an ECO-layout of an ECO base cell includes: generating first and second active area patterns and arranging them on opposite sides of a first axis; generating non-overlapping first, second and third conductive patterns and arranging each of them so as to correspondingly overlap the first and second active area patterns; locating the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern which overlaps corresponding central regions of the second, and third conductive patterns; aligning the first cut-pattern relative to the first axis; generating a fourth conductive pattern; locating the fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to occupy an area which substantially overlaps a first segment of the first conductive pattern and a first segment of one of the second and third conductive patterns, thereby resulting in the ECO-layout.

METHOD OF MANUFACTURING CONDUCTORS AND SEMICONDUCTOR DEVICE WHICH INCLUDES CONDUCTORS

A method of manufacturing conductors for a semiconductor device, the method comprising: forming a structure on a base; and eliminating selected portions of members of a first set and selected portions of members of a second set from the structure. The structure includes: capped first conductors arranged parallel to a first direction; and capped second conductors arranged parallel to and interspersed with the capped first conductors. The capped first conductors are organized into at least first and second sets. Each member of the first set has a first cap with a first etch sensitivity. Each member of the second set has a second cap with a second etch sensitivity. Each of the capped second conductors has a third etch sensitivity. The first, second and third etch sensitivities are different. 1. A method of manufacturing conductors for a semiconductor device , the method comprising: capped first conductors arranged parallel to a first direction; and', 'capped second conductors arranged parallel to and interspersed with the capped first conductors;, 'forming a structure on a base, the structure including each member of the first set having a first cap with a first etch sensitivity;', 'each member of the second set having a second cap with a second etch sensitivity;', 'each of the second conductors has a third cap with a third etch sensitivity; and', 'the first, second and third etch sensitivities are different from each other; and, 'wherein the capped first conductors are organized into at least first and second sets;'}eliminating selected portions of members of the first set and selected portions of members of the second set from the structure.2. The method of claim 1 , wherein the eliminating includes:removing the first cap from selected portions of members of the first set resulting in first uncapped portions of the first conductors;removing the second cap from selected portions of members of the second set resulting in second uncapped portions of the first conductors ...

CAPACITIVE TOUCH SCREEN AND CONTROL METHOD THEREOF

A capacitive touch screen includes a plurality of touch sensing electrodes and a touch controller. Each of the plurality of touch sensing electrodes includes at least one driving area and at least one receiving area. The at least one driving area and the at least one receiving area are located in a same layer of the capacitive touch screen. The touch controller, electrically connected to the at least one driving area and the at least one receiving area in the plurality of touch sensing electrodes, is utilized for scanning the at least one driving area in order and detecting signals received by the at least one receiving area, or scanning the at least one receiving area in order and detecting signals received by the at least one driving area. 1. A capacitive touch screen , comprising:a plurality of touch sensing electrodes, each comprising at least one driving area and at least one receiving area; anda touch controller, for scanning the at least one driving area in the plurality of touch sensing electrodes in order and detecting signals received by the at least one receiving area in the plurality of touch sensing electrodes, or scanning the at least one receiving area in the plurality of touch sensing electrodes in order and detecting signals received by the at least one driving area in the plurality of touch sensing electrodes;wherein the at least one driving area and the at least one receiving area in the plurality of touch sensing electrodes are located in a same layer of the capacitive touch screen;wherein each of the at least one driving area in the plurality of touch sensing electrodes is electrically connected to the touch controller respectively, and each of the at least one receiving area in the plurality of touch sensing electrodes is electrically connected to each other and then electrically connected to the touch controller.2. The capacitive touch screen of claim 1 , wherein each of the plurality of touch sensing electrodes is a quadrangular electrode ...

SH2 DOMAIN VARIANTS

The present invention relates to variant SH2 domains for binding a phosphotyrosine (pTyr)-containing peptide. The variant SH2 domains of the present invention include a parent SH2 domain having at least one amino acid substitution in a pre-defined region of 15 amino acid positions of the parent SR2 domain, wherein said at least one amino acid substitution increases the affinity of the variant SH2 domain for the pTyr-containing peptide relative to the parent SH2 domain. The present application relates also to methods of using the variant SH2 domains in the treatment of protein kinase-associated disorders, or the diagnosis or prognosis of protein kinase-associated disorders, for isolating and measuring the concentration of pTyr-containing molecules, and as reagents in research. 1. A variant SH2 domain having a binding site for a phosphotyrosine (pTyr)-containing peptide , wherein the variant SH2 domain comprises at least one amino acid substitution in a pre-defined region of 15 amino acid positions of a parent SH2 domain that increases the binding affinity of the variant SH2 domain for the pTyr-containing peptide relative to the parent SH2 domain , and wherein the pre-defined region of 15 amino acids of the parent SH2 domain corresponds to Arg18 (position 1) , Lys19 (position 2) , Ala21 (position 3) , Arg38 (position 4) , Ser40 (position 5) , Glu41 (position 6) , Thr42 (position 7) , Thr43 (position 8) , Ala46 (position 9) , Ser48 (position 10) , Leu49 (position 11) , Ser50 (position 12) , Lys63 (position 13) , His64 (position 14) , and Lys66 (position 15) of SEQ ID NO:1 when said parent SH2 domain is aligned with SEQ ID NO:1.2. (canceled)3. The variant SH2 domain of claim 1 , wherein the at least one substitution includes a substitution to a small or hydrophobic residue at a position in the parent SH2 domain corresponding to position 10.4. The variant SH2 domain of claim 3 , wherein the small or hydrophobic residue includes alanine claim 3 , isoleucine claim 3 , ...

LIGHT ASSEMBLY

A light assembly includes a case, a light member, an adjustment unit and a reflection unit. The light member is located on the support member at the center of the case, and the adjustment unit and the reflection unit are located within the case. The reflection unit includes multiple first reflection members, and multiple second reflection members. The light member is located at the position surrounded by the respective root portions of the first and second reflection members. The first and second reflection members are pivoted relative to the light member when the adjustment unit is operated. 1. A light assembly comprising:a case having a support member at a center thereofa light member connected to the support member;an adjustment unit pivotably connected to an inside of the case, anda reflection unit pivotably connected to the inside of the case and having multiple first reflection members and multiple second reflection members, the light member located at a position surrounded by respective root portions of the first and second reflection members, an angle of the first and second reflection members being adjustable relative to the light member by operation of the adjustment unit.2. The light assembly as claimed in claim 1 , wherein the light member is a Light Emitting Diode.3. The light assembly as claimed in claim 1 , wherein the first and second reflection members are simultaneously moved relative to the light member when the adjustment unit is operated.4. The light assembly as claimed in claim 1 , wherein the case has a first pivotal portion on one of four side thereof claim 1 , two second pivotal portions are located on two of the four sides of the case claim 1 , the first pivotal portion is located between the first pivotal portion claim 1 , the two second pivotal portions are symmetrical relative to the support member claim 1 , the first and second pivotal portions are located on three of the four sides relative to the support member claim 1 , two ...

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INDIVIDUAL IMAGING DEVICE

It is desired to provide technology that enables automatic measurement of the size of a subject with a reduced number of frames of images required, relaxed restrictions on the coverage and light projection, and no limitation on the shape of the subject. Provided is an information processing device including: a depth information acquiring unit configured to acquire depth information; a data conversion unit configured to convert the depth information into three-dimensional data; a subject extraction unit configured to extract a subject area where a subject is present on the basis of the three-dimensional data; and a size measurement unit configured to measure a size of the subject on the basis of the subject area, in which the size measurement unit detects six planes circumscribing the subject area and measures the size of the subject on the basis of the six planes. 1. An information processing device comprising:a depth information acquiring unit configured to acquire depth information;a data conversion unit configured to convert the depth information into three-dimensional data;a subject extraction unit configured to extract a subject area where a subject is present on a basis of the three-dimensional data; anda size measurement unit configured to measure a size of the subject on a basis of the subject area,wherein the size measurement unit detects six planes circumscribing the subject area and measures the size of the subject on a basis of the six planes.2. The information processing device according to claim 1 ,wherein the size measurement unit measures a distance between each of three pairs of parallel planes facing each other as the size of the subject.3. The information processing device according to claim 1 ,wherein the size measurement unit detects a plurality of combinations of six planes circumscribing the subject area, detects six planes having a smallest enclosed volume among the plurality of combinations of six planes, and measures the size of the subject ...

PHENYLEPHRINE RESINATE PARTICLES AND USE THEREOF IN PHARMACEUTICAL FORMULATIONS

Phenylephrine particles suitable for solid, semi solid or liquid dosage forms are disclosed. 1. A drug-resin complex comprising phenylephrine and a cation polystyrene sulfonate , wherein said cation polystyrene sulfonate comprises particle sizes of about 74 μm to about 177 μm prior to being combined with the phenylephrine.2. The drug-resin complex of claim 1 , wherein the cation is selected from the group consisting of sodium claim 1 , copper claim 1 , zinc claim 1 , iron claim 1 , calcium claim 1 , strontium claim 1 , magnesium and lithium.3. The drug-resin complex of claim 2 , wherein the cation is sodium.4. An extended release particle claim 3 , wherein said extended release particle comprises the drug-resin complex of coated with a coating.5. The extended release particle of claim 4 , wherein the coating comprises a cellulose material.6. The extended release particle of claim 5 , wherein the cellulose material is selected from the group consisting of cellulose acetate and hydroxypropylcellulose.7. A pharmaceutical formulation comprising the extended release particle of .8. The pharmaceutical formulation of claim 7 , further comprising an immediate release form of phenylephrine.9. A method of forming a coated drug-resin complex claim 1 , comprising coating the drug-resin complex of .10. The drug-resin complex of claim 1 , wherein at least about 50% of the particles have particle sizes of about 74 μm to about 177 μm.11. The drug-resin complex of claim 10 , wherein at least about 80% of the particles have a particle sizes of about 74 μm to about 177 μm.12. The drug-resin complex of claim 11 , wherein at least about 90% of the particles have a particle sizes of about 74 μm to about 177 μm.13. The drug-resin complex of claim 1 , wherein less than 15% of the particles have a particle size less than about 44 μm. The present invention relates to phenylephrine particles suitable for solid, semi solid or liquid dosage forms. The phenylephrine particles, which may be ...

System for generating standard cell layout having engineering change order (eco) cells

A system (including a processor and memory with computer program code) configured to execute a method which includes generating a layout diagram including: generating first and second active area patterns on opposite sides of (and having long axes parallel to) a first symmetry axis; generating non-overlapping first, second and third conductive patterns (having long axes perpendicular to the first symmetry axis) which overlap the first and second active area patterns; centering the first conductive pattern between the second and third conductive patterns; generating a first cut-pattern for, and which overlaps, central regions of the second and third conductive patterns; centering the first cut-pattern relative to the first symmetry axis; generating a fourth conductive pattern over an area bounded by the first cut-pattern; and expanding the fourth conductive pattern to substantially overlap a portion of the first conductive pattern and a portion of the second or third conductive patterns.

SEMICONDUCTOR DEVICE HAVING FIN STRUCTURE

A semiconductor device includes a fin structure, a first conductive line, a second conductive line and a first conductive rail. The fin structure is disposed on a substrate. The first conductive line is arranged to wrap a first portion of the fin structure. The second conductive line is attached on a second portion of the fin structure. The second portion is different from the first portion. The first conductive rail is disposed in a same layer as the first conductive line and the second conductive line on the substrate. The first conductive rail is attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line. 1. A semiconductor device , comprising:a fin structure, disposed on a substrate;a first conductive line, wrapping a first portion of the fin structure;a second conductive line, attached on a second portion of the fin structure, the second portion being different from the first portion; anda first conductive rail, disposed in a same layer as the first conductive line and the second conductive line on the substrate, the first conductive rail being attached on one end of the first conductive line and one end of the second conductive line for electrically connecting the first conductive line and the second conductive line.2. The semiconductor device of claim 1 , wherein the first conductive line is a polysilicon line and the second conductive line is a metal line.3. The semiconductor device of claim 1 , wherein the first conductive rail extends in a direction parallel to the fin structure.4. The semiconductor device of claim 1 , wherein the one end of the first conductive line and the one end of the second conductive line are contacted with a lateral surface of the first conductive rail.5. The semiconductor device of claim 1 , wherein the first conductive rail is arranged to have a first recess and a second recess claim 1 , and the one end of the ...

Method and system of manufacturing conductors and semiconductor device which includes conductors

A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.

INFRARED SENSOR

An infrared sensor includes a Fresnel lens, a rear casing, a reflecting mirror, a pyroelectric infrared sensor, a sensor circuit board, and a front casing. Therein, the rear casing is combined to the rear side of the front casing to form a sensor casing. The Fresnel lens is engaged on the upper surface of the front casing. The sensor circuit board is internally disposed in the sensor casing, with the pyroelectric infrared sensor installed on the sensor circuit board. The reflecting mirror is disposed on the upper part of the pyroelectric infrared sensor and beneath the Fresnel lens. Therefore, the present invention enlarges the sensing angle from 110 degrees to 220 degrees, such that the sensing scope is enlarged, the blind area is decreased, and the overall utility is enhanced. 1. An infrared sensor , comprising:a Fresnel lens;a rear casing;a reflecting mirror;a pyroelectric infrared sensor,a sensor circuit board; anda front casing,wherein the rear casing is combined to the rear side of the front casing to form a sensor casing, the Fresnel lens is engaged on the upper surface of the front casing, and the sensor circuit board is internally disposed in the sensor casing, with the pyroelectric infrared sensor installed on the sensor circuit board, and the reflecting mirror is disposed on the upper part of the pyroelectric infrared sensor and beneath the Fresnel lens;the Fresnel lens further comprising at least a first area and at least a second area, wherein the pyroelectric infrared sensor directly senses an infrared ray passing through the first area and at the same time senses another infrared ray passing through the second area and reflected by the reflecting mirror.2. The infrared sensor of claim 1 , wherein two outer sides and two ends of the Fresnel lens are provided with a rubber pad claim 1 , respectively.3. The infrared sensor of claim 1 , wherein at least a part of the reflecting mirror is placed on the path of the infrared ray projected from the ...

LIGHT ASSEMBLY

A light assembly includes multiple first units and multiple controller members. Each first unit has multiple light members received therein. Each first unit has two control members connected to two ends thereof. The control members and the power source is electrically connected wirelessly so that the control members controls the operation of the light members. Two control members communicate with each other by a common frequency. Multiple light assemblies are electrically connected to each other by the control members using the common frequency. 1. A light assembly comprising:multiple first units each having multiple light members received therein, each first unit having two ends;multiple second units, each of the two ends of each first unit being connected and sealed with one of the multiple second unit;each second unit including a cylindrical end member, a first control member, multiple plugs, each of the two ends of each first unit being connected with the corresponding second unit by the end member of the corresponding second unit, the end member having a first room and a second room respectively defined in two ends thereof, the first room communicating with the second room, the end member having a third room defined radially therein, the third room communicating with the first room;the first control member received in the first room of the end member and adapted to be charged by a power source by wireless way, the first control member providing power to the light members and turning on or turning off the light members simultaneously, the first control member electrically connected to the light members by wireless way or wired way;the second and third rooms receiving one of the multiple plugs respectively; the plugs received in the second and third rooms being female plugs respectively and electrically connected to the first control member by wireless way or by wired way;each of the first control members being electrically connected to each other wirelessly by ...

SEMICONDUCTOR DEVICE AND LAYOUT METHOD THEREOF

In some embodiments, a semiconductor device comprises a first active region, a second active region, and a conductive metal structure. The second active region is separate from the first active region. The conductive metal structure is arranged to connect the first active region and the second active region. The conductive metal structure includes a first leg, a second leg and a body. The second leg is separate from the first leg and a body extending between and connecting the first leg and the second leg. 1. A semiconductor device , comprising:a first active region;a second active region separate from the first active region; anda conductive metal structure arranged to connect the first active region and the second active region, the conductive metal structure including a first leg, a second leg separate from the first leg, and a body extending between and connecting the first leg and the second leg.2. The semiconductor device as claimed in claim 1 , wherein each of the first leg and the second leg connects the first active region and the second active region.3. The semiconductor device as claimed in claim 1 , wherein one of the first leg and the second leg connects the first active region and the second active region.4. The semiconductor device as claimed in claim 1 , wherein the first leg is connected to one of the first action region and the second active region claim 1 , and the second leg is connected to the other one of the first active region and the second active region.5. The semiconductor device as claimed in claim 1 , wherein a width of the first leg in a first direction is greater than a width of the body in a second direction different from the first direction.6. The semiconductor device as claimed in claim 5 , wherein each of the first leg and the second leg connects the first active region and the second active region.7. The semiconductor device as claimed in claim 5 , wherein one of the first leg and the second leg connects the first active region ...

ILLUMINATION APPARATUS FOR VEHICLE

An illumination apparatus for vehicle is disclosed, which includes an illumination module and a microcontroller. The illumination module includes a circuit base and an LED array which is disposed on the circuit base and includes a plurality of LED packages. Each of the LED packages includes a driver chip, a light source and a packaging structure, in which the driver chip and the light source are disposed. The driver chip is electrically connected to the light source to drive the light source to emit lights. The microcontroller is electrically connected to the LED packages to control the operation of the LED packages. Therefore, lights emitted from the LED packages can form a dynamic or static image; moreover, the light source (LED chip) and the driver chip are in the same packaging structure, so the circuit layout of the circuit base can be simplified. 1. An illumination apparatus for a vehicle , comprising:an illumination module, including a first circuit base and a first LED array, the first LED array being disposed on the first circuit base and comprising a plurality of first LED packages, each of the first LED packages comprising a first driver chip, a first light source and a first packaging structure, the first driver chip and the first light source being disposed within the first packaging structure, and the first driver chip being electrically connected to the first light source so as to drive the first light source to emit light; anda first microcontroller, being electrically connected to the first LED packages so as to control operation of the first driver chips of the first LED packages.2. The illumination apparatus of claim 1 , further comprising a housing module including a base and an outer cover claim 1 , wherein the outer cover is disposed on the base claim 1 , and the illumination module is disposed within the housing module.3. The illumination apparatus of claim 1 , wherein the first light source comprises at least one LED chip claim 1 , and the ...

Authorization Management Method and Apparatus, and Electronic Device

An authorization management method and apparatus, and an electronic device are provided. The method is applicable to a mobile terminal. A display screen of the mobile terminal is a bendable display screen and the display screen simultaneously displays an active authorization application and a passive authorization application. The method includes: monitoring whether the display screen is bent; and in a case that it is monitored that the display screen is bent, sending a first authorization confirmation instruction to the active authorization application such that the active authorization application provides an authorized account for the passive authorization application, and the passive authorization application acquires the authorized account from the active authorization application and performs a login through the account. 1. An authorization management method , applicable to a mobile terminal , a display screen of the mobile terminal being a bendable display screen and the display screen simultaneously displaying an active authorization application and a passive authorization application , the method comprising:monitoring whether the display screen is bent; andin a case that it is monitored that the display screen is bent, sending a first authorization confirmation instruction to the active authorization application such that the active authorization application provides an authorized account for the passive authorization application, and the passive authorization application acquires the authorized account from the active authorization application and performs a login through the account.2. The authorization management method as claimed in claim 1 , whereinthe display screen simultaneously displaying the active authorization application and the passive authorization application comprises: in a case that the display screen is bent in a vertical screen, dividing the display screen into a first screen area and a second screen area based on a bending position, ...

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks. 1. An integrated circuit layout , comprising:a P-type active region and an N-type active region;a plurality of trunks;a first metal connection connected to the P-type active region; anda second metal connection connected to the N-type active region, each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection;', 'each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection; and', 'a first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks., 'wherein'}2. The integrated circuit layout of claim 1 , wherein the first metal connection includes a plurality of jogs claim 1 , and the plurality of jogs extends from a side of the first metal connection opposite the plurality of trunks.3. The integrated circuit layout of claim 2 , further comprising a power supply line extending parallel to the first metal connection claim 2 , wherein the power supply line comprises a plurality of protrusions extending from a surface of the power supply line closest to the first metal connection.4. The integrated circuit layout of claim 3 , wherein the plurality of protrusions is arranged in an alternating fashion with the plurality of jogs in ...

METHOD AND SYSTEM FOR PIN LAYOUT

A computer readable storage medium encoded with program instructions, wherein, when the program instructions is executed by at least one processor, the at least one processor performs a method. The method includes selecting a cell, determining whether a pin has an area smaller than a predetermined area, allowing a pin access of the pin to extend in a corresponding patterning track of the pin access when the pin access when the pin is determined to be having an area smaller than the predetermined threshold, and causing an integrated circuit to be fabricated according to the pin. 1. A computer readable storage medium encoded with program instructions , wherein , when the program instructions is executed by at least one processor , the at least one processor performs a method comprising the steps of:selecting a cell;determining whether a first pin access of a first pin and a second pin access of a second pin disposed adjacent to the first pin in the cell are on a same patterning track;separating the first pin and the second pin from each other by a first predetermined distance when the first pin access and the second pin access are determined to not be on a same patterning track;determining whether a third pin access of a third pin and a fourth pin access of a fourth pin disposed adjacent to the third pin in the cell are on a same patterning track;separating the third pin and the fourth pin from each other by a second predetermined distance when the third pin access and the fourth pin access are determined to be on a same patterning track, the second predetermined distance being less than the first predetermined distance; andcausing an integrated circuit to be fabricated according to the first pin, the second pin, the third pin, and the fourth pin.2. The method according to claim 1 , further comprising:determining whether the first pin, the second pin, the third pin or the fourth pin extends along a single patterning track; anddetermining the first pin, the second pin, ...

BONE MARROW CELL LABELING METHODS AND SYSTEMS

A method and system for labeling bone marrow cells. The method includes: acquiring a specimen image, extracting a cell contour from the specimen image by using an image processing algorithm, and marking the extracted cell contour by a marking frame to obtain a contour cell image; inputting the contour cell image into a classification model to obtain a classified cell image and its corresponding classified cell information; obtaining preset color information and preset name information for preset cell classes, classifying the preset color information according to the preset cell classes to obtain classification color information; and extracting name information and classified color information corresponding to the classified cell image according to the classified cell information of the classified cell image and the classification color information, collectively labeling the classified cell image according to the extracted name information and classified color information, and displaying the collectively labeled classified cell image. 1. A method for labeling bone marrow cells , comprising:acquiring a specimen image, extracting a cell contour from the specimen image by using an image processing algorithm, and marking the extracted cell contour by a marking frame, to obtain a contour cell image of the extracted cell contour;inputting the contour cell image into a classification model to obtain a classified cell image and its corresponding classified cell information;obtaining preset color information and preset name information for preset cell classes, and classifying the preset color information according to the preset cell classes to obtain classification color information; andextracting name information and classified color information corresponding to the classified cell image according to the classified cell information and the classification color information, collectively labeling the classified cell image according to the extracted name information and ...

Structure and method for semiconductor device

A method for forming a semiconductor structure includes following operations. Gate structures are arranged above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure. The first and second active regions are spaced apart by the non-active region. Contacts are arranged above the first and second active regions. At least one gate via is arranged above the first active region or the second active region. The at least one gate via is electrically coupled with the gate structures. At least one local interconnect is selectively arranged over the non-active region, to couple at least one of the contacts above the first active region to at least one of the contacts above the second active region.

GATE PAD LAYOUT PATTERNS FOR MASKS AND STRUCTURES

A layout design of a standard cell for a set of masks includes a first gate pad layout pattern, a second gate pad layout pattern immediately adjacent to the first gate pad layout pattern, and a third gate pad layout pattern immediately adjacent to the second gate pad layout pattern. Each gate pad layout pattern has first and second sides extending along a first direction, the second side further along a second direction than the first side. A first gate pad pitch is a distance between first sides of the first and second gate pad layout patterns and has a value different from that of a second gate pad pitch that is a distance between first sides of the second and third gate pad layout patterns. Each gate pad pattern is usable for forming a gate pad surrounding a set of channel structures. 1. A set of masks corresponding to a layout design of a standard cell , the layout design comprising:a first gate pad layout pattern usable for forming a first gate pad surrounding a first set of channel structures, the first gate pad layout pattern having a first side and a second side extending along a first direction, the second side being further along a second direction than the first side;a second gate pad layout pattern usable for forming a second gate pad surrounding a second set of channel structures, the second gate pad layout pattern having a first side and a second side extending along the first direction, the second side being further along the second direction than the first side, the second gate pad layout pattern being immediately adjacent to the second side of the first gate pad layout pattern, and a first gate pad pitch being a distance from the first side of the first gate pad layout pattern to the first side of the second gate pad layout pattern; anda third gate pad layout pattern usable for forming a third gate pad surrounding a third set of channel structures, the third gate pad layout pattern having a first side and a second side extending along the first ...

APPLICATION PROCESING METHOD AND APPARATUS, STORAGE MEDIUM, AND COMPUTING DEVICE

An application processing method is performed at a computing device, the method including: displaying a first page of a first child application managed by a parent application, the first page of the first child application including a child application jump portal; detecting a child application jump operation corresponding to the first page in response to a user selection of the child application jump portal; presenting, in the first page candidate child application identifiers according to the child application jump operation; determining a child application identifier that is selected from the presented child application identifiers through a user selection operation; and generating, by using a second child application corresponding to the user-selected child application identifier, a second page that is displayed by covering the first page already displayed and that belongs to the second child application. 1. An application processing method , performed by a computing device , the method comprising:displaying a first page of a first child application managed by a parent application, wherein the parent application is a social networking application having a plurality of users and the first child application is hosted by the parent application and accessible to a subset of the plurality of users and the first page of the first child application includes a child application jump portal;detecting a child application jump operation corresponding to the first page in response to a user selection of the child application jump portal;presenting, in the first page, candidate child application identifiers according to the child application jump operation;determining a child application identifier that is selected from the presented child application identifiers through a user selection operation; andgenerating, by using a second child application corresponding to the user-selected child application identifier, a second page that is displayed by covering the first page ...

SH2 DOMAIN VARIANTS

The present invention relates to variant SH2 domains for binding a phosphotyrosine (pTyr)-containing peptide. The variant SH2 domains of the present invention include a parent SH2 domain having at least one amino acid substitution in a pre-defined region of 15 amino acid positions of the parent SR2 domain, wherein said at least one amino acid substitution increases the affinity of the variant SH2 domain for the pTyr-containing peptide relative to the parent SH2 domain. The present application relates also to methods of using the variant SH2 domains in the treatment of protein kinase-associated disorders, or the diagnosis or prognosis of protein kinase-associated disorders, for isolating and measuring the concentration of pTyr-containing molecules, and as reagents in research. 119.-. (canceled)20. A method for preventing or inhibiting the effects of a tyrosine kinase in a cell , the method comprising delivering or introducing a variant SH2 domain into the cell , the variant SH2 domain varying from a parent SH2 domain , so that relative to the parent SH2 domain , the variant SH2 domain comprises a modified phosphotyrosine (pTyr) binding region substituted at at least one amino acid position in a pre-defined region of 15 amino acid positions of the parent SH2 domain , the substituted amino acids increasing the binding affinity of the modified pTyr binding region for a pTyr-containing peptide relative to an unmodified pTyr binding region of the parent SH2 domain.21. The method of claim 20 , wherein the variant SH2 domain is provided within a carrier that allows transportation across the cell.22. The method of claim 20 , wherein the polypeptide is provided as a fused product comprising the polypeptide and a cell membrane penetrating molecule.23. (canceled)24. A method of assessing the presence of pTyr-containing peptides in a sample claim 20 , the method comprising (a) contacting the sample to a variant SH2 domain claim 20 , such that a pTyr-containing peptide/variant ...

HOUSING ASSEMBLY FOR PORTABLE ELECTRONIC DEVICE

A housing assembly for a portable electronic device includes a first body, a second body, a first engaging member, a first resilient member and a first housing. The first body has a first space. The second body is installed to the first body and has a first release hole. The first engaging member is movably located in the first space. The first engaging member has at least one first engaging portion. The first resilient member provides a force to the first engaging member to orient the first engaging member toward the first release hole. The first housing is connected to the second body and has at least one first contact portion. When assembling, the first contact portion contacts the first engaging portion. The force of the first resilient member applied to the first engaging member to firmly connect the first housing to the second body. 1. A housing assembly for a portable electronic device , comprising:a first body having a first side and a second side which is located corresponding to the first side, the first side having a first space;a second body installed to the first body and having a first release hole and at least one first hole which is located corresponding to the first space of the first body;a first engaging member movably located in the first space of the first body and having at least one first engaging portion which is located corresponding to the at least one first hole of the second body, the first engaging member located corresponding to the first release hole of the second body;a first resilient member providing a force to the first engaging member to orient the first engaging member toward the first release hole of the second body; anda first housing connected to the second body and having a first side and a second side, the first side of the first housing having at least one first contact portion which is located corresponding to the at least one first engaging portion of the first engaging member;when assembling, the at least one first ...

LIGHT EMITTING APPARATUS AND LIGHTING MODULE

The present invention provides a light emitting apparatus and a lighting module, comprising: a circuit substrate, a plurality of optical sources and an optical element; the optical element comprises a translucent element and an interference element; the plurality of light sources are arranged on the circuit substrate for lighting the optical element; the optical element is arranged above the plurality of light sources; and the interference element is arranged on the translucent element, which is used to make light emitted from each of the light sources offset interference in a first polarization direction, enhance interference in a second polarization direction, and emit through the translucent element. The light emitting apparatus and the lighting module of the present invention are employed to provide a more diversified optical pattern to the user and improve the user experience. 1. A light emitting apparatus , comprising: a circuit substrate , a plurality of optical sources and an optical element; wherein the optical element comprises a translucent element and an interference element;the plurality of light sources are arranged on the circuit substrate for lighting the optical element;the optical element is arranged above the plurality of light sources; and the interference element is arranged on the translucent element, and the interference element is used to make light emitted from each of the light sources offset interference in a first polarization direction, enhance interference in a second polarization direction, and emit through the translucent element.2. The light emitting apparatus according to claim 1 , wherein a surface of the optical element facing the light sources is curved along the direction away from the light sources.3. The light emitting apparatus according to claim 1 , wherein the interference element is made of micro units with a same direction.4. The light emitting apparatus according to claim 3 , wherein the plurality of light sources are ...

Pegylated Insulin Lispro Compounds

The present invention relates to the field of diabetes. More particularly, the invention relates to PEGylated insulin lispro compounds that are PEGylated with high molecular weight poly(ethylene glycol), are highly soluble at physiological pH, have an extended duration of action, and characterized by pharmacokinetic, pharmacodynamic, and/or activity peak-trough ratios of less than 2. The invention also relates to methods of providing such molecules, to pharmaceutical compositions containing them, and to their therapeutic uses. 133-. (canceled)34. A method of treating hyperglycemia or diabetes in a patient in need of such a treatment , comprising administering to the patient a therapeutically effective amount of a PEGylated insulin lispro compound of the formula: P-[(A)-(B)] , or a pharmaceutically acceptable salt thereof , wherein:A is the A-chain of insulin lispro (SEQ ID NO: 1);B is the B-chain of insulin lispro (SEQ ID NO: 3); andP is a PEG having a molecular weight in the range from about 17.5 kDa to about 40 kDa and is attached via a urethane covalent bond to the epsilon-amino group of the lysine at position 28 of B, and wherein A and B contain a disulfide bond between the cysteine at position 7 of A (SEQ ID NO: 1) and the cysteine at position 7 of B (SEQ ID NO: 3), a disulfide bond between the cysteine at position 20 of A (SEQ ID NO: 1) and the cysteine at position 19 of B (SEQ ID NO: 3), and a disulfide bond between the cysteine at position 6 of A (SEQ ID NO: 1) and the cysteine at position 11 of A (SEQ ID NO: 1).35. The method of claim 34 , wherein the patient is treated for diabetes mellitus.36. The method of claim 34 , wherein the patient is treated for gestational diabetes.37. The method of claim 34 , wherein the PEG has a molecular weight in the range from about 17.5 kDa to about 25 kDa.38. The method of claim 34 , wherein the PEG has a molecular weight of about 20 kDa.39. A method of treating hyperglycemia or diabetes in a patient in need of such a ...

Advanced Metal Connection With Metal Cut

Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures. 1. A method for fabricating a conductive interconnection layer of an integrated circuit , comprising:patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; andcutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the conductive connector portion at one or more locations between the semiconductor structures.2. The method of claim 1 , wherein the different layer of the integrated circuit is a polysilicon layer that includes a plurality of polysilicon structures that are separated by a predetermined polysilicon pitch claim 1 , and wherein the conductive connector portion is patterned to extend across multiple polysilicon structures in the polysilicon layer.3. The method of claim 2 , further comprising:fabricating via interconnections between the conductive interconnection ...

FINGER PRINT DETECTION APPARATUS AND DETECTION METHOD THEREOF

The finger print detection method includes: accessing a part of an input image to generate a checked image; setting a gray level range, wherein each of a gray level of the gray level rang is larger than a minimum gray level and smaller than a maximum gray level; obtaining a detected pixel number of the checked image corresponding to all of the gray levels within the gray level range; and, checking whether the detected pixel number is larger than a product value of a preset ratio and a total pixel number of the checked image or not to determine whether the checked image is a finger print or not. 1. A finger print detection method , comprising:accessing a part of an input image to generate a checked image;setting a gray level range, wherein each of a gray level of the gray level rang is larger than a minimum gray level and smaller than a maximum gray level;obtaining a detected pixel number of the checked image corresponding to all gray levels within the gray level range; andchecking whether the detected pixel number is larger than a product value of a preset ratio and a total pixel number of the checked image or not to determine whether the checked image is a finger print or not.2. The finger print detection method according to claim 1 , wherein step of the obtaining the detected pixel number of the checked image corresponding to all of the gray levels within the gray level range comprises:obtaining a histogram of a plurality of pixel numbers of the checked image corresponding to the all gray levels;selecting the pixel numbers corresponding to the gray levels within the gray level range to generate a plurality of selected pixel numbers; andsumming the selected pixel numbers to generate the detected pixel number.3. The finger print detection method according to claim 1 , further comprising:sensing an image to obtain the input image; andsetting a scan area on the image, and obtaining the checked image according to the scan area.4. The finger print detection method ...

SEMICONDUCTOR DEVICE INCLUDING POWER-GRID-ADAPTED ROUTE-SPACING AND METHOD FOR GENERATING LAYOUT DIAGRAM OF SAME

A semiconductor device includes: a conductive layer M(h) including first and second power grid (PG) segments and first routing segments which are conductive, where h is an integer and h≥1; long axes of the first and second PG segments and the first routing segments extending in a first direction; the first and second PG segments being separated in a second direction by a PG gap having a midpoint, the second direction being substantially perpendicular to the first direction. The first routing segments are distributed: between the first and second PG segments; and substantially uniformly in the second direction with respect to the midpoint of the PG gap. 1. A semiconductor device comprising:a conductive layer M(h) including first and second power grid (PG) segments and first routing segments which are conductive, where h is an integer and h≥1;long axes of the first and second PG segments and the first routing segments extending in a first direction;the first and second PG segments being separated in a second direction by a PG gap having a midpoint, the second direction being substantially perpendicular to the first direction; and between the first and second PG segments; and', 'substantially uniformly in the second direction with respect to the midpoint of the PG gap., 'the first routing segments being distributed2. The semiconductor device of claim 1 , further comprising:a conductive layer M(h−1), below the conductive layer M(h), including third and fourth PG segments and second routing segments which are conductive; andwherein long axes of the third and fourth PG segments extending in the first direction.3. The semiconductor device of claim 2 , further comprising: one or more transistors; and', 'one or more conductive plugs connecting portions of the one or more transistors to corresponding ones of the third and fourth PG segments and the second routing segments in the conductive layer M(h−1)., 'a device layer below the conductive layer M(h−1), the device layer ...

Shooting device, shooting method, and program

The present disclosure relates to a shooting device, a shooting method, and a program capable of suppressing shooting of an image including large blurring due to motion of a camera such that an image with less blurring may be shot. The camera motion is detected, a distribution degree of a trajectory of the camera motion based on a camera motion detection result is calculated to be compared with a predetermined threshold, and start and finish of exposure is controlled on the basis of a comparison result. The present disclosure may be applied to the shooting device.

FINGERPRINT SENSING APPARATUS, AN INTEGRATED SENSOR DEVICE, AND A FINGERPRINT SENSING METHOD

A fingerprint sensing apparatus including an integrated sensor device and a fingerprint sensing circuit is provided. The integrated sensor device includes at least two sensors. The integrated sensor device is configured to sense a fingerprint to obtain two different types of information related to the fingerprint. The fingerprint sensing circuit electrically connected to the integrated sensor device. The fingerprint sensing circuit is configured to drive the integrated sensor device to sense the fingerprint. One of the two different types of information is determined according to the other of the two different types of information. In addition, an integrated sensor device and a fingerprint sensing method are also provided. 1. A fingerprint sensing apparatus , comprising:an integrated sensor device, comprising at least two sensors, and configured to sense a fingerprint to obtain two different types of information related to the fingerprint; anda fingerprint sensing circuit, electrically connected to the integrated sensor device, and configured to drive the integrated sensor device to sense the fingerprint,wherein one of the two different types of information is determined according to the other of the two different types of information.2. The fingerprint sensing apparatus according to claim 1 , wherein the at least two sensors comprise a biometric sensor and a force sensor claim 1 , and the two different types of information comprise a biological feature and a force value of the fingerprint.3. The fingerprint sensing apparatus according to claim 2 , wherein the biometric sensor senses the fingerprint to obtain the biological feature of the fingerprint by biometric sensing pixels thereof.4. The fingerprint sensing apparatus according to claim 2 , wherein the force sensor senses the fingerprint to obtain the force value of the fingerprint claim 2 , and the force sensor is selected from one of a capacitive sensor and a resistive sensor.5. The fingerprint sensing ...

Circuit with combined cells and method for manufacturing the same

In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.

Semiconductor Device Layout

A semiconductor device, comprising at least one active region; at least one MD region formed over a portion of the at least one active region; and at least one gate electrode formed over a portion of the at least one active region different than the portion of the active region where the MD region is formed. The semiconductor device further comprises at least one metal layer over at least a portion of the at least one active region, the at least one metal layer being located on a layer of the semiconductor device, different than the layers on which the at least one MD region and at least one gate electrode are formed. A via is formed over the at least one active region and configured to connect one of the at least one gate electrodes to one of the at least one metal layers. The at least one metal layer is configured to enable the at least one gate electrode to be connected to another at least one electrode and/or at least one MD region. 1. A semiconductor device , comprising:at least one active region;at least one gate electrode located over a portion of the at least one active region;a via located over the at least one active region and configured to connect one of the at least one gate electrodes to another portion of the semiconductor device.2. The semiconductor device of claim 1 , further comprising at least one metal layer over at least a portion of the at least one active region claim 1 , the at least one metal layer being located on a layer of the semiconductor device claim 1 , different than the layer on which the at least one gate electrode is located.3. The semiconductor device of claim 2 , wherein the via is configured to connect the one of the at least one gate electrodes to one of the at least one metal layers.4. The semiconductor device of claim 3 , wherein the at least one metal layer is located over an active region.5. The semiconductor device of claim 2 , further comprising at least one MD region located over a portion of the at least one active ...

DATA SHARING METHOD AND APPARATUS, AND ELECTRONIC DEVICE

The present disclosure relates to the technical field of computers, and particularly relates to a data sharing method and an apparatus, and an electronic device. The method is applied to a mobile terminal. A display screen of the mobile terminal is a bendable display screen. The method includes determining a first application and a second application in the display screen; and in a case that it is detected that the display screen is bent, sharing the first data information of the first application to the second application. 1. A data sharing method , applied to a mobile terminal , a display screen of the mobile terminal being a bendable display screen , the method comprising:determining a first application and a second application in the display screen; andin a case that it is detected that the display screen is bent, sharing first data information of the first application to the second application.2. The data sharing method as claimed in claim 1 , wherein in the case that it is detected that the display screen is bent claim 1 , sharing the first data information of the first application to the second application comprises:determining the first data information, to be shared, of the first application;determining a receiving position where the second application receives the first data information; andin the case that it is detected that the display screen is bent, extracting the first data information from the first application, sending the first data information to the second application, and putting the first data information at the receiving position.3. The data sharing method as claimed in claim 2 , wherein in a case that the receiving position is within a search bar of the second application claim 2 ,the method further comprises:searching according to the first data information in the search bar, and displaying searched content.4. The data sharing method as claimed in claim 1 , wherein in a case that the first data information is text claim 1 ,the method ...

OXIDE DISPERSION-STRENGTHENED ALLOY (ODS), LEAD-FREE AND FREE-CUTTING BRASS AND PRODUCING METHOD THEREOF

Oxide dispersion-strengthened alloy (ODS), lead-free and free-cutting brass and producing method thereof The mass percent of components in the brass are: 52.0%-90.0% of copper, 0.001%-0.99% of phosphorus, 0.15%-0.70% of tin, 0.25%-3.0% of manganese, 0.15%-0.90% of aluminum, 0.10%-1.5% of nickel, 0.191%-0.90% of oxygen, and 0.06%-0.80% of carbon, the ratio of aluminum to oxygen not exceeding 27:24, with the balance being zinc and inevitable impurities, wherein lead is not more than 0.08%. The brass is produced by a powder metallurgy method: brass powder, copper oxide powder, and graphite micro powder are mixed evenly; 0.001%-1.5% of a forming agent is added and mixed evenly with the mixture; and then molded by compression, and sintering are performed before post-treatment. 1. Oxide dispersion-strengthened alloy (ODS) , lead-free and free-cutting brass , wherein the mass percent of components in the brass are: 52.0%-90.0% of copper , 0.001%-0.99% of phosphorus , 0.15%-0.70% of tin , 0.25%-3.0% of manganese , 0.15%-0.90% of aluminum , 0.10%-1.5% of nickel , 0.191%-0.90% of oxygen and 0.06%-0.80% of carbon , and the ratio of aluminum to oxygen not exceeding 27:24 , with the balance being zinc and inevitable impurities , wherein lead is not more than 0.08%.2. The oxide dispersion-strengthened alloy (ODS) claim 1 , lead-free and free-cutting brass of claim 1 , wherein the mass percent of components in the brass are: 54.0%-80.0% of copper claim 1 , 0.01%-0.79% of phosphorus claim 1 , 0.15%-0.60% of tin claim 1 , 0.30%-2.0% of manganese claim 1 , 0.16%-0.80% of aluminum claim 1 , 0.12%-1.3% of nickel claim 1 , 0.20%-0.75% of oxygen claim 1 , and 0.08%-0.70% of carbon claim 1 , the ratio of aluminum to oxygen not exceeding 27:24 claim 1 , with the balance being zinc and inevitable impurities claim 1 , wherein lead is not more than 0.07%.3. The oxide dispersion-strengthened alloy (ODS) claim 2 , lead-free and free-cutting brass of claim 2 , wherein the mass percent of ...

Sacubitril intermediate and preparation method thereof

The present invention relates to a sacubitril intermediate and a preparation method thereof. The sacubitril intermediate disclosed herein can be prepared by a deprotection reaction of a compound. In addition, the intermediate can be used as a raw material to synthesize sacubitril. The method disclosed herein has advantages of easily obtained raw materials, simple preparation process, low cost, environment friendly, and etc., which is very suitable for industrial production.

METHOD AND SYSTEM OF MANUFACTURING CONDUCTORS AND SEMICONDUCTOR DEVICE WHICH INCLUDES CONDUCTORS

A method of generating a layout diagram includes: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes. 1. An arrangement of conductors for manufacturing a semiconductor device , the arrangement comprising:a base including parallel transistor-channel structures arranged in a first direction;first conductors arranged parallel to a second direction and which are capped with corresponding first or second caps, each first cap having a first etch sensitivity, each second cap having a second etch sensitivity, the second direction being orthogonal to the first direction; andsecond conductors arranged parallel to and interspersed with the first conductors and which are capped with third caps, each third cap having a third etch sensitivity; and the first conductors are organized into at least first and second sets; and', 'the first, second and third etch sensitivities being different from each other., 'wherein2. The arrangement of claim 1 , wherein:the transistor-channel structures are fins;the first conductors are drain/source electrodes;the second conductors are gate electrodes; andfor a given region including corresponding sections of one or more of the fins, a corresponding one of the gate electrodes and corresponding ones of drain/source electrodes represent ...

Program operating method and apparatus, computing device, and storage medium

This application provides a program operating method and a related apparatus. The method includes obtaining first operating data of the program from a server, the first operating data comprising at least an instruction for starting the program; executing the first operating data, and displaying a first page of the program according to the first operating data; determining, in response to a second triggering instruction of a control in the first page, a second page identifier corresponding to the control; obtaining second operating data from the server according to the second page identifier if operating data corresponding to the second page identifier is not in the first operating data, the second operating data comprising the operating data corresponding to the second page identifier; and executing the second operating data, and displaying a second page according to the second operating data, the second operating data comprising portions of the program.

SYSTEM AND METHOD FOR MANAGING A BLOCKCHAIN CLOUD SERVICE

In accordance with an embodiment, described herein is a system and method for implementing a distributed ledger a blockchain cloud service. The blockchain cloud service can include nodes of the distributed ledger and a management console component. The management console component can include a web application running in a script runtime environment, a plurality of backend of APIs for communicating with various nodes of the blockchain cloud service, and a plurality of client APIs configured to be invoked by a client application. The plurality of client APIs uses one or more of the plurality of backend APIs in provisioning the distributed ledger as a blockchain cloud service, and in managing the managing the blockchain cloud service. 1. A system for managing a blockchain cloud service , comprising:a computer comprising at least one processor;a container runtime service running on the computer, the container runtime service supporting a plurality of containers;a distributed ledger and a management console running in a container of the plurality of containers;wherein the distributed ledger is provisioned, via the management console, as a blockchain cloud service;wherein the management console comprises a graphical user interface (GUI) framework;wherein the GUI framework provides a set of components used in a web component of the management console for visualizing a set of data associated with the distrusted ledger.2. The system of claim 1 ,wherein the management console comprises a plurality of client application programming interfaces (APIs) and a plurality of backend APIs.3. The system of claim 2 ,wherein provisioning the distributed ledger as a blockchain cloud service comprises starting an ordering node, starting a peer node, and starting a chaincode node.4. The system of claim 3 ,wherein the plurality of client APIs are configured to be invoked by a client application.5. The system of claim 4 ,wherein the plurality of backend APIs are configured to communicate ...

Memory devices and methods for forming the same

A method of forming a memory device includes forming a first electrode; forming a resistive switching layer over the first electrode; forming a dielectric layer over the resistive switching layer; forming a first opening in the dielectric layer, wherein the first opening passes through the dielectric layer and exposes the resistive switching layer; forming a first trench in the dielectric layer, wherein the first trench is directly above the first opening; and forming a second electrode having a step shape in the first opening and the first trench.

Removal of residue from a substrate

A method and an apparatus of removing a particle from a metal plug on a substrate is disclosed. The method comprises introducing a slurry onto the metal layer and polishing the metal layer. A solution comprising hydrogen peroxide is introduced onto the metal plug and at least one particle is removed from the metal plug.

Removal of residue from a substrate

A method and an apparatus of removing a particle from a metal layer over a substrate is disclosed. The method comprises introducing a slurry onto the metal layer and polishing the metal layer. A solution comprising hydrogen peroxide is introduced onto the metal layer and at least one particle is removed from the metal layer.

PEGYLED INSULIN-LISPRO COMPOUNDS

Modified release dosage forms

A dosage form comprises: (a) a core comprising at least one active ingredient; and (b) a molded shell which surrounds the core, wherein the shell provides a predetermined time delay of greater than one hour for the onset of dissolution of the active ingredient upon contacting of the dosage form with a liquid medium and the delay is independent of the pH of the liquid medium. The weight of the shell may be at least 50 percent of the weight of the core, and the shell may have a thickness of about 500-4000 microns, or be substantially free of pores having a diameter of 0.5 to 5 microns.

Stable insulin preparations

The present invention provides a monomeric insulin analog formulation stabilized against aggregation in which the buffering agent is either TRIS or arginine. The stable formulations of the present invention are useful for treating diabetes, and are particularly advantageous in treatment regimes requiring lengthy chemical and physical stability, such as, in continuous infusion systems.

Lighting apparatus and light emitting diode device thereof

Lighting apparatus and light emitting diode device thereof

A lighting emitting diode (LED) device includes a first adjust module and a second adjust module. The first adjust module includes at least one first LED and has a first internal impedance having a first characteristic curve. A range covered by the first characteristic curve includes a first incomplete conduction region and a first conduction region. As the current increases from zero value and up, the first internal impedance decreases exponentially in the first incomplete conduction region, is approximately linear in the first conduction region. The second adjust module includes an impedance-providing component and an electronic component coupled in series. The second adjust module is coupled in parallel with the first adjust module. The second adjust module has a second internal impedance having a second characteristic curve. The first characteristic curve and the second characteristic curve match one another.

Pegylated insulin lispro compounds

Osmotic tablet with a compressed outer coating

The present invention features a method of manufacturing an osmotic tablet including the steps of (i) compressing a tablet core including a first pharmaceutically active agent and a hydrophilic polymer; (ii) applying an osmotic coating to the outer surface of the tablet core to form a coated tablet, wherein the osmotic coating includes at least one opening exposing the tablet core; and (iii) compressing an immediate release coating onto the surface of the coated tablet, wherein the release coating includes a second pharmaceutically active agent.

Cement surface grinding device

A cement surface grinding device includes a central disk which is extended upwards with a central shaft; the central disk being rotary with respect to the central shaft; at least one outer rotary disk arranged around the central disk; a bottom of the outer rotary disk being installed with a grinding sheet; and a rotary frame arranged above the central disk and the at least one outer rotary disk; the rotary frame including a connecting frame and a plurality of connecting rods; an upper side of the central shaft being connected to a central hole of a seat and the seat being connected to a lower side of the connecting frame; each outer rotary disk being formed with an outer belt wheel and the central disk being formed with a connecting element; and a belt winding around the connecting element and the outer belt wheel.