SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first substrate; a first adhesive layer disposed on a surface of the first substrate; and a first bonding layer disposed on a surface of the first adhesive layer. A density of the first adhesive layer is greater than a density of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and first bonding layer, such that it is advantageous to improve a performance of the semiconductor structure. 1. A semiconductor structure , comprising:a first substrate;a first adhesive layer disposed on a surface of the first substrate; anda first bonding layer disposed on a surface of the first adhesive layer, wherein a density of the first adhesive layer is greater than a density of the first bonding layer.2. The semiconductor structure of claim 1 , wherein the first bonding layer comprises a dielectric material comprising carbon (C).3. The semiconductor structure of claim 2 , wherein the first bonding layer further comprises silicon (Si) and nitrogen (N).4. The semiconductor structure of claim 1 , wherein the first adhesive layer comprises at least one of silicon nitride claim 1 , silicon oxynitride and silicon oxide.5. The semiconductor structure of claim 1 , wherein a thickness of the first adhesive layer ranges from 30 Å to 100 Å.6. The semiconductor structure of claim 2 , wherein an atomic concentration of the carbon is uniform in the first bonding layer claim 2 , or the atomic concentration of the carbon is increased as a thickness of the first bonding layer is increased.7. The semiconductor structure of claim 1 , further comprising a second substrate claim 1 , wherein a second adhesive layer and a second bonding layer disposed on a surface of the second adhesive layer are formed on a surface of the second substrate claim 1 , a density of the second adhesive layer is ...

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first substrate; a first adhesive layer disposed on the surface of the first substrate; a first buffer layer disposed on the surface of the first adhesive layer; and a first bonding layer disposed on the surface of the first buffer layer, wherein the densities of the first adhesive layer and the first buffer layer are greater than that of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and the first buffer layer, and the first buffer layer and the first bonding layer exhibit higher adhesion, which are beneficial to improve the performance of the semiconductor structure. 1. A semiconductor structure , comprising:a first substrate;a first adhesive layer disposed on a surface of the first substrate;a first buffer layer disposed on a surface of the first adhesive layer; and 'the first adhesive layer and a density of the first buffer layer are both greater than a density of the first bonding layer.', 'a first bonding layer disposed on a surface of the first buffer layer, wherein a density of'}2. The semiconductor structure of claim 1 , wherein a material of the first bonding layer and a material of the first buffer layer comprise a dielectric material comprising carbon (C) claim 1 , and an atomic concentration of carbon in the first bonding layer is greater than an atomic concentration of carbon in the first buffer layer.3. The semiconductor structure of claim 2 , wherein the atomic concentration of carbon in the first bonding layer is greater than 35% claim 2 , and the atomic concentration of carbon in the first buffer layer is in a range from 0% to 50%.4. The semiconductor structure of claim 2 , wherein the atomic concentration of carbon in the first bonding layer is increased as a thickness of the first bonding layer is increased claim 2 , and the atomic concentration of carbon in ...

Semiconductor structure and method of forming the same

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding.

Method of forming semiconductor structure

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding.

THROUGH ARRAY CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit. 1. A three-dimensional (3D) NAND memory device , comprising: a first region including an alternating dielectric stack comprising a plurality of dielectric layer pairs, and', 'a second region including an alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs;, 'an alternating layer stack disposed on a substrate, the alternating layer stack comprisinga barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region; anda plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, wherein at least one of the plurality of through array contacts is electrically connected with at least one peripheral circuit.2. The memory device of claim 1 , further comprising:a plurality of slit structures each extending vertically through the alternating conductor/dielectric stack and laterally along a word line direction to divide the alternating conductor/dielectric stack into a plurality of memory fingers.3. The memory device of claim 2 , wherein:the barrier structure laterally extends along the word line direction; andthe first region is ...

BONDING CONTACTS HAVING CAPPING LAYER AND METHOD FOR FORMING THE SAME

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact and the second bonding contact includes a capping layer at the bonding interface and having a conductive material different from a remainder of the respective first or second bonding contact. 1. A semiconductor device , comprising:a first semiconductor structure comprising a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and comprising a first bonding contact;a second semiconductor structure comprising a second device layer, and a second bonding layer disposed below the second device layer and comprising a second bonding contact; anda bonding interface between the first semiconductor structure and the second semiconductor structure,wherein the first bonding contact is in contact with the second bonding contact at the bonding interface, andat least one of the first bonding contact and the second bonding contact comprises a capping layer at the bonding interface having a conductive material different from a remainder of the respective first or second bonding contact.2. The semiconductor device of claim 1 , wherein the conductive material of the capping layer comprises cobalt claim 1 , and the remainder ...

JOINT OPENING STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole. 1. A method of forming a joint opening structure in a three-dimensional (3D) memory device , comprising:forming a first stacked layer on a substrate;forming a first through hole penetrating the first stacked layer to expose the substrate;forming a first channel structure at a bottom of the first through hole and in contact with the substrate;forming a second channel structure in the first through hole and in contact with the first channel structure;forming a third channel structure above the first through hole and in contact with the second channel structure, wherein a size of the third channel structure along a lateral direction is larger than a top aperture of the first through hole;forming a second stacked layer over the third channel structure;forming a second through hole penetrating the second stacked layer to expose the third channel structure;forming a fourth channel structure in the second through hole and in contact with the third channel structure; andforming a fifth channel structure above the second through hole and in contact with fourth channel ...

JOINT OPENNING STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole. 1. A method of forming a joint opening structure in a three-dimensional (3D) memory device , comprising:forming a first stacked layer and forming a first insulating connection layer on the first stacked layer;forming a first through hole that penetrates the first stacked layer and the first insulating connection layer;forming a first channel structure overlaying the surface of the substrate that is exposed by the first through hole;forming a first functional layer on the sidewall of the first through hole;forming a second channel structure and forming a first filling structure on the sidewall of the first functional layer and the exposed surface of the first channel structure;forming a third channel structure in contact with the second channel structure above the first through hole, wherein a projection of the third channel structure on the substrate covers a projection of the first through hole on the substrate;forming a second stacked layer and forming a second insulating connection layer on the first insulating connection layer;forming a second through hole that ...

Bonding contacts having capping layer and method for forming the same

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. A first capping layer is formed at an upper end of the first bonding contact. The first capping layer has a conductive material different from a remainder of the first bonding contact. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact by the first capping layer.

THROUGH ARRAY CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit. 1. A three-dimensional (3D) memory device , comprising:an alternating dielectric stack comprising a plurality of dielectric layer pairs arranged in a vertical direction;an alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs arranged in the vertical direction; andat least one through array contact extending through the alternating dielectric stack in the vertical direction and electrically connecting to a peripheral circuit;wherein the alternating dielectric stack is sandwiched and separated from the alternating conductor/dielectric stack by two parallel barrier structures extending laterally along a word line direction.2. The memory device of claim 1 , wherein:no barrier structure connects the two parallel barrier structures along a bit line direction.3. The memory device of claim 1 , further comprising:a first substrate with an interconnection structure;a second substrate disposed on the first substrate;wherein the at least one through array contact extends through the second substrate and connects to the interconnection structure.4. The memory device of claim 1 , wherein:the alternating dielectric stack and the barrier structures are located in a staircase region.5. The ...

THROUGH ARRAY CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit. 1. A three-dimensional (3D) memory device , comprising:an alternating dielectric stack comprising a plurality of dielectric layer pairs arranged in a vertical direction;an alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs arranged in the vertical direction;a barrier structure located between the alternating dielectric stack and the alternating conductor/dielectric stack in a lateral direction; andat least one through array contact extending through the alternating dielectric stack in the vertically direction and electrically connecting to a peripheral circuit.2. The memory device of claim 1 , further comprises:a plurality of channel structures extending through the alternating conductor/dielectric stack in the vertically direction.3. The memory device of claim 2 , further comprising:a plurality of dummy channel structures each extending vertically through the alternating conductor/dielectric stack, wherein the plurality of dummy channel structures are located between the plurality of channel structures and the barrier structure.4. The memory device of claim 1 , wherein the barrier structure comprises silicon oxide and silicon nitride.5. The memory device of claim 1 , wherein ...

Semiconductor processing apparatus and control method thereof

This invention relates to a semiconductor processing apparatus and a control method thereof. The semiconductor processing apparatus includes a processing chamber including two or more reaction regions. Each of the reaction regions includes an independent gas path module. The control method includes: cycle periods of introducing gas into the reaction regions are synchronized during the semiconductor processing. The semiconductor processing apparatus and the control method thereof of this invention can control the cycle periods of the reaction gas introduced into the reaction regions to be in consistent, so that the gas introduced into different reaction regions is the same at the same time, and the interference of the gas between the reaction regions is avoided, thereby improving the product yield.

Through array contact structure of three-dimensional memory device

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Bonding contacts having capping layer and method for forming the same

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact and the second bonding contact includes a capping layer at the bonding interface and having a conductive material different from a remainder of the respective first or second bonding contact.

Joint opening structures of three-dimensional memory devices and methods for forming the same

Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

Through array contact structure of three-dimensional memory device

Through array contact structure of three-dimensional memory device

A three-dimensional (3D) memory device includes a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack. The first stack includes first and second dielectric layers arranged alternately in a vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes an unclosed shape.

Through array contact structure of three-dimensional memory device

Embodiments of through array contact structures of a 3D memory device is disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Through array contact structure of three-dimensional memory device

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Semiconductor devices

A semiconductor device includes a first stacked layer, an insulating layer disposed over the first stacked layer, a second stacked layer disposed over the insulating layer, a channel structure extending through the second stacked layer, the insulating layer and the first stacked layer, a first filling structure, and a second filling structure. The channel structure includes a first channel structure extending through the first stacked layer, a second channel structure extending through the second stacked layer, and a third channel structure disposed in the insulating layer and in contact with the first and second channel structures. A size of the third channel structure in a first direction is larger than a size of the first channel structure in the first direction. The first direction is perpendicular to a stacking direction of the first stacked layer. The first filling structure is in contact with an inner surface of the first channel structure. The second filling structure is in contact with the first filing structure and an inner surface of the second channel structure.

Bonding contacts having capping layer and method for forming the same

In an example, a semiconductor device includes a first semiconductor structure including a memory array device, a second semiconductor structure including a peripheral device, and a bonding structure comprising a first bonding pad, a second bonding pad, and a remainder layer located between and in contact with the first and second bonding pad in a vertical direction. The first bonding pad is located between the remainder layer and the first semiconductor structure in the vertical direction. The second bonding pad is located between the remainder layer and the second semiconductor structure in the vertical direction. A conductive material of the remainder layer is cobalt metal different from the first and second bonding pads.