Voltage adjustment based on pending refresh operations

Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

METHODS FOR TUNING COMMAND/ADDRESS BUS TIMING AND MEMORY DEVICES AND MEMORY SYSTEMS USING THE SAME

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

Transmitting data signals on separate layers of a memory module, and related methods, systems and apparatuses

Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).

FIELD SUPPRESSED METAL GAPFILL

Embodiments of the disclosure relate to methods for bottom-up metal gapfill without substantial deposition outside of the feature. Additional embodiments provide a method of forming a metal material on the top surface of the substrate and the bottom of the feature before depositing the metal gapfill. The disclosed methods

System and method for automated software engineering

Systems and methods for automated software engineering are disclosed. A particular embodiment is configured to: establish a data connection with a software code repository; provide a collection of autonomous computer programs or bots configured to automatically perform a specific software development life cycle (SDLC) task; use a first bot of the collection of bots to perform an automatic code review of a software module from the software code repository; use a second bot of the collection of bots to perform automatic unit testing of the software module from the software code repository; and use a third bot of the collection of bots to perform an automatic deployment of the software module from the software code repository. A health engine module can monitor the execution of the other software modules and capture execution metrics. Any of the bots in the bot collection can be machine learning models trained using training data.

TRANSMITTING DATA SIGNALS ON SEPARATE LAYERS OF A MEMORY MODULE, AND RELATED METHODS AND APPARATUSES

Apparatuses and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane.

CONFORMAL MOLYBDENUM DEPOSITION

Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include forming a nucleation layer directly on a dielectric layer on a substrate surface by exposing the substrate surface to a molybdenum-containing precursor and a nucleation reactant, and conformally depositing a molybdenum film on the nucleation layer. Another aspect of the disclosure pertains to a method that is part of a gap fill process, comprising forming a nucleation layer directly on a dielectric region within one or more high aspect ratio gap features, including vertical gap features and/or horizontal gap features, and conformally depositing a molybdenum film on the nucleation layer to fill the feature.

MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARYING PHYSICAL DIMENSIONS, MEMORY FORMATS, AND OPERATIONAL CAPABILITIES

An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices. 1. An apparatus comprising:a plurality of memory devices; memory interface circuitry, and', 'at least one first-in first-out (FIFO) circuit or multiplexer circuit; and, 'a buffering device including a plurality of independent control lines, each of the plurality of independent control lines operably coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices, and', 'a plurality of independent data channels, each of the plurality of independent data channels operably coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices., 'a parallel bus operably connecting the buffering device to the plurality of memory devices, the parallel bus including2. The apparatus of claim 1 , wherein each of the first subsets of the plurality of memory devices includes memory devices of a single memory type.3. The apparatus of claim 1 , wherein each of the second subsets of the plurality of memory devices includes memory ...

TRANSMITTING DATA SIGNALS ON SEPARATE LAYERS OF A MEMORY MODULE, AND RELATED METHODS, SYSTEMS AND APPARATUSES

Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).

METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

High power laser flat panel workpiece treatment system controller

A pulsed DUV workpiece treatment apparatus and method for delivering light to irradiate the workpiece, for crystallization of a material on the workpiece, carried on a work stage, which may comprise a pulsed laser DUV light source and an optical train producing a very narrow width very elongated beam of light pulses with a set of parameters required to be maintained within a respective selected narrow range of values on a pulse to pulse basis is disclosed, which may comprise: a laser controller; a work stage controller; a system controller receiving process recipe control demands from a customer recipe control command generator and providing control signals to the laser controller and the workstage controller, which may comprise: a database driven process controller which may comprise: a database containing generic process command steps selectable by a user through an external process user interface.

TUBULAR HEAT SPREADERS FOR MEMORY MODULES AND MEMORY MODULES INCORPORATING THE SAME

Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. An apparatus may have a printed circuit board (PCB) having an edge connector. At least one integrated circuit device may be disposed on a surface of the PCB. A tubular heat spreader may be disposed along an edge of the PCB opposite the edge connector.

Pre-emphasis for strobe signals in memory device

A memory device has a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals representing timing information of the data. The strobe terminals have a fixed signal level in an inactive mode of the memory device. The memory further includes a controller for reducing any signal instability of the strobe signals when the memory device switches from the inactive mode to a data transfer mode.

PRE-EMPHASIS FOR STROBE SIGNALS IN MEMORY DEVICE

Some embodiments of the invention include a memory device having a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals representing timing information of the data. The strobe terminals have a fixed signal level in an inactive mode of the memory device. The memory further includes a controller for reducing signal instability of the strobe signals when the memory device switches from the inactive mode to a data transfer mode. Other embodiments are described and claimed.

CONFORMAL MOLYBDENUM DEPOSITION

Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include converting an amorphous silicon layer to a metal layer by thermally soaking the amorphous silicon layer comprising silicon atoms in the presence of a metal compound selected from the group consisting of a molybdenum compound and a tungsten compound until at least a portion of the silicon atoms in the amorphous silicon layer are replaced by metal atoms selected from the group consisting of molybdenum atoms and tungsten atoms. The methods include conformally depositing a molybdenum film on the metal layer.

Memory modules and memory packages including graphene layers for thermal management

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

TUBULAR HEAT SPREADERS FOR MEMORY MODULES AND MEMORY MODULES INCORPORATING THE SAME

Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. For example, a memory module may have a printed circuit board (PCB) having an edge connector, a plurality of memory devices disposed on a surface of the PCB, and a tubular heat spreader disposed along an edge of the PCB opposite the edge connector. The tubular heat spreader may comprise a tubular portion open at both ends thereof to permit the through flow of a cooling gas; and two planar elements extending in parallel away from the tubular portion and configured to provide a friction fit with the memory module. Each of the planar elements may be configured to convey thermal energy from the memory module to the tubular portion.

Pre-emphasis for strobe signals in memory device

A memory device has a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals representing timing information of the data. The strobe terminals have a fixed signal level in an inactive mode of the memory device. The memory further includes a controller for reducing any signal instability of the strobe signals when the memory device switches from the inactive mode to a data transfer mode.

Pre-emphasis for strobe signals in memory device

Some embodiments of the invention include a memory device having a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals representing timing information of the data. The strobe terminals have a fixed signal level in an inactive mode of the memory device. The memory further includes a controller for reducing signal instability of the strobe signals when the memory device switches from the inactive mode to a data transfer mode. Other embodiments are described and claimed.

ESD protection circuit for a switching power converter

An ESD protection circuit for a switching power converter which includes a high-side switching element connected between a supply voltage and the switching node, and a low-side switching element connected between the switching node and a common node. A current conduction path couples an ESD event that occurs on the switching node to an ESD sense node, and an ESD sensing circuit coupled to the sense node generates a trigger signal when an ESD event is sensed. A first logic gate keeps the high-side switching element off when the trigger signal indicates the sensing of an ESD event, and a second logic gate causes the low-side switching element to turn on when an ESD event is sensed such that the low-side switching element provides a conductive discharge path between the switching node and common node.

Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Methods for memory power management and memory devices and systems employing the same

Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

PLASMA-ENHANCED MOLYBDENUM DEPOSITION

Embodiments of the disclosure are directed to methods of depositing a molybdenum film directly on a substrate surface (e.g., a low-K dielectric material) by exposing the substrate surface to a molybdenum-containing precursor and a plasma at a temperature of less than or equal to 400° C. The molybdenum-containing precursor comprises one or more of molybdenum pentachloride (MoCl 5 ), molybdenum dioxide dichloride (MoO 2 Cl 2 ), molybdenum oxytetrachloride (MoOCl 4 ), molybdenum hexacarbonyl, bis(tert-butylimido)-bis(dimethylamido)molybdenum, or bis(ethylbenzene) molybdenum. The plasma comprises one or more of hydrogen (H 2 ), nitrogen (N 2 ), or a silane (Si x H y ). In some embodiments, when the molybdenum-containing precursor comprises molybdenum hexafluoride (MoF 6 ), the plasma does not include hydrogen (H 2 ).

Methods for tuning command/address bus timing and memory devices and memory systems using the same

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARYING PHYSICAL DIMENSIONS, MEMORY FORMATS, AND OPERATIONAL CAPABILITIES

An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Automatic facial animation using an image of a user

In one embodiment, a method for facial animation is provided. The method first determines an image of a user. Facial feature information for a facial region is then detected in the image. For example, a number of points around the face for a user are determined. The facial region is then normalized based on the content and the facial feature information. The normalized facial region is then animated into a series of animated facial images. These series of animated facial images may be automatically inserted in the content. Accordingly, an image of a user's face may be automatically inserted into the content from the image of the user using the above method. The content may then be played where the animated series of facial images is included in the content being played.

MEMORY MODULES AND MEMORY PACKAGES INCLUDING GRAPHENE LAYERS FOR THERMAL MANAGEMENT

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

High power laser flat panel workpiece treatment system controller

A pulsed DUV workpiece treatment apparatus and method for delivering light to irradiate the workpiece, for crystallization of a material on the workpiece, carried on a work stage, which may comprise a pulsed laser DUV light source and an optical train producing a very narrow width very elongated beam of light pulses with a set of parameters required to be maintained within a respective selected narrow range of values on a pulse to pulse basis is disclosed, which may comprise: a laser controller; a work stage controller; a system controller receiving process recipe control demands from a customer recipe control command generator and providing control signals to the laser controller and the workstage controller, which may comprise: a database driven process controller which may comprise: a database containing generic process command steps selectable by a user through an external process user interface.

INTEGRATED CLEANING AND SELECTIVE MOLYBDENUM DEPOSITION PROCESSES

Embodiments of the disclosure advantageously provide in situ selectively deposited molybdenum films having reduced resistivity and methods of reducing or eliminating lateral growth of a selectively deposited molybdenum layer. Additional embodiments provide integrated clean and deposition processes which improve the selectivity of in situ selectively deposited molybdenum films on features, such as a via. Further embodiments advantageously provide methods of improving uniformity and selectivity of bottom-up gap fill for vias with improved film properties.

Tubular heat spreaders for memory modules and memory modules incorporating the same

Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. An apparatus may have a printed circuit board (PCB) having an edge connector. At least one integrated circuit device may be disposed on a surface of the PCB. A tubular heat spreader may be disposed along an edge of the PCB opposite the edge connector.

MEMORY DEVICES, MODULES AND SYSTEMS HAVING MEMORY DEVICES WITH VARYING PHYSICAL DIMENSIONS, MEMORY FORMATS, AND OPERATIONAL CAPABILITIES

An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

SYSTEM AND COMPUTER PROGRAM FOR PROVIDING AUTOMATED ACTIONS AND CONTENT TO ONE OR MORE WEB PAGES RELATING TO THE IMPROVED MANAGEMENT OF A VALUE CHAIN NETWORK

A system, computer program product and system for providing automated actions and content to one or more web pages relating to the management of a value chain network. The value chain network includes a shared database on a computer over a network. The computer program product includes identifying an event in a value chain network, calculating a target value and a projected lost value, calculating a potential impact on a related performance target associated with the event, receiving one or more actions to resolve the event in the value chain network from one or more remote computers operated by respective one or more users, calculating a recovered value, calculating the difference between the target value and the recovered value, comparing the difference between the target value and the recovered value and historical differences stored in a database, storing the difference between the target value and the recovered value when the difference is less the respective historical differences stored in the database, retrieving the respective historical differences stored in the database, and transmitting one or more web pages containing the target value, recovered value and respective historical differences to a computer display. The target value is the anticipated value if the event in the value chain network had not occurred and the projected lost value is the anticipated lost value due to the event in the value chain network. The recovered value is the anticipated recovered value less the cost associated with each of the one or more actions to resolve the event in the value chain. 1. A computer program product embodied on a non-transitory computer readable medium for providing automated actions and content to one or more web pages relating to the management of a value chain network , wherein the value chain network includes a shared database on a computer over a network , wherein the computer program is implemented by one or more processors executing processor ...

VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS

Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations. 1. A method comprising:identifying a quantity of refresh intervals associated with refreshing memory cells of a memory device;identifying a quantity of received refresh commands;determining a quantity of refresh operations by determining a difference between the quantity of refresh intervals and the quantity of received refresh commands; andadjusting a supply voltage associated with the memory device for a duration based at least in part on the quantity of refresh operations.2. The method of claim 1 , wherein the refresh operations are pending refresh operations.3. The method of claim 1 , wherein:adjusting the supply voltage associated with the memory device for the duration comprises increasing the supply voltage from a first voltage to a second voltage based at least in part on the quantity of refresh operations.4. The method of claim 3 , wherein a value of the second voltage is based at least in part on the quantity of refresh operations.5. The method of claim 1 , further comprising:receiving a ...

Memory modules and memory packages including graphene layers for thermal management

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

VOLTAGE ADJUSTMENT BASED ON PENDING REFRESH OPERATIONS

Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

SYSTEM AND METHOD FOR AUTOMATED SOFTWARE ENGINEERING

Systems and methods for automated software engineering are disclosed. A particular embodiment is configured to: establish a data connection with a software code repository; provide a collection of autonomous computer programs or bots configured to automatically perform a specific software development life cycle (SDLC) task; use a first bot of the collection of bots to perform an automatic code review of a software module from the software code repository; use a second bot of the collection of bots to perform automatic unit testing of the software module from the software code repository; and use a third bot of the collection of bots to perform an automatic deployment of the software module from the software code repository. A health engine module can monitor the execution of the other software modules and capture execution metrics. Any of the bots in the bot collection can be machine learning models trained using training data.

MEMORY MODULES AND MEMORY PACKAGES INCLUDING GRAPHENE LAYERS FOR THERMAL MANAGEMENT

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

Current limit scheme for DC-DC converters

A current limit scheme for current-mode DC-DC converters. The current limit scheme is used to limit the current through the inductor during a current limit event. Current flows through the inductor alternately from first and second power devices, with one of said devices operating in the on-state while the other is in the off-state. The current through the second power device is sensed and tracked if the peak inductor current exceeds a particular value. The inductor current is regulated by modulating the on-time of the first power device that delivers current from the input voltage source to the output through the inductor. Thus, the modulator adjusts the on-time of the first power device using past and present information related to the current flowing through the second power device and the instantaneous output voltage of the converter to limit the peak inductor current from exceeding a maximum value.

Automated extraction of performance segments and metadata values associated with the performance segments from contract documents

A data processing system for extracting metadata values is described. The data processing system includes an input unit and a processor communicably coupled to the input unit. The input unit is configured to receive a contract document. The processor is configured to extract at least one segment from the contract document and identify a type of the at least one segment. The processor is further configured to extract at least one metadata value from the at least one segment based on a model, wherein the model is determined based on the identified type of the at least one segment.

Tubular heat spreaders for memory modules and memory modules incorporating the same

Systems, apparatuses, and methods for thermal dissipation on or from an electronic device are described. For example, a memory module may have a printed circuit board (PCB) having an edge connector, a plurality of memory devices disposed on a surface of the PCB, and a tubular heat spreader disposed along an edge of the PCB opposite the edge connector. The tubular heat spreader may comprise a tubular portion open at both ends thereof to permit the through flow of a cooling gas; and two planar elements extending in parallel away from the tubular portion and configured to provide a friction fit with the memory module. Each of the planar elements may be configured to convey thermal energy from the memory module to the tubular portion.

METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME

Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

Semiconductor Devices Including Polar Insulation Layer Capped By Non-Polar Insulation Layer

Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer. 1. A semiconductor device comprising:a semiconductor substrate;a polar insulation layer disposed on the semiconductor substrate, the polar insulation layer comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate; anda non-polar insulation layer disposed above the polar insulation layer.2. The semiconductor device of claim 1 , wherein a thickness of the polar insulation layer is less than fifty percent of a combined thickness of the polar and non-polar insulation layers.3. The semiconductor device of claim 2 , wherein the thickness of the polar insulation layer is less than twenty-five percent of the combined thickness of the polar and non-polar insulation layers.4. The semiconductor device of claim 3 , wherein the thickness of the polar insulation layer is between five percent and fifteen percent of the combined thickness of the polar and non-polar insulation layers.5. The semiconductor device of claim 4 , wherein the thickness of the polar insulation layer and the combined thickness of the polar and non-polar insulation layers are both measured along a hypothetical axis that is normal to an interface between the semiconductor substrate and the polar insulation layer.6. The semiconductor device of claim 1 , wherein the thickness of the polar insulation layer is less than ten nanometers.7. The semiconductor device of claim 6 , wherein the ...

APPARATUS AND METHODS FOR MEASURING CURRENT

In an embodiment, a body of apparatus includes an opening, such as a V-shaped jaw, that deterministically locates a position of a wire in at least one dimension when the wire is placed in the opening. The apparatus also includes a plurality of sensors. At least one differential signal can be generated from signals from magnetic sensors, such as anisotropic magnetoresistance (AMR) sensors, of the plurality of sensors to cancel out common mode interference. An additional sensor of the plurality of sensors provides an output from which the location of the wire in another dimension is determined. The current flowing through the wire can be derived from at least the at least one differential signal and the location of the wire the other dimension. 1. An apparatus for measuring current flowing through a wire , the apparatus comprising:a housing with an opening configured to receive the wire and to define a location of a point of the wire in a first dimension when the wire is positioned in the opening;two magnetic sensors within the housing positioned on opposing sides of the opening in the first dimension;another one or more sensors; and generate a differential signal indicative of a difference between outputs of the two magnetic sensors;', 'determine a location of the point of the wire in a second dimension based on an output of the another one or more sensors; and', 'derive a measure of the current flowing through the wire based on the differential signal and the determined location of the point of the wire in at least the second dimension., 'a processor in communication with the two magnetic sensors and the another one or more sensors, the processor configured to2. The apparatus of claim 1 , wherein the opening is configured to define the same location of a center point of the wire in the first dimension independent of the width of the wire.3. The apparatus of claim 1 , wherein at least a portion of the opening is substantially V-shaped.4. The apparatus of claim 1 , ...

COATED FERTILIZER CONTAINING UREASE INHIBITOR

Magnesium oxide, urease inhibitor, and superphosphate coated urea-based fertilizer core, methods for their use, and production thereof, are disclosed. The coating can be a powder coating containing particles that are 1 micron to 100 microns in average mean diameter. The fertilizer core, coated by the magnesium oxide, urease inhibitor, and superphosphate coating, can contain 50 wt. % or more, based on the total weight of the core, of a urea-based fertilizer, such as urea. The coating can optionally contain or exclude anticaking agent(s), and/or binding agent(s). 1. A coated fertilizer comprising:a fertilizer core comprising a urea-based fertilizer; anda powder coating in direct contact with at least a portion of the surface of the fertilizer core, wherein the powder coating comprises magnesium oxide, a urease inhibitor, and a superphosphate.2. The coated fertilizer of claim 1 , wherein the fertilizer core comprises 50 wt. % or more claim 1 , based on the total weight of the core claim 1 , of the urea-based fertilizer.3. The coated fertilizer of claim 1 , wherein the fertilizer core consists of the urea-based fertilizer.4. The coated fertilizer of claim 1 , wherein the urea-based fertilizer is urea.5. The coated fertilizer of claim 1 , wherein the magnesium oxide claim 1 , urease inhibitor claim 1 , and/or superphosphate are particles with a mean average diameter of 20 microns to 40 microns.6. The coated fertilizer of claim 1 , wherein the urease inhibitor is N-(n-butyl) thiophosphoric triamide claim 1 , or phenylphosphorodiamidate claim 1 , or any combination thereof.7. The coated fertilizer of claim 1 , wherein the urease inhibitor is N-(n-butyl) thiophosphoric triamide.8. The coated fertilizer of claim 1 , wherein the superphosphate is single superphosphate or triple superphosphate claim 1 , or a combination thereof.9. The coated fertilizer of claim 1 , wherein the powder coating consists of magnesium oxide claim 1 , the urease inhibitor claim 1 , and the ...

Apparatus and method of temperature drift compensation

Practical electronics such as amplifiers or voltage references can have circuit imbalances due to manufacturing imperfections. For example, amplifiers can have an undesirable offset voltage. The offset voltage might also drift with temperature making the design of these devices difficult. Disclosed are techniques which decrease the amount of offset voltage which provide predictability of device parameters over a range of temperatures.

WIDE RANGE TRANSIMPEDANCE AMPLIFIER

One aspect of this disclosure is a transimpedance amplifier circuit with multiple resistive feedback loops can be implemented with multiple Kelvin sensing channels. A transimpedance amplifier and multiple Kelvin sensing channels can be implemented on a single die having multiple contacts, such as pins, for connecting multiple resistors to the Kelvin sensing channels. The Kelvin sensing channels can be implemented with T-junction switch networks in certain embodiments. 1. An apparatus comprising a die , the die comprising:a transimpedance amplifier;a switch network comprising an input switch, an intermediate node, and an output switch, the input switch being electrically connected to the output switch at the intermediate node, wherein the input switch is electrically connected between an output of the transimpedance amplifier and the intermediate node; anda contact configured to provide an electrical connection to the intermediate node external to the die.2. The apparatus of claim 1 , wherein the contact is a pin.3. The apparatus of claim 1 , wherein the die further comprises another contact electrically connected to an input of the transimpedance amplifier.4. The apparatus of claim 1 , wherein each of the input switch and the output switch comprises:a first switch;a second switch;a pull-up device connected to a first junction between the first switch and the second switch;a third switch;a fourth switch; anda pull-down device connected to a second junction between the third switch and the fourth switch,wherein the pull-up device and the pull-down device are configured to be on responsive to a first signal, wherein the first, second, third, and fourth switches are configured to be on responsive to a second signal, and wherein the first signal is an inverse of the second signal.5. The apparatus of claim 4 , wherein the first switch is electrically connected between the output of the transimpedance amplifier and the first junction claim 4 , and wherein the second switch ...

ADC WITH CAPACITIVE DIFFERENCE CIRCUIT AND DIGITAL SIGMA-DELTA FEEDBACK

A low power high precision mixed signal analog to digital converter is provided for processing biometric signals in the presence of a large interferer signal for cableless patient monitoring; a capacitive difference circuit produces an analog difference signal by differencing an analog feedback loop signal and an input signal; an analog-to-digital converter sigma delta converter produces a digital version of the difference signal, a digital feedback loop includes a digital integrator and a capacitive digital-to-analog converter configured to produce the analog loop feedback signal based upon the digital version of the difference. 1. A low power analog-to-digital converter system comprising:a capacitive difference circuit, coupled to receive an analog input signal and to receive an analog loop feedback signal, and to output an analog difference signal representing a difference between the analog input signal and the analog loop feedback signal;a capacitive difference amplifier circuit configured to amplify the analog difference signal in proportion to a ratio of a first capacitance of the capacitive difference circuit and a second capacitance of the capacitive difference circuit to provide an amplified analog difference signal;a sigma-delta analog-to-digital converter (SD-ADC) coupled to produce a digital output signal based upon the amplified analog difference signal;a digital integrator circuit, coupled to receive the digital output signal and to provide a digital integration signal; anda capacitive digital-to-analog converter (DAC) coupled to produce the analog loop feedback signal based upon the digital output signal.2. The system of claim 1 ,wherein the analog input signal includes a biometric signal portion within a first frequency range and includes an interferer signal portion within a second frequency range; andwherein the analog loop feedback signal includes a signal portion within the second frequency range.3. The system of claim 1 ,wherein the analog ...

QUANTIZATION NOISE CANCELLATION IN A FEEDBACK LOOP

An analog front end (AFE) system for substantially eliminating quantization error or noise can combine an input of an integrator circuit in the AFE system with an input of the digital-to-analog converter (DAC) circuit in the feedback loop of the AFE system. By combining the input of the integrator with the input of the DAC circuit in the feedback loop, the in-band quantization noise of the filter can be substantially eliminated, thereby improving measurement accuracy. 1. An analog front end (AFE) system for compensating quantization error , the AFE system comprising:a gain circuit including a first input configured to receive an input signal, a second input configured to receive a feedback signal using a feedback path, and an output configured to provide an amplified version of the difference between the input signal and the feedback signal;an analog-to-digital converter (ADC) configured to receive a gain circuit output signal and output a digital output signal;a digital frequency-selective filter circuit configured to receive the ADC digital output signal and output a quantized filter circuit output signal;a digital-to-analog converter (DAC) circuit, the DAC circuit configured to receive the filter output signal and output the feedback signal to the second input of the gain circuit; andan AFE system output circuit configured to combine the ADC output signal and the filter circuit output signal, and output a quantization error-compensated AFE output signal.2. The AFE system of claim 1 , wherein the gain circuit output is configured to be periodically sampled to substantially reject any sampling noise contribution of the gain circuit.3. The ATE system of claim 1 , wherein the gain circuit comprises capacitive gain-setting elements.4. The AFE system of claim 1 , wherein the digital frequency-selective filter includes a quantizer circuit to output the quantized filter circuit output signal.5. The AFE system of claim 4 , wherein the quantizer circuit includes a sigma- ...

DYNAMIC ANTI-ALIAS FILTER FOR ANALOG-TO-DIGITAL CONVERTER FRONT END

An analog front end system can include a filter bypass switch connected in a boot-strapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage. Using bootstrapped switches can allow both the charge injection and capacitive coupling of the bypass switches of a differential anti-alias filter (AAF) to be common mode. A differential input signal of the ADC is not affected by the charge injection and capacitive coupling of the bypass switches in the AAF filter to a first order. 1. An analog front end (AFE) system including an anti-alias filter circuit having a filter bypass switch configured to provide at least one of a charge injection and a clock feedthrough that is independent of an input signal , the AFE system comprising:at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample an output of the anti-alias filter circuit;a gain or buffer circuit including an input to receive the input signal; and a filter resistor;', 'a filter capacitor coupled to a terminal of the filter resistor; and', 'the filter bypass switch connected in a boot-strapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, the filter bypass switch connected in parallel with the filter resistor, the filter bypass switch including an ON state and an OFF state,', 'wherein when in the ON state, the filter bypass switch is configured to bypass the filter resistor allowing the gain or buffer circuit to drive the at least one sampling capacitor through the filter bypass switch; and', 'wherein when in the OFF state, the filter bypass switch is configured to cause the gain or buffer circuit to drive the at least one sampling capacitor through the filter resistor., 'the anti-alias filter circuit coupled to an output of the gain or buffer circuit, the filter circuit including2. The AFE system of claim 1 , wherein the filter bypass switch connected in a boot-strapped ...

CURRENT MEASURING APPARATUS AND METHODS

Magnetic sensors may be positioned around an opening for a wire to measure the current flowing through the wire. A non-symmetric positioning of the sensors around the target measurement zone can enable an expanded measurement zone compared to conventional current measurement devices. Further, some sensors may be paired such that a hypothetical line connecting the sensors is tangential to the target measurement zone. Other sensors may be paired such that a hypothetical line between the sensors crosses the target measurement zone. The different pairs of the sensors can enable a reduction in the impact of stray field interference on the measurement of the current flowing through the wire. 1. An apparatus for measuring current flow through a wire , the apparatus comprising:a housing with an opening configured to receive a wire, wherein the opening corresponds to a target measurement zone for measuring a current flowing through the wire when the wire is positioned within the opening;a first pair of magnetic sensors within the housing and positioned such that a line between the magnetic sensors of the first pair is substantially tangential to the target measurement zone;a second pair of magnetic sensors within the housing and positioned such that a line between the magnetic sensors of the second pair crosses through the target measurement zone; anda hardware processor in communication with the first pair of magnetic sensors and the second pair of magnetic sensors, the hardware processor configured to derive a measure of the current flowing through the wire based on outputs from the first pair of magnetic sensors and the second pair of magnetic sensors.2. The apparatus of claim 1 , wherein the first pair of magnetic sensors and the second pair of magnetic sensors are positioned to reduce an impact of one or more stray fields on the measure of the current flowing through the wire when the wire is positioned within the target measurement zone.3. The apparatus of claim 1 , ...

High Gain Load Circuit for a Differential Pair Using Depletion Mode Transistors

A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

ANTI-CAKING FERTILIZER COMPOSITIONS

A particulate fertilizer coating composition or a coated fertilizer containing a solid acidic particulate material and a solid basic particulate material. The coating composition and coated fertilizer are each stable, chemical compatible with other fertilizers, and/or are abrasion resistant. 1. A fertilizer composition comprising a fertilizer particle having at least a portion of its surface coated with a particulate coating composition comprising a solid acidic particulate material and a solid basic particulate material.2. The fertilizer composition of claim 1 , wherein the fertilizer particle is a urea-based fertilizer particle or a phosphate-based fertilizer particle.3. The fertilizer composition of claim 2 , wherein the fertilizer particle comprises a single superphosphate (SSP) claim 2 , a triple super-phosphate (TSP) claim 2 , or a combination thereof.4. The fertilizer composition of claim 1 , wherein the solid acidic particulate material comprises at least one of a phosphate-based fertilizer claim 1 , a biostimulant claim 1 , a calcium lignosulfonate claim 1 , or a combination thereof.5. The fertilizer composition of claim 4 , wherein the solid acidic particulate material is a phosphate-based fertilizer selected from a solid particulate SSP claim 4 , a solid particulate TSP claim 4 , or a blend of solid particulate SSP and solid particulate TSP.6. The fertilizer composition of claim 1 , wherein the solid basic particulate material comprises a metal oxide claim 1 , preferably MgO claim 1 , ZnO claim 1 , CuO claim 1 , or blends thereof.7. The fertilizer composition of claim 1 , wherein:the fertilizer particle is a urea particle;the solid acidic particulate material comprises SSP or TSP, or a combination thereof; andthe solid basic particulate material comprises MgO.8. The fertilizer composition of claim 1 , comprising less than 10% claim 1 , 1 to 5% claim 1 , or 2 to 3.5% of the solid basic particulate material based on the total weight of the coated fertilizer ...

Color-stable thermoplastic composition

A thermoplastic composition is disclosed that includes a polyaryl ester polymer or copolymer and a phthalone compound according to the formula wherein Z 1 represents the atoms necessary to complete a 9- to 13-membered single or fused aromatic ring structure, Z 2 represents the atoms necessary to complete a pyridine or quinoline ring, each R 1 and each R 2 can independently be halogen, an alkyl group, an aryl group, a heterocyclic group, an alkoxy group, an aryloxy group, an aromatic or aliphatic thioether group, an aromatic or aliphatic carboxylic acid ester group, or an aromatic or aliphatic amide group, a is an integer from 0 to 6, b is an integer from 0 to 4, n is 1 or 2, and X is present only if n=2 and is a single bond or a divalent organic radical bonded to the Z 1 ring structure through an ether, ketone, or thio linkage.

CONTACTLESS CURRENT MEASUREMENT USING MAGNETIC SENSORS

Embodiments of the present disclosure provide mechanisms for measuring currents flowing in one or more conductor wires. The mechanisms are based on using magnetic sensor pairs arranged within a housing with an opening for the wires, where each magnetic sensor pair can generate a pair of signals indicative of magnetic fields in two different directions. The outputs of the sensor pairs can be used to derive a measure of current(s) flowing through the one or more wires. The use of magnetic sensor pairs that can measure magnetic field in two different directions may enable simultaneous current measurement in multiple wires placed within the opening, improve accuracy of current measurements while relaxing requirements for precise control of the placement of the wire(s), reduce the impact of stray magnetic interference, and enable both AC and DC measurements. 1. An apparatus for measuring current flow through at least one wire , the apparatus comprising:a housing comprising an opening for receiving the at least one wire; a first signal indicative of a magnetic field in a first direction, and', 'a second signal indicative of a magnetic field in a second direction; and, 'a plurality of magnetic sensor pairs arranged within the housing, each magnetic sensor pair configured to generate signals when the at least one wire extends through the opening, the signals includinga hardware processor configured to derive a measure of a current in the at least one wire based on the signals generated by at least two or more of the plurality of magnetic sensor pairs.2. The apparatus according to claim 1 , wherein the first direction is perpendicular to the second direction.3. The apparatus according to claim 1 , wherein each of the plurality of magnetic sensor pairs is arranged with respect to a common reference point so that claim 1 , for each magnetic sensor pair:the first direction is perpendicular to a line connecting a sensor reference point of the magnetic sensor pair and the common ...

WEATHERABLE THERMOPLASTIC COMPOSITIONS, METHOD OF MANUFACTURE, AND ARTICLES THEREFROM

A thermoplastic composition including a polyaryl ester, a polymer different from the polyaryl ester, and a phthalone compound according to the formula (I) wherein Zrepresents the atoms necessary to complete a 9- to 13-membered single or fused aromatic ring structure, Zrepresents the atoms necessary to complete a pyridine or quinoline ring, each Rand each Rare independently halogen, an alkyl group, an aryl group, a heterocyclic group, an alkoxy group, an aryloxy group, an aromatic or aliphatic thioether group, an aromatic or aliphatic carboxylic acid ester group, or an aromatic or aliphatic amide group, a is 0 to 6, b is 0 to 4, n is 1 or 2, and X is present only if n=2 and is a single bond or a divalent organic radical bonded to the Zring structure through an ether, ketone, or thio linkage. 3. The thermoplastic composition of claims 1 , wherein the polyaryl ester is a copolymer of a polyaryl ester derived from resorcinol or bisphenol A and a mixture of isophthalic acid claims 1 , halide claims 1 , or anhydride claims 1 , terephthalic acid claims 1 , halide claims 1 , or anhydride claims 1 , and a polycarbonate derived from bisphenol A and a carbonate source.4. The thermoplastic composition of claim 2 ,wherein at least 80 percent of the total number of T groups containing aromatic moieties are derived from isophthalic acid and/or terephthalic acid; andat least 80 percent of the total number of J groups contain aromatic moieties derived from resorcinol or bisphenol A and the balance thereof are aliphatic, alicyclic, or aromatic.6. The thermoplastic composition of claim 5 , whereinat least 90 percent of the total number of T groups contain aromatic moieties derived from isophthalic acid and/or terephthalic acid; and{'sup': 1', '1, 'all of the Rgroups contain aromatic moieties, preferably wherein all of the Rgroups are derived from bisphenol A and/or resorcinol.'}7. The thermoplastic composition of claim 6 , wherein the T groups are derived from isophthalic acid and/or ...

Semiconductor Devices Including Polar Insulation Layer Capped by Non-Polar Insulation Layer

Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.

3-AXIS MAGNETIC POSITION SYSTEM FOR MINIMALLY INVASIVE SURGICAL INSTRUMENT, SYSTEMS AND METHODS THEREOF

A minimally invasive surgical instrument using 3-axis magnetic positioning, system and methods thereof. This invention describes two key ideas that enable the development of a magnetic position system based on integrated anisotropic magnetoresistive (AMR) magnetic field sensors. This achieves the resolution, power and area targets necessary to integrate 3 axes anisotropic magnetoresistance (AMR) sensors along with the Analog Front End integrated circuit (IC) in a 4 mm by 350 um integrated solution for catheter applications. The stringent area and power dissipation requirements are met by development through both system level solutions for higher field strengths and a minimally necessary Analog Front End (AFE) to meet the 1 mm rms resolution requirement in the power dissipation and area budget. 1. A multi-axis magnetic apparatus used in a positioning of a medical device comprising:a first die configured to measure at least one of first axis orientation and first position;a second die configured to measure at least one of second axis orientation and second position; and,a third die comprising an analog front end.2. The multi-axis magnetic apparatus used in the positioning of a medical device of claim 1 , wherein one of the first claim 1 , second claim 1 , and third dice is configured to measure at least one of third axis orientation and third position.3. The multi-axis magnetic apparatus used in the positioning of a medical device of further comprising a full bridge.4. The multi-axis magnetic apparatus used in the positioning of a medical device of claim 3 , wherein the full bridge comprises magnetoresistive elements.5. The multi-axis magnetic apparatus used in the positioning of a medical device of further comprising a half bridge comprising magnetoresistive elements.6. The multi-axis magnetic apparatus used in the positioning of a medical device of further comprising a half bridge comprising poly-resistive elements.7. The multi-axis magnetic apparatus used in the ...

MAGNETIC SENSOR SYSTEMS

A calibration apparatus for calibrating a magnetic sensor configured to generate an output signal indicative of magnetic field strength when a bias signal is applied to it is disclosed. The apparatus includes a test magnetic field generator (MFG) to generate magnetic fields of known magnitude, and further includes a processor to control the MFG to generate a known magnetic field, control the sensor to generate a test output signal when the MFG generates the known magnetic field and a known bias signal is applied to the sensor, and determine how to change the bias signal based on a deviation of the measured test output signal from an expected output signal. Using a test MFG that produces known magnetic fields when known bias signals are applied to sensors allows evaluating and compensating for changes in sensitivity of the sensors by accordingly changing bias signals applied to the sensors. 1. An apparatus for calibrating a magnetic sensor configured to generate an output signal indicative of magnetic field strength when an input signal is applied to the magnetic sensor , the apparatus comprising:a test magnetic field generator; and control the test magnetic field generator to generate a first known magnetic field,', 'control the magnetic sensor to generate a first test output signal when the test magnetic field generator generates the first known magnetic field and a first input signal is applied to the magnetic sensor,', 'determine a first compensation value for the first input signal based on a deviation of the first test output signal from a first expected output signal, wherein the first expected output signal is indicative of magnetic field strength of the first known magnetic field, and', 'determine a compensated input signal to be applied to the magnetic sensor, wherein the compensated input signal is based on the first compensation value., 'a processor configured to2. The apparatus according to claim 1 , wherein:controlling the magnetic sensor to generate ...

Thermoplastic compositions, method of manufacture, and articles therefrom

A thermoplastic composition including a polycarbonatesiloxane-arylate; a phthalone compound; and optionally an additional component different from the polycarbonatesiloxane-arylate and the phthalone compound; wherein the phthalone compound has a formula: wherein Z 1 represents the atoms necessary to complete a 9- to 13-membered single or fused aromatic ring structure, Z 2 represents the atoms necessary to complete a pyridine or quinoline ring, each R 1 and each R 2 are independently halogen, an alkyl group, an aryl group, a heterocyclic group, an alkoxy group, an aryloxy group, an aromatic or aliphatic thioether group, an aromatic or aliphatic carboxylic acid ester group, or an aromatic or aliphatic amide group, a is an integer from 0 to 6, b is an integer from 0 to 4, n is 1 or 2, and X is present only if n=2 and is a single bond or a divalent organic radical bonded to the Z 1 ring structure through an ether, ketone, or thio linkage.

Rac-like genes from maize and methods of use

The present invention provides methods and compositions relating to creating or enhancing disease resistance in plants. The invention provides isolated maize Rac nucleic acids and their encoded proteins that are involved in altering the disease resistance pathway in plants, increasing transformation efficiency, inducing programmed cell death, and modulating the oxidative burst in a plant. The invention further provides recombinant expression cassettes, host cells, transgenic plants, and antibody compositions.

Magnetic sensor systems

A calibration apparatus for calibrating a magnetic sensor configured to generate an output signal indicative of magnetic field strength when a bias signal is applied to it is disclosed. The apparatus includes a test magnetic field generator (MFG) to generate magnetic fields of known magnitude, and further includes a processor to control the MFG to generate a known magnetic field, control the sensor to generate a test output signal when the MFG generates the known magnetic field and a known bias signal is applied to the sensor, and determine how to change the bias signal based on a deviation of the measured test output signal from an expected output signal. Using a test MFG that produces known magnetic fields when known bias signals are applied to sensors allows evaluating and compensating for changes in sensitivity of the sensors by accordingly changing bias signals applied to the sensors.

Rac-like genes and methods of use

The present invention provides methods and compositions relating to creating or enhancing disease resistance in plants. The invention provides isolated maize Rac nucleic acids and their encoded proteins that are involved in the altering the disease resistance pathway in plants, increasing transformation efficiency, inducing programmed cell death, and modulating the oxidative burst in a plant. The invention further provides recombinant expression cassettes, host cells, transgenic plants, and antibody compositions.

Dynamic anti-alias filter for analog-to-digital converter front end

An analog front end system can include a filter bypass switch connected in a boot-strapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage. Using bootstrapped switches can allow both the charge injection and capacitive coupling of the bypass switches of a differential anti-alias filter (AAF) to be common mode. A differential input signal of the ADC is not affected by the charge injection and capacitive coupling of the bypass switches in the AAF filter to a first order.

Sic mosfet structures with asymmetric trench oxide

We herein describe a silicon-carbide (SiC) based power semiconductor device comprising: a drain region of a first conductivity type; a drift region of the first conductivity type disposed on the drain region, the drift region having a lower doping concentration compared to the doping concentration of the drain region; a body region of a second conductivity type, opposite to the first conductivity type, disposed over the drift region; a contact region of the first conductivity type, disposed within the body region; a source Ohmic contact being disposed on the source region; and one or more trench gate regions being in contact with the source region, the body region and the drift region. Each of the one or more trench gate regions are configured to form a channel region in the body region between the source region and the drift region. At least one trench gate region comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface. The insulation layer comprises different thicknesses such that the insulation layer is thinner at a portion of one of the vertical sidewalls including the channel region than at the other vertical side wall and the trench bottom.

ADC with capacitive differential circuit and digital sigma-delta feedback

Leistungsarmes Analog-Digital-Wandlersystem, aufweisend:eine kapazitive Differenzschaltung, gekoppelt zum Empfangen eines analogen Eingangssignals und zum Empfangen eines analogen Schleifenrückkopplungssignals und zum Ausgeben eines analogen Differenzsignals, das eine Differenz zwischen dem analogen Eingangssignal und dem analogen Schleifenrückkopplungssignal darstellt;eine kapazitive Differenzverstärkerschaltung, ausgebildet zum Verstärken des analogen Differenzsignals proportional zu einem Verhältnis einer ersten Kapazität der kapazitiven Differenzverstärkerschaltung und einer zweiten Kapazität der kapazitiven Differenzverstärkerschaltung, um ein verstärktes analoges Differenzsignal zu liefern;einen Sigma-Delta-Analog-Digital-Wandler (SD-ADW), gekoppelt zum Erzeugen eines digitalen Ausgangssignals auf Basis des verstärkten analogen Differenzsignals;eine digitale Integriererschaltung, gekoppelt zum Empfangen des digitalen Ausgangssignals und zum Liefern eines digitalen Integrationssignals; undeinen kapazitiven Digital-Analog-Wandler (DAW), gekoppelt zum Erzeugen des analogen Schleifenrückkopplungssignals auf Basis des digitalen Integrationssignals. A low power analog-to-digital converter system, comprising: a capacitive differential circuit coupled to receive an analog input signal and to receive an analog loop feedback signal and for outputting an analog differential signal representing a difference between the analog input signal and the analog loop feedback signal; a capacitive differential amplifier circuit formed for amplifying the differential analog signal proportional to a ratio of a first capacitance of the differential capacitive amplifier circuit and a second capacitance of the differential capacitive amplifier circuit to provide an amplified differential analog signal; a sigma-delta analog-to-digital converter (SD-ADC) coupled for generating a digital output signal based on the amplified analog difference signal; a digital integrator circuit coupled to ...

Current measurement using magnetic sensors and contour intervals

Embodiments of the present disclosure provide mechanisms for measuring currents flowing in one or more conductor wires. The mechanisms are based on using magnetic sensor pairs arranged within a housing with an opening for the wires, where each magnetic sensor pair can generate a pair of signals indicative of magnetic fields in two different directions. The outputs of the sensor pairs can be used to derive a measure of current(s) flowing through the one or more wires. The use of magnetic sensor pairs that can measure magnetic field in two different directions may enable simultaneous current measurement in multiple wires placed within the opening, improve accuracy of current measurements while relaxing requirements for precise control of the placement of the wire(s), reduce the impact of stray magnetic interference, and enable both AC and DC measurements.

Rac-like genes and methods of use

The present invention provides methods and compositions for introducing plant Rac polypeptides and polynucleotides into animal cells. The invention provides methods for treating patients with infections, preventing reperfusion injuries and preventing blood vessel damage by introduction of plant Rac polypeptides and polynucleotides.

Transgenic plants with enhanced agronomic traits

This invention provides recombinant DNA for expression of proteins that are useful for imparting enhanced agronomic trait(s) to transgenic crop plants. Also provided by this invention is transgenic seed for growing a transgenic plant having recombinant DNA in its genome and exhibiting an enhance agronomic trait, i.e. enhanced nitrogen use efficiency, increased yield, enhanced water use efficiency, enhanced tolerance to cold stress and/or improved seed compositions. Also disclosed are methods for identifying such transgenic plants by screening for nitrogen use efficiency, yield, water use efficiency, growth under cold stress, and seed composition changes. This invention also discloses a method of identifying the target genes of a transcription factor.

High power laser flat panel workpiece treatment system controller

Automated extraction of performance segments and metadata values associated with the performance segments from contract documents

AUTOMATED EXTRACTION OF PERFORMANCE SEGMENTS AND METADATA VALUES ASSOCIATED WITH THE PERFORMANCE 5 SEGMENTS FROM CONTRACT DOCUMENTS A data processing system (104) for extracting metadata values is described. The data processing system (104) comprises an input unit (202) and a processor (204) communicably coupled to the input unit (202). The input unit (202) is configured to 10 receive a contract document. The processor (204) is configured to extract (502) at least one segment from the contract document and identify (504) a type of the at least one segment. The processor (204) is further configured to extract (506) at least one metadata value from the at least one segment based on a model, wherein the model is determined based on the identified type of the at least one segment. 15 FIG.1 DATA EXTRACTION SYSTEM 100 DATASTORAGE DATA SYSTEM PROCESSING 106 SYSTEM 104 COMMUNICATION NETWORK 108 USER DEVICE /14 102 INPUT UNIT OUTPUT UNIT 110 112 FIG. 1 19

Transgenic plants with enhanced agronomic traits

This invention provides recombinant DNA for expression of proteins that are useful for imparting enhanced agronomic trait(s) to transgenic crop plants. Also provided by this invention is transgenic seed for growing a transgenic plant having recombinant DNA in its genome and exhibiting an enhance agronomic trait, i.e. enhanced nitrogen use efficiency, increased yield, enhanced water use efficiency, enhanced tolerance to cold stress and/or improved seed compositions. Also disclosed are methods for identifying such transgenic plants by screening for nitrogen use efficiency, yield, water use efficiency, growth under cold stress, and seed composition changes. This invention also discloses a method of identifying the target genes of a transcription factor.

Current measuring apparatus and methods

Magnetic sensors may be positioned around an opening for a wire to measure the current flowing through the wire. A non-symmetric positioning of the sensors around the target measurement zone can enable an expanded measurement zone compared to conventional current measurement devices. Further, some sensors may be paired such that a hypothetical line connecting the sensors is tangential to the target measurement zone. Other sensors may be paired such that a hypothetical line between the sensors crosses the target measurement zone. The different pairs of the sensors can enable a reduction in the impact of stray field interference on the measurement of the current flowing through the wire.

Plasma-enhanced molybdenum deposition

Embodiments of the disclosure are directed to methods of depositing a molybdenum film directly on a substrate surface (e.g., a low-κ dielectric material) by exposing the substrate surface to a molybdenum-containing precursor and a plasma at a temperature of less than or equal to 400 °C. The molybdenum-containing precursor comprises one or more of molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), molybdenum hexacarbonyl, bis(tert-butylimido)-bis(dimethylamido)molybdenum, or bis(ethylbenzene) molybdenum. The plasma comprises one or more of hydrogen (H2), nitrogen (N2), or a silane (SixHy). In some embodiments, when the molybdenum-containing precursor comprises molybdenum hexafluoride (MoF6), the plasma does not include hydrogen (H2).

Conformal molybdenum deposition

Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include converting an amorphous silicon layer to a metal layer by thermally soaking the amorphous silicon layer comprising silicon atoms in the presence of a metal compound selected from the group consisting of a molybdenum compound and a tungsten compound until at least a portion of the silicon atoms in the amorphous silicon layer are replaced by metal atoms selected from the group consisting of molybdenum atoms and tungsten atoms. The methods include conformally depositing a molybdenum film on the metal layer.

Voltage adjustment based on pending refresh operations

Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

Integrated cleaning and selective molybdenum deposition processes

Embodiments of the disclosure advantageously provide in situ selectively deposited molybdenum films having reduced resistivity and methods of reducing or eliminating lateral growth of a selectively deposited molybdenum layer. Additional embodiments provide integrated clean and deposition processes which improve the selectivity of in situ selectively deposited molybdenum films on features, such as a via. Further embodiments advantageously provide methods of improving uniformity and selectivity of bottom-up gap fill for vias with improved film properties.

Field suppressed metal gapfill

Embodiments of the disclosure relate to methods for bottom-up metal gapfill without substantial deposition outside of the feature. Additional embodiments provide a method of forming a metal material on the top surface of the substrate and the bottom of the feature before depositing the metal gapfill.

Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Methods of making urea calcium sulfate (ucs) using high shear mixing

A urea calcium sulfate (UCS) fertilizer granule includes urea, calcium sulfate, and a calcium sulfate urea adduct, and is prepared by a continuous process including: (a) combining urea, calcium sulfate, and water to form an aqueous slurry, wherein the urea is solubilized in the aqueous slurry; (b) mixing the aqueous slurry in a high shear mixing apparatus, wherein the high shear mixing apparatus applies a shear of at least 50,000/seconds to the aqueous slurry; and (c) removing at least a portion of the water from the aqueous slurry to form the UCS fertilizer granule. The UCS fertilizer granule includes at least 80% calcium sulfate urea adduct. Methods for making a fertilizer composition including urea calcium sulfate (UCS) fertilizer granules are also described.

Conformal molybdenum deposition

Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include forming a nucleation layer directly on a dielectric layer on a substrate surface by exposing the substrate surface to a molybdenum-containing precursor and a nucleation reactant, and conformally depositing a molybdenum film on the nucleation layer. Another aspect of the disclosure pertains to a method that is part of a gap fill process, comprising forming a nucleation layer directly on a dielectric region within one or more high aspect ratio gap features, including vertical gap features and/or horizontal gap features, and conformally depositing a molybdenum film on the nucleation layer to fill the feature.

Urea calcium sulfate coated urea fertilizer and blends thereof

Disclosed is a fertilizer granule containing a core containing at least 90 wt. % of urea, and a shell containing a urea calcium sulfate (UCS) adduct, where the shell covers at least a portion of an outer surface of the core, and blends of the fertilizer granules with other fertilizers. Methods of making and using the fertilizer granule and the blends are also disclosed.

High gain load circuit for a differential pair using depletion mode transistors

A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

Method and system for determining risk score for a contract document

METHOD AND SYSTEM FOR DETERMINING RISK SCORE FOR A CONTRACT DOCUMENT A method (400) for determining a risk score for a contract document, is provided. The method includes extracting (402), by a processor (120), at least one clause from the contract document and determining (410), by the processor (120), a clause category risk score associated with a clause category of the extracted at least one clause. The clause category risk score is determined based on a clause risk score of the extracted at least one clause and a clause risk probability associated with the clause risk score of the extracted at least one clause. The method further includes determining (412), by the processor (120), the risk score for the contract document based on the clause category risk score associated with the clause category of the extracted at least one clause. FIG. 4 19 1/4 ol~

Voltage adjustment based on pending refresh operations

Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

Voltage adjustment based on pending refresh operations

Anti-caking fertilizer compositions

A particulate fertilizer coating composition or a coated fertilizer containing a solid acidic particulate material and a solid basic particulate material. The coating composition and coated fertilizer are each stable, chemical compatible with other fertilizers, and/or are abrasion resistant.

Urea calcium sulfate coated urea fertilizer and blends thereof

Disclosed is a fertilizer granule containing a core containing at least 90 wt. % of urea, and a shell containing a urea calcium sulfate (UCS) adduct, where the shell covers at least a portion of an outer surface of the core, and blends of the fertilizer granules with other fertilizers. Methods of making and using the fertilizer granule and the blends are also disclosed.

Urea calcium sulfate coated urea fertilizer and blends thereof

Disclosed is a fertilizer granule containing a core containing at least 90 wt. % of urea, and a shell containing a urea calcium sulfate (UCS) adduct, where the shell covers at least a portion of an outer surface of the core, and blends of the fertilizer granules with other fertilizers. Methods of making and using the fertilizer granule and the blends are also disclosed.

Color-stable thermoplastic composition

A thermoplastic composition is disclosed that includes a polyaryl ester polymer or copolymer and a phthalone compound according to the formula; wherein Z 1 represents the atoms necessary to complete a 9- to 13-membered single or fused aromatic ring structure, Z 2 represents the atoms necessary to complete a pyridine or quinoline ring, each R 1 and each R 2 can independently be halogen, an alkyl group, an aryl group, a heterocyclic group, an alkoxy group, an aryloxy group, an aromatic or aliphatic thioether group, an aromatic or aliphatic carboxylic acid ester group, or an aromatic or aliphatic amide group, a is an integer from 0 to 6, b is an integer from 0 to 4, n is 1 or 2, and X is present only if n= 2 and is a single bond or a divalent organic radical bonded to the Z 1 ring structure through an ether, ketone, or thio linkage.

Semiconductor devices including polar insulation layer capped by non-polar insulation layer

Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.

Plasma-enhanced molybdenum deposition

Embodiments of the disclosure are directed to methods of depositing a molybdenum film directly on a substrate surface (e.g., a low-κ dielectric material) by exposing the substrate surface to a molybdenum-containing precursor and an organosilane reducing agent at a temperature of less than or equal to 450 °C. The molybdenum-containing precursor comprises one or more of molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), molybdenum hexafluoride (MoF6), molybdenum hexacarbonyl, bis(tert-butylimido)-bis(dimethylamido)molybdenum, or bis(ethylbenzene) molybdenum. The organosilane reducing agent comprises trimethylsilyl compounds, such as 1,4-bis(trimethylsilyl)-2-methyl-2,5-cyclohexadiene.

Plasma-enhanced molybdenum deposition

Embodiments of the disclosure are directed to methods of depositing a molybdenum film directly on a substrate surface (e.g., a low-κ dielectric material) by exposing the substrate surface to a molybdenum-containing precursor and an organosilane reducing agent at a temperature of less than or equal to 450° C. The molybdenum-containing precursor comprises one or more of molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), molybdenum hexafluoride (MoF6), molybdenum hexacarbonyl, bis(tert-butylimido)-bis(dimethylamido)molybdenum, or bis(ethylbenzene) molybdenum. The organosilane reducing agent comprises trimethylsilyl compounds, such as 1,4-bis(trimethylsilyl)-2-methyl-2,5-cyclohexadiene.

Methods for tuning command/address bus timing and memory devices and memory systems using the same

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

Thermoplastic compositions, method of manufacture, and articles therefrom

A thermoplastic composition including a polycarbonatesiloxane-arylate; a phthalone compound; and optionally an additional component different from the polycarbonatesiloxane- arylate and the phthalone compound; wherein the phthalone compound has a formula: wherein Z 1 represents the atoms necessary to complete a 9- to 13-membered single or fused aromatic ring structure, Z 2 represents the atoms necessary to complete a pyridine or quinoline ring, each R 1 and each R 2 are independently halogen, an alkyl group, an aryl group, a heterocyclic group, an alkoxy group, an aryloxy group, an aromatic or aliphatic thioether group, an aromatic or aliphatic carboxylic acid ester group, or an aromatic or aliphatic amide group, a is an integer from 0 to 6, b is an integer from 0 to 4, n is 1 or 2, and X is present only if n= 2 and is a single bond or a divalent organic radical bonded to the Z 1 ring structure through an ether, ketone, or thio linkage.

High gain load circuit for a differential pair using depletion mode transistors

A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

Method of forming interconnect structure

Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III):wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X′, and Y′ are independently selected from nitrogen (N) and carbon (C).

Weatherable thermoplastic compositions, method of manufacture, and articles therefrom

High power laser flat panel workpiece treatment system controller

According to aspects of an embodiment of the disclosed subject matter an overview of the architecture may start with the fact that the functionality of MSC software may be provided by at least two top-level. components a Server Daemon Process and a GUI Client. The Server Daemon Process, e.g., server (20 ) can be responsible for executing the device commands and monitoring the status of the devices, while the GUI Client, e.g.. GUI (40) can be responsible for taking user specific information recipe definitions from the user and sending user commands to the Server Daemon Process (40). The GUI Client (10) can also display the status of the devices and the progress of the crystallization process to the user: According to aspects of an embodiment of the disclosed subject matter, an OEM schema database (22) may be separated from an MSC schema database (24). This may be because the OEM schema database (22) may contain read-only information, e.g., data task definitions data. The tool users can be not expected to modify it. By keeping the OEM schema data separate from the MSC schema data, it may be easy to upgrade the system with new task definitions from the work system supplier, e.g., the MSC system manufacturer (the OEM) and also easier, e.g., for the overall system to be customized to a particular user's needs, e.g., the best way to optimize for throughput for the user's particular manufacturing system being controlled and other needs.

High power laser flat panel workpiece treatment

According to aspects of an embodiment of the disclosed subject matter an overview of the architecture may start with the fact that the functionality of MSC software may be provided by at least two top-level. components a Server Daemon Process and a GUI Client. The Server Daemon Process, e.g., server (20 ) can be responsible for executing the device commands and monitoring the status of the devices, while the GUI Client, e.g.. GUI (40) can be responsible for taking user specific information recipe definitions from the user and sending user commands to the Server Daemon Process (40). The GUI Client (10) can also display the status of the devices and the progress of the crystallization process to the user: According to aspects of an embodiment of the disclosed subject matter, an OEM schema database (22) may be separated from an MSC schema database (24). This may be because the OEM schema database (22) may contain read-only information, e.g., data task definitions data. The tool users can be not expected to modify it. By keeping the OEM schema data separate from the MSC schema data, it may be easy to upgrade the system with new task definitions from the work system supplier, e.g., the MSC system manufacturer (the OEM) and also easier, e.g., for the overall system to be customized to a particular user's needs, e.g., the best way to optimize for throughput for the user's particular manufacturing system being controlled and other needs.

3-axis magnetic position system for minimally invasive surgical instrument, systems and methods thereof

A minimally invasive surgical instrument using 3-axis magnetic positioning, system and methods thereof. This invention describes two key ideas that enable the development of a magnetic position system based on integrated anisotropic magnetoresistive (AMR) magnetic field sensors. This achieves the resolution, power and area targets necessary to integrate 3 axes anisotropic magnetoresistance (AMR) sensors along with the Analog Front End integrated circuit (IC) in a 4 mm by 350 um integrated solution for catheter applications. The stringent area and power dissipation requirements are met by development through both system level solutions for higher field strengths and a minimally necessary Analog Front End (AFE) to meet the 1 mm rms resolution requirement in the power dissipation and area budget.

Methods of making urea calcium sulfate (ucs) using high shear mixing

A urea calcium sulfate (UCS) fertilizer granule includes urea, calcium sulfate, and a calcium sulfate urea adduct, and is prepared by a continuous process including: (a) combining urea, calcium sulfate, and water to form an aqueous slurry, wherein the urea is solubilized in the aqueous slurry; (b) mixing the aqueous slurry in a high shear mixing apparatus, wherein the high shear mixing apparatus applies a shear of at least 50,000/seconds to the aqueous slurry; and (c) removing at least a portion of the water from the aqueous slurry to form the UCS fertilizer granule. The UCS fertilizer granule includes at least 80% calcium sulfate urea adduct. Methods for making a fertilizer composition including urea calcium sulfate (UCS) fertilizer granules are also described.

Methods of making urea calcium sulfate (ucs) using high shear mixing

A urea calcium sulfate (UCS) fertilizer granule includes urea, calcium sulfate, and a calcium sulfate urea adduct, and is prepared by a continuous process including: (a) combining urea, calcium sulfate, and water to form an aqueous slurry, wherein the urea is solubilized in the aqueous slurry; (b) mixing the aqueous slurry in a high shear mixing apparatus, wherein the high shear mixing apparatus applies a shear of at least 50,000/seconds to the aqueous slurry; and (c) removing at least a portion of the water from the aqueous slurry to form the UCS fertilizer granule. The UCS fertilizer granule includes at least 80% calcium sulfate urea adduct. Methods for making a fertilizer composition including urea calcium sulfate (UCS) fertilizer granules are also described.

Methods for memory power management and memory devices and systems employing the same

Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.

Coated fertilizer containing urease inhibitor

Magnesium oxide, urease inhibitor, and superphosphate coated urea-based fertilizer core, methods for their use, and production thereof, are disclosed. The coating can be a powder coating containing particles that are 1 micron to 100 microns in average mean diameter. The fertilizer core, coated by the magnesium oxide, urease inhibitor, and superphosphate coating, can contain 50 wt. % or more, based on the total weight of the core, of a urea-based fertilizer, such as urea. The coating can optionally contain or exclude anticaking agent(s), and/or binding agent(s).

Halide and organic precursors for metal deposition

Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.

Halide and organic precursors for metal deposition

Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.

Color-stable thermoplastic composition

A thermoplastic composition is disclosed that includes a polyaryl ester polymer or copolymer and a phthalone compound according to the formula wherein Z 1 represents the atoms necessary to complete a 9- to 13-membered single or fused aromatic ring structure, Z 2 represents the atoms necessary to complete a pyridine or quinoline ring, each R 1 and each R 2 can independently be halogen, an alkyl group, an aryl group, a heterocyclic group, an alkoxy group, an aryloxy group, an aromatic or aliphatic thioether group, an aromatic or aliphatic carboxylic acid ester group, or an aromatic or aliphatic amide group, a is an integer from 0 to 6, b is an integer from 0 to 4, n is 1 or 2, and X is present only if n=2 and is a single bond or a divalent organic radical bonded to the Z 1 ring structure through an ether, ketone, or thio linkage.

Method of forming interconnect structure

Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III):, wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X', and Y' are independently selected from nitrogen (N) and carbon (C).