ЯЧЕЙКА КОММУТИРУЮЩЕЙ СРЕДЫ

Ячейка коммутирующей среды, содержащая схемы И, схемы И-НЕ, схемы ИЛИ и триггеры управления, причем первые входы схем И-НЕ соединены с единичными выходами соответствующих триггеров управления, а вторые входы подключены к выходу схемы И координатной выборки узла, а входы приемных схем И-НЕ подключены к дополнительным шинам запрещения распространения волны поиска кратчайшей трассы, выход схемы И-НЕ опроса состояний приемных схем И-НЕ соединен через схему ИЛИ с нулевым входом триггера управления, единичный выход которого соединен с первым входом выходной схемы И-НЕ анализа принадлежности ячейки трассе, а также с входом приемной схемы И-НE, кроме того, два других входа выходной схемы И-НЕ анализа принадлежности ячейки трассе соединены один с нулевым выходом триггера управления смежной ячейки, другой - с выходом входной схемы И-НЕ анализа принадлежности ячейки трассе, отличающаяся тем, что содержит схемы суммирования по модулю два для анализа встречи волн, первые входы которых соединены с входной ...

УСТРОЙСТВО ПОИСКА НИЖНЕЙ ОЦЕНКИ РАЗМЕЩЕНИЯ В ПОЛНОСВЯЗНЫХ МАТРИЧНЫХ СИСТЕМАХ ПРИ ОДНОНАПРАВЛЕННОЙ ПЕРЕДАЧЕ ИНФОРМАЦИИ

... 1. Устройство поиска нижней оценки размещения в полносвязных матричных системах при однонаправленной передаче информации, содержащее первый регистр сдвига, второй регистр сдвига, блок формирования перестановок (БФП), блок постоянной памяти, блок запоминания лучшего варианта (БЗЛВ), коммутатор, АЛУ, дешифратор выбора дуги, реверсивный счетчик ячеек, блок оперативной памяти, счетчик топологии, первый и второй счетчики расстояний, умножитель, сумматор, регистр минимальной длины связей, первый элемент сравнения, вычитатель, триггер начала счета, триггер режима, триггер задания топологии, регистр длины связей, второй элемент сравнения, счетчик дуг, дешифратор блокировки дуги, регистр номера дуги, регистр минимального веса, электронную модель графа, группу с 1-го по n-й элементов ИЛИ, группу 1-го по m-й элементов И, первый и второй элементы И, второй блок элементов ИЛИ, третий элемент И, первый и второй одновибраторы, первый, второй и третий элементы задержки, первый блок элементов ИЛИ, причем ...

Quantum circuit synthesis using deterministic walks

Design method and device of printed circuit board and storage medium

Extracting parasitic capacitance from circuit designs

An integrated circuit includes a target wiring layer, a first adjacent wiring layer above the target wiring layer, and a second adjacent wiring layer below the target wiring layer. Each adjacent wiring layer including crossing wires orthogonal to the target wiring layer. Modify a putative design of the integrated circuit by selecting a target wire; identifying lateral neighbors of the target wire; defining regions of the target wire where the lateral neighbors are homogeneous in cross-section; for each region of the target wire, calculating a wire pattern for the crossing wires; identifying segments within above and below portions of the wire pattern; for each above and below segment pair, obtaining a per-unit-length capacitance from a reduced pattern database; extracting a total parasitic capacitance from the per-unit-length pattern capacitances; and in response to an assessment of the impact of the total parasitic capacitance on circuit performance, producing a modified design.

PCB stencil manufacturing method and system

A PCB stencil manufacturing method and system. The method comprises: inputting PCB stencil design information in a preset input format, the PCB stencil design information comprises solder pad element information; and converting the PCB stencil design information into corresponding system core data information, the system core data information comprises solder pad element packaging information, and the solder pad element packaging information comprises a solder pad element packaging pattern and solder pad element coordinates; and querying a stencil opening database according to the solder pad element packaging pattern, records in the stencil opening database comprise the following attributes: a solder pad element packaging pattern and a stencil opening pattern; and placing a stencil opening pattern corresponding to a matching solder pad element packaging pattern to an opening layer according to the solder pad element coordinates.

Method and IC Design with Non-Linear Power Rails

The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

Measurement apparatus and a method for determining a substrate grid

A measurement apparatus and method for determining a substrate grid describing a deformation of a substrate prior to exposure of the substrate in a lithographic apparatus configured to fabricate one or more features on the substrate. Position data for a plurality of first features and/or a plurality of second features on the substrate is obtained. Asymmetry data for at least a feature of the plurality of first features and/or the plurality of second features is obtained. The substrate grid based on the position data and the asymmetry data is determined. The substrate grid and asymmetry data are passed to the lithographic apparatus for controlling at least part of an exposure process to fabricate one or more features on the substrate.

Leakage analysis on semiconductor device

A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.

CHIP MODULE STRUCTURE AND METHOD AND SYSTEM FOR CHIP MODULE DESIGN USING CHIP-PACKAGE CO-OPTIMIZATION

A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.

LENGTH-OF-DIFFUSION PROTECTED CIRCUIT AND METHOD OF DESIGN

УСТРОЙСТВО ДЛЯ МОДЕЛИРОВАНИЯ СИСТЕМ МАССОВОГО ОБСЛУЖИВАНИЯ

Изобретение относится к области вычислительной техники, предназначено для моделирования процесса обслуживания двух потоков заявок с различными приоритетами и может быть использовано в устройствах, моделирующих работу систем массового обслуживания. Техническим результатом является обеспечение возможности обслуживания до окончания заявки низкого приоритета по окончании обслуживания заявки высокого приоритета, так как ее обслуживание продолжается с момента после приостановления. Устройство содержит семь элементов И, два триггера, три элемента ИЛИ, два элемента ИЛИ_НЕ, датчик случайных чисел, две группы элементов И по N элементов в каждой группе, где N равно числу разрядов вычитающего счетчика, два вычитающих счетчика и генератор тактовых импульсов. 1 ил.

VERFAHREN ZUR TAKT-GATE-ANALYSE VON ENTWÜRFEN FÜR ELEKTRONISCHE SYSTEME UND ZUGEHÖRIGE SYSTEME, VERFAHREN UND VORRICHTUNGEN

Systeme und Verfahren, die in dieser Offenbarung beschrieben werden, beziehen sich allgemein auf ein Analysieren elektronischer Schaltungsanordnungen und insbesondere auf ein Analysieren einer Effizienz eines Takt-Gatings in den elektronischen Schaltungsanordnungen. Die Analyse kann ein Identifizieren einer verschwendeten Verbreitung von Taktsignalen durch Takt-Gates und/oder für eine Schaltungsanordnung als Ganzes einschließen. In manchen Ausführungsformen kann eine modifizierte Gating-Logik bestimmt werden, welche die Takt-Gating-Effizienz verbessert, zum Beispiel durch Eliminieren mindestens mancher verschwendeter Verbreitungen von Taktsignalen.

Intelligent electric installation system and method based on wearable equipment

Method for automatically cleaning redundant wire

Flip-chip device

Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

Local cell-level power gating switch

A power gating switch is described at a local cell level of an integrated circuit die. In one example a plurality of logic cells have a data input line and a data output line and a power supply input to receive power to drive circuits of the logic cell. A power switch for each logic cell is coupled between a power supply and the power supply input of the respective logic cell to control power being connected from the power supply to the respective logic cell.

Information processing apparatus, computer-readable recording medium, and information processing method

An information processing apparatus includes a memory; and a processor coupled to the memory and the processor that creates module partitioning candidates of a plurality of software codes including one or more input nodes from a plurality of input nodes in a data flow graph and calculates a cost corresponding to a bit width of a signal line of the module partitioning candidates for each of the created plurality of module partitioning candidates, and selects one or more module partitioning candidates having a given cost from the plurality of module partitioning candidates as a partitioning target module based on the calculated cost.

Display apparatus and method of manufacturing the same

A display apparatus and a method of manufacturing the same are disclosed. The display apparatus includes at least one light emitting diode chip, a conductive portion disposed under the light emitting diode chip and coupled to the light emitting diode chip, and an insulating material surrounding the conductive portion. The conductive portion includes a first conductive portion and a second conductive portion, and the insulating material is formed to expose at least a portion of the upper surfaces of the first conductive portion and the second conductive portion.

A METHOD AND A CIRCUIT FOR ADAPTIVE REGULATION OF BODY BIAS VOLTAGES CONTROLLING NMOS AND PMOS TRANSISTORS OF AN IC

A method and a circuit for adaptive regulation of body bias voltages controlling nmos and pmos transistors of an integrated circuit includes a digital circuit, a counter, a control unit and a charge pump. A first ring oscillator monitor measures a period duration of nmos transistors and a second ring oscillator monitor measures a period duration of pmos transistors. A first closed control loop adaptively regulates the performance cn of the body bias controlled nmos transistors of the digital circuit by comparing the measured period duration of nmos dominated first ring oscillator monitor to a period duration of a reference clock and a second closed control loop adaptively regulating the performance cp of the body bias controlled pmos transistors of the digital circuit by comparing the measured period duration of pmos dominated second ring oscillator monitor to the period duration of the reference clock.

CELL STRUCTURES AND SEMICONDUCTOR DEVICES HAVING SAME

A semiconductor device includes active areas formed as predetermined shapes on a substrate. The device also includes a first structure having at least two contiguous rows including: at least one instance of the first row, and at least one instance of the second row. The device also includes the first structure being configured such that: each of the at least one instance of the first row in the first structure having a first width in the first direction; and each of the at least one instance of the second row in the first structure having a second width in the first direction, the second width being substantially different than the first width. The device also includes a second structure having an odd number of contiguous rows including: an even number of instances of the first row, and an odd number of instances of the second row.

METHODS AND APPARATUS FOR PROFILE-GUIDED OPTIMIZATION OF INTEGRATED CIRCUITS

Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.

WORK SUPPORT DEVICE, WORK SUPPORT SYSTEM, AND ANALYSIS PROGRAM

A work support device according to the invention detects circuit symbols and conducting wires from circuit drawing data that does not have information unique to a circuit part, and by matching the detection result with a result of tracing a conduction path by handwriting by a worker, the circuit part and the conducting wire through which the conduction path passes are specified.

Interconnect structure for logic circuit

Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

Systems and methods for implementing a machine perception and dense algorithm integrated circuit and enabling a flowing propagation of data within the integrated circuit

Systems and methods of propagating data within an integrated circuit includes: identifying a coarse data propagation path for distinct subsets of data of an input dataset that includes: setting inter-core data movements for the distinct subsets of data, the inter-core data movements defining a predetermined propagation of a given subset of data between two or more of a plurality of cores of an integrated circuit array of the integrated circuit; identifying a granular data propagation path for each distinct subset of data that includes: setting intra-core data movements for each distinct subset of data, the intra-core data movements defining a predetermined propagation of the given subset of data within one or more of the plurality of cores of the integrated circuit array of the integrated circuit; enabling a flow of the input dataset within the integrated circuit based on the coarse data propagation path and the granular propagation path.

VIRTUALIZATION, VISUALIZATION AND AUTONOMOUS DESIGN & DEVELOPMENT OF OBJECTS

An integrated platform is provided that enables the various steps of development operations from design to sales, the virtualization, the visualization and the interpretation of a device so it may be fully created (designed), viewed, manipulated, packaged, simulated, tested, published and marketed right from within the platform. The resulting virtual device (VD) may be a multi-layered, -dimensional, -angular, -disciplinary, -documentarian, -service, manipulated and used in multiple ways. The provided VD may include visual representations of the VD via a traditional display device in a non-immersive environment and/or within an immersive environment via new virtual-reality (VR) devices. For instance, a user may create, manipulate, in real-time, layered multi-dimensional views of a VD in a virtual-reality, augmented-reality (AR), augmented virtual-reality (AVR), and/or mixed-reality (MR) environments.

ЯЧЕЙКА КОММУТИРУЮЩЕЙ СРЕДЫ

Ячейка коммутирующей среды, содержащая схемы И, схемы И-НЕ, схемы ИЛИ и триггеры управления, причем первые входы схем И-НЕ соединены с единичными выходами соответствующих триггеров управления, а вторые входы подключены к выходу схемы И координатной выборки узла, а входы приемных схем И-НЕ подключены к дополнительным шинам запрещения распространения волны поиска кратчайшей трассы, выход схемы И-НЕ опроса состояний приемных схем И-НЕ соединен через схему ИЛИ с нулевым входом триггера управления, единичный выход которого соединен с первым входом выходной схемы И-НЕ анализа принадлежности ячейки трассе, а также с входом приемной схемы И-НЕ, кроме того, два других входа выходной схемы И-НЕ анализа принадлежности ячейки трассе соединены один с нулевым выходом триггера управления смежной ячейки, другой - с выходом входной схемы И-НЕ анализа принадлежности ячейки трассе, отличающаяся тем, что содержит две схемы ИЛИ-НЕ для запрещения волнового процесса, входы которых соединены с входными шинами ...

УСТРОЙСТВО ДЛЯ РЕШЕНИЯ ЗАДАЧИ О НАЗНАЧЕНИЯХ

Изобретение относится к области вычислительной техники и может быть использовано для получения точного решения задачи о назначениях. Техническим результатом является повышение надежности устройства. Устройство содержит генератор тактовых импульсов, группу из n счетчиков, три элемента И, группу из n дешифраторов, две группы регистров, группу из n первых сумматоров, сумматор, схему сравнения, блок вторых элементов И, третий регистр, элемент задержки, группу из n*n триггеров, группу из n*n третьих блоков элементов И, группу из n шифраторов. 1 ил.

Analogue circuit design

An analogue circuit design apparatus is configured to receive information representing technical requirements for the analogue circuit 301, wherein the technical requirements comprising circuit performance requirements, and manufacturing requirements associated with a specific set of manufacturing process related rules. The analogue circuit design apparatus is configured to identify a plurality of potential analogue circuit design architectures, for satisfying the circuit performance requirement, that will satisfy the at least one manufacturing requirement. An initial analogue circuit design architecture is selected as a current analogue circuit design architecture from among this plurality of potential architectures 303, wherein the selection of the initial analogue circuit design is dependent on the set of manufacturing process related rules. The current design architecture is used to produce a current design 305 and it is determined if the current design will meet the at least one circuit ...

ADAPTIVE MULTI-TIER POWER DISTRIBUTION GRIDS FOR INTEGRATED CIRCUITS

The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

Design method for efficiently extracting central line of integrated circuit layout photomask

ESD device design method, Pcell, process design package and ESD protection circuit design method

The invention provides an ESD (Electro-Static Discharge) device design method, a PCell, a process design package and an ESD protection circuit design method, and aims to effectively integrate a mapping relation between a pressure bearing value and a physical parameter of an ESD device of a corresponding type into the PCell, so that when the ESD device of the type is designed, the physical parameter of the ESD device of the corresponding type can be effectively integrated into the PCell. According to the method, the pressure bearing performance of the ESD device of the type under the corresponding physical parameters can be visually read on the visual interface of the PCell, the development efficiency of an ESD protection circuit is improved, and the physical size design difficulty can be reduced for various types of ESD devices. Besides, based on industrial standard test data related to the performance of the produced ESD device, the mapping relation between the pressure bearing value of ...

Method and device for correcting optical proximity effect of layout and storage medium

The invention relates to the technical field of integrated circuit layout design, in particular to a method and device for conducting optical proximity effect correction on a layout and a storage medium, and can solve the problem that a large amount of repeated calculation is caused by conducting multiple times of correction on the same graph to a certain extent. The method for correcting the optical proximity effect of the layout comprises the steps that a bounding box of a unit in the integrated circuit layout is obtained, the area of the bounding box corresponding to the unit is not smaller than a first preset threshold value, the unit comprises at least one subunit, and the subunit is a graph with a geometrical shape; combining any adjacent preset number of subunits in the unit to obtain a first combined subunit; comparing the first combined subunit with other adjacent subunits in the unit to determine a first repeated subunit; and jointly inputting the first repeated subunit and the ...

Micro-electro-mechanical system (MEMS) and related actuator bumps, methods of manufacture and design structures

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes and a contact point on a substrate. The method further includes forming a MEMS beam over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.

Systems and methods for improving design performance through placement of functional and spare cells by leveraging LDE effect

Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design. According to some embodiments, conducting placement and optimization further includes: moving the at least one spare cells to locations to ...

PHYSICALLY UNCLONABLE CAMOUFLAGE STRUCTURE AND METHODS FOR FABRICATING SAME

An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.

Analog Hardware Realization of Trained Neural Networks

Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components including a plurality of operational amplifiers and a plurality of resistors. Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection. The method also includes generating a resistance matrix for the weight matrix. Each element of the resistance matrix corresponds to a respective weight of the weight matrix and represents a resistance value.

METHODS FOR OPTIMIZING CIRCUIT PERFORMANCE VIA CONFIGURABLE CLOCK SKEWS

An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

REDUCTION OR ELIMINATION OF PATTERN PLACEMENT ERROR IN METROLOGY MEASUREMENTS

Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.

CRITICAL DIMENSION UNIFORMITY

A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

Interactive information system with modular structure

An interactive information system is disclosed. The interactive information system includes (i) an interactive module arranged in a first frame including a display module displaying a graphic user interface (GUI), a touch input module receiving a user input to the GUI, and an interactive module bridge board transmitting inter-frame signals including electrical signals of the display module and the touch input module, (ii) a control module arranged in a second frame to generate the GUI and to perform a function of the interactive information system based on the user input, and (iii) an internal cable connecting the interactive module bridge board and the control module to transmit inter-frame signals between the first frame and the second frame. The internal cable is further to transmit power to the interactive module bridge board which transmits power to the display module and the touch input module.

ANALOGUE CIRCUIT DESIGN

ЯЧЕЙКА КОММУТИРУЮЩЕЙ СРЕДЫ

Ячейка коммутирующей среды, содержащая схемы "И", схемы "И-НЕ", схемы "ИЛИ" и триггеры управления, причем первые входы схем "И-НЕ" соединены с единичными выходами соответствующих триггеров управления, а вторые входы подключены к выходу схемы "И" координатной выборки узла, а входы приемных схем "И-НЕ" подключены к дополнительным шинам запрещения распространения волны поиска кратчайшей трассы, выход схемы "И-НЕ" опроса состояний приемных схем "И-НЕ" соединен через схему "ИЛИ" с нулевым входом триггера управления, единичный выход которого соединен с первым входом выходной схемы "И-НЕ" анализа принадлежности ячейки трассе, а также с входом приемной схемы "И-НЕ", кроме того, два других входа выходной схемы "И-НЕ" анализа принадлежности ячейки трассе соединены один с нулевым выходом триггера управления смежной ячейки, другой - с выходом входной схемы "И-НЕ" анализа принадлежности ячейки трассе, отличающаяся тем, что содержит схему суммирование по модулю два анализа встречи волн, первый вход которой ...

Analogue circuit design

Design method of onboard computer board-level low-direct-current impedance coplanar electromagnetic band-gap power supply layer

Hardware layer design method based on embedded operating system

The invention relates to the technical field of hardware layer design, in particular to a hardware layer design method based on an embedded operating system, which comprises the following steps of: analyzing an application program interface stored in a current hardware layer, and acquiring an application program interface stored in a configured hardware layer of a current operating system; receiving a current operation system running task, and analyzing an application program interface which needs to be configured for the running task; searching in an application program interface stored in a hardware layer according to the analyzed application program interface which needs to be configured for the operation task, and feeding back an application program interface searching process to a system end user in real time; according to the method, an intelligent hardware layer design mode can be brought to an existing embedded operating system, and in the step execution process of the method, intelligent ...

Adaptive multi-layer power distribution grid for integrated circuits

The embodiment of the invention relates to an adaptive multi-layer power distribution grid for an integrated circuit. Layout and routing phases for a hard macro comprising a plurality of tiles are modified such that some of the tiles are assigned a more robust grid layer and such that other of the tiles are assigned a less robust grid layer.

TRANSMISSION PATH DESIGN ASSISTANCE SYSTEM, TRANSMISSION PATH DESIGN ASSISTANCE METHOD, AND COMPUTER READABLE MEDIUM STORING TRANSMISSION PATH DESIGN ASSISTANCE PROGRAM

A transmission path design assistance system assisting in the design of a transmission path with different reflection specification values for each frequency is obtained. The transmission path design assistance system includes: an acquisition unit to acquire reflection specification values of a reflection characteristic of a transmission path to be designed and a constraint of characteristic impedance distribution of the transmission path; and a computation processing unit including: a reflection characteristic calculation unit to calculate the reflection characteristic from inputted characteristic impedance distribution; a reflection characteristic modification unit to modify, on the basis of the reflection specification values acquired by the acquisition unit, the reflection characteristic calculated by the reflection characteristic calculation unit; a characteristic impedance distribution calculation unit to calculate characteristic impedance distribution from the reflection characteristic ...

PUF cell array, system and method of manufacturing same

A physically unclonable function (PUF) cell array includes a first PUF cell in a first column in a first direction, and a first row in a second direction, and a second PUF cell in a second row in the second direction. The first PUF cell includes a first set of conductive structures extending in the first and second direction, being on a first metal layer, and including a first and a second conductive structure extending in the first direction. The second PUF cell includes a second set of conductive structures extending in the first direction and second direction, being on the first metal layer and including a third and a fourth conductive structure extending in the first direction. The first and third conductive structures, or the second and fourth conductive structures are symmetric to each other with respect to a central line of the first and second PUF cells.

УСТРОЙСТВО ПОИСКА НИЖНЕЙ ОЦЕНКИ РАЗМЕЩЕНИЯ В ПОЛНОСВЯЗНЫХ МАТРИЧНЫХ СИСТЕМАХ ПРИ ОДНОНАПРАВЛЕННОЙ ПЕРЕДАЧЕ ИНФОРМАЦИИ

Изобретение относится к области цифровой вычислительной техники и предназначено для моделирования комбинаторных задач при проектировании вычислительных систем (ВС), например для размещения процессов (задач, файлов, данных, управляющих процессов и т.д.). Техническим результатом является расширение области применения устройства за счет введения средств поиска нижней оценки размещения в полносвязных матричных системах при однонаправленной передаче информации по критерию минимизации интенсивности взаимодействия процессов и данных. Устройство содержит регистры сдвига, блок формирования перестановок, блок постоянной памяти, блок запоминания лучшего варианта, коммутатор, АЛУ, дешифраторы, реверсивный счетчик ячеек, блок оперативной памяти, счетчики, умножитель, сумматор, регистры, элементы сравнения, вычитатель, триггеры, электронную модель графа, группу элементов ИЛИ, группу элементов И, элементы И, блоки элементов ИЛИ, одновибраторы, элементы задержки, блок формирования нижней оценки, содержащий ...

УСТРОЙСТВО ДЛЯ МОДЕЛИРОВАНИЯ СИСТЕМ МАССОВОГО ОБСЛУЖИВАНИЯ

Изобретение относится к вычислительной технике. Технический результат заключается в расширении функциональных возможностей за счет моделирования обслуживания заявок в трехрежимных СМО при различных программах функционирования с учетом отказов и восстановлений ее элементов. Устройство для моделирования систем массового обслуживания, содержащее генератор случайного потока импульсов, счетчики импульсов, элементы запрета, элементы И, триггеры, элементы ИЛИ, реверсивный счетчик, блок формирования программы функционирования СМО, блоки моделирования первого и второго рабочих режимов СМО. Каждый из блоков моделирования первого и второго рабочих режимов СМО содержит генератор тактовых импульсов, элемент ИЛИ, счетчик импульсов, элемент И и группу блоков моделирования выполнения работ (обслуживания заявок), каждый из которых содержит триггер, элементы И, элементы ИЛИ, счетчик времени наработки, отказов, времени восстановления, первый генератор случайных импульсов, первый формирователь импульсов, элементы ...

Internal resistor of resistance type bias magnetic treatment device and design method thereof

Material number analysis method and system

Method, system and device for adjusting clock skew

Matching circuit design method and device

The invention provides a matching circuit design method and device and a computer storage medium. The matching circuit design method comprises the following steps: acquiring a corresponding relation between a frequency point of a first-stage network and output impedance and a corresponding relation between a frequency point of a second-stage network and input impedance; based on the ideal states of the first-stage network and the second-stage network, determining ABCD parameters of a matching circuit; constructing an RS parameter of the matching circuit by using the corresponding relation between the frequency point of the first-stage network and the output impedance, the corresponding relation between the frequency point of the second-stage network and the input impedance and the ABCD parameter; and optimizing the RS parameter based on the matching target of the first-stage network and the second-stage network to obtain an optimal solution satisfying the matching target, and determining ...

Design method and device for updating PCB packaging in batches and terminal equipment

The embodiment of the invention provides a design method and device for updating PCB packages in batches and terminal equipment, and relates to the field of PCB design, and the design method for updating the PCB packages in batches comprises the steps: obtaining a modified package pattern after each to-be-updated package pattern in each PCB is modified, and storing all the modified package patterns in a specified folder; creating a text list in a specified folder, and listing packaging names corresponding to all the modified packaging patterns into the text list; and updating each to-be-updated packaging pattern based on all the modified packaging patterns and all the packaging names in the text list. According to the method and the device, the problems of wrong selection and missing selection caused by manual identification selection can be avoided, and correction and updating of PCB packaging can be simpler, so that the labor cost and the time cost can be reduced.

Chip packaging method and device

The invention provides a chip packaging method and device, an initial packaging structure comprises a packaging substrate and a chip arranged at one side of the packaging substrate, and the method comprises the following steps: determining the position of a packaging ring based on the initial packaging structure, and arranging the packaging ring at the position of the packaging ring; performing flip-chip bonding on the chip and the packaging substrate to obtain an updated packaging structure; simulation processing is carried out based on the parameters of the updated packaging structure, and a simulation processing result is obtained; and determining a first area on the chip based on the simulation result, and obtaining a target packaging structure. The packaging ring is arranged before the chip and the packaging substrate are subjected to flip-chip bonding, so that warping and deformation of the packaging substrate in the flip-chip bonding process are reduced. The chip is subjected to ...

DIELET DESIGN TECHNIQUES

Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

TRACE LENGTH ON PRINTED CIRCUIT BOARD (PCB) BASED ON INPUT/OUTPUT (I/O) OPERATING SPEED

A wireline communications system is described. The wireline communications system includes a printed circuit board (PCB). The wireline communications system also includes a system on chip (SoC) die on the PCB. The wireline communications system further includes an external memory device coupled to a memory interface of the SoC die. The external memory device is coupled to the memory interface of the SoC die through a PCB trace. A length of the PCB trace is configured according to an operating speed of the memory interface (308).

MEMORY ELEMENT GRAPH-BASED PLACEMENT IN INTEGRATED CIRCUIT DESIGN

A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Efficient topological compilation for metaplectic anyon model

Certain ensembles of metapletic anyons allow for topologically protected encoding and processing of quantum information. Such processing is done by sequences of gates (circuits) drawn from a certain basis of unitary metaplectic gates. A subject unitary operator required for the desired processing can be approximated to any desired precision by a circuit that has to be effectively and efficiently synthesized on a classical computer. Synthesis methods use unitary reflection operators that can be represented either exactly or by ancilla-assisted approximation over the basis of metaplectic gates based on cost-optimizing determinations made by the synthesis algorithm.

Memory element graph-based placement in integrated circuit design

A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.

Timing optimization of memory blocks in a programmable IC

Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.

MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD

A memory device includes a bit line, a source line, a plurality of word lines, and a memory cell. The memory cell includes a plurality of memory strings coupled in parallel between the bit line and the source line. Each of the plurality of memory strings includes a plurality of memory elements coupled in series between the bit line and the source line, and electrically coupled correspondingly to the plurality of word lines.

Leakage analysis on semiconductor device

A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.

And optimization of physical cell placement

In an embodiment, a method for designing an integrated circuit with target characteristics uses a physical design graph. The physical design graph includes a plurality of physical design sub-configurations, each of the plurality of physical design sub-configurations including a placement of a group of physical cells and having annotated characteristics. The method includes partitioning an integrated circuit electrical design into a plurality of electrical design sub-configurations, including a specific electrical design sub-configuration requiring a specific group of the physical cells. The method includes selecting from the physical design graph, based on the required specific group of the physical cells and the target characteristics, a physical design sub-configuration including the specific group of the physical cells in a specific placement and having the target characteristics. The method includes determining an integrated circuit physical design for manufacturing the integrated circuit ...

Predictive antenna diode insertion in a macro having a clock mesh

Embodiments of the invention include protecting against antenna violations in a macro having a clock mesh. Aspects include obtaining a design of the macro, the design including a clock layer having a plurality of clock pins and determining a longest vertical wire and a longest horizontal wire allowed based on a design of the clock mesh. Aspects also include identifying, based at least in part on the longest vertical wire and the longest horizontal wire, a plurality of checkbox regions for a clock pin of the plurality of clock pins and calculating a total diffusion area for each of the plurality of checkbox regions. Aspects further include adding, to the design of the macro, an antenna diode to the clock pin based on a determination that the total diffusion area for any of the plurality of checkbox regions is less than a threshold value.

METHODS AND APPARATUS FOR IN-FIELD THERMAL CALIBRATION

Methods and apparatus for in-field thermal calibration are disclosed. A disclosed example apparatus includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to execute the instructions to determine that a system on chip (SOC) package is deployed, the SOC package deployed with a default first thermal model, in response to the determination that the SOC package is deployed, monitor at least one temperature of the SOC package from a sensor and power usage of the SOC package, calibrate a second thermal model based on the at least one temperature and the power usage, and publish the calibrated second thermal model for control of the SOC package.

Signal transmission method and apparatus, and display device

A signal transmission method is applied to a receiving terminal so as to improve the anti-interference capability of the signals on the transmission line, and the signal transmission method includes: receiving a signal sent by a transmitting terminal through a transmission line; detecting whether there is a transmission error in the received signal; and when there is a transmission error in the received signal, adjusting at least one parameter of specified parameters affecting an anti-interference capability of signals on the transmission line, and/or controlling the transmitting terminal to adjust the at least one parameter of the specified parameters affecting the anti-interference capability of signals on the transmission line.

Systems and methods for obfuscating a circuit design

Systems and methods for generating an integrated circuit (IC) chip design are described. One of the methods includes receiving, on a data sheet, by a server, electrical parameters of a system on chip (SoC) to be designed. The method further includes receiving physical parameters of the SoC on the data sheet, generating a first design of the SoC according to the electrical parameters and the physical parameters, and receiving test parameters for testing the first design. The method further includes testing, via a design verification tool, the first design by applying the test parameters to the first design, receiving a second design of a second SoC, and coupling the second design to the first design to generate a first IC chip design. The method includes arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.

RECIPROCAL QUANTUM LOGIC (RQL) CIRCUIT SYNTHESIS

A method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit.

Process mapping method of input/output port

Automated optimization of large scale quantum circuits using continuous parameters

ANALOGUE CIRCUIT DESIGN

An analogue circuit design apparatus is disclosed comprising a primary design unit and a plurality of secondary design units. The primary design unit is configured to: identify a plurality of circuit portions for forming the analogue circuit; determine for each circuit portion respectix/e technical criteria; and provide the respective technical criteria to at least one of a plurality of secondary design units. Each of the plurality of secondary design units is configured to: design a respective circuit portion based on the technical criteria for that respective circuit portion; and output a resulting initial design of the respective circuit portion. The primary design unit is further configured to obtain, a set of designs comprising a respective design for each circuit portion, generate, at least an initial design for the analogue circuit, based on the set of designs, simulate an analogue circuit based on the generated design and verify whether or not the analogue circuit meets the technical ...

LAYER DISTRIBUTION METHOD CONSIDERING BUS AND NON-BUS NETWORKS

The present invention relates to construction of a layer distributor of a super-large-scale integrated circuit in the technical field of integrated circuit computer aided designs. Due to continuous development of the manufacturing industry and appearance of a system-on-chip design concept, the number of buses between modules on a chip is rapidly increased and becomes a decisive factor of performance and power consumption. Therefore, the important influence of the bus on the chip design is fully considered, and the layer distributor considering the bus and non-bus networks is provided. The distributor is based on the following three effective methods: 1) a method for determining network priority based on a multi-element cost function; 2) a layer adjustment strategy based on a lookup table, the layer adjustment strategy comprising a layer adjustment technology with a limited number of layers and a layer adjustment technology with an unlimited number of layers; and 3) a bus maximum time series ...

Automated optimization of large-scale quantum circuits with continuous parameters

The disclosure describes the implementation of automated techniques for optimizing quantum circuits of the size and type expected in quantum computations that outperform classical computers. The disclosure shows how to handle continuous gate parameters and report a collection of fast algorithms capable of optimizing large-scale-scale quantum circuits. For the suite of benchmarks considered, the techniques described obtain substantial reductions in gate counts. In particular, the techniques in this disclosure provide better optimization in significantly less time than previous approaches, while making minimal structural changes so as to preserve the basic layout of the underlying quantum algorithms. The results provided by these techniques help bridge the gap between computations that can be run on existing quantum computing hardware and more advanced computations that are more challenging to implement in quantum computing hardware but are the ones that are expected to outperform what can ...

Emulation system supporting four-state for sequential logic circuits

An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

Multi-Input Logic Circuitry

Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.

METHOD OF MAKING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A method of making a semiconductor structure includes forming a plurality of gate electrodes over a plurality of active regions. The method further includes increasing a width of a portion of each of the plurality of gate electrodes between adjacent active regions of the plurality of active regions, wherein increasing the width of the portion of each of the plurality of gate electrodes comprises increasing the width of less than an entirety of each of the plurality of gate electrodes between the adjacent active regions. The method further includes removing a central region of each of the plurality of gate electrodes, wherein the central region has the increased width, and removing the central region comprises removing less than an entirety of the portion of each of the plurality of gate electrodes.

INTERACTIVE INFORMATION SYSTEM WITH MODULAR STRUCTURE

An interactive information system includes a first frame, a second frame, and a first inter-frame cable. A first interactive module is arranged in the first frame and includes a first display module; a first touch input module; at least one first user input device; a first control module bridge board configured to transmit intra-frame electrical signals; a first interactive module bridge board configured to transmit inter-frame signals; and a first intra-frame cable. A control module is arranged in the second frame and includes a logic module configured to generate the first GUI and to perform function of the interactive information system based on user inputs. The first interactive module and the control module are electrically coupled via only the first inter-frame cable. Both the first frame and the second frame contain an electro-magnetic (EM) shielding material.

Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices

Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes dielectric layers, a conductive layer disposed in the dielectric layers, and a via layer disposed in the dielectric layers proximate the conductive layer. An underball metallization (UBM) layer is disposed in the dielectric layers proximate the via layer. A first connector coupling region is disposed in the via layer and the UBM layer. A via layer portion of the first connector coupling region is coupled to a first contact pad in the conductive layer. A second connector coupling region is disposed in the UBM layer. The second connector coupling region is coupled to a conductive segment in the UBM layer and the via layer. The second connector coupling region is coupled to a second contact pad in the conductive layer by the conductive segment.

METHOD FOR DETERMINING A HOUSING FOR ELECTRONIC COMPONENTS

Analogue circuit design

An analogue circuit design apparatus comprises a primary design unit and a plurality of secondary design units. The primary design unit is configured to: identify a plurality of circuit portions for forming the analogue circuit; determine for each circuit portion respective technical criteria; and provide the respective technical criteria to at least one of a plurality of secondary design units. Each of the plurality of secondary design units is configured to: design a respective circuit portion based on the technical criteria for that respective circuit portion; and output a resulting initial design of the respective circuit portion. The primary design unit is further configured to obtain, a set of designs comprising a respective design for each circuit portion, generate, at least an initial design for the analogue circuit, based on the set of designs, simulate an analogue circuit based on the generated design and verify whether or not the analogue circuit meets the technical requirements ...

Analogue circuit design

An analogue circuit design apparatus is disclosed comprising a primary design unit and a plurality of secondary design units. The primary design unit is configured to: receive information representing technical requirements for the analogue circuit; identify, based on the received information, a plurality of circuit portions for fanning the analogue circuit; determine, for each circuit portion of the plurality circuit portions, respective technical criteria for that circuit portion; produce a set of designs comprising a respective design for each circuit portion: for at least one circuit portion of the plurality of circuit portions obtain information relating to parasitics that will be experienced in the analogue circuit if the analogue circuit were to include that designed circuit portion; adapt the design of at least one circuit portion based on the obtained information relating to parasitics; and output a complete circuit design including at least one circuit portion adapted based on ...

Target correction code determination method, device, and storage medium

Relay protection secondary loop simulation training system

DESIGN METHOD OF DUMMY PATTERN LAYOUT

A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

INTEGRATED CIRCUIT WITH ASYMMETRIC MIRRORED LAYOUT ANALOG CELLS

A device includes a first cell active area asymmetrically positioned in a first device column between a first barrier line and a second barrier line, a second cell active area asymmetrically positioned in a second device column between the first barrier line and a third barrier line, where the first cell has a first cell length in a first direction perpendicular to the first barrier line which is three times a second cell length in the first direction. The first cell active area and the second cell active area are a first distance from the first barrier line, and the first cell active area is a second distance from the second barrier line, and the second cell active area is the second distance away from the third barrier line.

METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS

In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

INTEGRATED CIRCUIT HAVING ANGLED CONDUCTIVE FEATURE

An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions ...

Method for designing vehicle controller-only semiconductor based on die and vehicle controller-only semiconductor by the same

The present invention relates to a method for designing a die-based vehicle controller-only semiconductor and a vehicle controller-only semiconductor manufactured by the same, and breaks the conventional semiconductor process to design and manufacture a novel conceptual vehicle controller-only semiconductor, EIP (ECU in Package), through a fusion of a new semiconductor process technique with a controller system technique, thereby obtaining an effect of capable of implementing a high performance/high quality semiconductor in micro-miniature size/ultra-light weight in a short time period.

TAPPED INDUCTOR VOLTAGE CONTROLLED OSCILLATOR

A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element. The inductive element has a plurality of conductive segments forming a physical loop. The inductive element has electrical connections on the physical loop to the plurality of conductive segments forming at least one electrical loop disposed within an interior space formed by the physical loop. The amplifier has an input and an output, the input coupled to a first conductive segment forming a first impedance and the output coupled to a second conductive segment forming a second impedance.

SYSTEMS AND METHODS FOR MODELING WIRELESS POWER TRANSFER SYSTEMS INCLUDING STACKED RING RESONATORS

Model training system and method

The invention provides a model training system and a model training method, which are used for realizing efficient transmission of data among a large number of processors. The system comprises a first group, the first group comprises an MEMS and S * C processors, S is the number of nodes in the first group, C is the number of processors in one node, and both S and C are positive integers; the MEMS is used for constructing an optical transmission channel between any two nodes in the S nodes; and the S * C processors are used for jointly training the model. In one iteration of the joint training model, the S * C processors are used for running model training in the respective processors to obtain respective corresponding data, and at least two of the S * C processors transmit target data through optical transmission channels, wherein the processor receiving the target data can be used for adjusting parameters of model training in the processor according to the target data.

Finfet Technology semiconductor layout

Testing SoC with portable scenario models and at different levels

A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Semiconductor structures with deep trench capacitor and methods of manufacture

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Self-biased current trimmer with digital scaling input

In an embodiment, a circuit provided by the present invention includes a transistor connected to allow current to flow from a voltage supply to an output port. The circuit further includes a resistance ladder digital-to-analog converter (RDAC) configured to receive a digital input that indicates a voltage scaling factor. The RDACis further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA). The circuit further includes an amplifier having an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA), and a non-inverting input connected to the output port of the first transistor.

CONDUCTOR SCHEME SELECTION AND TRACK PLANNING FOR MIXED-DIAGONAL-MANHATTAN ROUTING

The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

SEMICONDUCTOR DEVICE INCLUDING TRIMMED-GATES AND METHOD OF FORMING SAME

A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are substantially free of extending into the gap.

System and Method for Placing Integrated Circuit Functional Blocks According to Dataflow Width

Macroblock placement for an integrated circuit register-transfer level design is enhanced by tagging blocks having a set of functions as usage element definitions that have a minimum input signal width, such as tags added to a netlist of the design. Tagged blocks aid preferred and regular placement of library cells that are morphed to adapt for reduced congestion and improved utilization.

System for creating layout pattern for manufacturing mask rom, mask rom manufactured using the system, and method for creating mask pattern

When generating a temporary ROM code file and a design information file, a host server generates a dedicated ROM compiler and an intermediate file associated with the dedicated ROM compiler. In a workstation, the dedicated ROM compiler is executed, whereby the contents of a design information file are changed to the contents corresponding to a correct ROM code. The dedicated ROM compiler is specifically designed to be capable of changing only a particular design parameter and the design information file associated with the temporary ROM code file.

Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness

Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met.

Computing device and crosstalk information detection method

A computing device and a method reads a circuit board layout file from a storage device, and selects a first signal transmission line from circuit board layout file as a target line. The computing device and method computes a distance between the target line and the aggressor line corresponding to each unit sample length. If the distance is more than or equal to a height of a sample region, the computing device and method defines the height of the sample region as a crosstalk space between the target line and the aggressor line corresponding to a unit sample length. Otherwise, if the distance is less than the height of the sample region, the computing device and method defines the distance as the crosstalk space between the target line and the aggressor line corresponding to the unit sample length.

Computing device and method for checking signal transmission lines

A computing device and a method selects a signal transmission line from a circuit board, computes an actual length of each line segment of the selected signal transmission line, and computes an actual distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. If each actual length is less than or equal to a corresponding reference length and each actual distance is more than or equal to a corresponding reference distance, the device and method determines a design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is more than a corresponding reference length, or if any actual distance is less than a corresponding reference distance, the device and method determines the design of the signal transmission line does not satisfy the design standards.

Design and verification of 3d integrated circuits

A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.

Intensity selective exposure photomask

An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.

Apparatus and system for implementing variable speed scan testing

In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.

Layout Decomposition Based on Partial Intensity Distribution

Layout design data are decomposed for double dipole lithography based on partial intensity distribution information. The partial intensity distribution information is generated by performing optical simulations on the layout design data. The layout decomposition may further be adjusted during an optical proximity correction process. The adjustment may utilize the partial intensity distribution information.

Electrical-Thermal Co-Simulation with Joule Heating and Convection Effects for 3D Systems

In a method for simulating temperature and electrical characteristics within an circuit, a temperature of at least one volume within the circuit as a function of a resistance within the at least one volume is repeatedly calculated and the resistance as a function of the temperature is repeatedly calculated until the temperature is within a predetermined tolerance of a previous temperature result and until the resistance is within a predetermined tolerance of a previous resistance result. Once the temperature is within a predetermined tolerance of the previous temperature result and the resistance is within a predetermined tolerance of the previous resistance, then an output indicative of the temperature is generated.

Manufacturing method, manufacturing program and manufacturing system for semiconductor device

A method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor integrated circuit; carrying out calculation for a transferred image in the physical layout; carrying out calculation for a signal delay based on the physical layout, and obtaining a wiring not meeting a specification having the signal delay previously set therein; and setting a portion into which a repeater is to be inserted based on at least one result of results obtained from the information on the graphic and calculation for the transferred image, respectively, with respect to the wiring not meeting the specification.

Electronic design automation object placement with partially region-constrained objects

A global placer receives a plurality of regions, each region occupying a sub-area of a design area. receives a plurality of movebound objects, each movebound object associated with a region. The global placer receives a plurality of unconstrained objects, each unconstrained object associated with no region. The global placer receives a tolerance, wherein the placement tolerance defines a coronal fringe to at least one region. The global placer initially placing the plurality of movebound objects and unconstrained objects. The global placer iterates over objects without preference to region-affiliation to select an object, wherein the objects are comprised of the plurality of movebound objects and plurality of unconstrained objects. The global placer determines whether movebound object is within the tolerance of a region associated with the movebound object.

Method for designing wiring topology for electromigration avoidance and fabrication method of integrate circuits including said method

A method for designing wiring topology for electromigration avoidance, which is composed of multiple sources, multiple sinks and multiple wires, is disclosed. The steps of said method to get an optimal topology includes: 1. calculating the length of all the wires to choose one of the wires with the shortest length as a feasible wire, 2. deciding a capacity of the feasible wire, 3. deciding the capacities of the other wire according to the capacity of the feasible wire, a flow of the source of the feasible wire and a flow of the sink of the feasible wire, 4. comparing the length of the other wires to select another feasible wire, 5. repeating said steps until finding all feasible wires for constructing a feasible topology, 6. creating a flow network according to the feasible topology, 7. iteratively checking if a negative cycle exists in the flow network and removing it until no more negative cycles.

Printed circuit board design assisting device, method, and program

A printed circuit board design assisting device includes a frame ground extraction section that extracts a ground pattern that is provided in a surface layer of a printed circuit board and that is to be connected to a metal component from design data on the printed circuit board stored in a design data storage section to store information for specifying the ground pattern in a data storage section, an electrostatic discharge determination section that performs a determination as to electrostatic discharge for the ground pattern specified from the information stored in the data storage section to store a determination result in a determination result storage section, and an output section that outputs the determination result stored in the determination result storage section.

Semiconductor layer forming method and structure

A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.

Method for Integrated Circuit Manufacturing and Mask Data Preparation Using Curvilinear Patterns

A method for manufacturing a semiconductor device is disclosed, wherein during the physical design process, a curvilinear path is designed to represent an interconnecting wire on the fabricated semiconductor device. A method for fracturing or mask data preparation (MDP) is also disclosed in which a manhattan path which is part of the physical design of an integrated circuit is modified to create a curvilinear pattern, and where a set of charged particle beam shots is generated, where the set of shots is capable of forming the curvilinear pattern on a resist-coated surface.

Pattern-Dependent Proximity Matching/Tuning Including Light Manipulation By Projection Optics

Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).

Optimization of Source, Mask and Projection Optics

Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein, and preferably including optimizing a source, a mask, and the projection optics. The projection optics is sometimes broadly referred to as “lens”, and therefore the joint optimization process may be termed source mask lens optimization (SMLO). SMLO is desirable over existing source mask optimization process (SMO), partially because including the projection optics in the optimization can lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics. The projection optics can be used to shape wavefront in the lithographic projection apparatus, enabling aberration control of the overall imaging process. According to the embodiments herein, the optimization can be accelerated by iteratively using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).

Clock Optimization with Local Clock Buffer Control Optimization

A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

Printed circuit board for use in gigabit-capable passive optical network and method for laying out the printed circuit board

A method for laying out a printed circuit board for use in a gigabit-capable passive optical network includes the steps of providing a printed circuit board and laying out an analog circuit module, an analog-to-digital conversion module, a signal processing module, an optoelectronic transmitting and receiving module, and a power module on the printed circuit board. The printed circuit board has a first periphery and an opposing second periphery. The analog circuit module and the optoelectronic transmitting and receiving module are laid out at the first periphery of the printed circuit board. The power module is laid out at the second periphery of the printed circuit board. Electromagnetic wave generated by a power IC inserted in the power module does not interfere with data transmission taking place at the optoelectronic transmitting and receiving module. Furthermore, a printed circuit board for use with the method is proposed.

Robust design using manufacturability models

The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.

Mask revision recording circuit for a memory circuit

A mask revision recording circuit for a memory circuit includes a mask recording module and a reading unit. The mask recording module includes a plurality of mask recording units, and a layout of each mask recording unit corresponds to all masks of a layout of the memory circuit. The reading unit is coupled to the mask recording module for reading information of the mask recording module corresponding to a mask revision of the memory circuit according to a clock and an enable signal.

Routing g-based pin placement

A method for routing-based pin placement is provided and includes receiving a logical description of a macro of a partitioned circuit with connectivity information and a physical outline, generating an abstracted shape as an abstraction of a generic shape of a pin for providing a connection to the macro in accordance with the connectivity information as a shape conforming to dimensions of the macro, providing a routing tool with freedom to route a net for connection to the pin toward any part of the abstracted shape of the pin to create a routed net and identifying a location where the routed net crosses the physical outline as a chosen location for the pin.

Timing operations in an ic with configurable circuits

Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

Method to compensate optical proximity correction

A method to compensate optical proximity correction adapted for a photolithography process includes providing an integrated circuit (IC) layout. The IC layout includes active regions, a shallow trench isolation (STI) region and ion implant regions overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region disposed in the STI region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Then, the corrected IC layout is transferred to a photomask.

Compiler for Closed-Loop 1xN VLSI Design

Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

User Guided Short Correction And Schematic Fix Visualization

Techniques for assisting a designer in correcting discrepancies identified in layout design data. A user interface may be provided listing identified shorts and relevant information related to those shorts. Still further, the user interface may allow a designer to selectively choose a subset of the identified shorts, and to designate or otherwise provide correction data for use to correct the shorts before performing a short isolation process on the selected shorts. Alternately or additionally a user interface may provide a designer with graphical images showing the correction that should be made by a designer to address an identified discrepancy in layout design data.

Method For Improving Circuit Design Robustness

Improving circuit design robustness is based on identifying process sensitive and design critical devices. Design critical devices are identified using circuit design information. Various model-based simulations may be performed on the layout areas associated with the identified design critical devices to extract process sensitive and design critical devices. To make the circuit design more robust, various techniques may be employed to treat the extracted process sensitive and design critical devices.

System and method for protecting a computing device using vsd material, and method for designing same

Embodiments described herein provide for programmatic design or simulation of substrates carrying electrical elements to integrate voltage switchable dielectric (“VSD”) material as a protective feature. In particular, VSD material may be incorporated into the design of a substrate device for purpose of providing protection against transient electrical conditions, such as electrostatic discharge (ESD).

Simulator

A simulator used in a distributed process simulation includes: a storage unit configured to store map information, agent information, and area allocation information; a simulation execution unit; a condition determination unit configured to determine the condition of the reference agent to be referenced by the simulation execution unit based on a movement state of the agent; an allocation discrimination unit configured to discriminate another computer allocated an area in which the reference agent corresponding to the condition can be located; and an agent information acquisition unit configured to acquire the information about the agent satisfying the condition of the reference agent from the other discriminated computer.

Memory module and video camera

According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.

Verification support apparatus, verifying apparatus, computer product, verification support method, and verifying method

A verification support apparatus includes a detecting unit that detects an inconsistency between a simulation result at an observation point in a circuit-under-test and an expected value; a setting unit that sets a portion of output values to logic values different from those of the simulation result when the detecting unit detects the inconsistency, wherein the output values are random values output from elements that receive a signal in a second clock domain that receives the signal from a first clock domain asynchronously; a comparing unit that compares the expected value and a simulation result at the observation point after the setting by the setting unit; and an identifying unit that identifies whether the portion of the output values are a cause of the inconsistency, based on a result of comparison by the comparing unit.

Method and Apparatus for Characterizing and Reducing Proximity Effect on Cell Electrical Characteristics

Circuit elements are characterized for effects of proximity context on electrical characteristic. Based on the characterization, proximity context cell models, and corresponding modeled electrical characteristic values are obtained. Logic cells are characterized and modeled according to the proximity context cell models. Optionally the electrical characteristic can be time delay, leakage, dynamic power, or coupling noise among other parameters.

Method and Apparatus for Placement and Routing of Partial Reconfiguration Modules

A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Method and system for double-sided printing of a series of sheets

A method and a system for double-sided printing of a series of sheets is provided. First printing data for being printed onto a first surface of the series of sheets are provided. The first printing data comprise a plurality of first subsets, each first subset for being printed onto one sheet. Second printing data for being printed onto a second surface of the series of sheets are provided. The second printing data comprise a plurality of second subsets. Each second subset is associated with a respective first subset. A first print is printed in dependence upon the first printing data onto the first surface of the series of sheets. A second print is printed in dependence upon the second printing data onto the second surface of the series of sheets. The first print is scanned and first print data in dependence thereupon are provided. The second print is scanned and second print data in dependence thereupon are provided. For each sheet the first print data and the second print data are processed to determine if the second print data are associated with the respective first print data and data indicative thereof are stored in a database.

Design support apparatus for semiconductor device, design support program, and layout information generating method

A design support apparatus according to an aspect of the present invention includes: a terminal position setting unit that obtains, from a floor plan result generated from circuit design information, positional information on first and second connection terminals of a connection target circuit area to be connected to an inductor to be generated, and sets third and fourth connection terminals at respective positions where the first and third connection terminals and the second and fourth connection terminals can be respectively connected by a shortest wiring, the third and fourth connection terminals connecting the inductor to another circuit; and a pattern generation unit that generates a wiring pattern of the inductor based on the positions of the third and fourth connection terminals, and generates layout information on the inductor based on the wiring pattern.

Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium

A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

Noise reduction using feedback to a wire spreader router

A computer implemented method, system, and/or computer program product reduce noise in a circuit. A level of noise imposed by an aggressor line on a victim line is determined. The aggressor line and the victim line are an aggressor/victim line pair from multiple aggressor/victim line pairs in a circuit. Determination of the noise level is conducted during a predetermined window of time during which a signal is being transmitted along the aggressor line. Each of the multiple aggressor/victim line pairs are ranked according to a level of noise being imposed by each aggressor line on each victim line. The spacing between a highest ranked aggressor/victim line pair is then expanded.

Metal density aware signal routing

Methods and apparatus for routing signal paths in an integrated circuit. One or more signal routing paths for transferring signals of the integrated circuit may be determined. A dummy fill pattern for the integrated circuit may be determined based on the one or more metal density specifications and at least one design rule for reducing cross coupling capacitance between the dummy fill pattern and the routing paths. The signal routing paths and/or the dummy fill pattern may be incrementally optimized to meet one or more timing requirements of the integrated circuit.

Method for technology porting of cad designs, and computer program product therefor

An embodiment of a design of one or more devices such as e.g. integrated circuits is ported from a source design technology to a target design technology by:—producing a standardized set of porting rules which translate device information related to the device or devices from the source design technology to the target design technology, and—creating a migrated design for the device or devices resulting from porting the CAD design from the source design technology to the target design technology by applying the standardized set of rules to the device information related.

Method of Fabricating Isolated Capacitors and Structure Thereof

A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Method for computing io redistribution routing

A method of determining signal routing in an integrated circuit includes providing first coordinates of an input/output cell and second coordinates of an input/output pad to a parametric routing module. The parametric routing module receives at least one wire path parameter. The parametric routing module uses the at least one connection path parameter to determine a physical dimension of a wire path between the first coordinates and the second coordinates.

Method and apparatus for performing implication and decision making using multiple value systems during constraint solving

Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. An embodiment can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. Next, the embodiment can generate a circuit model based on the set of constraints, wherein assignable values for at least one node in the circuit model are represented in multiple value systems. The embodiment can then assign random values to the set of random variables based on the circuit model.

System and methods for converting planar design to finfet design

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.

Decoupling capacitor insertion using hypergraph connectivity analysis

Decoupling capacitors (dcaps) are placed in an IC design by assigning different dcap utilization rates to logic cones, applying the rates to corresponding dcap regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a dcap at the overlapping region having the highest dcap utilization rate. The best location for the dcap is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The dcap is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to dcap location, and inserting the next dcap at a region corresponding to the node which then has the greatest number of connected edges.

Relative Positioning of Circuit Elements in Circuit Design

Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.

Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells

An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell. Within each row, for each standard cell in the row, the voltage connection area of that standard cell is then connected to one of a plurality of voltage supplies having regards to a voltage requirement of the corresponding functional component defined by the standard cell, and independent of the voltage supply to which each adjacent cell in the row is connected. This provides a particularly flexible mechanism for placing standard cells during the layout operation, since standard cells that are required to run off the same voltage supply no longer need to be placed together.

Clock mesh synthesis with gated local trees and activity driven register clustering

A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

Integrated circuit design tool apparatus and method of designing an integrated circuit

An integrated circuit design tool apparatus including a processing resource arranged to support a circuit simulator, a circuit simulator interrogator, and a well distance calculator is provided. The circuit simulator interrogator communicates first and second well distance values separately to the circuit simulator and receives first and second performance parameter value back from the circuit simulator interrogator in response. The well distance calculator determines a performance parameter limit value, and projects, substantially linearly, a well distance change value in respect of the performance parameter limit value using the first and second performance parameter values, the performance parameter limit value and a trial well distance change value. Also, a well distance change characterising equation using the well distance change value projected is used in order to obtain the minimum well distance value associated with the performance parameter limit value.

Normally closed microelectromechanical switches (mems), methods of manufacture and design structures

Normally closed (shut) micro-electro-mechanical switches (MEMS), methods of manufacture and design structures are provided. A method of forming a micro-electrical-mechanical structure (MEMS), includes forming a plurality of electrodes on a substrate, forming a beam structure in electrical contact with a first of the electrodes, and bending the beam structure with a thermal process. The method further includes forming a cantilevered electrode extending over an end of the bent beam structure, and returning the beam structure to its original position, which will contact the cantilevered electrode in a normally closed position.

Semiconductor structure and method for fabricating semiconductor layout

A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.

Optimizing lithographic mask for manufacturability in efficient manner

Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.

DFM Improvement Utility with Unified Interface

A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

Method, Program Product and Apparatus for Performing Double Exposure Lithography

A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process is disclosed. The method includes defining an initial H-mask and an initial V-mask corresponding to the target pattern; identifying horizontal critical features in the H-mask and vertical critical features in the V-mask; assigning a first phase shift and a first percentage transmission to the horizontal critical features, which are to be formed in the H-mask; and assigning a second phase shift and a second percentage transmission to the vertical critical features, which are to be formed in the V-mask. The method further includes the step of assigning chrome to all non-critical features in the H-mask and the V-mask.

Method for implementing circuit design for integrated circuit and computer readable medium

In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.

Implementing enhanced clock tree distributions to decouple across n-level hierarchical entities

A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.

Solutions for modeling spatially correlated variations in an integrated circuit

A computer-implemented method for modeling Spatially Correlated Variation (SCV) in a design of an Integrated Circuit (IC) is disclosed. In one embodiment, the method includes: generating a set of coefficient values for a position dependent SCV function, the set of coefficient values being selected from a set of random variables; obtaining a set of coordinates defining a position of each of a plurality of devices in a defined field; evaluating the position dependent SCV function to determine a device attribute variation for each of the plurality of devices based upon the coordinates of each of the plurality of devices; modifying at least one model parameter based upon the evaluation of the position dependent SCV function; and running a circuit simulation using the at least one modified model parameter.

Methodology for performing post layer generation check

There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified.

Method for ensuring dpt compliance with autorouted metal layers

A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to generate an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and using color covers. A reduced DPT compatible design rule set.

Electrostatic damage protection circuitry verification

Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.

Incremental concurrent processing for efficient computation of high-volume layout data

Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system.

System and method for automated real-time design checking

Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.

Multi-patterning lithography aware cell placement in integrated circuit design

A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.

Barrier Device

This disclosure relates to an apparatus and method 10 for protecting an electronic circuit from an airflow. The apparatus 10 comprises a base 12, wherein said base 12 comprises a cover means for covering at least part of the electronic circuit. The apparatus further comprises a guide means for guiding an airflow around the electronic circuit.

Power grid mosaicing with deep-sub-tile cells

A computer aided design system can determine coverage of a metal layer mosaic. The system can apply a tile pattern to a design including at least one layer. Then, the system can identify at least one tile of the tile pattern that violates at least one first design rule. After that, the system can apply a sub-tile pattern to an area identified in the identifying the at least one tile of the tile pattern that violates the design rule. The system further can identify at least one sub-tile of the sub-tile pattern that violates at least one second design rule. Finally, the system can apply a deep-sub-tile pattern to an area identified in the identifying the at least one sub-tile of the sub-tile pattern that violates the second design rule.

Parasitic extraction for semiconductors

Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points.

Printed circuit board and layout method thereof

A printed circuit board includes a signal layer having a pair of differential transmission lines thereon. An eye width and an eye height of an eye diagram obtained at output terminals of the pair of differential transmission lines are variable according to a distance between the pair of differential transmission lines. The eye width and the eye height of the eye diagram are at minimum values when the distance between the pair of differential transmission lines is at a first distance. The eye width and the eye height meet requirements of the pair of differential transmission lines for the eye diagram when the distance between the pair of differential transmission lines is set at a second distance, the second distance is less than the first distance.

Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for asip design

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure

Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam comprising amorphous silicon material and providing an insulator material over and adjacent to the amorphous silicon beam. The method further includes forming a via through the insulator material and exposing a material underlying the amorphous silicon beam. The method further includes providing a sacrificial material in the via and over the amorphous silicon beam. The method further includes providing a lid on the sacrificial material and over the insulator material. The method further includes venting, through the lid, the sacrificial material and the underlying material to form an upper cavity above the amorphous silicon beam and a lower cavity below the amorphous silicon beam, respectively.

Adjusting Sizes of Connectors of Package Components

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Method and apparatus to improve reliability of vias

In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

Computer aided design system and method

A computer aided design system comprises an interface creating module, a first calculating module, a dividing module and a second calculating module. The interface module creates a parameter setting interface to display the proposed design on the screen of the device formed with nets and cline segments and select at least one net in response to the user's operation. The first calculating module calculates the length of the cline segments of the potential net in order based on the coordinates of the cline segments and generates a dividing signal. The dividing module divides the cline segments into a first team and a second team based on the compared result with a predetermined width according to the dividing signal. The second calculating module adds the calculated cline segments length in the first team and in the second team to obtain a first length and a second length.

Method of resistor matching in analog integrated circuit layout

A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.

Automatic Place and Route Method for Electromigration Tolerant Power Distribution

The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (J max ) for mean time to failures (MTTF) to be increased.

Distributed resonant clock grid synthesis

A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid to implement a resonant tank clock grid and the input grid buffer is resized. A check of the resonant tank design criteria is then made. If the design criteria are met the resonant VLSI clock grid with its LC tanks is implemented. If not, another attempt at implementing a suitable LC tanks placement and sizing is made. The process iterates until a VLSI clock grid that meets the design criteria is obtained.

High performance design rule checking technique

Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Interconnection device in a multi-layer shielding mesh

An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines.

Micro-electro-mechanical system (mems) capacitive ohmic switch and design structures

A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method comprises forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method comprises forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method comprises forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method comprises forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.

Method and apparatus for plasma processing

A plasma processing apparatus is disclosed for minimizing the non-uniformity of potential distribution around wafer circumference. The apparatus includes a focus ring formed of a dielectric, and a conductor or a semiconductor having RF applied thereto. A surface voltage of the focus ring is determined to be not less than a minimum voltage for preventing reaction products caused by wafer processing from depositing thereon. The surface height, surface voltage, material, and structure of the focus ring are optimized so that the height of an ion sheath formed on the focus ring surface is either equal or has a height difference within an appropriate tolerance range to the height of the ion sheath formed on the wafer surface.

Automated stimulus steering during simulation of an integrated circuit design

A method is contemplated in which the stimulus to an IC design simulation may be automatically manipulated or steered so that the test environment is altered during subsequent simulations of the IC design based upon the simulation results and/or configuration settings of previous simulations of the IC design. More particularly, a stimulation steering tool may analyze the simulation results and/or the test environment, and manipulate the test environment, which may include the test generator output, and the test bench model, for subsequent simulations.

Scanner based optical proximity correction system and method of use

A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether δ 1 <ε 1 , wherein δ 1 represents model vs. exposure difference and ε 1 represents predetermined criteria. The technique further includes completing the model when δ 1 <ε 1 .

Design system for semiconductor device, method for manufacturing semiconductor device, semiconductor device and method for bonding substrates

The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

Methods of of improving bump allocation for semiconductor devices and semiconductor devices with improved bump allocation

In a method of improving bump allocation for a semiconductor device and a semiconductor device with improved bump allocation, a predetermined signal bump is surrounded with at least three bumps, each being a ground bump or a paired differential signal bump.

Configuring a programmable device using high-level language

A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.

Lens heating aware source mask optimization for advanced lithography

A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method including computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the illumination source and the design layout, the computing of the multi-variable cost function accounting for lens heating effects; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied.

Cell routability prioritization

A layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout. The routability characteristics are prioritized so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout. The prioritization of the routability characteristics can be indicated by a set of weights, with each weight in the set indicating the priority of a corresponding routability characteristic of the standard cell layout. The weights can be used to calculate a weighted sum of the routability characteristics of the standard cell, thereby providing a way to efficiently compare the routability of different standard cell layouts.

Thermal Relief Automation

An approach is provided in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and identifies one or more electrical properties corresponding to a component assigned to the selected power plane thru pin location. As such, the dynamic thermal relief generator computes a conductive material exclusion amount based upon the identified electrical properties, which indicates an amount of area to exclude conductive material on the selected power plane layer. In turn, the dynamic thermal relief generator creates a thermal relief pattern based upon the computed conductive material exclusion amount that identifies conductive material voids on the selected power plane layer to exclude the substantially conductive material.

Semiconductor device design method, system and computer-readable medium

In a semiconductor device design method performed by at least one processor, first and second electrical components are extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second electrical components in the semiconductor substrate. Parasitic parameters of a coupling in the semiconductor substrate between the first and second electrical components are extracted using a first tool. Intrinsic parameters of the first and second electrical components are extracted using a second tool different from the first tool. The extracted parasitic parameters and intrinsic parameters are combined into a model of the semiconductor device. The parasitic parameters of the coupling are extracted based on a model of the coupling included in the second tool.

Algorithm of cu interconnect dummy inserting

The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect.

Power State Transition Verification For Electronic Design

Various implementations of the invention may be applied to generate an auxiliary verification statement. The auxiliary verification statement defines properties that check if the power domains are active at appropriate times is generated. Particularly, the auxiliary verification statement checks to ensure that power domain transitions do not interfere with the operation of the device design. With various implementations of the invention, an auxiliary verification statement may be generated by first determining a set of properties instantiated in a verification statement and then synthesizing the auxiliary verification statement based upon the determined properties, the corresponding device design and the power domains. In some implementations, the auxiliary verification statement instantiates properties that check if the power domains related to the properties in the verification statement are active when the verifications statement is exercised. In various implementations, this is accomplished by substituting select ones of the properties in the verification statement with select properties corresponding to the power domain.

Decoupling capacitor cell, cell-based ic, cell-based ic layout system and method, and portable device

A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring.

Passive devices for finfet integrated circuit technologies

Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Method of designing pattern layouts

A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts.

Computer system and method for performing a routing supply and demand analysis during the floor planning stage of an integrated circuit design process

A floor planning tool is provided that performs the functions that are typically performed by floor planning tools, but in addition, determines the supply of routing resources and the demand on routing resources for all routing channels while applying variable routing rules and static timing estimations to arrive at a preliminary routed floor plan. This drastically reduces the number of iterations that subsequently will need to be performed by the floor planning tool and by routing and static timing analysis tools to arrive at a final routed floor plan.

Novel methodology of optical proximity correction optimization

A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.

Layout of a MOS Array Edge with Density Gradient Smoothing

A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.