Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 3642. Отображено 100.
05-01-2012 дата публикации

Cell deterioration warning apparatus and method

Номер: US20120002468A1
Автор: Frankie F. Roohparvar, Jung-Sheng Hoei, Vishal Sarin
Принадлежит: Micron Technology Inc

Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device.

Подробнее
Номер записи: 1
10-04-2016 дата публикации

Устройство для формирования выборки мгновенного значения напряжения

Номер: RU0000160870U1
Автор: Мария Сергеевна Жаворонкова, Сергей Николаевич Бондарь
Принадлежит: Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Ставропольский государственный аграрный университет"

Устройство для формирования выборки мгновенного значения напряжения, содержащее: операционный усилитель (ОУ); генератор тактовых импульсов, который через логический инвертор подключен к входу управления второго ключа, а через формирователь импульсов соединен с входом установки в единичное состояние триггера, вход установки в нулевое состояние которого соединен с выходом компаратора; выход триггера соединен со входом управления первого ключа; источник входного напряжения, через первый резистор и первый ключ, соединен с первыми выводами второго ключа и запоминающего конденсатора, отличающееся тем, что в устройство введены второй, третий и четвертый резисторы, буферный повторитель на ОУ, причем первый вывод второго резистора соединен с первыми выводами второго ключа и запоминающего конденсатора, вторым выводом первого ключа и неинвертирующим входом ОУ; второй вывод второго резистора соединен с неинвертирующим входом буферного повторителя на ОУ, выходом ОУ и, через четвертый резистор, с инвертирующим входом ОУ и вторым выводом третьего резистора, первый вывод которого заземлен; инвертирующий вход компаратора соединен с источником входного напряжения и первым выводом первого резистора; неинвертирующий вход компаратора соединен с выходом устройства, выходом буферного повторителя на ОУ и его инвертирующим входом; вторые выводы второго ключа и запоминающего конденсатора заземлены. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 160 870 U1 (51) МПК G11C 27/02 (2006.01) H03K 3/02 (2006.01) H03L 5/00 (2006.01) H03K 9/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ТИТУЛЬНЫЙ (21)(22) Заявка: ЛИСТ ОПИСАНИЯ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ 2015152000/08, 03.12.2015 (24) Дата начала отсчета срока действия патента: 03.12.2015 (45) Опубликовано: 10.04.2016 Бюл. № 10 1 6 0 8 7 0 R U (57) Формула полезной модели Устройство для формирования выборки мгновенного значения напряжения, содержащее: операционный усилитель (ОУ); генератор тактовых импульсов, который через логический ...

Подробнее
Номер записи: 2
01-03-2012 дата публикации

High speed switched capacitor reference buffer

Номер: US20120049951A1
Автор: Ganesh Kiran, Jagannathan Venkataraman, Visvesvaraya A. Pentakota
Принадлежит: Texas Instruments Inc

Conventional single-ended and differential reference buffers used for switched capacitor loads (such as sample-and-hold circuits for analog-to-digital converters) often have errors due to “memory” and are current source limited. Here, however, single-ended and differential reference buffers are provided, which include low bandwidth switched capacitor feedback loops to limit noise from the feedback loop and decouple internal bias nodes to avoid memory issues. Additionally, the differential reference buffers shown include flipped voltage followers that can sink/source large currents, which are not current source limited, and that can be underdamped so as to obtain a two pole settling response to reduce power consumption.

Подробнее
Номер записи: 3
19-04-2012 дата публикации

Semiconductor device and sample-and-hold circuit

Номер: US20120092042A1
Автор: Tatsuya Takei
Принадлежит: Olympus Corp

A semiconductor device includes a MOS transistor switch that controls passage and interruption of a signal by switching between an ON state and an OFF state, a first switch connected between a back gate terminal of the MOS transistor switch and a source terminal of the MOS transistor switch, and a second switch connected between the back gate terminal of the MOS transistor switch and a power supply voltage terminal If the MOS transistor switch is in the ON state, the first switch is in the ON state and the back gate terminal of the MOS transistor switch is connected to the source terminal of the MOS transistor switch. If the MOS transistor switch is in the OFF state, the second switch is in the ON state, and the back gate terminal of the MOS transistor switch is connected to the power supply voltage terminal.

Подробнее
Номер записи: 4
26-07-2012 дата публикации

Track and Hold Circuit

Номер: US20120188110A1
Автор: Tracy Johancsik
Принадлежит: SiFlare Inc

A track and hold circuit includes an input, a first output configured to produce a first output signal, and a second output configured to produce a second output signal while the track and hold circuit is in a first mode. While the track and hold circuit is in a second mode, the second output signal is combined with the first output signal and output on the first output.

Подробнее
Номер записи: 5
02-08-2012 дата публикации

Cell operation monitoring

Номер: US20120195126A1
Автор: Frankie F. Roohparvar
Принадлежит: Micron Technology Inc

Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Atypical cell, block, string, column, row, etc. . . . operation is monitored and locations and type of atypical operation stored. Adjustment of operation is performed based upon the atypical cell operation.

Подробнее
Номер записи: 6
27-09-2012 дата публикации

Low Leakage Capacitor for Analog Floating-Gate Integrated Circuits

Номер: US20120241829A1
Автор: Allan T. Mitchell, Imran Mahmood Khan, Kaiping Liu
Принадлежит: Texas Instruments Inc

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Подробнее
Номер записи: 7
28-02-2013 дата публикации

Sample and hold circuit and a/d converter

Номер: US20130050002A1
Автор: Hikaru Watanabe
Принадлежит: Toyota Motor Corp

The present invention is related to a sample and hold circuit and an A/D converter, and prevents an output saturation for an input voltage over a power supply voltage range in the sample and hold circuit. A first switch which is turned on when an input voltage is to be sampled; a sampling capacitor configured to sample the input voltage input via the first switch when the first switch is turned on, and sample a predetermined reference voltage when the first switch is turned off; an adding/subtracting part configured to perform an addition or a subtraction between the input voltage sampled by the sampling capacitor and the predetermined reference voltage sampled by the sampling capacitor; and a hold part configured to hold and output a voltage obtained by the addition or the subtraction by the adding/subtracting part are provided.

Подробнее
Номер записи: 8
04-07-2013 дата публикации

Shift Register and Gate Driving Circuit Using the Same

Номер: US20130169609A1
Автор: An Joon Sung, Lee Won Hee, Son Ki Min
Принадлежит: HYDIS TECHNOLOGIES CO., LTD.

Disclosed are a shift register, and a gate driving circuit including a plurality of shift registers connected in sequence to respectively supply scan signals to a plurality of gate lines of a display device. Each shift register includes: an input unit which outputs a directional input signal having a gate high or low voltage based on an output signal from a previous or subsequent shift register to a first node; an inverter unit which is connected to the first node, generates an inverting signal to a signal at the first node, and outputs the inverting signal to a second node; and an output unit which includes a pull-up unit connected to the first node and activating an output clock signal based on the signal at the first node, and a pull-down unit activating and outputting a pull-down output signal based on a signal at the second node. 1. A gate driving circuit comprising a plurality of shift registers connected in sequence to respectively supply scan signals to a plurality of gate lines of a display device ,the shift register comprising:an input unit which outputs a directional input signal having a gate high voltage VGH or a gate low voltage VGL based on an output signal from a previous or subsequent shift register of the shift register to a first node;an inverter unit which is connected to the first node, generates an inverting signal to a signal at the first node, and outputs the inverting signal to a second node; andan output unit which comprises a pull-up unit connected to the first node and activating an output clock signal based on the signal at the first node to be output as an output signal to a corresponding gate line, and a pull-down unit activating and outputting a pull-down output signal based on a signal at the second node,the inverter unit being controlled by coupling with a control clock signal.2. The gate driving circuit according to claim 1 , wherein the inverter unit comprises:a first switching device that comprises a gate terminal to receive the ...

Подробнее
Номер записи: 9
25-07-2013 дата публикации

Analog Memories Utilizing Ferroelectric Capacitors

Номер: US20130188411A1
Автор: Calvin B. Ward, Joseph T. Evans, Jr.
Принадлежит: Individual

A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes having a value determined by a data value having at least three states to be stored in the ferroelectric memory cell currently connected to the write line. A read circuit measures the charge stored in the ferroelectric memory cell currently connected to the read line.

Подробнее
Номер записи: 10
29-08-2013 дата публикации

Track and hold circuit and method

Номер: US20130222163A1
Автор: Frederic Darthenay
Принадлежит: NXP BV

A track and hold circuit has a main transistor for which the gate voltage is provided by a buffer circuit which is supplied with a different voltage supply than the circuit of the main transistor. This avoids the need for a bootstrap circuit.

Подробнее
Номер записи: 11
29-08-2013 дата публикации

Electro-optical device, shift register circuit, and semiconductor device

Номер: US20130222220A1
Автор: Youichi Tobita
Принадлежит: Mitsubishi Electric Corp

An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.

Подробнее
Номер записи: 12
29-08-2013 дата публикации

Circuit and method for reading a resistive switching device in an array

Номер: US20130223132A1
Автор: Frederick Perner
Принадлежит: Hewlett Packard Development Co LP

A read circuit for sensing a resistive state of a resistive switching device in a crosspoint array has an equipotential preamplifier connected to a selected column line of the resistive switching device in the array to deliver a read current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. The read circuit includes a reference voltage generation component for generating the reference voltage for the equipotential preamplifier. The reference voltage generation component samples the biasing voltage via the selected column line and adds a small increment to a sampled biasing voltage to form the reference voltage.

Подробнее
Номер записи: 13
12-09-2013 дата публикации

HIGH SPEED INTERFACE FOR MULTI-LEVEL MEMORY

Номер: US20130235638A1
Автор: Sutardja Pantas
Принадлежит: MARVELL WORLD TRADE LTD.

A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller. 1. A method of controlling a memory chip , the memory chip including a plurality of storage elements , the method comprising:receiving a plurality of target values from a memory controller, wherein each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements; andfor each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller.2. The method of claim 1 , wherein each target value of the plurality of target values corresponds to one or more of a current claim 1 , a voltage claim 1 , a resistance claim 1 , or a threshold voltage.3. The method of claim 1 , wherein the adjusting the measurable parameter of the storage element comprises:programming the storage element;measuring the measurable parameter of the storage element;determining whether the measurable parameter of the storage element has reached the target value corresponding to the storage element received from the memory controller; andin response to the measurable parameter of the storage element not having reached the target value corresponding to the storage element received from the memory ...

Подробнее
Номер записи: 14
19-09-2013 дата публикации

Analog circuit and display device and electronic device

Номер: US20130240891A1
Автор: Hajime Kimura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

The invention provides an analog circuit that decreases an effect of variation of a transistor. By flowing a bias current in a compensation operation, a voltage between the gate and source of the transistor to be compensated is held in a capacitor. In a normal operation, the voltage stored in the compensation operation is added to a signal voltage. As the capacitor holds the voltage according to the characteristics of the transistor to be compensated, the effect of variation can be decreased by adding the voltage stored in the capacitor to the signal voltage. Further, an analog circuit which decreases the effect of variation can be provided by applying the aforementioned basis to a differential circuit, an operational amplifier and the like.

Подробнее
Номер записи: 15
26-09-2013 дата публикации

SAMPLING CIRCUIT FOR MEASURING REFLECTED VOLTAGE OF TRANSFORMER FOR POWER CONVERTER OPERATED IN DCM AND CCM

Номер: US20130249601A1
Автор: CHEN JUNG-SHENG, Lin Chin-Yen, LIN Li, TANG Yue-Hong, YANG Ta-Yung
Принадлежит: SYSTEM GENERAL CORP.

A sampling circuit of the power converter according to the present invention comprises an amplifier circuit receiving a reflected voltage for generating a first signal. A first switch and a first capacitor are utilized to generate a second signal in response to the reflected voltage. A sample-signal circuit generates a sample signal in response to the disable of a switching signal. The switching signal is generated in accordance with a feedback signal for regulating an output of the power converter. The feedback signal is generated in accordance with the second signal. The sample signal is utilized to control the first switch for sampling the reflected voltage. The sample signal is disabled once the first signal is lower than the second signal. The sampling circuit precisely samples the reflected voltage of the transformer of the power converter for regulating the output of the power converter. 1. An sampling circuit for sampling a reflected voltage of a transformer for the power converter , comprising:an amplifier circuit coupled to receive the reflected voltage for generating a first signal;a first capacitor generating a second signal in response to the reflected voltage;a first switch coupled between the reflected voltage and the first capacitor; anda sample-signal circuit generating a sample signal in response to the disable of a switching signal, in which the switching signal is generated in accordance with a feedback signal for regulating an output of the power converter;wherein the feedback signal is generated in accordance with the second signal; the sample signal is utilized to control the first switch for sampling the reflected voltage; the sample signal is disabled once the first signal is lower than the second signal; the second signal comparing with the first signal has a propagation delay.2. The circuit as claimed in claim 1 , further comprising an oscillator generating a pulse signal coupled to generate the switching signal; in which the sample signal ...

Подробнее
Номер записи: 16
26-09-2013 дата публикации

SHIFT REGISTER APPARATUS AND DISPLAY SYSTEM UTILIZING THE SAME

Номер: US20130249876A1
Автор: HUANG Sheng-Feng, LIN Cheng-Hsiao
Принадлежит: InnoLux Corporation

A shift register apparatus including a first shift register cell is disclosed. The first shift register cell includes a first logic unit, a first control unit and a first output unit. The first logic unit generates a first control signal and a second control signal according to a start signal and a first setting signal. During a first period, the first control unit employs the first and second control signals to make a first clock signal update the first setting signal and the first output unit employs the first and second control signals to make a second clock signal update the first shifted signal. During a second period, the first output unit controls the first shifted signal according to the first and second control signals such that the first shifted signal does not follow the second clock signal. 1. A shift register apparatus , comprising: a first logic unit generating a first control signal and a second control signal according to a start signal from the input terminal and a first setting signal;', 'a first control unit according to the first and second control signals to make a first clock signal from the input terminal update the first setting signal during a first period; and', 'a first output unit outputting a first shifted output signal to the output terminal, wherein during the first period, the first output unit employs the first and second control signals to make a second clock signal from the input terminal update the first shifted output signal, and during the second period, the first output unit controls the first shifted output signal according to the first and second control signals such that the first shifted output signal does not follow the second clock signal., 'a first shift register cell, which are serially connected, each of the shift register cell having an input terminal connected to an output terminal of a preceding shift register cell and an output terminal connected to an input terminal of a succeeding shift register cell, comprising, ...

Подробнее
Номер записи: 17
03-10-2013 дата публикации

OPTIMIZED THRESHOLD SEARCH IN ANALOG MEMORY CELLS USING SEPARATOR PAGES OF THE SAME TYPE AS READ PAGES

Номер: US20130258738A1
Автор: Anholt Micha, Barkon Maya, Dalal Meir, Teitel Moti
Принадлежит:

A method includes reading a group of analog memory cells using first explicit read thresholds, to produce first readout results. The group is re-read using second explicit read thresholds, to produce second readout results. The group is read using one or more sets of auxiliary thresholds so as to produce auxiliary readout results, such that the number of the auxiliary thresholds in each set is the same as the number of the first explicit read thresholds and the same as the number of the second explicit read thresholds. A readout performance of third read thresholds, which include at least one of the first explicit read thresholds and at least one of the second explicit read thresholds, is evaluated using the first, second and auxiliary readout results. 1. A method , comprising:reading a group of analog memory cells using first explicit read thresholds, to produce first readout results;re-reading the group using second explicit read thresholds, to produce second readout results;reading the group using one or more sets of auxiliary thresholds so as to produce auxiliary readout results, such that the number of the auxiliary thresholds in each set is the same as the number of the first explicit read thresholds and the same as the number of the second explicit read thresholds; andevaluating a readout performance of third read thresholds, which comprise at least one of the first explicit read thresholds and at least one of the second explicit read thresholds, using the first, second and auxiliary readout results.2. The method according to claim 1 , wherein the auxiliary thresholds in each set lie in respective intervals of analog values stored in the memory cells claim 1 , and comprising setting the auxiliary thresholds in each set to a respective different combination of lower and upper edges of the respective intervals.3. The method according to claim 2 , wherein setting the auxiliary thresholds comprises assigning a respective different binary code to each of the ...

Подробнее
Номер записи: 18
17-10-2013 дата публикации

Analog sensing of memory cells with a source follower driver in a semiconductor memory device

Номер: US20130272070A1
Автор: Frankie F. Rooparvar, Jung-Sheng Hoei, Vishal Sarin
Принадлежит: Micron Technology Inc

Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations.

Подробнее
Номер записи: 19
31-10-2013 дата публикации

Methods and Apparatus for Non-Volatile Memory Cells

Номер: US20130286729A1
Автор: Yue-Der Chih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data. Methods for operating the non-volatile memory cells are disclosed.

Подробнее
Номер записи: 20
31-10-2013 дата публикации

Method and System For Error Correction in Flash Memory

Номер: US20130290813A1
Автор: Aditya Ramamoorthy, Pantas Sutardja, Zining Wu
Принадлежит: MARVELL WORLD TRADE LTD

A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.

Подробнее
Номер записи: 21
14-11-2013 дата публикации

Passive Offset and Overshoot Cancellation for Sampled-Data Circuits

Номер: US20130300488A1
Автор: Hae-Seung Lee
Принадлежит: Maxim Integrated Products Inc

A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

Подробнее
Номер записи: 22
13-02-2014 дата публикации

GATE DRIVE CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME

Номер: US20140043222A1
Автор: HAN Jong-Heon, Kim Jae-Kyoung, Shin Seob
Принадлежит: Samsung Display Co., Ltd.

A gate drive circuit includes a plurality of stages connected one after another to each other. Each of the stages includes a charging section, a driving section, a discharging section, a holding section and a holding control section. The driving section pulls up a high level of a first clock signal to output a gate signal. The discharging section discharges a voltage potential of a first node to a first off-voltage. The holding section holds a voltage potential of the first node to the first off-voltage. The holding control section receives the first clock signal and a second clock signal. The holding control section holds a voltage potential of the holding section to a second off-voltage through a second node in accordance with the second clock signal to prevent floating of the holding section. 1. A gate drive circuit having a plurality of stages , each stage connected one after another to each other and including a first stage in which a scan start signal is provided to an input terminal , the gate drive circuit configured to sequentially output output signals of respective stages , each of the stages comprising:a charging section that charges the scan start signal or an output signal provided from a previous stage;a driving section coupled to the charging section through a first node, and configured to pull-up a high level of a first clock signal to output a gate signal as the first node is charged to a high level;a discharging section connected to the first node, and configured to discharge a signal of the first node to a first off-voltage in response to an output signal provided from a next stage;a holding section connected to an output node and the first node, and configured to hold the signal of the first node to the first off-voltage; anda holding control section connected to the first node and the holding section, and configured to receive the first clock signal and a second clock signal, and to hold a signal of the holding section to a second off-voltage ...

Подробнее
Номер записи: 23
27-02-2014 дата публикации

SHIFTING REGISTER, GATE DRIVING APPARATUS AND DISPLAY APPARATUS

Номер: US20140055334A1
Автор: QI Xiaojing, Qing Hiagang
Принадлежит:

A shifting register, a gate driving apparatus and a display apparatus comprising the shifting register. The shifting register comprises a latch (), a transmission gate (), a first TFT (T), a second TFT (T), a third TFT (T) and a first inverter (), the first TFT (T), having a gate connected to a reset (Reset) of the shifting register, a drain connected to a drain of the second TFT (T) and an input (M) of the latch () respectively; the second TFT (T), having a gate connected to an input (Input) of the shifting register, the third TFT (T), having a gate connected to the inverting output of the latch (), a drain connected to an input of the first inverter (); an output of the transmission gate being connected to a drain of the third TFT (T), an input of the transmission gate being connected to a clock signal input (CLOCK); the drain of the third TFT (T) being connected to a non-inverting output (Output_Q) of the shifting register, an output of the first inverter being connected to an inverting output (Output_QB) of the shifting register. The shifting register achieves a signal shift with only one latch (). 1. A shifting register , comprising: a latch , a transmission gate , a first TFT , a second TFT , a third TFT and a first inverter , wherein ,the first TFT, having a gate connected to a reset of the shifting register, a source connected to a high-level output of a driving power, and a drain connected to a drain of the second TFT and an input of the latch respectively;the second TFT, having a gate connected to an input of the shifting register, a source connected to a low-level output of the driving power;a non-inverting output of the latch being connected to a non-inverting control of the transmission gate, an inverting output of the latch being connected to an inverting control of the transmission gate;the third TFT, having a gate connected to the inverting output of the latch, a source connected to the low-level output of the driving power, and a drain connected to ...

Подробнее
Номер записи: 24
06-03-2014 дата публикации

SAMPLING CIRCUIT, A/D CONVERTER, D/A CONVERTER, AND CODEC

Номер: US20140062741A1
Автор: Nakanishi Junya, NAKANISHI Yutaka
Принадлежит:

A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals. 1. A sampling circuit comprising:a continuous section that is a circuit transmitting a continuous signal;a sampling and holding section that is connected to the continuous section and that is a circuit transmitting a signal which is sampled but not quantized; anda digital section that is connected to the sampling and holding section and that is a circuit transmitting a signal which is sampled and quantized,wherein the sampling and holding section includes a plurality of capacitive elements for accumulating charge generated by an input signal, and a plurality of first switching elements that correspond to the plurality of capacitive elements, respectively, andwherein a plurality of first clock signals supplied to the plurality of first switching elements are signals having different operation timings, and the first switching elements perform an ON/OFF operation in response to the first clock signals, respectively.2. The sampling circuit according to claim 1 , wherein the first switching elements hold the charge respectively accumulated in the plurality of capacitive elements.3. The sampling circuit according to claim 2 , wherein the continuous section includes a plurality of second switching elements for accumulating charge in the plurality of capacitive elements claim 2 , respectively claim 2 ,wherein a plurality ...

Подробнее
Номер записи: 25
20-03-2014 дата публикации

Shift Register Driving Apparatus And Display

Номер: US20140079175A1
Автор: Wu Zhongyuan
Принадлежит: BOE Technology Group Co., Ltd.

A shift register, a driving apparatus and a display. The shift register comprises: an evaluating unit for receiving a second clock signal and outputting an output signal to a signal output terminal under a control of an input signal; a reset controlling unit, a first terminal of which being connected to the evaluating unit and receiving the input signal, a second terminal of which receiving a first clock signal, a third terminal of which receiving a low level signal, for inputting a control signal to a reset unit under controls of the input signal and the first clock signal; the reset unit for receiving a high level signal and resetting the signal output terminal under a control of the control signal input by the reset controlling unit. When the shift register evaluates the output terminal, the gate of the reset transistor () is charged rapidly, which renders that the reset transistor () is turned off in time. Therefore, the great instantaneous current generated when the reset transistor () and the evaluating transistor () are turned on at the same time is avoided and circuit elements are protected while the power consumption is reduced. The shift register further utilizes an output signal feedback and a dual-gate technique of the input transistors so as to decrease an influence due to a leakage current from the input transistors, which may reduce the power consumption and enhance the stability. 1. A shift register , comprising:an evaluating unit for receiving a second clock signal and outputting an output signal to a signal output terminal under a control of an input signal;a reset controlling unit, a first terminal of which being connected to the evaluating unit and receiving the input signal, a second terminal of which receiving a first clock signal, a third terminal of which receiving a low level signal, for inputting a control signal to a reset unit under controls of the input signal and the first clock signal;the reset unit for receiving a high level signal ...

Подробнее
Номер записи: 26
05-01-2017 дата публикации

DETECTION OF THE AUTHENTICITY OF AN ELECTRONIC CIRCUIT OR OF A PRODUCT CONTAINING SUCH A CIRCUIT

Номер: US20170004333A1
Автор: Farison Denis, Marinet Fabrice, Modave Jean-Louis
Принадлежит:

A method of authenticating a slave device. The method includes initializing, by a host device, a charge retention circuit of the slave device, and receiving, by the host device, an indication of a discharge time of the charge retention circuit. The host device authenticates the slave device based on the received indication of the discharge time of the charge retention device. 1. A method , comprising:initializing, by a host device, a charge retention circuit of a slave device;receiving, by the host device, an indication of a discharge time of the charge retention circuit;determining, by the host device, an authenticity of the slave device based on the received indication of the discharge time of the charge retention device; andcontrolling, by the host device, interactions with the slave device based on the determined authenticity of the slave device.2. The method of wherein the host device compares information representative of time claim 1 , generated by the charge retention circuit claim 1 , with information indicative of an expected duration.3. The method of wherein initializing the charge retention circuit comprises switching off a power supply of the slave device.4. The method of wherein a duration of time in which the power supply of the slave device is switched off is random.5. The method of claim 1 , comprising:transmitting, by the host device to the slave device, a voltage representative of a charge level to be stored in the charge retention circuit;charging, by the slave device, of the charge retention circuit;switching off, by the host device, of a power supply of the slave device for a duration of time;measuring, by the slave device, a residual quantity of charge in the charge retention circuit at an expiration of the duration of time;transmitting, by the slave device to the host device, information representative of the residual quantity; andcomparing, by the host device, said information with an expected value of said information.6. The method of claim ...

Подробнее
Номер записи: 27
07-01-2021 дата публикации

SHIFT REGISTER, GATE DRIVING CIRCUIT, AND DISPLAY APPARATUS

Номер: US20210005124A1
Автор: DU Ruifang, LIU Lingjuan, MA Xiaoye, YANG Ruiying
Принадлежит:

Embodiments of the present disclosure provide a shift register, a gate driving circuit, and a display apparatus. The shift register comprises a power consumption-reducing sub-circuit and an output sub-circuit; wherein: the power consumption-reducing sub-circuit is connected to a clock signal terminal, a control terminal, and the output sub-circuit, the power consumption-reducing sub-circuit is used to output a signal of the clock signal terminal to the output sub-circuit under the control of the control terminal; the output sub-circuit is connected to the clock signal terminal through the power consumption-reducing sub-circuit and is also connected to an output terminal and a pull-up node, the output sub-circuit is used to output an output signal of the power consumption-reducing sub-circuit to the output terminal under the control of the pull-up node. 1. A shift register comprising:a power consumption-reducing sub-circuit and an output sub-circuit; wherein:the power consumption-reducing sub-circuit is connected to a clock signal terminal, a control terminal, and the output sub-circuit, the power consumption-reducing sub-circuit is configured to output a signal of the clock signal terminal to the output sub-circuit under control of the control terminal; andthe output sub-circuit is connected to the clock signal terminal through the power consumption-reducing sub-circuit and is also connected to an output terminal and a pull-up node, the output sub-circuit is configured to output an output signal of the power consumption-reducing sub-circuit to the output terminal under control of the pull-up node.2. The shift register of claim 1 , further comprising an input sub-circuit claim 1 , a pull-down control sub-circuit claim 1 , a pull-down sub-circuit claim 1 , and a reset sub-circuit; wherein:the input sub-circuit is connected to an input terminal and the pull-up node, the input sub-circuit is configured to output a voltage of the input terminal to the pull-up node under ...

Подробнее
Номер записи: 28
02-01-2020 дата публикации

METHOD AND SYSTEM FOR A TRACK AND HOLD AMPLIFIER WITH EXTENDED DYNAMIC RANGE

Номер: US20200005882A1
Автор: Zabroda Oleksiy
Принадлежит:

Systems and methods for a track and hold amplifier with extended dynamic range may include a track amplifier comprising a first PMOS transistor coupled to a first NMOS transistor, a second PMOS transistor coupled to a second NMOS transistor, a capacitor at gates of each NMOS and PMOS transistor, and a plurality of switches. The track and hold amplifier is operable to, during a tracking mode of the track and hold amplifier, couple a differential input signal to each NMOS and PMOS transistor via a first switch coupled to a first capacitor coupled to the gate of the first PMOS transistor and a second capacitor coupled to the gate of the first NMOS transistor, and via a second switch coupled to a third capacitor coupled to the gate of the second PMOS and a fourth capacitor coupled to the gate of the second NMOS transistor. 1. A method for communication , the method comprising: operatively coupling a differential input signal to each NMOS and PMOS transistor via a first switch coupled to a first capacitor coupled to the gate terminal of the first PMOS transistor and a second capacitor coupled to the gate terminal of the first NMOS transistor, and via a second switch coupled to a third capacitor coupled to the gate terminal of the second PMOS and a fourth capacitor coupled to the gate terminal of the second NMOS transistor;', 'operatively coupling the gate terminal of the first PMOS transistor to the gate terminal of the second PMOS transistor via a third switch;', 'operatively coupling the gate terminal of the first NMOS transistor to the gate terminal of the second NMOS transistor via a fourth switch;', 'operatively coupling a first common mode voltage to the gate terminals of the first and second PMOS transistors; and', 'operatively coupling a second common mode voltage to the gate terminals of the first and second NMOS transistors., 'during a tracking mode of the track and hold amplifier, 'in a track and hold amplifier comprising a first PMOS transistor coupled to a ...

Подробнее
Номер записи: 29
03-01-2019 дата публикации

SHIFT REGISTER UNIT CIRCUIT, METHOD OF DRIVING THE SAME, GATE DRIVE CIRCUIT, AND DISPLAY APPARATUS

Номер: US20190006018A1
Автор: Fang Jun, Li Fuqiang, WANG Jiguo, Zhang Jie
Принадлежит:

A shift register unit circuit is disclosed that includes a first node control circuit, a second node control circuit, and a plurality of output circuits. Each of the plurality of output circuits is connected to a respective output terminal and provides a gate drive signal to the respective output terminal. Also disclosed are a method of driving the shift register unit circuit, a gate drive circuit, and a display apparatus. 1. A shift register unit circuit , comprising:a first node control circuit configured to supply an active potential from a first scan level terminal to a first node in response to an input pulse from an input terminal being active, to supply an inactive potential from a second scan level terminal to the first node in response to a reset pulse from a reset terminal being active, and to supply an inactive potential from a first reference level terminal to the first node in response to a second node being at an active potential;a second node control circuit configured to supply an inactive potential from the first reference level terminal to the second node in response to the first node being at an active potential, and to set the second node at an active potential in response to the first node being at an inactive potential and a reset hold signal from a reset hold terminal being active; andN output circuits each connected to a respective internal node, a respective clock terminal and a respective output terminal, the respective internal node being electrically connected to the first node, N being an integer greater than or equal to 2,wherein each of the N output circuits is configured to supply a clock signal from the respective clock terminal to the respective output terminal in response to the respective internal node being at an active potential, to supply an inactive potential from the first reference level terminal to the respective output terminal in response to the second node being at an active potential, and to cause a change in the ...

Подробнее
Номер записи: 30
04-01-2018 дата публикации

SAMPLE-AND-HOLD CIRCUIT WITH RTS NOISE REDUCTION BY PERIODIC MODE SWITCHING

Номер: US20180007294A1
Автор: Eshel Noam, Zeituni Golan
Принадлежит:

A sample-and-hold-circuit includes an amplifier transistor, a resistor connected between a source terminal of the amplifier and a voltage, a first switch connected in parallel with the resistor, and a second switch connected between a gate terminal of the amplifier transistor and the voltage. When the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode; and when the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode. 1. A sample-and-hold circuit , comprising:an amplifier transistor;a resistor connected between a source terminal of the amplifier transistor and a predetermined voltage;a first switch connected in parallel with the resistor; anda second switch connected between a gate terminal of the amplifier transistor and the predetermined voltage.2. The sample-and-hold circuit according to claim 1 , whereinin a case where the first switch is closed and the second switch is open, the amplifier transistor is in an inversion mode, andin a case where the first switch is open and the second switch is closed, the amplifier transistor is in an accumulation mode.3. The sample-and-hold circuit according to claim 2 , wherein the first switch and the second switch are controlled such that when the first switch is open claim 2 , the second switch is closed;and when the first switch is closed, the second switch is opened.4. The sample-and-hold circuit according to claim 2 , wherein the amplifier transistor is switched between the inversion mode and the accumulation mode in an alternating manner.5. The sample-and-hold circuit according to claim 1 , wherein the source terminal of the amplifier transistor is connected to a bottom terminal of the amplifier transistor.6. The sample-and-hold circuit according to claim 1 , further comprising a clamping transistor claim 1 ,wherein a drain terminal of the clamping transistor is connected to the source terminal of the amplifier ...

Подробнее
Номер записи: 31
08-01-2015 дата публикации

APPROXIMATE MULTI-LEVEL CELL MEMORY OPERATIONS

Номер: US20150009736A1
Автор: Burger Douglas C., Ceze Luis Henrique, Sampson Adrian, Strauss Karin
Принадлежит:

The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency. 1. A device , comprising:a controller for providing a digital data value; and an array of multi-level cells, each multi-level cell in the array being configured to utilize a respective probability distribution of likely analog values to represent a stored digital data value, and', 'one or more write circuits configured for storing the digital data value as an approximate analog value by writing to a multi-level cell in the array using analog values within a target range that overlaps the probability distributions associated with digital data values stored in adjacent multi-level cells in the array., 'a multi-level cell memory including'}2. The device of in which each multi-level cell in the array is adapted for storing at least two digital data values.3. The device of in which each multi-level cell in the array is selected from one of a multi-level flash memory or a multi-level phase change memory.4. The device of in which the controller further sets a flag that indicates when the digital data value is to be stored as a precise analog value and when the digital data value is to be stored as an approximate analog value.5. The device of in which the one or more write circuits are further configured to ...

Подробнее
Номер записи: 32
14-01-2016 дата публикации

SAMPLING CIRCUIT

Номер: US20160012912A1
Автор: KOTANI Tadashi
Принадлежит: OLYMPUS CORPORATION

Sampling is continuously performed at high speed with a simple sampling circuit including a polarity switcher to invert or non-invert the polarity of an input signal; an integrating circuit to integrate the signal output from the polarity switcher to output integrated values corresponding to the amount of charge stored in a capacitor; a computing section configured to compute a sampling value every sampling period in such a manner that a difference between one of the integrated values output from the integrating circuit at the start of the sampling period and another one of the integrated values output from the integrating circuit at the end of the sampling period is multiplied by a sign corresponding to the polarity set by the polarity switcher; and a control section configured to control the polarity switcher to alternately invert the polarity of the input signal every sampling period in synchronization with a sampling cycle. 1. A sampling circuit comprising:a polarity switcher configured to invert or non-invert a polarity of an input signal to output the inverted or non-inverted signal;an integrating circuit configured to integrate the signal output from the polarity switcher to output integrated values;a computing section configured to compute a sampling value every predetermined sampling period, the sampling value being obtained in such a manner that a difference value between an integrated value which is one of the integrated values output from the integrating circuit at a start of the sampling period and an integrated value which is another one of the integrated values output from the integrating circuit at an end of the sampling period is multiplied by a sign corresponding to the polarity set by the polarity switcher; anda control section configured to control the polarity switcher to alternately invert the polarity of the input signal every sampling period in synchronization with a sampling cycle.2. The sampling circuit of claim 1 , whereinthe polarity ...

Подробнее
Номер записи: 33
15-01-2015 дата публикации

Switchable readout device

Номер: US20150014534A1
Автор: Ming-Sheng Yang, Tai-Ping Sun, Tse-Hsin CHEN, Yi-Chuan Lu
Принадлежит: National Chi Nan Univ

A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

Подробнее
Номер записи: 34
10-01-2019 дата публикации

SHIFT REGISTER UNIT AND GATE SCANNING CIRCUIT

Номер: US20190013083A1
Автор: Li Fuqiang, WANG Jiguo
Принадлежит:

The present disclosure provides a shift register unit and a gate scanning circuit. In the shift register unit, when a first scanning pulse inputting terminal is at a first level, a voltage at a first node is pulled by a first DC voltage terminal; when a second scanning pulse inputting terminal is at the first level, the voltage at a first node is pulled by a second DC voltage terminal. In addition, each stage of the shift register unit have two scanning pulse outputting terminal. In a next period after the first scanning pulse outputting terminal outputs gate driving signals to the Nth row of pixel units, the second scanning pulse outputting terminal may output gate voltages to the (N+1)th row of pixel units. 1. A shift register unit , comprising:an inputting sub-circuit, electrically connected to a first DC voltage terminal, a second DC voltage terminal, a third DC voltage terminal, a first scanning pulse inputting terminal, a second scanning pulse inputting terminal and a first node, and configured to conduct the first node with the first DC voltage terminal in response to the first scanning pulse inputting terminal being a first level, and to conduct the first node with the second DC voltage terminal in response to the second scanning pulse inputting terminal being the first level;a first energy storage sub-circuit, electrically connected to the first node and configured to maintain the charge of the first node when the first node is floating;a second energy storage sub-circuit, electrically connected to a third node and configured to maintain the charge of the third node when the third node is floating;a first outputting sub-circuit, electrically connected to the first node, a first clock signal terminal and a first scanning pulse outputting terminal, and configured to conduct the first scanning pulse outputting terminal with the first clock signal terminal in response to the first node being the first level;a second outputting sub-circuit, electrically ...

Подробнее
Номер записи: 35
14-01-2016 дата публикации

DELAY CIRCUIT, ELECTRONIC CIRCUIT USING DELAY CIRCUIT AND ULTRASONIC IMAGING DEVICE

Номер: US20160013782A1
Автор: NAKAGAWA Tatsuo
Принадлежит:

A delay circuit and an ultrasonic imaging apparatus with the higher-accuracy delay time, the longer maximum delay time, and the lower power consumption are provided. An input line to which an analog input signal is input, a plurality of analog signal memory devices, an output line, a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices, a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line, and a clock generation part that generates sampling switch control signals for controlling the sampling switches and output switch control signals for controlling the output switches are provided, and phase of the sampling switch control signals may be shifted with respect to phase of the output switch control signals. 1. A delay circuit comprising:an input line to which an analog input signal is input;a plurality of analog signal memory devices;an output line from which an analog output signal is output;a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices;a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line; anda clock generation part that generates sampling switch control signals for respectively controlling the plurality of sampling switches and output switch control signals for respectively controlling the plurality of output switches from a reference clock,the delay circuit delaying signals by controlling the plurality of sampling switches to accumulate the analog input signal in the plurality of analog signal memory devices and controlling the plurality of output switches to output the signals accumulated in the plurality of analog signal memory devices to the output line,wherein phase of the plurality of sampling switch ...

Подробнее
Номер записи: 36
11-01-2018 дата публикации

ELECTRONIC SWITCH EXHIBITING LOW OFF-STATE LEAKAGE CURRENT

Номер: US20180013417A1
Автор: Samuels Howard R.
Принадлежит: ANALOG DEVICES, INC.

According to some aspects, a low-leakage switch is provided. In some embodiments, the low-leakage switch includes a plurality of pass transistors in series that selectively couple two ports of the low-leakage switch and a node biasing circuit coupled to a node between the plurality of pass transistors. In these embodiments, the node biasing circuit may adjust a voltage at the node to change the gate-to-source voltage of the pass transistors and, thereby, reduce the leakage current through the pass transistors when the low-leakage switch is turned off. The node biasing circuit may also include circuitry to reduce the leakage current introduced by the node biasing circuit into the node when the low-leakage switch is turned on. 1. A low-leakage switch , comprising:a first port and a second port;a plurality of pass transistors coupled between the first port and the second port; the plurality of pass transistors including at least two n-type pass transistors; anda first node-biasing circuit coupled to a first node between the at least two n-type pass transistors and configured to adjust a voltage at the first node responsive to the at least two n-type pass transistors being turned off, the first node-biasing circuit including a first p-type transistor coupled to the first node, a second p-type transistor coupled in series with the first p-type transistor, and a first n-type transistor having a terminal coupled between the first and second p-type transistors.2. The switch of claim 1 , wherein the first node-biasing circuit is further configured to turn on the first and second p-type transistors and turn off the first n-type transistor responsive to the at least two n-type pass transistors being turned off.3. The switch of claim 2 , wherein the first node-biasing circuit is further configured to turn off the first and second p-type transistors and turn on the first n-type transistor responsive to the at least two n-type pass transistors being turned on.4. The switch of ...

Подробнее
Номер записи: 37
14-01-2021 дата публикации

Track-and-Hold Circuit

Номер: US20210012848A1
Автор: Fukuyama Hiroyuki, Katsurai Hiroaki, Miura Naoki, Nosaka Hideyuki
Принадлежит:

A track-and-hold circuit with a high sampling rate and reduced power consumption is provided. A track-and-hold circuit performing switching between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, by using a clock signal, such that only the data signal in the hold mode is output, the track-and-hold circuit including: two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal; a clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits; and a multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the clock signal. 1. A track-and-hold circuit performing switching , by using a clock signal , between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output , such that only the data signal in the hold mode is output , the track-and-hold circuit comprising:two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal;a clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits; anda multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the clock signal.2. A track-and-hold circuit performing switching , by using a clock signal , between a track mode in which a data signal ...

Подробнее
Номер записи: 38
09-01-2020 дата публикации

SHIFT REGISTER UNIT, DRIVING METHOD, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

Номер: US20200013474A1
Автор: BAI Yajie, DAN Yi, KIM Sangsoo, Wu Hailong, Xu Zhuo
Принадлежит:

A shift register unit includes a common circuit and an output circuit. The common circuit is configured to control a potential at a pull-up node under the control of an input end, a resetting end and a first clock signal input end. The output circuit is configured to control 2M gate driving signal output ends to output gate driving signals respectively under the control of the pull-up node, a noise reduction control end and an output control end, where M is an integer greater than 1. 1. A shift register unit , comprising a common circuit and an output circuit , whereinthe common circuit is connected to a first clock signal input end, a second clock signal input end, an input end, a resetting end, a first voltage input end, a second voltage input end and a pull-up node, and configured to control a potential at the pull-up node under the control of the input end, the resetting end and the first clock signal input end; andthe output circuit is connected to the pull-up node, the first voltage input end, the second voltage input end, a noise reduction control end, an output control end and 2M gate driving signal output ends, and configured to control the 2M gate driving signal output ends to output gate driving signals respectively under the control of the pull-up node, the noise reduction control end and the output control end, where M is an integer greater than 1.2. The shift register unit according to claim 1 , wherein the common circuit comprises a pull-up control node control sub-circuit and a pull-up node control sub-circuit;the pull-up control node control sub-circuit is connected to the input end, the resetting end, the first clock signal input end, the first voltage input end, the second voltage input end and a pull-up control node, and configured to control a potential at the pull-up control node under the control of the input end, the resetting end and the first clock signal input end; andthe pull-up node control sub-circuit is connected to the pull-up control ...

Подробнее
Номер записи: 39
15-01-2015 дата публикации

SHIFT REGISTER UNIT, DISPLAY PANEL AND DISPLAY DEVICE

Номер: US20150016584A1
Автор: Dun Dongliang, Xia Zhiqiang
Принадлежит:

A shift register unit, a display panel including the shift register unit and a display device including the display panel are provided. The shift register unit includes a driving module, an output module, a first transistor, and a second transistor. By connecting a second electrode of the first transistor in the shift register unit with an output terminal of the shift register unit, even if a channel width of the second transistor is considerably smaller than a theoretical design value, abnormal output of the shift register unit can be avoided. 1. A shift register unit comprising a driving module , an output module , a first transistor and a second transistor ,wherein a first port of the driving module receives a positive selection signal, a second port of the driving module receives a first level signal, a third port of the driving module receives a reverse selection signal, a fourth port of the driving module receives a second level signal, a fifth port of the driving module receives a low voltage signal, a sixth port of the driving module is connected with a gate of the first transistor and a first electrode of the second transistor, a seventh port of the driving module is connected with a third port of the output module, an eighth port of the driving module is connected with a first electrode of the first transistor, a gate of the second transistor and a first port of the output module at a pull-up node, a ninth port of the driving module receives a clock blocking signal, a tenth port of the driving module receives a clock signal, a second electrode of the first transistor is connected with the third port of the output module, a second electrode of the second transistor receives the low voltage signal, a second port of the output module receives the clock blocking signal, and the third port of the output module serves as an output terminal of the shift register unit;the driving module is configured to output the first level signal through the eighth port when ...

Подробнее
Номер записи: 40
09-01-2020 дата публикации

Method and Apparatus for Signal Extraction with Sample and Hold and Release

Номер: US20200014301A1
Автор: Telefus Mark
Принадлежит: INTELESOL, LLC

For AC-DC conversion, signal is extracted, then sampled and held and released. Extraction element receives AC signal to generate extracted signal, then sample and hold and release element receives the extracted signal to generate DC signal. Extraction and/or sample and hold and release signal processing may use microprocessor or controller programmably to generate the extracted signal and/or DC signal. Extraction is configurable such that AC signal is received at extraction time or temporal window, whereby said extraction element generates the extracted signal having an extraction current or voltage value during at least one extraction time, and preferably said sample and hold and release element generates the DC signal having the same extraction current or voltage value. 1. Signal processing apparatus comprising:signal extraction circuit; andsignal sampling and holding and releasing circuit;wherein said signal extraction circuit receives an AC signal to generate an extracted signal, and said signal sampling and holding and releasing circuit receives the generated extracted signal to generate a DC signal;wherein no sampling or extraction by said signal extraction circuit substantially occurs between predetermined extraction or sampling times, such that sampling or extraction by said signal extraction circuit discontinuously occurs only at said predetermined extraction or sampling times, thereby advantageously conserving electrical energy by eliminating continuous AC-DC signal conversion.2. Apparatus of wherein said signal extraction circuit or said signal sampling and holding and releasing circuit comprises a processor or controller that programmably generates the extracted signal or the DC signal.3. Apparatus of wherein said signal extraction circuit is configurable electronically to receive the AC signal at one or more extraction times claim 1 , whereby said signal extraction circuit generates the extracted signal having an extraction current or voltage value ...

Подробнее
Номер записи: 41
18-01-2018 дата публикации

Sample-and-Hold Circuit

Номер: US20180019020A1
Автор: Olarte Gonzalez Javier Mauricio, Saez Richard Titov Lara, VILAS BOAS André Luis
Принадлежит:

A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged. 1. A sample-and-hold circuit comprising:a switch enable terminal for receiving a switch enable signal;an input terminal for intermittently receiving an input voltage;a first transistor having one conducting terminal coupled to the input terminal, having another conducting terminal coupled to a node and having a control terminal coupled to the switch enable terminal;an intermediate capacitor coupled between the node and a ground terminal;a second transistor having one conducting terminal coupled to the node, having another conducting terminal coupled to an output terminal and having a control terminal coupled to the switch enable terminal; anda hold capacitor coupled between the output terminal and the ground terminal,wherein, when the input terminal is receiving the input voltage, a first value of the switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the intermediate capacitor and the hold capacitor to the sampled input voltage,wherein, when the input terminal is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at the output terminal, the sampled input voltage until the hold capacitor discharges, andwherein the charge on the intermediate capacitor delays discharging of ...

Подробнее
Номер записи: 42
18-01-2018 дата публикации

PHYSICAL QUANTITY DETECTION CIRCUIT, PHYSICAL QUANTITY DETECTION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Номер: US20180019717A1
Автор: MURASHIMA Noriyuki
Принадлежит:

A physical quantity detection device includes a switched capacitor filter circuit having a first sample-and-hold circuit adapted to sample and hold a first signal, which is based on an output signal of a physical quantity detection element, an amplifier circuit to which an output signal of the first sample-and-hold circuit is input, and a first switched capacitor circuit to which a first output signal of the amplifier circuit is input, wherein an output signal of the first switched capacitor circuit is input to the amplifier circuit, and an A/D conversion circuit adapted to perform an A/D conversion on an output signal of the switched capacitor filter circuit. 1. A physical quantity detection circuit comprising:a switched capacitor filter circuit having a first sample-and-hold circuit adapted to sample and hold a first signal, which is based on an output signal of a physical quantity detection element, an amplifier circuit to which an output signal of the first sample-and-hold circuit is input, and a first switched capacitor circuit to which a first output signal of the amplifier circuit is input, wherein an output signal of the first switched capacitor circuit is input to the amplifier circuit; andan A/D conversion circuit adapted to perform an A/D conversion on an output signal of the switched capacitor filter circuit.2. The physical quantity detection circuit according to claim 1 , wherein a first chopping circuit to which an output signal of the first sample-and-hold circuit is input,', 'an operational amplifier to which an output signal of the first chopping circuit is input, and', 'a second chopping circuit to which an output signal of the operational amplifier is input., 'the amplifier circuit includes'}3. The physical quantity detection circuit according to claim 2 , whereinchopping frequencies in the first chopping circuit and the second chopping circuit are equal to or lower than a half of a sampling frequency with which the A/D conversion circuit samples ...

Подробнее
Номер записи: 43
21-01-2021 дата публикации

SAMPLE AND HOLD SWITCH DRIVER CIRCUITRY WITH SLOPE CONTROL

Номер: US20210021769A1
Автор: Dai Tiejun, Fu Ling, Gao Zhe, Yang Yu-Shen
Принадлежит:

A switch driver circuit includes a first transistor coupled between a voltage supply and a first output node. A second transistor is coupled between the first output node and a first discharge node. A first slope control circuit is coupled to the first discharge node to discharge the first discharge node at a first slope. A third transistor is coupled between the voltage supply and a second output node. A fourth transistor is coupled between the second output node and a second discharge node. A second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope. The first and second slopes are mismatched. 1. A switch driver circuit , comprising:a first transistor coupled between a voltage supply and a first output node;a second transistor coupled between the first output node and a first discharge node;a first slope control circuit coupled to the first discharge node to discharge the first discharge node at a first slope;a third transistor coupled between the voltage supply and a second output node;a fourth transistor coupled between the second output node and a second discharge node; anda second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope, wherein the first and second slopes are mismatched.2. The switch driver circuit of claim 1 ,wherein the first slope control circuit comprises a first resistor having a first resistance,wherein the second slope control circuit comprises a second resistor having a second resistance,wherein the first and second resistors are mismatched with one another.3. The switch driver circuit of claim 2 ,wherein the first output node is coupled to drive a first sample and hold switch coupled to a first row of a pixel array, andwherein the second output node is coupled to drive a second sample and hold switch coupled to the first row of the pixel array.4. The switch driver circuit of claim 3 , further comprising:a fifth ...

Подробнее
Номер записи: 44
26-01-2017 дата публикации

INVERTER, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

Номер: US20170025057A1
Автор: LI Quanhu
Принадлежит:

The present disclosure relates to display technology, and provides an inverter, a gate driving circuit and a display apparatus, capable of solving the problem that it is difficult to apply Scan Power technology in the display apparatus since a power signal outputted from the inverter has a small current. The inverter comprises: a current amplification module configured to amplify a current of the output terminal of the inverter based on a signal at a first clock signal terminal, a signal at a second clock signal terminal, a signal at a third clock signal terminal, a signal at a fourth clock signal terminal, a signal at a first input signal terminal, and a signal at a second input signal terminal, and to control the output terminal of the inverter to output a high level signal; and a pull-down module configured to control the output terminal of the inverter to output a low level signal. The inverter according to the present disclosure may be applied in a display apparatus employing the Scan Power technology. 1. An inverter , comprising:a current amplification module connected to a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a fourth clock signal terminal, a first input signal terminal, a second input signal terminal, a high level terminal, a low level terminal and an output terminal of the inverter, and configured to amplify a current at the output terminal of the inverter based on a signal at the first clock signal terminal, a signal at the second clock signal terminal, a signal at the third clock signal terminal, a signal at the fourth clock signal terminal, a signal at the first input signal terminal and a signal at the second input signal terminal, and to control the output terminal of the inverter to output a high level signal; anda pull-down module connected to the first input signal terminal, the low level terminal and the output terminal of the inverter, and configured to control the output terminal of the ...

Подробнее
Номер записи: 45
29-01-2015 дата публикации

NON-VOLATILE MEMORY WITH LINEAR HOT-ELECTRON INJECTION TECHNIQUE AND STRAIN GAUGE USING THE SAME

Номер: US20150027237A1
Автор: Chakrabartty Shantanu
Принадлежит: BOARD OF TRUSTEES OF MICHIGAN STATE UNIVERSITY

A linear hot-electron injection technique is provided for a non-volatile memory arrangement. The non-volatile memory is comprised of: a floating gate transistor; a capacitor with a first terminal electrically coupled to the gate node of the floating gate transistor; a current reference circuit electrically coupled to the source node of the floating gate transistor; and a feedback circuit electrically coupled between the source node of the floating gate transistor and a second terminal of the capacitor. The feedback circuit operates to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the floating gate transistor. 122-. (canceled)23. A self-powered static-strain sensor , comprising:a piezoelectric member that generates a voltage in response to as mechanical strain; and a floating gate transistor having a gate node and a source node;', 'a capacitor having a first terminal and a second terminal, the first terminal electrically coupled to the gate node of the floating gate transistor;', 'a current reference circuit electrically coupled to the source node of the floating gate transistor and operable to source a current therein; and', 'a feedback circuit electrically coupled between the source node of the floating gate transistor and the second terminal of the capacitor, and operable to adjust a voltage at the gate node of the floating gate transistor in accordance with a source-to-drain voltage across the floating gate transistor., 'a non-volatile memory circuit powered by the voltage received from the piezoelectric member and includes'}24. The self-powered static-strain sensor of wherein the current reference circuit operates to hold the source current constant claim 23 , thereby ensuring that the source-to-gate voltage of the floating gate transistor remains constant.25. The self-powered static-strain sensor of wherein the current reference circuit is implemented by two transistors in a cascading ...

Подробнее
Номер записи: 46
28-01-2016 дата публикации

Sample-and-Hold Circuit for an Interleaved Analog-to-Digital Converter

Номер: US20160027528A1
Автор: Craninckx Jan, DEGUCHI Kazuaki, Verbruggen Bob
Принадлежит: IMEC VZW

The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage. 1. A sample-and-hold circuit comprisinga transistor arranged for switching between a sample mode and a hold mode;a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode, the bootstrap circuit comprising a bootstrap capacitance arranged for being precharged to a given charge voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode, wherein the bootstrap circuit comprises a programmable switched capacitor charge pump for generating the given charge voltage to which the bootstrap capacitance is precharged.2. The sample-and-hold circuit as in claim 1 , wherein the switched capacitor charge pump comprises a first capacitor and a second capacitor.3. The sample-and-hold circuit as in claim 2 , wherein the second capacitor is programmable.4. The sample-and-hold circuit as in claim 2 , wherein the first capacitor is arranged to be charged to a supply voltage and the second capacitor is arranged for being discharged claim 2 , the first and ...

Подробнее
Номер записи: 47
25-01-2018 дата публикации

GATE DRIVING CIRCUIT AND DISPLAY DEVICE

Номер: US20180025684A1
Автор: Chan Chien-Ting, CHEN Po-Yi, HSU Yu-Tuan
Принадлежит:

The invention provides a gate driving circuit and a display device. The gate driving circuit is configured to drive a display panel of the display device, and includes shift registers and at least a dummy shift register. The shift registers are respectively configured to generate and output scan signals to scan lines of the display panel, the dummy shift register is configured to generate a dummy scan signal before the scan signals are generated. The dummy scan signal and the scan signals are sequentially generated. 1. A gate driving circuit for driving a display panel , the gate driving circuit comprising:{'sup': st', 'th', 'st', 'th, '1to Nstage first shift registers configured to respectively generate and output 1to Nstage first scan signals to a plurality of first scan lines of the display panel; and'}one or more first dummy shift registers configured to respectively generate and output one or more first dummy scan signals before the first scan signals are generated;wherein the one or more first dummy scan signals and the first scan signals are sequentially outputted, and N is an integer.2. The gate driving circuit of claim 1 , wherein the one or more first dummy shift registers are 1to Mstage first dummy shift registers claim 1 , and M is an integer multiple of 2.3. The gate driving circuit of claim 1 , wherein the one or more first dummy shift registers are 1to Mstage first dummy shift registers claim 1 , and M is an integer greater than or equal to 3.4. The gate driving circuit of claim 1 , wherein the one or more first dummy shift registers are 1to Mstage first dummy shift registers claim 1 , and M is 4.5. The gate driving circuit of claim 1 , wherein a 1stage first dummy shift register of the one or more first dummy shift registers is configured to generate a 1stage first dummy scan signal of the one or more first dummy scan signals according to a starting signal.6. The gate driving circuit of claim 1 , wherein the 1stage first shift register is configured ...

Подробнее
Номер записи: 48
24-01-2019 дата публикации

GOA SIGNAL DETERMINING CIRCUIT, DETERMINING METHOD, GATE DRIVER CIRCUIT AND DISPLAY DEVICE

Номер: US20190027079A1
Автор: Dong Xue, HAN Mingfu, HAN Seung-Woo, Huang Yinglong, IM Yun-Sik, JUN Jung-Mok, KIM Ji Ha, Lv Jing, SHANG Guangliang, WANG Zhichong, YAO Xing, YUAN Lijun, ZHENG Haoliang
Принадлежит: BOE Technology Group Co., Ltd.

A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal. 1. A GOA signal determining circuit ,connecting an input end of a GOA unit, at least two clock signal ends of the GOA unit and a control end of a reset unit of a PU node in the GOA unit; wherein the GOA signal determining circuit is configured to detect a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and wherein upon determining both of the signal of the input end of the GOA unit and the signal of the at least two clock signal ends of the GOA unit involving an anomaly, the GOA signal determining circuit outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit,wherein, the at least two clock signal ends comprises at least one pair of clock signal ends having input signals complemented with each other, the PU node of the GOA unit is connected to a gate of the output transistor of the GOA unit, and a drain of the output transistor is connected to an output end of the GOA unit, and is configured to output a driving signal to a gate line connected to the output end of the GOA unit.2. The GOA signal determining circuit according to further comprising a NOR gate ...

Подробнее
Номер записи: 49
29-01-2015 дата публикации

SHIFT REGISTER, DRIVER CIRCUIT AND DISPLAY DEVICE

Номер: US20150030116A1
Автор: Horiuchi Satoshi, Iwamoto Akihisa, Iwase Yasuaki, Mizunaga Takayuki, Tagawa Akira, Tanaka Shinya
Принадлежит:

A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive. 1. A shift register , comprising an initial stage , a first intermediate stage , a second intermediate stage , and a final stage , wherein:each of the first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor;the second intermediate stage includes a control circuit which is (i) connected to the setting circuit and (ii) supplied with a control ...

Подробнее
Номер записи: 50
24-01-2019 дата публикации

CORRELATED DOUBLE SAMPLING INTEGRATING CIRCUIT

Номер: US20190027229A1
Автор: ZHAN Chang, ZHANG Mengwen
Принадлежит:

A correlated double sampling integrating circuit is provided. The circuit includes: a sampling and holding module, an energy storage unit and a feedback module. The sampling and holding module is configured to perform sampling and holding for different input signals. The energy storage unit is configured to store charges corresponding to the input signals upon the sampling and holding to generate node signals, and the feedback module is configured to form a negative feedback loop with the energy storage unit to control node signals at an integrating stage to keep consistent with node signals at a resetting stage and prevent output jump of the correlated double sampling integrating circuit. The correlated double sampling integrating circuit reduces noise, and prevents or weakens output jump of the correlated double sampling integrating circuit caused by the increase of the count of integrations. 1. A correlated double sampling integrating circuit , comprising a sampling and holding module , an energy storage unit and a feedback module;wherein the sampling and holding module is configured to sample and hold different input signals;the energy storage unit is configured to store charges corresponding to the input signals that is sampled and held to generate node signals; andthe feedback module is configured to form a negative feedback loop with the energy storage unit to control a node signal at an integrating stage to keep consistent with a node signal at a resetting stage.2. The circuit according to claim 1 , wherein the feedback module comprises a differential amplifier and a switch unit claim 1 , configured to respectively form different negative feedback loops with the energy storage unit to respectively control the node signals generated by the energy storage unit at the integrating stage and the resetting stage claim 1 , such that the node signal at the integrating stage keep consistent with the node signal at the resetting stage.3. The circuit according to claim ...

Подробнее
Номер записи: 51
23-01-2020 дата публикации

SHIFT REGISTER UNIT AND METHOD FOR DRIVING THE SAME, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

Номер: US20200027515A1
Автор: DU Ruifang, Gu Xiaofang, Liu Guodong, MA Xiaoye, Zhang Donghui
Принадлежит:

A shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus are disclosed. The shift register unit includes: an input circuit configured to transmit an input signal to a pull-up node; an output circuit configured to transmit a clock signal to an output signal terminal under control of a voltage at the pull-up node; a first reset circuit configured to reset the pull-up node to a first level under control of a first reset signal; a first pull-down control circuit configured to control levels at the pull-up node and the output signal terminal under control of a first control signal; and a first voltage control circuit electrically connected to a second control signal terminal, and configured to control a voltage signal waveform at the first pull-down node under control of a second control signal. 1. A shift register unit , comprising:an input circuit electrically connected to an input signal terminal and a pull-up node of the shift register unit, and configured to transmit an input signal from the input signal terminal to the pull-up node;an output circuit electrically connected to an output signal terminal, a clock signal terminal and the pull-up node, and configured to transmit a clock signal from the clock signal terminal to the output signal terminal under control of a voltage at the pull-up node;a first reset circuit electrically connected to a first reset signal terminal, the pull-up node and a first level terminal, and configured to reset the pull-up node to a first level at the first level terminal under control of a first reset signal from the first reset signal terminal;a first pull-down control circuit electrically connected to a first control signal terminal, the pull-up node, a first pull-down node of the shift register unit, the first level terminal, and the output signal terminal, and configured to control levels at the pull-up node and the output signal terminal using the first level at the first level ...

Подробнее
Номер записи: 52
23-01-2020 дата публикации

SHIFT REGISTER AND METHOD OF DRIVING THE SAME, GATE DRIVING CIRCUIT, DISPLAY DEVICE

Номер: US20200027516A1
Автор: FENG Xuehuan
Принадлежит:

The present application provides a shift register and a method of driving the same, and a gate driving circuit. The shift register includes a detection sub-shift register. The detection sub-shift register includes: a detection input sub-circuit configured to provide a signal of the first input terminal to the pull-up control node under the control of the first clock signal terminal, and provide a signal of the second clock signal terminal to the first pull-up node under the control of the pull-up control node; and a detection output sub-circuit configured to provide a signal of the third clock signal terminal to the first output terminal under the control of the first pull-up node. 1. A shift register , comprising:a display sub-shift register; and a first input terminal, a first output terminal, a first reset terminal, and a second reset terminal;', 'a detection input sub-circuit coupled to a first clock signal terminal, a second clock signal terminal, the first input terminal, a pull-up control node and a first pull-up node of the detection sub-shift register, and configured to provide a signal of the first input terminal to the pull-up control node under control of the first clock signal terminal, and provide a signal of the second clock signal terminal to the first pull-up node under control of the pull-up control node;', 'a detection output sub-circuit coupled to the first pull-up node, a third clock signal terminal and the first output terminal, and configured to provide a signal of the third clock signal terminal to the first output terminal under control of the first pull-up node;', 'a detection output control sub-circuit coupled to the first output terminal, a first pull-down node and a low-level voltage terminal, and configured to provide a signal of the low-level voltage terminal having a constant low level to the first output terminal under control of the first pull-down node;', 'a detection reset sub-circuit coupled to the first reset terminal, the ...

Подробнее
Номер записи: 53
04-02-2016 дата публикации

METHOD OF OPERATING NON-VOLATILE MEMORY DEVICE

Номер: US20160034327A1
Автор: KIM KYUNG-RYUN
Принадлежит:

A method of operating a non-volatile memory device including first buffer memory cells and main memory cells, where the first buffer memory cells store first data, the main memory cells store second data, which is read from the first buffer memory cells, or recovered first data, which is recovered from the second data through a correction process, includes reading data, which is stored in sample buffer memory cells included in the first buffer memory cells, as sample data when an accumulated number of read commands, which are executed on the non-volatile memory device, reaches a reference value. The method includes counting the number of errors included in the sample data based an error correction code, and determining whether the main memory cells store the second data or the recovered first data based on the number of the errors relative to the first threshold value. 1. A method of operating a non-volatile memory device including first buffer memory cells and main memory cells , the first buffer memory cells storing a first data , the main memory cells storing a second data , which is read from the first buffer memory cells , or a recovered first data , which is recovered from the second data through a correction process , the method comprising:reading data, which is stored in sample buffer memory cells included in the first buffer memory cells, as sample data when an accumulated number of read commands, which are executed on the non-volatile memory device, reaches a reference value;counting a number of errors included in the sample data based on an error correction code; anddetermining whether the main memory cells store the second data or the recovered first data based on the number of the errors relative to a first threshold value.2. The method of further comprising determining that second buffer memory cells included in the non-volatile memory device store the recovered first data when the number of the errors is greater than the first threshold value claim 1 ...

Подробнее
Номер записи: 54
05-02-2015 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20150034948A1
Автор: Takahashi Kei
Принадлежит:

Electric charge is stored, in accordance with a bias voltage, in a gate of a transistor performing switching operation between an input terminal and an output terminal, and the gate is brought into an electrically floating state at the time of completing the storage of electric charge in the gate. One electrode of a capacitor is connected to the gate in an electrically floating state, and the potential of the other electrode of the capacitor is increased, so that the voltage of the gate is increased using capacitive coupling. The potential of the gate of the transistor is increased, and the bias voltage is sampled without being decreased. Each of the transistor performing switching operation and a transistor connected to the gate of the transistor is a transistor with an extremely low off-state current. 1. A semiconductor device comprising:a first transistor;a second transistor;a third transistor; anda first capacitor,wherein a gate of the first transistor is electrically connected to a first electrode of the first capacitor,wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor,wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor, andwherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor.2. The semiconductor device according to claim 1 , further comprising a fourth transistor claim 1 ,wherein the one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor via the fourth transistor.3. The semiconductor device according to claim 1 , further comprising a second capacitor electrically connected to the other of the source and the drain of the first transistor.4. The semiconductor device according to claim 1 ,wherein a second electrode of the first capacitor is selectively supplied with a first potential and a ...

Подробнее
Номер записи: 55
01-05-2014 дата публикации

Data storage in analog memory cells using a non-integer number of bits per cell

Номер: US20140119089A1
Автор: Avraham Meir, Eyal Gurgi, Micha Anholt, Naftali Sommer
Принадлежит: Apple Inc

A method for data storage includes, in a first programming phase, storing first data in a group of analog memory cells by programming the memory cells in the group to a set of initial programming levels. In a second programming phase that is subsequent to the first programming phase, second data is stored in the group by: identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels; and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels.

Подробнее
Номер записи: 56
05-02-2015 дата публикации

SHIFT REGISTER UNIT, SHIFT REGISTER AND DISPLAY APPARATUS

Номер: US20150036784A1
Автор: Nie Leisen, QI Xiaojing, QING Haigang
Принадлежит:

A shift register unit, a shift register and a display apparatus, insulate a start charging capacitor from the gate of the driving transistor, and adopt a dual pulling-down structure for the gate of the driving transistor and the output terminal simultaneously thereby the transistor can be turned off normally and a leakage is prevented. The shift register unit comprises: a driving transistor (T); a first capacitor (C) for storing an electrical signal from a previous stage; an output pulling-up module () connected with a drain of the driving transistor (T); a drive output terminal (OUT (N)) connected with a source of the driving transistor (T); a carry signal output terminal connected with a gate of the driving transistor (T) or the drive output terminal (OUT (N)); an output pulling-down module () connected with a source of the driving transistor (T); a first pulling-down module (), which is connected with the gate of the driving transistor (T) through a pulling-up node (PU) and connected with the output pulling-down module () through a pulling-down node (PD); and an insulation pulling-up module () connected between the pulling-up node (PU) and the first capacitor (C). 1. A shift register , comprising:a driving transistor;a first capacitor for storing an electrical signal from a previous stage;an output pulling-up module, which is connected with a drain of the driving transistor and used for pulling-up the drain of the driving transistor to a high level;a drive output terminal connected with a source of the driving transistor;a carry signal output terminal, which is connected with a gate of the driving transistor or the drive output terminal and used for outputting an electrical signal to a next stage;an output pulling-down module, which is connected with a source of the driving transistor and used for pulling-down the source of the driving transistor to a second level a first pulling-down module, which is connected with the gate of the driving transistor through a ...

Подробнее
Номер записи: 57
30-01-2020 дата публикации

Gate Drive Circuit, Display Device and Method for Driving Gate Drive Circuit

Номер: US20200035138A1
Автор: Xie Yongxian, Xiong Xiong, Zou Yifeng
Принадлежит:

A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal. 1. A gate drive circuit , comprising a scan signal generation circuit and output control circuits in N stages ,wherein the scan signal generation circuit comprises first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages;each of the output control circuits in N stages comprises an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit connected to the input terminal and the second output terminal, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal;a first control terminal of an m-th stage output control circuit of the output control circuits in N stages is connected to a (2m−1)-th stage first output terminal of the first output terminals in 2N stages to receive a scan ...

Подробнее
Номер записи: 58
30-01-2020 дата публикации

Shift Register Unit, Gate Driving Circuit, Display Apparatus and Driving Method

Номер: US20200035316A1
Автор: FENG Xuehuan, Li Yongqian
Принадлежит:

Disclosed are a shift register unit, a gate driving circuit, a display apparatus and a driving method. The shift register unit includes: a first input sub-circuit, configured to receive a display input signal from a display input terminal, and input a display output control signal to a first node in a display period of one frame according to the display input signal; a second input sub-circuit, configured to receive a random input signal in the display period of one frame, and input a blanking output control signal to the first node in a blanking period of one frame according to the random input signal; and an output sub-circuit, configured to output a composite output signal via an output terminal under the control of the first node.

Подробнее
Номер записи: 59
30-01-2020 дата публикации

Gate Drive Circuit, Method of Driving Gate Drive Circuit, Display Device, and Method of Manufacturing Array Substrate

Номер: US20200035317A1
Автор: FENG Xuehuan, Li Meng, Li Yongqian
Принадлежит:

A gate drive circuit, a method of driving a gate drive circuit, a display device, and a method of manufacturing an array substrate are provided. The gate drive circuit includes a repair signal line, a plurality of output signal lines, and a plurality of shift register units that are cascaded. The repair signal line is configured to transmit the repair signal to the first output signal line. The plurality of shift register units include a first shift register unit and a plurality of second shift register units, and the plurality of second shift register units are correspondingly connected to the second output signal lines. The first output signal line corresponds to but is in a state of being disconnected to the first shift register unit, and the first output signal line and the plurality of second output signal lines are configured to output a set of shift pulse signals. 1. A gate drive circuit , comprising a repair signal line , a plurality of output signal lines , and a plurality of shift register units that are cascaded ,wherein the repair signal line is configured to receive a repair signal;the plurality of output signal lines comprise a first output signal line and a plurality of second output signal lines, and the repair signal line is connected to the first output signal line, and is configured to transmit the repair signal to the first output signal line;the plurality of shift register units comprise a first shift register unit and a plurality of second shift register units, and the plurality of second shift register units are correspondingly connected to the plurality of second output signal lines; andthe first output signal line corresponds to but is in a state of being disconnected to the first shift register unit, and the first output signal line and the plurality of second output signal lines are further configured to output a set of shift pulse signals.2. The gate drive circuit according to claim 1 , further comprising a repair signal generation ...

Подробнее
Номер записи: 60
12-02-2015 дата публикации

DATA SAMPLER CIRCUIT

Номер: US20150043681A1
Автор: Mandal Sajal Kumar
Принадлежит: STMICROELECTRONICS INTERNATIONAL N.V.

A circuit includes: a first circuit stage configured to sample a differential input signal at a first logic state of a sampling clock and regenerate the sampled differential input signal at a second logic state of the sampling clock to output a first regenerated differential signal; a second circuit stage configured to amplify the first regenerated differential signal at the second logic state of the sampling clock to output an amplified differential signal; and a third circuit stage configured to regenerate the amplified differential signal at the first logic state of the sampling clock to output a second regenerated differential signal. 1. A circuit , comprising:a first circuit stage configured to sample a differential input signal at a first logic state of a sampling clock and regenerate the sampled differential input signal at a second logic state of the sampling clock to output a first regenerated differential signal;a second circuit stage configured to amplify the first regenerated differential signal at the second logic state of the sampling clock to output an amplified differential signal; anda third circuit stage configured to regenerate the amplified differential signal at the first logic state of the sampling clock to output a second regenerated differential signal.2. The circuit of claim 1 , wherein the first circuit stage includes a differential sampling circuit controlled by the sampling clock and including first and second capacitances for holding voltages of the sampled differential input signal.3. The circuit of claim 2 , wherein the first circuit stage further includes a tail switched sense amplifier circuit including a first tail transistor of a differential amplifier circuit claim 2 , the first tail transistor having a gate terminal coupled to receive the sampling clock claim 2 , the differential amplifier circuit deactivated by the first logic state of the sampling clock and activated by second logic state of the sampling clock.4. The circuit of ...

Подробнее
Номер записи: 61
12-02-2015 дата публикации

SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DISPLAY DEVICE

Номер: US20150043704A1
Автор: MA Zhanjie
Принадлежит: BOE Technology Group Co., Ltd.

A shift register unit comprises a pull-up control module (), a pull-up module (), a pull-down control module () and a pull-down module (), the pull-up control module () is connected to a first clock signal terminal (CLK), a first voltage signal terminal (V), a second voltage signal terminal (V) and a pull-up control node (Aj), the pull-up module () is connected to the pull-up control node (A), the first voltage signal terminal (V) and a signal output terminal (OUTPUT) of present stage, the pull-down control module () is connected to a second clock signal terminal (CLK), a signal input terminal (INPUT) and a pull-down control node (B), and the pull-down module () is connected to the pull-down control node (B), the first clock signal terminal (CLK) and the signal output terminal (OUTPUT) of present stage. There also disclose a gate driving circuit and a display device. The shift register unit can ameliorate a potential suspension problem existing in nodes of the shift register unit, so as to improve stability of an output signal. 1. A shift register unit comprising: a pull-up control module , a pull-up module , a pull-down control module and a pull-down module , whereinthe pull-up control module is connected to a first clock signal terminal, a first voltage signal terminal, a second voltage signal terminal and a pull-up control node, and configured to control a potential at the pull-up control node;the pull-up module is connected to the pull-up control node, the first voltage signal terminal and a signal output terminal of present stage and configured to pull up a signal outputted from the signal output terminal of present stage to a high potential when the pull-up module is controlled by a signal at the pull-up control node to be in a turn-on state and a signal at the first voltage signal terminal is at a high level;the pull-down control module is connected to a second clock signal terminal, a signal input terminal and a pull-down control node and configured to ...

Подробнее
Номер записи: 62
08-02-2018 дата публикации

Shift Register

Номер: US20180040283A1
Автор: CAO Shijie, Hu Zhijin, LEE Chang-yeh, LIAO Congwei, Zhang Shengdong
Принадлежит: Shenzhen China Star Optoelectronics Technology Co. Ltd.

A shift register is disclosed. The shift register comprises a multistage shift register units. Each of the stage shift register unit comprises: a driving module, charging to the driving signal via the first clock signal based on the driving control signal; an input module, outputting the driving control signal based on the second clock signal and the first control signal; a low level maintenance module, keeping the potential of the driving signal at the low level potential of the second reference. The shift register can avoid the leakage from the first output end, decrease the raising time of the driving signal and occupy the small area. 1. A shift register , wherein the shift register comprises a plurality of shift register units , and at least one shift register unit comprises: an input end, connecting to a first clock signal;', 'a control end, for receiving a driving control signal;', 'a first output end, for outputting a driving signal, and the driving module charges and discharges to the driving control signal through the first clock signal based on the driving control signal;, 'a driving module, comprisingan input module, connecting to the control end, the input module outputs the driving control signal based on a second clock signal and a first control signal;a low level maintenance mean, connecting to the first output end, for keeping level potential of the driving signal at low level potential of a second reference voltage based on a first reference voltage, a third clock signal, the first clock signal and the first control signal;wherein, the driving module comprises a first thin film transistor and a first capacitance, and a first end of the first thin film transistor connecting to the first clock signal, a second end of the first thin film transistor connecting to the input module, a third end of the first thin film transistor being used for outputting the driving signal, one end of the first capacitance connecting to a second end of the first thin film ...

Подробнее
Номер записи: 63
08-02-2018 дата публикации

SHIFT REGISTERS AND DRIVING METHODS THEREOF, GATE DRIVING APPARATUS AND DISPLAY APPARATUSES

Номер: US20180040382A1
Автор: GU Honggang, SHAO Xianjie, Song Jie, Wang Qianqian
Принадлежит:

Embodiments of the present disclosure disclose a shift register. The shift register comprises an input circuit configured to control a voltage of a first node, an output circuit configured to control an output signal of a signal output terminal, a first reset circuit configured to reset the voltage of the first node, a second reset circuit configured to reset the output signal, a pull-up control circuit configured to control the voltage of the first node according to the voltage of the second node, and a pull-down control circuit configured to control the voltage of the second node according to the voltage of the first node and control the voltage of the second node to be an effective voltage in response to the voltage of the first node being a non-effective voltage. Further, a gate driving apparatus, an array substrate, and a display apparatus are also proposed. 1. A shift register , comprising:an input circuit coupled to a signal input terminal, a first voltage signal terminal, and a first node and configured to supply a first voltage signal from the first voltage signal terminal to the first node according to an input signal from the signal input terminal;an output circuit coupled to a first clock signal terminal, a signal output terminal, and the first node and configured to supply a first clock signal from the first clock signal terminal to the signal output terminal, as an output signal, according to the voltage of the first node;a first reset circuit coupled to a reset signal terminal, a second voltage signal terminal, and the first node and configured to supply a second voltage signal from the second voltage signal terminal to the first node according to a reset signal from the reset signal terminal, to reset the voltage of the first node;a second reset circuit coupled to a second clock signal terminal, a third voltage signal terminal, a second node, and the signal output terminal and configured to supply a third voltage signal from the third voltage signal ...

Подробнее
Номер записи: 64
09-02-2017 дата публикации

SUCCESSIVE COMPARISON A/D CONVERSION CIRCUIT

Номер: US20170041016A1
Автор: Harada Yasunari
Принадлежит: OLYMPUS CORPORATION

A successive comparison A/D conversion circuit includes: an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal or adding the reference signal to the third differential signal, and outputs the generated first differential signal to the pair of differential input terminals; and a control circuit. 1. A successive comparison A/D conversion circuit , comprising:an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result;a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result;an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal, or by adding the reference signal to the third differential signal, and outputs the ...

Подробнее
Номер записи: 65
24-02-2022 дата публикации

DISPLAY PANEL AND DISPLAY DEVICE

Номер: US20220059001A1
Автор: Yuan Yong
Принадлежит:

Provided are a display panel and display device. The display panel includes a driver circuit, where the driver circuit includes an N-stage cascaded shift register which includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to control a signal of a second node. The third control unit is configured to receive the first voltage signal and generate an output signal in response to a signal of a third node, or receive the second voltage signal and generate an output signal in response to the signal of the second node. The fourth control unit is connected to the third node. 1. A display panel , comprising:a driver circuit comprising a shift register that is N-stage cascaded, wherein N is a number greater than or equal to 2;wherein the shift register comprises:a first control unit configured to receive an input signal and control a signal of a first node in response to a first clock signal;a second control unit configured to receive a first voltage signal and a second voltage signal and control a signal of a second node in response to the signal of the first node, the first clock signal, and a second clock signal;a third control unit configured to one of receive the first voltage signal and generate an output signal in response to a signal of a third node, or receive the second voltage signal and generate an output signal in response to the signal of the second node, wherein the third node is connected to the first node, the first voltage signal is a low level signal, and the second voltage signal is a high level signal; anda fourth control unit connected to the third node and configured to control a potential of the third node to be a first low level signal in at least a first time period in a case where the first node is a low level signal, wherein a ...

Подробнее
Номер записи: 66
07-02-2019 дата публикации

Memory cell including multi-level sensing

Номер: US20190043570A1
Автор: Bruce Querbach, Christopher CONNOR
Принадлежит: Intel Corp

An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

Подробнее
Номер записи: 67
07-02-2019 дата публикации

SAMPLE-AND-HOLD CIRCUIT FOR A LIDAR SYSTEM

Номер: US20190043599A1
Автор: LIVEZEY Darrell
Принадлежит:

The present invention relates to a sample-and-hold circuit comprising a plurality of sample-and-hold branches arranged in parallel and each comprising a buffer and a sample-and-hold block comprising one or more sample-and-hold cells characterised in that said sample-and-hold circuit further comprises a clock and timing circuit arranged for setting an adaptable time delay to enable sampling and sampling phase for each sample-and-hold block, wherein the time delay of at least one sample-and-hold block can be set to value bigger than one sampling clock period. 1. A sample-and-hold circuit comprising a plurality of sample-and-hold branches arranged in parallel and each comprising a buffer and a sample-and-hold block comprising one or more sample-and-hold cells , said sample-and-hold circuit further comprising a clock and timing circuit arranged for setting an adaptable time delay to enable sampling and sampling phase for each sample-and-hold block , wherein the time delay of at least one sample-and-hold block can be set to value bigger than one sampling clock period.2. The sample-and-hold circuit as in claim 1 , wherein said clock and timing circuit is also arranged for adapting a sampling frequency applied in said sample-and-hold block of a sample-and-hold branch of said plurality.3. The sample-and-hold circuit as in claim 1 , wherein said clock and timing circuit is arranged for setting a number of iterations to be performed using said time delay and said sampling phase.4. The sample-and-hold circuit as in claim 1 , wherein said clock and timing circuit is arranged for setting a number of input signals applied to said sample-and-hold circuit.5. The sample-and-hold circuit as in claim 1 , comprising a switching block for controlling read and write operations of said sample-and-hold cells.6. The sample-and-hold circuit as in claim 1 , wherein each sample-and-hold cell comprises a write-in switch claim 1 , a read-out switch and a storage element.7. A light detection and ...

Подробнее
Номер записи: 68
18-02-2016 дата публикации

GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

Номер: US20160049208A1
Автор: He Jian, ZHENG Liangliang
Принадлежит:

The present disclosure provides a gate driving circuit and a display apparatus, wherein the gate driving circuit comprises a shift register () including a plurality of shift register units connected with each other sequentially, and the gate driving circuit further comprises: a first strobe module () and/or a second strobe module (); the first strobe module (), connected to a gate scanning trigger signal line (STV) and strobe signal lines (CS CS); the second strobe module (), connected to the strobe signal lines. With incorporation of the first strobe module (), a gate scanning trigger signal on a gate scanning trigger signal line (STV) is supplied to a predetermined shift register unit according to strobe signals provided on the strobe signal lines (CS CS); and the second strobe module (), which is configured to cut off communication between the predetermined shift register unit and its previous stage of shift register unit according to the strobe signals provided on the strobe signal lines (CS CS), so that the shift register is turned off from the predetermined shift register unit, and thus it can be achieved on a liquid crystal display panel that the gate signal(s) in a black-scan area are selectively turned off in a partial display mode, thus power consumption of the whole display panel being reduced. 1. A gate driving circuit comprising a shift register including a plurality of shift register units connected with each other sequentially , the gate driving circuit further comprising:a first strobe module, connected to a gate scanning trigger signal line and strobe signal lines, is configured to provide a gate scanning trigger signal on the gate scanning trigger signal line to a predetermined shift register unit according to strobe signals provided by the strobe signal lines, so that the shift register operates from the predetermined shift register unit; and/ora second strobe module, connected to the strobe signal lines, is configured to cut off communication ...

Подробнее
Номер записи: 69
26-02-2015 дата публикации

SELECTIVE ACTIVATION OF PROGRAMMING SCHEMES IN ANALOG MEMORY CELL ARRAYS

Номер: US20150055388A1
Автор: Perlmutter Uri, Shalvi Ofir, Sokolov Dotan, Sommer Naftali
Принадлежит:

A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme. 1. An apparatus , comprising:a plurality of memory cells; and select one of a first programming scheme and a second programming scheme dependent upon a criterion;', 'wherein peak power consumed while programming using the first programming scheme is greater than peak power consumed while programming using the second programming scheme; and', 'store data in a subset of the plurality of memory cells using the selected programming scheme., 'circuitry configured to2. The apparatus of claim 1 , wherein a programming speed while programming using the first programming scheme is faster than a programming speed while programming using the second programming scheme.3. The apparatus of claim 1 , wherein the criterion depends on a number of memory cells included in the subset of the plurality of memory cells.4. The apparatus of claim 1 , wherein the criterion depends on a number of Programming and Erasure (P/E) cycles previously applied to memory cells included in the subset of the plurality of memory cells.5. The apparatus of claim 1 , wherein the criterion depends on a number of read errors encountered when reading memory cells included in the subset of the plurality of memory cells.6. The apparatus of claim 1 , wherein a number of memory cells programmed in parallel using the first programming scheme is greater than a number of memory cells programmed in parallel using the second ...

Подробнее
Номер записи: 70
14-02-2019 дата публикации

SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

Номер: US20190051365A1
Автор: Chen Yang, Gao Bo, Li Yan, Shi Lingyun, Sun Wei
Принадлежит:

A shift register unit and a driving method thereof, a gate driving circuit and a display apparatus. The shift register unit includes an input circuit, a first pull-down circuit, a second pull-down circuit, and an output circuit. In a first state, the first pull-down circuit is configured to pull down the level of a pull-up node, and the second pull-down circuit is configured to pull down a level of the output terminal. 1. A shift register unit , comprising an input circuit , a first pull-down circuit , a second pull-down circuit , and an output circuit;wherein the input circuit is coupled to a pull-up node, an input signal terminal, a first level signal terminal, a reset signal terminal and a second level signal terminal, and is configured to charge the pull-up node;the output circuit is coupled to the pull-up node, a first clock signal terminal and an output terminal, and is configured to output a signal inputted by the first clock signal terminal to the output terminal under control of a level of the pull-up node;the first pull-down circuit is coupled to the pull-up node, a first level power signal terminal and a third level signal terminal; andthe second pull-down circuit is coupled to the first clock signal terminal, a second clock signal terminal, the first level power signal terminal and the output terminal;wherein in a first state, the first pull-down circuit is configured to pull down the level of the pull-up node, and the second pull-down circuit is configured to pull down a level of the output terminal.2. The shift register unit according to claim 1 , wherein the first pull-down circuit comprises a first transistor;a gate electrode of the first transistor is coupled to the third level signal terminal, a first electrode of the first transistor is coupled to the pull-up node, and a second electrode of the first transistor is coupled to the first level power signal terminal.3. The shift register unit according to claim 1 , wherein the second pull-down circuit ...

Подробнее
Номер записи: 71
14-02-2019 дата публикации

Reduced-Leakage Apparatus for Sampling Electrical Signals and Associated Methods

Номер: US20190051366A1
Автор: Elsayed Mohamed M.
Принадлежит:

An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches. 1. An apparatus , comprising: a first switch coupled to provide an input signal to be sampled;', 'a second switch coupled to the first switch and to a first capacitor;', 'a third switch coupled to the second switch and to a second capacitor; and', 'a fourth switch to selectively couple to ground a node between the first and second switches., 'a sample-and-hold (S/H) circuit, comprising2. The apparatus according to claim 1 , wherein the fourth switch is closed during a hold mode of the S/H circuit.3. The apparatus according to claim 2 , wherein the fourth switch is open during a sample mode of the S/H circuit.4. The apparatus according to claim 1 , wherein the first claim 1 , second claim 1 , third claim 1 , and fourth switches comprise claim 1 , respectively claim 1 , first claim 1 , second claim 1 , third claim 1 , and fourth metal semiconductor field effect transistors (MOSFETs).5. The apparatus according to claim 1 , wherein a gate of the second switch is coupled to a buffer claim 1 , and wherein the buffer is coupled to a supply voltage provided by a native transistor.6. The apparatus according to claim 1 , wherein a bulk of the second switch is coupled to a source of a native transistor claim 1 , and wherein a drain of the second switch is coupled to a gate of the native transistor.7. The apparatus according to claim 1 , further comprising a diode coupled to the second switch and to a source of a native transistor claim 1 , wherein a gate of the native transistor is coupled to the second switch.813-. (canceled)14. A method of using a sample and ...

Подробнее
Номер записи: 72
14-02-2019 дата публикации

Apparatus for Sampling Electrical Signals with Improved Hold Time and Associated Methods

Номер: US20190051367A1
Автор: Elsayed Mohamed M.
Принадлежит:

An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor. 1. An apparatus , comprising: a first switch to provide an input signal that is to be sampled;', 'a second switch coupled to receive the input signal, the second switch further coupled to a capacitor; and', 'a first native transistor coupled to the second switch and to the capacitor., 'a sample-and-hold (S/H) circuit, comprising2. The apparatus according to claim 1 , further comprising a third switch coupled to a ground of the S/H circuit and to a node between the first and second switches.3. The apparatus according to claim 2 , wherein the third switch is closed during a hold mode of the S/H circuit.4. The apparatus according to claim 2 , wherein the third switch is open during a sample mode of the S/H circuit.5. The apparatus according to claim 1 , wherein the first switch comprises a first metal semiconductor field effect transistor (MOSFET) claim 1 , and wherein the second switch comprises a second MOSFET.6. The apparatus according to claim 5 , wherein during a hold mode of the S/H circuit claim 5 , a gate of the first native transistor is coupled to a drain of the second MOSFET claim 5 , and wherein a source of the first native transistor is coupled to a bulk of the second MOSFET.7. The apparatus according to claim 6 , further comprising a second native transistor having a source coupled to a gate of the second MOSFET and a gate coupled to the drain of the second MOSFET.8. The apparatus according to claim 6 , wherein a source of the first MOSFET is coupled to receive the input signal claim 6 , and wherein a drain of the first MOSFET is coupled to a source of the second MOSFET.9. The apparatus ...

Подробнее
Номер записи: 73
14-02-2019 дата публикации

Apparatus for Sampling Electrical Signals with Reduced Leakage Current and Associated Methods

Номер: US20190051368A1
Автор: Elsayed Mohamed M.
Принадлежит:

An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer. 1. An apparatus , comprising: a first switch coupled to receive an input signal, the first switch further coupled to a first capacitor;', 'a buffer coupled to the first switch; and', 'a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer., 'a sample-and-hold (S/H) circuit, comprising2. The apparatus according to claim 1 , further comprising a second switch coupled to the first switch.3. The apparatus according to claim 2 , wherein during a sample mode of the S/H circuit claim 2 , the second switch is open.4. The apparatus according to claim 3 , wherein during a hold mode of the S/H circuit claim 3 , the second switch is closed.5. The apparatus according to claim 2 , further comprising a third switch coupled to provide the input voltage to the first switch.6. The apparatus according to claim 5 , wherein the first switch comprises a first metal semiconductor field effect transistor (MOSFET) claim 5 , the second switch comprises a second MOSFET claim 5 , and the third switch comprises a third MOSFET.7. The apparatus according to claim 1 , wherein the voltage source has a voltage derived from a maximum expected negative internal offset voltage of the buffer.8. The apparatus according to claim 1 , wherein the voltage source applies the offset voltage to the input of the buffer to reduce a leakage current of the S/H circuit.9. An apparatus claim 1 , comprising: a transistor to provide an input signal that is to be sampled to a first capacitor;', 'a duty-cycled buffer to selectively buffer a voltage across the first capacitor ...

Подробнее
Номер записи: 74
22-02-2018 дата публикации

CURRENT SAMPLING AND HOLDING CIRCUIT AND SIGNAL ACQUISITION SYSTEM

Номер: US20180053564A1
Автор: ZHANG Mengwen
Принадлежит:

A current sampling and holding circuit is disclosed. The current sampling and holding circuit includes: a canceling circuit, connected in series between a VDD terminal and a current sensor, being conducted according to a first enable signal, and configured to output a current to cancel a direct-current component in the current sensor; and a mirroring circuit, connected in parallel between the VDD terminal and a ground voltage with the canceling circuit and the current sensor connected in series, and being conducted according to a second enable signal inverse to the first enable signal, and configured to perform current transfer according to a current difference between a mirror current of a shunt current and an output current of the current sensor. According to the present application, the setup speed of the current sampling and holding circuit is improved, and the noise output by the current sampling and holding circuit is reduced. 1. A current sampling and holding circuit , comprising:a canceling circuit, connected in series between a VDD terminal and a current sensor, being conducted according to a first enable signal, and configured to output a current to cancel a direct-current component in the current sensor; anda mirroring circuit, connected in parallel, between the VDD terminal and a ground voltage, with the canceling circuit and the current sensor connected in series, and being conducted according to a second enable signal inverse to the first enable signal, and configured to perform current transfer according to a current difference between a mirror current of a shunt current and an output current of the current sensor.222222. The current sampling and holding circuit according to claim 1 , further comprising: a second switch (S); wherein one terminal of the second switch (S) is connected to the canceling circuit and the other terminal of the second switch (S) is connected to the current sensor claim 1 , wherein the second switch (S) is configured to turn ...

Подробнее
Номер записи: 75
14-02-2019 дата публикации

APPARATUS AND METHOD FOR SIGNAL PROCESSING BY CONVERTING AMPLIFIED DIFFERENCE SIGNAL

Номер: US20190052251A1
Автор: KIM Jongpal
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A signal processing apparatus includes: a difference signal acquirer configured to obtain a difference signal reflecting a change in an input signal at a preset time interval based on a reference signal; a signal amplifier configured to amplify the difference signal; and a signal restorer configured to generate an output signal by converting the amplified difference signal to a digital signal and summing the digital signal. 1. A signal processing apparatus , comprising:a signal amplifier comprising a first input terminal, a second input terminal, a third input terminal and a fourth input terminal;a first inputter configured to transfer a first input signal alternately to the first input terminal and the second input terminal; anda second inputter configured to transfer a second input signal alternately to the third input terminal and the fourth input terminal,wherein the signal amplifier is configured to amplify a difference signal based on the first input signal and the second input signal, and output the amplified difference signal.2. The apparatus of claim 1 , wherein the first inputter comprises:a first switch of which a switching operation is controllable based on a first control signal; anda second switch of which a switching operation is controllable based on a second control signal.3. The apparatus of claim 2 , wherein:in a first phase, the first switch is close-circuited based on the first control signal to transfer a first reference signal to the first input terminal and the second switch is open-circuited based on the second control signal to transfer the first input signal to the second input terminal; andin a second phase, the first switch is open-circuited based on the first control signal to transfer the first input signal to the first input terminal and the second switch is close-circuited based on the second control signal to transfer the first reference signal to the second input terminal.4. The apparatus of claim 2 , wherein a terminal of the ...

Подробнее
Номер записи: 76
13-02-2020 дата публикации

SHIFT REGISTER, METHOD FOR DRIVING THE SAME, GATE DRIVE CIRCUITRY AND DISPLAY APPARATUS

Номер: US20200051655A1
Автор: Chen Xiaoxiao, Dong Ji, Feng Bo, Ji Haoliang, WANG Shijun, XIAO Wenjun, Yang Bingqing
Принадлежит:

A shift register, a method for driving the same, a gate drive circuitry and a display apparatus are provided. The shift register includes: an input circuit, connected to a signal input terminal, a pull-up node and a first control terminal, and configured to provide a signal of the signal input terminal to the pull-up node under the control of the first control terminal; an output circuit, connected to the pull-up node, a first clock signal terminal and a signal output terminal, and configured to provide a signal of the first clock signal terminal to the signal output terminal under the control of the pull-up node; and a pull-up node control circuit, connected to the pull-up node, a second clock signal terminal, a third clock signal terminal and a first voltage terminal, and configured to provide a signal of the first voltage terminal to the pull-up node. 1. A shift register , comprising:an input circuit, an output circuit and a pull-up node control circuit,wherein the input circuit is connected to a signal input terminal, a pull-up node and a first control terminal, and is configured to provide a signal of the signal input terminal to the pull-up node under the control of the first control terminal;the output circuit is connected to the pull-up node, a first clock signal terminal and a signal output terminal, and is configured to output a signal of the first clock signal terminal to the signal output terminal under the control of the pull-up node; andthe pull-up node control circuit is connected to the pull-up node, a second clock signal terminal, a third clock signal terminal and a first voltage terminal, and is configured to provide a signal of the first voltage terminal to the pull-up node under the control of the second clock signal terminal and the third clock signal terminal.2. The shift register according to claim 1 , further comprising:a reset circuit, connected to the pull-up node, a second control terminal, and a reset signal terminal, and configured to ...

Подробнее
Номер записи: 77
13-02-2020 дата публикации

SHIFT REGISTER UNIT, SHIFT REGISTER CIRCUIT AND DISPLAY DEVICE

Номер: US20200051656A1
Автор: FENG Xuehuan, Li Yongqian
Принадлежит:

The present disclosure relates to the field of display technologies and, more particularly, to a shift register unit, a shift register circuit, and a display device. The shift register unit includes a detection input circuit, a display input circuit, an inverter circuit, a pull-down circuit, a reset circuit, and a first output circuit. In a working process of the shift register unit, the display input circuit and the detection input circuit share the inverter circuit, the pull-down circuit, the reset circuit, and the first output circuit. 1. A shift register unit , comprising:a detection input circuit coupled to a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a first input terminal, a first power signal terminal, a pull-up node and a first node, and configured to transmit a signal from the third clock signal terminal to the pull-up node in response to a signal from the first clock signal terminal and a signal from the second clock signal terminal;a display input circuit coupled to a second input terminal, the pull-up node, and a second power signal terminal, and configured to transmit a signal from the second power signal terminal to the pull-up node in response to a signal from the second input terminal;an inverter circuit coupled to a third power signal terminal, the pull-up node, a pull-down node, the first node, and the first power signal terminal, and configured to transmit a signal from the third power signal terminal to the pull-down node in response to the signal from the third power signal terminal, transmit a signal from the first power signal terminal to the pull-down node in response to a signal from the pull-up node, and transmit the signal from the first power signal terminal to the pull-up node in response to a signal from the pull-down node;a pull-down circuit coupled to the pull-down node, the first power signal terminal, a fourth power signal terminal, an output terminal, and a first signal output ...

Подробнее
Номер записи: 78
13-02-2020 дата публикации

LEVEL SHIFTER

Номер: US20200052678A1
Автор: Chen Chien-Yuan, LEE Cheng Hung, LIAO Hung-Jen, Shieh Hau-Tai
Принадлежит:

A level shifter is configured to receive an input signal in a first voltage domain and output an output signal in a second voltage domain. An input terminal is configured to receive an input signal in a first voltage domain. A first sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain, and a second sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain. An enable circuit is configured to equalize a voltage level of first and second output signals at respective first and second output terminals in response to an enable signal. The first and second sensing circuits are configured output complementary output signals in the second voltage domain at the first and second output terminals in response to the enable signal and the input signal. 1. A level shifter configured to receive an input signal in a first voltage domain and output an output signal in a second voltage domain , the level shifter comprising:an input terminal configured to receive an input signal in a first voltage domain;a first output terminal;a second output terminal;a first sensing circuit configured to shift the input signal from the first voltage domain to the second voltage domain;a second sensing circuit configured to shift the input signal from the first voltage domain to the second voltage domain;an enable circuit configured to equalize a voltage level of first and second output signals at the respective first and second output terminals in response to an enable signal, wherein the first and second sensing circuits are configured output complementary output signals in the second voltage domain at the first and second output terminals in response to the enable signal and the input signal.2. The level shifter of claim 1 , wherein the enable circuit is configured to equalize the outputs to a predetermined voltage level.3. The level shifter of claim 2 , wherein the predetermined ...

Подробнее
Номер записи: 79
15-05-2014 дата публикации

SHIFT REGISTER UNIT AND GATE DRIVE DEVICE FOR LIQUID CRYSTAL DISPLAY

Номер: US20140133621A1
Автор: SHANG Guangliang
Принадлежит:

A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit. 1. A shift register unit , comprising:a third thin film transistor for controlling a level at a pull-up node under a control of a first control signal;a first thin film transistor for outputting a first clock signal to a signal output terminal under a control of a level at the pull-up node;a control unit for controlling a level at a pull-down node;a second level output unit for outputting a second level signal to the signal output terminal under a control of the level at the pull-down node;a tenth thin film transistor for inputting a first level signal to the pull-down node under a control oft the level at the pull-down node; andan eleventh thin film transistor for inputting a first level signal to the pull-down node under a control of a level at the signal output terminal.2. The shift register unit of claim 1 , whereina drain of the first thin film transistor is connected to a first clock signal input terminal, a source thereof is connected to the signal output terminal, and a gate thereof is connected to the pull-up node;a drain of the third thin film transistor is connected to a signal input terminal, a source thereof is connected to the pull-up node, and a gate thereof is connected to the signal input terminal or a second clock signal ...

Подробнее
Номер записи: 80
05-03-2015 дата публикации

DATA RECEPTION APPARATUS AND DATA COMMUNICATION SYSTEM

Номер: US20150063514A1
Автор: Akita Hironobu, MATSUDAIRA Nobuaki, YAMAMOTO Hirofumi
Принадлежит:

A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples). 1. A data reception apparatus comprising:a receive-side clock source provided to be separate from a transmit-side clock source of a data transmission apparatus that transmits data, the receive-side clock source generating a receive clock and outputting the receive clock;an oversampling data generation section to generate oversampling data by oversampling each bit of a received bit string that is received from the data transmission apparatus in synchronization with the receive clock inputted from the receive-side clock source;a bit integrated number calculation section to calculate an integrated number of bits by integrating a predetermined number of bits in the received bit string;a sample integrated number calculation section to calculate an integrated number of samples by integrating the number of samples corresponding to each bit of the predetermined number of bits integrated by the bit integrated number calculation section, in the oversampling data generated by the oversampling data generation section; and obtain an approximated line based on a plurality of points each of which indicates correspondence between the integrated number of bits and ...

Подробнее
Номер записи: 81
10-03-2022 дата публикации

DISPLAY PANEL AND DISPLAY DEVICE

Номер: US20220076604A1
Автор: An Ping, LAI Qingjun, YANG Jinjin, ZHU Yihua
Принадлежит: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.

Provided are a display panel and a display device. The display panel includes a driving circuit comprising N stages of cascaded shift registers. Each shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node. The second control unit is configured to receive a first voltage signal and control a signal of a second node. The third control unit is configured to receive a signal of a fourth node and control an output signal, or receive a second voltage signal and control the output signal. The fourth control unit is configured to receive the first voltage signal and a third voltage signal and control the signal of the fourth node. 1. A display panel , comprising: a first control unit, which is configured to receive an input signal and control a signal of a first node in response to a first clock signal;', 'a second control unit, which is configured to receive a first voltage signal and control a signal of a second node in response to at least the input signal and the signal of the first node;', 'a third control unit, which is configured to receive a signal of a fourth node and control an output signal in response to the signal of the second node, or receive a second voltage signal and control an output signal in response to a signal of a third node, wherein the third node is connected to the first node, the first voltage signal is a high level signal, and the second voltage signal is a low level signal; and', 'a fourth control unit, which is configured to receive the first voltage signal and a third voltage signal, and control the signal of the fourth node in response to at least the signal of the second node, wherein the third voltage signal is a low level signal;', 'wherein in a case where the output signal is a low level signal, a potential of the signal of the fourth node is lower than or equal to a potential ...

Подробнее
Номер записи: 82
10-03-2022 дата публикации

Sample and hold switch driver circuitry with slope control

Номер: US20220078360A1
Автор: Ling Fu, Tiejun Dai, Yu-Shen Yang, Zhe GAO
Принадлежит: Omnivision Technologies Inc

A switch driver circuit includes a plurality of pullup transistors. The plurality of pullup transistors includes a first pullup transistor coupled between a voltage supply and a first output node. A plurality of pulldown transistors includes a first pulldown transistor coupled between the first output node and a ground node. A slope control circuit is coupled to the ground node. A plurality of global connection switches includes a first global connection switch coupled between the first output node and the slope control circuit.

Подробнее
Номер записи: 83
03-03-2016 дата публикации

RECEIVER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: US20160065189A1
Автор: KUDO Masahiro
Принадлежит:

A receiver circuit includes: a plurality of first holding circuits respectively latching a plurality of reception data pieces on the basis of a same clock signal; a comparison circuit respectively comparing first reception data pieces and second reception data pieces after a certain time elapses since the latch of the plurality of first holding circuits, the first reception date pieces being respectively latched by the plurality of first holding circuits, the second reception data pieces being respectively input to the plurality of first holding circuits; and a plurality of second holding circuits respectively latching the first reception data pieces when a first output signal of the comparison circuit indicates that the first reception data pieces and the second reception data pieces are identical. 1. A receiver circuit , comprising:a plurality of first holding circuits configured to respectively latch a plurality of reception data pieces on the basis of a same clock signal;a comparison circuit configured to respectively compare first reception data pieces and second reception data pieces after a certain time elapses since the latch of the plurality of first holding circuits, the first reception date pieces being respectively latched by the plurality of first holding circuits, the second reception data pieces being respectively input to the plurality of first holding circuits; anda plurality of second holding circuits configured to respectively latch the first reception data pieces when a first output signal of the comparison circuit indicates that the first reception data pieces and the second reception data pieces are identical.2. The receiver circuit according to claim 1 ,wherein the plurality of first holding circuits are configured to latch in synchronization with a first edge of the clock signal, andthe comparison circuit is configured to compare in synchronization with a second edge of the clock signal, the second edge being a subsequent edge of the first ...

Подробнее
Номер записи: 84
02-03-2017 дата публикации

SHIFT REGISTER AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

Номер: US20170061922A1
Автор: WANG Jiguo
Принадлежит:

There are presented a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register includes a first feedback module and a pull-down module, wherein the first feedback module comprises at least two feedback units, control terminals of respective feedback units are connected to different control points respectively, each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node, the first node is connected to a control terminal of the pull-down module, and the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register. The shift register is used to enhance noise resistance capability of the shift register. 1. A shift register , comprising: a first feedback module; and a pull-down module , wherein the first feedback module comprises at least two feedback units , control terminals of respective feedback units are connected to different control points respectively , each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node , the first node is connected to a control terminal of the pull-down module , and the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register.2. The shift register according to claim 1 , wherein the shift register further comprises a control module claim 1 , the first feedback module comprises two feedback units claim 1 , which are a first feedback unit and a second feedback unit claim 1 , the different control points are a second node and a third node claim 1 , the control module has an output terminal connected to the second node and is configured to control a level of the second node claim 1 , a control terminal of the first feedback unit is ...

Подробнее
Номер записи: 85
04-03-2021 дата публикации

Word line timing management

Номер: US20210065763A1
Автор: Ferdinando Bedeschi, Riccardo Muzzetto, Umberto Di Vincenzo
Принадлежит: Micron Technology Inc

Methods, systems, and devices for word line timing management are described. In some examples, a digit line may be precharged as part of accessing a memory cell. The memory cell may include a storage component and a selection component. A word line may be coupled with the selection component, and the word line may be selected in order to couple the storage component with the digit line, by way of the selection component. The word line may be selected while the digit line is still being precharged, and the storage component may become coupled with the digit line with reduced delay after the end of precharging of the digit line, concurrent with the end of the precharging of the digit line, or while the digit line is still being charged. Related techniques for sensing a logic state stored by the memory cell are also described.

Подробнее
Номер записи: 86
04-03-2021 дата публикации

TRACK AND HOLD CIRCUITS WITH TRANSFORMER COUPLED BOOTSTRAP SWITCH

Номер: US20210065830A1
Автор: Corsi Marco, Haroun Baher, Payne Robert Floyd, RAGHUNATHAN Ashwin, Sankaran Swaminathan, Seyed Aliroteh Seyed Miaad
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor. 1. A track and hold circuit , comprising:a signal input terminal;a clock input terminal;an output terminal;a transistor having a source, a drain, and a gate; the source being coupled to the signal input terminal; and the drain being coupled to the output terminal; anda transformer having a primary winding, and a secondary winding; the primary winding coupled to the clock input terminal; and the secondary winding coupled between the source and the gate.2. The track and hold circuit of claim 1 , further comprising a voltage source having a first terminal claim 1 , and a second terminal claim 1 , the second terminal of the voltage source being coupled to the signal input terminal;wherein the secondary winding comprises a first end, and a second end, the first end of the secondary winding being coupled to the first terminal of the voltage source, and the second end of the secondary winding being coupled to the gate.3. The track and hold circuit of claim 2 , wherein the primary winding comprises a first end claim 2 , a second end claim 2 , and a tap between the first end and the second end claim 2 , the tap being coupled to a supply voltage.4. The track and hold circuit of claim 1 , wherein:the primary winding comprises a first end coupled to a reference terminal, and a second end coupled to the clock input terminal; andthe secondary winding comprises a first end coupled to the signal input terminal, and a second end coupled to the ...

Подробнее
Номер записи: 87
28-02-2019 дата публикации

MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT

Номер: US20190065366A1
Автор: Brandt Kevin R., Feeley Peter, Hale Christopher S., Hamilton Marc S., Hubbard Daniel J., Li Yun, Malshe Ashutosh, Muchherla Kishore Kumar, Ratnam Sampath K.
Принадлежит:

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes. 1. A memory system , comprising:a memory array including a plurality of memory cells; and select a garbage collection (GC) source block storing valid data,', 'calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and', 'wherein the storage mode is for controlling a number of bits stored in memory cells of the available memory block for subsequent or upcoming data writes.', 'designate a storage mode for an available memory block based on the valid data measure,'}], 'a controller coupled to the memory array, the controller configured to2. The memory system of wherein the controller is further configured to designate single-level cell (SLC) mode for the storage mode based on comparing the valid data measure to a decision threshold.3. The memory system of wherein the controller is configured to designate the SLC mode based on the decision threshold representing a threshold amount of the valid data stored in the GC source block claim 2 , wherein the threshold amount is configurable and is greater than zero and less than 25% of a total capacity of the GC source block.4. The memory system of wherein the threshold amount is 10% of a total capacity of the GC source block.5. The memory system of wherein the controller is further configured to designate the storage mode for the available memory block corresponding to a host cursor for the ...

Подробнее
Номер записи: 88
28-02-2019 дата публикации

GATE DRIVING CIRCUIT AND ELECTROLUMINESCENT DISPLAY USING THE SAME

Номер: US20190066604A1
Автор: HAN Honggyu, KONG Chungsik, LEE Sewan, SHIN Mihee
Принадлежит: LG DISPLAY CO., LTD.

An organic light emitting display comprises pixels connected to gate lines, and a gate driving circuit to supply a gate signal to at least one gate line, and having stages connected to each other in a cascading way. A n(n is a positive integer) stage of the gate driving circuit includes a Q1 node charging unit to charge a Q1 node to a turn-on voltage using first and second clock signals in reverse-phase, and a pull-up transistor to apply the turn-on voltage to an output terminal in response to a Q1 node voltage. The Q1 node charging unit includes a first charging unit to charge the Q1 node voltage to the turn-on voltage using the second clock signal; and a second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has the turn-on voltage. 1. An electroluminescent display comprising:pixels connected to gate lines; anda gate driving circuit to supply a gate signal to at least one of the gate lines, and composed of a plurality of stages connected to each other in a cascading way,{'sup': 'th', 'wherein a n(n is a positive integer) stage of the gate driving circuit comprisesa Q1 node charging unit to charge a Q1 node to a turn-on voltage using a first and a second clock signals in reverse-phase, anda pull-up transistor to apply a turn-on voltage to an output terminal in response to a Q1 node voltage,wherein the Q1 node charging unit comprises:a first charging unit to charge the Q1 node voltage to a turn-on voltage using the second clock signal, anda second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has a turn-on voltage.3. The electroluminescent display of claim 1 , wherein the Q1 node charging unit further comprises a Q2 node controller to apply an electric potential voltage to the Q2 node in a section where the Q1 node has a turn-off voltage.4. The electroluminescent display of claim 3 , wherein the Q2 node controller comprises ...

Подробнее
Номер записи: 89
27-02-2020 дата публикации

GATE DRIVE OUTPUT STAGE CIRCUIT, GATE DRIVING UNIT, AND DRIVE METHOD

Номер: US20200066210A1
Автор: Li Yongqian, Yuan Can, Yuan Zhidong
Принадлежит:

The present disclosure discloses a gate drive output stage circuit, a gate driving unit, and a drive method. The gate drive output stage circuit includes: a first control sub-circuit configured to transmit a start signal of a compensation driving terminal to a first node; a second control sub-circuit configured to transmit a first clock signal of a first clock terminal to a control node when the first node is at an effective level; a first output sub-circuit configured to transmit a second clock signal of a second clock terminal to a first output terminal when the control node is at an effective level; and a second output sub-circuit configured to transmit a first power supply voltage signal of a first power supply voltage terminal to a second output terminal when the control node is at the effective level. 1. A gate drive output stage circuit , comprising:a first control sub-circuit configured to transmit a start signal of a compensation driving terminal to a first node;a second control sub-circuit configured to transmit a first clock signal of a first clock terminal to a control node when the first node is at an effective level;a first output sub-circuit configured to transmit a second clock signal of a second clock terminal to a first output terminal when the control node is at an effective level; anda second output sub-circuit configured to transmit a first power supply voltage signal of a first power supply voltage terminal to a second output terminal when the control node is at the effective level.2. The gate drive output stage circuit according to claim 1 , wherein the first control sub-circuit comprises: a first control transistor claim 1 , a first electrode of the first control transistor being coupled to the compensation driving terminal claim 1 , and a second electrode of the first control transistor being coupled to the first node claim 1 , and the first control transistor being configured to be turned on before the start signal is valid.3. The gate ...

Подробнее
Номер записи: 90
07-03-2019 дата публикации

SRAM with Error Correction in Retention Mode

Номер: US20190074056A1
Автор: CHEVALLIER CHRISTOPHE J., Sheafor Stephen James
Принадлежит:

A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information. 1. An apparatus comprising:a SRAM array with an adjustable power supply and peripheral circuitry;a register connected to peripheral circuitry to store a retention voltage value for the adjustable power supply, wherein the peripheral circuitry has an ECC circuit to detect at least one error in a SRAM word; andwherein the retention voltage is set to a level ensuring loss of at least some SRAM bits in SRAM words retained in the SRAM array.2. The apparatus of claim 1 , further comprising:a tester programmed to perform (a)-(f) until a proportion of lost bits meets a threshold condition, wherein (a)-(f) comprise:(a) writing first data to the SRAM array;(b) reduce voltage to the SRAM array to a current retention voltage;(c) read second data back from the SRAM array;(d) determine the proportion of lost bits by evaluating the second data relative to the first data;(e) if the proportion of lost bits does not meet the threshold condition, reduce the current retention voltage; and(f) if the proportion of lost bits meets the threshold condition, store a last value for the current retention voltage at which the threshold condition was not met in the register.3. The apparatus of claim 2 , wherein the threshold condition is more than n out of m bits lost claim 2 , where n and m are predetermined integers.4. The apparatus of claim 3 , wherein n is 1 and m is 39.5. The apparatus of claim 2 , wherein the tester is further configured to disable the ECC circuit when performing (a)-(f).6. The apparatus of claim 5 , further comprising a sense ...

Подробнее
Номер записи: 91
15-03-2018 дата публикации

Multiplexer Distortion Cancellation

Номер: US20180075925A1
Автор: Bodnar Rares Andrei, Delizia Pasquale, HURRELL Christopher Peter
Принадлежит:

Distortion in a combined sample and hold circuit and multiplexer can be reduced by dividing the sample and hold circuit and the multiplexer up into main and compensation signal channels, and considering the total error signal that arises during an acquire phase across both the switches of the multiplexer and the input switches of the sample and hold stage as a single error signal that has to be compensated. This compensation is then achieved by causing the same error voltages to be induced in both the main and compensation channels of the whole MUX and sample and hold circuit, such that errors can be made to cancel, thus improving the performance of the stage. 1. A sampling circuit for sampling signals from multiple inputs , comprising: respective main and compensation input switches thereto;', 'a respective main channel sampling capacitor; and', 'a respective compensation channel sampling capacitor, and', 'wherein the main channel sampling capacitor is distinct from the compensation channel sampling capacitor;, 'a sample and hold stage comprising main and compensation channels, the main and compensation channels includinga multiplexer comprising a plurality of input nodes and a plurality of main switches, the main switches controlling signals in the main channel of the sample and hold stage; andone or more compensation switches, the one or more compensation switches controlling signals in the compensation channel of the sample and hold stage;wherein corresponding respective properties of the main and compensation switches in the combined MUX and sample and hold circuit are configured such that the same total error charges are generated in the main and compensation channel sampling capacitors.2. A sampling circuit according to claim 1 , configured such that the error charges in use substantially cancel one another.3. A sampling circuit according to claim 2 , and further comprising a differencing circuit configured to receive a first error signal indicative of the ...

Подробнее
Номер записи: 92
19-03-2015 дата публикации

Outputting a particular data quantization from memory

Номер: US20150081957A1
Автор: Theodore T. Pekny
Принадлежит: Micron Technology Inc

The present disclosure includes methods, devices, and systems for outputting data particular quantization of data from memory devices and systems. Outputting data particular quantization of data can include enabling a particular one of a plurality of different quantizations of data. The particular one of the plurality of quantizations of data can then be output.

Подробнее
Номер записи: 93
16-03-2017 дата публикации

SHIFT REGISTER GROUP

Номер: US20170076821A1
Автор: Chen Chia-Heng, Lin Wei-Li, Tung Che-Wei
Принадлежит:

A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided. 1. A shift register group , the shift register group comprising a plurality of series-coupled shift registers each being configured to provide an output signal , each one of the plurality of shift registers comprising:a first output terminal, configured to provide the output signal;a first output terminal control circuit, electrically coupled to the first output terminal and configured to receive a clock signal and determine whether to transmit the clock signal to the first output terminal or not according to a voltage at a driving node;a first driving node control circuit, electrically coupled to the driving node and configured to receive a first control signal and determine whether to transmit the first control signal to the driving node or not according to a second control signal; anda second driving node control circuit, electrically coupled to the driving node and configured to receive a third control signal and determine whether to transmit the third control signal to the driving node or not according to a fourth control signal,wherein the third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number, ...

Подробнее
Номер записи: 94
16-03-2017 дата публикации

TRACK AND HOLD WITH ACTIVE CHARGE CANCELLATION

Номер: US20170076823A1
Автор: AGGRAWAL Himanshu, EL-CHAMMAS Manar Ibrahim
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state. 1. A track and hold circuit , comprising:a primary sampling capacitor; a track state that connects an input signal to the primary sampling capacitor; and', 'a hold state that isolates the input signal from the primary sampling capacitor; and, 'a primary switching transistor configured to providea cancellation transistor coupled to the primary sampling capacitor, wherein the cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.2. The track and hold circuit of claim 1 , wherein the primary switching transistor is a field effect transistor and the cancellation transistor is a field effect transistor; wherein the circuit further comprises:a first switch coupled to a body terminal of the primary switching transistor, and configured to connect the body terminal of the primary switching transistor to a source terminal of the primary switching transistor while the primary switching transistor is in the track state, and connect the body terminal of the primary switching transistor to a common voltage while the primary switching transistor is in the hold state;a second switch coupled to a body terminal of ...

Подробнее
Номер записи: 95
05-03-2020 дата публикации

SHIFT REGISTER, GATE DRIVING CIRCUIT, DISPLAY DEVICE, AND DRIVING METHOD THEREOF

Номер: US20200075112A1
Автор: Dun Dongliang, FEI Rili, Jian Shoufu, Qin Dandan, Wang Tinghai, XIA Houxun, Xia Zhiqiang, Xie Ying
Принадлежит:

A shift register includes a forward/backward scan-control module, configured to transmit a signal of a forward-scan-signal terminal or a signal of a backward-scan-signal terminal to a first node; an interlock module, configured to transmit a signal of a first voltage terminal to a second node, and transmit a signal of a second voltage terminal to the first node; a pull-down module, configured to transmit the signal of the first voltage terminal to a gate-signal output terminal; an output module, configured to transmit a signal of a second clock-signal terminal to the gate-signal output terminal; and a reset module, configured to transmit the signal of the second voltage terminal to the first node, and transmit the signal of the first voltage terminal to the gate-signal output terminal. The disclosed shift register can prevent leakage of the first node, and thus improve the quality and the performance of the shift register. 1. A shift register , comprising:a forward/backward (FW/BW) scan-control module, configured to, in response to a signal of a first control terminal, transmit a signal of a forward-scan-signal terminal to a first node, and in response to a signal of a second control terminal, transmit a signal of a backward-scan-signal terminal to the first node;an interlock module, configured to, in response to a signal of the first node, transmit a signal of a first voltage terminal to a second node, and in response to a signal of the second node, transmit a signal of a second voltage terminal to the first node;a pull-down module, configured to, in response to a signal of a first clock-signal terminal, transmit the signal of the first voltage terminal to a gate-signal output terminal;an output module, configured to, in response to the signal of the first node, transmit a signal of a second clock-signal terminal to the gate-signal output terminal; anda reset module, configured to, in response to a signal of a third control terminal, transmit the signal of the ...

Подробнее
Номер записи: 96
05-03-2020 дата публикации

SHIFT REGISTER UNIT, DRIVE METHOD, GATE DRIVE CIRCUIT AND DISPLAY DEVICE

Номер: US20200075113A1
Автор: Li Yongqian, Yuan Can, Yuan Zhidong
Принадлежит:

A shift register unit, a drive method, a gate drive circuit and a display device are provided, in the field of display technologies. A first input signal terminal connected to an input control circuit of the shift register unit is connected to a first output terminal of a shift register unit at a previous stage, and a second input signal terminal connected to the input control circuit is connected to a second output terminal of the shift register unit at the previous stage. A signal output by the first output terminal of the shift register unit at the previous stage is a first clock signal and a signal output by the second output terminal is a second clock signal. Therefore, the first control node of the shift register unit may be controlled by flexibly adjusting a timing sequence of the first clock signal and the second clock signal. 1. A shift register unit , comprising: an input control circuit and an output circuit; whereinthe input control circuit is connected to a first input signal terminal, a second input signal terminal and a first control node respectively, and the input control circuit is configured to adjust a potential of the first control node in response to a first input signal output by the first input signal terminal or a second input signal output by the second input signal terminal; andthe output circuit is connected to the first control node, a first clock signal terminal, a second clock signal terminal, a first output terminal and a second output terminal respectively, and the output circuit is configured to output a first clock signal from the first clock signal terminal to the first output terminal and output a second clock signal from the second clock signal terminal to the second output terminal in response to the potential of the first control node;wherein the first input signal terminal is connected to a first output terminal of a shift register unit at a previous stage, and the second input signal terminal is connected to a second output ...

Подробнее
Номер записи: 97
18-03-2021 дата публикации

Shift Register Unit, Gate Driving Circuit, Display Device, and Driving Method

Номер: US20210082328A1
Автор: FENG Xuehuan, Li Yongqian
Принадлежит:

A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes a first input circuit, an output control circuit, and an output circuit. The first input circuit is configured to output a first input signal to a first node in response to a first control signal; the output control circuit is configured to output an output control signal to a second node under control of a level of the first node; and the output circuit includes an output terminal, and the output circuit is configured to output an output signal to the output terminal under control of a level of the second node. 1. A shift register unit , comprising a first input circuit , an output control circuit , and an output circuit ,wherein the first input circuit is connected to a first node, and is configured to output a first input signal to the first node in response to a first control signal;the output control circuit is connected to the first node and a second node, and is configured to output an output control signal to the second node under control of a level of the first node; andthe output circuit comprises an output terminal, and the output circuit is connected to the second node, and is configured to output an output signal to the output terminal under control of a level of the second node.2. (canceled)3. The shift register unit according to claim 1 , wherein the output terminal comprises a shift output terminal and at least one scan signal output terminal.4. The shift register unit according to claim 3 , further comprising a third node control circuit claim 3 ,wherein the third node control circuit is connected to the first node and a third node, and is configured to control a level of the third node under control of the level of the first node.5. The shift register unit according to claim 4 , further comprising a first noise reduction circuit claim 4 ,wherein the first noise reduction circuit is connected to the first node, the ...

Подробнее
Номер записи: 98
14-03-2019 дата публикации

SHIFT REGISTER CIRCUIT, DRIVING METHOD THEREOF, GATE DRIVE CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE

Номер: US20190080779A1
Автор: CHEN MO, GAO Jilei, LIU Jinliang, Sun Songmei, Zhang Yang, ZHAO Jian
Принадлежит:

A shift register circuit includes a set circuit, a first reset circuit, a first control circuit, and an output circuit. The output circuit is configured to change an active potential at the first node further away from an inactive potential in response to a first clock signal transferred to a signal output terminal being active, and the first control circuit is further configured to, responsive to the first clock signal transferred to the signal output terminal being active, restrict a change in the active potential at the first node based on a second reference voltage from a second reference voltage, the second reference voltage having a magnitude between an active input pulse and the inactive potential. 1. A shift register circuit comprising:a set circuit configured to, responsive to an input pulse from a signal input terminal being active, transfer the input pulse to a first node to set the first node at an active potential;a first reset circuit configured to transfer a first reference voltage from a first reference voltage terminal to the first node to set the first node at an inactive potential in response to a reset pulse from a reset signal terminal being active, and to transfer the first reference voltage from the first reference voltage terminal to a signal output terminal in response to the reset pulse from the reset signal terminal being active;an output circuit configured to transfer a first clock signal from a first clock signal terminal to the signal output terminal in response to the first node being at the active potential, and to change the active potential at the first node further away from the inactive potential in response to the first clock signal transferred to the signal output terminal being active; anda first control circuit configured to maintain the first node at the active potential in response to the input pulse from the signal input terminal being active, and to restrict a change in the active potential at the first node based on a ...

Подробнее
Номер записи: 99
14-03-2019 дата публикации

SHIFT REGISTER CIRCUITRY AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUITRY AND DISPLAY DEVICE

Номер: US20190080780A1
Автор: Fan Jun, Li Fuqiang, WANG Jiguo
Принадлежит:

Embodiments of the present disclosure provide a shift register circuitry and a driving method thereof, a gate driving circuitry, and a display device. The shift register circuitry includes an input circuit and a plurality of output circuits coupled to the input circuit. The input circuit is coupled to an input signal terminal, and is configured to, under the control of the voltage at the input signal terminal, cause the plurality of output circuits to operate. Each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal. 1. A shift register circuitry , comprising an input circuit and a plurality of output circuits coupled to the input circuit;wherein the input circuit is coupled to an input signal terminal, and is configured to, under the control of a voltage at the input signal terminal, cause the plurality of output circuits to operate; andwherein each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal.2. The shift register circuitry according to claim 1 , further comprising a pull-up point isolation circuit;wherein the pull-up point isolation circuit is coupled to the input circuit and the plurality of output circuits, and is configured such that a conductivity from the input circuit to the plurality of output circuits is unidirectional.3. The shift register circuitry according to claim 1 , at least further comprising a pull-down control circuit claim 1 , a first pull-down circuit claim 1 , and a second pull-down circuit;wherein the plurality of output circuits comprise at least a first output circuit and a ...

Подробнее
Номер записи: 100