Method for making elelctron emitter

The present disclosure provides a method for making electron emitter includes the following steps. First, a linear support is provided. Second, at least one carbon nanotube film or at least one carbon nanotube wire is provided. Third, the at least one carbon nanotube film or wire is wrapped around the linear support. Fourth, the linear support is removed to obtain a carbon nanotube hollow cylinder. Fifth, the carbon nanotube hollow cylinder is fused.

System And Manufacturing A Cathodoluminescent Lighting Device

A device for lighting a room is described. The device has an envelope with a transparent face, the face having an interior surface coated with a cathodoluminescent screen and a thin, reflective, conductive, anode layer. There is a broad-beam electron gun mounted directly to feedthroughs in a base of the envelope with a heated, button-on-hairpin, cathode for emitting electrons in a broad beam towards the anode, and a power supply mounted on the feedthroughs at the base of the envelope that drives the cathode to a multi-kilovolt negative voltage. A two-prong snubber serves as an anode contact to permit the power supply to drive the anode to a voltage near ground. A method of manufacture of the anode uses a single step deposition and lacquering process followed by a metallization using a conical-spiral tungsten filament coated with aluminum by a thermal spray coating process.

Method for making cathode slurry

A method for making cathode slurry is provided and includes the following steps. First, a number of electron emitters, an inorganic binder, and an organic carrier are provided. Second, the electron emitters, the inorganic binder, and the organic carrier are mixed to obtain a mixture. Third, the mixture is mechanically pressed and sheared.

Self assembly of field emission tips by capillary bridge formations

A first side has a first surface on which is located a material, at least a portion of which is to be formed into at least one tip. A second side has a second surface which is heated. At least one of the first and second surfaces being moved so material located on the first surface comes into physical contact with the second surface. Then at least one of the first side and the second side are moved, wherein the physical contact between the material and the second surface is maintained, causing the material to stretch between the second surface and the first surface, generating at least one capillary bridge. Movement is continued until the physical contact between the material and the second surface is broken resulting in the formation of at least one sharp conductive tip.

SUBSTRATE WITH CARBON NANOTUBES, AND METHOD TO TRANSFER CARBON NANOTUBES

A substrate for field emitters uses carbon nanotubes (CNTs) on a conductive substrate, the CNTs being erected essentially perpendicular to the substrate and aligned. In a method to transfer a CNT forest from a first substrate to a second substrate, the second substrate is coated with adhesive and the peaks (tips) of the CNTs on the first substrate are embedded in the uncurred adhesive on the second substrate. After the adhesive cures, the CNTs are removed from the first substrate with the peaks anchored in the cured adhesive on the second substrate. 1. A method for transferring carbon nanotubes from a first substrate to a second substrate , comprising the steps of:growing carbon nanotubes on the first substrate with said carbon nanotubes aligned with each other and grown substantially perpendicularly to said first substrate, said carbon nanotubes on said first substrate each having a peak;coating a second substrate with an uncured adhesive layer; andtransferring the carbon nanotubes from said first substrate to said second substrate by submerging the peaks of the carbon nanotubes in the uncured adhesive layer on the second substrate and anchoring the carbon nanotubes at said peaks in said adhesive layer by curing the adhesive layer and, after curing of said adhesive layer, removing said carbon nanotubes from said first substrate with said carbon nanotubes remaining anchored in the cured adhesive layer on said second substrate.2. A method as claimed in comprising covering only said peaks of said carbon nanotubes with said uncured adhesive layer on said second substrate.3. A method as claimed in comprising submerging said peaks of said carbon nanotubes in said uncured adhesive layer with 30% to 70% of a length of each nanotube remaining outside of said uncured adhesive layer.4. A method as claimed in comprising employing an adhesive having a viscosity when uncured in a range between 500 and 100 mPas. The present application is a divisional of Ser. No. 13/075,401, ...

FIELD EMITTING FLAT LIGHT SOURCE AND METHOD FOR MAKING THE SAME

A field emission flat light source and a manufacturing method thereof are provided. The field emission flat light source includes an anode (), a cathode (), a light guide plate () and a separation body (). The anode () and the light guide plate () are separated by the separation body (). The cathode () is provided in the contained space () formed by the anode (), the light guide plate () and the separation body (). The anode () includes an anode substrate (), a metal reflective layer () provided on the anode substrate () and a light emitting layer () provided on the metal reflective layer (). The cathode () includes a cathode substrate () and an electron emitter () provided on the surface of the cathode substrate (). The thermal conductivity of the field emission flat light source is improved. The field emission flat light source is applied to the field of the liquid crystal display or the illumination light. 1. A field emission flat light source , comprising: an anode , a cathode , a light-transmittable panel , and a isolater , the anode and the light-transmittable panel are in a flat plate shape , the anode is parallel to the cathode; wherein the anode and the light-transmittable panel is separated by the isolater; the anode , the light-transmittable panel , and the isolater cooperatively forms a vacuum confined space , the cathode is suspended in the vacuum confined space; the anode comprises an anode substrate , a metal reflective layer positioned on the anode substrate , and an emitting layer positioned on the metal reflective layer; the cathode comprises a plurality of cathode substrates which are separately disposed and electron emitter formed on surfaces thereof.2. The field emission flat light source according to claim 1 , wherein the cathode substrates are parallel metal wires or the cathode substrates form a network composed of metal wires.3. The field emission flat light source according to claim 1 , wherein the electron emitter has a structure type of ...

METHOD FOR MAKING FIELD EMISSION CATHODE DEVICE

A method for making a field emission cathode device is provided. A filler, a substrate, and a metal plate are provided. The metal plate has a first surface and a second surface opposite to the first surface, and defines at least one through hole extending through from the first surface to the second surface. At least one electron emitter is inserted into the at least one through hole. The first surface of the metal plate is attached to the substrate. At least a part of the at least one electron emitter is located between the first surface and the substrate. The at least one through hole is filled with the filler to firmly fix the at least one electron emitter. 1. A method for making a field emission cathode device , the method comprising:{'b': '10', 'step (S), providing a filler, a substrate, and a metal plate, wherein the metal plate has a first surface and a second surface opposite to the first surface, and defines at least one through hole extending through from the first surface to the second surface;'}{'b': '20', 'step (S), inserting at least one electron emitter into the at least one through hole;'}{'b': '30', 'step (S), attaching the first surface of the metal plate to the substrate, wherein at least a part of the at least one electron emitter is located between the first surface and the substrate; and'}{'b': '40', 'step (S), filling the at least one through hole with the filler to firmly fix the at least one electron emitter.'}220. The method of claim 1 , wherein the step (S) comprises:{'b': '21', 'step (S), providing a field emission wire supply device supplying a continuous field emission wire, the field emission wire supply device having a hollow needle and a tip, wherein the field emission wire extends through the hollow needle and out from the tip;'}{'b': '22', 'step (S), positioning the field emission wire into the at least one through hole, and severing the field emission wire to obtain at least one electron emitter.'}{'b': 23', '21', '22, 'step (S), ...

METHOD FOR MAKING EMITTER HAVING CARBON NANOTUBES

A method for making an emitter is disclosed. A number of carbon nanotubes in parallel with each other are provided. The carbon nanotubes have a number of first ends and a number of second ends opposite to the number of first ends. The first ends are attached on a first electrode and the second ends are attached on a second electrode. The first electrode and the second electrode are spaced from each other. A voltage is supplied between the first electrode and the second electrode to break the carbon nanotubes. 1. A method for making an emitter , comprising:selecting one or more carbon nanotubes from a carbon nanotube array;fixing each end of the one or more carbon nanotubes on one of two electrodes, wherein the two electrodes are spaced from each other; andsupplying a voltage between the two electrodes to break the one or more carbon nanotubes.2. The method of claim 1 , wherein the selecting one or more carbon nanotubes from a carbon nanotube array comprises:contacting a metal thread with the carbon nanotube array; andpulling the metal thread away from the carbon nanotube array.3. The method of claim 2 , wherein a diameter of the metal thread is in a range from about 20 nanometers to about 100 nanometers.4. The method of claim 1 , wherein the supplying the voltage between the two electrodes comprises placing the two electrodes with the one or more carbon nanotubes attached into a reaction chamber.5. The method of claim 4 , wherein the reaction chamber is under a vacuum.6. The method of claim 4 , wherein the reaction chamber is filled with a noble gas selected from the group consisting of helium claim 4 , argon claim 4 , and neon.7. The method of claim 1 , wherein the voltage is in a range from about 7V to about 10V.8. A method for making an emitter claim 1 , comprising:providing a plurality of carbon nanotubes in parallel with each other, wherein the plurality of carbon nanotubes has a plurality of first ends and a plurality of second ends opposite to the plurality ...

ELECTRON EMISSION ELEMENT, ELECTRON EMISSION DEVICE, CHARGE DEVICE, IMAGE FORMING DEVICE, ELECTRON RADIATION CURING DEVICE, LIGHT-EMITTING DEVICE, IMAGE DISPLAY DEVICE, BLOWER DEVICE, COOLING DEVICE, AND MANUFACTURING METHOD FOR ELECTRON EMISSION ELEMENT

An electron emission element () includes an electrode substrate () and a thin film electrode (), and emits electrons from the thin film electrode () by voltage application across the electrode substrate () and the thin film electrode (). An electron accelerating layer () containing at least insulating fine particles () is provided between the electrode substrate () and the thin film electrode (). The electrode substrate () has a convexoconcave surface. The thin film electrode () has openings () above convex parts of the electrode substrate (). 1. An electron emission element , comprising:an electrode substrate;a thin film electrode; andan electron accelerating layer between the electrode substrate and the thin film electrode, the electron accelerating layer containing at least insulating fine particles,the electron emission element emitting, from the thin film electrode, electrons which are accelerated between the electrode substrate and the thin film electrode by voltage application across the electrode substrate and the thin film electrode,the electrode substrate having a convexoconcave surface on which the electron accelerating layer is provided, andthe thin film electrode having openings above convex parts of the convexoconcave surface of the electrode substrate.2. The electron emission element as set forth in claim 1 , wherein the insulating fine particles are (i) monodisperse insulating fine particles and (ii) aligned in the electron accelerating layer so as to fill the electron accelerating layer.3. The electron emission element as set forth in claim 1 , wherein the insulating fine particles contain at least one of silicon oxide claim 1 , aluminum oxide claim 1 , and titanium oxide.4. The electron emission element as set forth in claim 1 , wherein the insulating fine particles have an average diameter of 5 nm through 1000 nm.5. The electron emission element as set forth in claim 1 , wherein the electron accelerating layer has a thickness of 8 nm through 3000 ...

SPARK GAP SWITCH FOR HIGH POWER ULTRA-WIDEBAND ELECTROMAGNETIC WAVE RADIATION FOR STABILIZED DISCHARGE

A spark gap switch for high power ultra-wideband electromagnetic wave radiation is provided. The spark gap switch includes a casing, electrodes, brackets and an electrode protrusion. Openings are formed in respective opposite ends of the casing. The electrodes are installed in the casing at positions spaced apart from each other in such a way that the electrodes face each other and are disposed inside the openings. The brackets are installed in the respective openings of the casing. The brackets fasten rear ends of the corresponding electrodes to the casing. The electrode protrusion is provided on a central portion of at least either of the electrodes to induce stabilized discharge. The maximum diameter of the electrodes is smaller than the inner diameter of the casing so that the circumferential outer surfaces of the electrodes do not make contact with the circumferential inner surface of the casing. 1. A spark gap switch for high power ultra-wideband electromagnetic wave radiation , comprising:a casing having a cylindrical shape, with openings formed in respective opposite ends of the casing;a plurality of electrodes installed in the casing at positions spaced apart from each other by a predetermined distance in such a way that the electrodes face each other and are disposed inside the openings, wherein surfaces of the electrodes mat face each other comprise planar or curved surfaces to increase capacitance;a plurality of brackets installed in the respective openings of the casing, the brackets fastening rear ends of the corresponding electrodes to the casing; andan electrode protrusion provided on a central portion of at least either of the electrodes, the electrode protrusion inducing stabilized discharge.2. The spark gap switch as set forth in claim 1 , wherein each of the electrodes has a “U” shape.3. The spark gap switch as set forth in claim 2 , wherein an electrode assisting member is provided on a central portion of at least either of the electrodes and a ...

METHOD FOR MAKING CARBON NANOTUBE FIELD EMITTER

The present application relates to a method for making a carbon nanotube field emitter. A carbon nanotube film is drawn from the carbon nanotube array by a drawing tool. The carbon nanotube film includes a triangle region. A portion of the carbon nanotube film closed to the drawing tool is treated into a carbon nanotube wire including a vertex of the triangle region. The triangle region is cut from the carbon nanotube film by a laser beam along a cutting line. A distance between the vertex of the triangle region and the cutting line can be in a range from about 10 microns to about 5 millimeters. 1. A method for making a carbon nanotube field emitter , comprising steps of:{'b': '1', '(S) providing a carbon nanotube array located on a substrate;'}{'b': '2', '(S) drawing a carbon nanotube film from the carbon nanotube array by a drawing tool, wherein the carbon nanotube film comprises a triangle region;'}{'b': '3', '(S) forming a carbon nanotube wire of a portion of the carbon nanotube film, wherein the carbon nanotube wire comprises a vertex of the triangle region;'}{'b': '4', '(S) cutting along the triangle region from the carbon nanotube film with a laser beam along a cutting line, and a distance between the vertex of the triangle region and the cutting line is in a range from about 10 microns to about 5 millimeters.'}2. The method of claim 1 , wherein the drawing tool is a clamp or an adhesive tape.33. The method of claim 1 , wherein in the step (S) claim 1 , forming the carbon nanotube wire comprises treating the portion of the carbon nanotube film with an organic solvent.4. The method of claim 3 , wherein the organic solvent comprise a material that is selected from the group consisting of ethanol claim 3 , methanol claim 3 , acetone claim 3 , dichloroethane claim 3 , chloroform claim 3 , or a mixture thereof.53. The method of claim 1 , wherein in the step (S) claim 1 , forming the carbon nanotube wire comprises twisting the portion of the carbon nanotube film.63 ...

Corrugated Dielectric for Reliable High-current Charge-emission Devices

Micro-fabricated charge-emission devices comprise an electrically conductive gate electrode with an aperture, an electrically conductive base electrode, a charge-emitting microstructure extending from a surface in electrical contact with the base electrode and terminating near the aperture of the gate electrode, and a dielectric layer stack disposed between the base electrode and the gate electrode. The dielectric layer stack comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed between the second dielectric layer and the base electrode. The first dielectric layer is of a different selectively etchable dielectric material than the second dielectric layer. The dielectric layer stack h formed therein a cavity within which the charge-emitting emitting microstructure is disposed. The cavity has a corrugated wall shaped by the first dielectric layer undercutting the second dielectric layer. The corrugated wall surrounds the charge-emitting microstructure disposed within the cavity. 1. A micro-fabricated charge-emission device comprising:an electrically conductive gate electrode with an aperture;an electrically conductive base electrode;a charge-emitting microstructure extending from a surface in electrically conductive contact with the base electrode and terminating near the aperture of the gate electrode; anda dielectric layer stack disposed between the base electrode and the gate electrode, the dielectric layer stack comprising a first dielectric layer and a second dielectric layer, the first dielectric layer being disposed between the second dielectric layer and the base electrode, the first dielectric layer being of a different selectively etchable dielectric material than the second dielectric layer, the dielectric layer stack having formed therein a cavity within which the charge-emitting microstructure is disposed, the cavity having a corrugated wall shaped by the first dielectric layer undercutting the second ...

CARBON NANOTUBE FIELD EMITTER

A carbon nanotube field emitter is disclosed. The carbon nanotube field emitter includes an emission portion and a supporting portion. The emission portion and the supporting portion are configured as one piece to form a roll structure. The emission portion includes a first rolled carbon nanotube layer, which includes a number of carbon nanotubes. The supporting portion includes a rolled composite layer, which includes at least one second rolled carbon nanotube layer and a rolled metal layer stacked with each other. Another carbon nanotube field emitter with a number of separated emission tips on the emission portion is also disclosed. 1. A carbon nanotube field emitter comprising an emission portion and a supporting portion , wherein the emission portion and the supporting portion form a single rolled structure , the emission portion comprises a first rolled carbon nanotube layer comprising a plurality of carbon nanotubes , and the supporting portion comprises a rolled composite layer comprising at least one second rolled carbon nanotube layer and a rolled metal layer stacked with each other.2. The carbon nanotube field emitter as claimed in claim 1 , wherein the plurality of carbon nanotubes is aligned along a first direction in the first rolled carbon nanotube layer.3. The carbon nanotube field emitter as claimed in claim 1 , wherein the at least one second rolled carbon nanotube layer comprises a plurality of carbon nanotubes and the plurality of carbon nanotubes is aligned along the first direction.4. The carbon nanotube field emitter as claimed in claim 1 , wherein both the first rolled carbon nanotube layer and the at least one second rolled carbon nanotube layer comprise at least one carbon nanotube drawn film.5. The carbon nanotube field emitter as claimed in claim 4 , wherein the at least one carbon nanotube drawn film comprises a plurality of carbon nanotubes claim 4 , and a majority of the plurality of carbon nanotubes are substantially parallel to each ...

METHOD FOR MAKING CARBON NANOTUBE FIELD EMITTER

A method for making a carbon nanotube field emitter is disclosed. The method includes steps of providing a carbon nanotube layer having a first surface and a second surface opposite to each other, wherein the first surface is divided into a first area and a second area along a first direction by a line, coating a metal layer on the first area of the first surface, and rolling the coated carbon nanotube layer around the first direction to form the carbon nanotube field emitter. 1. A method for making a carbon nanotube field emitter comprising:(a) providing a carbon nanotube layer having a first surface and a second surface opposite to each other, wherein the first surface is divided into a first area and a second area along a first direction by a line;(b) coating a metal layer on the first area; and(c) rolling the coated carbon nanotube layer around the first direction to form the carbon nanotube field emitter.2. The method as claimed in claim 1 , wherein the step (c) comprises forming an emission portion by rolling the second area of the carbon nanotube layer claim 1 , and forming a supporting portion by rolling the coated first area of the carbon nanotube layer claim 1 , the emission portion and the supporting portion being formed as one piece.3. The method as claimed in claim 2 , further comprising (d) cutting the emission portion into a plurality of emission tips.4. The method as claimed in claim 3 , wherein in the step (d) claim 3 , the emission portion is cut by a laser.5. The method as claimed in claim 4 , wherein an angle α formed between a cutting direction and the first direction is equal to or larger than 0 degrees and smaller than or equal to 5 degrees.6. The method as claimed in claim 1 , wherein in the step (c) claim 1 , the first surface is an inner surface of the rolled coated carbon nanotube layer.7. The method as claimed in claim 1 , wherein in the step (c) claim 1 , the second surface is an inner surface of the rolled coated carbon nanotube layer.8 ...

VACUUM ELECTRON POWER TUBE

A vacuum tube that may include but is not limited to a plurality of electrodes. A first electrode of the plurality of electrodes may be configured to operatively connect to an electrical source. A second electrode of the plurality of electrodes may be configured to operatively connect to a first load of a plurality of loads, wherein the first electrode may be configured to complete a first circuit through the second electrode and the first load. A third electrode of the plurality of electrodes may be configured to operatively connect to a second load of the plurality of loads that is independent from the first load, wherein the first electrode may be configured to complete a second circuit through the third electrode and the second load. 1. A vacuum tube comprising:a plurality of electrodes;a first electrode of the plurality of electrodes configured to operatively connect to an electrical source;a second electrode of the plurality of electrodes configured to operatively connect to a first load of a plurality of loads, wherein the first electrode is configured to complete a first circuit through the second electrode and the first load; anda third electrode of the plurality of electrodes configured to operatively connect to a second load of the plurality of loads that is independent from the first load, wherein the first electrode is configured to complete a second circuit through the third electrode and the second load.2. The vacuum tube of wherein the first electrode includes an anode claim 1 , wherein the second electrode includes a first cathode claim 1 , and wherein the third electrode includes a second cathode.3. The vacuum tube of further comprising at least one anode baffle claim 2 , wherein the at least one anode baffle is configured to restrict electron flow to near zero from the first cathode to the anode and from the second cathode to the anode claim 2 , except as electron flow is permitted via at least one cathode interface structure.4. The vacuum tube of ...

METHOD FOR MAKING FIELD EMISSION CATHODE

The disclosure relates to a method for making field emission cathode. A microchannel plate is provided. The microchannel plate includes a first surface and a second surface opposite to the first surface. The microchannel plate defines a number of holes extending through the microchannel plate from the first surface to the second surface. The plurality of holes are filled with a carbon nanotube slurry. The carbon nanotube slurry is adhered on inner walls of the plurality of holes. The carbon nanotube slurry in the plurality of holes is solidified. 1. A method for making field emission cathode , the method comprising:providing a first microchannel plate, wherein the first microchannel plate comprises a first surface and a second surface, opposite to the first surface; and the first microchannel plate defines a plurality of first holes extending through the first microchannel plate from the first surface to the second surface; andfilling the plurality of first holes with a carbon nanotube slurry, wherein the carbon nanotube slurry is adhered on inner walls of the plurality of first holes; andsolidifying the carbon nanotube slurry.2. The method of claim 1 , wherein the carbon nanotube slurry comprises a plurality of carbon nanotubes and an organic carrier.3. The method of claim 2 , wherein a weight ratio of the plurality of carbon nanotubes is in a range from about 2.5% to about 3% claim 2 , and a weight ratio of the organic carrier is in a range from about 97% to about 98%.4. The method of claim 1 , wherein a viscosity of the carbon nanotube slurry is in a range from about 10 P·s to about 11 P·s at a shear rate of about 10 second-1.5. The method of claim 1 , wherein the carbon nanotube slurry comprises a plurality of carbon nanotubes claim 1 , a plurality of conductive particles and an organic carrier.6. The method of claim 1 , wherein the carbon nanotube slurry comprises a plurality of carbon nanotubes claim 1 , a glass powders and an organic carrier.7. The method of ...

CARBON NANOTUBE FIELD EMITTER AND PREPARATION METHOD THEREOF

A method for making a carbon nanotube field emitter is provided. A carbon nanotube film is dealed with a carbon nanotube film in a circumstance with a temperature ranged from 1400 to 1800° C. and a pressure ranged from 40 to 60 MPa to form at least one first carbon nanotube structure. The at least one first carbon nanotube structure is heated to graphitize the at least one first carbon nanotube structure to form at least one second carbon nanotube structure. At least two electrodes is welded to fix one end of the at least one second carbon nanotube structure between adjacent two electrodes to form a field emission preparation body. The field emission preparation body has a emission end. The emission end is bonded to form a carbon nanotube field emitter. 1. A method for making a carbon nanotube field emitter , comprising:{'b': '1', 'S: handling a carbon nanotube film in an environment of a temperature ranged from 1400 to 1800° C. and a pressure ranged from 40 to 60 MPa to form at least one first carbon nanotube structure;'}{'b': '2', 'S: heating the at least one first carbon nanotube structure to graphitize the first carbon nanotube structure thereby forming at least one second carbon nanotube structure;'}{'b': '3', 'S: welding at least two electrodes to fix one end of the at least one second carbon nanotube structure between the at least two electrodes to form a field emission preparation body, wherein the field emission preparation body comprises an emission end; and'}{'b': '4', 'S: bonding the emission end of the field emission preparation to form a carbon nanotube field emitter.'}2. The method of claim 1 , wherein the at least one second carbon nanotube structure comprises a first end and a second end claim 1 , the first end is opposite to the second end claim 1 , and the first end of the at least one second carbon nanotube structure is fixed between the at least two electrodes by a spot welding method or a laser welding method.3. The method of claim 2 , wherein ...

APPARATUS FOR GENERATING X-RAY RADIATION IN AN EXTERNAL MAGNETIC FIELD

An apparatus is provided for generating X-ray radiation in an outer magnetic field, which may be generated by a magnetic field device. The apparatus includes a cathode configured to generate an electron beam and an anode configured to retard the electrons of the electron beam and generate an X-ray beam. The apparatus further includes a device configured to generate an electric field orientated from the anode in the direction of the cathode and substantially collinear to the outer magnetic field, wherein the cathode, as an electron emitter, includes a cold cathode that passively provides free electrons by field emission. 1. An apparatus for generating x-ray radiation in an external magnetic field generable by a magnetic field device , the apparatus comprising:{'b': '30', 'a cathode configured to generate an electron beam ();'}an anode configured to decelerate the electrons of the electron beam and generate an x-ray beam; and{'b': '50', 'a device configured to generate an electric field directed from the anode in a direction of the cathode, wherein the electric field is substantially collinear with the external magnetic field ();'}wherein the cathode as an electron emitter comprises a cold cathode that passively provides free electrons by field emission.2. The apparatus of claim 1 , wherein the electron emitter has a linear embodiment.3. The apparatus of claim 1 , wherein the electron emitter has a convex surface in a cross section in relation to an axial direction of extent claim 1 , wherein the convex surface extends exclusively in a direction of the anode.4. The apparatus of claim 1 , wherein the electron emitter has a form of a semi-cylinder in the cross section in relation to an axial direction of extent.5. The apparatus of claim 1 , wherein the cathode comprises a substrate on which the electron emitter is arranged.6. The apparatus of claim 3 , wherein the axial direction of extent extends parallel or at an angle to a first direction extending perpendicular to a ...

Chip Scale Encapsulated Vacuum Field Emission Device Integrated Circuit and Method of Fabrication Therefor

A chip scale encapsulated vacuum field emission device integrated circuit and method of fabrication therefor are disclosed. The vacuum field emission device is a monolithically fabricated triode vacuum field emission device, also known as a VACFET device. The VACFET device includes a substrate, a VACFET formed laterally on the substrate, and a containment shell that seals around a periphery of the VACFET and against the substrate. Preferably, the VACFET of the VACFET device includes an anode and a cathode formed on the substrate, a bottom gate and a top gate. The bottom gate is located between the anode and the cathode and the substrate, and the top gate is located above the anode and the cathode with respect to the substrate. 1. A monolithically fabricated vacuum field effect transistor (VACFET) device , comprising:a substrate;a VACFET formed laterally on the substrate; anda containment shell that seals around a periphery of the VACFET and against the substrate.2. The device of claim 1 , wherein the VACFET includes:an anode and a cathode formed on the substrate; anda bottom gate located between the anode and the cathode and the substrate.3. The device of claim 2 , wherein the cathode overlaps the bottom gate.4. The device of claim 2 , wherein the VACFET includes:a top gate located above the anode and the cathode with respect to the substrate.5. The device of claim 3 , wherein the top gate is housed within the containment shell.6. The device of claim 3 , wherein the cathode overlaps the top gate.7. The device of claim 2 , wherein the anode and the cathode are cantilevered above the substrate and over the bottom gate.8. The device of claim 1 , wherein the device includes a metal plug for closing an opening in the shell and creating a vacuum seal.9. The device of claim 8 , wherein the metal plug functions as a metal contact that provides an electrical connection to the VACFET.10. A method for monolithic fabrication of a VACFET device claim 8 , the method comprising: ...

INTEGRATED VACUUM MICROELECTRONIC STRUCTURE AND MANUFACTURING METHOD THEREOF

An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer. 1. A method , comprising:depositing a first insulating layer on a first surface of a substrate;depositing a first conductive layer on the first insulating layer;selectively removing portions of the first conductive layer;depositing a second insulating layer on the first conductive layer and the first insulating layer;forming a trench in the first and second insulating layers, the trench extending to the substrate, the trench being spaced from the first conductive layer by portions of the second insulating layer;forming a cathode by depositing a second conductive layer over the trench and on the second insulating layer; andforming an anode by forming a third conductive layer on a second surface of the substrate.2. The method according to claim 1 , further comprising:forming openings in the second insulating layer by selectively removing portions of the second insulating layer; anddepositing a third conductive layer on the second conductive layer and in the openings, the third conductive layer contacting the first conductive layer and the second conductive layer.3. The method according to ...

NANOSTRUCTURE FIELD EMISSION CATHODE STRUCTURE AND METHOD FOR MAKING

Various embodiments are described herein for nanostructure field emission cathode structures and methods of making these structures. These structures generally comprise an electrode field emitter comprising a resistive layer having a first surface, a connection pad having a first surface disposed adjacent to the first surface of the resistive layer, and a nanostructure element for emitting electrons in use, the nanostructure element being disposed adjacent to a second surface of the connection pad that is opposite the first surface of the connection pad. Some embodiments also include a coaxial gate electrode that is disposed about the nanostructure element. 1. An electrode field emitter comprising:a resistive layer having a first surface;a connection pad having a first surface disposed adjacent to the first surface of the resistive layer; anda nanostructure element for emitting electrons during use, the nanostructure element being disposed adjacent to a second surface of the connection pad that is opposite the first surface of the connection pad.2. The emitter of claim 1 , wherein the nanostructure element comprises one of a nanotube emitter claim 1 , a nanofiber emitter claim 1 , and a nanowire emitter.3. The emitter of claim 1 , wherein the nanostructure element is made from one of carbon claim 1 , ZnO claim 1 , TiO claim 1 , tungsten and gold.4. The emitter of claim 1 , wherein the nanostructure element has a diameter in the range of about 3 nanometers to about 100 nanometers and a length of about 1 micrometer to about 10 micrometers.5. The emitter of claim 1 , wherein the resistive layer comprises one of a pure semiconductor material claim 1 , a doped semiconductor material claim 1 , a metal oxide and combinations thereof.6. The emitter of claim 1 , wherein the resistive layer has a resistivity in the range of about 10to about 10ohm·m.7. The emitter of claim 1 , wherein the connection pad has a diameter in the range of about 0.5 micrometers to about 5 ...

METHOD OF MANUFACTURING LIQUID CRYSTAL DISPLAY

A method of manufacturing a liquid crystal display includes: preparing a lower mother substrate, where lower cells, each including a thin film transistor, are provided on the lower mother substrate, and a lower alignment layer is disposed on the lower cells; preparing an upper mother substrate, where upper cells corresponding to the lower cells are provided on the upper mother substrate, and an upper alignment layer is disposed on the upper cells; providing a mother substrate assembly by providing a liquid crystal mixture layer between the lower and upper mother substrates and combining the lower and upper mother substrates; providing a pretilt of the liquid crystals by applying a voltage to a voltage application unit of the lower mother substrate; and curing an alignment supporting agents in the liquid crystal mixture layer or the lower and upper alignment layers by irradiating light to a side of the mother substrate assembly. 1. A method of manufacturing a liquid crystal display , the method comprising:preparing a lower mother substrate, wherein a plurality of lower cells, each of which comprises a thin film transistor, is provided on the lower mother substrate, and a lower alignment layer is disposed on the plurality of lower cells;preparing an upper mother substrate, wherein a plurality of upper cells corresponding to the plurality of lower cells, respectively, are provided on the upper mother substrate, and an upper alignment layer is disposed on the plurality of upper cells;providing a mother substrate assembly by providing a liquid crystal mixture layer comprising liquid crystals between the lower mother substrate and the upper mother substrate and combining the lower mother substrate and the upper mother substrate;providing a pretilt of the liquid crystals by applying a voltage to a voltage application unit of the lower mother substrate, wherein the voltage application unit of the lower mother substrate is exposed by the upper mother substrate; andcuring an ...

INTEGRATED GAS DISCHARGE TUBE AND PREPARATION METHOD THEREFOR

Provided is an integrated gas discharge tube. In the integrated gas discharge tube, the structure of the gas discharge tube is regulated into an upper cover and an insulative base, and the internal side surface and the external side surface of the bottom surface of the insulative base are respectively subject to electrode integration, so that the discharge effect of the gas discharge tube is effectively increased and the preparation process and the preparation flow of a multi-terminal-to-ground gas discharge tube are greatly simplified so as to greatly simplify the preparation process and to realize batch production and high integration of the gas discharge tube. Also provided is a preparation method for an integrated gas discharge tube. 1. An integrated gas discharge tube , comprising: an upper cover , and an insulative base with a bottom integrated with a plurality of electrodes , wherein the insulative base has a cavity structure , the upper cover and the insulative base are connected in a sealed manner to form a cavity , the bottom comprises an inner surface and an outer surface , at least one electrode is disposed on the inner surface , at least two electrodes are disposed on the outer surface , and at least one of the at least two electrodes on the outer surface of the bottom is correspondingly connected electrically with at least one of the at least one electrode on the inner surface of the bottom.2. The integrated gas discharge tube of claim 1 , wherein the insulative base has a layered structure and comprises a bottom claim 1 , at least one cavity layer on the bottom claim 1 , and a sealing layer on the cavity layer claim 1 , and the sealing layer includes a solder layer for brazing welding at a high temperature or a metal layer for parallel welding.3. The integrated gas discharge tube of claim 2 , wherein at least one of the at least one cavity layer is provided with at least one conductive strip extending in a vertical direction or a transverse direction. ...

Field Emission Devices

A method for making field emission devices so that they have emitter tips in the form of a needle-like point with a width and length configured such that ratio of the width to the length ranges from about 0.001 to about 0.05, and associated methods for making the tips by 3-D printing. 1. A method for making a field emission device , comprising the steps of:providing an array of emitter tips; andcoating portions of the emitter tips with a conductive material by depositing the conductive material onto the emitter tips from one side only of the emitter tips at an angle of from about 30 degrees to about 60 degrees relative to the length axis of the emitter tips such that the conductive material is deposited onto the emitter tips in a sharp tip configuration in the form of a needle-like point with a width and length configured such that the ratio of the width to the length ranges from about 0.001 to about 0.05.2. The method of claim 1 , wherein the array of emitter tips is formed by 3-D printing.3. The method of claim 2 , wherein the 3-D printing is performed by one or more of fused deposition modeling claim 2 , inkjet printing claim 2 , stereolithography claim 2 , and selective sintering.4. The method of claim 2 , wherein the array of emitter tips formed by 3-D printing is made from one or more of carbon claim 2 , metal claim 2 , powder of nylon claim 2 , graphite-infused nylon claim 2 , aluminum-infused nylon and conductive resin.5. The method of claim 1 , wherein in the array the emitters are identical to one another.6. The method of claim 1 , wherein in the array the emitters are uniformly spaced apart.7. The method of claim 1 , wherein in the array the emitters are not identical to one another.8. The method of claim 1 , wherein in the array the emitters are not uniformly spaced apart.9. The method of claim 1 , wherein the step of providing the array of emitter tips comprises providing the array of emitter tips from a soluble material claim 1 , and the method further ...

SYSTEMS AND METHODS FOR IMPLEMENTING ROBUST CARBON NANOTUBE-BASED FIELD EMITTERS

Systems and methods in accordance with embodiments of the invention implement carbon nanotube-based field emitters. In one embodiment, a method of fabricating a carbon nanotube field emitter includes: patterning a substrate with a catalyst, where the substrate has thereon disposed a diffusion barrier layer; growing a plurality of carbon nanotubes on at least a portion of the patterned catalyst; and heating the substrate to an extent where it begins to soften such that at least a portion of at least one carbon nanotube becomes enveloped by the softened substrate. 1. A method of fabricating a carbon nanotube-based field emitter , comprising: 'wherein the substrate has thereon disposed a diffusion barrier layer;', 'patterning a substrate with a catalyst;'}growing a plurality of carbon nanotubes on at least a portion of the patterned catalyst; andheating the substrate to an extent where it begins to soften such that at least a portion of at least one carbon nanotube becomes enveloped by the softened substrate.2. The method of claim 1 , further comprising allowing the grown carbon nanotubes and the softened substrate to cool to room temperature.3. The method of claim 2 , wherein the substrate comprises titanium.4. The method of claim 3 , wherein the diffusion barrier layer comprises aluminum oxide.5. The method of claim 4 , wherein the diffusion barrier layer has a thickness of less than approximately 30 angstroms.6. The method of claim 3 , wherein the catalyst is patterned on to the substrate in the form of a plurality of dots.7. The method of claim 6 , wherein the catalyst pattern is created using a lift-off process.8. The method of claim 7 , wherein the thickness of the patterned catalyst is less than approximately 35 angstroms.9. The method of claim 6 , wherein the grown plurality of carbon nanotubes are in the form of bundles of carbon nanotubes claim 6 , wherein each bundle of carbon nanotubes corresponds with one dot.10. The method of claim 9 , wherein the ...

METHOD FOR FABRICATING FIELD EMISSION CATHODE STRUCTURE

A method for fabricating the field emission cathode structure includes following steps. A first carbon nanotube structure is provided. The first carbon nanotube structure is suspended. A voltage is applied to heat the first carbon nanotube structure to form a temperature gradient. A number of second carbon nanotubes are grown on a surface of the first carbon nanotube structure to form a second carbon nanotube structure. 1. A method for fabricating the field emission cathode structure , the method comprising:providing a first carbon nanotube structure;suspending the first carbon nanotube structure;applying a voltage to the first carbon nanotube structure to heat the first carbon nanotube structure to form a temperature gradient; andgrowing a plurality of second carbon nanotubes on a surface of the first carbon nanotube structure to form a second carbon nanotube structure.2. The method of claim 1 , wherein the first carbon nanotube structure is a free-standing structure.3. The method of claim 2 , wherein a part of the first carbon nanotube structure is suspended between a first support and a second support spaced from each other claim 2 , and the first carbon nanotubes extend from the first support to the second support.4. The method of claim 3 , wherein the first support and the second support are conductive claim 3 , the voltage is applied to the first carbon nanotube structure via the first support and the second support claim 3 , and a current flows through the first carbon nanotube structure from the first support to the second support.5. The method of claim 3 , wherein the temperature gradient is formed on the surface of the first carbon nanotube structure claim 3 , and a temperature decreases gradually along the direction away from the middle position between the first support and the second support.6. The method of claim 1 , wherein the first carbon nanotube structure comprises a plurality of first carbon nanotubes aligned along the same direction claim 1 , ...

CARBON NANOTUBE FIELD EMITTER AND PREPARATION METHOD THEREOF

A carbon nanotube field emitter comprises at least two electrodes and at least one graphitized carbon nanotube structure. The at least one graphitized carbon nanotube structure comprises a first end and a field emission end. The first end is opposite to the field emission end. The first end is fixed between the at least two electrodes, and the field emission end is exposed from the at least two electrodes and configured to emit electrons. 1. A carbon nanotube field emitter , comprising:at least two electrodes and at least one graphitized carbon nanotube structure, wherein the at least one graphitized carbon nanotube structure comprises a first end and a field emission end, the first end is opposite to the field emission end, the first end is fixed between the at least two electrodes, and the field emission end is exposed from the at least two electrodes and configured to emit electrons.2. The carbon nanotube field emitter of claim 1 , wherein a density of the graphitized carbon nanotube structure is larger than or equal to 1.6 g/m.3. The carbon nanotube field emitter of claim 1 , wherein the field emission end comprises a plurality of protrusions and a plurality of burrs.4. The carbon nanotube field emitter of claim 1 , wherein the graphitized carbon nanotube structure comprises a plurality of carbon nanotube drawn films stacked with each other.5. The carbon nanotube field emitter of claim 4 , wherein an angle between an aligned directions of carbon nanotubes in two adjacent carbon nanotube drawn films ranges from about 0 degrees to about 30 degrees.6. The carbon nanotube field emitter of claim 4 , wherein the angle between an aligned directions of carbon nanotubes in the two adjacent carbon nanotube drawn films is 0 degrees.7. The carbon nanotube field emitter of claim 4 , wherein each carbon nanotube drawn film comprises a plurality of carbon nanotubes claim 4 , and the plurality of carbon nanotubes are arranged parallel to a surface of a carbon nanotube drawn ...

Gate all around vacuum channel transistor

A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

Particle acceleration devices with improved geometries for vacuum-insulator-anode triple junctions

For high-voltage devices such as particle accelerators, novel geometries for a triple-junction at which an insulator, an anode and a vacuum meet are disclosed. A singularity in the electric field at the triple-junction is eliminated, reducing dielectric flashover and allowing the devices to operate at higher voltages without breakdown. In one aspect, such a device includes a cathode, an anode having an anode surface exposed to a vacuum, and a dielectric body disposed between the cathode and anode, the dielectric body having a dielectric surface that is exposed to the vacuum, wherein the dielectric surface and the anode surface approach each other such that an angle measured across the vacuum between the dielectric surface and the anode surface decreases with decreasing distance between the dielectric surface and the anode surface until the dielectric surface and the anode surface meet and are parallel.

VACUUM CHANNEL TRANSISTOR STRUCTURES WITH SUB-10 NANOMETER NANOGAPS AND LAYERED METAL ELECTRODES

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure. 1. A method of forming a semiconductor device , the method comprising:forming an emitter electrode and a collector electrode in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode comprising layers;forming a channel in the dielectric layer so as to traverse the nanogap; andforming a top layer over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.2. The method of claim 1 , wherein a dielectric material is formed on a global backgate.3. The method of claim 1 , wherein the emitter electrode and the collector electrode are formed on a high-k dielectric material.4. The method of claim 3 , wherein the high-k dielectric material is formed on a local bottom gate.5. The method of claim 1 , wherein the emitter electrode comprises an emitter tip opposing a collector tip of the collector electrode such that the nanogap is formed between the emitter and collector tips.6. The method of claim 5 , wherein the emitter tip comprises the layers.7. The method of claim 6 , wherein the collector tip comprises the layers.8. The method of claim 5 , wherein the layers comprise at least one low workfunction material interposed in a high workfunction material.9. The method of claim 1 , wherein the layers comprise one or more low workfunction layers and one or more high workfunction layers.10. ...

FOLD OVER EMITTER AND COLLECTOR FIELD EMISSION TRANSISTOR

A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned. 1. A field emission transistor comprising:a gate within a trench of a dielectric layer, the gate in electrical communication with a gate contact;an emitter comprising a first emitter portion lining a first sidewall of the trench and a second emitter portion angled from the first emitter portion toward the gate; anda collector comprising a first collector portion lining a second sidewall of the trench and a second collector portion angled from the first collector portion toward the gate;wherein the emitter and collector are separated from the gate by a void.2. The field emission transistor of claim 1 , further comprising:gate dielectric material between and contacting the gate contact and the first emitter portion and between and contacting the gate contact and the first collector portion.3. The field emission transistor of claim 1 , wherein the first emitter portion and the first collector portion are substantially parallel to the gate.4. The field emission transistor of claim 1 , wherein the second emitter portion and the second collector portion are substantially ...

ELECTRIC FIELD EMITTING SOURCE, ELEMENT USING SAME, AND PRODUCTION METHOD THEREFOR

An electric field emitting source is equipped with an electron emitting film which comprises a nano-sized electron emitting substance and has a first surface and a second surface constituting the surface opposite thereto, and a cathode which secures one end of the electron emitting film and comprises a first block and a second block respectively corresponding to the first surface and the second surface of the electron emitting film. 1. A field emission source comprising:an electron emission film containing nano-sized electron emission materials and having a first surface and a second surface opposite to the first surface; anda cathode comprising a first block corresponding to the first surface and a second block corresponding to the second surface to fix one end of the electron emission film.2. The field emission source of claim 1 ,wherein the cathode is provided on both ends of the field emission film.3. The field emission source of claim 1 ,wherein at least one of the first and second blocks is formed of one of an insulating material and a metallic material.4. The field emission source of claim 1 ,wherein the electron emission materials of the electron emission film are combined to one another through a molecular force without requiring a binder.5. The field emission source of claim 1 ,wherein the field emission source further comprises a base that supports the first block, andthe first surface of the field emission film is positioned in parallel with a surface of the base.6. The field emission source of claim 2 ,wherein at least one of the first and second blocks is formed of one of an insulating material and a metallic material.7. The field emission source of claim 2 ,wherein the electron emission materials of the electron emission film are combined to one another through a molecular force without requiring a binder.8. The field emission source of claim 2 ,wherein the field emission source further comprises a base that supports the first block, andthe first ...

CATHODE STRUCTURE FOR COLD FIELD ELECTRON EMISSION AND METHOD OF FABRICATING THE SAME

A cathode structure for cold field electron emission and method of fabricating a single-tip cathode structure for cold field electron emission. The cathode structure comprises a pointed cathode wire; and a graphene-based coating on at least a tip of the pointed cathode wire. In a preferred embodiment, graphene is coated on nickel tips by chemical vapour deposition wherein nickel functions as a catalyst for growth of graphene. The cathode structure provides stable cold field emission for electron microscopy and lithography applications and exhibits an ultralow work function value of about 1.1 eV. 1. A cathode structure for cold field electron emission comprising:a pointed cathode wire; anda graphene-based coating on at least a tip of the pointed cathode wire.2. The cathode structure of claim 1 , exhibiting a low work function value of about 1.1 eV.3. The cathode structure of claim 1 , wherein the cathode wire comprises a metal.4. The cathode structure of claim 3 , wherein the metal is in polycrystalline form.5. The cathode structure of claim 3 , wherein the metal comprises one or more of a group consisting of Ni claim 3 , Co claim 3 , Pd claim 3 , Al claim 3 , Cu claim 3 , and Ag.6. The cathode structure of claim 1 , wherein the graphene based coating comprises one or more of a group consisting of graphene claim 1 , graphene oxide (GO) claim 1 , rGO and their derivatives.7. The cathode structure of claim 1 , wherein a radius of the tip is in the range from about 100 to 800 nm.8. The cathode structure of claim 1 , exhibiting a low electric field strength requirement of about 0.5 V/nm.9. A method of fabricating a cathode structure for cold field electron emission claim 1 , the method comprising the steps of:providing a pointed cathode wire; andcoating at least a tip of the pointed cathode wire with a graphene-based material.10. The method of claim 9 , wherein the coating is performed by chemical vapor deposition claim 9 , CVD.11. The method of claim 10 , wherein a ...

LIGHT EMITTING DIODES, FAST PHOTO-ELECTRON SOURCE AND PHOTODETECTORS WITH SCALED NANOSTRUCTURES AND NANOSCALE METALLIC PHOTONIC CAVITY AND ANTENNA, AND METHOD OF MAKING SAME

A new ultra-thin high-efficiency photoelectron source utilizing a metallic photonic resonant cavity having a photonic resonant cavity with a top metallic with a plurality of openings, each having an average dimension less than the wavelength of the excitation photons in vacuum, a bottom metallic layer and a photoelectron emission layer of semiconductor positioned between the top metallic layer and the bottom metallic. 131-. (canceled)32. A photoelectron source assembly comprising:a photonic resonant cavity enhancing the absorption of the excitation photons includinga top metallic layer with a plurality of openings, each having an average dimension less than the wavelength of the excitation photons in vacuum;a bottom metallic layer; anda photoelectron emission layer of semiconductor positioned between the top metallic layer and the bottom metallic layerwherein, upon shinning excitation photons on the top metallic layer, photoelectrons are generated in the photoelectron emission layer and escape to outside of the photonic resonant cavity.3338-. (canceled)3938. The photoelectron source assembly of claim wherein each of the openings a shape selected from the group consisting of round , polygon , and triangle or a superposition of one or more thereof.4038. The photoelectron source assembly of claim wherein the openings are openings between a plurality of metallic disks.41. The photoelectron source assembly of wherein the shape of the disks is selected from the group consisting of round claim 40 , polygon claim 40 , and triangle claim 40 , or a superposition of one or more thereof.42. The photoelectron source assembly of wherein the top metallic layer has a thickness at least a factor of 2 smaller than the wavelength of the excitation photons in vacuum.43. The photoelectron source assembly of wherein the top metallic layer has a thickness of about 15 to about 40 nm.44. The photoelectron source assembly of wherein the top metallic layer or the bottom metallic layer is ...

VACUUM CHANNEL TRANSISTOR STRUCTURES WITH SUB-10 NANOMETER NANOGAPS AND LAYERED METAL ELECTRODES

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure. 1. A semiconductor device comprising:an emitter electrode and a collector electrode formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode comprising layers;a channel formed in the dielectric layer so as to traverse the nanogap; anda top layer over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.2. The semiconductor device of claim 1 , wherein a dielectric material is formed on a global backgate underlying the channel.3. The semiconductor device of claim 1 , wherein the emitter electrode and the collector electrode are formed on a high-k dielectric material.4. The semiconductor device of claim 3 , wherein the high-k dielectric material is formed on a local bottom gate.5. The semiconductor device of claim 1 , wherein the emitter electrode comprises an emitter tip opposing a collector tip of the collector electrode such that the nanogap is formed between the emitter and collector tips.6. The semiconductor device of claim 5 , wherein the emitter tip comprises the layers.7. The semiconductor device of claim 5 , wherein the collector tip comprises the layers.8. The semiconductor device of claim 5 , wherein the layers comprise at least one low workfunction material interposed in a high workfunction material.9. The semiconductor device of claim 1 , wherein the layers ...

FIELD-EMISSION DEVICE WITH IMPROVED BEAMS-CONVERGENCE

The present disclosure may provide a field emission device with an enhanced beam convergence. For this, the device may include a gate structure disposed between a cathode electrode and an anode electrode, wherein the gate structure includes a gate electrode and an atomic layer sheet disposed on the gate electrode, the gate electrode facing an emitter and having at least one aperture formed therein. 1. A field emission device comprising:a cathode electrode;at least one emitter on the cathode electrode;an anode electrode disposed away in a longitudinal direction of the device from the cathode electrode; anda gate structure disposed between the cathode electrode and the anode electrode, wherein the gate structure includes a gate electrode and an atomic layer sheet disposed on the gate electrode, the gate electrode facing the emitter and having at least one aperture formed therein.2. The device of claim 1 , wherein the at least one aperture comprises a plurality of apertures claim 1 , and the at least one emitter comprises a plurality of emitters claim 1 , wherein the plurality of apertures have a locational correspondence respectively with the plurality of emitters.3. The device of claim 2 , wherein the atomic layer sheet is curved in each of the apertures regions.4. The device of claim 3 , wherein the curvedness of the atomic layer sheet allows a reduced distortion of a potential distribution between the gate structure and the cathode electrode claim 3 , and claim 3 , hence claim 3 , electrons emitted from the emitters have an enhanced trajectory convergence.5. The device of claim 1 , wherein the at least one aperture comprises a plurality of apertures claim 1 , and the at least one emitter comprises a plurality of emitters claim 1 , wherein the plurality of apertures have a size-correspondence respectively with the plurality of emitters.6. The device of claim 1 , wherein the atomic layer sheet includes a graphene sheet.7. The device of claim 1 , wherein the atomic ...

ELECTRON EMISSION SOURCE AND METHOD FOR MAKING THE SAME

An electron emission source is provided. The electron emission source comprises a first electrode, an insulating layer, and a second electrode, The first electrode, the insulating layer, and the second electrode are successively stacked with each other. the second electrode is a graphene layer, and the graphene layer is an electron emission end to emit electron. A thickness of the graphene layer ranges from about 0.1 nanometers to about 50 nanometers. 1. An electron emission source , comprising a first electrode , an insulating layer , and a second electrode successively stacked in a said order , the second electrode is a graphene layer , a thickness of the graphene layer ranges from approximately 0.1 nanometers to approximately 50 nanometers , and the graphene layer defines an electron emission end to emit electrons.2. The electron emission source of claim 1 , wherein the graphene layer comprises at least one graphene film claim 1 , the graphene film consists of a single-layer graphene.3. The electron emission source of claim 1 , wherein the graphene layer consists of a single-layer graphene claim 1 , and the single-layer graphene has a thickness of one single carbon atom.4. The electron emission source of claim 1 , wherein a material of the insulating layer is alumina claim 1 , silicon nitride claim 1 , silicon oxide claim 1 , tantalum oxide claim 1 , or boron nitride.5. The electron emission source of claim 4 , wherein the material of the insulating layer is boron nitride claim 4 , and a thickness of the insulating layer ranges from approximately 0.3 nanometers to approximately 0.6 nanometers.6. The electron emission source of claim 1 , wherein the electron emission source consists of the first electrode claim 1 , a boron nitride layer claim 1 , and the graphene layer successively stacked in the said order.7. A method for making an electron emission source claim 1 , comprising:depositing an insulating layer on a surface of a first electrode, wherein the ...

X-RAY TUBE HAVING PLANAR EMITTER WITH TUNABLE EMISSION CHARACTERISTICS

An electron emitter can include: a plurality of elongate rungs connected together end to end from a first emitter end to a second emitter end in a plane so as to form a planar pattern; a plurality of corners, wherein each elongate rung is connected to another elongate rung through a corner having a corner apex and an opposite corner nadir; a first gap between adjacent non-connected elongate rungs, wherein the first gap extends from the first emitter end to a middle rung; a second gap between adjacent non-connected elongate rungs, wherein the second gap extends from the second emitter end to the middle rung, wherein the first gap does not intersect the second gap; and one or more cutouts at one or more of the corners of the plurality of corners between the corner apex and corner nadir or at the corner nadir. 1. An electron emitter comprising:a plurality of elongate rungs connected together end to end from a first emitter end to a second emitter end in a plane so as to form a planar pattern;a plurality of corners, wherein each elongate rung is connected to another elongate rung through a corner of the plurality of corners, each corner having a corner apex and an opposite corner nadir between the connected elongate rungs of the plurality of elongate rungs;a first gap between adjacent non-connected elongate rungs of the plurality of elongate rungs, wherein the first gap extends from the first emitter end to a middle rung;a second gap between adjacent non-connected elongate rungs of the plurality of elongate rungs, wherein the second gap extends from the second emitter end to the middle rung, wherein the first gap does not intersect the second gap; andone or more cutouts at one or more of the corners of the plurality of corners between the corner apex and corner nadir or at the corner nadir.2. The emitter of claim 1 , wherein one or more body portions of each corner between the corner apex and corner nadir claim 1 , excluding the one or more cutouts claim 1 , together ...

Field emission devices and methods for making the same

The present disclosure includes field emission device embodiments. The present disclosure also includes method embodiments for forming field emitting devices. One device embodiment includes a housing defining an interior space including a lower portion and an upper portion, a cathode positioned in the lower portion of the housing, a elongate nanostructure coupled to the cathode, an anode positioned in the upper portion of the housing, and a control grid positioned between the elongate nanostructure and the anode to control electron flow between the anode and the elongate nanostructure.

SELF-ALIGNED GATED EMITTER TIP ARRAYS

Methods for fabrication of self-aligned gated tip arrays are described. The methods are performed on a multilayer structure that includes a substrate, an intermediate layer that includes a dielectric material disposed over at least a portion of the substrate, and at least one gate electrode layer disposed over at least a portion of the intermediate layer. The method includes forming a via through at least a portion of the at least one gate electrode layer. The via through the at least one gate electrode layer defines a gate aperture. The method also includes etching at least a portion of the intermediate layer proximate to the gate aperture such that an emitter structure at least partially surrounded by a trench is formed in the multilayer structure. 1. A method for forming a self-aligned gated emitter cell , comprising: a substrate;', 'an intermediate layer comprising a dielectric material disposed over at least a portion of the substrate; and', 'at least one gate electrode layer disposed over at least a portion of the intermediate layer;, 'providing a multilayer structure, comprisingforming a via through at least a portion of the at least one gate electrode layer, wherein the via through the at least one gate electrode layer defines a gate aperture; andetching at least a portion of the intermediate layer proximate to the gate aperture such that an emitter structure at least partially surrounded by a trench is formed in the multilayer structure.2. The method of claim 1 , wherein the substrate comprises a semiconductor claim 1 , a III-V compound claim 1 , a metal claim 1 , or a dielectric material.3. The method of claim 1 , wherein the substrate comprises silicon claim 1 , germanium claim 1 , gallium arsenide claim 1 , gallium nitride claim 1 , silicon carbide claim 1 , an oxide of silicon claim 1 , or a transition metal oxide.4. The method of claim 1 , wherein the intermediate layer comprises at least one post structure claim 1 , and wherein the at least one post ...

MICROPLASMA GENERATION DEVICES AND ASSOCIATED SYSTEMS AND METHODS

Microplasma generators and associated arrays and methods are described herein. Certain embodiments relate to a microplasma generator in which an elongated semiconductor structure can control electronic cun'ent supplied to a microplasma cavity. Plasmas can be created by supplying energy to a neutral gas so that free electrons and ions are created. In a thermal plasma, electrons, ions, and neutral atoms and/or molecules (referred to as “neutrals”) are in thermal equilibrium 1. A microplasma generator , comprising:an elongated semiconductor structure comprising a longitudinal axis; anda microplasma cavity spatially defined by a structure comprising the elongated semiconductor structure and an electrode,wherein the microplasma generator is configured to generate a microplasma when a voltage is applied across the elongated semiconductor structure along the longitudinal axis of the structure.2. The microplasma generator of claim 1 , wherein the voltage is a quasi-static voltage.3. The microplasma generator of claim 1 , wherein the voltage is a direct current voltage.4. The microplasma generator of claim 1 , comprising a gate electrode adjacent to the elongated semiconductor structure and outside the microplasma cavity.5. The microplasma generator of claim 4 , wherein the gate electrode is separated from the elongated semiconductor structure by an electrically insulating material.6. The microplasma generator of claim 4 , wherein the gate electrode is configured such that claim 4 , when a voltage is applied to the gate electrode claim 4 , a saturation current of the elongated semiconductor structure is altered.7. The microplasma generator of claim 4 , wherein the gate electrode is formed claim 4 , at least in part claim 4 , of a metal and/or a semiconductor.8. The microplasma generator of claim 1 , wherein the semiconductor structure has a saturation current of at least about 0.1 mA.9. (canceled)10. The microplasma generator of claim 1 , wherein the aspect ratio of the ...

ELECTRON EMISSION SOURCE AND METHOD FOR FABRICATING THE SAME

Provided is an electron emission source including a substrate, a fixed structure provided on the substrate, and an electron emission yarn provided between the substrate and the fixed structure. The fixed structure includes a first portion having a first width and a second portion having a second width greater than the first width, and the electron emission yarn extends on a first sidewall of the first portion of the fixed structure from between the fixed structure and the substrate. 1. An electron emission source comprising:a substrate;a fixed structure provided on the substrate; andan electron emission yarn provided between the substrate and the fixed structure,wherein the fixed structure comprises a first portion having a first width and a second portion having a second width greater than the first width, andthe electron emission yarn extends on a first sidewall of the first portion of the fixed structure from between the fixed structure and the substrate.2. The electron emission source of claim 1 , wherein the electron emission yarn protrudes from an upper surface of the fixed structure.3. The electron emission source of claim 2 , wherein the electron emission yarn protrudes by several nanometers to several micrometers from the upper surface of the fixed structure.4. The electron emission source of claim 2 , wherein the electron emission yarn extends in a direction perpendicular to the upper surface of the substrate.5. The electron emission source of claim 1 , wherein the first portion of the fixed structure comprises a second sidewall facing an opposite direction to the first sidewall claim 1 , and the electron emission yarn extends on the second sidewall from between the fixed structure and the substrate.6. The electron emission source of claim 1 , wherein the electron emission yarn is provided in plurality claim 1 , and end portions of the plurality of electron emission yarns have the same heights.7. The electron emission source of claim 1 , wherein the first ...

SELF-ALIGNED GATED EMITTER TIP ARRAYS

Methods for fabrication of self-aligned gated tip arrays are described. The methods are performed on a multilayer structure that includes a substrate, an intermediate layer that includes a dielectric material disposed over at least a portion of the substrate, and at least one gate electrode layer disposed over at least a portion of the intermediate layer. The method includes forming a via through at least a portion of the at least one gate electrode layer. The via through the at least one gate electrode layer defines a gate aperture. The method also includes etching at least a portion of the intermediate layer proximate to the gate aperture such that an emitter structure at least partially surrounded by a trench is formed in the multilayer structure. 1. A method for forming a self-aligned gated emitter cell , comprising: a substrate;', 'an intermediate layer comprising a dielectric material disposed over at least a portion of the substrate; and', 'at least one gate electrode layer disposed over at least a portion of the intermediate layer;, 'providing a multilayer structure, comprisingforming a via through at least a portion of the at least one gate electrode layer, wherein the via through the at least one gate electrode layer defines a gate aperture; andetching at least a portion of the intermediate layer proximate to the gate aperture such that an emitter structure at least partially surrounded by a trench is formed in the multilayer structure.227-. (canceled) The present application claims a priority benefit to U.S. provisional application Ser. No. 61/733,180, filed Dec. 4, 2012, entitled “Self-Aligned Grated Tip Arrays for Efficient ionization of Gasses and Electron Emission,” U.S. provisional application Ser. No. 61/843,784, filed Jul. 8, 2013, entitled “Self-Aligned Gated Emitters Tips and Arrays Including Such Emitter Tips,” U.S. provisional application Ser. No. 61/843,805, filed Jul. 8, 2013, entitled “Low-Voltage High-Pressure Field Ionizer for Portable ...

UV Pipe

A pipe source of UV flux has an inner pipe made of UV transmissive material and coated on its outer surface with a UV emitting phosphor. An outer pipe has a cathode array disposed on or near its inner surface, such as an array of thermionic filament cathodes mounted longitudinally or transverse to the length of the pipe, cold cathode arrays formed on the inner surface of the pipe or cold cathode arrays formed on separate substrates which are then attached to the inner surface of the outer pipe. The ends of this two-pipe assembly are hermetically sealed with flanges or end plates at either end of the pipe and evacuated to a pressure below 1×10Torr. Internal spacing rings may be used to provide additional separation between the inner and out pipes. Current from the cathode arrays is accelerated by an anode voltage to strike the UV phosphors when then emit UV light flux which illuminates the inside of the pipe and the fluid material flowing through the inner pipe. 1.2. A cathodoluminescent UV pipe source of ultraviolet light flux comprising:an inner pipe made of UV transmissive material and coated on its outer surface with a cathodoluminescent UV emitting phosphor;the UV phosphor layer on the outer surface of the inner pipe covered with a thin layer of conductive, UV reflective material;an outer pipe with one or more cathode arrays disposed on or near its inner surface;{'sup': '−3', 'a vacuum of at least 10Torr between the inner and outer pipes;'}end plates or flanges providing a vacuum hermetic seal of the space between the inner and outer pipes;the cathode arrays operable to emit current which is accelerated across the vacuum space between the inner and outer pipes by an anode voltage to strike the UV phosphors Which then emit UV flux which illuminates the inside of the pipe and material flowing through the inner pipe.3. The pipe source of in which UV-C phosphors belong to the group consisting of zirconium pyrophosphate; hafnium pyrophosphate claim 2 , yttrium ...

MICRO-PLASMA FIELD EFFECT TRANSISTORS

In some aspects, a micro-plasma device comprises a plasma gas enclosure containing at least one plasma gas, a plasma generation circuit interfaced with the plasma gas enclosure, and a plurality of electrodes interfaced with the plasma gas enclosure. In other aspects, a micro-plasma circuitry apparatus comprises a first layer having plasma generating electrodes, a second layer having a cavity formed therein, and a third layer having a circuit formed therein. The circuit includes a micro-plasma circuit (MPC) that includes one or more micro-plasma devices (MPDs). A metallic layer covers the MPC except at locations of the MPDs. The first layer is bonded to the second layer and the second layer is bonded to the third layer, thereby forming an enclosure that contains at least one plasma gas. 1. A micro-plasma device , comprising:a plasma gas enclosure containing at least one plasma gas;a plasma generation circuit interfaced with the plasma gas enclosure; anda plurality of electrodes interfaced with the plasma gas enclosure.2. The micro-plasma device of claim 1 , wherein the at least one plasma gas includes at least one noble gas.3. The micro-plasma device of claim 1 , wherein the plasma enclosure is at least partially comprised of fused silica.4. The micro-plasma device of claim 1 , wherein the plasma generation circuit includes plasma generating electrodes.5. The micro-plasma device of claim 4 , wherein the plasma generating electrodes are formed as an interdigital transducer (IDT).6. The micro-plasma device of claim 4 , wherein the plasma generating electrodes are formed in a layer at least partially comprised of fused silica.7. The micro-plasma device of claim 6 , wherein the layer is bonded to the plasma enclosure.8. The micro-plasma device of claim 1 , wherein the plasma generation circuit includes an RF power source.9. The micro-plasma device of claim 1 , wherein the plasma generation circuit includes a matching inductor.10. The micro-plasma device of claim 1 , ...

Planar Field Emission Transistor

A field emission transistor uses carbon nanotubes positioned to extend along a substrate plane rather than perpendicularly thereto. The carbon nanotubes may be pre-manufactured and applied to the substrate and then may be etched to create a gap between the carbon nanotubes and an anode through which electrons may flow by field emission. A planar gate may be positioned beneath the gap to provide a triode structure. 1. A field emission transistor comprising:a planar substrate;a first and second electrode supported by the substrate in spaced opposition across a separation region extending along a plane of the substrate;a plurality of carbon nanotubes in electrical communication with the first electrode and extending from the first electrode toward the second electrode to terminate at a free space region in the separation region; anda gate electrode for establishing an electrical field in the free space region;wherein electrons may be transmitted between the first and second electrodes by a combination of electrical conduction through the plurality of carbon nanotubes and field emissions in the free space region, the latter controllable by the gate electrode.2. The field emission transistor of wherein the plurality of carbon nanotubes are oriented to preferentially extend along a direction perpendicular to an extent of the first and second electrodes along the planar substrate.3. The field emission transistor of wherein the free space region for each of the plurality of carbon nanotubes is substantially identical.4. The field emission transistor of wherein the first electrode is a metal layer applied to the substrate over pre-applied carbon nanotubes.5. The field emission transistor of further including an insulating material supported by the substrate within the separation region to provide an insulating surface extending along the plane of the substrate to which the plurality of carbon nanotubes are applied.6. The field emission transistor of wherein the gate is a ...

PYROLYZED POROUS CARBON MATERIALS AND ION EMITTERS

Embodiments related to the use and production of porous carbon materials in ion emitters and other applications are described 1. An ion emitter comprising:a porous carbon emitter body; anda source of ions in fluid communication with the porous emitter body, wherein a mean pore radii of the porous carbon emitter body is from 100 nm to 1 μm, and wherein a standard deviation of the mean pore radii is from 10 nm to 70 nm.2. (canceled)3. The ion emitter of claim 2 , wherein a mean pore radii of the porous carbon emitter body is from 200 nm to 800 nm.4. (canceled)5. The ion emitter of claim 1 , wherein the porous emitter body is at least one of a carbon aerogel and a carbon xerogel.6. The ion emitter of claim 1 , wherein the porous carbon emitter body is disposed on a substrate.7. The ion emitter of claim 6 , wherein the porous carbon emitter body is monolithically formed with the substrate.8. The ion emitter of claim 1 , wherein a thermal expansion hysteresis of the carbon porous emitter body is less than or equal to 5%.9. The ion emitter of claim 1 , wherein the source of ions is an ionic liquid.10. An array of ion emitters comprising:a substrate;a plurality of porous carbon emitter bodies disposed on the substrate; anda source of ions in fluid communication with the plurality of porous emitter bodies through the substrate, wherein a mean pore radii of the porous carbon emitter body is from 100 nm to 1 μm, and wherein a standard deviation of the mean pore radii is from 10 nm to 70 nm.11. (canceled)12. The array of ion emitters of claim 11 , wherein a mean pore radii of the plurality of porous carbon emitter bodies is from 200 nm to 800 nm.13. (canceled)14. The array of ion emitters of claim 10 , wherein the plurality of porous carbon emitter bodies are at least one of a carbon aerogel and a carbon xerogel.15. The array of ion emitters of claim 10 , wherein the plurality of porous carbon emitter bodies are monolithically formed with the substrate.16. The array of ion ...

FIELD EMISSION DEVICE

Provided is a field emission device. The field emission device includes a cathode electrode having a first surface and a second surface facing the first surface, the cathode electrode including grooves that are recessed from the first surface toward the second surface, the grooves extending in a first direction parallel to the first surface and emitter structures which are disposed within the grooves and each of which includes a core extending in the first direction and a conductive wire configured to surround the core. The grooves may be arranged in a second direction crossing the first direction, and the emitter structures may be disposed at vertical levels different from each other. 1. A field emission device comprises:a cathode electrode having a first surface and a second surface facing the first surface, the cathode electrode comprising grooves that are recessed from the first surface toward the second surface, the grooves extending in a first direction parallel to the first surface; andemitter structures which are disposed within the grooves and each of which comprises a core extending in the first direction and a conductive wire configured to surround the core,wherein the grooves are arranged in a second direction crossing the first direction, andthe emitter structures are disposed at vertical levels different from each other.2. The field emission device of claim 1 , wherein the first surface of the cathode electrode comprises a concave region that is recessed toward the second surface claim 1 , andthe grooves are defined in the concave region.3. The field emission device of claim 2 , wherein the concave region has a constant height along the first direction.4. The field emission device of claim 1 , wherein the grooves comprise a first groove and a second groove spaced apart from each other in a second direction perpendicular to the first direction claim 1 ,a bottom surface of the first groove is inclined with respect to a bottom surface of the second groove ...

METHOD OF MANUFACTURING EMITTER

Disclosed is a method of manufacturing an emitter in which the tip of the emitter can be formed into a desired shape even when various materials are used for the emitter. The method includes performing an electrolytic polishing process of polishing a front end of a conductive emitter material so that a diameter of the front end is gradually reduced toward a tip; performing a first etching process by irradiating a processing portion of the emitter material processed by the electrolytic polishing process with a charged particle beam; performing a sputtering process by irradiating the pointed portion formed by the first etching process with a focused ion beam; and performing a secondary etching process of further sharpening the tip by an electric field induced gas etching processing while observing a crystal structure of the tip of the pointed portion processed by the sputtering process using a field ion microscope. 1. A method of manufacturing a sharpened needle-shaped emitter , the method comprising:performing an electrolytic polishing process of polishing a front end of a conductive emitter material so that a diameter of the front end is gradually reduced toward a tip;performing a first etching process by irradiating a processing portion of the emitter material processed by the electrolytic polishing process with a charged particle beam to form a pyramid-shaped pointed portion with the tip as an apex;performing a sputtering process by irradiating the pointed portion formed by the first etching process with a focused ion beam using rare gas as an ionizing gas; andperforming a secondary etching process of further sharpening the tip by an electric field induced gas etching processing while observing a crystal structure of the tip of the pointed portion processed by the sputtering process with a field ion microscope, thereby making a number of atoms constituting the tip to be equal to or less than a predetermined number.2. The method of claim 1 , wherein the sputtering ...

CIRCUIT FOR INHIBITING SINGLE-ENDED ANALOGUE SIGNAL NOISE, AND TERMINAL ATTACHMENT

The utility model discloses a circuit for inhibiting single-ended analogue signal noises and a terminal accessory. The circuit includes an input interface module, a differential amplification module, an analogue signal processing module, an isolation module and a control module, wherein the input interface module at least includes an analogue signal line and a digital signal line, the differential amplification module includes differential input ends and an output end; the analogue signal line and the digital signal line of the input interface module are respectively connected to the differential input ends of the differential amplification module, so that the analogue signal line and the digital signal line form a pseudo-differential pair, and the output end of the differential amplification module is connected to the analogue signal processing module; the digital signal line is further connected to the isolation module, and the isolation module is further connected to the control module. 1. A circuit for inhibiting single-ended analogue signal noises , wherein the circuit is used for connecting a host , the circuit comprises an input interface module , a differential amplification module , an analogue signal processing module , an isolation module and a control module , wherein the differential amplification module comprises differential input ends and an output end;the input interface module is respectively connected to the differential input ends of the differential amplification module through an analogue signal line and a digital signal line, and the output end of the differential amplification module is connected to the analogue signal processing module; wherein the analogue signal line is used for transmitting an analogue signal, the analogue signal is a single-ended analogue signal, and the single-end analogue signal is the analogue signal forming a loop with a ground signal; the digital signal line is used for transmitting a digital signal, and the digital ...

SEMICONDUCTOR-FREE VACUUM FIELD EFFECT TRANSISTOR FABRICATION AND 3D VACUUM FIELD EFFECT TRANSISTOR ARRAYS

A vacuum field-emission-transistor device, a drain comprised of either a metal or a semimetal material, a gate arranged adjacent to, but separated from, the drain, a source comprised of either a metal or a semimetal material adjacent to, but separated from the metal gate, and a void through the metal drain and the metal gate to expose the drain, wherein the distance between the drain and the source is shorter than a mean free path distance of electrons in air. 1. A vacuum field-emission-transistor device , comprising:a drain electrode comprised of either a metal or a semimetal material;a metal gate arranged adjacent to, but separated from, the drain;a source electrode comprised of either a metal or a semimetal material adjacent to, but separated from the metal gate; anda void through just the source and the metal gate to expose the drain, wherein the void is open to ambient atmosphere,wherein a distance between the drain and the source is shorter than a mean free path distance of electrons in ambient air and the distance between the metal gate and the source is less than half the distance between the metal gate and the drain.2. The device of claim 1 , further comprising an array of devices arranged adjacent to each other in a planar array.3. The device of claim 2 , wherein the drain of each device in the array of devices is held at a common voltage.4. The device of claim 1 , wherein the source and the drain are one of the group consisting of: graphene claim 1 , copper claim 1 , or gold.5. The device of claim 1 , wherein the gate is a self-limited oxidizing metal or semimetal.6. The device of claim 1 , wherein the gate is one of either aluminum or silicon.7. The device of claim 1 , wherein the source and drain have a coating to enhance their work function.8. A device claim 1 , comprising: a drain electrode formed from regions of metal or semimetal on a first dielectric film;', 'a gate formed on a second dielectric film arranged on the first dielectric film;', 'a ...

GATE ALL AROUND VACUUM CHANNEL TRANSISTOR

A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed. 1. A device , comprising:a substrate;a first semiconductor pillar structure oriented in a first direction, the first semiconductor structure having a first tapered end pointing away from the substrate;a second semiconductor pillar structure oriented in the first direction and spaced apart from the first semiconductor pillar structure, the second semiconductor structure having a second tapered end pointing toward the substrate;a gap region between the first semiconductor pillar structure and the second semiconductor pillar structure; anda gate structure adjacent to the gap region in a second direction transverse to the first direction.2. The device of claim 1 , wherein the first and second tapered ends face one another and are separated by the gap region.3. The device of claim 1 , wherein the gate structure surrounds the gap region.4. The device of claim 3 , wherein the gate structure surrounds at least a portion of each of the first semiconductor pillar structure and the second semiconductor pillar structure.5. The device of claim 1 , wherein the first semiconductor pillar structure has a first dimension in the second direction claim 1 , the second semiconductor pillar structure ...

Two-Dimensional Graphene Cold Cathode, Anode, and Grid

In an embodiment, a method includes forming a first diamond layer on a substrate and inducing a layer of graphene from the first diamond layer by heating the substrate and the first diamond layer. The method includes forming a second diamond layer on top of the layer of graphene and applying a mask to the second diamond layer. The mask includes a shape of a cathode, an anode, and one or more grids. The method further includes forming a two-dimensional cold cathode, a two-dimensional anode, and one or more two-dimensional grids by reactive-ion electron-beam etching. Each of the two-dimensional cold cathode, the two-dimensional anode, and the one or more two-dimensional grids includes a portion of the first diamond layer, the graphene layer, and the second diamond layer such that the graphene layer is positioned between the first diamond layer and the second diamond layer. 120-. (canceled)21. An apparatus , comprising:a substrate;a two-dimensional anode positioned on the substrate;a two-dimensional cold cathode positioned on the substrate opposed to the two-dimensional anode; andone or more two-dimensional grids each including a portion positioned on the substrate between the two-dimensional anode and the two-dimensional cold cathode; a first diamond layer;', 'a second diamond layer; and', 'a layer of graphene induced from the first diamond layer, the layer of graphene positioned between the first diamond layer and the second diamond layer., 'wherein each of the two-dimensional anode, the two-dimensional cold cathode, and the one or more two-dimensional grids comprises22. The apparatus of claim 21 , wherein the first diamond layer comprises a hexagonal diamond.23. The apparatus of claim 21 , wherein the layer of graphene is induced from the first diamond layer by heating the substrate and the first diamond layer.24. The apparatus of claim 23 , wherein the heating is performed at a temperature between 400 degrees Celsius and 500 degrees Celsius.25. The apparatus of ...

FOLD OVER EMITTER AND COLLECTOR FIELD EMISSION TRANSISTOR

A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned. 1. A field emission transistor comprising:a gate in electrical communication with a gate contact;gate contact dielectric material surrounding the gate contact;an emitter comprising a first emitter portion adjacent to the gate contact dielectric material and a second emitter portion angled from the first emitter portion toward the gate, and;an collector comprising a first collector portion adjacent to the gate contact dielectric material and a second collector portion angled from the first collector portion toward the gate.2. The field emission transistor of claim 1 , wherein the first emitter portion and the first collector portion are substantially parallel to the gate.3. The field emission transistor of claim 1 , wherein the second emitter portion and the second collector portion are substantially perpendicular to the gate.4. The field emission transistor of claim 1 , wherein the second emitter portion is bent with respect to the first emitter portion and wherein the second collector portion is bent with respect to the first collector portion.5. The field emission ...

METHOD TO FABRICATE PORTABLE ELECTRON SOURCE BASED ON NITROGEN INCORPORATED ULTRANANOCRYSTALLINE DIAMOND (N-UNCD)

A source cold cathode field emission array (FEA) source based on ultra-nanocrystalline diamond (UNCD) field emitters. This system was constructed as an alternative for detection of obscured objects and material. Depending on the geometry of the given situation a flat-panel source can be used in tomography, radiography, or tomosynthesis. Furthermore, the unit can be used as a portable electron or X-ray scanner or an integral part of an existing detection system. UNCD field emitters show great field emission output and can be deposited over large areas as the case with carbon nanotube “forest” (CNT) cathodes. Furthermore, UNCDs have better mechanical and thermal properties as compared to CNT tips which further extend the lifetime of UNCD based FEA. 1. A field emitter array device comprising ,a wafer substrate;an electrical insulator layer disposed on the wafer substrate;a plurality of metal tabs for establishing an electrical circuit;a flat panel emitter layer comprising ultrananocrystalline diamond; anda two dimensional electron extraction grid disposed above the flat panel emitter layer, thereby forming a two dimensional field emitter array device.2. The field emitter array as defined in wherein the wafer substrate comprises silicon.3. The field emitter array as defined in wherein the electrical insulator layer comprises SiN.4. (canceled)5. The field emitter array as defined in wherein the metal tabs comprise tungsten tabs.6. (canceled)7. The field emitter array as defined in further including a collimator claim 1 , an X-ray target claim 1 , a focusing electrode claim 1 , a spacer and a lead shield claim 1 , thereby forming an X-ray system for inspection of a specimen.8. The field emitter array as defined in wherein the electron extraction grid comprises copper.9. The field emitter array as defined in wherein the electron extraction grid includes openings claim 8 , thereby enabling electron extraction therethrough.10. The field emitter array as defined in having a ...

ELECTRODE COATING FOR ELECTRON EMISSION DEVICES WITHIN CAVITIES

Embodiments of a method for forming a field emission diode for an electrostatic discharge device include forming a first electrode, a sacrificial layer, and a second electrode. The sacrificial layer separates the first and second electrodes. The method further includes forming a cavity between the first and second electrode by removing the sacrificial layer. The cavity separates the first and second electrodes. The method further includes depositing an electron emission material on at least one of the first and second electrodes through at least one access hole after formation of the first and second electrodes. The access hole is located remotely from a location of electron emission on the first and second electrode. 1. A method for forming a field emission diode for an electrostatic discharge device , the method comprising:forming a first electrode, a sacrificial layer, and a second electrode, wherein the sacrificial layer separates the first and second electrode;forming a cavity between the first and second electrode by removing the sacrificial layer, wherein the cavity separates the first and second electrodes; anddepositing an electron emission material on a surface of at least one of the first and second electrodes through at least one access hole after formation of the first and second electrodes, wherein the access hole is located remotely from a location of electron emission on the first or second electrodes;plugging the access hole after depositing the electron emission material and forming a vacuum or low gas pressure in the cavity, wherein the cavity is hermetically sealed.2. The method of claim 1 , wherein the electron emission material is deposited with selective electroless deposition on the surface of the first and second electrodes.3. The method of claim 1 , further comprising:selectively depositing the electron emission material on the first and second electrodes through an access hole, and wherein the electron emission material is palladium.4. The ...

ELECTRON EMISSION SOURCE AND METHOD FOR FABRICATING THE SAME

Provided is an electron emission source including a substrate, a fixed structure provided on the substrate, and an electron emission yarn provided between the substrate and the fixed structure. The fixed structure includes a first portion having a first width and a second portion having a second width greater than the first width, and the electron emission yarn extends on a first sidewall of the first portion of the fixed structure from between the fixed structure and the substrate. 1. An electron emission source manufacturing method comprising:preparing a fixed structure;forming an electron emission yarn extending along a first sidewall, a bottom surface, and a second sidewall of the fixed structure on the fixed structure; andfixing the fixed structure on a substrate,wherein the electron emission yarn is fixed between the fixed structure and the substrate.2. The method of claim 1 , wherein the forming of the electron emission yarn comprises:winding the fixed structure with a preliminary electron emission yarn; and{'b': '15', 'cutting the preliminary electron emission yarn on an upper surface of the fixed structure.'}3. The method of claim 2 , wherein the cutting of the preliminary electron emission yarn comprises performing cutting in a first direction parallel to an upper surface of the substrate along a center of the upper surface of the fixed structure.4. The method of claim 2 , wherein the cutting of the preliminary electron emission yarn comprises performing cutting in a first direction parallel to an upper surface of the substrate along a plurality of cutting lines on the upper surface of the fixed structure.5. The method of claim 4 , further comprising removing the cut preliminary electron emission yarn on the upper surface of the fixed structure. This application is a divisional of U.S. application Ser. No. 15/697,272 filed Sep. 6, 2017, which claims priority to Korean Patent Application No. 10-2017-0012283, filed on Jan. 25, 2017, in the Korean ...

ELECTRON EMISSION DEVICE AND METHOD FOR MANUFACTURING THE SAME

A method of producing an electron emitting device includes: step A of providing an aluminum substrate or providing an aluminum layer supported by a substrate; step B of anodizing a surface of the aluminum substrate or a surface of the aluminum layer to form a porous alumina layer having a plurality of pores; step C of applying Ag nanoparticles in the plurality of pores to allow the Ag nanoparticles to be supported in the plurality of pores; step D of, after step C, applying a dielectric layer-forming solution onto substantially the entire surface of the aluminum substrate or the aluminum layer, the dielectric layer-forming solution containing, in an amount of not less than 7 mass % but less than 20 mass %, a polymerization product having siloxane bonds; step E of, after step D, at least reducing a solvent contained in the dielectric layer-forming solution to form the dielectric layer; and step F of forming an electrode on the dielectric layer. 1. A method of producing an electron emitting device , comprising:step A of providing an aluminum substrate or providing an aluminum layer supported by a substrate;step B of anodizing a surface of the aluminum substrate or the aluminum layer to form a porous alumina layer having a plurality of pores;step C of applying Ag nanoparticles in the plurality of pores to allow the Ag nanoparticles to be supported in the plurality of pores;step D of, after step C, applying a dielectric layer-forming solution onto substantially the entire surface of the aluminum substrate or the aluminum layer, the dielectric layer-forming solution containing, in an amount of not less than 7 mass % but less than 20 mass %, a polymerization product having siloxane bonds;step E of, after step D, at least reducing a solvent contained in the dielectric layer-forming solution to form a dielectric layer; andstep F of, after step E, forming an electrode on the dielectric layer.2. The method of producing an electron emitting device of claim 1 , wherein the ...

FOLD OVER EMITTER AND COLLECTOR FIELD EMISSION TRANSISTOR

A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned. 1. An integrated circuit device comprising: a gate within a trench of a dielectric layer, the gate in electrical communication with a gate contact;', 'an emitter comprising a first emitter portion lining a first sidewall of the trench and a second emitter portion angled from the first emitter portion toward the gate; and', 'a collector comprising a first collector portion lining a second sidewall of the trench and a second collector portion angled from the first collector portion toward the gate;', 'wherein the emitter and collector are separated from the gate by a void., 'a field emission transistor comprising2. The integrated circuit device of claim 1 , further comprising:gate dielectric material between and contacting the gate contact and the first emitter portion and between and contacting the gate contact and the first collector portion.3. The integrated circuit device of claim 1 , wherein the first emitter portion and the first collector portion are substantially parallel to the gate.4. The integrated circuit device of claim 1 , wherein the second emitter portion and ...

Two-Dimensional Graphene Cold Cathode, Anode, and Grid

In an embodiment, a method includes forming a first diamond layer on a substrate and inducing a layer of graphene from the first diamond layer by heating the substrate and the first diamond layer. The method includes forming a second diamond layer on top of the layer of graphene and applying a mask to the second diamond layer. The mask includes a shape of a cathode, an anode, and one or more grids. The method further includes forming a two-dimensional cold cathode, a two-dimensional anode, and one or more two-dimensional grids by reactive-ion electron-beam etching. Each of the two-dimensional cold cathode, the two-dimensional anode, and the one or more two-dimensional grids includes a portion of the first diamond layer, the graphene layer, and the second diamond layer such that the graphene layer is positioned between the first diamond layer and the second diamond layer.

VACUUM EXHAUST METHOD

A vacuum exhaust method is for decreasing a pressure in a processing chamber in which a mounting table configured to mount thereon a substrate is provided by using a gas exhaust unit. The vacuum exhaust method includes mounting a non-evaporated getter (NEG) on the mounting table, and adsorbing an active gas in the processing chamber on the NEG mounted on the mounting table. In the adsorbing the active gas, the NEG is maintained at a predetermined temperature. 1. A vacuum exhaust method for decreasing a pressure in a processing chamber , in which a mounting table configured to mount thereon a substrate is provided , by using a gas exhaust unit , the method comprising:mounting a non-evaporated getter (NEG) on the mounting table; andadsorbing an active gas in the processing chamber on the NEG mounted on the mounting table.2. The vacuum exhaust method of claim 1 , wherein in said adsorbing the active gas claim 1 , the NEG is maintained at a predetermined temperature.3. The vacuum exhaust method of further comprising: before said mounting the NEG claim 1 , activating the NEG.4. The vacuum exhaust method of further comprising: before said mounting the NEG claim 2 , activating the NEG.5. The vacuum exhaust method of claim 1 , wherein in said mounting the NEG claim 1 , the NEG to be mounted on the mounting table is stored in an activated state under a vacuum atmosphere.6. The vacuum exhaust method of claim 2 , wherein in said mounting the NEG claim 2 , the NEG to be mounted on the mounting table is stored in an activated state under a vacuum atmosphere.7. The vacuum exhaust method of further comprising: after said adsorbing the active gas claim 1 , unloading the NEG from the processing chamber claim 1 ,wherein said unloading the NEG is performed after a pressure in the processing chamber becomes lower than or equal to a predetermined pressure.8. The vacuum exhaust method of claim 1 , wherein said mounting the NEG is performed when a vacuum level in the processing chamber ...

METHOD OF MAKING FIELD EMITTER

A method of making a field emitter includes following steps. A carbon nanotube layer is provided, and the carbon nanotube layer includes a first surface and a second surface opposite to each other. A carbon nanotube composite layer is formed via electroplating a first metal layer on the first surface and electroplating a second metal layer on the second surface. A first carbon nanotube layer and a second carbon nanotube layer is formed by separating apart the carbon nanotube composite layer, wherein a fracture surface is formed in the carbon nanotube composite layer, a number of first carbon nanotubes in the first carbon nanotube layer are exposed from the fracture surface, and a number of second carbon nanotubes in the second carbon nanotube layer are exposed from the fracture surface. 1. A method of making a field emitter , the method comprising:providing a carbon nanotube layer comprising a first surface and a second surface opposite to the first surface, wherein the carbon nanotube layer comprises a plurality of carbon nanotubes;forming a carbon nanotube composite layer via electroplating a first metal layer on the first surface and electroplating a second metal layer on the second surface; anddividing the carbon nanotube composite layer, wherein the first metal layer is separated into a first portion and a second portion, the carbon nanotube layer is divided into a first carbon nanotube layer comprising a plurality of first carbon nanotubes and a second carbon nanotube layer comprising a plurality of second carbon nanotubes, the second metal layer is separated into a third portion and a fourth portion, the first carbon nanotube layer is sandwiched between the first portion and the third portion, the second carbon nanotube layer is sandwiched between the second portion and the fourth portion, some of the plurality of first carbon nanotubes extend out of the first portion and the second portion, and some of the plurality of second carbon nanotubes extend out of ...

PYROLYZED POROUS CARBON MATERIALS AND ION EMITTERS

Embodiments related to the use and production of porous carbon materials in ion emitters and other applications are described 1. An ion emitter comprising:a porous carbon emitter body; anda source of ions in fluid communication with the porous emitter body.2. The ion emitter of claim 1 , wherein a mean pore radii of the porous carbon emitter body is from 100 nm to 1 μm.3. The ion emitter of claim 2 , wherein a mean pore radii of the porous carbon emitter body is from 200 nm to 800 nm.4. The ion emitter of claim 2 , wherein a standard deviation of the mean pore radii is from 10 nm to 70 nm.5. The ion emitter of claim 1 , wherein the porous emitter body is at least one of a carbon aerogel and a carbon xerogel.6. The ion emitter of claim 1 , wherein the porous carbon emitter body is disposed on a substrate.7. The ion emitter of claim 6 , wherein the porous carbon emitter body is monolithically formed with the substrate.8. The ion emitter of claim 1 , wherein a thermal expansion hysteresis of the carbon porous emitter body is less than or equal to 5%.9. The ion emitter of claim 1 , wherein the source of ions is an ionic liquid.10. An array of ion emitters comprising:a substrate;a plurality of porous carbon emitter bodies disposed on the substrate; anda source of ions in fluid communication with the plurality of porous emitter bodies through the substrate.11. The array of ion emitters of claim 10 , wherein a mean pore radii of the porous carbon emitter body is from 100 nm to 1 μm.12. The array of ion emitters of claim 11 , wherein a mean pore radii of the plurality of porous carbon emitter bodies is from 200 nm to 800 nm.13. The array of ion emitters of claim 11 , wherein a standard deviation of the mean pore radii is from 10 nm to 70 nm.14. The array of ion emitters of claim 10 , wherein the plurality of porous carbon emitter bodies are at least one of a carbon aerogel and a carbon xerogel.15. The array of ion emitters of claim 10 , wherein the plurality of porous ...

Vertical Vacuum Channel Transistor

A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the same time providing a higher density of vertical transistor devices during the manufacturing process. 16-. (canceled)7. A vertical vacuum channel transistor , comprising:a sharp tip structure comprising two tip portions, wherein one tip portion of the two tip portions is an emitter of the vertical vacuum channel transistor and another tip portion of the two tip portions is a collector of the vertical vacuum channel transistor;a vacuum channel between the two tip portions; anda gate of the vertical vacuum channel transistor, wherein a metal contact for each of the emitter, the collector and the gate of the vertical vacuum channel transistor is formed in a respective trench for each of the emitter, the collector and the gate of the vertical vacuum channel transistor that each extend downward in a vertical direction from a common top surface.8. The vertical vacuum channel transistor of claim 7 , wherein the two tip portions are formed from an approximately 10-20 nm thick silicon germanium (SiGe) layer of material.9. The vertical vacuum channel transistor of claim 7 , wherein the one tip portion and the another tip portion are separated by the vacuum channel that is less than 150 nm in length.1020-. (canceled)21. The vertical vacuum channel transistor of claim 8 , wherein the silicon germanium (SiGe) layer is a portion of an inverted T-shaped fin structure.22. The vertical vacuum channel transistor of claim 21 , further comprising:a bottom spacer formed on a horizontal surface of the inverted T-shaped fin structure.23. The vertical vacuum channel transistor of claim 22 , where the ...

VERTICAL VACUUM CHANNEL TRANSISTOR WITH MINIMIZED AIR GAP BETWEEN TIP AND GATE

A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack. 1. A semiconductor structure for controlling an electric field from a gate structure , the semiconductor structure comprising:a fin stack including a plurality of layers disposed between inner surfaces of a first dielectric layer;a conductive material disposed in direct contact with outer surfaces of the first dielectric layer; andan air gap defined within the fin stack with epitaxial growths disposed therein.2. The semiconductor structure of claim 1 , wherein a second dielectric layer directly contacts outer surfaces of the conductive material.3. The semiconductor structure of claim 1 , wherein a portion of the first dielectric layer is formed in direct contact with spacers.4. The semiconductor structure of claim 1 , wherein the epitaxial growths are triangle-shaped epitaxial growths created in a tip-to-tip configuration.5. The semiconductor structure of claim 1 , wherein a nitride-based dielectric is disposed over the conductive material.6. The semiconductor structure of claim 1 , wherein gate claim 1 , emitter claim 1 , and collector contacts are formed.7. The semiconductor structure of claim 1 , wherein the epitaxial growths directly contact the fin stacks.8. The semiconductor structure of claim 1 , wherein the epitaxial growths minimize a space defined by the air gap.9. The ...

PLANAR GATE-INSULATED VACUUM CHANNEL TRANSISTOR

A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions. 1. A method of forming a planar gate-insulated vacuum channel semiconductor structure , the method comprising:depositing a conformal hard mask liner over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region;using shallow trench isolation (STI) to form cavities on either side of the gate stack;filling the cavities with dielectric material using oxide deposition;performing chemical-mechanical planarization (CMP) to a height of the conformal hard mask liner;performing a first etching using reactive-ion etching along a first direction cutting the gate stack from a top direction down to approximately the tip-shaped SiGe source/drain region;performing a second etching using wet etching along a second direction perpendicular to the first direction to create a void in a channel in the tip-shaped SiGe source/drain region under the gate stack; andcreating a vacuum in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.2. The method of claim 1 , wherein the forming a conformal hard ...

Image Intensifier with Thin Layer Transmission Layer Support Structures

A light intensifier includes a semiconductor structure to multiply electrons and block stray particles. A thin gain substrate layer includes an electron multiplier region that is doped to generate a plurality of electrons for each electron that impinges on an input surface of the gain substrate layer and blocking structures that are doped to direct the plurality of electrons towards emission areas of an emission surface of the gain substrate layer. Respective ribs of a first plurality of ribs on the input surface of the gain substrate layer are vertically aligned with respective blocking structures, and respective blocking structures are vertically aligned with respective ribs of a second plurality of ribs at the emission surface. This alignment directs electrons along a path through the gain substrate layer to reduce noise. The support ribs provide mechanical strength to the gain substrate layer, improving robustness of the light intensifier while minimizing noise. 1. An apparatus , comprising: a gain substrate layer doped to generate a plurality of electrons for each received electron that impinges on an input surface of the gain substrate layer;', 'a first plurality of ribs disposed at an input surface of the gain substrate layer;', 'a blocking structure disposed within the gain substrate layer that is doped to repel the plurality of electrons towards an emission area of an emission surface of the gain substrate layer;', 'a shielding region doped to absorb stray particles that impinge on the emission surface of the gain substrate layer, wherein the stray particles include one or more of stray photons and stray ions; and', 'a second plurality of ribs disposed at the emission surface of the gain substrate layer., 'a semiconductor structure that includes2. The apparatus of claim 1 , wherein:each rib of the first plurality of ribs is vertically aligned with respective ribs of the second plurality of ribs.3. The apparatus of claim 1 , wherein:each rib of the first ...

Field emission display cell structure and fabrication process

A lateral-emitter field-emission device includes a thin-film emitter cathode (50) of thickness less than several hundred angstrom and has an edge or tip (110) with small radius of curvature. In the display cell structure, a cathodoluminescent phosphor anode (60), allowing a large portion of the phosphor anode's top surface to emit light in a desired direction. An anode contact layer contacts the phosphor anode (60) from below to form a buried anode contact (90) which does not interfere with light emission. The anode phosphor is precisely spaced apart form the cathode edge or tip and receives electrons emitted by the field emission from the edge or tip of the lateral-emitter cathode, when a small bias voltage is applied. The device may be configured as diode, triode, or tetrode, etc. having one or more control electrodes (140) and/or (170) positioned to allow control of current from the emitter to the phosphor anode by an electrical signal applied to the control electrode.

Fabrication process for a field emission display cell structure

A lateral-emitter field emission device has a thin-film emitter cathode 50 which has thickness of not more than several hundred angstroms and has an edge or tip 110 having a small radius of curvature. To form a novel display cell structure, a cathodoluminescent phosphor anode 60 is positioned below the plane of the thin-film lateral-emitter cathode 50, allowing a large portion of the phosphor anode's top surface to emit light in the desired direction. An anode contact layer contacts the phosphor anode 60 from below to form a buried anode contact 90 which does not interfere with light emission. The anode phosphor is precisely spaced apart from the cathode edge or tip and receives electrons emitted by field emission from the edge or tip of the lateral-emitter cathode, when a small bias voltage is applied. The device may be configured as a diode, triode, or tetrode, etc. having one or more control electrodes 140 and/or 170 positioned to allow control of current from the emitter to the phosphor anode by an electrical signal applied to the control electrode. In a particularly simple embodiment, a single control electrode 140 is positioned in a plane below the emitter edge or tip 110 and automatically aligned to that edge. The display cell structure may be repeated many times in an array, and the display cell structure of the invention lends itself to novel array structures which are also disclosed. A fabrication process is disclosed using subprocess steps S1-S19 similar to those of semiconductor integrated circuit fabrication to produce the novel display cell structures and their arrays. Various embodiments of the fabrication process allow the use of conductive or insulating substrates 20 and allow fabrication of devices having various functions and complexity.

Field emission display cell structure

A lateral-emitter field emission device has a thin-film emitter cathode 50 which has thickness of not more than several hundred angstroms and has an edge or tip 110 having a small radius of curvature. To form a novel display cell structure, a cathodoluminescent phosphor anode 60 is positioned below the plane of the thin-film lateral-emitter cathode 50, allowing a large portion of the phosphor anode's top surface to emit light in the desired direction. An anode contact layer contacts the phosphor anode 60 from below to form a buried anode contact 90 which does not interfere with light emission. The anode phosphor is precisely spaced apart from the cathode edge or tip and receives electrons emitted by field emission from the edge or tip of the lateral-emitter cathode, when a small bias voltage is applied. The device may be configured as a diode, triode, or tetrode, etc. having one or more control electrodes 140 and/or 170 positioned to allow control of current from the emitter to the phosphor anode by an electrical signal applied to the control electrode. In a particularly simple embodiment, a single control electrode 140 is positioned in a plane below the emitter edge or tip 110 and automatically aligned to that edge. The display cell structure may be repeated many times in an array, and the display cell structure of the invention lends itself to novel array structures which are also disclosed.

Field emission display cell structure

A lateral-emitter field emission device has a thin-film emitter cathode 50 which has thickness of not more than several hundred angstroms and has an edge or tip 110 having a small radius of curvature. To form a novel display cell structure, a cathodoluminescent phosphor anode 60 is positioned below the plane of the thin-film lateral-emitter cathode 50, allowing a large portion of the phosphor anode's top surface to emit light in the desired direction. An anode contact layer contacts the phosphor anode 60 from below to form a buried anode contact 90 which does not interfere with light emission. The anode phosphor is precisely spaced apart from the cathode edge or tip and receives electrons emitted by field emission from the edge or tip of the lateral-emitter cathode, when a small bias voltage is applied. The device may be configured as a diode, triode, or tetrode, etc. having one or more control electrodes 140 and/or 170 positioned to allow control of current from the emitter to the phosphor anode by an electrical signal applied to the control electrode. In a particularly simple embodiment, a single control electrode 140 is positioned in a plane below the emitter edge or tip 110 and automatically aligned to that edge. The display cell structure may be repeated many times in an array, and the display cell structure of the invention lends itself to novel array structures which are also disclosed. A fabrication process is disclosed using subprocess steps S1-S19 similar to those of semiconductor integrated circuit fabrication to produce the novel display cell structures and their arrays. Various embodiments of the fabrication process allow the use of conductive or insulating substrates 20 and allow fabrication of devices having various functions and complexity.

Fabrication methods for bidirectional field emission devices and storage structures

Bidirectional field emission devices (FEDs) and associated fabrication methods are described. A basic device includes a first unitary field emission structure and an adjacently positioned, second unitary field emission structure. The first unitary structure has a first cathode portion and a first anode portion, while the second unitary structure has a second cathode portion and a second anode portion. The structures are positioned such that the first cathode portion opposes the second anode portion so that electrons may flow by field emission thereto and the second cathode portion opposes the first anode portion, again so that electrons may flow by field emission thereto. A control mechanism defines whether the device is active, while biasing voltages applied to the first and second unitary structures define the direction of current flow. Multiple applications exist for such a bidirectional FED. For example, an FED DRAM cell is discussed, as are methods for fabricating the various devices.

Porous thin-film-deposition substrate, electron emitting element, methods of producing them, and switching element and display element

A method of producing a porous thin-film-deposition substrate, which has the steps of: placing onto a substrate that has an electrostatic charge on its surface, fine particles with a surface electrostatic charge opposite to the electrostatic charge of the substrate surface, depositing a thin film on the fine-particle-placed substrate, and then removing the fine particles to form fine pores in the thin film; further, a method of producing an electron emitting element, which has the steps of: adding a catalyst metal on a substrate, placing fine particles onto the catalyst-added substrate, depositing a thin film on the fine-particle-placed substrate, then removing the fine particles to form fine pores in the film, and growing needle-shaped conductors on the catalyst metal that is exposed on a bottom face of the fine pore.

Porous thin-film-deposition substrate, electron emitting element, methods of producing them, and switching element and display element

A method of producing a porous thin-film-deposition substrate, which has the steps of: placing onto a substrate that has an electrostatic charge on its surface, fine particles with a surface electrostatic charge opposite to the electrostatic charge of the substrate surface, depositing a thin film on the fine-particle-placed substrate, and then removing the fine particles to form fine pores in the thin film; further, a method of producing an electron emitting element, which has the steps of: adding a catalyst metal on a substrate, placing fine particles onto the catalyst-added substrate, depositing a thin film on the fine-particle-placed substrate, then removing the fine particles to form fine pores in the film, and growing needle-shaped conductors on the catalyst metal that is exposed on a bottom face of the fine pore.

METHOD FOR PRODUCING A COLD CATHODE, A DEVICE FOR FIELD EMISSION AND A FIELD EMISSION DEVICE PRODUCED BY THIS METHOD.

Углеродсодержащий наноматериал с низким порогом полевой эмиссии электронов и способ его получения (варианты)

ÐÎÑÑÈÉÑÊÀß ÔÅÄÅÐÀÖÈß (19) RU (11) 2007 112 860 (13) A (51) ÌÏÊ H01J 9/02 (2006.01) ÔÅÄÅÐÀËÜÍÀß ÑËÓÆÁÀ ÏÎ ÈÍÒÅËËÅÊÒÓÀËÜÍÎÉ ÑÎÁÑÒÂÅÍÍÎÑÒÈ, ÏÀÒÅÍÒÀÌ È ÒÎÂÀÐÍÛÌ ÇÍÀÊÀÌ (12) ÇÀßÂÊÀ ÍÀ ÈÇÎÁÐÅÒÅÍÈÅ (21), (22) Çà âêà: 2007112860/09, 29.03.2007 Àäðåñ äë ïåðåïèñêè: 198332, Ñàíêò-Ïåòåðáóðã, óë. Ìàðøàëà Êàçàêîâà, 28, ê.1, êâ.342, Ñ.Ê. Ãîðäååâó (72) Àâòîð(û): Ãîðäååâ Ñåðãåé Êîíñòàíòèíîâè÷ (RU), Êîð÷àãèíà Ñâåòëàíà Áîðèñîâíà (RU) R U (43) Äàòà ïóáëèêàöèè çà âêè: 20.10.2008 Áþë. ¹ 29 (71) Çà âèòåëü(è): Ãîðäååâ Ñåðãåé Êîíñòàíòèíîâè÷ (RU), Êîð÷àãèíà Ñâåòëàíà Áîðèñîâíà (RU) 2 0 0 7 1 1 2 8 6 0 R U Ñòðàíèöà: 1 RU A (57) Ôîðìóëà èçîáðåòåíè 1. Óãëåðîäñîäåðæàùèé íàíîìàòåðèàë ñ íèçêèì ïîðîãîì ïîëåâîé ýìèññèè ýëåêòðîíîâ, èìåþùèé ðàçìåð ÷àñòèö ìåíåå 50 ìêì, îòëè÷àþùèéñ òåì, ÷òî îí ïðåäñòàâë åò ñîáîé ÷àñòèöû, ñîñòî ùèå èç äðà èç äèýëåêòðè÷åñêîãî èëè ïîëóïðîâîäíèêîâîãî ìàòåðèàëà, è ïîâåðõíîñòíîãî ñëî , ñîñòî ùåãî èç ãðàôèòîïîäîáíîãî óãëåðîäà òîëùèíîé 0,5-50 íì. 2. Óãëåðîäñîäåðæàùèé íàíîìàòåðèàë ïî ï.1, îòëè÷àþùèéñ òåì, ÷òî äèýëåêòðè÷åñêèì èëè ïîëóïðîâîäíèêîâûì ìàòåðèàëîì âë þòñ àëìàç, íèòðèä áîðà, íèòðèä êðåìíè , êàðáèä êðåìíè , êàðáèä áîðà, îêñèä êðåìíè , êðåìíèé. 3. Ñïîñîá ïîëó÷åíè óãëåðîäñîäåðæàùåãî íàíîìàòåðèàëà ñ íèçêèì ïîðîãîì ïîëåâîé ýìèññèè ýëåêòðîíîâ, îòëè÷àþùèéñ òåì, ÷òî ïîðîøêè äèýëåêòðè÷åñêîãî èëè ïîëóïðîâîäíèêîâîãî ìàòåðèàëà òåðìîîáðàáàòûâàþò â ñðåäå óãëåâîäîðîäîâ ïðè òåìïåðàòóðå, ïðåâûøàþùåé òåìïåðàòóðó èõ òåðìè÷åñêîãî ðàçëîæåíè , â òå÷åíèå âðåìåíè, íåîáõîäèìîãî äë îáðàçîâàíè íà ïîâåðõíîñòè ÷àñòèö ïîðîøêà ñëî óãëåðîäà òîëùèíîé 0,5-50 íì. 4. Ñïîñîá ïî ï.3, îòëè÷àþùèéñ òåì, ÷òî â êà÷åñòâå äèýëåêòðè÷åñêîãî èëè ïîëóïðîâîäíèêîâîãî ìàòåðèàëà èñïîëüçóþò ïîðîøêè àëìàçà, íèòðèä áîðà, íèòðèä êðåìíè , êàðáèä êðåìíè , êàðáèä áîðà, îêñèä êðåìíè , êðåìíè ñ ðàçìåðîì ÷àñòèö 0,1-10 ìêì. 5. Ñïîñîá ïîëó÷åíè óãëåðîäñîäåðæàùåãî íàíîìàòåðèàëà ñ íèçêèì ïîðîãîì ïîëåâîé ýìèññèè ýëåêòðîíîâ, îòëè÷àþùèéñ òåì, ÷òî ïîðîøêè àëìàçà òåðìîîáðàáàòûâàþò â èíåðòíîé ñðåäå èëè âàêóóìå ïðè òåìïåðàòóðå, ïðåâûøàþùåé ...

Gas discharge panel

A method for manufacturing gated carbon-nanotube field emission displays

본 발명은 직격이 수㎛ 크기 이하인 미세한 홀이 형성된 하부 기판상에 직접 성장된 탄소나노튜브를 전계방출원으로 이용하고, 전자의 흐름을 제어할 수 있는 삼극형 전계방출 표시소자의 제조방법에 관한 것으로, 투명전극, 발광층이 형성된 상부기판과 대응되도록 형성된 하부기판을 포함한 전계방출 표시소자의 제조방법에 있어서, 하부 기판상에 게이트 절연막, 게이트 전극을 차례로 형성하고 상기 게이트 절연막이 소정부분 노출되도록 상기 게이트 전극을 선택적으로 식각하는 단계와, 상기 기판 표면이 소정부분 노출되도록 게이트 절연막을 습식식각과 건식식하여 홀을 형성하는 단계와, 상기 게이트 전극상에 전자선 증착기를 사용하여 소정의 경사를 갖도록 도전층을 형성하는 단계와, 상기 도전층상 및 상기 홀의 기판상에 초박막의 촉매금속를 증착한 후, 화학기상증착법을 사용하여 선택적으로 홀 중앙에 탄소나노튜브를 형성하는 단계와, 리프트-오프 공정을 통해 상기 도전층을 제거하여 기판상에 직접성장된 탄소나노튜브를 갖는 삼극형 전계방출 표시소자를 형성하는 것을 특징으로 한다. The present invention relates to a method of manufacturing a tripolar field emission display device that can control the flow of electrons by using carbon nanotubes grown directly on a lower substrate having a fine hole of several micrometers in size or less as a field emission source. The method of manufacturing a field emission display device including a transparent electrode and a lower substrate formed to correspond to an upper substrate on which a light emitting layer is formed, the method comprising: forming a gate insulating film and a gate electrode on a lower substrate in order and exposing a predetermined portion of the gate insulating film. Selectively etching the gate electrode, forming a hole by wet etching the gate insulating layer with a dry etching so as to expose a predetermined portion of the surface of the substrate, and conducting a predetermined inclination using an electron beam evaporator on the gate electrode. Forming a layer, and the ultra-thin catalyst gold on the conductive layer and the substrate of the hole After depositing the inner layer, using a chemical vapor deposition method to selectively form a carbon nanotube in the center of the hole, and the lift-off process to remove the conductive layer by a tripolar type having a carbon nanotube directly grown on the substrate A field emission display device is formed.

Light transmissive metal electrode and manufacturing method thereof

The present invention provides a light-transmitting metal electrode including a substrate and a metal electrode layer having plural openings. The metal electrode layer also has such a continuous metal part that any pair of point-positions in the part is continuously connected without breaks. The openings in the metal electrode layer are periodically arranged to form plural microdomains. The plural microdomains are so placed that the in-plane arranging directions thereof are oriented independently of each other. The thickness of the metal electrode layer is in the range of 10 to 200 nm.

Manufacture of camera tube target

Field Effect Device using Carbonnanotube and Method for the same

본 발명은 탄소나노튜브를 이용한 전계방출소자 및 그 제조방법을 제공하기 위한 것으로서, 구조체를 이용하여 균일한 미세공(hole)을 가공한 후, 화학결합에 의해 상기 미세공 안에 수직으로 정렬되고 길이가 일정한 탄소나노튜브를 이용하여, 탄소나노튜브 배열공정시 온도의 제약을 적게 받으며 대면적을 갖는 전계방출소자에 적용이 가능하다. The present invention is to provide a field emission device using a carbon nanotube and a method for manufacturing the same, and after processing a uniform hole (pore) using a structure, and vertically aligned in the fine hole by a chemical bond and the length By using a constant carbon nanotubes, it is possible to apply to the field emission device having a large area and less temperature constraints in the carbon nanotube arraying process.

Production of color filter

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Method for a field emitter array of a field emission display

PURPOSE: A method for forming field emitter array of field emission display is provided to make lower voltage operation of device possible and to improve durability of emitter tip by forming silicide around silicon tip and simultaneously depositing metal film up to around tip by sputtering. CONSTITUTION: A disk oxidation film of a designated size is formed on the top of silicon substrate(1). Rough tip shape is formed by making an isotropic etching lower silicon substrate(1) as much as a designated depth considering above disk oxidation film as mask. Gate insulation film(7) of a designated thickness is formed on front surface of above structure except lower part of above disk oxidation film by incline deposition method using electron beam depositor. Gate metal is deposited on the top of whole structure. Tip is protruded by lift off process. Silicide is formed at the end part of above tip.

Method for preparing field-emission electron source

一种场发射电子源的制备方法，包括以下步骤：提供一碳纳米管薄膜，该碳纳米管薄膜中的碳纳米管沿同一方向延伸排列；提供一第一电极和一第二电极，将碳纳米管薄膜的两端分别固定于第一电极和第二电极上，该碳纳米管薄膜中碳纳米管从第一电极向第二电极延伸；通过使用有机溶剂处理该碳纳米管薄膜，形成多个碳纳米管线；将该碳纳米管线通电流加热熔断，得到多个碳纳米管针尖；提供一导电基体，将一碳纳米管针尖设置于该导电基体上，形成一场发射电子源。

A kind of graphene-based field emission cold-cathode and preparation method

本发明属于真空电子技术和新型碳材料技术的交叉领域，具体涉及一种石墨烯基场发射冷阴极及制备方法。场发射冷阴极由基片和发射体组成，基片作为导电基底为硅片或者金属片，发射体为石墨烯薄膜层。石墨烯薄膜层与基底紧密接触，厚度为20μm~180μm，由团簇粒径为15μm~45μm的石墨烯团簇构成。本发明的石墨烯基冷阴极可用上述方法制备，呈阵列式形貌，具有开起电场低、阈值电场低、发射电流大等良好的性能优势，可作为一种优异的电子源应用于场发射显示（FED）等领域。

Patent JPS5325632B2

Manufacture of faceplate for image pickup tube

Manufacturing method of field emission device having silicide as emitter and gate

본 발명은 실리사이드를 에미터와 게이터로 갖는 전계 방출 소자의 제조 방법에 관한 것으로, 실리콘 기판 (11)을 일정 깊이로 에칭하는 단계와, 실리콘 기판 (11)상에 산화막 (12)을 형성한 후에 CVD에 의해 폴리실리콘 (13)을 증착하는 단계와, 폴리실리콘 (13)상에 얇게 포토레지스트 (14)를 증착하고 포토레지스트 (14)와 폴리실리콘 (13)을 에칭하는 단계와, 포토레지스트 (14)를 제거한 후에 산화막 (12)을 습식 에칭 하는 단계와, 금속을 증착한 후에 열처리하여 실리사이드흘 형성하여 게이트 (17) 와 에미터 (16)를 형성하는 단계를 구비한다. 그로 인해, 내구성이 우수하고 저전압에서도 전계 방출이 가능한 전계 방출 소자를 얻을 수 있다.

Field emission cathode and method of manufacturing the same

Spaced-gate emission device and method for making same

전계 방출 장치는, 절연 기판 상에 방출물 재료를 배치하고, 방출물 재료에 대해 희생막(sacrificial film)을 도포하며, 상기 희생층 위에, 내부에 개구가 랜덤하게 분포되어 있는 도전 게이트층을 형성하는 것에 의해 제조된다. 바람직한 실시예에 있어서, 게이트는 희생층에 마스킹 입자를 도포하고, 마스킹 입자와 희생막 위에 도전성막을 도포하며, 그 후 마스킹 입자를 제거하여 랜덤하게 분포된 개구를 노출시키는 것에 의해 형성된다. 그 후, 희생막이 제거된다. 그 다음에, 개구가 방출물 재료까지 연장한다. 바람직한 실시예에 있어서, 희생막은, 게이트로부터 에미터를 분리시키기 위해 막이 제거된 후에 남아 있는 절연 스페이서를 포함한다. 그 결과, 저렴한 비용의 평 패널 디스플레이를 제조하는데 사용할 수 있는 랜덤하게 분포된 다수의 방출 개구를 갖는 신규하고도 경제적인 전계 방출 장치가 얻어진다. The field emission device arranges an emission material on an insulated substrate, applies a sacrificial film to the emission material, and forms a conductive gate layer having randomly distributed openings therein on the sacrificial layer. It is manufactured by doing. In a preferred embodiment, the gate is formed by applying masking particles to the sacrificial layer, applying a conductive film over the masking particles and the sacrificial film, and then removing the masking particles to expose a randomly distributed opening. Thereafter, the sacrificial film is removed. The opening then extends to the emitter material. In a preferred embodiment, the sacrificial film includes an insulating spacer that remains after the film is removed to separate the emitter from the gate. The result is a novel and economical field emission device having a plurality of randomly distributed emission apertures that can be used to produce low cost flat panel displays.

Patent JPS6349394B2

Method for manufacturing a field emission device having a silicide as an emitter and a gate

본 발명은 실리사이드를 에미터와 게이터로 갖는 전계 방출 소자의 제조 방법에 관한 것으로, 실리콘 기판(11)을 일정 깊이로 에칭하는 단계와, 실리콘 기판(11)상에 산화막(12)을 형성한 후에 CVD에 의해 폴리실리콘(13)을 증착하는 단계와, 폴리실리콘(13)상에 얇게 포토레지스트(14)를 증착하고 포토레지스트(14)를 제거한 후에 산화막(12)을 습식 에칭하는 단계와, 금속을 증착한 후에 열처리하여 실리사이드를 형성하여 게이트(17)와 에미터(16)를 형성하는 단계를 구비한다. 그로 인해, 내구성이 우수하고 저전압에서도 전계 방출이 가능한 전계 방출 소자를 얻을 수 있다.

Panel for displaying dc gas discharge

Asymmetric deflection systems for cathode ray tubes

Electrode Forming Method for Flat Plate Devices

본 발명은 평판소자의 전극을 형성하는 신규한 방법을 개시한다. The present invention discloses a novel method of forming an electrode of a plate element. 종래의 인쇄방법은 완성된 전극의 물성이 낮고 고해상도가 불가능하며, 박막방법은 원가가 과도하며 별도의 패터닝이 필요하며, 전착법도 별도의 도전전극이 필요하며 생산성이 낮은 문제가 있었다. The conventional printing method has low physical properties of the finished electrode and high resolution is impossible, and the thin film method requires excessive costing and requires separate patterning, and the electrodeposition method requires a separate conductive electrode and has low productivity. 본 발명에서는 전극의 소요패턴에 따른 창을 가지는 투과패턴을 열분해성 수지에 의해 기판상에 형성한 뒤, 은경반응에 의해 Ag를 부착시키고 투과패턴을 제거하여 전극을 형성하도록함으로써, 고순도의 Ag에 의한 고물성의 금속전극을 낮은 제조원가와 높은 생산성으로 구현할 수 있게 하였다. In the present invention, after forming a transmission pattern having a window according to the required pattern of the electrode on the substrate by a thermally decomposable resin, by attaching Ag by a silver mirror reaction, and removing the transmission pattern to form an electrode, to a high-purity Ag The high physical properties of the metal electrode can be realized with low manufacturing cost and high productivity.

Manufacturing method of triode carbon nanotube field emission array

본 발명은 저전압 전계방출 물질인 탄소 나노튜브를 이용한 전계방출 어레이의 제조방법에 관한 것으로, 후면 노광법에 의한 삼극관 탄소나노튜브 전계방출 어레이의 제조 방법을 제공하여 별도의 마스크층을 사용하지 않고 공정상에 제조되는 박막층 자체를 마스크층으로 사용함으로써 적은 수의 마스크층을 사용하여 삼극관구조의 탄소나노튜브 전계방출 어레이를 용이하게 제조할 수 있다. The present invention relates to a method of manufacturing a field emission array using carbon nanotubes, which are low voltage field emission materials, and to providing a method of manufacturing a tripolar carbon nanotube field emission array by a back exposure method, without using a separate mask layer. By using the thin film layer itself prepared on the mask layer as a mask layer, a carbon nanotube field emission array having a triode structure can be easily manufactured using a small number of mask layers.

Producing method for field emission type electron source

本发明涉及一种场发射电子源的制备方法，包括以下步骤：提供一碳纳米管长线；加热该碳纳米管长线；提供一电子发射源，使用该电子发射源轰击该碳纳米管长线，使该碳纳米管长线在被轰击处熔断；将熔断后的碳纳米管长线设置于导电基体上即得到场发射电子源。

Electrostatic deflecting cathode-ray tube

Field emission device

본 발명은 전계 방출 에미터로 탄소 나노 튜브를 사용하는 코플래너 구조의 전계 방출 소자에서 동일층에 대칭적으로 형성된 두 전극 상부에 탄소 나노 튜브를 대칭적으로 형성하여 소자의 수명을 증대시키기에 적합한 전계 방출 소자에 관한 것으로, 하부 기판 상의 동일 평면에 대칭적으로 형성되며 구동 전압을 인가하기 위한 두 전극과, 상기 두 전극 상에 대칭적으로 형성된 탄소 나노 튜브를 포함하여 구성하고, 상기 두 전극 중 하나의 전극 상에 형성된 탄소 나노 튜브를 전자 방출원으로 사용하다 열화된 경우 다른 전극 상에 형성된 탄소 나노 튜브를 전자 방출원으로 사용하도록 함으로써, 소자의 수명을 증대시킬 수 있는 효과가 있다. The present invention is suitable for increasing the lifetime of the device by symmetrically forming carbon nanotubes on two electrodes symmetrically formed on the same layer in a coplanar field emission device using carbon nanotubes as field emission emitters. A field emission device, comprising: two electrodes symmetrically formed on the same plane on a lower substrate and for applying a driving voltage, and carbon nanotubes symmetrically formed on the two electrodes, wherein When the carbon nanotubes formed on one electrode are used as the electron emission source and deteriorated, the carbon nanotubes formed on the other electrode can be used as the electron emission source, thereby increasing the life of the device.

Production of color filter

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。