СПОСОБ ПОЛУЧЕНИЯ СОЕДИНЕНИЙ АЛКОКСИДА ИНДИЯ, СОЕДИНЕНИЯ АЛКОКСИДА ИНДИЯ, ПОЛУЧАЕМЫЕ СОГЛАСНО СПОСОБУ, И ИХ ПРИМЕНЕНИЕ

Изобретение относится к соединению алкоксида индия, которое получено путем реакции тригалогенида индия InX, где X=F, Cl, Br, I, со вторичным амином формулы R'NH, где R'=СС-алкил, в молярном соотношении от 8:1 до 20:1 по отношению к тригалогениду индия, в присутствии спирта общей формулы ROH, где R=СС-алкил. Также предложены способ получения алкоксида индия и его применение. Соединение алкоксида индия применяют для получения содержащих оксид индия покрытий, имеющих отличные электрические свойства. 5 н. и 7 з.п. ф-лы, 1 ил., 2 пр.

ОБНОВЛЕНИЕ ИЗДЕЛИЙ ИЗ ТУГОПЛАВКИХ МЕТАЛЛОВ

... 1. Обновленная танталовая мишень для распыления, включающая использованную танталовую мишень для распыления, содержащую танталовую пластину для распыления и пластину-подложку, в которой использовавшаяся для распыления поверхность указанной танталовой пластины для распыления содержит один или большее количество израсходованных участков поверхности, и массу связанных частиц металла на каждом указанном одном или большем количестве израсходованных участков поверхности, где указанная масса связанных частиц металла частично или полностью заполняет каждый указанный один или большее количество израсходованных участков поверхности, причем указанная использованная танталовая мишень для распыления обновляется без отделения указанной пластины-подложки от указанной танталовой пластины для распыления. 2. Обновленная танталовая мишень для распыления по п.1, в которой указанная масса связанных частиц металла обладает микроструктурой, в основном сходной с микроструктурой указанной танталовой пластины для ...

Способ изготовления контактно-барьерной металлизации

Способ изготовления контактно-барьерной металлизации, включающий предварительное удаление естественного окисла с поверхности кремниевых подложек путем обработки в водном растворе фтористоводородной кислоты, нанесение на поверхность подложек диэлектрического слоя и формирование в нем контактных окон, размещение кремниевых подложек в реакторе, вакуумирование реактора, продувку реактора водородом и селективное осаждение вольфрама при 270-350°C из парогазовой смеси гексафторида вольфрама и водорода при соотношении компонентов 1:(10-100) и общем давлении 13,3-66,5 Па, отличающийся тем, что, с целью повышения эффективности контактно-барьерной металлизации на основе слоев вольфрама путем повышения селективности процесса осаждения, продувку реактора водородом проводят при 450-750°C и давлении 13,3-133,3 Па в течение 30-90 мин.

СПОСОБ СОЗДАНИЯ ОМИЧЕСКИХ КОНТАКТОВ К КРЕМНИЮ

Способ создания омических контактов к кремнию р-типа проводимости, включающий нанесение молибдена на кремниевую подложку катодным распылением, отличающийся тем, что, с целью повышения надежности омического контакта, катодное распыление молибдена проводят путем создания в рабочей камере вакуума (1,3-6,7)10-4 Па, введения фторосодержащего газа, BF3, до создания вакуума (2,7-3,2)10-2 Па, зажигания плазмы и последующей подачи высокого напряжения на мишень 2000-3000 В.

ЭЛЕКТРОДНАЯ СТРУКТУРА ТЫЛЬНОГО ЭЛЕКТРОДА ПОЛУПРОВОДНИКОВОЙ ПОДЛОЖКИ, СПОСОБ ЕЕ ПОЛУЧЕНИЯ И РАСПЫЛЯЕМАЯ МИШЕНЬ ДЛЯ ПРИМЕНЕНИЯ В ПОЛУЧЕНИИ ЭЛЕКТРОДНОЙ СТРУКТУРЫ

Изобретение относится к электродной структуре тыльного электрода, способу получения электродной структуры тыльного электрода и распыляемой мишени для формирования слоя Ag-го сплава для применения в способе получения электродной структуры тыльного электрода. Электродная структура тыльного электрода, сформированного на тыльной поверхности полупроводниковой подложки и имеющего многослойную структуру, включает металлические слои, наслоенные в следующем порядке: слой Ti, слой Ni и слой Ag-го сплава, где слой Ag-го сплава включает сплав Ag и дополнительного металла M, выбранного из Sn, Sb и Pd, электродная структура тыльного электрода выполнена так, что, когда тыльный электрод подвергается элементному анализу с помощью рентгеновского фотоэлектронного спектрометра в направлении глубины от слоя Ag-го сплава к слою Ni, на границе между слоем Ni и слоем Ag-го сплава наблюдается промежуточная область, где могут быть обнаружены спектры, полученные от всех металлов, т.е. Ni, Ag и дополнительного элемента ...

СПОСОБ ИЗГОТОВЛЕНИЯ КОНТАКТНО-БАРЬЕРНОЙ МЕТАЛЛИЗАЦИИ

Способ изготовления контактно-барьерной металлизации, включающий процессы напыления и отжига в азотной среде, отличающийся тем, что контактно-барьерную металлизацию формируют путем последовательного нанесения пленок W (15% Ti) толщиной 0,17-0,19 мкм магнетронным распылением сплавной мишени, со скоростью 2,5 Å/с и пленку Al (1,5% Si) толщиной 0,35-0,45 мкм, с последующим термическим отжигом при температуре 450-480°C в течение 30 мин.

СПОСОБ ПОЛУЧЕНИЯ ПОКРЫТИЙ

... 1. Способ получения покрытий, включающий испарение материала, формирование направленного к подложке потока осаждаемого материала и осаждение его на подложке, отличающийся тем, что, с целью повышения адгезии, на осажденное покрытие воздействуют импульсным магнитным полем непосредственно или через промежуточную среду, обладающую высокой электропроводностью. 2. Способ по п.1, отличающийся тем, что на осажденное покрытие воздействуют импульсным магнитным полем амплитудой 20-28 кЭ и длительностью 120-130 мкс.

CПOCOБ ИЗГOTOBЛEHИЯ ПOЛУПPOBOДHИKOBЫX ПPИБOPOB

Methode zur Bildung von Metallsilizidschichten auf Source- und Draingebiete

Mfg. self-aligned gallium arsenide MESFET - involves forming T=shaped tungsten gate electrode

Mfr. of a self-aligned MESFET with a T-shaped tungsten gate electrode involves (a) applying a thin Si layer over the entire surface of a semi-insulating GaAs substrate by plasma-enhanced CVD, applying a Si3N4 layer by photo-CVD and ion implanting to produce an n-active layer using a photo-mask; (b) forming a gate electrode pattern by etching the Si3N4 layer using. the photo-mask; (c) selectively depositing tungsten by CVD only on the exposed Si layer and not on the Si3N4 layer; (d) thickening the tungsten in the transverse direction to form a T-shape; (e) forming an n+-layer by ion implantation using the T-shaped tungsten gate such that the gap between the gate electrode and the n+-layer is 1000-2000 Angstroms; (f) activating the n- and n+-layers using the Si layer and the Si3N4 layer as cover film; (g) ion implanting through the Si and Si3N4 layers to provide insulation between the devices; and (h) etching the Si and Si3N4 layers and applying an ohmic metallisation (AuGe/Ni) by a lift-off ...

Verfahren zur Herstellung einer ohmschen Elektrode

Improving resistance of metal-silicide layers to heat treatment - when deposited on previously sputter-cleaned surface in layer with adequate thickness

Thin layers of silicides of refractory metals, used in Si processes, are formed by siliciding of metal layers deposited in a sputtering process immediately after sputter cleaning in an inert gas the surface of the substrate. The metal deposition pref. Ti, is made in the same equipment with a layer thickness of at least 50 nm, pref. 60 nm, to allow heat treatments at temps. of at least 900 deg. C. The silicide formation is then carried out, using rapid thermal annealing in N2, in 2 steps at a temp. in the range 600-850 deg. C sepd. by a wet etching step to remove the unreacted metal or metal-nitride. Following high temp. processes are then carried out at a min. temp. of 900 deg. C., e.g. to flow an intermediate oxide layer. The siliciding process is carried out pref. in N2 over a time of 20 secs. at 650 deg. C for the first step and for 10 secs. at 850 deg. C for the second step. The intermediate oxide is formed by a deposition of SiO2, pref. 150 nm thick from thermal decomposition of tetratethylortho-silicate ...

Transistor mit permeabler Basis

Verbindungsverfahren einer Verdrahtung mit einem Halbleitergebiet und durch dieses Verfahren hergestellte Halbleitervorrichtung

Halbleitervorrichtung aus einer galliumnitridartigen III-V-Halbleiterverbindung und Verfahren zu ihrer Herstellung

Verfahren zur Herstellung eines Films für eine Halbleiteranordnung bei niedriger Temperatur

METHOD OF PRODUCING OHMIC AND/OR SCHOTTKY BARRIER CONTACTS ON SEMICONDUCTOR SUBSTRATES

Verfahren zum Herstellen einer Kontaktzone

Peripherieabdichtung für Halbleiterplättchen durch Gasinjektion.

Verfahren zur Herstellung einer Bipolartransistorstruktur für Höchstgeschwindigkeitsschaltung.

Verfahren zur Herstellung eines eingebetteten dynamischen Direktzugriffsspeichers

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG MIT EINEM ELEKTRISCHEN KONTAKT

Verfahren zur Metallisierung von Submikron Kontaktlöchern in Halbleiterkörpern

HALBLEITERBAUELEMENT MIT NIEDRIGEM KONTAKTWIDERSTAND ZU HOCHDOTIERTEN GEBIETEN

VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS MIT EINER STÜCKWEISE IM SUBSTRAT VERLAUFENDEN VERDRAHTUNG

Verfahren zur Hemmung von Ausdiffusion von Dotierstoffen.

MAGNETRON-KATHODENZERSTAEUBUNGSVORRICHTUNG, VERSEHEN MIT SEPARATEN MAGNETISCHEN EINSCHLUSSFELDERN ZUR TARGETTRENNUNG UND MIT EINER DURCH RADIOFREQUENZ VERSTAERKTEN POLARISIERUNG.

Verfahren zum Herstellen von Kontakten aus flache Übergänge enthaltenden integrierten Schaltungen.

Verfahren zur Herstellung von ohmschen Kontakten für Verbindungshalbleiter

Verfahren zur Dampfabscheidung eines Kupferfilms.

Ein herstellungsverfahren eines bipolaren Transistors.

Herstellungsverfahren für Halbleiteranordnungen

Verfahren zur Herstellung von aus monomolekularen Schichten aufgebauten Filmen unter Anwendung von Silanen, die Acetylen- bindungen enthalten

Verfahren zur Herstellung eines verbesserten Metallsilizidbereichs in einem Silizium enthaltenden leitenden Gebiet in einer integrierten Schaltung

In einem Aspekt der vorliegenden Erfindung wird ein Schichtstapel mit zumindest drei Materialschichten auf einem Silizium enthaltenden leitenden Gebiet vorgesehen, um einen Silizidbereich auf und in dem Silizium enthaltenden leitenden Gebiet zu bilden, wobei die Schicht benachbart zu dem Silizium die Metallatome für die chemische Reaktion liefert, und wobei die folgenden Schichten eine ausreichende Intertheit der chemischen Reaktion liefern. Das Verfahren kann als ein In-Situ-Verfahren ausgeführt werden, wobei der Durchsatz und die Leistungsfähigkeit der Abscheideanlage im Vergleich zu typischen und konventionellen Prozessen, in denen zumindest zwei Abscheidekammern verwendet werden müssen, verbessert ist.

Method of manufacturing back contact of e.g. solar cell, involves thermally spraying materials containing metal or alloy on back layer of wafer to form lower and upper layers, where materials have different melting temperatures

The method involves thermally spraying aluminum on back layer of crystalline silicon wafer (16) to form an aluminum layer (18) such that aluminum is applied over the entire surface of back layer. Materials containing metal or alloy are thermally sprayed on the back layer to form lower and upper layers (12,14), where the materials have different melting temperatures. The back layer is plated with tin. An independent claim is included for semiconductor device.

Verfahren zur Bildung eines Kontaktloches für eine Metall-Leitung in einem Halbleiter-Bauelement

Verfahren zur Bildung eines Kontaktlochs (28), um eine Metall-Leitung mit einem Kontaktbereich auf einem Halbleitersubstrat (21) durch das Kontaktloch (28) zu verbinde mit folgenden Schritte, Bilden einer Silizium-Gateoxidschicht (22), einer Polysiliziumschicht (23) und einer oberen Silizium-Gateoxidschicht (24) auf einer Oberfläche des Halbleitersubstrats (21) in der genannten Reihenfolge; Ätzen der Silizium-Gateoxidschicht (22), der Polysiliziumschicht (23) und der oberen silizium-Gateoxidschicht (24), um ein erstes Kontaktloch zu bilden; Bilden des Kontaktbereichs auf dem Halbleitersubstrat (21); Bilden einer Siliziumoxid-Seitenwandbeabstandung (26) auf einer Seitenwandoberfläche des ersten Kontaktlochs; Abscheiden einer Metallgrenzschicht (29) auf der oberen Silizium-Gateoxidschicht (24), auf der Seitenwandbeabstandung (26) und in dem ersten Kontaktloch; Bilden eines Metallgrenzschicht-Schutzes (210') auf der Metallgrenzschicht (29), wobei der Metallgrenzschicht-Schutz (210') das erste ...

VAKUUMKAMMER MIT HOHEM DURCHFLUSS UND MODULAREN AUSSTATTUNGSELEMENTEN WIE PLASMAERZEUGUNGSQUELLE, VAKUUMPUMPE UND/ODER FREITRAGENDEM WERKSTÜCKTRÄGER

MULTIFUNKTIONALER VERFAHRENSRAUM FÜR CVD-VERFAHREN

VERFAHREN UND VORRICHTUNG ZUM ABSCHEIDEN EINES IN FLÜSSIGER FORM VORLIEGENDEN PREKURSORS AUF EINEM SUBSTRAT

VERFAHREN ZUR HERSTELLUNG EINES HALBLEITER-BAUELEMENTS

Bei einem Struktur-Herstellungsverfahren wird eine Stapelstruktur hergestellt, die eine untere Schicht, eine mittlere Schicht und eine erste Maskenschicht aufweist. Die mittlere Schicht weist eine erste Deckschicht, eine Zwischenschicht und eine zweite Deckschicht auf. Die erste Maskenschicht wird unter Verwendung einer ersten Resiststruktur als eine Ätzmaske strukturiert. Die zweite Deckschicht wird unter Verwendung der strukturierten ersten Maskenschicht als eine Ätzmaske strukturiert. Über der strukturierten zweiten Deckschicht wird eine zweite Maskenschicht hergestellt, die unter Verwendung einer zweiten Resiststruktur als eine Ätzmaske strukturiert wird. Die zweite Deckschicht wird unter Verwendung der strukturierten zweiten Maskenschicht als eine Ätzmaske strukturiert. Die Zwischenschicht und die erste Deckschicht werden unter Verwendung der strukturierten zweiten Deckschicht als eine Ätzmaske strukturiert. Die untere Schicht wird unter Verwendung der strukturierten ersten Deckschicht ...

METHOD FOR FORMING SCHOTTKY-BARRIER DIODES

HALBLEITERANORDNUNG

INTEGRIERTE HALBLEITERSCHALTUNG MIT EINER AUS ALUMINIUM ODER AUS EINER ALUMINIUMLEGIERUNG BESTEHENDEN AEUSSEREN KONTAKTLEITERBAHNEBENE

VERFAHREN ZUR HERSTELLUNG VON SOWIE STRUKTUREN FUER VLSI-SCHALTUNGEN MIT HOHER DICHTE

Semiconductor device especially FET production

A semiconductor device production process involves (a) forming an insulating layer (50) on a semiconductor substrate (42); (b) forming a cover layer (52) with an opening (54) on the insulating layer; (c) removing the insulating layer at the bottom of the opening; and (d) melting to provide the cover layer (52) with a curved surface. Preferably, the cover layer (52) is an electron beam cover layer which reacts to electron beams. Also claimed is an FET production process involving forming an ohmic electrode on a semiconductor substrate, covering the entire structure surface with a cover layer having an opening through which the substrate is etched to form a recess, removing the cover layer, carrying out the above steps (a) to (d) and then forming a gate electrode connected to the substrate surface with the etched recess. Further claimed are a semiconductor device and an FET produced by the above processes.

Einstellen der Schwellenspannung durch metastabile Plasmabehandlung

Ein Verfahren umfasst ein Ausbilden einer ersten High-k-Dielektrikumsschicht über einem ersten Halbleiterbereich, Ausbilden einer zweiten High-k-Dielektrikumsschicht über einem zweiten Halbleiterbereich, Ausbilden einer ersten Metallschicht, die einen ersten Abschnitt über der ersten High-k-Dielektrikumsschicht und einen zweiten Abschnitt über der zweiten High-k-Dielektrikumsschicht umfasst, Ausbilden einer Ätzmaske über dem zweiten Abschnitt der ersten Metallschicht und Ätzen des ersten Abschnitts der ersten Metallschicht. Die Ätzmaske schützt den zweiten Abschnitt der ersten Metallschicht. Die Ätzmaske wird mit metastabilem Plasma verascht. Eine zweite Metallschicht wird dann über der ersten High-k-Dielektrikumsschicht ausgebildet.

Verfahren zum Herstellen von MOS-Transistoren mit flachen Source/Drain-Gebieten, kurzen Kanallängen und einer selbstjustierten, aus einem Metallsilizid bestehenden Kontaktierungsebene.

Verfahren zur Herstellung eines Kontaktierungsbereichs auf einem strukturierten Halbleiterkörper

AN OHMIC CONTACT FOR AN INTERMETALLIC COMPOUND SEMICONDUCTOR AND A METHOD OF PROVIDING SUCH A CONTACT

VERFAHREN ZUR MINIMIERUNG MECHANISCHER SPANNUNGEN IN ABGESCHIEDENEN WOLFRAMSILIZIDSCHICHTEN

Verfahren zur Substratbearbeitung

KOHLENSTOFF-NANORÖHREN-WACHSTUMSVERFAHREN

Halbleiterherstellungsverfahren

Verfahren zum Anschlussfüllen für Anschlüsse mit hohem Aspektverhältnis, bei welchem eine Keimbildungsschicht an einem Boden eines Kontaktlochs und nicht auf den Seitenwänden gebildet wird. Die Anschlussfüllung wird in Richtung von unten zur Oberkante des Kontaktlochs gebildet und nicht von den Seitenwänden her nach innen. Der resultierende Anschluss ist hohlraumfrei und übergangslos.

Gestapeltes photovoltaisches Bauelement und Herstellungsverfahren

Verfahren zum lokalen Erhitzen eines in einem Halbleitersubstrat angeordneten vergrabenen Bereichs

Verfahren zum lokalen Erhitzen eines in einem Halbleitersubstrat angeordneten vergrabenen Bereichs, umfassend die Schritte: - Bereitstellen eines Halbleitersubstrats; - Erzeugen zumindest eines in dem Halbleitersubstrat angeordneten vergrabenen Bereichs, der einen geringeren spezifischen Widerstand aufweist als das umgebende Halbleitersubstrat; - lokales Erhitzen des vergrabenen Bereichs durch Induktion von Wirbelströmen mittels eingestrahlter elektromagnetischer Energie.

Wafer pedestal cover

Method of forming a copper wiring in a semiconductor device

FORMATION OF LAYER OF MULTICONSTITUENT

Sputtering apparatus

Electrode arrangement for semiconductor devices

Disclosed herein is a semiconductor device applicable to a bipolar semiconductor integrated circuit device in which a base electrode (9) is directly extracted from an active base region (61) through a superposed layer of a polysilicon film (601) and a metal silicide film (501) while an emitter electrode (10) is partially formed by a polysilicon film (602) and a contact hole is defined to form a base metal silicide film with the polysilicon film being employed as a mask. Consequently, the distance between an emitter layer (71) and a base electrode hole (50) is reduced without necessity of including margins of emitter and base electrode wires extending over respective holes in the said distance.

PROCESS FOR PRODUCING CMOS STRUCTURES WITH BIPOLAR TRANSISTORS

Field effect transistor

The field effect transistor having an asymmetric gate 2 comprises a source region 4, a drain region 5 and a side wall 9a. The side wall acts as a mask during ion implantation to form the source and drain regions so that the drain region is separated from the gate 2. The transistor has a reduced short channel effect, reduced source resistance, improved transconductance and improved drain breakdown voltage. ...

Ferroelectric capacitors

A composite electrode for a ferroelectric capacitor comprising laminated metal and conductive metal oxide layers is formed by DC magnetron sputtering. Iridium is deposited at a first power level and iridium oxide is deposited at a second higher power level whilst maintaining the substrate temperature and oxygen / argon gas mixture ratio constant.

Method of forming boron doped silicon layers in semiconductor devices using higher order silanes

A method of forming a semiconductor device includes depositing a boron doped amorphous silicon layer on a substrate having many steps, projections or cavities, by thermal decomposition of a higher order silane gas eg Si2H6orSi3H8 and diborane gas at 150 DEG -450 DEG C. The diborane gas may be supplied to the substrate in a reaction limited. At least one of O2, N2O, NH3, N2 or NF3 may be added to the reactants. The thermal decomposition may be carried out at 0.01-0.2 Torr. An insulator layer may first be formed on substrate which is etched to form a contact hole prior to deposition of the doped silicon. Alternatively after first forming a conductor element the doped silicon layer may be etched, an insulating layer applied, a contact hole formed in the insulating film to expose the first conductor element, the contact hole refilled and a second conductor element formed thereon. A dynamic RAM may be produced by forming a trench on a substrate, forming a MOSFET having source/drain region and ...

Bicmos process for counter doped collecter

In a BICMOS circuit the bipolar transistor base region is formed in an n-type well serving as the collector of the transistor. Boron ions are implanted at two different energy levels to form the base region (26) and to counter dope the well to form a region (34) below the base region which is more lightly doped than the remainder of the well. The ion implantation counter doping the well may comprise two energy levels. Such counter doping reduces the electric field at the collector base junction and reduces collector base capacitance. ...

Method of manufacturing a semiconductor device

PROBLEM TO BE SOLVED: To increase the mobility and conductivity of electrons, and to improve the electrical characteristics of elements by reducing a contact resistance by completely removing a natural oxide film before depositing an amorphous silicon, and maximizing the size of a grain by silicon ion implantation and re- crystallization. SOLUTION: An insulating layer 3 is formed on a silicon substrate 1 in which a junction 2 is formed, the patterning of the insulating layer 3 is carried out, and a contact hole 4 is formed so that the silicon substrate 1 at the upper part of the junction 2 can be exposed. At this time, wet cleaning is executed by using a BOE or HF solution, a plasma processing using CF4 is executed, and the loading of the silicon substrate 1 is operated in a reactor for removing a natural oxide film 10 which is formed on the exposed silicon substrate 1. Afterwards, an amorphous silicon 6 is deposited by low pressure chemical deposition, using thermal decomposition of SiH4 ...

Semiconductor device and method for fabricating a diffusion barrier metal layertherein

Stacked showerhead assembly for delivering gases and rf power to a reaction chamber

Forming copper wiring using as precursor (hfac)Cu(VTMOS)

A method of forming a copper wiring in a semiconductor device comprises the steps of supplying a wafer to a reaction chamber evaporating 1,1,1,5,5,5-hexafluoro-2,4-pentadionato(vinyltrimethoxysilane)-copper(I) (hfac)Cu(VTMOS). Compound precursor in a liquid delivery system, flowing said evaporate precursor into the reaction chamber, and depositing by decomposing, the copper on the wafer by metal organic chemical vapour deposition (MOCVD). A diffusion barrier may be formed initially on the substrate of one or more of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN or CVD WN.

Method and apparatus for treating a semiconductor wafer

Electrode material for compound semiconductor

Semiconductor device having aluminum interconnection

ELECTRODE BOAT APPARATUS

SEMICONDUCTOR MANUFACTURING METHOD

EVAPORATOR FOR VACUUM DEPOSITION OF FILMS

FABRICATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUITS

Bicmos process utilizing novel planarization technique

A method for forming a BICMOS integrated circuit having MOS field effect transistors and bipolar junction transistors is disclosed. The process comprises first defining separate active areas, forming a gate dielectric layer and a first layer of polysilicon. This polysilicon is then selectively etched to form a plurality of equally-spaced first polysilicon members comprising the gates (33, 34) of the MOS transistors and the extrinsic base contacts (35) of the NPN transistors. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members (65, 66, 67, 68, 69). Impurities are diffused from the polysilicon members to form source/drain regions (73, 74, 75, 76) of the MOS transistors and the extrinsic base (81) and emitter (77) regions of the NPN transistors. The final processing steps include providing ...

Field effect transistor having a recessed gate

The device comprises a substrate (11), a source electrode (22) and a drain electrode (23), a recessed channel region formed over an area of the semiconductor substrate between the source electrode and the drain electrode, and a gate electrode (29) which may be inclined toward the source or drain electrodes and formed over the recessed channel portion. A method of forming an asymmetric recessed channel using reactive ion etching is also divided. ...

Semiconductor devices

Plasma assisted sputter deposition.

A plasma-assisted sputter deposition system 1 comprising a reactor into which a process gas is introduced to be used for producing plasma and an annular electrode 2 made of a material for sputtering by said plasma. The lower surface of said annular electrode is arranged at an angle or parallel to the surface of a wafer 9 to be deposited with said material. Two or more circular magnets with different diameters 19a, 19b are arranged above the electrode. The magnets are arranged to have alternate polarities facing the electrode so as to generate one or more close loop magnetic flux lines 37 below the electrode. The electrode is connected to an electrical power source 10 and a wafer holder 5 for holding said wafer in a stationary position for film deposition is provided.

FIELD EFFECT TRANSISTORS

Method and apparatus for metallizing high aspect ratio silicon semiconductor device contacts

A CVD apparatus (10) is equipped with a cleaning gas source (23, 24), selectively connectable to a gas inlet (16) of the chamber (25) of the apparatus (10), structure, to supply a gas mixture of hydrogen and argon in which the hydrogen con-tent is between 20 percent and 80 percent by volume. A selectively operable 450 MHz RF energy source (71, 71a) is coupled to the chamber (25) to energize a plasma in gas. A selectively operable 13.56 MHz RF energy source (72), controllable independently of the MF energy source (71, 71a) and connected between the wafer support (40) and a chamber anode (26) may be provided to bias a wafer (75) on the support to less than 100 volts, preferably 15 to 35 volts, negative. A heater (42) heats the wafer (75) to temperature about 550 ‹C. Preferably, a turbo molecular pump (32) is used to pump the cleaning gas while maintaining a pressure of between 1 mTorr and 10 Torr and at a rate of from 3 to 12 sccm.

Diffusion barrier layer for a semiconductor device and a fabrication method thereof

A diffusion barrier layer for a semiconductor device

Method of forming an interconnection in a contact hole in an insulation layer over a silicon substrate

Method of making a capacitor for an integrated circuit

Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Control of abnormal growth in dichloro silane based CVD polycide WSi films

In a process for mitigating and/or eliminating the abnormal growth of underlying polysilicon in dichloro silane-based CVD polycide WSix films, a first technique conducts the deposition of the underlying polysilicon layer at a temperature that substantially avoids crystallization of the underlying polysilicon. A second approach reduces the exposure (for example time period and or concentration) of the mono-silane SiH4 post flush, so as to avoid infusion of silicon into the underlying polysilicon layer, and resulting abnormal growth. In this manner, abnormal effects, such as stress fractures formed in subsequent layers, can be eliminated. The polysilicon layer is flushed with a first flush material (SiH4) to provide a transition layer and then with a second flush material (dichlorosilane (DCS)) to provide a second material layer over the polysilicon layer, which provides adherence characteristics, providing a combination of the first flush material and the second flush material ...

HEAT TRANSFER APPARATUS

Depositing a tantalum film

Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect

ELECTRODE AND SEMICONDUCTOR DEVICE PROVIDED WITH THE ELECTRODE

MANUFACTURE OF INTEGRATED CIRCUITS

Method for metallizing a semiconductor element

A method of forming a metal electrode on a semiconductor device includes the steps of mechanically abrading the surface of the device as by grit dusting, plasma etching the surface and applying the metal electrode. Where surface adjacent regions of differing dislocation densities are present, the mechanical abrading followed by plasma etching produces a surface to which a metal layer may be applied with relatively uniform adherence characteristics.

Interconnect Structure for Semiconductor Devices

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Atomic layer deposition of a copper-containing seed layer

The present disclosure relates to the field of microelectronic device fabrication and, more particularly, to the formation of copper-containing seed layers for the fabrication of interconnects in integrated circuits. The copper-containing seed layers may be formed in an atomic layer deposition process with a copper pre-cursor and organometallic co-reagent.

Method of manufacturing a semiconductor device

Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi) 2 Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.

Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device

Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

Semiconductor device and method of forming the same

A device may includes a first conductive film, a first insulating film, a second conductive film, a third conductive film, and a fourth conductive film. The first conductive film includes copper. The first insulating film is disposed over the first conductive film. The first insulating film has a first contact hole. The contact hole reaches a first surface of the first conductive film. The second conductive film includes aluminum. The second conductive film is disposed in the first contact hole. The third conductive film includes titanium nitride. The third conductive film is disposed in the contact hole. The third conductive film covers a part of the first surface of the first conductive film. The fourth conductive film is free of titanium nitride. The fourth conductive film is disposed between the second and third conductive films.

Semiconductor Device Comprising Contact Elements with Silicided Sidewall Regions

When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.

Method of manufacturing semiconductor device

The method of manufacturing the semiconductor device comprises the steps of forming a MOS transistor 26 including a gate electrode 16 and source/drain diffused layers 24 formed in the silicon substrate 10 on both sides of the gate electrode 16 , forming a NiPt film 28 over the silicon substrate 10 , covering the gate electrode 16 and the source/drain diffused layers 26 , making thermal processing to react the NiPt film 28 with the upper parts of the source/drain diffused layers 24 to form Ni(Pt)Si films 34 a, 34 b on the source/drain diffused layers 24 , and removing selectively the unreacted part of the NiPt film 28 using a chemical liquid of above 71° C. including 71° C. containing hydrogen peroxide and forming an oxide film on the surface of the Ni(Pt)Si films 34 a, 34 b.

Method for reducing contact resistance of cmos image sensor

This description relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at the pixel contact hole area and performing contact filling. This description also relates to a method for reducing CMOS Image Sensor (CIS) contact resistance, the CIS having a pixel array and a periphery. The method includes implanting N+ or P+ for pixel contact plugs at a pixel contact hole area, performing Physical Vapor Deposition (PVD) at pixel contact hole area, annealing for silicide formation at the pixel contact hole area, performing contact filling and depositing a first metal film layer, wherein the first metal film layer links contact holes for a source, a drain, or a poly gate of a CMOS device.

Use of epitaxial ni silicide

An epitaxial Ni silicide film that is substantially non-agglomerated at high temperatures, and a method for forming the epitaxial Ni silicide film, is provided. The Ni silicide film of the present disclosure is especially useful in the formation of ETSOI (extremely thin silicon-on-insulator) Schottky junction source/drain FETs. The resulting epitaxial Ni silicide film exhibits improved thermal stability and does not agglomerate at high temperatures.

Method to form uniform silicide by selective implantation

Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

Semiconductor Contact Barrier

System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.

LOW RESISTANCE STACKED ANNULAR CONTACT

An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components. 1. An integrated circuit , comprising:a semiconductor substrate;a plurality of lower components disposed in and on said substrate, said lower components including transistors;a pre-metal dielectric (PMD) layer disposed over said lower components and said substrate; conventional lower contacts; and', 'annular lower contacts, such that each said annular lower contact is configured in at least one closed-loop annular ring of said lower liner and said lower contact metal, said annular ring surrounding a corresponding pillar of dielectric material of said PMD layer, such that said PMD material pillar has substantially equal length and width, being 1 to 4 times a width of said conventional lower contacts, and a width of said annular ring is 0.75 to 2.5 times said width of said conventional lower contacts;, 'lower contacts disposed in said PMD layer, making electrical connections to said lower components and extending to a top surface of said PMD layer, said lower contacts having a metal lower liner on lateral and lower surfaces of said lower contacts and a lower contact metal disposed ...

Interconnect Structure for Semiconductor Devices

A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium. 1. A method of manufacturing a semiconductor device , the method comprising:forming a dielectric layer on a substrate;embedding a conductive material into the dielectric layer, the conductive material comprising a first material and having a recess; andsiliciding the conductive material to form an alloy layer at least partially within the recess, the alloy layer comprising the first material and a second material, the second material comprising germanium, arsenic, tungsten, or gallium.2. The method of claim 1 , wherein the siliciding the conductive material further comprises forming a seed layer of silicon on the conductive material.3. The method of claim 1 , wherein the siliciding the conductive material further comprises:introducing a first precursor material to the conductive material, the first precursor material being a silicon containing precursor material; andintroducing a second precursor material to the conductive material, the second precursor material containing the second material.4. The method of claim 3 , wherein the introducing the first precursor material and the introducing the second precursor material are begun simultaneously.5. The method of claim 3 , wherein the introducing the first precursor material is begun after the introducing the second precursor material.6. The method of claim 1 , wherein the conductive material comprises copper.7. The method of claim 1 , further comprising forming a barrier layer between the conductive material and the ...

Through-Package-Via (TPV) Structures On Inorganic Interposer And Methods For Fabricating Same

The present invention generally relates to the use of glass as the interposer material with the surface of the interposer and/or the walls of through vias in being coated by a stress relief barrier that provides thermal expansion and contraction stress relief and better metallization capabilities. The present invention discloses ways in that a stress relief barrier can be used to reduce the effects of stress caused by the different CTEs while also, in some applications, acting as an adhesion promoter between the metallization and the interposer. The stress relief barrier acts to absorb some of the stress caused by the different CTEs and promotes better adhesion for the conductive metal layer, thus helping to increase reliability while also providing for smaller designs. 1. A microelectronic package comprising:a plurality of through vias having walls in a glass interposer having a top portion;a stress relief barrier on at least a portion of the top portion of the glass interposer;a metallization seed layer on at least a portion of the stress relief layer; anda conductor on at least a portion of the metallization seed layer and through at least a portion of the plurality of the through vias forming a plurality of metalized through package vias, wherein at least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.2. The microelectronic package of claim 1 , wherein the stress relief barrier comprises a polymer film.3. The microelectronic package of claim 2 , wherein the polymer film comprises a thin dry film build up dielectric.4. The microelectronic package of claim 2 , wherein the polymer film is deposited as a dry film claim 2 , liquid coating claim 2 , or vapor phase deposition thin film.5. The microelectronic package of claim 1 , wherein the stress relief barrier has a coefficient of thermal expansion between the glass interposer and the conductor.6. The microelectronic package of claim 1 , wherein the stress relief ...

PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS USING CHLORINE GAS

The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Provided is a method of manufacturing a TSV structure, which prevents a substrate from warping even if it is made thin. A method of manufacturing a semiconductor device comprises integrating semiconductor elements on a surface of a semiconductor substrate to form at least a part of a circuit, forming holes from the surface of the semiconductor substrate, forming an insulating film and a barrier film on an inner surface of each hole, forming a conductive metal on a surface of the barrier film to fill each hole, processing a back surface of the semiconductor substrate to reduce the thickness thereof to thereby protrude the conductive metal, and providing a SiCN film on the back surface of the semiconductor substrate. 1. A method of manufacturing a semiconductor device , comprising:(a) integrating semiconductor elements on a surface of a semiconductor substrate to form at least a part of a circuit;(b) forming a hole from the surface of the semiconductor substrate;(c) forming an insulating film and a barrier film on an inner surface of the hole;(d) forming a conductive metal on an inner surface of the barrier film to fill the hole;(e) processing a back surface of the semiconductor substrate to reduce a thickness of the semiconductor substrate to thereby protrude the conductive metal, the barrier film, and the insulating film from the back surface; and(f) providing a SiCN film on the back surface of the semiconductor substrate.2. The method of manufacturing a semiconductor device according to claim 1 , wherein the (f) comprises controlling a composition of the SiCN film so that warping of the semiconductor substrate becomes substantially zero.3. The method of manufacturing a semiconductor device according to claim 1 , wherein the (f) comprises forming the SiCN film having a composition in which 2 at % to 40 at % C is added to SiN.4. The method of manufacturing a semiconductor device claim 1 , wherein the (e) comprises reducing the thickness of the semiconductor substrate ...

HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS

An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate. 1. A process for forming an integrated circuit , comprising:providing a substrate having transistors, a first pre-metal dielectric, and a contact photoresist pattern for a contact wall seal surrounding a FeCap area;forming at least one contact wall seal that is at least partially filled with a first hydrogen barrier material wherein said first hydrogen barrier material covers the walls of said at least one contact wall seal;forming at least one metal wall seal that is at least partially filled with a second hydrogen barrier material wherein said second hydrogen barrier material covers the walls of said at least one metal wall seal;forming at least one via wall seal that is at least partially filled with a third hydrogen barrier material wherein said third hydrogen barrier material covers the walls of said at least one via wall seal;forming a top plate seal over said FeCap array, said top plate seal being over and in contact with one of said at least one via wall seal.2. The process of wherein said first hydrogen barrier is at least one of TiN claim 1 , TiAlN claim 1 , and TiAlON claim 1 , and wherein said contact wall seal is filled with CVD-W.3. The process of wherein said third hydrogen barrier material is at least one of TaN claim 1 , TaON claim 1 , and TiN and wherein said at least one via wall seal is filled with Cu.4. The process of wherein said forming said top plate seal further comprises:forming a photoresist pattern on top of a dielectric layer, said dielectric layer containing a trench for a via wall seal;etching said dielectric layer to form a trench for an interconnect signal lead and a trench for said top plate seal;forming a TaN barrier layer on a bottom ...

Integrated circuits including copper local interconnects and methods for the manufacture thereof

Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having source/drain regions, and a plurality of transistors including a plurality of gate conductors formed over the semiconductor substrate and between the source/drain regions. Device-level contacts are formed in ohmic contact with the gate conductors and with the source/drain regions. The device-level contacts terminate at substantially the same level above the semiconductor substrate. Copper interconnect lines are then formed in a level above the device-level contacts and in ohmic contact therewith to locally interconnect the plurality of transistors.

Structure of electrical contact and fabrication method thereof

A method of fabricating an electrical contact comprises the following steps. A substrate having at least a silicon region is provided. At least an insulation layer is formed on the substrate, wherein the insulation layer comprises at least a contact hole which exposes the silicon region. A metal layer is formed on sidewalls and bottom of the contact hole. An annealing process is performed to form a first metal silicide layer in the silicon region nearby the bottom of the contact hole. A conductive layer covering the metal layer and filling up the contact hole is then formed, wherein the first metal silicide layer is transformed into a second metal silicide layer when the conductive layer is formed.

METHOD FOR FORMING A VIA CONTACTING SEVERAL LEVELS OF SEMICONDUCTOR LAYERS

A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material. 1. A method for forming a via connecting a first upper level layer to a second lower level layer , both layers being surrounded with an insulating material , the method comprising the steps of:a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge;b) forming a layer of a protection material on said edge only;c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; andd) filling the opening with at least one conductive contact material.2. The method of claim 1 , wherein the protection material is a conductive material.3. The method of claim 2 , wherein claim 2 , at step b) claim 2 , the layer of the conductive protection material is formed by electroless deposition.4. The method of claim 1 , wherein the first and second layers are silicon layers covered with a metal silicide.5. The method of claim 4 , wherein the metal silicide is based on a metal selected from the group comprising platinum and nickel.6. The method of claim 1 , wherein:the thickness of the insulating material separating the first layer from the gates of transistors formed on the second layer ranges between 10 and 500 nm;the thickness of the first layer ranges between 5 and 150 nm; andat step b), a layer of the protection material having a thickness ranging between 10 and 50 nm is formed.7. The method of claim 2 , wherein the conductive protection material ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a first conductor formed over a semiconductor device; an insulation film formed over the semiconductor substrate and the first conductor and having an opening arriving at the first conductor; a first film formed in the opening and formed of a compound containing Zr; a second film formed over the first film in the opening and formed of an oxide containing Mn; and a second conductor buried in the opening and containing Cu. 111.-. (canceled)12. A semiconductor device manufacturing method comprising:forming a first conductor over a semiconductor substrate;forming an insulation film over the semiconductor substrate and over the first conductor;forming in the insulation film an opening arrived to the first conductor;forming in the opening a first film formed of a compound containing Zr;forming a second film containing Cu and Mn over the first film in the opening;forming a second conductor containing Cu in the opening; andoxidizing Mn in the second film to change the second film into a third film formed of an oxide containing Mn by thermal processing.13. The semiconductor device manufacturing method according to claim 12 , wherein{'sub': '2', 'the first film is a ZrBfilm, ZrBN film or ZrN film.'}14. A semiconductor device manufacturing method according to claim 12 , whereinin the forming the opening, the opening is formed, including a contact hole arriving at the first conductor and a trench connected to a top of the contact hole.15. A semiconductor device according to claim 14 , whereinin the forming the second film, the second film is formed by forming the second film in the contact hole and the trench while selectively removing the first film on a bottom of the contact hole.16. A semiconductor device manufacturing method according to claim 14 , further comprising claim 14 , after the forming the first film and before the forming the second film claim 14 ,selectively removing the first film on a bottom of the contact hole.17. A ...

Devices Including Metal-Silicon Contacts Using Indium Arsenide Films and Apparatus and Methods

Described are apparatus and methods for forming films comprise indium and arsenic. In particular, these films may be formed in a configuration of two or more chambers under “load lock” conditions. These films may include additional components as dopants, such as aluminum and/or gallium. Such films can be used in metal/silicon contacts having low contact resistances. Also disclosed are devices including the films comprising indium arsenide. 1. A substrate processing apparatus comprising:a first processing chamber to clean a substrate to provide a cleaned substrate;a second processing chamber in communication with the first processing chamber to deposit a layer comprising indium arsenide on the cleaned substrate;a third processing chamber in communication with the second processing chamber to deposit a metal layer on the layer comprising indium arsenide; anda control system in communication with the first, second and third processing chambers,wherein the first, second and third processing chambers are in communication under load lock conditions.2. The apparatus of claim 1 , wherein the first processing chamber performs atomic hydrogen cleaning or cleaning with a fluorine-containing precursor.3. The apparatus of claim 1 , wherein the second processing chamber is an atomic layer deposition (ALD) chamber claim 1 , physical vapor deposition (PVD) chamber claim 1 , chemical vapor deposition (CVD) chamber or molecular beam epitaxy (MBE) chamber.4. The apparatus of claim 3 , wherein the second processing chamber is an ALD chamber.5. The apparatus of claim 3 , wherein the PVD chamber is a sputtering chamber.6. The apparatus of claim 1 , wherein the indium arsenide layer further comprises one or more of gallium claim 1 , aluminum claim 1 , antimony and phosphorus.7. The apparatus of claim 1 , wherein the third processing chamber is an ALD chamber.8. The apparatus of claim 1 , wherein the control system controls the second processing chamber to deposit a layer comprising indium ...

PROCESS OF FORMING THROUGH-SILICON VIA STRUCTURE

In a process, an opening is formed to extend from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A metal silicide layer is formed on at least one portion of the metal seed layer. A metal layer is formed on the metal silicide layer and the metal seed layer to fill the opening. 1. A process , comprising:forming an opening extending from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate;forming a metal seed layer on a sidewall of the opening;forming a metal silicide layer on at least one portion of the metal seed layer; andforming a metal layer on the metal silicide layer and the metal seed layer to fill the opening.2. The process of claim 1 , wherein the metal silicide layer comprises copper.3. The process of claim 1 , wherein the metal layer comprises copper claim 1 , and the metal seed layer comprises copper.4. The process of claim 1 , further comprising:forming a barrier layer lining the opening before forming the metal seed layer, wherein barrier layer comprises at least one selected from the group consisting of TaN, Ta, TiN, and Ti.5. The process of claim 4 , further comprising:forming a passivation layer lining the opening before forming the barrier layer.6. The process of claim 5 , wherein the passivation layer comprises silicon oxide.7. The process of claim 1 , further comprising:performing a thinning process on a back surface of the semiconductor substrate to expose an end of the metal layer.8. The process of claim 7 , further comprising:stacking a semiconductor component on the back surface of the semiconductor substrate, the semiconductor component electrically connected to the exposed end of the metal layer.9. A process claim 7 , comprising:forming an opening extending from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate;forming a metal seed ...

Nisi rework procedure to remove platinum residuals

The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C.

REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT

Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel. 1. A method of forming a semiconductor structure comprising:forming an interfacial dielectric layer at a bottom surface of a cavity laterally enclosed by a dielectric gate spacer and over a semiconductor substrate;forming a gate dielectric layer having a dielectric constant greater than 3.9 on said interfacial dielectric layer and on inner sidewalls of said dielectric gate spacer;forming a metal-containing layer on said gate dielectric layer;annealing said metal-containing layer, wherein a metallic element within said metal-containing layer diffuses through said gate dielectric layer and at least to an interface between said interfacial dielectric layer and said gate dielectric layer; andremoving said metal-containing layer selective to said gate dielectric layer.2. The method of claim 1 , wherein said metallic element is selected from Group IIA elements claim 1 , Group IIIB elements claim 1 , Al claim 1 , Ge claim 1 , and Ti.3. The method of claim 1 , further comprising:forming a sacrificial metal-containing cap layer on said metal-containing ...

Cost-Effective Gate Replacement Process

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME

One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer. 1. A method of forming a semiconductor structure , comprising:providing a workpiece;forming a barrier layer over said workpiece;forming a seed layer over said barrier layer;forming an inhibitor layer over said seed layer;removing a portion of said inhibitor layer to expose a portion of said seed layer; andselectively depositing a fill layer on said exposed seed layer.2. The method of claim 1 , wherein said selective deposition includes a process selected from the group consisting of electroplating claim 1 , electroless plating claim 1 , and chemical vapor deposition.3. The method of claim 1 , wherein substantially none of said fill layer selectively deposits on said inhibitor layer.4. The method of claim 3 , wherein said fill layer spills over said inhibitor layer.5. The method of claim 1 , wherein said removing said portion of said inhibitor layer comprises laser ablation.6. The method of claim 1 , wherein said fill layer and/or said seed layer comprises copper metal and/or a copper alloy.7. The method of claim 1 , wherein said barrier layer and/or said inhibitor layer comprises Ta (tantalum).8. The method of claim 1 , wherein said workpiece includes an opening claim 1 , said barrier layer formed within said opening.9. A method of forming an electronic device claim 1 , comprising:providing a workpiece;forming a barrier layer over said workpiece;forming a seed layer over said barrier layer;forming an inhibitor layer over said seed layer;removing a portion of said inhibitor layer to expose a portion of said seed layer; andforming a fill layer on said exposed seed layer, ...

Semiconductor structure and fabricating method thereof

A semiconductor device comprises a substrate, a metal-semiconductor compound layer and at least one kind of metal dopant. The substrate has a surface. The metal-semiconductor compound layer extends downwards into the substrate from the surface. The metal dopant which is made by one of a group of metal elements with atomic numbers ranging from 57 to 78 or the arbitrary combinations thereof and doped in the metal-semiconductor compound layer and the substrate with at least one peak concentration formed adjacent to the interface of the metal-semiconductor compound layer and the substrate.

Method of Making Metal/Semiconductor Compound Thin Film

The present disclosure provides a method of making metal/semiconductor compound thin films, in which a target material is partially ionized into an ionic state during metal deposition using a PVD process, so as to produce metal ions, and in which a substrate bias voltage is applied to a semiconductor substrate, causing the metal ions to accelerate into the semiconductor substrate and enter the semiconductor substrate, resulting in more metal ions diffusing to the surface of the semiconductor substrate, greater deposition depth, and increased thickness of the eventually formed metal/semiconductor compound thin film. An amount of metal ions entering the semiconductor substrate can be adjusted by adjusting the substrate bias voltage, so as to adjust the thickness of the eventually formed metal/semiconductor compound. 1. A method of making a metal/semiconductor compound thin film , characterized in that the method comprises:providing a semiconductor substrate;depositing a metal layer on the semiconductor substrate using a PVD process, the metal layer including metal diffusing into the semiconductor substrate, wherein a target material in the PVD process for depositing the metal layer is ionized into an ionic state, causing it to produce metal ions, and wherein a substrate bias is applied to the semiconductor substrate;removing a remaining part of the metal layer from a surface of the semiconductor substrate, andperforming annealing for the semiconductor substrate to form metal/semiconductor compound thin film on the surface of the semiconductor substrate.2. The method of making the metal/semiconductor compound thin film according to claim 1 , further characterized in that the metal/semiconductor compound thin film has a thickness of 3-11 nm.3. The method of making the metal/semiconductor compound thin film according to claim 2 , further characterized in that the target material is partially ionized into an ionic state by applying a first bias voltage to the target ...

Metal semiconductor alloy contact with low resistance

A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Nano-MOS Devices and Method of Making

The present invention discloses a method of making nano-MOS devices having a metal gate, thereby avoiding the poly depletion effect, and enhancing the MOS device's performance. The method forms metal gates by depositing a metal film over sidewall surfaces on two sides of a polycrystalline semiconductor layer. The metal in the metal film diffuses toward the sidewall surfaces of the polycrystalline semiconductor layer and forms, after annealing, metal-semiconductor compound nanowires (i.e., metal gates) on the sidewall surfaces of the polycrystalline semiconductor layer. Thus, high-resolution lithography is not required to form metal compound semiconductor nanowires, resulting in significant cost saving. At the same time, a nano-MOS device is also disclosed, which includes a metal gate, thereby avoiding the poly depletion effect, and resulting in enhanced MOS device performance. 119-. (canceled)20. A method of making a nano-MOS device , the method comprising:providing a semiconductor substrate;forming a gate oxide layer on the semiconductor substrate;forming a patterned semiconductor layer on the gate oxide layer;forming metal-semiconductor compound nanowires on sidewalls of the patterned semiconductor layer;removing the patterned semiconductor layer; andforming source/drain regions for the nano-MOS device whereby one or more of the metal-semiconductor-compound nanowires constitute a gate for the nano-MOS device.21. The method of making the nano-MOS device according to claim 20 , wherein the patterned semiconductor layer includes polysilicon claim 20 , wherein the semiconductor substrate is silicon or silicon-on-insulator claim 20 , and the metal-semiconductor-compound nanowires are metal silicide nanowires.22. The method of making the nano-MOS device according to claim 20 , wherein the patterned semiconductor layer includes polycrystalline germanium claim 20 , wherein the semiconductor substrate is germanium or germanium-on-insulator claim 20 , and the metal- ...

Asymmetric Gate MOS Device and Method of Making

An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented. 1. An asymmetric gate MOS device , characterized in that , the asymmetric gate MOS device has a metal gate , and the metal gate has different work functions on the source side and on the drain side of the MOS device.2. An asymmetric gate MOS device according to claim 1 , characterized in that claim 1 , the metal gate includes a metal-semiconductor-compound nanowire.3. An asymmetric gate MOS device according to claim 2 , characterized in that claim 2 , the MOS device comprises:a semiconductor substrate;a gate oxide layer formed over the semiconductor substrate;a gate formed over the gate oxide layer, wherein the gate has sidewalls formed on its two sides; andsource/drain regions formed in the semiconductor substrate on the two sides of the gate.4. An asymmetric gate MOS device according to claim 3 , characterized in that claim 3 , a length of the metal gate is about 2-11 nm.5. An asymmetric gate MOS device according to claim 4 , characterized in that claim 4 , the semiconductor substrate includes silicon or silicon on insulator claim 4 , and the metal-semiconductor-compound nanowire is a metal silicide nanowire.6. An asymmetric gate MOS device according to claim 4 , characterized in that claim 4 , the semiconductor substrate includes germanium or germanium on insulator claim 4 , and the metal-semiconductor-compound nanowire ...

METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES

An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face. 140-. (canceled)41. A method of fabricating an integrated circuit structure on a support structure , the method comprising:forming a plurality of linearly extending material stack lines each comprising a polysilicon material, a metal silicide material, and an oxide top material;cutting the material stack lines at an angle relative a linearly extending direction to form respective angled end faces at each of the material stack lines, the respective angled end faces being spaced in the linearly extending direction; andforming an electrical contact landing pad as an extension of each of the material stack lines at each respective angled end face.42. The method of claim 41 , wherein the material stack lines are parallel material stack lines.43. The method of claim 42 , further comprising covering the parallel material lines with an encapsulation insulating material prior to cutting the parallel material lines.44. The method of claim 43 , further comprising removing a portion of the encapsulation insulating material from a portion of the material stack lines proximate the respective angled end faces prior to forming the respective electrical contact landing pads.45. The method of claim 41 , ...

METHOD OF FORMING NICKEL SALICIDE ON A SILICON-GERMANIUM LAYER

A method of forming nickel self-aligned silicide (Ni-salicide) is disclosed, the method including the following steps in the sequence set forth: providing a substrate; forming a gate on the substrate and forming a SiGe source and a SiGe drain beneath a surface of the substrate; growing a silicon epitaxial layer over the SiGe source and the SiGe drain; amorphizing the silicon epitaxial layer; depositing a Ni—Pt layer over the amorphized silicon epitaxial layer; performing a first rapid thermal anneal process to cause Ni—Pt alloy and the amorphized silicon epitaxial layer to react; removing the unreacted Ni—Pt alloy by wet etching; and performing a second rapid thermal anneal process to form a Ni-salicide. 1. A method of forming nickel self-aligned silicide (Ni-salicide) , comprising the following steps in the sequence set forth:providing a substrate;forming a gate on the substrate and forming a SiGe source and a SiGe drain beneath a surface of the substrate;growing a silicon epitaxial layer over the SiGe source and the SiGe drain;amorphizing the silicon epitaxial layer;depositing a Ni—Pt layer over the amorphized silicon epitaxial layer;performing a first rapid thermal anneal process to cause Ni—Pt alloy and the amorphized silicon epitaxial layer to react;removing the unreacted Ni—Pt alloy by wet etching; andperforming a second rapid thermal anneal process to form a Ni-salicide.2. The method of claim 1 , wherein amorphizing the silicon epitaxial layer is accomplished by selective ion implantation.3. The method of claim 2 , wherein silicon ions claim 2 , germanium ions claim 2 , or a mixture thereof claim 2 , are implanted in the selective ion implantation.4. The method of claim 3 , wherein the silicon epitaxial layer has a thickness of 30 Å to 120 Å.5. The method of claim 4 , wherein the selective ion implantation is performed at an energy of 5 KeV to 50 KeV and a dose of 1.0×10/cmto 1.0×10/cm.6. The method of claim 1 , wherein the Ni—Pt layer has a thickness of 80 Å ...

Method for manufacturing semiconductor device

The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed. 1. (canceled)2. A method of manufacturing a semiconductor device comprising:forming a semiconductor film comprising amorphous silicon over a substrate;emitting a first laser beam having a length along a first direction and a width along a second direction, the first laser beam including TEM00 mode; modifying the first laser beam along the first direction by using a first cylindrical lens; and', 'modifying the first laser beam along the second direction by using a second cylindrical lens, and, 'shaping the first laser beam to a second laser beam having a linear shape, wherein the step of shaping includesirradiating the semiconductor film with the second laser beam to crystallize the semiconductor film,wherein the semiconductor film comprises a crystal region of which crystal plane orientation in a direction perpendicular to a surface of the semiconductor film is {100}.3. The method according to claim 2 , wherein the crystal region occupies 40% or more of the semiconductor film.4. The method according to claim 2 , wherein the semiconductor film has a thickness of greater than or equal to 10 nm and less than or equal to 100 nm.5. The method according to claim 2 , wherein the semiconductor film is formed on an insulating film having a thickness of 50 to 150 ...

Contacts for Semiconductor Devices and Methods of Forming Thereof

A method for a method of forming a semiconductor device includes providing a semiconductor substrate having a bottom surface opposite a top surface with circuitry disposed at the top surface. The method further includes forming a first metal layer having a first metal over the bottom surface of the semiconductor substrate. The first metal layer is formed by depositing an adhesion promoter followed by depositing the first metal. 1. A method of forming a semiconductor device , the method comprising:providing a semiconductor substrate having a bottom surface opposite a top surface with circuitry disposed at the top surface; andforming a first metal layer comprising a first metal over the bottom surface of the semiconductor substrate, wherein forming the first metal layer comprising depositing a adhesion promoter followed by depositing the first metal.2. The method of claim 1 , further comprising removing a native oxide from the first bottom surface to expose a second bottom surface of the semiconductor substrate claim 1 , wherein the first metal layer is deposited without breaking vacuum after removing the native oxide.3. The method of claim 1 , further comprising forming a metal silicide layer between the first metal layer and the semiconductor substrate.4. The method of claim 3 , wherein the metal silicide layer is less than about five atomic layers in thickness.5. The method of claim 1 , wherein the adhesion promoter is not a continuous layer over the bottom surface.6. The method of claim 1 , wherein the adhesion promoter is formed as islands over the bottom surface.7. The method of claim 1 , wherein the contact resistance between the first metal layer and the semiconductor substrate is independent of the adhesion promoter.8. The method of claim 1 , wherein the first metal layer is deposited as a blanket layer over substantially the entire bottom surface of the semiconductor substrate.9. The method of claim 1 , wherein the first metal layer comprises titanium or ...

SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is to formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap. 1. A method for fabricating a semiconductor device comprising:forming a dielectric layer over a substrate;forming an opening by etching the dielectric layer;forming a first conductive pattern in the opening;forming sacrificial spacer on sidewalls of the opening over the first conductive pattern;forming an ohmic contact layer over the first conductive pattern;forming a second conductive pattern over the ohmic contact layer;forming air gap by removing the sacrificial spacer; andforming a third conductive pattern over the second conductive pattern to cap the air gap.2. The method of claim 1 , wherein the forming of the third conductive pattern includes:forming a barrier layer over an entire surface including the second conductive pattern and the air gap;forming a conductive layer over the barrier layer to fill the opening; andplanarizing the conductive layer and the barrier layer.3. The method of claim 2 , wherein of the barrier layer and the conductive layer include a metal-containing material claim 2 , respectively.4. The method of claim 1 , further comprising:after the forming of the sacrificial spacer, recessing a surface of the first conductive pattern.5. The method of claim 1 , wherein the first conductive pattern include a silicon-containing material.6. The method of claim 1 , wherein the second conductive ...

LOW-K DIELECTRIC INTERCONNECT SYSTEMS

A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask. 1forming a low-k dielectric layer having a height over a substrate, wherein a ratio between the height and a distance between a first pattern and a second pattern is greater than a pre-defined height-to-width aspect ratio threshold;depositing a cap layer over the low-k dielectric layer;performing a treatment process to the cap layer; and 'wherein the first trench is associated with the first pattern and the second trench is associated with the second pattern.', 'after the performing the treatment process to the cap layer, etching the low-k dielectric layer to form a first trench and a second trench using the cap layer as an etching mask,'}. A method of fabricating a semiconductor device, comprising: The present application is a continuation application of U.S. patent application Ser. No. 15/168,596, filed May 31, 2016, entitled “LOW-K DIELECTRIC INTERCONNECT SYSTEMS,” issuing as U.S. Pat. No. 9,768,061, which is hereby incorporated by reference in its entirety.The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest ...

SEMICONDUCTOR DEVICE

Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure. 1. A semiconductor device , comprising:a substrate;a first dielectric layer on the substrate;a first lower conductive line in the first dielectric layer;an etch stop layer on the first dielectric layer;a via-structure that penetrates the etch stop layer and is connected to the first lower conductive line;a second dielectric layer on the etch stop layer; andan upper conductive line that penetrates the second dielectric layer and is connected to the via-structure,wherein the first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line,wherein the upper conductive line is in contact with a top surface of the etch stop layer, andwherein the etch stop layer has at an upper portion with a rounded surface in contact with the via-structure.2. The semiconductor device of claim 1 , wherein the etch stop layer includes:a first etch stop pattern;a second etch stop pattern on the first etch stop pattern; anda third etch stop pattern on the second etch stop pattern.3. The semiconductor device of claim 2 , wherein the third etch stop pattern has the rounded surface in contact with the via-structure.4. The semiconductor device of claim 3 , wherein the ...

TUNGSTEN NITRIDE BARRIER LAYER DEPOSITION

Provided herein are methods of tungsten nitride (WN) deposition. Also provided are stacks for tungsten (W) contacts to silicon germanium (SiGe) layers and methods for forming them. The stacks include SiGe/tungsten silicide (WSi)/WN/W layers, with WSiproviding an ohmic contact between the SiGe and WN layers. Also provided are methods for reducing fluorine (F) attack of underlying layers in deposition of W-containing films using tungsten hexafluoride (WF). Apparatuses to perform the methods are also provided. 1. A method comprising:providing a feature formed in a dielectric layer and a silicon germanium (SiGe) layer on a substrate, wherein the feature comprises a SiGe surface;exposing the SiGe surface to nitrogen radicals to treat the SiGe surface;depositing a tungsten (W) layer on the treated SiGe surface; anddepositing a tungsten nitride (WN) layer conformal to the feature.2. The method of claim 1 , further comprising filling the feature with tungsten (W).3. The method of claim 1 , wherein nitrogen radicals are generated in an inductively-coupled plasma generated from nitrogen (N) gas.4. The method of claim 1 , further comprising forming a nitride layer on the SiGe surface.5. The method of claim 1 , wherein depositing the W layer on the treated SiGe surface comprises exposing the substrate to alternating pulses of tungsten hexafluoride (WF) and a reducing agent.6. The method of claim 5 , wherein the reducing agent is silane (SiH).7. The method of claim 5 , wherein the treated SiGe surface prevents diffusion of fluorine from the WFinto SiGe underlying the treated SiGe surface.8. The method of claim 1 , wherein the W layer is between 5 Å and 30 Å thick.9. The method of claim 1 , wherein depositing WN layer comprises exposing the feature to alternating pulses of tungsten hexafluoride (WF) claim 1 , a reducing agent claim 1 , and a nitriding agent.10. The method of claim 9 , wherein the reducing agent is diborane (BH) and the nitriding agent is ammonia (NH).11. The ...

Interconnect Structure and Methods of Forming

An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening. 1. A method of forming a device , comprising:forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer;creating a vacuum environment around the device;after creating the vacuum environment around the device, etching through the etch stop layer to extend the opening and expose a first conductive feature; andforming a second conductive feature in the opening.2. The method according to claim 1 , wherein a portion of the etch stop layer remains over the first conductive feature after the opening is formed claim 1 , the portion having a thickness in a range of about 0.1 Å to about 5 Å.3. The method according to claim 1 , wherein forming the second conductive feature comprises:forming a barrier layer in the opening;forming a seed layer over the barrier layer; andelectroplating a conductive material over the seed layer.4. The method according to claim 3 , wherein the opening in the dielectric layer is formed in an open air environment claim 3 , and wherein the vacuum environment is maintained during the forming of the barrier layer and the seed layer.5. The method according to claim 1 , wherein a process gas is used to etch through the etch stop layer to extend the opening and expose the first conductive feature claim 1 , the process gas comprising carbon and fluorine.6. The method according to claim 5 , wherein forming the second conductive feature in the ...

IC WITH 3D METAL-INSULATOR-METAL CAPACITOR

An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate. 1. A method of fabricating an integrated circuit (IC) including a Metal-Insulator-Metal (MIM) capacitor , comprising:providing a semiconductor surface layer on a substrate; forming a multilevel bottom capacitor plate over the semiconductor surface layer and having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces;', 'depositing at least one capacitor dielectric layer having thickness that does not vary on the bottom capacitor plate;', 'forming a top capacitor plate on the capacitor dielectric layer having thickness that does not vary; and, 'forming the MIM capacitor, comprisingforming filled contacts through a pre-metal dielectric layer to contact the top capacitor plate and to contact the bottom capacitor plate.2. The method of claim 1 , wherein the capacitor dielectric layer comprises a dielectric stack comprising a first silicon oxide layer claim 1 , a nitride layer claim 1 , and a second silicon oxide layer claim 1 , wherein the depositing the nitride layer comprises low pressure chemical vapor deposition (LPCVD) or ...

Semiconductor Contact Structure, Semiconductor Device, and Method for Forming the Same

Semiconductor contact structures, a semiconductor device including the semiconductor contact structures, and a method for forming the same are disclosed. In an embodiment, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, the interface layer including titanium (Ti), the interface layer contacting the channel layer; and a contact metal layer over the interface layer, the contact metal layer including aluminum silicon copper alloy (AlSiCu). 1. A semiconductor device comprising:a channel layer on a substrate;an interface layer on the channel layer, the interface layer comprising titanium (Ti), the interface layer contacting the channel layer; anda contact metal layer over the interface layer, the contact metal layer comprising aluminum silicon copper alloy (AlSiCu).2. The semiconductor device of claim 1 , wherein the channel layer comprises indium gallium arsenide (InGaAs).3. The semiconductor device of claim 1 , wherein the channel layer comprises indium arsenide (InAs) claim 1 , indium gallium phosphide (InGaP) claim 1 , indium aluminum arsenide (InAlAs) claim 1 , gallium nitride (GaN) claim 1 , indium gallium nitride (InGaN) claim 1 , aluminum gallium nitride (AlGaN) claim 1 , or silicon germanium (SiGe).4. The semiconductor device of claim 1 , wherein the substrate comprises indium phosphide (InP).5. The semiconductor device of claim 1 , wherein the substrate comprises silicon germanium (SiGe) claim 1 , gallium arsenide (GaAs) claim 1 , silicon (Si) claim 1 , germanium (Ge) claim 1 , silicon carbide (SiC) claim 1 , or sapphire (AlO).6. The semiconductor device of claim 1 , wherein the material of the contact metal layer is represented by the formula AlSiCu claim 1 , wherein x is between 1 atomic percent and 2 atomic percent claim 1 , and wherein y is between 0.5 atomic percent and 4 atomic percent.7. The semiconductor device of claim 1 , wherein the material of the contact metal layer is represented by the ...

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided. A barrier layer is formed on the substrate. A sacrificial layer is formed on the barrier layer. An opening pattern is formed over the sacrificial layer by utilizing a photolithography process. The sacrificial layer is etched according to the opening pattern to form first trenches by using the barrier layer as an etch stop layer. A medium layer material is filled in the first trenches. The sacrificial layer is etched to form second trenches by using the barrier layer as the etch stop layer. A hard mask layer material is filled in the second trenches. The medium layer material is etched to form a hard mask layer by using the barrier layer as the etch stop layer. 1. A manufacturing method of a semiconductor structure , comprising:providing a substrate;forming a barrier layer on the substrate;forming a sacrificial layer on the barrier layer;forming an opening pattern over the sacrificial layer through a photolithography process;etching the sacrificial layer according to the opening pattern by taking the barrier layer as an etch stop layer to form first trenches;filling a medium layer material in the first trenches;etching the sacrificial layer by taking the barrier layer as the etch stop layer to form second trenches;filling a hard mask layer material in the second trenches; andetching the medium layer material by taking the barrier layer as the etch stop layer to form a hard mask layer.2. The manufacturing method of the semiconductor structure of claim 1 , wherein the sacrificial layer has a hardness less than a hardness of the hard mask layer3. The manufacturing method of the semiconductor structure of claim 1 , wherein both an etch selectivity ratio of the sacrificial layer to the barrier layer and an etch selectivity ratio of the medium layer material to the barrier layer are greater than 100.4. The manufacturing method of the semiconductor structure of claim 1 ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device according to an embodiment includes: a barrier metal layer provided on a surface of an insulating layer; and a conductive layer having a first metal layer provided on a surface of the barrier metal layer, and a second metal layer provided on a surface of the first metal layer. The second metal layer includes an identical metal to metal of the first metal layer, and an impurity configured to remove fluorine bonded to the metal. 1. A manufacturing method of a semiconductor device , comprising:forming a barrier metal layer on a surface of an insulating layer;forming a first metal layer on a surface of the barrier metal layer; andforming, on a surface of the first metal layer, a second metal layer including an identical metal to metal of the first metal layer, and an impurity configured to remove fluorine bonded to the metal.2. The manufacturing method of claim 1 , wherein a bond energy between the impurity and the metal is higher than a bond energy between the metal and the fluorine.3. The manufacturing method of claim 1 , wherein the impurity includes at least one of an aluminum atom (Al) claim 1 , a zirconium atom (Zr) claim 1 , a hafnium atom (Hf) claim 1 , a silicon atom (Si) claim 1 , a boron atom (B) claim 1 , a titanium atom (Ti) claim 1 , an oxygen atom (O) claim 1 , an yttrium atom (Y) and a carbon atom (C).4. The manufacturing method of claim 1 , wherein a concentration of the impurity is uniform in the second metal layer.5. The manufacturing method of claim 1 , wherein an impurity concentration in the second metal layer is 1×10to 1×10atoms/cm.6. The manufacturing method of claim 1 , comprising forming claim 1 , in the second metal layer claim 1 , at least one high concentration layer in which a concentration of the impurity is locally high. This application is a divisional of U.S. application Ser. No. 16/814,716 filed Mar. 10, 2020; U.S. application Ser. No. 16/814,716 is based upon and claims the benefit of priority from Japanese ...

CONDUCTIVE PLUG AND METHOD OF FORMING THE SAME

A method of forming a conductive plug is disclosed. A material layer having at least one opening is provided on a substrate. A first conductive layer is deposited in the opening, wherein the first conductive layer does not completely fill up the opening. A second conductive layer is deposited on the first conductive layer. A surface treatment is performed after the step of depositing the first conductive layer and before the step of depositing the second conductive layer, so that the first deposition rate of the second conductive layer at the lower portion of the opening is greater the second deposition rate of the second conductive layer at the upper portion of the opening. A void-free conductive plug can be easily formed with the method of the invention. 1. A method of forming a conductive plug , comprising:providing a material layer having at least one opening on a substrate;depositing a first conductive layer in the opening, wherein the first conductive layer does not completely fill up the opening;depositing a second conductive layer on the first conductive layer; andperforming a surface treatment after the step of depositing the first conductive layer and before the step of depositing the second conductive layer, so that a first deposition rate of the second conductive layer at a lower portion of the opening is greater than a second deposition rate of the second conductive layer at an upper portion of the opening.2. The method of claim 1 , wherein the surface treatment comprises a nitrogen-containing species.3. The method of claim 2 , wherein the nitrogen-containing species comprises nitrogen claim 2 , NO claim 2 , NH claim 2 , a mixture of nitrogen and hydrogen claim 2 , or a combination thereof.4. The method of claim 2 , wherein the surface treatment further comprises a fluorine-containing species.5. The method of claim 4 , wherein the fluorine-containing species comprises NF.6. The method of claim 1 , wherein each of the first and second conductive layers ...

SELF-ALIGNED BARRIER AND CAPPING LAYERS FOR INTERCONNECTS

An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided. 1. A process for forming an integrated circuit interconnect structure , said process comprising:a) providing a partially-completed interconnect structure having one or more vias and trenches, said vias and trenches comprising sidewalls defined by one or more electrically insulating materials and electrically conductive copper-containing bottom regions;b) depositing a layer comprising a nitride of a metal selected from the group consisting of manganese, chromium and vanadium on the partially-completed interconnect structure;c) depositing copper within said one or more vias and trenches.2. The process of claim 1 , further comprising removing nitrogen from said layer comprising metal nitride prior to said depositing copper within said one or more vias and trenches.3. The process as in wherein said removing nitrogen is accomplished by contact of the structure with a hydrogen-containing plasma.4. The process as in ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

According to embodiments, a semiconductor device is provided. The semiconductor device includes an insulation layer, an electrode, and a groove. The insulation layer is provided on a surface of a substrate. The electrode is buried in the insulation layer, and a first end surface of the electrode is exposed from the insulation layer. The groove is formed around the electrode on the surface of the substrate. The groove has an outside surface of the electrode as one side surface, and the groove is opened on the surface side of the insulation layer. The first end surface of the electrode buried in the insulation layer protrudes from the surface of the insulation layer. 1. A semiconductor device comprising:an insulation layer provided on a surface of a substrate;an electrode buried in the insulation layer and having a first end surface exposed from the insulation layer; anda groove formed on the surface of the substrate around the electrode.2. The semiconductor device according to claim 1 , wherein the groove has an outside surface of the electrode as one side surface claim 1 , and the groove is opened on the surface side of the insulation layer.3. The semiconductor device according to claim 1 , wherein the first end surface of the electrode protrudes from a surface of the insulation layer.4. The semiconductor device according to claim 1 , comprising:a different substrate stuck to the substrate via the insulation layer;an insulation layer provided on a sticking surface of the different substrate; anda corresponding electrode buried in the insulation layer in a position corresponding to the electrode and having a first end surface exposed from a surface of the insulation layer.5. The semiconductor device according to claim 4 , comprising:a groove that has an outside surface of the corresponding electrode as one side surface, that is opened on the surface side of the insulation layer in which the corresponding electrode is buried, and that surrounds the corresponding ...

VIA STRUCTURE AND METHOD OF FORMING THE SAME

A via structure and a method of forming the same are provided. In the forming method of the present invention, a via is formed in a dielectric layer. Next, a U-shaped seed layer is formed in the via. After that, a conductive material is selectively formed in the via to form a conductive bulk layer in the via. Through the present invention, the purposes of effectively removing the overhang adjacent to the opening of the via and protecting the U-shaped seed layer in the via can be achieved. 1. A method of forming a via structure , comprising:forming a via in a dielectric layer;forming a U-shaped seed layer in the via only; andselectively forming a conductive material in the via to form a conductive bulk layer in the via.2. The method of forming a via structure according to claim 1 , further comprising:providing a substrate having a conductive region; andforming the dielectric layer on the substrate, wherein at least a portion of the conductive region is exposed.3. The method of forming a via structure according to claim 1 , further comprising:forming a seed material layer, wherein the seed material layer is at least disposed in the via; andperforming a removing process by removing a portion of the seed material layer to form the U-shaped seed layer.4. The method of forming a via structure according to claim 1 , further comprising:forming a U-shaped barrier layer in the via, before forming the U-shaped seed layer.5. The method of forming a via structure according to claim 3 , further comprising:before forming the seed material layer, forming a barrier material layer, the barrier material layer covering the via and a surface of the dielectric layer; andperforming a removing process by removing a portion of the barrier material layer to formed a U-shaped barrier layer.6. The method of forming a via structure according to claim 3 , wherein the removing process comprises a dry etching process.7. The method of forming a via structure according to claim 3 , wherein the ...

Semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor device includes forming a metal-containing layer over a semiconductor substrate, forming an insulating film to cover the semiconductor substrate and the metal-containing layer, forming a first contact hole that penetrates through the insulating film to reach the semiconductor substrate, forming a second contact hole that penetrates through the insulating film to reach the metal-containing layer, forming a first conductive plug on a portion, exposed through the first contact hole, of the semiconductor substrate and including a first material, forming a second conductive plug on the first conductive plug and including a second material, the semiconductor substrate being closer to a lower surface of the second conductive plug than to an upper surface of the metal-containing layer, and forming a third conductive plug on a portion, exposed through the second contact hole, of the metal-containing layer, the third conductive plug including a third material.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings. 1. A method for fabricating a semiconductor device , comprising:forming an interlayer dielectric layer on a base substrate;forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate to expose the base substrate;forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings;forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer;forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings;performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric layer to cause the oxygen ions to diffuse into the high-K dielectric layer;removing the amorphous silicon layer; andforming a metal layer to fill the first openings and the second openings.2. The method according to claim 1 , wherein:the high-K dielectric layer has ...

SEMICONDUCTOR STRUCTURE CONTAINING LOW-RESISTANCE SOURCE AND DRAIN CONTACTS

Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device. 1. A method of forming a semiconductor structure , said method comprising:providing a structure comprising at least one first functional gate structure located on a first semiconductor material portion within a pFET device region of a semiconductor substrate and at least one second functional gate structure located on a second semiconductor material portion within an nFET device region of the semiconductor substrate, wherein a first epitaxial semiconductor material is located on each side of said at least one first functional gate structure and in contact with a surface of said first semiconductor material portion, and a second epitaxial semiconductor material is located on each side of said at least one second functional gate structure and in contact with a surface of said second semiconductor material portion, and wherein a surface of said first epitaxial semiconductor material includes a high k dielectric layer disposed thereon;forming a layer of a dipole metal or a metal-insulator-semiconductor oxide on said second epitaxial semiconductor material, but not said first epitaxial semiconductor material;removing said high k dielectric layer from said surface of said first epitaxial semiconductor material; andforming a first ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

While increasing a threshold voltage of a MOSFET configuring a CMOS, electric power saving of elements is achieved by suppressing excessive increase in the threshold voltage, and occurrence of performance variation among the elements is suppressed. A gate electrode of an NMOS is made of a P-type semiconductor film, a high-permittivity film is provided in a gate insulating film of the NMOS, and an impurity is prevented from being introduced into a channel region of the NMOS. Moreover, a high-permittivity film is provided also in a gate insulating film of a PMOS. 1. A semiconductor device comprising:a semiconductor substrate;a first insulating film on the semiconductor substrate;a semiconductor layer on the first insulating film;a first gate electrode including a first semiconductor film of a P type, which is formed on the semiconductor layer via a second insulating film; anda pair of first source/drain regions formed by introducing an impurity of an N type into the semiconductor layer next to the first gate electrode,wherein the semiconductor substrate, the first insulating film, and the semiconductor layer configure a SOI substrate,the first gate electrode and the pair of first source/drain regions configure an N-channel-type field-effect transistor, andthe second insulating film contains a material having a permittivity higher than a permittivity of silicon oxide.2. The semiconductor device according to claim 1 ,wherein the semiconductor layer mutually between the pair of first source/drain regions is an intrinsic semiconductor layer.3. The semiconductor device according to claim 1 ,{'sup': 17', '3, 'wherein an impurity concentration of the P type in the semiconductor layer mutually between the pair of first source/drain regions is 1×10/cmor lower.'}4. The semiconductor device according to claim 1 ,wherein, among a first region and a second region arranged in a direction along an upper surface of the SOI substrate, the N-channel-type field-effect transistor is ...

MOS Devices Having Epitaxy Regions with Reduced Facets

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. 120-. (canceled)21. A semiconductor device comprising:a semiconductor substrate;a gate structure; a first germanium comprising region;', 'a capping layer over the first germanium comprising region, the capping layer having a lower germanium percentage than the first germanium comprising region; and, 'a source/drain region adjacent the gate structure, the source/drain region comprisinga silicide extending through the capping layer, wherein a germanium percentage at a first point in the silicide is greater than a silicon percentage at the first point in the silicide.22. The semiconductor device of claim 21 , wherein a line extends from a second point outside of the silicide to the first point claim 21 , wherein the line is parallel to a major surface of the semiconductor substrate claim 21 , wherein a germanium percentage at the second point is lower than a silicon percentage at the second point.23. The semiconductor device of claim 21 , wherein the silicide extends higher than the first point in the silicide.24. The semiconductor device of claim 21 , wherein the source/drain region further comprises a second germanium comprising region under the first germanium comprising region claim 21 , wherein the second germanium comprising region has a lower germanium percentage than the first ...

Conductive Feature Formation and Structure

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

SILICIDE FILM NUCLEATION

Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication. 1. A system for fabricating a MOSFET device , comprising:a transfer chamber defining a transfer space;a plurality of process chambers, wherein each process chamber of the plurality of process chambers is coupled to the transfer chamber;a transfer robot in the transfer space configured to access the transfer chamber and the plurality of process chambers;a controller comprising instructions for device fabrication, wherein, when executed by a processor, the instructions:retrieve a substrate from the transfer chamber;dispose the substrate in a first process chamber of the plurality of process chambers;perform at least one pre-silicide treatment on the substrate in the first process chamber to increase a concentration of a dopant within the substrate or to increase a surface roughness of the substrate; andsubsequently, form, by deposition, in a second process chamber of the plurality of process chambers, a metal-silicide on the substrate.2. The system of claim 1 , wherein the plurality of process chambers comprises an NMOS chamber claim 1 , a PMOS chamber claim 1 , a pre-clean chamber claim 1 , a metal-silicide deposition chamber claim 1 , or a plasma chamber.3. The system of claim 2 , wherein the at least one pre-silicide treatment is performed in the NMOS chamber claim 2 , the PMOS chamber claim 2 , the metal-silicide deposition chamber claim 2 , or the plasma chamber.4. The system of claim 1 , wherein the metal-silicide deposition is performed in the first process chamber that comprises a metal-silicide deposition chamber.5. The system of ...

METHODS FOR SILICIDE DEPOSITION

Methods for depositing a metal silicide are provide and include heating a substrate having a silicon-containing surface to a deposition temperature, and exposing the substrate to a deposition gas to deposit a silicide film on the silicon-containing surface during a chemical vapor deposition process. The deposition gas contains a silicon precursor, a titanium or other metal precursor, and a phosphorus or other non-metal precursor. 1. A method for depositing a metal silicide , comprising:heating a substrate having a silicon-containing surface to a deposition temperature; andexposing the substrate to a deposition gas to deposit a silicide film on the silicon-containing surface during a chemical vapor deposition process, wherein the deposition gas comprises a silicon precursor, a titanium precursor, and a phosphorus precursor.2. The method of claim 1 , wherein the deposition temperature is in a range from about 400° C. to about 750° C.3. The method of claim 1 , wherein the silicide film has a Ti:Si atomic ratio from about 2:1 to about 15:1 and a P:Si atomic ratio about 2:1 to about 12:1.4. The method of claim 1 , wherein the silicide film comprises about 40 atomic percent (at %) to about 70 at % of titanium claim 1 , about 1 at % to about 50 at % of phosphorus claim 1 , and about 1 at % to about 25 at % of silicon.5. The method of claim 1 , wherein the silicide film comprises about 50 at % to about 60 at % of titanium claim 1 , about 25 at % to about 45 at % of phosphorus claim 1 , and about 2 at % to about 15 at % of silicon.6. The method of claim 1 , wherein the silicide film has a resistivity of about 150 μΩ-cm to about 300 μΩ-cm.7. The method of claim 1 , wherein the silicon precursor comprises silane claim 1 , disilane claim 1 , trisilane claim 1 , tetrasilane claim 1 , dichlorosilane claim 1 , trichlorosilane claim 1 , hexachlorodisilane claim 1 , or any combination thereof claim 1 , the titanium precursor comprises titanium tetrachloride claim 1 , tetrakis( ...

Method of Forming Contact Metal

A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench. 1. A device comprising:a source/drain feature disposed on a substrate;a silicide layer disposed on the source/drain feature;a dielectric layer disposed over the substrate;a titanium nitride (TiN) layer extending along a sidewall of the dielectric layer to a top surface of the silicide layer, wherein a comparison of a thickness of the TiN layer over the top surface of the silicide layer versus a thickness of the TiN layer along the sidewall of the dielectric layer is greater than 90%; anda conductive layer extending along the TiN layer.2. The device of claim 1 , further comprising a gate structure disposed on the substrate claim 1 , andwherein the TiN layer physically contacts the gate structure.3. The device of claim 2 , wherein the dielectric layer extends over a top surface of the gate structure.4. The device of claim 2 , wherein the gate structure includes a dielectric sidewall spacer claim 2 , andwherein the TiN layer physically contacts the dielectric sidewall spacer.5. The device of claim 1 , wherein the TiN layer has a u-shaped profile.6. The device of claim 1 , wherein the TiN layer includes a first sidewall portion and opposing second sidewall portion claim 1 , andwherein the conductive layer extends from the first sidewall portion to the second sidewall portion.7. The device of claim 1 , wherein the conductive layer has a first width adjacent the silicide layer and a second width disposed over the first width adjacent the silicide layer claim 1 , the second width different than the first width.8. A device comprising:a source/drain feature disposed on a substrate;a silicide layer ...

Interconnection Structure, Fabricating Method Thereof, and Semiconductor Device Using the Same

A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide. 1. A device comprising:a multi-gate transistor, the multi-gate transistor including a source/drain region;a dielectric layer overlying the source/drain region;a filled contact opening extending through the dielectric layer, the filled contact opening defined by sidewalls of the dielectric layer;a metal liner extending along and contacting the sidewalls of the dielectric layer;a barrier layer extending along and contacting the metal liner, the metal liner being interjacent the barrier layer and the sidewalls of the dielectric layer;a silicide of the source/drain region and the metal liner at a bottom of the filled contact opening; anda conductor within the filled contact opening, the barrier layer extending between the conductor and the silicide.2. The device of claim 1 , wherein the multi-gate transistor is at least partially in a substrate claim 1 , and further comprising two p-well regions in the substrate and an n-well region in the substrate claim 1 , the n-well region being interjacent the two p-well regions.3. The device of claim 2 , wherein the multi-gate transistor is an n-type FinFET having a first fin extending from the n-well region.4. The device of claim 3 , further comprising:a p-type FinFET having a second fin extending from one of the two p-well regions and including a second source/drain region; anda continuous gate electrode extending over the first fin and the second fin.5. The device of wherein the source/drain ...

METHOD OF FORMING SALICIDE BLOCK WITH REDUCED DEFECTS

A method of forming a salicide block with reduced defects is disclosed, the method including performing an ultraviolet cure process on a silicon nitride layer deposited in a previous step. High-energy ultraviolet light used in the ultraviolet cure process breaks the hydrogen-containing chemical bonds such as silicon-hydrogen and nitrogen-hydrogen in the silicon nitride layer, and the dissociated hydrogen forms molecular hydrogen which is thereafter evacuated away by a vacuuming apparatus. In this way, the hydrogen content in the silicon nitride layer can be effectively decreased and the reaction between hydrogen in the silicon nitride layer and photoresist subsequently coated thereon can hence be reduced. As a result, a salicide block with reduced defects can be obtained, thus improving process reliability and product yield. 1. A method of forming a salicide block , comprising the following steps in the sequence set forth:depositing a silicon nitride layer over a silicon wafer by plasma enhanced chemical vapor deposition, wherein the silicon nitride layer includes hydrogen-containing chemical bonds such as silicon-hydrogen and nitrogen-hydrogen;performing an ultraviolet cure process on the silicon nitride layer to break the hydrogen-containing chemical bonds and removing hydrogen; andpatterning the silicon nitride layer by photolithography and etching to form a salicide block.2. The method of claim 1 , further comprising the steps of:sputtering a metal over the silicon wafer;performing a rapid annealing process to form metal silicides over portions of the silicon wafer not covered by the salicide block; andstripping away the remaining metal not formed into the metal silicides.3. The method of claim 1 , wherein performing an ultraviolet cure process on the silicon nitride layer comprises:disposing the silicon wafer with the silicon nitride layer deposited thereon in an ultraviolet chamber; andirradiating ultraviolet light on the silicon nitride layer and vacuuming ...

METHOD OF MANUFACTURING THROUGH-SILICON-VIA

A method of manufacturing through-silicon-via (TSV) including the steps of sequentially forming a liner layer and a metal layer in a TSV hole, performing a chemical mechanical polishing process to remove the metal layer on the substrate so that the remaining metal layer in the TSV hole becomes a TSV, and forming a cap layer on the substrate without performing a NHtreatment. 1. A method of manufacturing through-silicon-via , comprising the steps of:providing a substrate;forming a TSV hole in said substrate;conformally forming a liner layer on said substrate and said TSV hole;forming a metal layer on said liner layer;performing a chemical mechanical polishing process to remove said metal layer on said substrate, so that the remaining said metal layer in said TSV hole becomes a through-silicon-via; and{'sub': '3', 'forming a cap layer on said substrate and said through-silicon-via without performing a NHtreatment.'}2. A method of manufacturing through-silicon-via according to claim 1 , further comprising conformally forming a barrier layer on said liner layer.3. A method of manufacturing through-silicon-via according to claim 1 , further comprising conformally forming a seed layer on said barrier layer.4. A method of manufacturing through-silicon-via according to claim 1 , further comprising performing an annealing process to said metal layer before performing said chemical mechanical polishing process.5. A method of manufacturing through-silicon-via according to claim 1 , wherein said anneal process is performed at a temperature larger than 400° C. with a duration of 30 minutes.6. A method of manufacturing through-silicon-via according to claim 1 , wherein said liner layer is formed by using a sub-atmospheric chemical vapor deposition process claim 1 , a low pressure chemical vapor deposition process claim 1 , or a furnace oxidation process.7. A method of manufacturing through-silicon-via according to claim 1 , wherein said barrier layer is formed by using a ...

MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A mask may be used in a process for manufacturing a semiconductor device. The semiconductor device may include a source line, a first drain contact terminal, and a second drain contact terminal. The mask may include the following elements: a source-line corresponding light-transmitting portion, which corresponds to the source line; a first-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the first drain contact terminal; a second-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the second drain contact terminal; and a first light-blocking portion, which abuts at least one of the source-line corresponding light-transmitting portion, the first-drain-contact-terminal corresponding light-transmitting portion, and the second-drain-contact-terminal corresponding light-transmitting portion.

METHODS FOR DEPOSITING NICKEL FILMS AND FOR MAKING NICKEL SILICIDE AND NICKEL GERMANIDE

In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. Nickel thin films can be used directly in silicidation and germanidation processes. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. (canceled)10. (canceled)11. (canceled)12. (canceled)13. (canceled)14. (canceled)15. (canceled)16. (canceled)17. (canceled)18. (canceled)19. A method for silicidation , comprising:providing a substrate having at least one exposed silicon region;depositing a nickel thin film over the exposed silicon region; andheating the substrate to form a nickel silicidewherein the nickel thin film is deposited by a nickel thin film deposition process comprising alternately and sequentially contacting the substrate with vapor phase pulses of a nickel precursor and a second reactant comprising an organic reducing agent, hydrogen, or forming gas.20. The method of claim 19 , wherein the nickel thin film is deposited by an ALD-type process.21. (canceled)22. The method of claim 19 , wherein the nickel precursor is selected from the group consisting of nickel betadiketonate compounds claim 19 , nickel betadiketiminato compounds claim 19 , nickel aminoalkoxide compounds claim 19 , nickel ...

CONDUCTIVE STRUCTURE AND METHOD OF FORMING THE SAME

Conductive structures and method of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive structure includes providing a substrate having a recess formed therein, the recess lined with a first seed layer and partially filled with a first conductive material; removing a portion of the first seed layer free from the first conductive material to form an exposed surface of the recess; lining the exposed surface of the recess with a second seed layer; and filling the recess with a second conductive material, the second conductive material covering the first conductive material and the second seed layer.

Semiconductor Devices and Fabrication Methods With Reduced Topology And Reduced Word Line Stringer Residual Material

Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a first dielectric layer over buried oxide regions and the removal of such dielectric layer to prepare a substantially planar substrate for subsequent formation of word lines. The method may allow for the production of semiconductor memory devices of reduced size with reduced word line stringer residual material. 1. A method of fabricating a semiconductor memory device comprising:providing a substrate, a buffer layer, and a hard mask layer;forming a buried diffusion region in the substrate;depositing a first dielectric fill material along the substrate;removing excess first dielectric fill material above the hard mask layer;performing self-aligned patterning to form at least one trench in a self-aligned contact region of the semiconductor;depositing a second dielectric fill material along the substrate;removing excess second dielectric fill material above the hard mask layer;removing the hard mask layer; andremoving the first dielectric fill material.2. The method of further comprising applying a photo resist layer to at least a portion of the semiconductor prior to performing self-aligned patterning.3. The method of further comprising removing the photo resist layer after performing self-aligned patterning.4. The method of further comprising depositing a first dielectric layer after removing the first dielectric fill material.5. The method of further comprising depositing a first conductive layer along the first word line dielectric layer.6. The method of further comprising depositing a second conductive layer along the first conductive layer.7. The method of further comprising etching at least one word line in the semiconductor.8. The method of wherein the buried diffusion region is formed by doping the substrate with n-type dopants.9. The method of wherein depositing the first dielectric fill material ...

METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING A RESISTOR STRUCTURE

Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element. 1. A method of fabricating a semiconductor device , comprising:providing a substrate including a transistor area and a resistor area;forming active gate structures on the substrate in the transistor area;forming dummy gate structures on the substrate in the resistor area;forming a lower interlayer insulating layer on the substrate to cover side walls of the active gate structures and the dummy gate structures;forming a resistor structure comprising a buffer insulating pattern, a resistor element, and an etch-retard pattern stacked sequentially on the dummy gate structures and the lower interlayer insulating layer in the resistor area;forming an intermediate interlayer insulating layer on the lower interlayer insulating layer to cover the resistor structure;forming resistor contact structures configured to pass through the intermediate interlayer insulating layer and the etch-retard pattern, and to contact the resistor element; andforming an upper interlayer insulating layer on the intermediate interlayer insulating layer and the resistor contact structures.2. The method according to claim 1 , further comprising forming source/drain areas in the substrate between the active gate structures claim 1 ,wherein the source/drain areas are covered by the lower interlayer insulating layer.3. The method according to claim 2 , further comprising forming gate contact structures configured to pass through the ...

METHOD FOR CLEANING VIA OF INTERCONNECT STRUCTURE OF SEMICONDUCTOR DEVICE STRUCTURE

A method for forming the semiconductor device structure is provided. The method includes forming a metal layer in a first dielectric layer over a substrate and forming an etch stop layer over the metal layer. The etch stop layer is made of metal-containing material. The method also includes forming a second dielectric layer over the etch stop layer and removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process. The method further includes performing a plasma cleaning process on the via and the second dielectric layer, and the plasma cleaning process is performed by using a plasma including nitrogen gas (N) and hydrogen gas (H). 1. A method for forming a semiconductor device structure , comprising:forming a metal layer in a first dielectric layer over a substrate;forming an etch stop layer over the metal layer, wherein the etch stop layer is made of metal-containing material;forming a second dielectric layer over the etch stop layer removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process; and{'sub': 2', '2, 'performing a plasma cleaning process on the via and the second dielectric layer, wherein the plasma cleaning process is performed by using a plasma comprising nitrogen gas (N) and hydrogen gas (H).'}2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein a ratio of the flow rate of nitrogen gas (N) to the flow rate of hydrogen gas (H) is in a range from about 2/1 to about 4/1.3. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:after the plasma cleaning process, performing a wet cleaning process on the second dielectric layer.4. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the etching process is performed by using an etch gas comprising fluorine-containing gas.5. The method for forming the semiconductor device ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Pretreatment is carried out in a first chamber. Then, a mixed gas of titanium tetrachloride and hydrogen is supplied into a second chamber. At this time, conditions are set such that partial pressure of the titanium tetrachloride is higher than 3 Pa. The conditions are set such that the product of the partial pressure of the titanium tetrachloride and supply time is greater than 800 Pa·second. The titanium tetrachloride continues to be supplied into the second chamber to form a titanium film under prescribed temperature conditions in a plasma atmosphere. The temperature conditions are set such that temperature is higher than temperature at which titanium silicide is formed and lower than temperature at which a metal silicide film agglomerates. A titanium nitride film is formed in a third chamber. 1. A method of manufacturing a semiconductor device , comprising the steps of:forming a metal silicide film over a semiconductor substrate;forming an interlayer insulating film over the semiconductor substrate to cover the metal silicide film;forming a first contact hole of a first depth, the first contact hole penetrating the interlayer insulating film and reaching the metal silicide film;forming a second contact hole of a second depth deeper than the first depth, the second contact hole penetrating the interlayer insulating film and reaching the semiconductor substrate;forming a barrier metal film in each of the first contact hole and the second contact hole; andforming a plug to fill each of the first contact hole and the second contact hole, forming a first barrier metal film, and', 'forming a second barrier metal film so as to be in contact with the first barrier metal film,, 'the step of forming a barrier metal film including the steps of'} [{'sub': 4', '2, 'supplying a mixed gas of titanium tetrachloride (TiCl) and hydrogen (H) under such conditions that partial pressure of the titanium tetrachloride is 3 Pa or higher and the product of the partial pressure of the ...

METHOD OF FORMING INTERCONNECT STRUCTURE

Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via. 1. A method of forming an interconnect structure , comprising:forming a via;forming a first barrier layer to at least cover a top surface and a sidewall of the via;forming a first dielectric layer on the first barrier layer;performing a first planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via;forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via;forming a blocking layer on the top surface of the via;forming a second barrier layer on the second dielectric layer;removing the blocking layer to expose the top surface of the via; andforming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via, wherein the forming the conductive feature in the opening comprises:forming a seed material on the second barrier layer, wherein the seed material is in direct contact with the top surface of the via;forming a conductive material on the seed material to fill up the ...

METHOD FOR FORMING IMPROVED LINER LAYER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

A method for manufacturing a semiconductor device includes conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer, annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N) and ammonia (NH) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200 Watts to about 4500 Watts, and forming a conductive layer on the liner layer on the top surface of the dielectric layer, and on the liner layer in a remaining portion of the opening. 1. A method for manufacturing a semiconductor device , comprising:conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer;{'sub': 2', '3, 'annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N) and ammonia (NH) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200 Watts to about 4500 Watts; and'}forming a conductive layer directly on the liner layer on the top surface of the dielectric layer, and directly on the liner layer in a remaining portion of the opening;wherein the liner layer forms at least one of a halogen barrier and a diffusion barrier.2. The method according to claim 1 , wherein the liner layer is deposited using atomic layer deposition (ALD).3. The method according to claim 1 , wherein the liner layer comprises titanium nitride.4. The method according to claim 3 , wherein a density of the liner layer is greater than about 4.5 g/cm.5. The method according to claim 3 , wherein the liner layer further comprises carbon claim 3 , and the annealing reduces an amount of carbon in the liner layer.6. The method according to claim 3 , wherein the annealing removes nitrogen containing claim 3 , organic residue from the liner layer.7. The method according to claim 3 , wherein the annealing increases a ratio of ...

METHOD FOR FORMING IMPROVED LINER LAYER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

A method for manufacturing a semiconductor device includes conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer, annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N) and ammonia (NH) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200 Watts to about 4500 Watts, and forming a conductive layer on the liner layer on the top surface of the dielectric layer, and on the liner layer in a remaining portion of the opening. 1. A semiconductor device , comprising:a dielectric layer;an opening formed in the dielectric layer;a liner layer on sidewall and bottom surfaces of the opening; anda conductive layer on the liner layer in the opening;{'sup': '3', 'wherein the liner layer comprises titanium nitride, and a density of the liner layer is greater than about 4.5 g/cm.'}2. The semiconductor device according to claim 1 , wherein the liner layer and the conductive layer form at least part of an interconnect.3. The semiconductor device according to claim 1 , wherein the liner layer and the conductive layer form at least part of a gate structure.4. The semiconductor device according to claim 3 , wherein the liner layer is formed on a gate dielectric.5. The semiconductor device according to claim 3 , wherein the liner layer is formed on a gate spacer.6. The semiconductor device according to claim 1 , wherein a thickness of the liner layer is in a range of about 5 angstroms to about 20 nm.7. The semiconductor device according to claim 6 , wherein a thickness of the liner layer is in a range of about 5 nm to about 10 nm.8. The semiconductor device according to claim 1 , wherein the liner layer is an oxygen diffusion barrier.9. The semiconductor device according to claim 1 , wherein the liner layer is a halogen diffusion barrier.10. The semiconductor device according to claim 1 , wherein the liner layer is a ...

CVD Mo DEPOSITION BY USING MoOCl4

A method of forming a molybdenum-containing material on a substrate is described, in which the substrate is contacted with molybdenum oxytetrachloride (MoOCl) vapor under vapor deposition conditions, to deposit the molybdenum-containing material on the substrate. In various implementations, a diborane contact of the substrate may be employed to establish favorable nucleation conditions for the subsequent bulk deposition of molybdenum, e.g., by chemical vapor deposition (CVD) techniques such as pulsed CVD. 1. A method of forming a molybdenum-containing material on a substrate , comprising contacting the substrate with molybdenum oxytetrachloride (MoOCl) vapor under vapor deposition conditions , to deposit the molybdenum-containing material on the substrate.2. The method of claim 1 , comprising establishing a nucleation surface on the substrate and wherein said contacting of the substrate with molybdenum oxytetrachloride (MoOCl) vapor comprises contacting the nucleation surface of the substrate with molybdenum oxytetrachloride (MoOCl) vapor to deposit the molybdenum-containing material on the substrate.3. The method of claim 2 , wherein establishing the nucleation surface on the substrate comprises contacting the substrate with diborane vapor and optionally separately with molybdenum oxytetrachloride (MoOCl) vapor.4. The method of claim 3 , wherein establishing the nucleation surface comprises a plurality of cycles of contacting the substrate with diborane vapor and separately with molybdenum oxytetrachloride (MoOCl) vapor.5. The method of claim 3 , wherein the contact of the titanium nitride layer with diborane vapor is conducted at temperature in a range of from 300° C. to 450° C.6. The method of claim 1 , wherein the vapor deposition conditions are pulsed vapor deposition conditions.7. The method of claim 1 , wherein the vapor conditions are selected such that the deposited molybdenum-containing material has a resistivity of at most 20 μΩ·cm.8. The method of claim ...

METHODS FOR DEPOSITING SEMICONDUCTOR FILMS

A method for forming a film on a substrate in a semiconductor process chamber includes forming a first layer on the substrate using a plasma enhanced process and a gas compound of a chloride-based gas, a hydrogen gas, and an inert gas. The process chamber is then purged and the first layer is thermally soaked with a hydrogen-based precursor gas. The process chamber is then purged again and the process may be repeated with or without the plasma enhanced process until a certain film thickness is achieved on the substrate. 1. A method for forming a film on a substrate , comprising: forming a first layer on the substrate using a plasma enhanced process and a gas compound of a chloride-based gas, a hydrogen gas, and an inert gas; and', 'thermally soaking the first layer with at least a hydrogen-based precursor gas., 'depositing a film on the substrate with a process temperature of less than 500 degrees Celsius, by2. The method of claim 1 , further comprising:forming a second layer on the first layer without using the plasma enhanced process and using a gas compound of a chloride-based gas, a hydrogen gas, and an inert gas; andthermally soaking the second layer with at least a hydrogen-based precursor gas.3. The method of claim 1 , further comprising:forming a second layer on the first layer using the plasma enhanced process and a gas compound of a chloride-based gas, a hydrogen gas, and an inert gas; andthermally soaking the second layer with at least a hydrogen-based precursor gas.4. The method of claim 1 , further comprising:{'sup': '2', 'powering the plasma enhanced process with less than approximately 0.283 watts/cm.'}5. The method of claim 1 , further comprising:{'sup': '2', 'powering the plasma enhanced process with less than approximately 0.141 watts/cm.'}6. The method of claim 1 , further comprising:thermally soaking with the at least a hydrogen-based precursor gas for a time duration of approximately 100 milliseconds to approximately 10 seconds.7. The method of ...

Low Thickness Dependent Work-Function nMOS Integration For Metal Gate

Film stacks and methods of forming film stacks including a high-k dielectric layer on a substrate, a high-k capping layer on the high-k dielectric layer, an n-metal layer on the high-k capping layer and an n-metal capping layer on the n-metal layer. The n-metal layer having an aluminum rich interface adjacent the high-k capping layer.

Contact Conductive Feature Formation and Structure

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH METAL-SEMICONDUCTOR COMPOUND REGION

A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region. 1. A method for forming a semiconductor device structure , comprising:forming a fin structure over a semiconductor substrate;forming a gate stack over the fin structure;forming an epitaxial structure over the fin structure, wherein the epitaxial structure is adjacent to the gate stack;forming a dielectric layer over the epitaxial structure;forming an opening in the dielectric layer to expose the epitaxial structure; andapplying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.2. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the metal-containing material is applied using a chemical vapor deposition process.3. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the metal-containing material is applied using an atomic layer deposition process.4. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising forming a modified region in the epitaxial structure before the metal-containing material is applied on the epitaxial structure claim 1 , wherein the modified region has lower ...

MICROELECTRONIC DEVICES COMPRISING MANGANESE-CONTAINING CONDUCTIVE STRUCTURES, AND RELATED ELECTRONIC SYSTEMS

A microelectronic device comprises a first conductive material comprising copper, a conductive plug comprising tungsten in electrical communication with the first conductive material, and manganese particles dispersed along an interface between the first conductive material and the conductive plug. Related electronic systems and related methods are also disclosed. 1. A microelectronic device , comprising:a first conductive material;a second conductive material in electrical communication with the first conductive material;a barrier material around the second conductive material; andmanganese particles at an interface between the first conductive material and the barrier material, the first conductive material comprising a greater atomic percent of the manganese particles proximate the barrier material than in other portions of the first conductive material.2. The microelectronic device of claim 1 , further comprising a third conductive material in electrical communication with the second conductive material.3. The microelectronic device of claim 2 , wherein the third conductive material has a lateral dimension greater than a lateral dimension of the second conductive material.4. The microelectronic device of claim 2 , wherein the second conductive material is between the first conductive material and the third conductive material.5. The microelectronic device of claim 1 , wherein a thickness of the barrier material is non-uniform between the first conductive material and the second conductive material.6. The microelectronic device of claim 1 , wherein the first conductive material contacts the barrier material and a dielectric material.7. The microelectronic device of claim 1 , wherein an aspect ratio of the second conductive material is within a range from about 1:1 to about 30:1.8. (canceled)9. The microelectronic device of claim 1 , wherein the barrier material comprises titanium.10. A microelectronic device claim 1 , comprising:a barrier material in electrical ...

TECHNIQUES FOR MAKING INTEGRATED INDUCTORS AND RELATED SEMICONDUCTOR DEVICES, ELECTRONIC SYSTEMS, AND METHODS

In some embodiments, integrated inductors may be built using processes for forming interconnects of semiconductor devices without requiring additional process steps. Integrated inductor coils may be formed by, for example, shunting an overlying electrically conductive material, such as, for example, bond pad metals (e.g., aluminum and alloys thereof), to an underlying electrically conductive material, such as, for example, an uppermost layer of wiring formed using Damascene processes (e.g., utilizing copper and alloys thereof), without vias to interconnect the two materials. In some embodiments, integrated inductors formed utilizing such processes may have a symmetric spiral design. 1. A semiconductor device , comprising:a substrate comprising a semiconductor material; and an electrically conductive material at an uppermost portion of an interconnect formed on the substrate;', 'another, different electrically conductive material in direct contact with portions of the electrically conductive material; and', 'an overpass/underpass region in which an electrically isolated portion of the electrically conductive material extends under another electrically isolated portion of the other electrically conductive material, a passivation material located between the electrically isolated portion of the portion of the electrically conductive material and the other portion of the other electrically conductive material., 'an integrated inductor comprising coils supported by the substrate, the coils comprising2. The semiconductor device of claim 1 , wherein the integrated inductor is free of vias between the electrically conductive material and the other electrically conductive material of the integrated inductor.3. The semiconductor device of claim 1 , wherein the electrically conductive material of the coils comprises a copper or copper alloy material and the other electrically conductive material comprises aluminum or aluminum alloy.4. The semiconductor device of claim 1 , ...

Hard Mask Removal Scheme

A method includes forming a barrier layer in a via hole and over a hard mask layer. The hard mask layer is disposed over a dielectric layer. The via hole is located through the dielectric layer and the hard mask layer. A filler layer is formed in the via hole and over the barrier layer. The filler layer and the hard mask layer are removed. A metal layer is formed in the via hole. 1. A method , comprising:forming a barrier layer in a via hole and over a hard mask layer, wherein the hard mask layer is disposed over a dielectric layer, and the via hole is located through the dielectric layer and the hard mask layer;forming a filler layer in the via hole and over the barrier layer;removing the filler layer and the hard mask layer; andforming a metal layer in the via hole.2. The method of claim 1 , wherein the via hole is located and above a via bottom metal layer and further comprising forming an etch stop layer over the via bottom metal layer.3. The method of claim 1 , further comprising forming the dielectric layer over the via bottom metal layer.4. The method of claim 1 , further comprising forming the via hole in the dielectric layer.5. The method of claim 1 , wherein the barrier layer is formed by a physical vapor deposition (PVD) or atomic layer deposition (ALD).6. The method of claim 1 , wherein the filler layer is formed by a chemical vapor deposition (CVD).7. The method of claim 1 , wherein the metal layer is deposited by an electroplating process.8. The method of claim 1 , further comprising forming a seed layer in the via hole prior to forming the metal layer.9. The method of claim 8 , wherein the seed layer is formed by physical vapor deposition (PVD).10. The method of claim 1 , further comprising polishing the metal layer.11. The method of claim 1 , wherein the filler layer comprises SiOCH.12. The method of claim 1 , wherein the metal layer comprises copper.13. A method claim 1 , comprising:forming a barrier layer in a via hole and over a hard mask layer, ...

METHOD OF FORMING A SEMICONDUCTOR DEVICE COMPRISING TITANIUM SILICON OXYNITRIDE

A method of making a semiconductor device includes forming a titanium nitride layer over a gate dielectric layer. The method further includes performing a silicon treatment on the titanium nitride layer to form at least one silicon monolayer over the titanium nitride layer. The method further includes driving silicon from the at least one silicon monolayer into the titanium nitride layer to form a TiSiON layer. 1. A method of making a semiconductor device , the method comprising:forming a titanium nitride layer over a gate dielectric layer;performing a silicon treatment on the titanium nitride layer to form at least one silicon monolayer over the titanium nitride layer; anddriving silicon from the at least one silicon monolayer into the titanium nitride layer to form a TiSiON layer.2. The method of claim 1 , wherein performing the silicon treatment comprises repeating the silicon treatment to form a plurality of silicon monolayers over the titanium nitride layer.3. The method of claim 1 , wherein performing the silicon treatment comprises performing the silicon treatment in the presence of a silicon-containing gas and a carrier gas.4. The method of claim 3 , wherein performing the silicon treatment comprises performing the silicon treatment in the presence of the carrier gas comprising at least one of helium claim 3 , argon claim 3 , neon or nitrogen gas.5. The method of claim 3 , wherein performing the silicon treatment comprise performing the silicon treatment in the presence of the silicon-containing gas comprising at least one of silane claim 3 , disilane or silicon tetrachloride.6. The method of claim 1 , wherein driving silicon into the titanium nitride layer comprises annealing the semiconductor device in the presence of oxygen gas or nitric oxide.7. The method of claim 1 , further comprising depositing an interfacial layer over a substrate claim 1 , wherein the interfacial layer is between the gate dielectric layer and the substrate.8. The method of claim 7 ...

ALIGNING CONDUCTIVE VIAS WITH TRENCHES

A method for forming conductive contacts on a wafer comprises forming a first hardmask, planarizing layer, second hardmask, and a layer of sacrificial mandrel material, and removing portions of the layer of sacrificial mandrel material to expose portions of the second hardmask and form a first and second sacrificial mandrel. Spacers are formed adjacent to the sacrificial mandrels. A filler material is deposited on the second hardmask, and a first mask is formed on the filler material. An exposed portion of the second sacrificial mandrel is removed to form a first cavity. The depth of the first cavity is increased. The first mask, portions of the first and second sacrificial mandrels, the filler material, portions of the second hardmask, the spacers, portions of the planarization layer and the first hardmask are removed. A second cavity is formed and the first and second cavities are filled with a conductive material. 1. A method for forming conductive contacts on a semiconductor wafer , the method comprising:forming a hardmask on an insulator layer, a planarizing layer on the hardmask and a layer of sacrificial mandrel material on the planarizing layer;removing portions of the layer of sacrificial mandrel material to expose portions of the planarizing layer and form a first sacrificial mandrel and a second sacrificial mandrel on the planarizing layer;depositing a layer of spacer material over the planarizing layer, the first sacrificial mandrel and the second sacrificial mandrel;depositing a first filler material over the layer of spacer material;patterning a first mask over the filler material;removing portions of the first filler material to expose a portion of the layer of spacer material over a portion of the first sacrificial mandrel and removing the mask;removing a portion of the layer of spacer material and an exposed portion of the first sacrificial mandrel to form a first cavity that exposes a portion of the planarizing layer;filling the first cavity with a ...

METAL CAP INTEGRATION BY LOCAL ALLOYING

A middle-of-line interconnect structure including copper interconnects and integral copper alloy caps provides effective electromigration resistance. A metal cap layer is deposited on the top surfaces of the interconnects. A post-deposition anneal causes formation of the copper alloy caps from the interconnects and the metal cap layer. Selective removal of unalloyed metal cap layer material provides an interconnect structure free of metal residue on the dielectric material layer separating the interconnects. 1. A fabrication method for integrating electrically conductive caps on interconnects , comprising:obtaining a structure including a dielectric layer having a top surface, a plurality of open-ended trenches extending within the dielectric layer, and interconnects comprising copper within the trenches, the interconnects having top surfaces that are substantially coplanar with the top surface of the dielectric layer;depositing a metal cap layer on the structure such that the metal cap layer directly contacts the top surfaces of the interconnects at a plurality of interfaces, the metal cap layer comprising at least one of titanium, ruthenium and cobalt;subjecting the structure to thermal annealing to form metal alloy caps comprising copper from the interconnects and at least one of titanium, ruthenium and cobalt at the interfaces from a portion of the metal cap layer while a residual portion of the metal cap layer remains non-alloyed, andselectively removing the non-alloyed residual portion of the metal cap layer from the structure;wherein the metal alloy caps exhibit a stoichiometry of at least one part titanium, ruthenium or cobalt per one part of copper.2. The method of claim 1 , wherein the interconnects consist essentially of copper.3. The method of claim 2 , wherein selectively removing the non-alloyed residual portion of the metal cap layer includes subjecting the structure to a wet etch.4. The method of claim 3 , wherein subjecting the structure to thermal ...

SIMULTANEOUS FORMATION OF LINER AND METAL CONDUCTOR

An integrated circuit device having a substrate including a dielectric layer is patterned with a set of conductive line trenches. Each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom. A metal fills the set of conductive line trenches, wherein the metal fill is created by an anneal and reflow process. A liner which is an alloy of the metal and a selected element formed at interfaces of the metal layer and a surface of the dielectric, created simultaneously with the metal fill by the anneal and reflow process. 1. An integrated circuit device comprising:a substrate including a dielectric layer patterned with a set of conductive line trenches, each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom;a metal filling the set of conductive line trenches, wherein the metal fill is created by an anneal and reflow process; anda liner which is an alloy of the metal and a selected element formed at interfaces of the metal layer and a surface of the dielectric, created simultaneously with the metal fill by the anneal and reflow process.2. The device as recited in wherein the metal layer is comprised of aluminum and the selected element is nitrogen.3. The device as recited in claim 2 , wherein the liner is comprised of an alloy selected from the group consisting of AlN and Al(N claim 2 , Si).4. The device as recited in claim 1 , wherein the metal fill is comprised of a metal selected from the group consisting of Al claim 1 , Co claim 1 , Ru claim 1 , Ir claim 1 , Rh claim 1 , and Ni.5. The device as recited in claim 1 , wherein the selected element is selected from the group consisting of N claim 1 , Si claim 1 , C claim 1 , and O.6. The device as recited in claim 1 , wherein the metal fill in the set of conductive lines trenches is coplanar with a top surface of the dielectric in field areas of the dielectric layer.7. The device as recited in wherein the ...

LOW-RESISTIVE, CMOS-COMPATIBLE, AU-FREE OHMIC CONTACT TO N-INP

A device includes an n-doped InP layer and an ohmic contact, in contact with the n-doped InP layer. The ohmic contact includes an annealed stack of at least three, or preferably four alternating layers of Si and Ni, such that: (i) the n-doped InP layer and one of the layers of the stack in contact with the n-doped InP layer are at least partly intermixed; and (ii) any two adjacent layers of the stack are at least partly intermixed. Related fabrication methods are also disclosed. 1. A device comprising:an n-doped InP layer; andan ohmic contact, in contact with the n-doped InP layer, wherein the ohmic contact comprises an annealed stack of at least a first layer of Ni on top of and in contact with the n-doped InP layer, a second layer of Si on top of and in contact with the first layer, a third layer of Ni on top of and in contact with the second layer, and a fourth layer of Si on top of and in contact with the third layer,whereinthe first layer and the second layer have, each, an average thickness that is substantially less than ⅕ an average thickness of each of the third layer and the fourth layer;the n-doped InP layer and one of the layers of the stack in contact therewith are at least partly intermixed; andany two adjacent layers of the stack are at least partly intermixed.2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. The device according to claim 1 , wherein the first layer and the second layer have claim 1 , each claim 1 , an average thickness that is equal to or less than ⅛ of the average thickness of the third layer and the fourth layer.7. The device according to claim 1 , wherein the ratio of Ni to Si in the annealed stack is substantially of 1:1.8. The device according to claim 1 , wherein a height of the stack is less than 80 nm as measured along a stacking direction thereof.9. The device according to claim 8 , wherein:a thickness of each of the first layer of Ni and the second layer of Si is 3 nm;a thickness of the third layer of Ni is 25 nm; anda ...

MOL INSITU PT REWORK SEQUENCE

The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an Oflash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia. 1. A device comprising:a semiconductor substrate;gate electrodes on the semiconductor substrate; spacers on each side of each gate electrode; and platinum-containing nickel silicide on the substrate adjacent each spacer, wherein the device is at least 99% free from platinum residues.2. The device according to claim 1 , further comprising nitride stress layers on and between the gate electrodes.3. The device according to claim 1 , wherein the platinum-containing nickel silicide is formed by:sputter depositing a layer of nickel (Ni)/platinum (Pt) from a Ni/Pt target on the substrate;performing a first RTA;wet stripping unreacted Ni;performing a second RTA;stripping unreacted Pt from the annealed Ni/Pt layer;treating the Pt stripped Ni/Pt layer with an oxygen plasma;cleaning the Ni/Pt layer with an SPM/APM clean; andstripping unreacted Pt from the cleaned Ni/Pt layer.4. The device according to claim 3 , wherein the unreacted Pt is stripped by applying Aqua Regia.5. The device according to claim 4 , wherein the spacers are etched and shaped concurrently with treating the Ni/Pt layer with the oxygen plasma.6. The device according to claim 5 , wherein the Ni/Pt layer is treated with the oxygen plasma at a temperature less than 400° C.7. The device according to claim 6 , wherein the Ni/Pt layer is treated with the oxygen plasma at a ...

FABRICATING METHOD OF COBALT SILICIDE LAYER COUPLED TO CONTACT PLUG

A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds. 1. A fabricating method of a cobalt silicide layer coupled to a contact plug , comprising:providing a substrate disposed within a chamber;performing a deposition process comprising forming a cobalt layer to cover the substrate when a temperature of the substrate is between 50° C. and 100° C., and a temperature of the chamber is between 300° C. and 350° C.; andafter the deposition process, performing an annealing process when a temperature of the substrate is between 300° C. and 350° C. to transform the cobalt layer into a cobalt silicide layer, wherein the duration of the annealing process is between 50 seconds and 60 seconds.2. The fabricating method of a cobalt silicide layer coupled to a contact plug of claim 1 , further comprising:after forming the cobalt silicide layer, performing a rapid thermal anneal process, wherein an operational temperature of the rapid thermal anneal process is between 600° C. and 650° C., and an operational time of the rapid thermal anneal process is between 30 seconds and 60 seconds.3. The fabricating method of a cobalt silicide layer coupled to a contact plug of claim 2 , further comprising:after the rapid thermal anneal process, removing the cobalt layer which is not transformed.4. The fabricating method of a cobalt silicide layer coupled to a contact plug of claim 1 , wherein during the annealing ...

Forming Self-Aligned Contact with Spacer First

Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided. 1. A method of forming self-aligned contacts , the method comprising the steps of:forming multiple gate sidewall spacers on a substrate;burying the gate sidewall spacers in a dielectric;forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed;forming the gates in the gate trenches;forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; andforming the self-aligned contacts in the contact trenches.2. The method of claim 1 , further comprising the steps of:forming a spacer material layer on the substrate; andpatterning the spacer material layer to form the gate sidewall spacers on the substrate.3. The method of claim 2 , wherein sidewall image transfer (SIT) is used to pattern the spacer material layer to form the gate sidewall spacers on the substrate.4. The method of claim 3 , further comprising the steps of:forming mandrels on the spacer material layer;forming composite SIT spacers on opposite sides of the mandrels, wherein the composite SIT spacers comprise i) first spacers on opposite sides of the mandrels and ...

MECHANISMS FOR CLEANING SUBSTRATE SURFACE FOR HYBRID BONDING

Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided. 1. A method for cleaning a surface of a semiconductor wafer for hybrid bonding , comprising:providing a semiconductor wafer, wherein the semiconductor wafer has a conductive pad embedded in an insulating layer and a metal oxide layer formed on a surface of the conductive pad;performing a plasma process to a surface of the semiconductor wafer;performing a cleaning process using a cleaning solution to the surface of the semiconductor wafer after the plasma process, wherein the metal oxide layer is reduced and metal-hydrogen bonds are formed on the surface of the conductive pad; andtransferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding.2. The method as claimed in claim 1 , wherein the cleaning solution comprises citric acid claim 1 , hydrofluoric acid (HF) claim 1 , or tetramethylammonium hydroxide (TMAH).3. The method as claimed in claim 2 , wherein the citric acid has a concentration in a range from about 0.25% to about 10%.4. The method as claimed in claim 2 , wherein the hydrofluoric acid (HF) has a concentration in a range from about 0.1% ...

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer. 1. An integrated circuit device comprising:a substrate;a landing pad on the substrate; anda through-via structure passing through the substrate and connected to the landing pad,the through-via structure including a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.2. The integrated circuit device of claim 1 , whereinthe through-via structure further includes a via insulation layer covering a sidewall of the second conductive barrier layer,the via insulation layer is spaced apart from the landing pad, andthe second conductive barrier layer contacts the landing pad.3. The integrated circuit device of claim 2 , whereinthe landing pad further includes a landing pad metal layer and a landing pad barrier layer,the landing pad metal layer is on the substrate,the landing pad barrier layer is on an upper surface and a sidewall of the landing pad metal layer,a lower surface of the first conductive barrier layer contacts the landing pad metal layer, anda lower surface of the second conductive barrier layer contacts the landing pad barrier layer.4. The integrated circuit device of claim 3 , wherein the second conductive barrier layer is spaced apart from the landing pad metal layer.5. The integrated circuit device of claim 3 , whereinthe lower surface of the first conductive barrier layer is positioned at a first distance from a first surface of the substrate,the lower surface of the second conductive ...

Method for Monitoring Generation of a Nickel Metal Silicide

Disclosed are a method for monitoring generation of a nickel metal silicide, comprising the steps: step 1, sequentially forming a first dielectric layer and a second polysilicon layer on the surface of a test silicon wafer; step 2, forming a nickel-platinum alloy on the surface of the second polysilicon layer; step 3, performing first annealing process to form a first nickel metal silicide having a molecular formula of Ni2Si; step 4, removing the unreacted nickel-platinum alloy remaining on the surface of the nickel metal silicide; and step 5, measuring the square resistance of the first nickel metal silicide to monitor the first annealing process. The stability and reliability of the monitoring result can be improved and misjudgment can be prevented.

BARRIER LAYER FOR COPPER INTERCONNECT

A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming a metal-containing layer in the dielectric layer, forming a barrier layer overlying the metal-containing layer, and performing a thermal process to form a metal oxide layer underlying the conductive layer. The metal oxide layer is a barrier layer formed at the boundary between the dielectric layer and the metal-containing layer. 1. A method , comprising:forming a dielectric layer overlying a substrate;forming an opening in the dielectric layer;forming a metal-containing layer overlying the opening;forming a barrier layer overlying the metal-containing layer;filling a conductive layer in the opening; andperforming a thermal process to form a metal oxide barrier layer underlying the conductive layer.2. The method of claim 1 , wherein the barrier layer has a resistivity less than about 60 μΩ/cm.3. The method of claim 1 , wherein the metal-containing layer has a crystal structure of face center cubic (FCC) structure.4. The method of claim 1 , wherein the barrier layer has a crystal structure of body center cubic (BCC) structure.5. The method of claim 1 , wherein the metal-containing layer is a CuMn layer claim 1 , a CuNb layer claim 1 , a CuTi layer claim 1 , a CuAl layer claim 1 , a CuCo layer claim 1 , a CuV layer claim 1 , a CuY layer claim 1 , a CuTc layer claim 1 , a CuRe claim 1 , or combinations thereof.6. The method of claim 1 , wheren the metal-containing layer is Cu-containing layer.7. The method of claim 6 , wherein the Cu-containing layer comprises an additive metal element including manganese (Mn) claim 6 , aluminum (Al) claim 6 , titanium (Ti) claim 6 , niobium (Nb) claim 6 , chromium (Cr) claim 6 , vanadium (V) claim 6 , yttrium (Y) claim 6 , technetium (Tc) claim 6 , rhenium (Re) claim 6 , cobalt (Co) claim 6 , or combinations thereof.8. The method of claim 1 , wherein the barrier layer is a tantalum (Ta) layer.9. The method of claim 8 , ...

SEMICONDUCTOR DEVICE INCLUDING AN INSULATING LAYER, AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

A method of forming a semiconductor device, includes depositing first copper material by physical vapor deposition (PVD) on an insulating layer and on a barrier material formed on a sidewall and a bottom of a trench in the insulating layer, heating the first copper material to reflow the first copper material into the trench, depositing a second copper material by PVD on the insulating layer, on the barrier material and on the first copper material, and heating the second copper material to reflow the second copper material into the trench such that the second copper material is formed on the first copper material and on the sidewall of the trench, the first and second copper materials forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than 1ppm. 1. A method of forming a semiconductor device , comprising;depositing first copper material by physical vapor deposition (PVD) on an insulating layer and on a barrier material formed on a sidewall and a bottom of a trench in the insulating layer;heating the first copper material to reflow the first copper material into the trench;depositing a second copper material by PVD on the insulating layer, on the barrier material and on the first copper material; and{'b': '1', 'heating the second copper material to reflow the second copper material into the trench such that the second copper material is formed on the first copper material and on the sidewall of the trench, the first and second copper materials forming a copper layer in the trench, an amount of sulfur and chlorine in the copper layer being less than ppm.'}2. The method of claim 1 , further comprising:performing chemical mechanical polishing (CMP) to planarize an upper surface of the copper layer and an upper surface of the insulating layer.3. The method of claim 1 , wherein after the heating of the second copper material claim 1 , an elevation of an upper surface of the second copper material is less than an elevation ...

Interconnection structures for semiconductor devices and fabrication methods of forming interconnection structures for semiconductor devices utilizing to-be-etched layer made of porous low-K dielectric material and a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N))

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate; and forming a to-be-etched layer made of porous low dielectric constant material on one surface of the semiconductor substrate. The method also includes forming a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) on the to-be-etched layer; and etching the first hard mask layer to have patterns corresponding to positions of subsequently formed openings. Further, the method includes forming the plurality of openings without substantial undercut between the to-be-etched layer and the first hard mask layer in the to-be-etched layer using the first hard mask layer as an etching mask; and forming a conductive structure in each of the openings. 1. A method for fabricating a semiconductor structure , comprising:providing a substrate;forming a to-be-etched layer made of a porous low-K dielectric material on one surface of the substrate;forming a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) on the to-be-etched layer;etching the first hard mask layer to have patterns corresponding to positions of subsequently formed a plurality of openings;forming the plurality of openings in the to-be-etched layer using the first hard mask layer as an etching mask without substantial undercut between the to-be-etched layer and the first hard mask layer; andforming a conductive structure in each of the openings.2. The method according claim 1 , after forming the first hard mask layer claim 1 , further including:forming a second hard mask layer on the first hard mask layer.3. The method according to claim 2 , after forming the second hard mask layer claim 2 , further including:forming a capping layer on the second hard mask layer.4. The method according to claim 1 , wherein etching the first hard mask layer further includes;forming a photoresist layer on the first hard mask layer;patterning the photoresist layer to have patterns ...

REMOVING METAL FILLS IN A WIRING LAYER

The present invention relates to a semiconductor manufacturing method, a mask forming method and a semiconductor structure. According to one aspect of the invention, a semiconductor manufacturing method is provided, comprising: forming a metal wiring layer on a semiconductor substrate, the metal wiring layer comprising dielectrics and metal wires and metal FILLs within the dielectrics; removing the metal FILLs in the metal wiring layer completely to form the metal wiring layer without the metal FILLs. With the technical solution according to embodiments of the invention, undesirable influences due to metal FILLs will be eliminated. 1. A semiconductor manufacturing method , comprising:forming a metal wiring layer on a semiconductor substrate, the metal wiring layer comprising dielectrics and metal wires and metal FILLs within the dielectrics; andremoving the metal FILLs in the metal wiring layer completely to form the metal wiring layer without the metal FILLs.2. The method according to claim 1 , wherein claim 1 , removing the metal FILLs in the metal wiring layer completely comprises:removing the dielectrics adjacent to the metal FILLs in all regions containing the metal FILLs within the metal wiring layer;removing the metal FILLs in the regions containing the metal FILLs;filling trenches formed by removing the metal FILLs and the dielectrics in the regions containing the metal FILLs with additional dielectrics; andpolishing the additional dielectrics.3. The method according to claim 1 , wherein claim 1 , removing the metal FILLs in the metal wiring layer completely comprises:removing the metal FILLs in all regions containing the metal FILLs within the metal wiring layer to form trenches;filling the trenches with additional dielectrics; andpolishing the additional dielectrics.4. The method according to claim 2 , further comprising: annealing the additional dielectrics.5. The method according to claim 2 , wherein claim 2 , the metal FILLs are removed through wet ...

PURE BORON FOR SILICIDE CONTACT

A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×10to about 5×10atoms/cm. 1. A method of making a semiconductor device , the method comprising:forming epitaxial contacts on opposing sides of a gate over a substrate;removing portions of the epitaxial contacts to form trench contact patterns in the epitaxial contacts; and{'sup': 21', '22', '2, 'depositing an amorphous boron layer within the trench contact patterns, the amorphous boron layer forming interfacial layers within the epitaxial contacts, and the interfacial layers each comprising boron in an amount in a range from about 5×10to about 5×10atoms/cm.'}2. The method of claim 1 , further comprising filling the trench contact patterns with a high-k dielectric material and a conductive metal to form trench contacts claim 1 , and wherein the high-k dielectric material forms a liner within the trench contact.3. The method of claim 1 , wherein removing portions of the epitaxial contacts comprises forming recesses within the epitaxial contacts.4. The method of claim 2 , wherein the trench contacts each have sidewalls and a base claim 2 , and both the sidewalls and the base contact the interfacial layers.5. The method of claim 1 , wherein the interfacial layers each have a thickness in a range from about 0.5 to about 2 nm.6. The method of claim 2 , wherein the high-k dielectric material is HfO claim 2 , ZrO claim 2 , AlO claim 2 , TiO claim 2 , LaO claim 2 , SrTiO claim 2 , LaAlO claim 2 , YO claim 2 , a pervoskite oxide claim 2 , or any combination thereof.7. The method of claim 1 , wherein the amorphous boron layer comprises substantially pure boron.8. The method of claim 1 , wherein removing portions of the epitaxial ...

OVERLAY MARKS, METHODS OF FORMING THE SAME, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME

In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed. 1. A method of fabricating a semiconductor device using an overlay mark , the method comprising:preparing a substrate having a circuit area, a vernier rule area, and a main rule area;forming gate patterns in the circuit area of the substrate;forming a lower interlayer insulating layer on the substrate to surround the gate patterns;forming a contact pattern between the gate patterns in the circuit area and a mirror pattern in the lower interlayer insulating layer in the main rule area;forming a lower stopping insulating layer on the gate patterns, the contact pattern, the mirror pattern, and the lower interlayer insulating layer;forming an upper interlayer insulating layer on the lower stopping insulating layer;forming a trench mask on the upper interlayer insulating layer, wherein the trench mask includes a trench opening vertically aligned with the contact pattern in the circuit area and a main pattern in the main rule area;forming a sacrificial layer on the trench mask; andforming a via mask on the sacrificial layer, wherein the via mask includes a via opening vertically aligned with the trench opening in the circuit area and a vernier pattern in the vernier rule area.2. The method according to claim 1 , wherein the main pattern has main slits vertically aligned with the mirror pattern.3. The method according to claim 2 , wherein the vernier pattern has ...

INTEGRATED CIRCUITS HAVING DEVICE CONTACTS AND METHODS FOR FABRICATING THE SAME

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto. A contact opening exposing the metal silicide is formed to the semiconductor device. A conductive material is deposited within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact. A self-aligned conductive material is deposited within the contact to form a conductive plug that at least partially fills the contact seam void, and a metallization layer is deposited overlying the contact. 1. A method for fabricating an integrated circuit , the method comprising:providing a semiconductor device with a metal silicide electrically coupled thereto;forming a contact opening to the semiconductor device and exposing the metal silicide;depositing a conductive material within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact;depositing a self-aligned conductive material within the contact to form a conductive plug that at least partially fills the contact seam void; anddepositing a metallization layer overlying the contact.2. The method of claim 1 , wherein the self-aligned conductive material comprises a tungsten-based claim 1 , nickel-based claim 1 , or silver-based self-aligned conductive material.3. The method of claim 1 , wherein the self-aligned conductive material comprises tungsten cobalt phosphide (WCoP) claim 1 , tungsten cobalt boride (WCoB) claim 1 , tungsten nitride (WN) claim 1 , nickel tungsten phosphide (NiWP) claim 1 , nickel phosphide (NiP) claim 1 , nickel titanium (NiTi) claim 1 , or silver (Ag)-based nanoclusters.4. The method of claim 1 , wherein the contact comprises tungsten.5. The method of claim 1 , wherein forming the conductive plug comprises filling about 50 to ...

EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region. 1. A method of forming a contact silicide extension comprising:forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; andforming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.2. The method of claim 1 , wherein the forming the undercut region below the dielectric layer and above the source-drain region comprises:forming a liner layer on the gate spacer, and the source-drain region;forming the dielectric layer on the liner layer and the gate stack;forming the contact trench in the dielectric layer, the bottom of the contact trench exposing a portion of the liner layer; andremoving a portion of the liner layer, the portion of the liner layer extending from directly below the bottom of the contact trench and below the dielectric layer to the gate spacer.3. The method of claim 2 , wherein the removing the portion of the liner layer comprises:performing an isotropic wet etching process to remove the portion of the liner layer selective to the dielectric layer, the source-drain region, ...

STRUCTURE AND FORMATION METHOD OF INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE

Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region. 1. A method for forming a semiconductor device structure , comprising:forming a dielectric layer over a semiconductor substrate;forming an opening in the dielectric layer to expose a conductive element;forming a conductive layer over the conductive element;modifying an upper portion of the conductive layer using a plasma operation to form a modified region; andforming a conductive plug over the modified region to fill the opening, wherein the conductive plug is substantially made of a single-element metal, and the conductive plug is in direct contact with the modified region.2. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the plasma operation comprises applying nitrogen-containing plasma on the conductive layer so that the upper portion of the conductive layer is modified to become the modified region.3. The method for forming a semiconductor device structure as claimed in claim 1 , wherein plasma used in the plasma operation comprises nitrogen-containing plasma claim 1 , carbon-containing plasma claim 1 , oxygen-containing plasma claim 1 , or a combination thereof.4. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the conductive layer is selectively deposited on the conductive element.5. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the conductive layer is formed on a sidewall and a bottom of the opening.6. The method for forming a semiconductor ...

METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area. 110.-. (canceled)11. A finFET device , comprising:a first gate structure and a second gate structure on a semiconductor substrate;a first active area on one end of said first and second gate structures;a second active area on the other end of said first and second gate structures; anda self-aligned TS structure configured to operatively couple said first active area to said second active area.12. The finFET device of claim 11 , wherein said self-aligned TS structure is a borderless pass-through structure that provides a pass-through route between said first and second active areas.13. The finFET device of claim 11 , further comprising a CB structure above at least one of said gate structures claim 11 , wherein said first CB structure is formed offset relative to said gate structure in a manner such that said first CB structure does not contact the TS structure.14. The finFET device of claim 13 , wherein CB structure is a self-aligned via defined in one direction by the borders of an M0 metal formation.15. The finFET device of claim 11 , wherein said first active area claim 11 , said second active area and said TS structure each are defined by at least one of a plurality of cut masks.16. The finFET device of claim 11 , further comprising a CA structure claim 11 , wherein said CA structure is formed to make contact with said TS structure and said first active area.17. The finFET device of claim 11 , ...