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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 5981. Отображено 100.
23-02-2012 дата публикации

Method and structure for forming high-k/metal gate extremely thin semiconductor on insulator device

Номер: US20120043623A1
Принадлежит: International Business Machines Corp

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

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15-03-2012 дата публикации

Bipolar junction transistor

Номер: US20120061802A1
Принадлежит: Individual

A bipolar junction transistor includes a semiconductor island on an insulating substrate; an emitter and at least one of a collector and sub collector within the semiconductor island, the emitter and the at least one of the collector and the sub collector being of a first conductivity type; a base within the semiconductor island separating the emitter and the at least one of the collector and the sub collector, the base being of a second conductivity type; a base contact region within the semiconductor island, the base contact region being of the second conductivity type; and a connecting base region adjacent the base within the semiconductor island and connecting the base to the base contact region while not directly contacting the emitter, the connecting base region being of the second conductivity type with a doping concentration less than a doping concentration of the base contact region.

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26-04-2012 дата публикации

Reacted Conductive Gate Electrodes and Methods of Making the Same

Номер: US20120098054A1

A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

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03-05-2012 дата публикации

Semiconductor device

Номер: US20120104494A1
Автор: Hiroki Fujii
Принадлежит: Renesas Electronics Corp

A field-effect transistor ( 142 ) includes a lowly p-doped region 110 formed on a surface of a substrate ( 102 ), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110 , and a device isolation insulating film 132 and device isolation insulating film 134 . Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134 ; and in the n-doped source region 114 , the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.

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17-05-2012 дата публикации

Source tip optimization for high voltage transistor devices

Номер: US20120119265A1

The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

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05-07-2012 дата публикации

Transistor and method for forming the same

Номер: US20120168879A1
Автор: Fumitake Mieno

The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.

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12-07-2012 дата публикации

Metal-oxide-semiconductor device having trenched diffusion region and method of forming same

Номер: US20120175702A1
Принадлежит: LSI Corp

An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

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12-07-2012 дата публикации

Semiconductor device

Номер: US20120175703A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A source region and a drain region are disposed in a substrate. A gate insulating film is disposed on the substrate. A gate electrode is disposed on the gate insulating film. The gate electrode may include a first gate portion adjacent to the source region and a second gate portion adjacent to the drain region. The first and second gate portions have different work functions from each other.

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19-07-2012 дата публикации

Stressed channel fet with source/drain buffers

Номер: US20120181549A1
Принадлежит: International Business Machines Corp

A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

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09-05-2013 дата публикации

Method for manufacturing semiconductor device and semiconductor device

Номер: US20130113037A1
Принадлежит: Unisantis Electronics Singapore Pte Ltd

A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

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30-05-2013 дата публикации

Semiconductor device

Номер: US20130134510A1
Автор: Shinichiro Yanagi
Принадлежит: Renesas Electronics Corp

In the interior of a semiconductor substrate having a main surface, a first p − epitaxial region is formed, a second p − epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n + buried region is formed between the first p − epitaxial region and the second p − epitaxial region in order to electrically isolate the regions. A p + buried region having a p-type impurity concentration higher than that of the second p − epitaxial region is formed between the n + buried region and the second p − epitaxial region. The p + buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.

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13-06-2013 дата публикации

Deep trench embedded gate transistor

Номер: US20130146992A1
Принадлежит: International Business Machines Corp

A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the source to the drain.

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20-06-2013 дата публикации

METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE

Номер: US20130153929A1

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers. 1. A semiconductor device comprising:a gate structure present on a substrate, the gate structure comprising a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region;a spacer adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region; anda raised source region and a raised drain region present adjacent to the spacer, wherein the raised source region and the raised drain region are separated from the gate conductor by the extension portion of the spacer.2. The semiconductor device of claim 1 , wherein the substrate is composed of a semiconductor material that is selected from the group consisting of Si claim 1 , strained Si claim 1 , SiC claim 1 , SiGe claim 1 , SiGeC claim 1 , Si alloys claim 1 , Ge claim 1 , Ge alloys claim 1 , GaAs claim 1 , InAs claim 1 , InP claim 1 , and combinations thereof.3. The semiconductor device of claim 1 , wherein the substrate is comprised of a semiconductor layer having a thickness of less than 10 nm that is present on a dielectric layer.4. The semiconductor ...

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25-07-2013 дата публикации

Lateral double diffused mos transistors and methods of fabricating the same

Номер: US20130187226A1
Автор: Sung Kun Park
Принадлежит: SK hynix Inc

A lateral double diffused MOS transistor including substrate of a first conductivity type, drift region of a second conductivity type and body region of the first conductivity type disposed in the substrate, source region of the second conductivity type disposed in the body region, drain region of the second conductivity type disposed in the drift region, isolation layer disposed in the drift region to surround sidewalls of the drain region, gate insulation layer and gate electrode sequentially stacked generally on the body region, first field plate extending from the gate electrode to overlap the drift region and to overlap a portion of the isolation layer, second field plate disposed above the isolation layer spaced apart from the first field plate, and coupling gate disposed above the isolation layer generally between the drain region and the second field plate, wherein the coupling gate is electrically connected to the second field plate.

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25-07-2013 дата публикации

Semiconductor device with high voltage transistor

Номер: US20130189820A1
Автор: Masashi Shima
Принадлежит: Fujitsu Semiconductor Ltd

A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions; implanting first impurity ions of a first conductivity type to form first, second and third wells; implanting second impurity ions of the first conductivity type to form first and second channel regions; implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region; forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region; forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and implanting fourth impurity ions of the second conductivity type to form second drain/source regions.

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15-08-2013 дата публикации

Stepped-source ldmos architecture

Номер: US20130207186A1
Автор: Jun Cai
Принадлежит: Fairchild Semiconductor Corp

A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

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26-09-2013 дата публикации

Methods of forming replacement gate structures with a recessed channel

Номер: US20130248985A1
Принадлежит: Globalfoundries Inc

Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

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17-10-2013 дата публикации

Semiconductor device including a mos transistor and production method therefor

Номер: US20130273703A1
Принадлежит: Unisantis Electronics Singapore Pte Ltd

It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar.

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07-11-2013 дата публикации

Semiconductor Device with Drain-End Drift Diminution

Номер: US20130292764A1
Принадлежит: FREESCALE SEMICONDUCTOR INC

A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

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26-12-2013 дата публикации

Methods for fabricating integrated circuits with drift regions and replacement gates

Номер: US20130344669A1
Принадлежит: Globalfoundries Inc

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

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06-02-2014 дата публикации

Tunnel field effect transistor

Номер: US20140035040A1

A TFET transistor includes an intrinsic channel, source and drain extension regions, source and drain conductive regions, a gate surmounting the channel and laid out such that an end of the channel is not covered by the gate. The transistor includes a first arrangement for forming an isolating space between the sides of the gate and the source conductive region including a first and a second dielectric spacer. The extension region has a thickness strictly greater than that of the channel such that the extension region has an increased thickness opposite the gate dielectric layer. The first face of the first spacer is in contact with the side of the gate followed by the side of the gate dielectric layer such that the first face covers the whole of the side of the layer.

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27-03-2014 дата публикации

SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS OF FABRICATION

Номер: US20140084369A1
Принадлежит:

Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance. 1. A semiconductor device comprising: a gate electrode formed over a channel region of the substrate, and', 'a recessed source interface and a recessed drain interface formed on the substrate at opposite sides of the gate electrode;, 'a substrate comprising'}a first spacer and a second spacer formed on opposite sidewalls of the gate electrode, wherein a portion of the recessed source interface extends laterally beneath the bottom surface of the first spacer, and a portion of the recessed drain interface extends laterally beneath the bottom surface of the second spacer; a first epitaxial region formed over the recessed source interface, and', 'a first cap layer formed over the first epitaxial region, wherein a portion of the first cap layer is formed between the first epitaxial region and the bottom surface of the first spacer; and, 'a source region comprising'} a second epitaxial region formed over the recessed drain interface, and', 'a second cap layer formed over the second epitaxial region, wherein a portion of the second cap layer is formed between the second epitaxial region and the bottom surface of the second spacer., 'a drain region comprising'}2. The semiconductor device of claim 1 , wherein the first and second epitaxial regions each comprises silicon and carbon doped with phosphorus.3. The semiconductor device of claim 2 , wherein the wherein the first and second epitaxial regions each comprises silicon havinga carbon concentration in the range of 0.5 atomic % to 4 atomic %, and ...

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01-01-2015 дата публикации

REPLACEMENT CHANNEL

Номер: US20150001584A1
Принадлежит:

The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure. 1. A semiconductor device , comprising:a continuous strain inducing or high mobility layer arranged within a substrate and configured to provide increased charge carrier mobility relative to the substrate;a gate arranged over the continuous strain inducing or high mobility layer, and separated from the continuous strain inducing or high mobility layer by a dielectric;a channel region arranged within the continuous strain inducing or high mobility layer and arranged under the gate; anddoped source/drain regions arranged within the continuous strain inducing or high mobility layer and laterally separated from one another by the channel region; anda low mobility layer separating an underside of the gate from the channel region.2. The semiconductor device of claim 1 , wherein the doped source/drain regions comprise raised source/drain regions claim 1 , which extend above an upper surface of the substrate.3. The semiconductor device of claim 2 , wherein the raised source/drain regions have a diamond shaped cross-section along a channel length direction of the continuous strain inducing or high mobility layer.4. The semiconductor device of claim 2 , wherein the raised source/drain regions have a hexagonal shaped cross-section along a channel length direction of the continuous strain inducing or high mobility layer.5. The semiconductor device of claim 2 , wherein the raised source/drain regions have an octagonal shaped cross-section ...

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01-01-2015 дата публикации

Transistor device with improved source/drain junction architecture and methods of making such a device

Номер: US20150001640A1
Принадлежит: Globalfoundries Inc

One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

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01-01-2015 дата публикации

ESD PROTECTION ELEMENT

Номер: US20150001679A1
Автор: SAWAHATA Kouichi
Принадлежит: RENESAS ELECTRONICS CORPORATION

In an aspect of the present invention, an ESD (Electrostatic Discharge) protection element includes a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; and current control resistances provided for a plurality of current paths from a second terminal to the collector diffusion layer through the emitter diffusion layer, respectively. The bipolar transistor further includes a base diffusion region connected with the second terminal through a first resistance which is different from the current control resistances. 1. An ESD (Electrostatic Discharge) protection element comprising:a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; andcurrent control resistances provided for a plurality of current paths from a second terminal to said collector diffusion layer through said emitter diffusion layer, respectively,wherein said bipolar transistor further comprises a base diffusion region connected with said second terminal through a first resistance which is different from said current control resistances.2. The ESD protection element according to claim 1 , wherein said emitter diffusion layer further comprises a plurality of first contacts connected with said second terminal through said current control resistances claim 1 , respectively claim 1 , and said base diffusion layer further comprises a plurality of second contacts connected with said second terminal through a plurality of said first resistances.3. The ESD protection element according to claim 1 , wherein said emitter diffusion layer comprises a plurality of emitter diffusion sub layers claim 1 , in each of which at least one contact is formed.4. The ESD protection element according to claim 3 , wherein said base diffusion layer is partially separated in a base width direction by an element separation region.5. The ESD protection element according to claim 1 , further ...

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06-01-2022 дата публикации

SEMICONDUCTOR STRUCTURE IMPLEMENTING SERIES-CONNECTED TRANSISTOR AND RESISTOR AND METHOD FOR FORMING THE SAME

Номер: US20220005734A1
Автор: CHUANG Ching-Cheng
Принадлежит:

A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure. 1. A semiconductor structure , comprising:a gate electrode and a resistor electrode disposed in a semiconductor substrate, wherein a dopant concentration of the gate electrode is greater than a dopant concentration of the resistor electrode;an isolation structure disposed in the semiconductor substrate, wherein the gate electrode and the resistor electrode are separated by the isolation structure;a source/drain (S/D) region disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode; anda conductive structure disposed in the semiconductor substrate and over the isolation structure, wherein the conductive structure is in direct contact with the S/D region and the resistor electrode.2. The semiconductor structure of claim 1 , wherein a width of the resistor electrode is greater than a width of the gate electrode.3. The semiconductor structure of claim 1 , further comprising:a well region disposed in the semiconductor substrate, wherein the resistor electrode is disposed over the well region, and a conductivity type of the well region is the same as a conductivity type of the S/D region. ...

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06-01-2022 дата публикации

STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) DEVICES

Номер: US20220005936A1
Принадлежит:

A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type. 1. A memory device , comprising:a vertical stack of an n-type vertical transport field effect transistor (VT FET) and a p-type vertical transport field effect transistor (VT FET) on a surface of a substrate, including:a conductive strap electrically connecting a source/drain of the n-type VT FET to a source/drain of the p-type VT FET;a liner segment and a bottom spacer on the substrate, wherein the liner segment and the bottom spacer separate a lower gate structure from the surface of the substrate; andan upper gate structure electrically connected to the lower gate structure by a common electrical contact perpendicular to the surface of the substrate.2. The memory device of claim 1 , further comprising a bottom source/drain layer below the vertical stack of the n-type VT FET and the p-type VT FET.3. The memory device of claim 2 , further comprising a top source/drain on the vertical stack of the n-type VT FET and the p-type VT FET.4. The memory device of claim 3 , further comprising a portion of an interlayer dielectric (ILD) layer separating the conductive strap from the common electrical ...

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05-01-2017 дата публикации

FINFET Devices and Methods of Forming

Номер: US20170005011A1
Принадлежит:

In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region. 1. A device comprising: a first channel region comprising a first material of a first fin on a substrate,', 'a first epitaxial source/drain region and a second epitaxial source/drain region each in a respective first recess in the first material, the first channel region being disposed between the first epitaxial source/drain region and the second epitaxial source/drain region, and', 'a first gate stack on the first channel region; and, 'a first p-type transistor comprising a second channel region comprising a second material of a second fin on the substrate, the second material being a different material from the first material,', 'a third epitaxial source/drain region and a fourth epitaxial source/drain region each in a respective second recess in the second material, the second channel region being disposed between the third epitaxial source/drain region and the fourth epitaxial source/drain region, and', 'a second gate stack on the second channel region., 'a second p-type transistor comprising2. The device of claim 1 , wherein a depth of the first recess is greater than a depth of the ...

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05-01-2017 дата публикации

DISTRIBUTED DECOUPLING CAPACITOR

Номер: US20170005087A1
Принадлежит:

The electrical device includes a plurality of fin structures, the plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. Each of the plurality of fin structures having substantially a same geometry. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures, wherein the decoupling capacitor is present underlying the power line to the semiconductor fin structures. 1. An electrical device comprising:a plurality of fin structures including at least one decoupling fin structure and at least one semiconductor fin structure;at least one semiconductor device including a channel region present in the at least one semiconductor fin structure, a gate structure present on the channel region of the at least one semiconductor fin structure, and source and drain regions present on source and drain region portions of the at least one semiconductor fin structure; andat least one decoupling capacitor including the at least one decoupling fin structure, wherein the decoupling capacitor is present underlying the power line to the at least one semiconductor fin structure.2. The electrical device of claim 1 , wherein the at least one decoupling fin structure provides as a first electrode of the at least one decoupling capacitor.3. The electrical device of further comprising a second electrode for the at least one decoupling capacitor provided by a metal contact.4. The ...

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05-01-2017 дата публикации

Semiconductor Devices and Method for Forming Semiconductor Devices

Номер: US20170005091A1
Принадлежит:

A semiconductor device includes a semiconductor laminar structure arranged on a semiconductor substrate. The semiconductor laminar structure includes a first doping region of a field effect transistor structure and at least a part of a body region of the field effect transistor structure. The body region has a first conductivity type and the first doping region has a second conductivity type. The semiconductor device further includes an electrically conductive contact structure providing an electrical contact to the first doping region of the field effect transistor structure and to the body region of the field effect transistor structure at one or more sidewalls of the semiconductor laminar structure. 1. A semiconductor device , comprising:a semiconductor laminar structure arranged on a semiconductor substrate, the semiconductor laminar structure comprising a first doping region of a field effect transistor structure and at least a part of a body region of the field effect transistor structure, wherein the body region comprises a first conductivity type and wherein the first doping region comprises a second conductivity type; andan electrically conductive contact structure providing an electrical contact to the first doping region of the field effect transistor structure and to the body region of the field effect transistor structure at one or more sidewalls of the semiconductor laminar structure.2. The semiconductor device of claim 1 , wherein a lateral dimension of the semiconductor laminar structure is less than 200 nm.3. The semiconductor device of claim 1 , wherein a height of the semiconductor laminar structure is at least 300 nm.4. The semiconductor device of claim 1 , wherein the electrically conductive contact structure extends along the semiconductor laminar structure from a first sidewall of the semiconductor laminar structure to a second sidewall of the semiconductor laminar structure.5. The semiconductor device of claim 1 , wherein a lateral dimension ...

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05-01-2017 дата публикации

Nanowire Semiconductor Device Structure and Method of Manufacturing

Номер: US20170005168A1
Принадлежит:

A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the source region. In an embodiment the modification may be performed by implanting either amorphizing dopants or lifetime reducing dopants. Alternatively, the source may be epitaxially grown with a different materials or process conditions to reduce the lifetime of minority carriers within the source region. 1. A method of manufacturing a semiconductor device , the method comprising:forming a nanowire over a substrate, wherein the nanowire comprises a source, a drain, and a channel between the source and the drain, wherein the source has a first conductivity type and the drain has the first conductivity type;covering a portion of the drain; andimplanting a first minority carrier lifetime reducing dopant into the source after the covering the portion of the drain.2. The method of claim 1 , wherein the implanting the first minority carrier lifetime reducing dopant further comprises implanting an amorphizing dopant into the source.3. The method of claim 2 , further comprising annealing the source to recrystallize the source into a polycrystalline material.4. The method of claim 1 , wherein the implanting the first minority carrier lifetime reducing dopants implants the first minority carrier lifetime reducing dopants at a non-perpendicular angle.5. The method of claim 1 , wherein the first minority carrier lifetime reducing dopants directly reduce a lifetime of minority carriers within the source.6. The method of claim 1 , wherein the nanowire has a longitudinal axis parallel with the substrate.7. The method of claim 1 , wherein the nanowire has a longitudinal axis perpendicular with the substrate.8. A method of manufacturing a semiconductor device claim 1 , the method comprising:forming a source region, a drain region, and a channel region within a nanowire; andmodifying the source region to reduce a minority ...

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05-01-2017 дата публикации

Ultra High Voltage Device

Номер: US20170005194A1
Принадлежит:

According to an embodiment, a semiconductor device is provided. The device includes: The second region has a greater curvature than the first region. The device includes: an N-type epitaxy layer; a P-well in the N-type epitaxy layer; a drain in the N-type epitaxy layer; a source in the P-well; and a bulk in the P-well and in contact with the source, wherein the bulk has a greater area in the second region than in the first region. 1. A semiconductor device having a first region and a second region , the second region having a greater curvature than the first region , the device comprising:an N-type epitaxy layer in the first region and the second region;a P-well in the N-type epitaxy layer;a first N+ diffusion layer in the N-type epitaxy layer;a second N+ diffusion layer in the P-well; anda P+ diffusion layer in the P-well and separated from the second N+ diffusion layer, wherein a distance between the P+ diffusion layer and the second N+ diffusion layer is smaller in the second region than in the first region.2. The device of claim 1 , further comprising a shallow trench isolation (STI) region separating the P+ diffusion layer from the second N+ diffusion layer.3. The device of claim 2 , wherein the STI region is smaller in the second region than in the first region.4. The device of claim 2 , wherein the STI region from the first region to the second region is continuous and gradually decreases.5. The device of claim 1 , further comprising an N-well in the N-type epitaxy layer claim 1 , the first N+ diffusion layer being in the N-well.6. The device of claim 1 , further comprising:a polysilicon layer over a portion of the P-well; anda gate oxide between the polysilicon layer and the P-well.7. The device of claim 1 , further comprising:a P-type substrate below the N-type epitaxy layer; andan insulator between the N-type epitaxy layer and the P-type substrate.8. A semiconductor device having a first region and a second region claim 1 , the second region having a ...

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05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20170005196A1
Принадлежит:

A semiconductor device includes a substrate, a liner, and an epitaxy structure. The substrate has a recess. The liner is disposed in the recess. The liner is denser than the substrate. The epitaxy structure is disposed in the recess. The liner is disposed between the epitaxy structure and the substrate. 1. A semiconductor device , comprising:a substrate having a recess;a liner disposed in the recess, wherein the liner is denser than the substrate; andan epitaxy structure disposed in the recess, wherein the liner is disposed between the epitaxy structure and the substrate.2. The semiconductor device of claim 1 , wherein the liner has at least one round corner.3. The semiconductor device of claim 2 , wherein a radius of curvature of the round corner is about 20 nm to about 60 nm.4. The semiconductor device of claim 1 , further comprising:a gate stack disposed on or above the substrate and adjacent to the recess.5. The semiconductor device of claim 4 , further comprising:an isolation structure disposed in the substrate, wherein the recess is disposed between the isolation structure and the gate stack.6. The semiconductor device of claim 4 , wherein two of the recesses are respectively disposed at opposite sides of the gate stack.7. The semiconductor device of claim 4 , wherein the substrate has a doping region disposed between the recess and the gate stack.8. The semiconductor device of claim 1 , wherein the liner and the substrate are made of substantially the same material.9. The semiconductor device of claim 1 , further comprising:a silicide region disposed on or above the epitaxy structure.10. A method for manufacturing a semiconductor device claim 1 , comprising:forming a recess in a substrate;performing a surface treatment on an inner surface of the recess to form a liner thereon, wherein the liner and the substrate are made of substantially the same material; andforming an epitaxy structure in the recess and on the liner.11. The method of claim 10 , wherein the ...

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05-01-2017 дата публикации

AMBIPOLAR SYNAPTIC DEVICES

Номер: US20170005281A1
Принадлежит:

Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices. 1. An ambipolar synaptic device comprising:an organic semiconductor layer including traps configured for trapping, de-trapping and/or recombination of both electrons and holes;a gate operatively associated with the organic semiconductor layer;a first structure configured for injecting both electrons and holes into the semiconductor layer;an inorganic channel layer;source and drain regions operatively associated with the inorganic channel layer;a first dielectric layer between the organic semiconductor layer and the inorganic channel layer, anda second dielectric layer between the gate and the organic semiconductor layer,the inorganic channel layer and the first dielectric layer being configured such that conductivity of the inorganic channel layer is modulated depending on the polarity and amount of charge stored in the organic semiconductor layer.210-. (canceled)11. The ambipolar synaptic device of claim 1 , wherein the first structure includes a transition metal-oxide adjoining the organic semiconductor layer.12. The ambipolar synaptic device of claim 1 , further including a self-assembled monolayer of gold nanoparticles adjoining the first dielectric layer.13. An ambipolar synaptic device comprising:a semiconductor layer including a channel;a gate operatively associated with the semiconductor layer;a source/drain structure comprised of a highly doped region of a first doping type confined within a highly doped ...

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07-01-2016 дата публикации

ESD Protection with Asymmetrical Bipolar-Based Device

Номер: US20160005730A1
Принадлежит: Freescale Semiconductor, Inc.

An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device. 1. A method of fabricating an electrostatic discharge (ESD) protection device in a semiconductor substrate , the semiconductor substrate comprising a semiconductor layer having a first conductivity type , the method comprising:performing a first well implantation procedure to implant dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions, wherein the inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices of the ESD protection device;performing a second well implantation procedure to implant dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices;wherein the first and second well implantation procedures are configured such that conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device and such that conduction of the second bipolar ...

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07-01-2016 дата публикации

Semiconductor Structure with Dielectric-Sealed Doped Region

Номер: US20160005807A1
Принадлежит:

Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the substrate material. Trenches are formed in the substrate and lined with a seal dielectric prior to filling the trenches with semiconductor material. Preferably, the trenches are overfilled and a CMP process planarizes the overfill material. An epitaxial layer can be grown atop the trenches after planarization, if desired. 1. A structure comprising:a semiconductor substrate;a first source/drain material disposed in the semiconductor substrate;a first dielectric liner disposed between the first source/drain material and the semiconductor substrate, the first dielectric liner having a bottom portion disposed along a bottom of the first source/drain material and having a sidewall portion disposed along a sidewall of the first source/drain material, a top surface of the first source/drain material, a top surface of the sidewall portion of the first dielectric liner, and a top surface of the semiconductor substrate being co-planar;a semiconductor layer over the top surface of the first source/drain material and the top surface of the semiconductor substrate; anda gate structure over the semiconductor layer, wherein a first portion of the semiconductor layer and at least a portion of the first source/drain material form a first source/drain, and a second portion of the semiconductor layer forms a channel.2. The structure of claim 1 , wherein a portion of the semiconductor layer underlying the gate structure consists essentially of a same material as a portion of the semiconductor substrate underlying the gate structure and in the top surface of the semiconductor substrate.3. The structure of further comprising:a second source/drain material disposed in the semiconductor substrate, the first source/drain material being disposed on a first side of the gate structure, and the second source/drain material being disposed ...

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07-01-2016 дата публикации

GATE DIELECTRIC PROTECTION FOR TRANSISTORS

Номер: US20160005828A1
Принадлежит:

At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge. 1. (canceled)2. (canceled)3. A method for forming a transistor , comprising:forming a source region on a substrate, comprising forming forming a first n+ dopant region on a p-type substrate and forming a first contact region above said first n+ dopant region;forming a drain region on said substrate adjacent said active gate region, comprising forming a second n+ dopant region on said p-type substrate and forming a second contact region above said second n+ dopant region;forming an active gate region on said substrate adjacent said source region, comprising forming a first gate oxide region above said p-type substrate between said first and second n+ dopant regions and forming a first polysilicon conductor region above said first gate oxide region; andforming a first inactive gate region on said substrate in parallel to said active gate region, comprising forming a second gate oxide region above said p-type substrate adjacent said first n+ dopant region, forming a second polysilicon conductor region above second first gate oxide region, and electrically coupling said second polysilicon conductor region to said first polysilicon conductor region, wherein said source region, said drain region, said active gate region, and said first inactive gate region comprise said transistor, ...

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07-01-2016 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20160005865A1
Принадлежит: Renesas Electronics Corp

The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP 1 formed on the substrate. The upper surface of the semiconductor layer EP 1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP 1.

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04-01-2018 дата публикации

VERTICAL TRANSISTOR WITH VARIABLE GATE LENGTH

Номер: US20180005895A1
Принадлежит:

A method of forming a vertical transistor includes forming a first pair of fins on a substrate; forming a second pair of fins on the substrate; forming a first trench in the substrate and interposed between each one of the first pair of fins; forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench; forming a first semiconductor structure interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region; and forming a second semiconductor structure interposed between each one of the second pair of fins, the second semiconductor structure having a first gate region interposed between a second source region and a second drain region. 1. A method of forming a vertical transistor , the method comprising:forming a first pair of fins on a substrate;forming a second pair of fins on the substrate;forming a first trench in the substrate and interposed between each one of the first pair of fins;forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench;forming a doped source or a doped drain at a base of the first trench in direct contact with the substrate;forming a doped source or a doped drain at a base of the second trench in direct contact with the substrate, wherein the doped source or the doped drain at the base of the second trench is deeper than the doped source or the doped drain at the base of the first trench;forming a first semiconductor structure interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region; andforming a second semiconductor structure interposed between each one of the second pair of fins, the second semiconductor ...

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07-01-2016 дата публикации

Bidirectional Two-Base Bipolar Junction Transistor Devices, Operation, Circuits, and Systems with Diode-Mode Turn-On and Collector-Side Base Driven

Номер: US20160006430A1
Принадлежит: Ideal Power Inc.

Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low. 92. A method for switching a power semiconductor device which includes both an n-type emitter/collector region , and also a p-type base contact region , on both first and second surfaces of a p-type semiconductor die , and which has an ON state and an OFF state , comprising the steps of:at turn-on, when an external voltage difference is applied between the emitter/collector regions, shorting the more positive one of the emitter/collector regions together with the base contact region on the same one of the surfaces, to thereby conduct current with a diode voltage drop characteristic of a p-n junction between the emitter/collector region and the semiconductor die; and thereafterin the ON state, flowing base current through the base contact region which is nearer the more positive one of the emitter/collector regions, without flowing base current through the other of the base contact regions;wherein the base contact region on the first surface is not electrically connected to the base contact region on the second surface, except through the semiconductor die itself;and wherein the emitter/collector region on the first surface is not directly electrically connected to the emitter/collector region on the second surface, except through the semiconductor die itself;whereby bidirectional switching is ...

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04-01-2018 дата публикации

INTERCONNECTS FOR VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS

Номер: US20180006023A1
Принадлежит:

Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure further includes an interconnect located in a trench defined in the semiconductor layer. The interconnect is coupled with the source/drain region or the gate electrode of the vertical-transport field-effect transistor, and may be used to couple the source/drain region or the gate electrode of the vertical-transport field-effect transistor with a source/drain region or a gate electrode of another vertical-transport field-effect transistor. 1. A structure comprising:a first vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin; andan interconnect located in a trench defined in the semiconductor layer, the interconnect coupled with the source/drain region or the gate electrode of the first vertical-transport field-effect transistor.2. The structure of wherein the interconnect is coupled with the source/drain region of the first vertical-transport field-effect transistor claim 1 , further comprising:a second vertical-transport field-effect transistor having a source/drain region located in the semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin,wherein the source/drain region of the first vertical-transport field-effect transistor is coupled by the interconnect with the source/drain region or the gate electrode of the second vertical-transport field-effect transistor.3. The structure of ...

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07-01-2021 дата публикации

SEMICONDUCTOR DEVICE WITH FIN TRANSISTORS AND MANUFACTURING METHOD OF SUCH SEMICONDUCTOR DEVICE

Номер: US20210005607A1
Автор: Matsumoto Koichi
Принадлежит: SONY CORPORATION

A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor. 1each of the first conductivity type transistor and the second conductivity type includes agate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode;the gate insulating film is made of a high dielectric constant material; andoffset spacers are (a) between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or (b) offset spacers in the first conductivity type transistor have a different thickness than offset spacers in the second conductivity type transistor.. A semiconductor device including a first conductivity type transistor and a second conductivity type transistor, wherein: This application is a continuation of U.S. Ser. No. 16/443,319 filed Jun. 17, 2019, which is a division of U.S. patent application Ser. No. 15/588,072 filed May 5, 2017, now U.S. Pat. No. 10,373,955 issued Aug. 6, 2019, which is a continuation of U.S. patent application Ser. ...

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07-01-2021 дата публикации

Integrated Assemblies Comprising Voids Between Active Regions and Conductive Shield Plates, and Methods of Forming Integrated Assemblies

Номер: US20210005611A1
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies. 1. Integrated memory comprising:a wordline;a shield plate;an access device comprising first and second diffusion regions and a channel region, the first and second diffusion regions and the channel region being arranged vertically so that the channel region is between the first and second diffusion regions; andwherein the access device is adjacent the wordline and the shield plate so that a part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween and that a part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween; the first insulating region comprising an insulative material, and the second insulating region comprising a void.2. The integrated memory of wherein the void fills an entirety of the second insulating region.3. The integrated memory of wherein the insulative material comprises silicon dioxide.4. The integrated memory of further comprising:a bitline in an electrical connection with first diffusion region; anda storage element in an electrical ...

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04-01-2018 дата публикации

Subtractive vfet process flow with replacement metal gate and metallic source/drain

Номер: US20180006118A1
Принадлежит: International Business Machines Corp

A method and a semiconductor device includes a substrate, and a first device type formed on the substrate, the first device type including an active channel region including a first fin, the first fin including a first fin width which is narrower than a second fin width above and below the active channel region. A second device type can be formed on the same substrate, the second device type includes a second active channel region including a second fin, the second fin including a first fin width which is the same as the second fin width both above and below the second active channel region.

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04-01-2018 дата публикации

TUNNELING FIELD EFFECT TRANSISTOR

Номер: US20180006143A1
Автор: Pawlak Bartlomiej Jan
Принадлежит:

A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region. 1. A tunneling field effect transistor device comprising a drain region , a source region and a gate region , the device comprising:a semiconductor substrate;a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above said substrate, said body having an axis that is oriented substantially perpendicular to an upper surface of said substrate, said body having two side surfaces and an upper surface, said body extending a full length of said drain region, said gate region and said source region, wherein said first semiconductor material is part of said drain region;a second semiconductor material positioned above at least a portion of said gate region and above said source region, wherein said second semiconductor material defines said channel region;a third semiconductor material positioned above said second semiconductor material and above at least a portion of said gate region and above said source region, said third semiconductor material being doped with a second type of dopant material that is opposite ...

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04-01-2018 дата публикации

Radiation Sensor, Method of Forming the Sensor and Device Including the Sensor

Номер: US20180006181A1
Принадлежит:

A semiconductor device includes a semiconductor structure formed on a substrate, a gate formed on a first side of the semiconductor structure, and a charge collector layer formed on a second side of the semiconductor structure. 1. A semiconductor device , comprising:a semiconductor structure formed on a substrate;a gate formed on a first side of the semiconductor structure; anda charge collector layer formed on a second side of the semiconductor structure.2. The semiconductor device of claim 1 , wherein the semiconductor device comprises a radiation sensor claim 1 , andwherein the semiconductor structure comprises a fin structure comprising semiconductor material, and the charge collector layer comprises a charge collector dielectric layer.3. The semiconductor device of claim 2 , wherein the fin structure comprises a pair of fin structures.4. The semiconductor device of claim 2 , further comprising:a gate dielectric formed between the gate and the first side of the fin structure.5. The semiconductor device of claim 4 , wherein the gate comprises a metal gate and the gate dielectric comprises a high-k dielectric material.6. The semiconductor device of claim 2 , wherein the charge collector dielectric layer comprises an oxide layer.7. The semiconductor device of claim 2 , wherein the radiation sensor comprises a modified vertical field effect transistor (VFET) claim 2 , a threshold voltage of the modified VFET shifting as a function of radiation dose claim 2 , and the gate being operable to sense the shifting of the threshold voltage.8. The semiconductor device of claim 2 , further comprising:a first source/drain region formed on the substrate, the fin structure being formed on the first source/drain region.9. The semiconductor device of claim 8 , further comprising:a second source/drain region formed on an upper surface of the fin structure.10. The semiconductor device of claim 8 , further comprising:a bottom spacer formed on the first source/drain region, the gate ...

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07-01-2021 дата публикации

LOW-RESISTANCE TOP CONTACT ON VTFET

Номер: US20210005735A1
Принадлежит:

A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region. 1. A method for forming a semiconductor device , the method comprising:forming a bottom source/drain region on a semiconductor substrate;forming a vertical semiconductor fin including a bottom end that contacts the semiconductor substrate and is in electrical communication with the bottom source/drain region;forming a top source/drain region on a top end of the vertical semiconductor, the top source/drain region separated from the semiconductor substrate by the vertical semiconductor fin;forming an electrically conductive cap on an outer surface of the top source/drain region; andforming an electrically conductive contact via in ohmic connection with the electrically conductive cap to establish an electrically conductive path from the contact via to the bottom source/drain region.2. The method of claim 1 , wherein the top source/drain region is also formed on sidewalls of the vertical semiconductor fin.3. The method of claim 2 , wherein forming the electrically conductive cap comprises:depositing an electrically conductive film on the outer surface of the top source/drain region; andperforming a temperature anneal process to form the electrically conductive cap by converting the electrically conductive film into a binary compound of a semiconductor material included in the top source/drain region.4. The method of claim 3 , wherein the electrically conductive film is also formed on the sidewalls of the vertical semiconductor fin.5. The method of ...

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07-01-2021 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20210005736A1
Автор: HONG Ying
Принадлежит:

Provided is a method of manufacturing a semiconductor device, the method including: forming an insulating layer on a substrate; forming a trench, which extends in a first direction parallel with the plane of the substrate, to a preset depth in the insulating layer in a second direction perpendicular to the plane of the substrate; forming a plurality of amorphous silicon strips, which extend from the inside of the trench in the second direction intersecting with the first direction, in parallel in a first direction; forming a spacer on a side of the amorphous silicon strip by using an insulating material layer; and crystallizing the amorphous silicon strip by heat treatment, wherein crystal nucleation sites are formed in the amorphous silicon layer in the trench, and a polycrystalline silicon layer is formed by lateral grain growth in a longitudinal direction of the amorphous silicon strip from the crystal nucleation site. 1. A method of manufacturing a semiconductor device , the method comprising:forming an insulating layer on a substrate;forming a trench to a preset depth in the insulating layer on the substrate;forming a plurality of amorphous silicon strips, which extend from the inside of the trench to intersect with the trench, in parallel in a longitudinal direction of the trench;forming spacers on sides of each of the amorphous silicon strips to protect an edge of each of the amorphous silicon strips; andcrystallizing the amorphous silicon strips by heat treatment to form polycrystalline silicon layers, wherein a crystal nucleation site is formed in each of the amorphous silicon layers in the trench, and then lateral grain growth is induced from each of the crystal nucleation site in a longitudinal direction of each of the amorphous silicon strips.2. The method of claim 1 , further comprising:forming a capping layer covering the amorphous silicon layer before the heat treatment.3. The method of claim 1 , wherein the forming the spacer on both sides of the ...

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07-01-2021 дата публикации

SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION AND TRENCH CAPACITOR

Номер: US20210005760A1
Принадлежит:

A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure. 1. A semiconductor device , comprising: a semiconductor surface layer including majority carrier dopants of a first conductivity type, and', 'a buried layer including majority carrier dopants of a second conductivity type;, 'a semiconductor structure, includinga metallization structure extending over the semiconductor surface layer; and a first trench extending through the semiconductor structure to the buried layer,', 'a first dielectric liner extending along a sidewall of the first trench from the semiconductor surface layer to the buried layer,', 'a first polysilicon including majority carrier dopants of the first conductivity type, the first polysilicon extending inside the first dielectric liner and filling the first trench to a top side of the semiconductor surface layer,', 'a first deep doped region including majority carrier dopants of the second conductivity type, the first deep doped region surrounding the first trench and extending from the semiconductor surface layer to the buried layer, and', 'first conductive features of the metallization structure that connect the first polysilicon to the first deep doped region., 'an isolation structure, including2. The semiconductor device of claim 1 , further comprising a capacitor claim 1 , the capacitor including:a second trench extending through the semiconductor structure to the buried layer,a second dielectric liner extending along a sidewall of the second trench from the semiconductor surface ...

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02-01-2020 дата публикации

Methods of Forming Contact Features in Field-Effect Transistors

Номер: US20200006160A1
Принадлежит:

A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches. 1. A method comprising:forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, wherein the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature;forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature;removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench;removing a remaining portion of the dummy contact feature to form a second trench; andforming a metal S/D contact in the first and the second trenches.2. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature includes selectively etching the dummy contact feature relative to the ILD layer.3. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature exposes the first epitaxial S/D feature claim 1 , such that the metal S/D contact directly contacts the first epitaxial S/D feature but not the second epitaxial S/D feature.4. The method of claim 1 , wherein the dummy contact feature includes a dielectric material different from a dielectric material of the ILD layer.5. The method of claim 4 , wherein the dummy contact feature includes a carbon-containing dielectric material.6. The method of claim 1 , ...

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02-01-2020 дата публикации

LEAVE-BEHIND PROTECTIVE LAYER HAVING SECONDARY PURPOSE

Номер: US20200006330A1
Принадлежит: Intel Corporation

Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer. 1. An integrated circuit , comprising:a first transistor device region including a first gate structure, the first gate structure including a gate electrode, a gate dielectric, and a layer, the layer between the gate electrode and gate dielectric and being compositionally different from the gate electrode and gate dielectric, and the layer including first and second portions, the first and second portions being collinear with each other and compositionally different from one another; anda second transistor device region including a contact structure, the contact structure being one of a second gate structure, a source contact, or a drain contact;wherein the first and second transistor device regions are arranged in a vertically stacked configuration, and a conductive interconnect extends downward from the gate electrode of the first gate structure to contact the contact structure.2. The integrated circuit of claim 1 , wherein the first gate structure is part of a non-planar transistor that includes a body of ...

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02-01-2020 дата публикации

TECHNIQUES FOR FORMING GATE STRUCTURES FOR TRANSISTORS ARRANGED IN A STACKED CONFIGURATION ON A SINGLE FIN STRUCTURE

Номер: US20200006331A1
Принадлежит: Intel Corporation

A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited. 1. An integrated circuit structure , comprising:a fin structure including an upper portion having opposing sidewalls and a lower portion having opposing sidewalls, wherein the sidewalls of the upper portion are collinear with the sidewalls of the lower portion;a first gate structure on the upper portion, the first gate structure including a first gate electrode and a first gate dielectric between the first gate electrode and the upper portion; anda second gate structure on the lower portion, the second gate structure including a second gate electrode and a second gate dielectric between the second gate electrode and the lower portion;wherein the first gate structure is different from the second gate structure with respect to at least one of composition and gate dielectric thickness.2. The integrated circuit structure of claim 1 , wherein the first gate electrode includes a first metal and the second gate electrode includes a second metal that is ...

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02-01-2020 дата публикации

CHANNEL STRUCTURES WITH SUB-FIN DOPANT DIFFUSION BLOCKING LAYERS

Номер: US20200006332A1
Принадлежит:

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack. 1. An integrated circuit structure , comprising:a fin comprising a lower fin portion and an upper fin portion, the lower fin portion comprising a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type, and the upper fin portion comprising a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer;an isolation structure along sidewalls of the lower fin portion;a gate stack over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side;a first source or drain structure at the first side of the gate stack; anda second source or drain structure at the second side of the gate stack, the first and second source or drain structures doped to a second conductivity type opposite the first conductivity type.2. The integrated circuit structure of claim 1 , wherein the top surface of the isolation structure is above a bottom surface of the second semiconductor layer.3. The integrated circuit structure of claim 1 , wherein the lower fin portion ...

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02-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20200006336A1
Принадлежит:

A method of manufacturing a semiconductor device includes forming a first transistor structure and a second transistor structure on a substrate, wherein source/drain structures of the first transistor structure and the second transistor structure are merged. The first and second transistor structures are separated by etching the source/drain structures. 1. A method of manufacturing a semiconductor device , comprising:forming a first transistor structure and a second transistor structure on a substrate, wherein source/drain structures of the first transistor structure and the second transistor structure are merged; andseparating the first and second transistor structures by etching the merged source/drain structures.2. The method according to claim 1 , further comprising before separating the first and second transistors:forming a silicide layer over the merged source/drain structures;forming an interlayer dielectric layer over the merged source/drain structures; andforming a gap in the interlayer dielectric layer in a region between the first and the second transistors.3. The method according to claim 2 , wherein the silicide layer is formed before forming the interlayer dielectric layer.4. The method according to claim 2 , wherein the silicide layer is formed after the gap is formed.5. The method according to claim 2 , wherein the gap exposes a portion of the source/drain structures claim 2 , and the portion of source/drain structures that is exposed is etched during the etching the source/drain structures.6. The method according to claim 2 , further comprising forming an etch stop layer over the silicide layer.7. A method of manufacturing a semiconductor device including a plurality of fin field effect transistors (FinFETs) claim 2 , the method comprising:forming a first fin structure and a second fin structure over a substrate, the first and second fin structures extending in a first direction in plan view,forming an isolation insulating layer over the substrate ...

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03-01-2019 дата публикации

ELECTROSTATIC DISCHARGE PROTECTION SEMICONDUCTOR DEVICE

Номер: US20190006348A1
Принадлежит:

An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other. 1. An ESD protection semiconductor device , comprising:a substrate;a gate set disposed on the substrate;a plurality of source fins and a plurality of drain fins disposed in the substrate respectively at two sides of the gate set, wherein the source fins and the drain fins comprise a first conductivity type;at least a first doped fin disposed in the substrate at one side of the gate set the same as the source fins and being spaced apart from the source fins, wherein the first doped fin comprises a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other; anda plurality of isolation structures disposed in one of the drain fins to define at least a second doped fin in the one of the drain fins, wherein the second doped fin is electrically connected to the first doped fin.2. The ESD protection semiconductor device according to claim 1 , wherein the source fins are electrically connected to a ground pad claim 1 , and the drain fins are electrically connected to an IO pad.3. The ESD protection semiconductor device according to claim 1 , wherein the source fins and the drain fins extend along a first direction and are ...

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03-01-2019 дата публикации

NON-PLANAR SEMICONDUCTOR DEVICE HAVING DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME

Номер: US20190006362A1
Принадлежит:

Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins. 120.-. (canceled)21. An integrated circuit structure , comprising:a first fin comprising silicon, the first fin having a lower fin portion and an upper fin portion, the first fin of an NMOS device;a second fin comprising silicon, the second fin having a lower fin portion and an upper fin portion, the second fin of a PMOS device;a first dielectric layer comprising silicon and oxygen, the first dielectric layer directly on sidewalls of the lower fin portion of the first fin;a second dielectric layer comprising silicon and oxygen, the second dielectric layer directly on sidewalls of the lower fin portion of the second fin;an insulating layer comprising nitrogen, the insulating layer over the first dielectric layer and over the second dielectric layer, and the insulating layer continuous over the first dielectric layer and the second dielectric layer;a dielectric fill material directly on the insulating layer, wherein the dielectric fill material comprises silicon and oxygen;a first gate electrode over a top ...

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03-01-2019 дата публикации

HYBRID FINFET STRUCTURE

Номер: US20190006392A1
Принадлежит:

A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin. 1. A semiconductor device comprising:a first fin field effect transistor (FinFET) device, the first FinFET device comprising a plurality of fins extending from a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins; anda second FinFET device, the second FinFET device comprising a substantially planar fin extending from the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.2. The semiconductor device of claim 1 , further comprising:a third gate structure traversing across the substantially planar fin and spaced from the second gate structure; anda contact, the contact landing on the epitaxial layer formed over the substantially planar fin between the second and third gate structures.3. The semiconductor device of claim 1 , wherein the substantially planar fin has a width in a direction parallel to the second gate structure that is at least 100 nm.4. The semiconductor device of claim 1 , wherein the epitaxial layer of semiconductor material includes silicon phosphorous (SiP).5. ...

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02-01-2020 дата публикации

CIRCUIT AND LAYOUT FOR RESISTIVE RANDOM-ACCESS MEMORY ARRAYS HAVING TWO BIT LINES PER COLUMN

Номер: US20200006429A1
Автор: McCollum John L.
Принадлежит: Microsemi SoC Corp.

A layout is presented for a ReRAM memory cell array including rows and columns of ReRAM cells, each ReRAM cell is in a row and column of ReRAM cells. Each ReRAM cell includes a ReRAM device. A first transistor is coupled between the ReRAM device and a first bit line associated with the column containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the ReRAM device and a second bit line associated with the column containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell. 1. A layout for a ReRAM memory array including rows and columns of ReRAM cells , each ReRAM cell in a row and column of ReRAM cells comprising:a ReRAM device;a first FinFET transistor coupled between the ReRAM device and a first bit line associated with the column containing the ReRAM cell, the first FinFET transistor having a gate coupled to a first word line associated with the row containing the ReRAM cell;a second FinFET transistor coupled between the ReRAM device and a second bit line associated with the column containing the ReRAM cell, the second FinFET transistor having a gate coupled to a second word line associated with the row containing the ReRAM cell;wherein each column includes a first group of fins and a second group of fins separate from the first group of fins;the first FinFET transistor for each memory cell in every column of the array is formed on the first group of fins associated with that column; andthe second FinFET transistor for each memory cell in every column of the array is formed on the second group of fins associated with that column.2. The ReRAM memory array of further including a sense amplifier for each column of the array claim 1 , the sense amplifier for each column in the array coupled to one of the first and second bit lines associated with its column in the array ...

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02-01-2020 дата публикации

Semiconductor devices and methods for forming semiconductor devices

Номер: US20200006483A1
Принадлежит:

A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate. 1. A semiconductor device comprising:a source region of a field effect transistor of the semiconductor device having a first conductivity type;a body region of the field effect transistor having a second conductivity type; anda drain region of the field effect transistor having the first conductivity type and having a buried portion,wherein the source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device,wherein at least a part of the body region is located between the source region and the drain region,wherein the drain region extends from the body region to a drain contact portion of the drain region, the drain contact portion located at a surface of the semiconductor substrate, wherein a current path of the field effect transistor extends in the drain region from the body region through the buried portion to the drain contact portion,wherein the buried portion of the drain region is located beneath a spacer doping region, wherein the spacer doping region is located within the semiconductor substrate,wherein the spacer doping region and the body region ...

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02-01-2020 дата публикации

Integrated Circuit Structure With Non-Gated Well Tap Cell

Номер: US20200006484A1
Принадлежит:

The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell; forming first fin active regions in the well tape cell and second fin active regions in the IC cell; forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tape cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tape cell. 1. A method , comprising:receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell;forming first fin active regions in the well tape cell and second fin active regions in the IC cell;forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active regions of the well tape cell;forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions;epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; andforming contacts landing on the first S/D features within the well tape cell.2. The method of claim 1 , wherein the epitaxially growing further includes epitaxially growing second S/D features on the second S/D regions of the second fin active regions within the IC cell using the gate stacks to constrain the epitaxially growing.3. The method of claim 1 , further comprising ...

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02-01-2020 дата публикации

III-V SEGMENTED FINFET FREE OF WAFER BONDING

Номер: US20200006485A1
Принадлежит:

A technique relates to a semiconductor device. A stack is formed of alternating layers of inserted layers and channel layers on a substrate. Source or drain (S/D) regions are formed on opposite sides of the stack. The inserted layers are converted into oxide layers. Gate materials are formed on the stack. 1. A semiconductor device comprising:a stack of alternating layers of oxide layers and channel layers on a substrate, the oxide layers having an indented middle portion;source or drain (S/D) regions on opposite sides of the stack; andgate materials on the stack.2. The semiconductor device of claim 1 , wherein the oxide layers separate the channel layers in the stack.3. The semiconductor device of claim 1 , wherein the oxide layers comprise AlGaO.4. The semiconductor device of claim 1 , wherein a buffer layer is between the stack and the substrate.5. The semiconductor device of claim 4 , wherein the buffer layer comprises GaPAs.6. The semiconductor device of claim 1 , wherein the gate materials comprise a high-k dielectric material.7. The semiconductor device of claim 6 , wherein the gate materials further comprise a gate metal on the high-k dielectric material.8. The semiconductor device of claim 1 , wherein the channel layers comprise GaAs.9. The semiconductor device of claim 1 , wherein the oxide layers are non-conductive.10. The semiconductor device of claim 1 , wherein the channel layers are conductive.11. A method of forming a semiconductor device claim 1 , the method comprising:forming a stack of alternating layers of oxide layers and channel layers on a substrate, the oxide layers having an indented middle portion;forming source or drain (S/D) regions on opposite sides of the stack; andforming gate materials on the stack.12. The method of claim 11 , wherein the oxide layers separate the channel layers in the stack.13. The method of claim 11 , wherein the oxide layers comprise AlGaO.14. The method of claim 11 , wherein a buffer layer is formed between the ...

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02-01-2020 дата публикации

High Surface Dopant Concentration Formation Processes and Structures Formed Thereby

Номер: US20200006486A1
Принадлежит:

Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region. 1. A structure comprising: a surface dopant region at an upper surface of the source/drain region, the surface dopant region comprising a peak dopant concentration proximate the upper surface of the source/drain region; and', 'a remainder portion of the source/drain region having a source/drain dopant concentration, the peak dopant concentration being at least an order of magnitude greater than the source/drain dopant concentration;, 'an active area on a substrate, the active area comprising a source/drain region, the source/drain region comprisinga dielectric layer over the active area; anda conductive feature through the dielectric layer to the active area and contacting the source/drain region at the upper surface of the source/drain region.2. The structure of claim 1 , wherein the surface dopant region comprises a dopant concentration gradient that decreases from the peak dopant concentration at a rate of 1 decade of concentration per 5 nm or less.3. The structure of claim 2 , wherein ...

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03-01-2019 дата публикации

Intermetallic Doping Film with Diffusion in Source/Drain

Номер: US20190006465A1
Принадлежит:

A method includes etching a substrate to form a first semiconductor strip. A first dummy gate structure is formed over a first channel region of the first semiconductor strip. First and second recesses are etched in the first semiconductor strip on either side of a first dummy gate. An intermetallic doping film is formed in the first recess and the second recess. A dopant of the intermetallic doping film is diffused into the first semiconductor strip proximate the recesses. Source/drain regions are epitaxially grown in the recesses. A device includes semiconductor strips and a plurality of gate stacks. A first epitaxial source/drain region is interposed between a first two of the plurality of gate stacks. A first dopant diffusion area surrounds the first epitaxial source/drain region and has a first concentration of a first dopant greater than a second concentration of the first dopant outside the first dopant diffusion area. 1. A method comprising:etching a substrate to form a first semiconductor strip;forming a first dummy gate structure over a first channel region of the first semiconductor strip, the first dummy gate structure being perpendicular to the first semiconductor strip;etching a first recess in the first semiconductor strip on a first side of the first dummy gate structure;etching a second recess in the first semiconductor strip on a second side of the first dummy gate structure;forming a first intermetallic doping film in the first recess and the second recess;diffusing a first dopant of the first intermetallic doping film into the first semiconductor strip proximate the first recess and into the first semiconductor strip proximate the second recess;epitaxially growing a source/drain region in the first recess; andepitaxially growing a source/drain region in the second recess.2. The method of claim 1 , wherein the first dopant is selected from a group consisting of phosphorous claim 1 , arsenic claim 1 , antimony claim 1 , bismuth claim 1 , or a ...

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03-01-2019 дата публикации

MOSFET WITH ULTRA LOW DRAIN LEAKAGE

Номер: US20190006466A1
Принадлежит:

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region. 1. A method for forming a semiconductor , comprising:etching one or more recesses through a passivation layer on a substrate, and into the substrate, wherein each of the one or more recesses undercut a portion of the passivation layer to form passivation layer overhangs; anddepositing a dielectric material on exposed portions of the passivation layer and a bottom surface of at least one of the one or more recesses to form a dielectric pad, wherein there is an exposed portion of the substrate between the dielectric pad and the sidewalls of the recess.2. The method as recited in claim 1 , further comprising forming a source/drain region on the dielectric pad in the at least one of the one or more recesses claim 1 , wherein the source/drain region forms on the exposed portion of the substrate between the dielectric pad and the sidewalls of the recess claim 1 , wherein the source/drain region is made of a II-VI material.3. The method as recited in claim 2 , wherein the II-VI material is selected from the group consisting of zinc oxide (ZnO) claim 2 , zinc sulfide (ZnS) claim 2 , zinc selenide (ZnSe) claim 2 , cadmium sulfide (CdS) claim 2 , and cadmium telluride (CdTe).4. The method as recited in claim 1 , wherein the dielectric material is formed by an evaporation process claim 1 , and the passivation layer overhangs prevent deposition of the dielectric material on the sidewalls of the recesses.5. The method as recited in claim 4 , wherein the dielectric material ...

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03-01-2019 дата публикации

SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE AND A MANUFACTURING METHOD THEREOF

Номер: US20190006469A1
Принадлежит:

Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×10/cmor more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure. 1. A semiconductor device comprising:a fin structure on a substrate including a negative channel field-effect transistor (nFET) region;a gate structure formed on the fin structure; and{'sup': 21', '3, 'a source/drain structure formed adjacent to the gate structure, the source/drain structure being formed with an epitaxial layer n-type impurity, the concentration of the n-type impurity is about 1.8×10/cmor more, and the outer portion of the source/drain structure including silicon (Si) and germanium (Ge), and the inner portion of the source/drain structure including Si but not Ge, and'}wherein an inclined surface portion of an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.2. The semiconductor device of claim 1 , wherein the source/drain structure comprises a surface contacting adjacent source/drain structures.3. The semiconductor device of claim 2 , wherein the surface contacting the adjacent source/drain structures is a (110) crystal surface.4. The semiconductor device of claim 3 , wherein the uppermost surface of the source/drain structure is a (111) crystal surface.5. The semiconductor device ...

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03-01-2019 дата публикации

TRENCH POWER SEMICONDUCTOR AND METHOD OF MAKING THE SAME

Номер: US20190006479A1
Принадлежит:

The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second side wall portion. 1. A trench power semiconductor component , comprising:a substrate;an epitaxial layer disposed on the substrate, the epitaxial layer having at least one trench formed therein; and a bottom insulating layer covering a lower inner wall of the at least one trench;', 'a shielding electrode located in the lower half part of the at least one trench, the shielding electrode and the epitaxial layer being separated from each other by the bottom insulating layer;', 'a gate electrode disposed on the shielding electrode;', 'an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode;', 'an upper insulating layer covering an upper inner wall of the at least one trench, wherein the upper insulating layer, the bottom insulating layer, and the inter-electrode dielectric layer jointly define a first slit and a second slit, one located on either side of the inter-electrode dielectric layer; and', 'a protection structure including a first wall portion and a second side wall portion, wherein the first wall portion fills at least one portion of ...

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03-01-2019 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20190006484A1
Принадлежит:

A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer. 1. A manufacturing method of a semiconductor device , comprising:forming a gate structure on a substrate and in a trench surrounded by a spacer, wherein the gate structure comprises a metal gate electrode and a gate dielectric layer encompassing the metal gate electrode, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode;forming a mask layer on the gate structure and in the trench, wherein at least one void is formed in the mask layer within the trench, and the at least one void is formed between the metal gate electrode and the spacer, wherein the bottom surface of the mask layer and the top surface of the gate dielectric layer are coplanar;forming a source/drain structure adjacent to the spacer;forming an etching stop layer on the source/drain structure; andforming a contact structure penetrating the etching stop layer, wherein the etching stop layer and the spacer are disposed between the at least one void and the contact structure.2. The manufacturing method of the semiconductor device according to claim 1 , further comprising:performing an etching back process to the gate structure before the step of forming the mask layer, wherein the gate structure further comprises a work function layer encompassing the metal gate electrode, and a topmost surface of the work function layer is lower than the topmost surface of the metal gate electrode after the etching back process.3. The manufacturing method ...

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03-01-2019 дата публикации

THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING SAME AND SEMICONDUCTOR DEVICE COMPRISING SAID THIN FILM TRANSISTOR

Номер: US20190006525A1
Принадлежит:

A thin film transistor having a high operation speed with a field effect mobility greater than 20 cm/Vs and a method for manufacturing the same, and a semiconductor device having the same are provided. A thin film transistor in which a gate electrode, a gate insulating film and an oxide semiconductor film are laminated on a substrate, a source region and a drain region are respectively formed in outer portions of the oxide semiconductor film in the width direction, and a channel region is formed in a region between the source region and the drain region; and a source electrode is connected to the source region, while a drain electrode is connected to the drain region. The gate insulating film contains fluorine; and the ratio of the width W of the channel region to the length L thereof, namely W/L is less than 8. 1. A thin film transistor in which a gate electrode , a gate insulating film , and an oxide semiconductor film are laminated on a substrate ,a source region and a drain region are formed on both outer sides of the oxide semiconductor film in a width direction,a channel region is formed in a region between the source region and the drain region,a source electrode is connected to the source region, anda drain electrode is connected to the drain region,wherein fluorine is contained in the gate insulating film, and a ratio (W/L) of a width W to a length L of the channel region is less than 8.2. The thin film transistor according to claim 1 ,wherein a ratio (W/L) of a width W to a length L of the channel region is 0.8 or less.3. The thin film transistor according to claim 1 ,wherein a content of fluorine in the gate insulating film is 1 to 25 at %.4. The thin film transistor according to claim 1 ,wherein the gate insulating film is made of a fluorinated silicon nitride.5. The thin film transistor according to claim 1 ,wherein a hydrogen content of the gate insulating film is 1 at % or less.6. The thin film transistor according to claim 1 ,wherein the oxide ...

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02-01-2020 дата публикации

Interfacial Layer Between Fin and Source/Drain Region

Номер: US20200006548A1
Принадлежит:

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium. 1. A method of manufacturing a semiconductor device , the method comprising:forming a fin and isolation regions on opposing sides of the fin, the fin protruding from a substrate;forming a dummy gate structure over the fin;forming a recess in the fin proximate the dummy gate structure;forming an interfacial layer in the recess, the interfacial layer comprising silicon germanium, wherein the interfacial layer has a silicon atomic percent content of about 90% or more; andgrowing an epitaxial source/drain region over the interfacial layer by epitaxial growth, wherein the interfacial layer completely separates the epitaxial source/drain region from the fin, wherein the interfacial layer has a higher silicon atomic percent content of silicon than the epitaxial source/drain region and the fin.2. The method of claim 1 , wherein a thickness of the interfacial layer is in a range from about 1 nm to about 4 nm.3. The method of claim 1 , wherein the interfacial layer encapsulates impurities on a surface of the fin.4. The method of claim 3 , wherein the impurities comprise chlorine claim 3 , oxygen claim 3 , carbon claim 3 , or fluorine.5. The method of claim 1 , wherein the interfacial layer has a surface roughness less than a surface of the recess.6. A method of manufacturing a semiconductor device claim 1 , the method comprising:forming a first fin and a second fin with an isolation region interposed between the first fin and the second fin;forming a dummy gate structure over the first fin and the second fin;forming a first recess in the first fin and a second recess in the second fin proximate ...

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02-01-2020 дата публикации

Vertical transistors with various gate lengths

Номер: US20200006553A1
Принадлежит: International Business Machines Corp

A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.

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08-01-2015 дата публикации

HIGH ELECTRON MOBILITY TRANSISTORS AND METHODS OF FABRICATING THE SAME

Номер: US20150008485A1
Принадлежит:

A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm. 1. A high electron mobility transistor (HEMT) , comprising:a channel forming layer;a channel supplying layer on the channel forming layer, the channel supplying layer configured to induce a two-dimensional electron gas (2DEG) channel in the channel forming layer;a channel increase layer on the channel supplying layer;source and drain electrodes on the channel increase layer; anda gate electrode on the channel supplying layer, whereinthe channel forming layer includes a lightly doped drain (LDD) region between the gate electrode and the drain electrode, andthe channel supplying layer does not include a doped region to form the LDD region.2. The HEMT of claim 1 , wherein a thickness of the channel supplying layer is less than or equal to about 15 nm.3. (canceled)4. The HEMT of claim 1 , whereinthe channel supplying layer includes a recess, andthe gate electrode is in the recess.5. The HEMT of claim 1 , further comprising:an oxygenated region in the channel supplying layer,wherein the oxygenated region is between the gate electrode and the channel forming layer.6. The HEMT of claim 1 , further comprising:at least one of a p-type semiconductor and a dielectric material between the channel supplying layer and the gate electrode.7. The HEMT of claim 1 , further comprising:an insulating layer between the gate electrode and the channel supplying layer.8. The HEMT of claim 1 , wherein the channel increase layer includes at least one of ...

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20-01-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220020691A1
Принадлежит:

Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell. 1. A semiconductor device , comprising: a first active region and a second active region that are adjacent to each other in a first direction;', 'a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction; and', 'a first metal layer on the gate electrode,', 'wherein the first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other,, 'a first logic cell and a second logic cell on a substrate, wherein each of the first and second logic cells includeswherein the first and second logic cells are adjacent to each other in the second direction along the first and second power lines,wherein the first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell,wherein the first metal layer of the first logic cell further includes one or more first lower lines aligned on first line tracks between the first and second power lines,wherein the first metal layer of the second logic cell further ...

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27-01-2022 дата публикации

GATE SPACERS IN SEMICONDUCTOR DEVICES

Номер: US20220028997A1

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region. 1. A semiconductor device , comprising:a substrate;a fin structure with a fin top surface disposed on the substrate;a source/drain (S/D) region disposed on the fin structure;a gate structure disposed on the fin top surface; anda gate spacer with first and second spacer portions disposed between the gate structure and the S/D region,wherein the first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure, andwherein the second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.2. The semiconductor device of claim 1 , wherein the second spacer portion has a tapered structure.3. The semiconductor device of claim 1 , wherein the first spacer portion has a non-tapered structure.4. The semiconductor device of claim 1 , wherein a first sidewall of the second spacer portion is adjacent to the fin structure and a second sidewall of the second spacer portion is adjacent to the S/D region.5. The semiconductor device of claim 1 , wherein the second spacer portion has a sloped sidewall adjacent to the fin structure and a substantially vertical sidewall adjacent to the S/D region.6. The semiconductor device of claim 1 , wherein the second spacer portion is disposed within the fin structure.7. The semiconductor device of claim 1 , wherein the second spacer is ...

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12-01-2017 дата публикации

BRIDGING LOCAL SEMICONDUCTOR INTERCONNECTS

Номер: US20170012061A1
Принадлежит:

A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates. 1. A semiconductor device comprising:a plurality of transistor gates comprising one or more inner gates and a plurality of outer gates, the plurality of transistor gates at least directly upon a buried-dielectric layer of a semiconductor substrate, the semiconductor substrate comprising a plurality of outer active areas and one or more inner active areas, wherein the plurality of outer active areas are of opposite polarity relative to at least one inner active area;an isolator directly upon the one or more inner gates associated with the one or more inner active areas and offset from the plurality of outer active areas, the isolator comprising a protective barrier portion directly upon a dielectric layer, the dielectric layer directly upon the one or more inner gates; anda monolithic contact bar electrically connecting the plurality of outer active areas, the monolithic contact bar directly upon the protective barrier portion, wherein the isolator electrically insulates the monolithic contact bar from the one or more inner gates.2. The semiconductor device of claim 1 , wherein the isolator also insulates the monolithic contact bar from the one or more inner active areas.3. The semiconductor device of claim 1 , further comprising an interlayer dielectric claim 1 , wherein a top surface of the monolithic contact bar and a top surface of the interlayer dielectric are coplanar.4. The semiconductor device of claim ...

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12-01-2017 дата публикации

INCREASED CONTACT AREA FOR FINFETS

Номер: US20170012129A1
Принадлежит:

A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess. 1. A method for forming fin field effect transistors , comprising:epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section;forming a dielectric liner over the S/D regions;etching a dielectric fill formed over the S/D regions to expose a top portion of the diamond-shaped cross section;recessing the fins into the diamond-shaped cross section;exposing an outer surface of the diamond-shaped cross section of the S/D regions;forming a contact liner on the exposed outer surface of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed; andforming contacts over surfaces of the top portion and in the recess.2. The method as recited in claim 1 , wherein etching the dielectric fill includes performing a timed etch in accordance with a pattern to reach the top portion of the diamond-shaped cross section.3. The method as recited in claim 1 , wherein recessing the fins into the diamond-shaped cross section includes performing a selective etch to etch a portion of the fins within the diamond-shaped cross section.4. The method as recited in claim 3 , wherein performing the selective etch includes performing a reactive ion etch with an HBr chemistry.5. The method as recited in claim 1 , further ...

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12-01-2017 дата публикации

Large area contacts for small transistors

Номер: US20170012130A1

A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO 2 , prevents erosion of an adjacent gate structure during the formation of the contact.

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14-01-2016 дата публикации

DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS

Номер: US20160013096A1
Принадлежит:

A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. 2. The method of claim 1 , wherein a portion of said contact via structure is in direct contact with a topmost horizontal surface of said dielectric metal oxide liner and a topmost surface of said silicon nitride liner.3. The method of claim 1 , wherein said dielectric metal oxide liner is recessed to a depth between a top surface of said buried insulator portion and a bottom surface of said buried insulator portion.4. The method of claim 3 , wherein another portion of said contact via structure is formed directly on a vertical sidewall surface of said buried insulator portion.5. The method of claim 1 , further comprising recessing said silicon nitride liner to a depth below the horizontal plane of a bottom surface of said top semiconductor portion.6. The method of claim 5 , wherein said silicon nitride liner is recessed to a depth below the horizontal plane of a bottom surface of said buried insulator portion.7. The method of claim 6 , wherein said contact via structure is in direct contact with a vertical ...

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14-01-2016 дата публикации

THIN FILM TRANSISTOR ARRAY

Номер: US20160013213A1
Автор: ISHIZAKI Mamoru
Принадлежит: TOPPAN PRINTING CO., LTD.

A thin film transistor array including a gate wiring connected to a gate electrode and extended in a first direction, a source wiring connected to a source electrode, a drain electrode having a gap from the source electrode, a semiconductor pattern formed at least in a portion corresponding to the gap between the source and drain electrodes, the semiconductor pattern having a region defined by extending the portion in a second direction perpendicular to the first direction, and a pixel electrode that overlaps with a capacitor electrode in the planar view. In the planar view, the drain electrode has a shape of a single line, the source electrode has a first portion in a line shape and a second portion in a sheath shape surrounding the drain electrode and keeping a space from the drain electrode, and the source wiring is narrower than the region of the semiconductor pattern. 1. A thin film transistor array , comprising:a gate electrode;a gate wiring connected to the gate electrode and extended in a first direction;a source electrode;a source wiring connected to the source electrode;a drain electrode having a gap from the source electrode in an area overlapped with the gate electrode in a planar view;a semiconductor pattern formed at least in a portion corresponding to the gap between the source electrode and the drain electrode, the semiconductor pattern having a region defined by extending the portion in a second direction perpendicular to the first direction;a capacitor electrode; anda pixel electrode connected to the drain electrode such that the pixel electrode overlaps with the capacitor electrode in the planar view,wherein, in the planar view, the drain electrode has a shape of a single line, the source electrode has a first portion in a line shape and a second portion in a sheath shape surrounding the drain electrode and keeping a space from the drain electrode, andthe source wiring has a width narrower than a width of the region of the semiconductor pattern.2. ...

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11-01-2018 дата публикации

SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

Номер: US20180012810A1
Автор: Zhou Fei
Принадлежит:

A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a second transistor region. The method also includes forming a first work function layer an the dielectric layer covering bottom and sidewall surfaces of the first and the second openings, forming a first sacrificial layer in each first opening and each second opening with a top surface lower than the top surface of the dielectric layer, removing a portion of the first work function layer exposed by the first sacrificial layer, removing the first work function layer formed in each first opening, and forming a second work function layer and a gate electrode in each first opening and each second opening. 1. A method for fabricating a semiconductor structure , comprising:providing a base structure including a first transistor region and a second transistor region, wherein the base structure includes a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in the first transistor region, and a plurality of second openings formed in the dielectric layer in the second transistor region;forming a first work function layer on the dielectric layer and covering bottom and sidewall surfaces of each of the first opening and the second opening;forming a first sacrificial layer in each first opening and each second opening, wherein a top surface of the first sacrificial layer is lower than a top surface of the dielectric layer;removing a portion of the first work function layer exposed by the first sacrificial layer using the first sacrificial layer as an etch mask;removing the first work function layer thrilled in each first opening; andforming a second work function layer and then a gate electrode in each ...

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14-01-2016 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20160013270A1
Автор: Liu Jinhua
Принадлежит:

A Si-on-half-insulator device and its manufacturing method are disclosed in this invention. In one embodiment, a horizontal insulating layer located below at least one of the source and drain regions is realized to reduce junction capacitance. In another embodiment, a horizontal insulating layer located below at least one of the source and drain regions and a vertical insulating layer located below at least one side surface of the gate are realized. The additional vertical insulating layer can reduce punch leakage. Further, a method of manufacturing the above semiconductor device is also disclosed, wherein the horizontal and vertical insulating layers are formed using an additional layer of epitaxially grown semiconductor material and isolating trenches. 1. A semiconductor device , comprising:a gate on a substrate;source and drain regions located on opposite sides of the gate;a horizontal insulating layer located substantially parallel to the surface of the substrate and below at least one of the source and drain regions.2. The semiconductor device according to claim 1 , further comprising a vertical insulating layer located substantially vertical to the surface of the substrate and below a side surface of the gate.3. The semiconductor device according to claim 2 , wherein the vertical insulating layer is lower than the source and drain regions.4. The semiconductor device according to claim 3 , further comprising isolating trenches located on one side of the source and drain regions away from the gate.5. The semiconductor device according to claim 4 , wherein the horizontal insulating layer intersects with the isolating trenches.6. The semiconductor device according to claim 2 , wherein the horizontal insulating layer and the vertical insulating layer are in “” or “” form.7. The semiconductor device according to claim 3 , wherein the horizontal insulating layer and the vertical insulating layer are in “” or “” form.8. A semiconductor device claim 3 , comprising:a ...

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11-01-2018 дата публикации

SEMICONDUCTOR STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION

Номер: US20180012882A1
Принадлежит:

A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region. 1. A semiconductor structure for electrostatic discharge protection , comprising:a substrate;a first doped well disposed in the substrate and having a first conductive type;a source doped region disposed in the substrate and having a second conductive type opposite to the first conductive type;a drain doped region disposed in the substrate and having the second conductive type, wherein the drain doped region is disposed above the first doped well;a gate structure disposed on the substrate and between the source doped region and the drain doped region; anda doped drain region surrounding the drain doped region and partially under the gate structure,wherein the gate structure is directly in contact with the drain doped region and separated from the source doped region.2. The semiconductor structure according to claim 1 , further comprising a second doped well claim 1 , wherein at least portions of the second doped well are disposed between the source doped region and the gate structure.3. The semiconductor structure according to claim 2 , wherein the second doped well has the second conductive type claim 2 , and a concentration of the second doped well is smaller than a concentration of the source doped region.4. The semiconductor structure according to claim 2 , wherein the second doped ...

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14-01-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20160013301A1
Автор: SIDDIQUI MD Imran
Принадлежит:

The semiconductor device includes a first semiconductor layer of a first conductivity type, an insulated gate structure, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, and a lightly doped semiconductor region of the second conductivity type. The insulated gate structure is formed in a trench configuration recessed into the first semiconductor layer. The first semiconductor region, the second semiconductor region, and the lightly doped semiconductor region are formed in the first semiconductor layer. The second semiconductor region contacts the first semiconductor region and the insulated gate structure. The second semiconductor region is formed on the lightly doped semiconductor region. The lightly doped semiconductor region is formed between and contacts the first semiconductor region and the insulated gate structure. A method of manufacturing a semiconductor device is also disclosed herein. 1. A semiconductor device comprising:a first semiconductor layer of a first conductivity type;an insulated gate structure formed in a trench configuration recessed into the first semiconductor layer;a first semiconductor region of a second conductivity type formed in the first semiconductor layer;a second semiconductor region of the first conductivity type formed in the first semiconductor layer, the second semiconductor region contacting the first semiconductor region and the insulated gate structure; anda lightly doped semiconductor region of the second conductivity type formed in the first semiconductor layer, the second semiconductor region formed on the lightly doped semiconductor region, the lightly doped semiconductor region formed between and contacting the first semiconductor region and the insulated gate structure.2. The semiconductor device as claimed in claim 1 , wherein the lightly doped semiconductor region and the first semiconductor region are individual semiconductor regions claim 1 , ...

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14-01-2016 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Номер: US20160013312A1
Автор: Fujimoto Hiroyuki
Принадлежит:

One semiconductor device includes an element-isolation region formed on a semiconductor substrate, an active region surrounded by said element-isolation region, a semiconductor pillar in the active region and protruding from the surface of the substrate, a gate electrode on a side surface of the pillar, with a gate-insulating film interposed there between, and extending in a first direction, a pillar-top diffusion layer in the top-end section of the pillar, a pillar-bottom diffusion layer in the bottom-end section of the pillar, a channel section between the pillar-top diffusion layer and the pillar-bottom diffusion layer, a silicide layer beneath the pillar-bottom diffusion layer and extending in a second direction perpendicular to the first direction, a contact plug to contact the silicide layer in the bottom-end section, and top-layer wiring to contact the contact plug in the top-end section. The contact plug is connected to the silicide layer through the pillar-bottom diffusion layer. 1. A semiconductor device comprising:an element-isolation region formed on a semiconductor substrate;an active region surrounded by the element-isolation region;a semiconductor pillar disposed in the active region so as to protrude from the surface of the semiconductor substrate;a gate electrode disposed on a side surface of the semiconductor pillar, with a gate insulating film interposed in between, so as to extend in a first direction;a pillar-top diffusion layer disposed on a top-end section of the semiconductor pillar;a pillar-bottom diffusion layer disposed on a bottom-end section of the semiconductor pillar;a channel section disposed between the pillar-top diffusion layer and the pillar-bottom diffusion layer;a silicide layer disposed beneath the pillar-bottom diffusion layer so as to extend in a second direction perpendicular to the first direction;a contact plug disposed so as to contact the silicide layer at a bottom-end section; anda top-layer wiring disposed so as to ...

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11-01-2018 дата публикации

DEVICE AND SYSTEM OF A SILICON CONTROLLED RECTIFIER (SCR)

Номер: US20180012961A1
Автор: Aharoni Efraim
Принадлежит:

Some demonstrative embodiments include devices and/or systems of a Silicon Controlled Rectifier (SCR). For example, a silicon controlled rectifier (SCR) may include a metal-oxide-semiconductor field-effect transistor (MOSFET), the MOSFET may include a gate; an N-type source region; a non-Lightly Doped Drain (LDD) N-type drain region; and a P-Well region extending between the N-type source region and the non-LDD N-type drain region, and extending between the non-LDD N-type drain region and a drain region of the gate. 1. A silicon controlled rectifier (SCR) comprising a metal-oxide-semiconductor field-effect transistor (MOSFET) , the MOSFET comprising:a gate;an N-type source region comprising a heavily doped region and a Lightly Doped Drain (LDD) region comprising light N-type doping;a non-LDD N-type drain region; anda P-Well region extending between said N-type source region and said non-LDD N-type drain region, and extending between said non-LDD N-type drain region and a drain region of said gate, the LDD region extending between said P-well region and a source region of said gate, said LDD region is in direct contact with the source region of said gate.2. The SCR of claim 1 , wherein said P-Well region is in direct contact with the drain region of said gate.3. The SCR of claim 1 , wherein said P-Well region fills an entire area under the drain region of said gate.4. The SCR of claim 1 , wherein said P-Well region separates between said non-LDD N-type drain region and the drain region of said gate.5. The SCR of claim 1 , wherein an entirety of said non-LDD N-type drain region is uniformly doped.6. The SCR of claim 1 , wherein an entirety of said non-LDD N-type drain region is heavily doped.7. The SCR of claim 1 , wherein said non-LDD N-type drain region does not include any light N-type doping.8. The SCR of claim 18 , wherein said LDD N-type region extends between said P-well region and a source region of said gate.9. The SCR of claim 18 , wherein said LDD N-Type ...

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11-01-2018 дата публикации

Field-Effect Transistors Having Contacts To 2D Material Active Region

Номер: US20180012962A1
Принадлежит:

Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer. 1. A field-effect transistor (FET) , comprising:a 2D material layer over a substrate wherein the substrate includes a plurality of fins and the 2D material is formed over top and sidewall surfaces of the plurality of fins, the 2D material layer including a channel region and a source/drain region, wherein the 2D material has a first thickness in the channel region and a second thickness is the source/drain region, wherein the first and second thicknesses are each measured as a number of monolayers of the 2D material in height above a surface of the substrate, and wherein the second thickness is greater than the first thickness;a contact interfacing a sidewall of the 2D material layer in the source/drain region; anda gate electrode over the channel region.2. The FET of claim 1 , wherein the first thickness is at least one monolayer less in thickness than the second thickness.3. The FET of claim 1 , wherein the contact also interfaces with a top surface of the 2D material having the second thickness.4. The FET of claim 1 , wherein the sidewall of the 2D material layer is nonlinear.5. The FET of claim 1 , wherein the sidewall of the 2D material layer is a passivated edge.6. The FET of claim 1 , wherein the contact interfaces the 2D material at a region having a third thickness different than the second thickness claim 1 , wherein the third thickness is measured as a number of monolayers ...

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11-01-2018 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20180012970A1
Автор: KIM Myoungsoo
Принадлежит: Samsung Electroncis Co., Ltd.

The semiconductor device including a device isolation layer disposed in a substrate and defining an active region, a first conductive pattern on the active region, an impurity region in the active region on a side of the first conductive pattern, a second conductive pattern on the active region between the impurity region and the first conductive pattern, a first spacer between the first conductive pattern and the second conductive pattern, and a contact plug disposed on and electrically connected to the first conductive pattern may be provided. The second conductive pattern may have a width less than a width of the contact plug. 1. A semiconductor device comprising:a device isolation layer in a substrate, the device isolation layer defining an active region;a first conductive pattern on the active region;an impurity region in the active region, the impurity region on a side of the first conductive pattern;a second conductive pattern on the active region, the second conductive pattern between the impurity region and the first conductive pattern;a first spacer between the first conductive pattern and the second conductive pattern; anda contact plug on the first conductive pattern, if contact plug electrically connected to the first conductive pattern, a width of the second conductive pattern being less than a width of the contact plug.2. The semiconductor device of claim 1 , wherein the first and second conductive patterns comprise a same material.3. The semiconductor device of claim 1 , further comprising:a third conductive pattern on the active region, the third conductive pattern between the second conductive pattern and the first impurity region, a width of the third conductive pattern being less than the width of the contact plug; anda second spacer between the second conductive pattern and the third conductive pattern.4. The semiconductor device of claim 1 , wherein the first conductive pattern is in an electrically floating state.5. The semiconductor device of ...

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11-01-2018 дата публикации

GATE LENGTH CONTROLLED VERTICAL FETS

Номер: US20180012993A1
Принадлежит:

A semiconductor structure and a method a method of forming a vertical FET (Field-Effect Transistor), includes growing a bottom source-drain layer of a second type on a substrate of a first type, growing a channel layer on the bottom source-drain layer, forming a first fin from the channel layer with mask on top of the first fin. A width of the mask is wider than a final first fin width. 1. A method of forming a vertical FET (Field-Effect Transistor) , comprising:growing a bottom source-drain layer of a second type on a substrate of a first type;growing a channel layer on the bottom source-drain layer;forming a first fin from the channel layer with mask on top of the first fin,wherein a width of the mask is wider than a final first fin width.2. The method according to claim 1 , further comprising:trimming the first fin laterally to a predetermined width; andforming a bottom spacer on the bottom source-drain layer.3. The method according to claim 2 , further comprising:forming a high-k dielectric layer on the bottom spacer, first fin, and the mask; andforming and metal gate layer on the high-k dielectric layer.4. The method according to claim 3 , further comprising:recessing the metal gate layer; andremoving an exposed portion of the high-k dielectric layer.5. The method according to claim 4 , further comprising:filling an interlayer dielectric over the bottom spacer;performing q chemical metal polishing to the mask; andremoving the mask.6. The method according to claim 5 , further comprising:forming a top spacer by conformal deposition and directional etch back to form a recessed area.7. The method according to claim 6 , further comprising:growing a top source-drain epitaxial layer of a second type on the first fin and the top spacer.8. The method according to claim 7 , further comprising:forming a first contact on the top source-drain epitaxial layer; andforming a second contact on the bottom source-drain layer.9. The method according to claim 1 , wherein the bottom ...

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10-01-2019 дата публикации

CONTACTING SOURCE AND DRAIN OF A TRANSISTOR DEVICE

Номер: US20190013241A1
Принадлежит:

A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact. 1. A method of manufacturing a semiconductor device , comprising:forming raised source and drain regions on a semiconductor layer;forming a first insulating layer over said semiconductor layer;forming a first contact to one of said raised source and drain regions in said first insulating layer;forming a second insulating layer over and above said first contact after forming said first contact;forming a trench in said second insulating layer to remove a portion of said second insulating layer and expose said first contact, wherein said forming of said trench in said second insulating layer comprises a first reactive ion etching;performing a first etching process through said trench to remove a portion of said first contact exposed below said trench, thereby forming a recessed surface of said first contact lower than an uppermost surface of said first contact, wherein said first etching process comprises a second reactive ion etching;removing a portion of said first insulating layer exposed by said trench to form a recess in said first insulating layer, said recess exposing a portion of a sidewall of ...

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14-01-2021 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20210013313A1
Автор: Wang Nan
Принадлежит:

A semiconductor device and fabrication method thereof are provided. The method includes: providing a gate structure, a first dielectric layer, and source/drain doped layers on a base substrate and in the base substrate on sides of the gate structure; forming a mask layer on the gate structure between the source/drain doped layers; forming a second dielectric layer on the first dielectric layer and exposing the mask layer; etching the second dielectric layer and the first dielectric layer using the mask layer as an etch mask, to form first grooves on the sides of the gate structure and exposing the source/drain doped layers; forming a first conductive structure in each first groove; patterning the mask layer to form a second groove in the mask layer to expose the gate structure at the bottom of the second groove; and forming a spacer on sidewalls of the second groove. 1. A fabrication method for a semiconductor device , including:providing a gate structure and a first dielectric layer, on a base substrate, and providing source/drain doped layers in the base substrate on sides of the gate structure;forming a mask layer on the gate structure between the source/drain doped layers;forming a second dielectric layer on the first dielectric layer and exposing the mask layer;etching the second dielectric layer and the first dielectric layer using the mask layer as an etch mask, to form first grooves on the sides of the gate structure and exposing the source/drain doped layers;forming a first conductive structure in each first groove;patterning the mask layer to form a second groove in the mask layer to expose the gate structure at the bottom of the second groove; andforming a spacer on sidewalls of the second groove.2. The method according to claim 1 , after forming the spacer on the sidewalls of the second groove claim 1 , further including:forming a second conductive structure in the second groove.3. The method according to claim 1 , wherein:{'sub': 'x', 'the mask layer is ...

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14-01-2021 дата публикации

TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR DESIGNING SAME

Номер: US20210013316A1
Принадлежит:

[Problem] To improve the drain current ON/OFF ratio characteristics. 1. A tunnel field-effect transistor comprising: a semiconductor layer formed to include a source region , a channel region arranged adjacent to the source region and whose boundary surface with the source region is set as a tunnel junction surface to cause carriers in the source region to tunnel through , and a drain region arranged adjacent to the channel region and to which the carriers are transported from the channel region; a gate part formed with a gate insulating film and a gate electrode arranged in this order on the semiconductor layer; and an insulation part arranged to cover a side face of the gate electrode , and having: a structure in which part of the source region is arranged under a bottom surface of the gate part as a surface on a side of the gate insulating film to cause the bottom surface and the part of the source region to come into contact with each other; and a drain offset structure in which a drain offset region is formed in the semiconductor layer to keep the gate electrode and the drain region away from each other , wherein{'sub': G', 'OV, 'when a gate length as a width of the gate electrode in a direction parallel to a channel direction between the source region and the drain region is denoted by L, and an extension distance of the source region extended toward the drain region in a direction parallel to the channel direction from a position in the source region opposite in a height direction of the gate electrode to a source-side reference position as a side face position of the gate electrode closest to the source region is denoted by L,'}{'sub': 'TG', 'claim-text': [{'br': None, '[Math. 1]'}, {'br': None, 'i': L', '=L', '−L, 'sub': TG', 'G', 'OV, '(1)'}, {'br': None, '[Math. 2]'}, {'br': None, 'sub': TG', 't_OFF, 'LL', '−L, 'sub': TG', 'direct', 'OFF, '(3)'}], 'Lexpressed in Formula (1) below as a ...

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09-01-2020 дата публикации

PRODUCT THAT INCLUDES A PLURALITY OF VERTICAL TRANSISTORS WITH A SHARED CONDUCTIVE GATE PLUG

Номер: US20200013684A1
Принадлежит:

The present disclosure is directed to various embodiments of a product that includes first and second vertical semiconductor structures for first and second, respectively, vertical transistor devices, and first and second gate structures positioned adjacent the first and second, respectively, vertical semiconductor structures. The product also includes a shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, wherein the shared conductive gate plug is conductively coupled to both the first gate structure and the second gate structure. 1. A product , comprising:a first vertical semiconductor structure;a first bottom source/drain region positioned adjacent the first vertical semiconductor structure;a second vertical semiconductor structure;a second bottom source/drain region positioned adjacent the second vertical semiconductor structure;a bottom spacer positioned above the first and second bottom source/drain regions; anda shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, the shared conductive gate plug being conductively coupled to both the first gate structure and the second gate structure.2. The product of claim 1 , wherein the first vertical semiconductor structure is a portion of a first vertical transistor device and wherein the second vertical semiconductor structure is a portion of a second vertical transistor device.3. The product of claim 2 , wherein the first vertical transistor device is an N-type device and the second vertical transistor device is a P-type device.4. The product of claim 1 , wherein materials of construction for the first gate structure and the second gate structure are the same.5. The product of claim 1 , wherein the first gate structure comprises a first work-function material layer and the second gate structure comprises a second work-function material layer that is different from the first work-function material ...

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09-01-2020 дата публикации

Replacement Gate Process for FinFET

Номер: US20200013779A1
Принадлежит:

A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin. 1. A device comprising:a dielectric isolation layer disposed over a substrate;a first fin structure disposed over the substrate and embedded within the dielectric isolation layer, wherein the dielectric isolation layer on a first side of the first fin structure has a first height and the dielectric isolation layer on a second side of the first fin structure has a second height, the first fin structure associated with a first transistor of a first type of conductivity;a second fin structure disposed over the substrate and embedded within the dielectric isolation layer, wherein the dielectric isolation layer on a third side of the second fin structure has a third height and the dielectric isolation layer on a fourth side of the second fin structure has a fourth height, wherein the first height is different than the third height and the second height is different than the fourth height, the second fin structure associated with a second transistor of a second type of conductivity, the second type being opposite the first type; andan etch stop layer extending from the second fin structure to a first feature disposed on the first fin structure without extending to the first fin structure.2. The device of claim 1 , wherein the dielectric isolation layer interfaces with the first ...

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09-01-2020 дата публикации

HETEROJUNCTION BIPOLAR TRANSISTOR WITH COUNTER-DOPED COLLECTOR REGION AND METHOD OF MAKING SAME

Номер: US20200013856A1
Принадлежит: STMICROELECTRONICS (CROLLES 2) SAS

A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region. 1. A method of manufacturing a bipolar transistor in a structure including a single-crystal silicon substrate including a collector connection region doped with a first conductivity type , the method comprising the steps of:a) coating the substrate in succession with a first insulating layer and a silicon layer;b) etching an opening through the silicon layer and the first insulating layer to expose a top surface of the substrate;c) in the opening, forming by selective epitaxy from the top surface of the substrate a collector region made of semiconductor material doped with the first conductivity type;d) forming a counter-doped region located inside the collector region and doped with both a dopant of the first conductivity type and a dopant of a second conductivity type opposite the first conductivity type;e) forming by selective epitaxy from a top surface of the collector region a base region made of semiconductor material doped with the second conductivity type; andf) forming by deposition on a top surface of the base region an emitter region made of semiconductor material doped with the first conductivity type.2. The ...

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09-01-2020 дата публикации

Dummy Gate Structure and Methods Thereof

Номер: US20200013874A1
Принадлежит:

A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness. 1. A method of semiconductor device fabrication , comprising:forming a multi-gate device including a first gate dielectric layer with a first thickness;depositing a second gate dielectric layer to form a first gate stack of a dummy gate disposed at least partially over an isolation region adjacent to a source or drain of the multi-gate device, wherein the second gate dielectric layer has a second thickness greater than the first thickness; andwhile forming the second gate dielectric layer, simultaneously depositing the second gate dielectric layer to form a second gate stack of an input/output (I/O) device.2. The method of claim 1 , further comprising prior to forming the multi-gate device claim 1 , forming the isolation region.3. The method of claim 2 , wherein the forming the isolation region further includes forming the isolation region separating a first active region from a second active region claim 2 , wherein the first active region is adjacent to a first side of the isolation region claim 2 , and wherein the second active region is adjacent to a second side of the isolation region.4. The method of ...

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09-01-2020 дата публикации

VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED GATE VARIATION AND REDUCED CAPACITANCE

Номер: US20200013879A1
Принадлежит:

A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin on a substrate, and depositing a sidewall liner on exposed surfaces of the vertical fin. The method further includes removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin. The method further includes laterally etching the support pillar to form a thinned support pillar, and forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness. 1. A method of forming a fin field effect transistor device , comprising:forming a vertical fin on a substrate;depositing a sidewall liner on exposed surfaces of the vertical fin;removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin;laterally etching the support pillar to form a thinned support pillar; andforming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness.2. The method of claim 1 , further comprising depositing a capping layer on the bottom source/drain layer.3. The method of claim 2 , further comprising converting the capping layer to a bottom spacer layer.4. The method of claim 3 , wherein the capping layer is converted to the bottom spacer layer through exposure to an oxidizing agent at a temperature in a range of about 400° C. to about 800° C.5. The method of claim 3 , wherein the capping layer is silicon-germanium.6. The method of claim 5 , wherein the capping layer has a germanium concentration in a range of about 40 atomic percent (at. %) to about 60 at. %.7. The method of claim 3 , further comprising removing the sidewall liner claim 3 , and forming a gate dielectric layer on the vertical fin claim 3 , bottom spacer layer claim 3 , and bottom source/drain layer.8. The method of claim 7 , wherein the gate dielectric layer ...

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21-01-2016 дата публикации

Semiconductor Devices and Methods of Fabricating the Same

Номер: US20160020205A1
Автор: Song Hyun-Seung
Принадлежит:

Provided is a semiconductor device including a substrate, first and second gate structures provided on the substrate, a source/drain region provided adjacent to the first gate structure, an interlayered insulating layer provided on the substrate to cover the source/drain region and the first and second gate structures, a source/drain contact hole penetrating the interlayered insulating layer and exposing the source/drain region, a trench formed in the interlayered insulating layer to expose a top surface of the second gate structure, a source/drain contact plug provided in the source/drain contact hole to be in contact with the source/drain region, and a resistor pattern provided in the trench to be in contact with a top surface of the second gate structure.

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21-01-2016 дата публикации

FABRICATION OF SHIELDED GATE TRENCH MOSFET WITH INCREASED SOURCE-METAL CONTACT

Номер: US20160020291A1
Автор: Chen John
Принадлежит:

A semiconductor device formed on a semiconductor substrate having a substrate top surface, comprising: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a gate top dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region; a metal layer disposed over at least a portion of a gate trench opening and at least a portion of the source region, wherein: the source region has a curved sidewall portion that is adjacent to the gate trench, and that extends above the gate top dielectric material.

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21-01-2016 дата публикации

SEMICONDUCTOR DEVICE HAVING INSULATING PATTERN AND METHOD OF FORMING THE SAME

Номер: US20160020324A1
Принадлежит:

A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.

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19-01-2017 дата публикации

SEMICONDUCTOR DEVICE HAVING A FIN

Номер: US20170018610A1
Автор: Seo Kang-Ill, SUK SUNG-DAE
Принадлежит:

Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region. 1. A semiconductor device comprising:a fin disposed on a substrate along a first direction;a sacrificial layer disposed on the fin;an active layer disposed on the sacrificial layer;a gate insulating layer and a gate electrode disposed along a second direction intersecting the first direction, wherein the gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer; anda source or drain region disposed on at least one side of the gate electrode on the substrate,wherein a width of each of a first region and a second region of the active layer measured in the second direction is greater than a width of a third region of the active layer measured in the second direction, and wherein the third region is disposed between the first region and the second region.2. The semiconductor device of claim 1 , wherein a concentration of germanium in the first region and the second region of the active layer is higher than a concentration of germanium in the third region.3. The semiconductor device of claim 1 , wherein a concentration of germanium in the first region of the active layer is higher than a concentration of germanium in the second region claim 1 , and wherein the first region is ...

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19-01-2017 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20170018615A1
Принадлежит: Fuji Electric Co Ltd

A semiconductor device includes an N-type silicon carbide substrate, an N-type silicon carbide layer formed on the N-type silicon carbide substrate, a P-type region selectively formed in a surface layer of the N-type silicon carbide layer, an N-type source region formed in the P-type region, a P contact region formed in the P-type region, a gate insulating film formed on a portion of a region from the N-type source region, through the P-type region, to the N-type silicon carbide layer, a gate electrode formed on the gate insulating film, an interlayer insulating film covering the gate electrode, and a first source electrode electrically connected to a surface of the P contact region and the N-type source region. An end of the interlayer insulating film covering the gate electrode has a slope of a predetermined angle.

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