PRODUCT THAT INCLUDES A PLURALITY OF VERTICAL TRANSISTORS WITH A SHARED CONDUCTIVE GATE PLUG

The present disclosure is directed to various embodiments of a product that includes first and second vertical semiconductor structures for first and second, respectively, vertical transistor devices, and first and second gate structures positioned adjacent the first and second, respectively, vertical semiconductor structures. The product also includes a shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, wherein the shared conductive gate plug is conductively coupled to both the first gate structure and the second gate structure. 1. A product , comprising:a first vertical semiconductor structure;a first bottom source/drain region positioned adjacent the first vertical semiconductor structure;a second vertical semiconductor structure;a second bottom source/drain region positioned adjacent the second vertical semiconductor structure;a bottom spacer positioned above the first and second bottom source/drain regions; anda shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, the shared conductive gate plug being conductively coupled to both the first gate structure and the second gate structure.2. The product of claim 1 , wherein the first vertical semiconductor structure is a portion of a first vertical transistor device and wherein the second vertical semiconductor structure is a portion of a second vertical transistor device.3. The product of claim 2 , wherein the first vertical transistor device is an N-type device and the second vertical transistor device is a P-type device.4. The product of claim 1 , wherein materials of construction for the first gate structure and the second gate structure are the same.5. The product of claim 1 , wherein the first gate structure comprises a first work-function material layer and the second gate structure comprises a second work-function material layer that is different from the first work-function material ...

Transistors comprising doped region-gap-doped region structures and methods of fabrication

Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

SYMMETRIC ARRANGEMENT OF FIELD PLATES IN SEMICONDUCTOR DEVICES

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate. 1. A semiconductor device comprising:an active region above a substrate;source and drain electrodes in contact with the active region;a gate above the active region and laterally between the source and drain electrodes;a first field plate between the source electrode and the gate;a second field plate between the drain electrode and the gate; andwherein the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.2. The device of claim 1 , wherein the first field plate and the second field plate have upper surfaces that are substantially coplanar with an upper surface of the gate.3. The device of claim 2 , wherein the first field plate is laterally spaced apart from the source electrode claim 2 , and the second field plate is laterally spaced apart from the drain electrode.4. The device of claim 2 , wherein the first field plate and the second field plate are individually biased by a voltage.5. The device of claim 2 , wherein the first field plate is electrically coupled to the source electrode and the second field plate is electrically coupled to the drain electrode.6. The device of claim 2 , wherein the first field plate and the second field plate are ...

UNIFORM BOTTOM SPACER FOR VFET DEVICES

Vertical field effect transistor (VFET) structures and methods of fabrication include a bottom spacer having a uniform thickness. The bottom spacer includes a bilayer portion including a first layer formed of an oxide, for example, and a second layer formed of a nitride, for example, on the first layer, and a monolayer portion of a fourth layer of a nitride for example, immediately adjacent to and intermediate the fin and the bilayer portion. 1. A method for forming a bottom spacer layer in a vertical field effect transistor (VFET) structure , the method comprising:forming one or more vertically oriented fins on a substrate;conformally depositing a first layer onto the substrate;conformally depositing a second layer onto the first layer;non-conformally depositing a third layer on the second layer;selectively removing the third layer selective to the second layer so as to completely remove the third layer from sidewalls and top surfaces of the one or more vertically oriented fins;selectively removing the second layer to the first and third layers so as to remove the second layer from sidewalls and top surfaces of the one or more vertically oriented fins, wherein selectively removing the second layer forms a recess immediately adjacent the one or more vertically oriented fins;selectively removing the first layer and remaining portions of the third layer to the second layer;conformally depositing a fourth layer onto the substrate filling the recess immediately adjacent the one or more vertically oriented fins; andselectively removing the fourth layer from the sidewalls and top surfaces of the one or more vertically oriented fins to form a monolayer portion of the fourth layer intermediate the one or more vertically oriented fins and a bilayer portion of the first layer and second layer.2. The method for forming the bottom spacer layer in the VFET structure of claim 1 , wherein conformally depositing the first layer claim 1 , the second layer claim 1 , and the fourth ...

RETROGRADE DOPED LAYER FOR DEVICE ISOLATION

Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins. 1. A method for forming a device , the method comprising:forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of:doped silicon (Si), and doped silicon-germanium (Si—Ge);forming a set of high mobility channel fins over the retrograde doped layer, wherein each of the set of high mobility channel fins comprises at least one of: Si, and Si—Ge, and a retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); andforming a set of silicon fins adjacent the set of high mobility channel fins.2. The method according to claim 1 , further comprising forming a carbon liner over the retrograde doped layer.3. The method according to claim 1 , the forming the retrograde doped layer comprising performing an in situ doping process.4. The method according to claim 3 , the forming the set of high mobility channel fins comprising:depositing the a high mobility channel material over the retrograde doped layer;patterning the high mobility channel material, the retrograde doped layer, and the a substrate; andetching the high mobility channel material, the retrograde doped layer, and the substrate.5. The method according to claim 4 , the depositing comprising ...

METHOD, APPARATUS, AND SYSTEM FOR REDUCING DOPANT CONCENTRATIONS IN CHANNEL REGIONS OF FINFET DEVICES

We disclose semiconductor devices, comprising a semiconductor substrate comprising a substrate material; and a plurality of fins disposed on the substrate, each fin comprising a lower region comprising the substrate material, a dopant region disposed above the lower region and comprising at least one dopant, and a channel region disposed above the dopant region and comprising a semiconductor material, wherein the channel region comprises less than 1×10dopant molecules/cm, as well as methods, apparatus, and systems for fabricating such semiconductor devices. 1. A method , comprising:forming a plurality of fins on a semiconductor substrate comprising a substrate material, each fin comprising a channel region comprising a semiconductor material;forming a block layer on a first side and a second side of at least the channel region of each fin;etching the semiconductor substrate between each pair of adjacent fins, thereby forming a lower region of each fin, wherein the lower region comprises the substrate material; andintroducing at least one dopant into a portion of the lower region adjacent to the channel region, thereby forming a dopant region disposed above the lower region and below the channel region.2. The method of claim 1 , wherein the block layer comprises nitride.3. The method of claim 1 , wherein the semiconductor material is selected from silicon or silicon-germanium (SiGe).4. The method of claim 1 , further comprising:depositing a shallow trench isolation (STI) material between each pair of adjacent fins, wherein a top of the STI material is at least as high as a top of the dopant region; andremoving the block layer from each fin.5. The method of claim 4 , wherein the width of the STI material between each pair of adjacent fins is at least 3 nm.6. The method of claim 4 , further comprising forming a gate structure over the channel region.7. The method of claim 1 , wherein in a first subset of fins claim 1 , the dopant is boron claim 1 , and in a second ...

CONTROL OF LENGTH IN GATE REGION DURING PROCESSING OF VFET STRUCTURES

Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length. 1. A method of forming a vertical FinFET , the method comprising:forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof;laterally recessing the semiconductor fin causing the fin mask to overhang above the fin;forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner;forming a gate mask laterally adjacent to the second portion of the conformal gate liner;removing the first portion of the conformal gate liner, wherein the second portion of the conformal gate liner remains intact after the removing of the first portion;removing the gate mask to expose the remaining second portion of the conformal gate liner; andforming a gate contact to the remaining second portion of the conformal gate liner, wherein a length of the gate is determined by the remaining second portion of the conformal gate liner.2. The method of claim 1 , ...

Nanosheet field effect transistor with spacers between sheets

Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

SEMICONDUCTOR STRUCTURE WITH MULTILAYER III-V HETEROSTRUCTURES

The source/drain of a fully III-V semiconductor or Si-based transistor includes a bottom barrier layer that may be lattice matched to the channel, a lower layer of a wide bandgap III-V material and a top layer of a comparatively narrow bandgap III-V material, with a compositionally graded layer between the lower layer and top layer gradually transitioning from the wide bandgap material to the narrow bandgap material. 1. A method , comprising:providing a starting semiconductor structure, the starting structure comprising a semiconductor substrate, an active region comprising a source region, a drain region and a channel region therebetween, and a gate structure above the channel region;in each of the source and drain regions, forming a bottom barrier layer of a first compound semiconductor material;forming a seed layer of a second compound semiconductor material over the bottom barrier layer, the seed layer having a first bandgap;forming a top layer of a third compound semiconductor material above the seed layer, the top layer having a second bandgap that is narrow compared to the first bandgap, wherein each compound semiconductor material comprises at least one semiconductor material from each of Groups III and V of the Periodic Table of Elements; andforming a compositionally graded layer of the second and third compound semiconductor materials between the seed layer and the top layer, the compositionally graded layer gradually transitioning from the second compound semiconductor material at a bottom portion thereof to the third compound semiconductor material at a top portion thereof.2. The method of claim 1 , wherein the bottom barrier layer has a bandgap that is wide in comparison to that of the top layer.3. The method of claim 1 , wherein the channel region comprises a fourth semiconductor material of at least one semiconductor material from Group IV or from each of Groups III and V of the Periodic Table of Elements.4. The method of claim 3 , wherein the fourth ...

EARLY PTS WITH BUFFER FOR CHANNEL DOPING CONTROL

A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers. 1. A method comprising:forming a recess in a substrate;forming a punch through stopper (PTS) layer directly below and aligned with a bottom surface of the recess;forming a buffer layer on the bottom surface and directly on side surfaces of the recess, with no material between the buffer layer and the side surfaces of the recess, wherein the portion of the buffer layer formed on the bottom surface of the recess is formed directly above and aligned with the PTS layer;forming a channel layer on and adjacent to the buffer layer; andannealing the channel, buffer, and PTS layers.2. The method according to claim 1 , wherein the substrate comprises silicon (Si) claim 1 , silicon germanium (SiGe) claim 1 , or a strain relaxed buffer (SRB).3. The method according to claim 1 , comprising forming the recess by:forming a hard-mask over a portion of the substrate; andetching a remaining portion of the substrate without the hard-mask to a depth of 5 nanometer (nm) to 60 nm.4. The method according to claim 1 , comprising forming the PTS layer by:implanting a dopant into the bottom surface of the recess; andannealing.5. The method according to claim 1 , further comprising performing a well implant in the bottom surface of the recess after forming the PTS layer claim 1 , but before forming the buffer layer.6. The method according to claim 1 , comprising forming the buffer layer of Si claim 1 , silicon:carbon (Si:C) claim 1 , SiGe claim 1 , or silicon germanium:carbon (SiGe:C).7. The method according to ...

TRACK-DEPENDENT DECODING

In one embodiment, an apparatus includes a controller and logic integrated with and/or executable by the controller. The logic is configured to perform track-dependent erasure decoding on encoded data based on detection of one or more time-varying signal quality issues associated with at least one of a plurality of tracks read simultaneously from a data storage medium. In another embodiment, a method includes determining, by a magnetic tape drive, track signal quality reliability for a plurality of tracks read simultaneously from a magnetic tape medium. In addition, the method includes performing, by the magnetic tape drive, track-dependent erasure decoding on encoded data based on detection of one or more time-varying signal quality issues associated with at least one of the plurality of simultaneously-read tracks. 1. An apparatus , comprising: 'perform track-dependent erasure decoding on encoded data based on detection of one or more time-varying signal quality issues associated with at least one of a plurality of tracks read simultaneously from a data storage medium.', 'a controller and logic integrated with and/or executable by the controller, the logic being configured to2. The apparatus as recited in claim 1 , wherein the one or more time-varying signal quality issues is determined based on side information about reliability of detected bytes within C1 codewords of each simultaneously-read track.3. The apparatus as recited in claim 2 , wherein the side information further comprises read or write channel performance of at least one read or write channel falling below a predetermined threshold based on statistics monitored by firmware of a tape drive used to read the plurality of tracks.4. The apparatus as recited in claim 3 , wherein the side information is selected from the group consisting of:C1 decoder performance falling below the predetermined threshold for a specific track in response to detection of at least one uncorrectable C1 codeword read from the ...

Vertical channel field-effect transistor (fet) process compatible long channel transistors

Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.

SYSTEMS AND METHODS FOR A BOW LABEL FOR A BEVERAGE CONTAINER

A bow label for a beverage container is disclosed herein. The bow label may include a first sheet at least partially attached to the beverage container. The bow label also may include a second sheet at least partially attached to the first sheet. The first sheet and the second sheet may include a first configuration and a second configuration. In addition, the bow label may include a pull cord disposed between and at least partially attached to the first sheet and the second sheet. In this manner, movement of the pull cord may move the first sheet and the second sheet between the first configuration and the second configuration. In some instances, the second configuration may include a bow-like shape. 1. A bow label for a beverage container , the bow label comprising:a first sheet at least partially attached to the beverage container;a second sheet at least partially attached to the first sheet, wherein the first sheet and the second sheet comprise a first configuration and a second configuration; anda pull cord disposed between and at least partially attached to the first sheet and the second sheet, wherein movement of the pull cord moves the first sheet and the second sheet between the first configuration and the second configuration, wherein the second configuration comprises a bow-like shape.2. The bow label of claim 1 , further comprising an access tab disposed about the second sheet for accessing the pull cord.3. The bow label of claim 2 , wherein the access tab comprises a removable flap.4. The bow label of claim 1 , further comprising a first strip of perforations disposed about the first sheet and the second sheet.5. The bow label of claim 1 , further comprising a second strip of perforations disposed about the first sheet and the second sheet.6. The bow label of claim 1 , where the bow-like shape is configured into a heart claim 1 , flower claim 1 , written message claim 1 , contour bottle or hand shape.7. The bow label of claim 1 , wherein the first sheet ...

SELF-ALIGNED CONTACT FOR VERTICAL FIELD EFFECT TRANSISTOR

Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer. 1. A semiconductor device comprising:a semiconductor fin vertically extending from a bottom source/drain region of a substrate;a conductive gate formed over a channel region of the semiconductor fin;a top source/drain region on a surface of the semiconductor fin;a top metallization layer on the top source/drain region; anda dielectric cap over the top metallization layer.2. The semiconductor device of further comprising a bottom source/drain contact formed over the dielectric cap and on a portion of the bottom source/drain region claim 1 , wherein a portion of the dielectric cap is between the bottom source/drain contact and the top metallization layer.3. The semiconductor device of further comprising a gate contact formed over the dielectric cap and on a portion of the conductive gate claim 1 , wherein a portion of the dielectric cap is between the gate contact and the top metallization layer.4. The semiconductor device of further comprising a gate contact formed through a portion of the dielectric cap and on a surface of the top metallization layer.5. The semiconductor device of claim 1 , wherein the dielectric cap comprises a dielectric material selected from the group consisting of a silicon nitride claim 1 , SiCN claim 1 , BN claim 1 , SiBN claim 1 , SiBCN claim 1 , and combinations thereof. This application is a divisional of U.S. patent application Ser. No. 15/599,878, filed May 19, 2017, the disclosure ...

FIN PITCH SCALING AND ACTIVE LAYER ISOLATION

A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate. 1. A method , comprising:providing a first semiconductor structure, the first structure comprising a semiconductor substrate of a bulk semiconductor material, and one or more original semiconductor fins coupled directly to the substrate;creating a dielectric layer over open areas of the substrate adjacent the one or more original fins;creating first cladding over the dielectric layer adjacent each of the one or more original fins, wherein the first cladding has uniform sidewalls and comprises a semiconductor material sufficiently different from that of the one or more original fins to allow selective etching thereof; andselectively etching to remove the one or more original fins, resulting in a second semiconductor structure, wherein the first cladding forms second fins and the dielectric layer provides electrical isolation of the second fins from the substrate.2. The method of claim 1 , wherein creating the dielectric layer comprises:conformally blanketly depositing a dielectric layer over the first semiconductor structure; andrecessing the dielectric layer.3. The method of claim 1 , wherein the first cladding comprises one of silicon and a semiconductor material comprising one or more periodic table elements from one or more of columns III claim 1 , IV and V. ...

FORMATION OF BOTTOM JUNCTION IN VERTICAL FET DEVICES

Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses. 1114-. (canceled)15. A semiconductor structure comprising:a semiconductor substrate;a fin disposed on said semiconductor substrate, the fin having a top surface and substantially vertical sides; andspaced-apart epitaxially grown semiconductor material disposed below respective vertical sides of said fin.16. The semiconductor structure of wherein said epitaxially grown semiconductor material extends under portions of said fin.17. The semiconductor structure of wherein said epitaxially grown semiconductor material comprises spaced-apart tapering surfaces juxtaposed under the fin.18. The semiconductor structure of wherein said epitaxially grown semiconductor material comprises a source or a drain.19. The semiconductor structure of wherein said semiconductor structure comprises a portion of vertical FET device.20. The semiconductor structure of wherein said vertical FET device is a gate-all around device.21. A vertical FinFET device comprising:a semiconductor substrate;a fin disposed on said semiconductor substrate, the fin having a top surface and substantially vertical sides;an epitaxially grown semiconductor material defining a bottom junction disposed below at least one of said vertical sides of said fin;a gate structure disposed adjacent to at least the vertical sides of the fin; anda top junction disposed adjacent said top surface of said fin.22. The vertical FinFET device of wherein ...

DIRECTED SELF-ASSEMBLY MATERIAL GROWTH MASK FOR FORMING VERTICAL NANOWIRES

A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material. 1. A method , comprising:forming at least one fin on a semiconductor substrate;forming a hard mask layer above said fin;forming a first directed self-assembly material above said hard mask layer;patterning said hard mask layer using a portion of said first directed self-assembly material as an etch mask to expose a portion of a top surface of said fin; andforming a substantially vertical nanowire on said exposed top surface, wherein at least one dimension of said substantially vertical nanowire is defined by an intrinsic pitch of said first directed self-assembly material.2. The method of claim 1 , further comprising:forming a recess in said at least one fin;forming said hard mask layer in said recess; andforming said first directed self-assembly material above said hard mask layer.3. The method of claim 2 , further comprising:forming an insulating layer surrounding at least a portion of said at least one fin; andforming said recess in said at least one fin and in said insulating layer.4. The method of claim 3 , further comprising removing portions of said insulating layer disposed adjacent said substantially vertical nanowire and extending above said top surface of said at least one fin.5. The method of claim 1 , wherein said first directed self-assembly material includes an etch-resistant component and an etchable component claim 1 , and the method further comprises:removing said etchable component to expose ...

DIRECTED SELF-ASSEMBLY MATERIAL ETCH MASK FOR FORMING VERTICAL NANOWIRES

A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material. 1. A method , comprising:forming at least one fin on a semiconductor substrate;forming a nanowire material above said at least one fin;forming a hard mask layer above said at least one fin;forming a first directed self-assembly material above said hard mask layer;patterning said hard mask layer using a portion of said first directed self-assembly material as an etch mask to expose a portion of said nanowire material; andetching said nanowire material using said hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of said at least one fin, wherein at least one dimension of said substantially vertical nanowire is defined by an intrinsic pitch of said first directed self-assembly material.2. The method of claim 1 , further comprising:forming a recess in said at least one fin;forming said nanowire material and said hard mask layer in said recess; andforming said first directed self-assembly material above said hard mask layer.3. The method of claim 2 , further comprising:forming an insulating layer surrounding at least a portion of said at least one fin; andforming said recess in said at least one fin and in said insulating layer.4. The method of claim 3 , further comprising removing portions of said insulating layer disposed adjacent said ...

MULTIPLE DIRECTED SELF-ASSEMBLY MATERIAL MASK PATTERNING FOR FORMING VERTICAL NANOWIRES

A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material. 1. A method , comprising:forming a first directed self-assembly material above a substrate;patterning said substrate using said first directed self-assembly material to define at least one fin in said substrate;forming a second directed self-assembly material above said at least one fin to expose a top surface of said at least one fin; andforming a substantially vertical nanowire on said top surface of said at least one fin, wherein at least a first dimension of said vertical nanowire is defined by an intrinsic pitch of said first directed self-assembly material and a second dimension of said vertical nanowire is defined by an intrinsic pitch of said second directed self-assembly material.2. The method of claim 1 , wherein patterning said substrate further comprises:forming a hard mask layer above said substrate;patterning said hard mask layer using said first directed self-assembly layer as an etch mask to expose said substrate;removing said first directed self-assembly material; andpatterning said substrate using said hard mask layer as en etch mask to define said at least one fin.3. The method of claim 2 , wherein said hard mask layer comprises a first film stack having a plurality of layers claim 2 , and the method further comprises:forming said first directed self-assembly layer ...

METHODS OF FORMING BOTTOM AND TOP SOURCE/DRAIN REGIONS ON A VERTICAL TRANSISTOR DEVICE

One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure. 1. A method of forming a vertical transistor device , the method comprising:forming a vertically oriented channel semiconductor structure above a substrate;performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during said epi deposition process; andafter performing said epi deposition process, forming a gate structure around a portion of said vertically oriented channel semiconductor structure positioned vertically between said bottom source/drain region and said top source/drain region.2. The method of claim 1 , wherein performing said epi deposition process comprises performing said epi deposition process to simultaneously form an entirety of said bottom source/drain region and an entirety of said top source/drain region during said epi deposition process.3. The method of claim 1 , wherein performing said epi deposition process comprises performing said epi deposition process to simultaneously form an upper portion of said bottom source/drain region and an entirety of said top source/drain region during said epi deposition process.4. The method of claim 1 , wherein said vertically oriented channel semiconductor structure and said substrate comprise different semiconductor materials.5. The method of claim 1 , wherein forming said vertically oriented channel semiconductor structure above said substrate comprises performing at least one etching process on said ...

METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE

One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure. 1. A method of forming a vertical transistor device , the method comprising:forming a plurality of layers of material above a bottom source/drain (S/D) layer of semiconductor material that is positioned above a semiconductor substrate;performing at least one etching process to define a cavity in said plurality of layers of material, wherein a portion of said bottom source/drain (S/D) layer of semiconductor material is exposed at a bottom of said cavity;performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on said bottom source/drain (S/D) layer of semiconductor material and in said cavity and a top source/drain (S/D) layer of semiconductor material above said vertically oriented channel semiconductor structure;after performing said at least one epi deposition process, removing at least one of said plurality of layers of material to thereby expose an outer perimeter surface of said vertically oriented channel semiconductor structure; andforming a gate structure around said exposed ...

METHODS, APPARATUS AND SYSTEM FOR SELF-ALIGNED RETROGRADE WELL DOPING FOR FINFET DEVICES

At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions. 1. A method , comprising:forming a plurality of fins of a transistor;forming a nitride cap layer on said plurality of fins;forming an N-type doped region in a first portion of said plurality of fins;forming a P-type doped region in a second portion of said plurality of fins;performing a shallow trench isolation (STI) fill process for depositing an STI material on said plurality of fins;performing a fin reveal process for removing said STI material to a predetermined level; andperforming a cap strip process for removing said nitride cap layer for forming a fin reveal position that is self-aligned with said P-type and N-type doped regions.2. The method of claim 1 , wherein forming said plurality of fins of a transistor comprises:forming a silicon layer;forming a nitride layer over said silicon layer;forming a fin hard mask nitride layer over said nitride layer;forming a plurality of fin hard mask oxide features over said fin hard mask nitride layer; andperforming a partial fin etch process.3. The method of claim 2 , further comprising:performing a fin nitride reactive ion (ME) etching process for removing horizontal portions of said nitride cap;performing an oxide ME process for removing said fin hard mask oxide features; andperforming a ...

SELF-ALIGNED CONTACTS FOR VERTICAL FIELD EFFECT TRANSISTOR CELL HEIGHT SCALING

A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts. 1. A method of forming a vertical FinFET device , comprising:forming a hard mask over a semiconductor substrate;forming a fin over the semiconductor substrate using the hard mask as an etch mask;forming a bottom source/drain region over the semiconductor substrate, where a lower portion of the fin is in contact with the bottom source/drain region;forming a gate stack over sidewalls of the fin, the gate stack extending laterally over the bottom source/drain region on at least one side of the fin, wherein the gate stack comprises a gate dielectric and a gate conductor formed over the gate dielectric;etching an opening in the hard mask and through a portion of the fin to expose an endwall of the fin and a top surface of the bottom source/drain region laterally adjacent to the endwall;forming a sidewall spacer within the opening, wherein the sidewall spacer is formed over the exposed endwall of the fin;forming a top source/drain region over an upper portion of the fin and a top source/drain metallization layer over the top source/drain region; andforming a bottom source/drain metallization layer over the bottom source drain region, wherein the top source/drain metallization layer is formed over a first side of the sidewall spacer and the bottom source/drain metallization layer is formed over a second side of the sidewall spacer opposite to the first side.2. The method of claim 1 , further comprising forming a bottom spacer over the bottom source/ ...

Method of forming vertical field effect transistors with self-aligned gates and gate extensions and the resulting structure

Disclosed is a method of forming an integrated circuit (IC) that incorporates multiple vertical field effect transistors (VFETs) (e.g., in a VFET array). In the method, self-aligned gates for each pair of VFETs and a self-aligned gate extension for contacting those self-aligned gates are essentially simultaneously formed such that the gates wrap around a pair of semiconductor fins, which are in end-to-end alignment, and such that the gate extension fills the space between adjacent ends of those semiconductor fins. By forming self-aligned gates and a self-aligned gate extension for a pair of VFETs, the method avoids the need for lithographically patterning extension cut isolation regions between adjacent pairs of VFETs in a VFET array. Thus, the method enables implementation of VFET array designs with a reduced fin pitch without incurring defects caused, for example, by overlay errors. Also disclosed herein is an IC formed according to the method.

NEGATIVE CAPACITANCE MATCHING IN GATE ELECTRODE STRUCTURES

A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material. 1. A semiconductor device , comprising: a floating gate electrode portion;', 'a negative capacitor portion;', 'a ferroelectric material capacitively coupling said floating gate electrode portion to said negative capacitor portion;', 'a first conductive material positioned between said floating gate electrode portion and said ferroelectric material, wherein a first portion of said first conductive material is embedded in and laterally surrounded by said floating gate electrode portion; and', 'a second conductive material positioned between said first portion of said first conductive material and said ferroelectric material, wherein said second conductive material is embedded in and laterally surrounded by a second portion of said first conductive material., 'a gate electrode structure positioned adjacent to a channel region of a transistor element, said gate electrode structure comprising2. The semiconductor device of claim 1 , wherein said first conductive material is different from said second conductive material.3. The semiconductor device of claim 1 , wherein said gate electrode structure further ...

NEGATIVE CAPACITANCE INTEGRATION THROUGH A GATE CONTACT

A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade. 1. A semiconductor device , comprising:a gate disposed over an active area of a semiconductor substrate and extending laterally over the semiconductor substrate outside of the active area;a gate contact disposed over the gate outside of the active area; anda ferroelectric layer disposed between the gate contact and the gate outside of the active area.2. The device of claim 1 , wherein the gate comprises a gate dielectric and a gate conductor disposed over the gate dielectric claim 1 , and the ferroelectric layer is disposed directly over the gate conductor.3. The device of claim 2 , wherein the gate conductor comprises tungsten.4. The device of claim 1 , further comprising a template layer disposed over the gate outside of the active area claim 1 , wherein the ferroelectric layer is disposed directly over the template layer.5. The device of claim 4 , wherein the template layer comprises titanium nitride or tantalum nitride.6. The device of claim 4 , wherein the template layer comprises a crystalline material having an average grain size of less than 10 nm.7. The device of claim 4 , wherein the template layer is adapted to promote crystallization and growth of grains within the ferroelectric layer.8. The device of claim 1 , further comprising a dielectric layer disposed over the gate claim 1 , wherein the gate contact is disposed within a trench that extends through the dielectric layer.9. The device of claim 8 , further comprising a conformal first electrode ...

SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET

A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region. 1. A method of forming a semiconductor structure , the method comprising:forming a first isolation region between fins of a first group of fins and between fins of a second group of fins, the first and second group of fins being formed in a bulk semiconductor substrate; andforming a second isolation region between the first group of fins and the second group of fins, the second isolation region extending through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.2. The method of claim 1 , wherein forming the first isolation region comprises:conformally depositing a first dielectric layer above the bulk semiconductor substrate and between the fins of the first and second group of fins.3. The method of claim 1 , wherein forming the second isolation region comprises:forming the second isolation region self-aligned with respect to the first and second group of fins.4. The method of claim 2 , wherein conformally depositing the first dielectric layer comprises:depositing the first dielectric layer with a thickness of at least half the distance between two adjacent fins.5. ...

METHODS OF FORMING GATE ELECTRODES ON A VERTICAL TRANSISTOR DEVICE

One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures. 1. A method of forming a vertical transistor device , the method comprising:forming bottom source/drain (S/D) regions;forming a plurality of vertically oriented channel semiconductor structures above said bottom source/drain (S/D) regions;forming a gate insulation layer above said vertically oriented channel semiconductor structures;forming a conformal layer of conductive gate material above said gate insulation layer;etching said conformal layer of conductive gate material to define conductive gate spacers on sidewalls of said vertically oriented channel semiconductor structures; andforming top source/drain (S/D) regions above said vertically oriented channel semiconductor structures.2. The method of claim 1 , further comprising recessing said conductive gate spacers.3. The method of claim 2 , wherein said conductive gate spacers between a first pair of said vertically oriented channel semiconductor structures merge to define a merged conductive gate spacer claim 2 , and the method further comprises recessing said conductive gate spacers and said merged conductive gate spacer.4. The method of claim 1 , wherein a mask layer is formed on upper surfaces of said vertically oriented channel semiconductor structures claim 1 , and the method further ...

DEVICE ISOLATION IN FINFET CMOS

Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins. 14.-. (canceled)5. A method for forming a fin field effect transistor , the method comprising:forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of:doped silicon (Si), and doped silicon-germanium (Si—Ge);forming a set of replacement fins over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material, andforming a carbon liner over the retrograde doped layer.6. (canceled)7. The method according to claim 5 , further comprising:patterning a plurality of fins over the substrate;patterning an opening in a hard mask formed over the plurality of fins; andremoving one or more of the plurality of fins exposed by the opening in the hard mask to form a set of openings in a source trench isolation (STI) layer.8. The method according to claim 5 , the forming the retrograde doped layer comprising growing the retrograde doped layer over the substrate using an in situ doping process.9. The method according to claim 5 , the forming the set of replacement fins comprising growing the set of replacement fins over the retrograde doped layer.10. The method according to claim 9 , the growing the set of replacement fins comprising performing a chemical vapor deposition ...

METHODS OF FORMING SUBSTRATES COMPRISED OF DIFFERENT SEMICONDUCTOR MATERIALS AND THE RESULTING DEVICE

Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer. 1. A method , comprising:obtaining a structure comprised of a first layer of a first semiconductor material, a second layer of a second semiconductor material positioned above said first layer and a strain relief buffer layer positioned between said first and second layers;forming an opening in said second layer exposing as a floor of said opening a portion of said strain relief buffer layer, said opening having sidewalls;forming an insulating sidewall spacer on said sidewalls of said opening; andafter forming said spacer, forming a third semiconductor material in said opening, wherein said first, second and third semiconductor materials are different semiconductor materials.2. The method of claim 1 , wherein said first semiconductor material is comprised of silicon claim 1 , germanium or silicon germanium claim 1 , said second semiconductor material is comprised of a III-V binary or ternary compound or a group IV element and said third semiconductor material is comprised of a III-V binary or ternary compound or a group IV element.3. The method of claim 1 , wherein said second semiconductor material is an N-type high electron mobility ...

METHOD AND STRUCTURE TO CONTROL CHANNEL LENGTH IN VERTICAL FET DEVICE

A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate. 1. A method of making a vertical FET device comprising:forming a plurality of fins over a semiconductor substrate, wherein the fins define an inter-fin spacing between sidewalls of adjacent fins;forming a hard mask over top surfaces of the fins;forming a gate dielectric directly over the sidewalls of the fins and over sidewalls of the hard masks;forming a gate conductor directly over the gate dielectric, wherein the gate conductor thickness is substantially equal to the inter-fin spacing;isotropically etching the gate conductor to form a functional gate; andremoving the hard mask to expose the top surfaces of the fins and removing the gate dielectric formed over the sidewalls of the hard mask prior to isotropically etching the gate conductor.2. The method of claim 1 , further comprising forming bottom source/drain regions in the semiconductor substrate prior to forming the gate dielectric.3. The method of claim 2 , wherein the bottom source/drain regions are formed by ion implantation into the semiconductor substrate.4. The method of claim 2 , further comprising forming a bottom spacer over the bottom source/drain regions prior to forming the gate dielectric.5. The method of claim 1 , wherein the gate conductor thickness over the sidewalls of the fins is substantially equal to the inter-fin spacing.6. The method of claim 1 , wherein the inter-fin spacing between adjacent fins is filled by the gate dielectric and the gate conductor.7. (canceled)8. A method of making a vertical FET ...

METAL LAYER ROUTING LEVEL FOR VERTICAL FET SRAM AND LOGIC CELL SCALING

Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively. 1. A method comprising:forming a source/drain (S/D) layer over a substrate;forming a blanket dielectric layer over the S/D layer;forming a metal routing layer over the blanket dielectric layer;patterning the metal routing layer;forming a replacement metal gate (RMG) stack over the S/D layer and the metal routing layer;forming a replacement fin trench through the RMG stack down to the S/D layer;forming a replacement fin stack in the replacement fin trench;forming a silicon nitride (SiN) cap over the replacement fin wider than the replacement fin;removing a portion of the RMG stack on each side of the SiN cap; andforming a gate all around (GAA) on a remaining portion of the RMG stack and around the replacement fin.2. The method according to claim 1 , comprising forming the S/D layer to a thickness of 5 nanometer (nm) to 50 nm.3. The method according to claim 1 , further comprising etching the blanket dielectric layer down to the S/D layer in designed contact areas prior to forming the metal routing layer.4. The method according to claim 1 , comprising patterning the metal routing layer to a width of 3 nm to 50 nm.5. The method according to ...

TRACK-DEPENDENT DECODING

In one embodiment, a method includes reading, using a plurality of read sensors of a magnetic head in a read channel of a tape drive, encoded data from a plurality of tracks of a magnetic tape medium simultaneously. Also, the method includes monitoring statistics for the read channel, the statistics monitored for the read channel including exponentially averaged mean squared error (MSE) or signal-to-noise ratio (SNR) for each simultaneously read track. Moreover, the method includes performing track-dependent erasure decoding on the encoded data based on detection of one or more time-varying signal quality issues associated with at least one of the plurality of tracks read simultaneously from the magnetic tape medium. The one or more time-varying signal quality issues are determined based on side information about reliability of detected bytes within C1 codewords of each simultaneously-read track. 1. A method , comprising:reading, using a plurality of read sensors of a magnetic head in a read channel of a tape drive, encoded data from a plurality of tracks of a magnetic tape medium simultaneously;monitoring statistics for the read channel, the statistics monitored for the read channel including exponentially averaged mean squared error (MSE) or signal-to-noise ratio (SNR) for each simultaneously read track; andperforming track-dependent erasure decoding on the encoded data based on detection of one or more time-varying signal quality issues associated with at least one of the plurality of tracks read simultaneously from the magnetic tape medium, the one or more time-varying signal quality issues being determined based on side information about reliability of detected bytes within C1 codewords of each simultaneously-read track,wherein the side information comprises C1 decoder performance falling below a predetermined threshold based on statistics accumulated for the C1 decoder during C1 decoding of the encoded data,wherein the statistics accumulated for the C1 decoder ...

Forming contacts for vfets

A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

POST-DECODING ERROR CHECK WITH DIAGNOSTICS FOR PRODUCT CODES

In one embodiment, a system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to perform iterative decoding on encoded data to obtain decoded data. The logic is also configured to perform post-decoding error diagnostics on a first portion of the decoded data in response to not obtaining a valid product codeword in the first portion after the iterative decoding of the encoded data. Other systems, methods, and computer program products for producing post-decoding error signatures are presented in accordance with more embodiments. 1. A system , comprising: perform iterative decoding on encoded data to obtain decoded data; and', 'perform post-decoding error diagnostics on a first portion of the decoded data in response to not obtaining a valid product codeword in the first portion after the iterative decoding of the encoded data., 'a controller and logic integrated with the controller, executable by the controller, or integrated with and executable by the controller, the logic being configured to2. The system as recited in claim 1 , wherein at least three decoding operations are performed in the iterative decoding.3. The system as recited in claim 1 , wherein the decoding comprises initial C1 decoding followed by C2 decoding followed by C1 decoding again.4. The system as recited in claim 1 , wherein the decoding comprises initial C2 decoding followed by C1 decoding followed by C2 decoding again.5. The system as recited in claim 1 , wherein the logic configured to perform post-decoding error diagnostics on the decoded data is further configured to identify an error signature in the decoded data.6. A controller-implemented method claim 1 , the method comprising:performing iterative decoding on encoded data to obtain decoded data; andperforming post-decoding error diagnostics on a first portion of the decoded data in response to not obtaining a valid product codeword in the first portion after the iterative ...

Particle removal with minimal etching of silicon-germanium

Particle-clean formulations and methods for semiconductor substrates use aqueous solutions of tetraethylammonium hydroxide (“TEAH,” CHNO) with or without hydrogen peroxide (HO). The solution pH ranges from 8-12.5. At process temperatures between 20-70 C, the TEAH solutions have been observed to remove particles from silicon-germanium (SiGe) with 20-99% Ge content in 15-300 seconds with very little etching (SiGe etch rates<1 nm/min). 1. A method of cleaning a substrate , the method comprising:providing a substrate; andexposing the substrate to a TEAH solution;{'sub': 2', '8', '21, 'wherein the TEAH solution comprises water (HO) and tetraethylammonium hydroxide (TEAH, CHNO)'}{'sub': '2', 'wherein a water (HO): TEAH ratio of the TEAH solution is between about 90:1 and 110:1; and'}wherein a pH of the TEAH solution is between 8 and 12.5.2. The method of claim 1 , wherein the substrate comprises a silicon-germanium (SiGe) compound.3. The method of claim 2 , wherein the SiGe compound is between about 20% and 99% Ge.4. The method of claim 2 , wherein the SiGe compound is about 25% or about 50% Ge.5. The method of claim 2 , wherein the SiGe compound is exposed on at least part of a surface of the substrate.6. The method of claim 2 , wherein the TEAH solution etches the SiGe compound at a rate less than 3 nm/min.7. The method of claim 2 , wherein the TEAH solution etches the SiGe compound at a rate less than 1 nm/min.8. The method of claim 2 , wherein the TEAH solution etches the SiGe compound at a rate less than 0.1 nm/min.9. The method of claim 2 , wherein the TEAH solution etches the SiGe compound at a rate less than 0.01 nm/min.10. The method of claim 1 , wherein the substrate is exposed to the TEAH solution by immersion in a bath.11. The method of claim 1 , wherein the substrate is exposed to the TEAH solution in a spin-cleaning apparatus.12. The method of claim 1 , wherein the substrate is exposed to the TEAH solution at a process temperature between about 25 C and ...

METHODS OF FORMING TRANSISTOR STRUCTURES

Methods for fabricating transistor structures are provided, the methods including: forming a fin structure with an upper fin portion and a lower fin portion, the upper fin portion including a sacrificial material; forming a gate structure over the fin; selectively removing the upper fin portion to form a tunnel between the gate structure and lower fin portion; and providing a channel material in the tunnel to define the channel region of the gate structure. The sacrificial material may be a material that can be selectively etched without etching the material of the lower fin portion. The channel material may further be provided to form source and drain regions of the transistor structure, which may result in a junctionless FinFET structure. 1. A method comprising: forming a fin above a substrate, the fin having a lower fin portion and an upper fin portion, the upper fin portion comprising a sacrificial material;', 'forming a gate structure over the fin;', 'selectively removing the upper fin portion, the selectively removing forming a tunnel between the gate structure and the lower fin portion; and', 'providing a channel material in the tunnel, the channel material forming a channel region of the gate structure., 'facilitating fabricating a transistor structure, the facilitating fabricating comprising2. The method of claim 1 , further comprising providing the channel material over a first part of the lower fin portion external a first side of the gate structure and over a second part of the lower fin portion external a second side of the gate structure claim 1 , the channel material over the first part of the lower fin portion forming a source region of the transistor structure contacting the channel region claim 1 , and the channel material over the second part of the lower fin portion forming a drain region of the transistor structure contacting the channel region.3. The method of claim 2 , wherein the channel material comprising the source region claim 2 , the ...

Finfet device including a uniform silicon alloy fin

A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

MICROCODE DATA RECOVERY STRATEGIES FOR USE OF ITERATIVE DECODE

Various embodiments for data error recovery in a tape storage system, by a processor device, are provided. In one embodiment, a method comprises modifying erasure control configuration settings upon rereading a buffered dataset having passed through at least one microcode-initiated iterative decode cycle. Xmicrocode-initiated iterative decode cycles are initiated on the buffered dataset while the tape is stopped, where x comprises at least one of a plurality of the microcode-initiated iterative decode cycles. The x microcode-initiated decode cycles are initiated on the buffered dataset until a predetermined error correction threshold is reached. 1. A method for data error recovery in a tape storage system , by a processor device , comprising:in a tape storage system, modifying erasure control configuration settings upon rereading a buffered dataset having passed through at least one microcode-initiated iterative decode cycle; andinitiating x microcode-initiated iterative decode cycles on the buffered dataset while the tape is stopped; wherein x comprises at least one of a plurality of the microcode-initiated iterative decode cycles and the x microcode-initiated decode cycles are initiated on the buffered dataset until a predetermined error correction threshold is reached.2. The method of claim 1 , further including initializing the at least one hardware-initiated iterative decode cycle and the at least one microcode-initiated iterative decode cycle on the buffered dataset when an uncorrectable read error occurs.3. The method of claim 1 , further including modifying the erasure control configuration settings using error flags and pointers generated from the at least one microcode-initiated iterative decode cycle on a consequent microcode-initiated iterative decode cycle.4. The method of claim 1 , further including initiating m hardware-initiated iterative decode cycles and n microcode-initiated iterative decode cycles on the buffered dataset while tape is at speed; ...

ITERATIVE DECODE AND POST-DECODE MICROCODE CUT AND PASTE OPTIMIZATION

Various embodiments for data error recovery in a tape storage system, by a processor device, are provided. In one embodiment, a method comprises, in a tape storage system using an iterative hardware and microcode decoder, initializing at least one iterative decode cycle on the buffered dataset when an uncorrectable read error occurs; and for a next iterative decode cycle, building upon data corrections obtained in a previous iterative decode cycle. 1. A method for data error recovery in a tape storage system , by a processor device , comprising:in a tape storage system using an iterative hardware and microcode decoder, initializing at least one iterative decode cycle on the buffered dataset when an uncorrectable read error occurs; andfor a next iterative decode cycle, building upon data corrections obtained in a previous iterative decode cycle.2. The method of claim 1 , further including initializing a microcode cut/paste algorithm on a buffered dataset; wherein a most corrected dataset recovered by the at least one iterative decode cycle is cut and pasted over a dataset resident in a reserved buffer segment.3. The method of claim 2 , further including initializing the at least iterative decode cycle on the buffered dataset until a predetermined error correction threshold is reached.4. The method of claim 3 , further including claim 3 , upon reaching the predetermined error correction threshold claim 3 , initializing the microcode cut/paste algorithm on the buffered dataset.5. The method of claim 4 , further including refreshing correction flags and pointers used by the cut/paste algorithm for correction improvement of the dataset resident in the reserved buffer segment.6. The method of claim 5 , further including merging C1 data rows into the dataset resident in the reserved buffer segment for recalling preceding data corrections for use on proceeding data segments by the microcode cut/paste algorithm.7. The method of claim 4 , further including claim 4 , upon a ...

METHODS OF FORMING EPITAXIAL SEMICONDUCTOR MATERIAL ON SOURCE/DRAIN REGIONS OF A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES

One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a <100> crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin. 1. A device , comprising:a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of said fin is positioned substantially in a <100> crystallographic direction of said crystalline structure of said substrate;a gate structure positioned around said fin;an outermost sidewall spacer positioned adjacent opposite sides of said gate structure; andan epi semiconductor material formed around portions of said fin positioned laterally outside of said outermost sidewall spacers in source/drain regions of said device, wherein said epi semiconductor material has a substantially uniform thickness along said sidewalls of said fin.2. The device of claim 1 , wherein said substrate is a (100) substrate claim 1 , said substrate fin has a long axis claim 1 , wherein said long axis of said fin is positioned in a <100> crystallographic direction of said (100) substrate.3. The device of claim 2 , wherein said epi semiconductor material is positioned around an upper surface of said fin and wherein an upper surface of said epi semiconductor material that is positioned above said upper surface of said fin has a substantially planar surface.4. The device of claim 3 , wherein an upper surface of said fin is positioned in a <001> crystallographic direction of said (100) substrate.5. The device of ...

UNIFORM BOTTOM SPACER FOR VFET DEVICES

Vertical field effect transistor (VFET) structures and methods of fabrication include a bottom spacer having a uniform thickness. The bottom spacer includes a bilayer portion including a first layer formed of an oxide, for example, and a second layer formed of a nitride, for example, on the first layer, and a monolayer portion of a fourth layer of a nitride for example, immediately adjacent to and intermediate the fin and the bilayer portion. 1. A vertical field effect transistor (VFET) structure comprising:one or more vertically oriented fins extending from a substrate; anda bottom spacer layer on the substrate having a uniform thickness less than a vertical height of the one or more vertically oriented fins, the bottom spacer layer comprising a bilayer portion including an oxide layer and a nitride layer on the oxide layer, and a monolayer portion of a nitride intermediate the fin and the bilayer portion.2. The VFET structure of claim 1 , wherein the nitride layer in the bilayer portion is at least twice a thickness of the oxide layer.3. The VFET structure of claim 1 , wherein the nitride in the monolayer portion is different from the nitride in the bilayer portion.4. The VFET structure of claim 1 , wherein the bilayer portion and the monolayer portion are deposited by atomic layer deposition.5. The VFET structure of claim 1 , wherein each of the one or more vertically oriented fins comprises a silicon borocarbonitride hardmask.6. The VFET structure of claim 1 , wherein the substrate comprises an epitaxy region claim 1 , wherein the one or more vertically oriented fined extend from the epitaxy region.7. The VFET structure of claim 6 , wherein the epitaxy region comprises dopants to define a bottom source/drain region for the VFET.8. The VFET structure of claim 1 , wherein the one or more vertically oriented fins extending from the substrate have a height dimension of about 5 nanometers (nm) to about 300 nm claim 1 , and a width dimension of about 5 nm to about 100 ...

Buglossoides 'MALIN'

A new and distinct plant named ‘MALIN’ characterized by vigorous plant growth and abundant side shoot development. Plants flower early in May and June and do not require vernalization. Seed germination rate is typically 80%. Seeds of the plant are used in the production of the oil commercially known Ahiflower oil. 1Buglossoides arvensis. A plant named ‘MALIN’ , representative seed deposited at the American Type Culture Collection (ATCC) having deposit Designation PTA-122229.2Buglossoides arvensis. seed as mentioned in .3Buglossoides arvensis. A plant part obtained from the plant of .4Buglossoides arvensis. A method of producing progeny plant comprising the steps of{'i': Buglossoides arvensis', 'Buglossoides arvensis, '(a) crossing the plant ‘MALIN’, representative seed having been deposited and having designation PTA-122229 as a female or male parent with another plant, and (b) selecting progeny.'}5Buglossoides arvensis. The method according to claim 4 , wherein the second plant is ‘MALIN’. The present invention relates to a new, distinct and stable hybrid of hereinafter referred it as ‘MALIN’. The present invention relates to seeds which are the ‘MALIN’, as well as, plants and the plant parts produced by these seeds which have all the morphological and physiological characteristics of the ‘MALIN’. The present invention also relates to methods for producing these seeds and plants of the ‘MALIN’. Furthermore, the present invention relates to method of producing progeny plants by crossing ‘MALIN’, as either the female or seed or male or pollen parent, with another plant and selecting progeny.The present invention relates to a new, distinct and stable variety of and hereinafter referred to by the variety denomination ‘MALIN’. The new ‘ MALIN’ originated from the process of selection of wild collected seed, which was germinated, observed selected and subsequently self-pollinated. Germination, selection and self-crossing were made as part of a controlled breeding program ...

METHODS OF FORMING MERGED SOURCE/DRAIN REGIONS ON INTEGRATED CIRCUIT PRODUCTS

A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region. 1. A method of forming a merged source/drain region , comprising:forming first and second vertically oriented channel semiconductor (VOCS) structures above a semiconductor substrate;forming a recess in said substrate between said first and second VOCS structures;forming a substantially horizontally-oriented P-type-doped semiconductor material in said recess;removing a first substantially horizontally-oriented portion of said substantially horizontally-oriented P-type-doped semiconductor material from within said recess while leaving a second substantially horizontally-oriented portion of said P-type-doped semiconductor material remaining in said recess; andforming a substantially horizontally-oriented N-type-doped semiconductor material in said recess laterally adjacent said second substantially horizontally-oriented portion of said P-type-doped semiconductor material, wherein said substantially ...

SEMICONDUCTOR DEVICE WITH METAL STRUCTURE UNDER AN ACTIVE LAYER

A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures. 1. A semiconductor device comprising:a substrate;a first semiconductor fin and a second semiconductor fin disposed over the substrate, the first and second semiconductor fins each having an upper portion and a width;epitaxial structures disposed over the upper portions of the first and second semiconductor fins, wherein the upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer;a metal structure between the active layer and the substrate, wherein the metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins;a first isolation material separating the metal structure from the active layer;a second isolation material separating the metal structure from the substrate; anda first contact electrically connecting the metal structure to the epitaxial structures.2. The semiconductor device of claim 1 , further comprising gate electrodes disposed over the semiconductor fins.3. The semiconductor device of claim 2 , further ...

VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion. 1. A structure , comprising:a vertical fin structure having a lower dopant region, an upper dopant region at an upper portion of the vertical fin structure and a channel region between the lower dopant region and the upper dopant region; anddoped semiconductor material provided on sides of the vertical fin structure at a lower portion, the lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.2. The structure of claim 1 , wherein the lower dopant region is a source region or a drain region.3. The structure of claim 1 , wherein the doped semiconductor material is provided in a recess in semiconductor material on the sides of the vertical fin structure.4. The structure of claim 3 , wherein the doped semiconductor material is an epitaxially grown doped semiconductor material that merges into the lower portion of the vertical fin structure claim 3 , the doped semiconductor material is Si:As claim 3 , Si:P or Si:CP for an NFET device and Si:B claim 3 , Si:Ga claim 3 , SiGe:B claim 3 , or SiGe:Ga for a PFET device.5. The structure of claim 3 , wherein the doped semiconductor material has a uniform dopant concentration.6. The structure of claim 3 , wherein the doped semiconductor material has a dopant gradient concentration claim 3 , with a lower dopant concentration at a bottom and sidewall of the ...

CONTROLLED JUNCTION TRANSISTORS AND METHODS OF FABRICATION

Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species. 114.-. (canceled)15. A semiconductor structure comprising:a semiconductor substrate;two doped regions formed on a semiconductor channel disposed on the semiconductor substrate, having a gap between them;a metal gate disposed on the semiconductor substrate over the gap, and extending over each of the two doped regions;a plurality of spacers formed adjacent to the metal gate and in contact with one of the two doped regions; anda cap region disposed on the metal gate.16. The semiconductor structure of claim 15 , wherein the plurality of spacers are comprised of silicon nitride.17. The semiconductor structure of claim 15 , wherein the plurality of spacers are comprised of SiBCN.18. The semiconductor structure of claim 15 , wherein the metal gate extends over each doped region by a distance ranging from about 3 nanometers to about 10 nanometers.19. The semiconductor structure of claim 15 , wherein each spacer of the plurality of spacers has a thickness ranging from about 3 nanometers to about 10 nanometers.20. The semiconductor structure of claim 15 , wherein the metal gate ...

METHOD, APPARATUS AND SYSTEM FOR IMPROVED NANOWIRE/NANOSHEET SPACERS

A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure. 1. A method , comprising:providing a semiconductor structure comprising a semiconductor substrate; at least one fin comprising one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and each of the second layers is more susceptible to oxidation than any of the first layers; and a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate;selectively oxidizing two portions of each of the second layers, wherein the two portions are exposed on the sidewalls of the fin;selectively stripping the two portions of each of the second layers, to yield a plurality of second layer recesses;depositing a second spacer material on at least the sidewalls of the fin, wherein the second spacer material fills the plurality of second layer recesses; andepitaxially growing a source/drain material from at least portions of each of the first layers exposed on the sidewalls of the fin.2. The method of claim 1 , wherein the first material is silicon and the second material is silicon/germanium (SiGe).3. The method of claim 1 , wherein the first spacer material comprises a low-k dielectric material.4. The method of claim 1 , wherein the ...

METHODS OF FORMING EMBEDDED SOURCE/DRAIN REGIONS ON FINFET DEVICES

One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench. 1. A method of forming embedded source/drain regions on a FinFET device comprised of a fin , a gate structure positioned around a section of said fin and a gate cap layer positioned above said gate structure , the method comprising:forming a sidewall spacer adjacent said gate structure;after forming said sidewall spacer, forming a layer of insulating material adjacent said sidewall spacer and above portions of said fin positioned laterally outside said sidewall spacer, said layer of insulating material having an upper surface that is substantially planar with an upper surface of said gate cap layer;performing a first recess etching process on said layer of insulating material to define a recessed layer of insulating material having a recessed upper surface, wherein at least an upper surface of said fin is exposed after said first recess etching process is completed;performing at least one second etching process to remove at least a portion of said fin and thereby define a recessed fin and a recessed fin trench positioned above said recessed fin, said recessed fin trench having said recessed layer of insulating material located adjacent opposite sides of said recessed fin trench; andperforming at least one epitaxial deposition process to form at least one epitaxial semiconductor material that is at least partially ...

DEVICE ISOLATION IN FINFET CMOS

Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins. 1. A semiconductor device comprising:a retrograde doped layer formed over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); anda set of replacement fins formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material.2. The semiconductor device according to claim 1 , further comprising a carbon liner between the retrograde doped layer and the set of replacement fins.3. The semiconductor device according to claim 1 , further comprising a set of silicon fins adjacent the set of replacement fins claim 1 , the set of silicon fins formed over the retrograde doped layer.4. The semiconductor device according to claim 1 , wherein the high mobility channel material comprises at least one of: Si claim 1 , and Si—Ge.5. A method for forming a fin field effect transistor claim 1 , the method comprising:forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge); andforming a set of replacement fins over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material.6. The method according to ...

VERTICAL FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACTS

A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts. 1. A vertical FinFET device , comprising:a fin disposed over a semiconductor substrate;a bottom source/drain region disposed over the semiconductor substrate, where a lower portion of the fin is in contact with the bottom source/drain region;a gate stack disposed over sidewalls of the fin, the gate stack extending laterally over the bottom source/drain region on at least one side of the fin,a top source/drain region disposed over an upper portion of the fin;a top source/drain metallization layer in electrical contact with the top source/drain region;a bottom source/drain metallization layer in electrical contact with the bottom source/drain region; anda sidewall spacer disposed over an endwall of the fin, wherein the sidewall spacer is disposed between the top source/drain metallization layer and the bottom source/drain metallization layer.2. The vertical FinFET device of claim 1 , wherein the top source/drain metallization layer is over a first side of the sidewall spacer and the bottom source/drain metallization layer is formed over a second side of the sidewall spacer opposite to the first side.3. The vertical FinFET device of claim 1 , wherein the sidewall spacer is disposed directly over the endwall of the fin.4. The vertical FinFET device of claim 1 , wherein the sidewall spacer thickness is 4 to 20 nm.5. The vertical FinFET device of claim 1 , wherein the sidewall spacer is disposed over the entire endwall surface of the fin.6. The ...

VERTICAL NANOWIRES FORMED ON UPPER FIN SURFACE

One illustrative device includes, among other things, at least one fin defined in a semiconductor substrate and a substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of the at least one fin. 1. A semiconductor device , comprising:at least one fin defined in a semiconductor substrate; anda substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of said at least one fin.2. The device of claim 1 , further comprising:a plurality of nanowires each having an oval-shaped cross-section disposed on said top surface along a length of said at least one fin.3. The device of claim 2 , wherein said at least one fin is one of a plurality of fins defined in said semiconductor substrate claim 2 , further comprising:a plurality of substantially vertical nanowires having oval-shaped cross-sections, each disposed on a top surface of a respective fin; anda dielectric material disposed between adjacent fins.4. The device of claim 1 , wherein a width of said substantially vertical nanowire is less than a width of said at least one fin.5. The device of claim 1 , wherein said substantially vertical nanowire comprises an epitaxial material.6. The device of claim 1 , wherein said oval-shaped cross-section comprises a circular cross-section.7. The device of claim 1 , wherein said substantially vertical nanowire comprises a silicon alloy.8. The device of claim 1 , wherein said at least one fin and said substantially vertical nanowire comprise different semiconductor materials.9. The device of claim 1 , wherein said substantially vertical nanowire has a first long axis extending in a direction perpendicular to a second long axis of said at least one fin.10. A semiconductor device claim 1 , comprising:at least one fin defined in a semiconductor substrate; anda substantially vertical nanowire having an oval-shaped cross-section disposed on a top surface of said at least one fin, wherein said substantially vertical ...

RETROGRADE DOPED LAYER FOR DEVICE ISOLATION

Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins. 1. A method for forming a device , the method comprising:forming a retrograde doped layer over a substrate, the retrograde doped layer comprising one of: doped silicon (Si), and doped silicon-germanium (Si—Ge);forming a set of high mobility channel fins over the retrograde doped layer, each of the set of high mobility channel fins comprising at least one of: Si, and Si—Ge; andforming a set of silicon fins adjacent the set of high mobility channel fins.2. The method according to claim 1 , further comprising forming a carbon liner over the retrograde doped layer.3. The method according to claim 1 , the forming the retrograde doped layer comprising performing an in situ doping process.4. The method according to claim 3 , the forming the set of high mobility channel fins comprising:depositing the high mobility channel material over the retrograde doped layer;patterning the high mobility channel material and the substrate; andetching the high mobility channel material and the substrate.5. The method according to claim 4 , the depositing comprising growing the high mobility channel material using a chemical vapor deposition of at least one of: Si claim 4 , and Si—Ge.6. The method according to claim 2 , the forming the ...

SUB-THERMAL SWITCHING SLOPE VERTICAL FIELD EFFECT TRANSISTOR WITH DUAL-GATE FEEDBACK LOOP MECHANISM

Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess. 1. A method for fabricating a feedback field effect transistor , comprising:receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin;forming a bottom spacer on a portion of the first source/drain;forming a first gate upon the bottom spacer;forming a sacrificial spacer upon the first gate;forming a gate spacer on the first gate from the sacrificial spacer;forming a second gate on the gate spacer, the gate spacer disposed between and in contact with the first gate and the second gate, wherein the first gate, the gate spacer, and the second gate form a portion of a dual-gate feedback loop mechanism of the feedback field effect transistor;forming a top spacer around portions of the second gate and hard mask;forming a recess in the top spacer and hard mask; andforming a second source/drain in the recess.2. The method of claim 1 , further comprising:depositing a dielectric material upon portions of the bottom spacer, first gate, and second gate.3. The method of claim 2 , wherein the dielectric material includes an inter-layer dielectric material.4. The ...

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

Efficient multichannel data format using variable-length headers

In one embodiment, a computer-implemented method includes writing a data set to a first write section of a magnetic medium and rewriting at least some of the data set as rewritten CWI-4 sets to a rewrite section of the magnetic medium. The data set includes a plurality of sub data sets, each sub data set including a data array organized in rows and columns. Each row of the data array includes four interleaved C1 codewords (a CWI-4). A first portion of the data set is stored as CWI-4 sets to the first write section of the magnetic medium with first headers. Each rewritten CWI-4 set is stored to the rewrite section of the magnetic medium as a number of rewritten CWI-4s having corresponding rewrite headers. Also, a length of any one of the rewrite headers is greater than a length of any one of the first headers.

EFFICIENT MULTICHANNEL DATA FORMAT USING VARIABLE-LENGTH HEADERS

In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. The program instructions are executable by a tape drive to cause the tape drive to perform a method. The method includes writing data to a first write section of a magnetic tape, at least some of the data being written in association with first headers. The method also includes selecting some of the data for rewrite based on detected errors. Moreover, the method includes rewriting the selected data to a rewrite section of the magnetic tape, the rewritten data being written in association with rewrite headers. A length of each of the rewrite headers is greater than a length of each of the first headers. 1. A computer program product , the computer program product comprising a computer readable storage medium having program instructions embodied therewith , wherein the computer readable storage medium is not a transitory signal per se , the program instructions executable by a tape drive to cause the tape drive to perform a method , the method comprising:writing data to a first write section of a magnetic tape, at least some of the data being written in association with first headers;selecting some of the data for rewrite based on detected errors; andrewriting the selected data to a rewrite section of the magnetic tape, the rewritten data being written in association with rewrite headers,wherein a length of each of the rewrite headers is greater than a length of each of the first headers.2. The computer program product as recited in claim 1 , wherein the data comprises at least one data set claim 1 , the at least one data set comprising a plurality of sub data sets claim 1 , each sub data set comprising a data array organized in rows and columns claim 1 , each row of the data array comprising four interleaved C1 codewords (a CWI-4) claim 1 , wherein the data is ...

Bitcell layout for a two-port sram cell employing vertical-transport field-effect transistors

Structures for a bitcell of a two-port static random access memory (SRAM) and methods for forming a structure for a bitcell of a two-port SRAM. A storage element of the SRAM includes a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a fin, a first pull-down (PD) VTFET with a fin that is aligned in a first row with the fin of the first PU VTFET, a second PU VTFET with a fin, and a second PD VTFET with a fin that is aligned in a second row with the fin of the second PU VTFET. The structure further includes a read port coupled with the storage element. The read port includes a read port pull-down (RPD) VTFET with a fin and a read port access (RPG) VTFET with a fin that is aligned in a third row with the fin of the RPG VTFET.

METHODS FOR THE PRODUCTION OF INTEGRATED CIRCUITS COMPRISING EPITAXIALLY GROWN REPLACEMENT STRUCTURES

Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases. 1. A method of producing an integrated circuit comprising:forming dummy structures from a semiconductor substrate;forming shallow trench isolation regions between the dummy structures, wherein the shallow trench isolation regions comprise a core and a liner overlying the core;etching the dummy structures to expose structure bases;precleaning the structure bases; andepitaxially growing replacement structures overlying the structure bases.2. The method of wherein forming the shallow trench isolation regions further comprises forming the liner between the core and the dummy structures.3. The method of wherein epitaxially growing the replacement structures comprises epitaxially growing replacement fins claim 1 , wherein the replacement fins comprise a compound from Group III of the Periodic Table.4. The method of wherein forming the shallow trench isolation regions further comprises forming the core comprising silicon oxide.5. The method of wherein forming the shallow trench isolation regions comprises forming the liner comprising silicon nitride.6. The method of wherein precleaning the structure bases comprises precleaning the structure bases such that a shallow trench isolation height changes by 10 percent or less during precleaning.7. The method of wherein forming the shallow trench isolation regions comprises;depositing a liner material overlying the dummy structures and the core.8. The method of wherein etching the dummy structures comprises;forming a cap overlying the ...

PUNCH-THROUGH-STOP AFTER PARTIAL FIN ETCH

A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s). 1. A method , comprising:providing a starting semiconductor structure, the structure comprising a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material and a hard mask layer over both regions;creating at least one partial fin in each region;creating a punch-through-stop (PTS) in each region;causing each PTS to diffuse across a top portion of and below a top surface of the substrate; andcreating at least one full fin in each region from the at least one partial fin in each region.2. The method of claim 1 , wherein creating the at least one partial fin in each region comprises partially etching both regions of the starting structure.3. The method of claim 2 , wherein the partially etching stops at a bottom surface of the layer of p-type semiconductor material.4. The method of claim 1 , further comprising creating a conformal liner over the structure after creating the at least one partial fin in each region and prior to creating a PTS in each region.5. The method of claim 4 , wherein creating the conformal liner comprises:creating a lower layer of dielectric ...

METHODS OF FORMING A GATE STRUCTURE ON A VERTICAL TRANSISTOR DEVICE

One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer. 1. A method of forming a gate structure on a vertical transistor device , the method comprising:forming a vertically oriented channel semiconductor structure;forming an initial multi-layered sidewall spacer around an entire perimeter of said vertically oriented channel semiconductor structure, wherein said initial multi-layered sidewall spacer has an initial height and comprises a non-sacrificial innermost first spacer comprised of a high-k insulating material, a sacrificial outermost spacer and at least one non-sacrificial second spacer comprised of a metal-containing material positioned between said non-sacrificial innermost first spacer and said sacrificial outermost spacer;performing at least one recess etching process on said initial multi-layered sidewall spacer to thereby define a recessed multi-layered sidewall spacer having a recessed height that is less than said initial height of said initial multi-layered sidewall spacer;performing at least one etching process to remove at least a portion of said sacrificial outermost spacer from said recessed multi-layered sidewall spacer while leaving said at least one non-sacrificial second spacer and said non-sacrificial innermost first spacer in position and thereby define a replacement gate ...

SEMICONDUCTOR DEVICES INCLUDING AN ELECTRICALLY-DECOUPLED FIN AND METHODS OF FORMING THE SAME

Semiconductor devices including a fin and method of forming the semiconductor devices are provided herein. In an embodiment, a method of forming a semiconductor device includes forming a fin overlying a semiconductor substrate. The fin is formed by epitaxially-growing a semiconductor material over the semiconductor substrate, and the fin has a first portion that is proximal to the semiconductor substrate and a second portion that is spaced from the semiconductor substrate by the first portion. A gate structure is formed over the fin and the semiconductor substrate. The first portion of the fin is etched to form a gap between the second portion and the semiconductor substrate. 1. A method of forming a semiconductor device , wherein the method comprises:forming a fin overlying a semiconductor substrate, wherein forming the fin comprises epitaxially-growing a semiconductor material over the semiconductor substrate and wherein the fin has a first portion proximal to the semiconductor substrate and a second portion spaced from the semiconductor substrate by the first portion;forming a gate structure over the fin and the semiconductor substrate;etching the first portion of the fin to form a gap between the second portion and the semiconductor substrate.2. The method of claim 1 , wherein etching the first portion of the fin comprises etching the first portion with the gate structure supporting the second portion to maintain the gap after etching.3. The method of claim 1 , wherein the gate structure is further defined as a dummy gate structure claim 1 , and wherein the method further comprises removing the dummy gate structure after etching the first portion of the fin.4. The method of claim 1 , further comprising filling the gap with a flowable dielectric material.5. The method of claim 1 , wherein forming the fin comprises patterning a dummy fin in the semiconductor substrate.6. The method of claim 5 , further comprising depositing a dielectric material adjacent to the ...

METHODS, APPARATUS, AND SYSTEM FOR IMPROVED NANOWIRE/NANOSHEET SPACERS

A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure. 113.-. (canceled)14. A semiconductor structure , comprising:a semiconductor substrate;at least one fin, wherein the at least one fin comprises one or more first layers comprising a first material and one or more second layers comprising a second material, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers;a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate;a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, andan epitaxial source/drain material disposed on at least the exposed portions of each of the first layers.15. The semiconductor device of claim 14 , wherein the second material is more susceptible to oxidation than the first material.16. The semiconductor device of claim 14 , wherein the first material is silicon and the second material is silicon/germanium (SiGe).17. The semiconductor device of claim 14 , wherein the first spacer material comprises a low-k dielectric material.18. The semiconductor device of claim 14 , wherein the second spacer ...

VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH SELF-ALIGNED CONTACTS

Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack. 1. A structure comprising:a gate stack;an interlayer dielectric layer over the gate stack;a first contact extending vertically through the interlayer dielectric layer to a first section of the gate stack;a second contact extending vertically through the interlayer dielectric layer to a second section of the gate stack; anda dielectric pillar laterally arranged in the interlayer dielectric layer between the first contact and the second contact, and the dielectric pillar penetrating vertically through the gate stack and dividing the gate stack into the first section and the second section.2. The structure of wherein the dielectric pillar composed of a first dielectric material claim 1 , and the interlayer dielectric layer is composed of a second dielectric material that is removable by an etching process selective to the first dielectric material of the dielectric pillar.3. The structure of further comprising:a liner layer having a first section and a second section, the first section of the liner layer arranged between the first contact and the first section of the gate stack, and the second section of the ...

METHODS OF FABRICATING SEMICONDUCTOR FIN STRUCTURES

Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride. 1. A method comprising: providing a substrate structure comprising a first semiconductor material;', 'providing one or more fin stacks above the substrate structure, one fin stack of the one or more fin stacks comprising at least one semiconductor layer including a second semiconductor material;', 'depositing a conformal protective film over the one or more fin stacks and the substrate structure; and', 'etching the substrate structure using, at least in part, the one or more fin stacks as a mask to facilitate defining the one or more semiconductor fin structures, wherein the conformal protective film protects sidewalls of the at least one semiconductor layer from etching during the etching of the substrate structure., 'fabricating one or more semiconductor fin structures, the fabricating comprising2. The method of claim 1 , wherein the second semiconductor material is claim 1 , at least in part claim 1 , a different semiconductor material from the first semiconductor material.3. The method of claim 1 , wherein the ...

VERTICAL FET WITH SELF-ALIGNED SOURCE/DRAIN REGIONS AND GATE LENGTH BASED ON CHANNEL EPITAXIAL GROWTH PROCESS

A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators. 1. A method comprising:forming a fin extending from, and perpendicular to, a planar surface of a substrate, the fin includes a channel adjacent to the substrate and a hardmask distal to the substrate;forming notches in the channel;forming gate length limit insulators in each of the notches;forming a bottom source/drain in the planar surface of the substrate where the channel meets the planar surface; removing a portion of the hardmask to leave a top source/drain opening aligned with the channel; and', 'forming the top source/drain only in the top source/drain opening;, 'replacing the hardmask with a top source/drain byforming a bottom spacer on the bottom source/drain;forming a gate insulator on at least the channel;depositing a gate conductor on the gate insulator; andremoving a portion of the gate conductor on the fin that is further from the bottom spacer than a distance between the gate length limit insulators to leave a gate length of the gate conductor defined by the distance between the gate length limit insulators.2. The method according to claim 1 , the notches are formed in the channel where the channel meets the hardmask claim 1 , and where the channel meets the bottom ...

Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor

A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

SELF-ALIGNED CONTACT FOR VERTICAL FIELD EFFECT TRANSISTOR

Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer. 1. A method for forming a semiconductor device , the method comprising:forming a semiconductor fin vertically extending from a bottom source/drain region of a substrate;forming a conductive gate over a channel region of the semiconductor fin;forming a top source/drain region on a surface of the semiconductor fin;forming a top metallization layer on the top source/drain region; andforming a dielectric cap over the top metallization layer.2. The method of further comprising forming a bottom spacer between the bottom source/drain region and the conductive gate.3. The method of further comprising forming a top spacer on the conductive gate and adjacent to sidewalls of the semiconductor fin.4. The method of further comprising recessing the top metallization layer below a surface of the top spacer prior to forming the dielectric cap.5. The method of further comprising forming a bottom source/drain contact over the dielectric cap and on a portion of the bottom source/drain region claim 1 , wherein a portion of the dielectric cap is between the bottom source/drain contact and the top metallization layer.6. The method of further comprising forming a dielectric liner between the bottom source/drain contact and the conductive gate; wherein the dielectric cap and the dielectric liner prevent the bottom source/drain contact from electrically contacting the conductive gate.7. The method of further comprising forming a gate ...

FORMATION OF BOTTOM JUNCTION IN VERTICAL FET DEVICES

Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses. 1. A method for use in forming a vertical FinFET device , the method comprising: a semiconductor substrate;', 'a fin disposed on the semiconductor substrate, the fin having a top surface, and spaced-apart vertical sides;', 'a mask disposed over the top surface of the fin; and', 'at least one spacer disposed over the vertical sides of the fin;, 'providing an intermediate semiconductor structure comprisingremoving portions of the substrate to define spaced-apart recesses each extending below a respective one of the spacers;growing semiconductor material in the recesses for a source or a drain for a bottom junction in the vertical FinFET device;forming a gate structure adjacent to at least the vertical sides of the fin; andforming, above the top of the fin, the other of the source or the drain for a top junction in the vertical FinFET device.2. The method of wherein the removing comprises removing portions of the substrate beneath the spacers and beneath a portion of the fin to define the spaced-apart recesses claim 1 , and wherein the growing comprises growing the semiconductor material in the spaced-apart recesses beneath the spacers and beneath the portion of the fin.3. The method of wherein growing comprises epitaxially growing semiconductor material in the recesses.4. The method of wherein the removing comprises first removing vertical portions of the substrate adjacent to and below ...

SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET

A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region. 1. A semiconductor structure comprising:a first isolation region located between fins of a first group of fins and between fins of a second group of fins, the first and second group of fins being formed in a bulk semiconductor substrate; anda second isolation region between the first group of fins and the second group of fins, the second isolation region extending through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.2. The semiconductor structure of claim 1 , wherein the first isolation region separates each individual fin of the first and second group of fins from one another and the second isolation region separates the first group of fins from the second group of fins.3. The semiconductor structure of claim 1 , wherein the second isolation region and the first and second group of fins are separated by a portion of the first isolation region that has a length equivalent to half the distance between two adjacent fins.4. The semiconductor structure of claim 1 , wherein the first and second isolation regions comprise a dielectric material.5. The semiconductor ...

JUNCTION OVERLAP CONTROL IN A SEMICONDUCTOR DEVICE USING A SACRIFICIAL SPACER LAYER

Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers. 1. A method for providing junction overlap control in a semiconductor device , the method comprising:providing a gate over a substrate;forming a set of junction extensions adjacent the gate;forming a set of spacer layers along each of a set of sidewalls of the gate;removing the gate between the set of spacer layers to form an opening;removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap distance; andforming a replacement gate electrode within the opening.2. The method according to claim 1 , the forming the set of junction extensions comprising:forming a dummy layer over the substrate; anddoping the substrate through the dummy layer.3. The method according to claim 2 , the forming the set of spacer layers comprising:oxidizing the gate to grow the dummy layer on the set of sidewalls of the gate;removing the dummy layer from atop the set of junction extensions; andforming a gate oxide over the gate.4. The method according to claim 3 , ...

INTEGRATED CIRCUIT STRUCTURE WITH STEPPED EPITAXIAL REGION

Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin. 1. A method of forming an integrated circuit (IC) structure , the method comprising:removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, wherein the removing undercuts the sidewall spacer to expose an underlying sidewall of the semiconductor fin;forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer;removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region, wherein a height of the first region over the substrate is greater than a height of the second region over the substrate; andforming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.2. The method ...

METHOD FOR FORMING REPLACEMENT METAL GATE AND RELATED STRUCTURES

The present disclosure relates to methods for forming replacement metal gate (RMG) structures and related structures. A method may include: forming a portion of sacrificial material around each fin of a set of adjacent fins; forming a first dielectric region between the portions of sacrificial material; forming a second dielectric region on the first dielectric region; forming an upper source/drain region from an upper portion of each fin; removing only the second dielectric region and the sacrificial material; and forming a work function metal (WFM) in place of the second dielectric region and the sacrificial material. The semiconductor structure may include gate structures surrounding adjacent fins; a first dielectric region between the gate structures; a second dielectric region above the first dielectric region and between the gate structures; and a liner between the first dielectric region and the gate structures such that the second dielectric region directly contacts the gate structures. 1. A method of forming a replacement metal gate structure for an integrated circuit , the method comprising:providing an initial structure including a substrate, a first fin formed over the substrate and a second fin formed over the substrate, the first and second fins being laterally separated from one another;forming a first portion of a sacrificial material around the first fin, a second portion of the sacrificial material around the second fin, and a first dielectric region between the first and second portions of the sacrificial material, wherein an upper surface of the first portion of the sacrificial material is positioned below an upper surface of the first fin, an upper surface of the second portion of the sacrificial material is positioned below an upper surface of the second fin, and an upper surface of the first dielectric region is positioned below the upper surface of the first portion of the sacrificial material and below the upper surface of the second portion ...

Integrated multiple channel data reliability testing for a magnetic tape drive

Data reliability testing for a magnetic tape drive is conducted separately for the channels of a magnetic tape drive which write and read tracks of a multiple track magnetic tape. Memory stores testing data representing data separately written to tracks of a multiple track magnetic tape; each of a plurality of read channels reads data sensed by a tape head from a separate track of a magnetic tape; and error processing logic detects differences between data from each of a plurality of the read channels, and stored testing data of the memory representing data written to the same separate tracks.

Method and structure to control channel length in vertical FET device

A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.

Epitaxial structures in complementary field effect transistors

Eine integrierte Schaltungsstruktur, umfassend: Isolationselemente (103), die sich in ein Substrat (102) erstrecken; eine dielektrische Beschichtung (110), die zwischen den Isolationselementen und dem Substrat (102) angeordnet ist; Source/Drain-Bereiche (146) eines ersten Transistors (166), die die Isolationselemente kontaktieren, wobei sich die Isolationselemente von dem Substrat (102) zu den Source/Drain-Bereichen (146) des ersten Transistors (166) erstrecken; Isolationsschichten (144), die mit den Source/Drain-Bereichen (146) des ersten Transistors (166) in Kontakt stehen; Source/Drain-Bereiche (142) eines zweiten Transistors (162), die mit den Isolationsschichten (144) in Kontakt stehen, wobei der erste Transistor (166) zwischen dem zweiten Transistor (162) und dem Substrat (102) angeordnet ist, und wobei die Isolationsschichten (144) sich zwischen den Source/Drain-Bereichen (146) des ersten Transistors (166) und den Source/Drain-Bereichen (142) des zweiten Transistors (162) befinden; Kanalgebiete (114) des ersten Transistors (166), die mit den Source/Drain-Bereichen (146) des ersten Transistors (166) in Kontakt stehen und sich dazwischen erstrecken; Kanalgebiete (118) des zweiten Transistors (162), die mit den Source/Drain-Bereichen (142) des zweiten Transistors (162) in Kontakt stehen und sich dazwischen erstrecken; und einen Gateleiter (150), der Seiten des Kanalgebiets (114) des ersten Transistors (166) und des Kanalgebiets des zweiten Transistors (162) umgibt. An integrated circuit structure comprising: isolation elements (103) extending into a substrate (102); a dielectric coating (110) disposed between the insulating elements and the substrate (102); source/drain regions (146) of a first transistor (166) contacting the isolation elements, the isolation elements extending from the substrate (102) to the source/drain regions (146) of the first transistor (166); insulating layers (144) contacting the source/drain regions (146) of the first transistor (166); ...

Pointer control system

Complementary FETs with wrap around contacts and methods of forming same

The present disclosure relates generally to wrap around contact formation in source/drain regions of a semiconductor device such as an integrated circuit (IC), and more particularly, to stacked IC structures containing complementary FETs (CFETs) having wrap around contacts and methods of forming the same. Disclosed is a stacked IC structure including a first FET on a substrate, a second FET vertically stacked above the first FET, a dielectric layer above the second FET, and a spacer layer between FETs, wherein each FET has an electrically isolated wrap-around contact formed therearound.

Post-decoding error check with diagnostics for product codes

A system includes a controller and logic integrated with and/or executable by the controller. The logic is configured to perform iterative decoding on encoded data to obtain decoded data. At least three decoding operations are performed in the iterative decoding, with the decoding operations being selected from a group comprising：C1 decoding and C2 decoding. The logic is also configured to perform post-decoding error diagnostics on a first portion of the decoded data in response to not obtaining a valid product codeword in the first portion after the iterative decoding of the encoded data. Other systems, methods, and computer program products for producing post-decoding error signatures are also presented.

Track-dependent decoding

A tape drive includes a magnetic head having a plurality of read sensors, each read sensor being configured to read data simultaneously, a controller, and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read sensors, encoded data from a plurality of tracks of a magnetic tape medium simultaneously. The logic is also configured to perform track-dependent erasure decoding on the encoded data based on detection of one or more time-varying signal quality issues associated with at least one of the plurality of tracks read simultaneously from the magnetic tape medium. The time varying signal quality may be determined based on reliability of detected bytes within C1 codewords or number of run-length limited (RLL) error detection flags per C1 codeword. C2 decoding on a plurality of erasure enabled C1 codewords may be performed with C2 error and erasure decoding. Erasure pointers may be inserted in place of each C1 codeword when a probability of byte errors in the C1 codeword exceeds a threshold.

Transistors comprising doped region-gap-doped region structures and methods of fabrication

Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Symmetric arrangement of field plates in semiconductor devices

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

Insulated epitaxial structures in nanosheet complementary field effect transistors

Integrated circuit structures include isolation elements extending into a substrate, and source/drain regions of a first transistor contacting the isolation elements. The isolation elements extend from the substrate to the source/drain regions of the first transistor. Isolation layers contact the source/drain regions of the first transistor, and source/drain regions of a second transistor also contact the isolation layers. Thus, the isolation layers are between the source/drain regions of the first transistor and the source/drain regions of the second transistor. Channel regions of the first transistor contact and extend between the source/drain regions of the first transistor, and channel regions of the second transistor contact and extend between the source/drain regions of the second transistor. A gate conductor surrounds sides of the channel region of the first transistor and the channel region of the second transistor.

A shower tray moulding incorporating a filler

Asynchronous digital threshold detector for a digital data storage channel

A zero-crossing detector for asynchronous detection of threshold transitions in a digitally sampled signal waveform. The Asynchronous Digital Threshold Detector (ADTD) receives a digitized self-clocking data readback waveform and provides the relative location of a zero-crossing within the sample period where it occurs. The digital output, which is useful for recovering data and clock signals, is in a digital form that can be used directly by a certain class of asynchronous digital phase detector systems. The ADTD is entirely digital and can be embodied in a low power configuration using CMOS technology.

Epitaxial structures in complementary field effect transistors

Verfahren bilden integrierte Schaltungsstrukturen, die Isolationselemente, die sich in ein Substrat erstrecken, und Source/Drain-Bereiche eines ersten Transistors umfassen, die die Isolationselemente kontaktieren. Die Isolationselemente erstrecken sich von dem Substrat zu den Source/Drain-Bereichen des ersten Transistors. Isolationsschichten kontaktieren die Source/Drain-Bereiche des ersten Transistors und Source/Drain-Bereiche eines zweiten Transistors kontaktieren auch die Isolationsschichten. Demzufolge befinden sich die Isolationsschichten zwischen den Source/Drain-Bereichen des ersten Transistors und den Source/Drain-Bereichen des zweiten Transistors. Kanalgebiete des ersten Transistors kontaktieren die Source/Drain-Bereiche des ersten Transistors und erstrecken sich dazwischen. Kanalgebiete des zweiten Transistors kontaktieren die Source/Drain-Bereiche des zweiten Transistors und erstrecken sich dazwischen. Ein Gateleiter umgibt Seiten des Kanalgebiets des ersten Transistors und des Kanalgebiets des zweiten Transistors. Methods form integrated circuit structures that include isolation elements that extend into a substrate and source / drain regions of a first transistor that contact the isolation elements. The isolation elements extend from the substrate to the source / drain regions of the first transistor. Isolation layers contact the source / drain regions of the first transistor and source / drain regions of a second transistor also contact the isolation layers. As a result, the isolation layers are located between the source / drain regions of the first transistor and the source / drain regions of the second transistor. Channel regions of the first transistor contact the source / drain regions of the first transistor and extend therebetween. Channel regions of the second transistor contact the source / drain regions of the second transistor and extend therebetween. A gate conductor surrounds sides of the channel region of the first transistor and the ...

Fin pitch scaling and active layer isolation

A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

Recording multiple codeword sets during latency period

Writing data to magnetic tape is performed by receiving data from a host, establishing sub data sets, computing C1 and C2 ECC, forming Codeword Quad sets, writing a beginning Data Set Separator to a magnetic tape, writing a plurality of contiguous instances of the CQ Set to the magnetic tape and writing a closing DSS. The number of instances of each Codeword Pair is increased, thereby allowing the benefits of writing short tape records and improving reading reliability while reducing susceptibility to mis-tracking errors and large defects, and while reducing the negative impact on data reliability. Otherwise unused latency times are utilizing and therefore no performance penalty is incurred.

Formation of bottom junction in vertical FET devices

Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

Detection of inter-block gaps in a data recording system

Iii-v-verbindungshalbleiterschichtstapel mit durch eine haftstellenreiche schicht bereitgestellter elektrischer isolation

Halbleiterstrukturen umfassend eine elektrische Isolation und Verfahren zum Bilden einer Halbleiterstruktur umfassend eine elektrische Isolation. Ein Schichtstapel ist auf einem Halbleitersubstrat gebildet, das von einkristallinem Halbleitermaterial umfasst ist. Der Schichtstapel umfasst eine Halbleiterschicht, die von einem III-V-Verbindungshalbleitermaterial umfasst ist. Eine polykristalline Schicht ist in dem Halbleitersubstrat gebildet. Die polykristalline Schicht erstreckt sich lateral unter dem Schichtstapel.

Methods, apparatus, and system for improved nanowire/nanosheet spacers

A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.