Halbleiteranordnung auf Basis von Gallium-Nitrid und Verfahren zur Herstellung

Bipolartransistor.

Spannungs- und defektfreie fehlangepasste Epitaxialheterostrukturen und deren Herstellungsverfahren.

Gruppe-III-Nitrid-basierte ESD-Schutzvorrichtung

Vorrichtung zum Schutz vor elektrostatischen Entladungen, umfassend:eine erste Gruppe-III-Nitrid-p-i-n-Diode; undeine zweite Gruppe-III-Nitrid-p-i-n-Diode, die mit der ersten Gruppe-III-Nitrid-p-i-n-Diode in einer antiparallelen Anordnung verbunden ist, wobei die Anordnung eingerichtet ist,ein Spannungsklemmen bei 5V oder weniger unter Vorspannung in Durchlassrichtung entweder der ersten oder der zweiten Gruppe-III-Nitrid-p-i-n-Diode für transienten Strom sowohl in der Durchlass- als auch in der Sperrrichtung bereitzustellen,wobei die erste Gruppe-III-Nitrid-p-i-n-Diode eine erste intrinsische Gruppe-III-Nitridzone umfasst, die zwischen einer ersten Gruppe-III-Nitridzone vom n-Typ und einer ersten Gruppe-III-Nitridzone vom p-Typ angeordnet ist;die zweite Gruppe-III-Nitrid-p-i-n-Diode eine zweite intrinsische Gruppe-III-Nitridzone umfasst, die zwischen einer zweiten Gruppe-III-Nitridzone vom n-Typ und einer zweiten Gruppe-III-Nitridzone vom p-Typ angeordnet ist;die erste Gruppe-III-Nitridzone ...

Halbleitervorrichtung und Herstellungsverfahren dafür

Eine Halbleitervorrichtung, enthaltend:eine Nitridhalbleiterschicht, die ein Gruppe-III-V-Nitridhalbleitermaterial enthält;einen Gate-Isolierfilm, der über der Nitridhalbleiterschicht ausgebildet ist und ein Material mit großer Dielektrizitätskonstante enthält;eine Gate-Elektrode, die auf dem Gate-Isolierfilm ausgebildet ist; undeine Source-Elektrode eine Drain-Elektrode, undeine Basisschicht, die ein leitfähiges Nitridmaterial enthält, um wenigstens eine Unterseite des Gate-Isolierfilms unter der Gate-Elektrode zu bedecken,wobei die Basisschicht mit der Source-Elektrode und der Drain-Elektrode kontaktlos ist.

LAMINATED CHANNEL LAYER

SEMICONDUCTOR DEVICE

INFRARED LIGHT RADIATING DEVICE.

FET DEVICE INCLUDING AN INGAAS CHANNEL AND METHOD OF MANUFACTURING SAME

Transistor a effet de champ, son procede de realisation, et procede d'integration monolithique d'un transistor a effet de champ et d'un laser

L'invention concerne notamment un transistor a effet de champ, comportant une grille a jonction PN enterree, ce transistor comportant : - une couche active 28, ayant un dopage N; - une couche a forte conductivite 25, ayant un dopage N+; et etant divisee en deux parties distinctes qui sont separees par un espace et qui se terminent chacune par un plan 31, 35 incline de 45° par rapport au plan de la couche active 28; - deux plots de metal 33, 34 constituant respectivement des contacts de source et de drain pour le transistor; - un barreau 30 de materiau semi-conducteur ayant un dopage de type P et comportant une face 37 en contact avec la couche active 28 pour constituer une jonction PN qui est la grille de commande du transistor; et ayant deux faces 32, 36 inclinees a 45° par rapport au plan de la couche active 28, et separees respectivement des deux plans 31, 35 terminaux des couches 35, par un espace vide ayant une largeur constante; - un plot de metal 30 situe sur le barreau 23' et constituant ...

TRANSISTOR A EFFET DE CHAMP EN INGAAS

L'INVENTION CONCERNE LA TECHNOLOGIE DES SEMICONDUCTEURS. UN TRANSISTOR A EFFET DE CHAMP EN INGAAS COMPREND NOTAMMENT UN SUBSTRAT 10, UNE COUCHE TAMPON 13, UNE COUCHE DE CANAL 16, UNE COUCHE DE CONTACT DE SOURCE-DRAIN 19, DES ELECTRODES DE SOURCE ET DE DRAIN 22, 25, UN CONTACT 31 ET UNE COUCHE D'ISOLANT 28 CONSISTANT EN NITRURE DE SILICIUM. CETTE COUCHE D'ISOLANT SITUEE ENTRE LE METAL DU CONTACT ET LA COUCHE DE CANAL, REDUIT LE COURANT DE FUITE DE GRILLE ET DONNE AU TRANSISTOR DES CARACTERISTIQUES SOUHAITABLES, EN PARTICULIER UNE TRANSCONDUCTANCE ELEVEE. APPLICATION AUX TRANSISTORS A EFFET DE CHAMP ULTRA-RAPIDES.

Indium gallium arsenide fet - includes thin film of silicon nitride and has high transconductance

SEMICONDUCTOR DEVICE OF THE TRANSISTOR KIND HAS HETEROJUNCTION (S)

ULTRAVIOLET RADIATION LIGHT EMITTING DIODE DEVICE

There is disclosed an ultraviolet radiation device. The device comprises a base portion, a plurality of semiconductor structures connected to the base portion and an ultraviolet radiation transparent element connected to the plurality of semiconductor structures. Preferably: (i) the at least one light emitting diode is in direct contact with the ultraviolet radiation transparent element, or (ii) there is a spacing between the at least one light emitting diode and the ultraviolet radiation transparent element, the spacing being substantially completely free of air. There is also disclosed a fluid treatment system incorporating the ultraviolet radiation device.

EPITAXIAL SUBSTRATE FOR SMEICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, AND PROCESS FOR PRODUCING EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT

Disclosed is an epitaxial substrate that has good two-dimensional electron gas properties and has a reduced strain-derived internal stress. The epitaxial substrate comprises a channel layer formed of a first group III nitride represented by Inx1Aly1Gaz1N wherein x1 + y1 + z1 = 1 and which has a composition satisfying x1 = 0 and 0 ≤ y1 ≤ 0.3. The epitaxial substrate further comprises a barrier layer formed of a second group III nitride represented by Inx2Aly2Gaz2N wherein x2 + y2 + z2 = 1 and which has a composition that falls within an area surrounded by five straight lines determined dependent upon the composition of the first group III nitride (AlN molar fraction) on a ternary phase diagram in which InN, AlN, and GaN constitute vertices.

HIGH VOLTAGE SEMICONDUCTOR DEVICE

A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coupled to the active element; and an insulating layer (202) adjacent the substrate and interposed between the passive device and ground surface such that there is no resistive ground path from the passive device to the ground surface.

INTEGRATED CIRCUIT HAVING DISLOCATION-FREE SUBSTRATE

An integrated circuit bulk substrate having a zinc blende or Wurtzite crystalline structre is alloyed with a material having atoms that replace atoms of the host semiconductor. The alloyed atoms have a bond length with the nearest neighboring host atoms that is less than the bond length of the host atoms. The number of bonded alloyed atoms is small compared to the number of host atoms so as not to substantially affect electronic conduction properties of the host material, but is large enough to virtually eliminate dislocations over a large surface area and volume of the host material on which active semiconductor devices are located.

LED array, LED head and image recording apparatus

An LED array includes a semiconductor substrate and a plurality of first LED portions formed integrally on a surface of the semiconductor substrate. The first LED portions emit light of a predetermined color. The LED array includes a plurality of second LED portions fixed to the semiconductor substrate and are disposed corresponding to the first LED portions. The second LED portions emit light whose color is different from the first LED portions. The second LED portions are so disposed that active layers of the second LED portions are substantially at the same height as active layers of the first LED portions.

Resonant tunnelling barrier structure device

A resonant tunnelling barrier (RTB) structure device (e.g., diode), having a large peak-to-valley current density (Jp/Jv) ratio, includes an InP substrate and a RTB structure structure. The RTB structure is formed by a first doped layer of InP or In0.53 GA0.47 As, a first barrier layer of Alx Ga1-x Asy Sb1-y (0≦x≦1, y=0.51+0.05x), a well layer of InP or Inz Ga1-z As (0.52≦z≦0.54), a second barrier layer of the AlGaAsSb, and a second doped layer of InP or Inz Ga1-z As. The layers of the RTB structure are lattice-matched to InP.

Semiconductor device

Disclosed is a semiconductor device comprising an undoped GaAs layer, an intermediate undoped layer and an undoped Ga1-xAlxAs layer which are successively provided on a substrate made of a semiinsulating GaAs crystal; the intermediate undoped layer being an undoped InyGa1-yAs layer, an undoped GaAs1-zSbz layer, a superlattice layer which includes an undoped InyGa1-yAs layer and an undoped GaAs1-zSbz layer, a superlattice layer which includes an undoped InyGa1-yAs layer and an undoped GaAs layer, or a superlattice layer which includes an undoped GaAs1-zSb layer and an undoped GaAs layer. When applied to a high electron mobility transistor, this semiconductor device affords a high current and a high speed and has the merit of a small dispersion in the threshold voltage thereof.

Boron phosphide-based semiconductor device and production method thereof

A boron phosphide-based semiconductor device including a substrate having thereon an oxygen-containing boron phosphide-based semiconductor layer having boron and phosphorus as constituent elements and oxygen, and a production process therefor.

Compounds and infrared devices including In1-xTlxQ, where Q is As1-yPy and 0</=y</=1

A semiconductor layer of In1-xTlxQ carried on a substrate forms an infrared device, where Q is selected from the group consisting essentially of As1-yPy and 0 Подробнее

III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION

Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.

GaAs semiconductor substrate and fabrication method thereof

A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle theta by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As-O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga-O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate.

Micro or below scale multi-layered heterostructure

A heteostructure having a first and a second layer, in micrometer or smaller (e.g. nanometer) scale, arranged in a configuration defining at least one undercut at one side of the second layer, underneath the first layer, is described herein. In various embodiments, the undercut is filled with passivation materials to protect the layers underneath the first layer. Further, in various embodiments, a large metal contact layer including coverage of the first layer sidewall may be employed to provide significant increase in contact area, and to reduce the device contact resist value.

Digital alloy FinFET co-integrated with passive resistor with good temperature coefficient

A method for integrating fin field effect transistors (FinFETs) and resistors on a common substrate is provided. By employing a digital alloy as a channel material for each FinFET and as a resistor body for each resistor, FinFETs with improved charge carrier mobility, and resistors with good temperature coefficient of resistance are obtained.

HETEROJUNCTION FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

A laminate includes a surface on which a gate electrode is provided, and is made of a nitride semiconductor. The laminate includes a first layer having a first band gap, and a second layer provided between the first layer and the surface and having a second band gap which is larger than the first band gap. The first and second layers and form a joint surface by a hetero junction. The surface includes a surface defect density equal to or smaller than 1.7×106 cm2.

Manufacturable thin film gallium and nitrogen containing devices

A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.

LЕD аrrау, LЕD hеаd аnd imаgе rесоrding аppаrаtus

Аn LЕD аrrау inсludеs а sеmiсоnduсtоr substrаtе аnd а plurаlitу оf first LЕD pоrtiоns fоrmеd intеgrаllу оn а surfасе оf thе sеmiсоnduсtоr substrаtе. Тhе first LЕD pоrtiоns еmit light оf а prеdеtеrminеd соlоr. Тhе LЕD аrrау inсludеs а plurаlitу оf sесоnd LЕD pоrtiоns fiхеd tо thе sеmiсоnduсtоr substrаtе аnd аrе dispоsеd соrrеspоnding tо thе first LЕD pоrtiоns. Тhе sесоnd LЕD pоrtiоns еmit light whоsе соlоr is diffеrеnt frоm thе first LЕD pоrtiоns. Тhе sесоnd LЕD pоrtiоns аrе sо dispоsеd thаt асtivе lауеrs оf thе sесоnd LЕD pоrtiоns аrе substаntiаllу аt thе sаmе hеight аs асtivе lауеrs оf thе first LЕD pоrtiоns.

LЕD аrrау, LЕD hеаd аnd imаgе rесоrding аppаrаtus

Аn LЕD аrrау inсludеs а sеmiсоnduсtоr substrаtе аnd а plurаlitу оf first LЕD pоrtiоns fоrmеd intеgrаllу оn а surfасе оf thе sеmiсоnduсtоr substrаtе. Тhе first LЕD pоrtiоns еmit light оf а prеdеtеrminеd соlоr. Тhе LЕD аrrау inсludеs а plurаlitу оf sесоnd LЕD pоrtiоns fiхеd tо thе sеmiсоnduсtоr substrаtе аnd аrе dispоsеd соrrеspоnding tо thе first LЕD pоrtiоns. Тhе sесоnd LЕD pоrtiоns еmit light whоsе соlоr is diffеrеnt frоm thе first LЕD pоrtiоns. Тhе sесоnd LЕD pоrtiоns аrе sо dispоsеd thаt асtivе lауеrs оf thе sесоnd LЕD pоrtiоns аrе substаntiаllу аt thе sаmе hеight аs асtivе lауеrs оf thе first LЕD pоrtiоns.

Semiconductor layer

To provide a semiconductor layer in which a GaN system epitaxial layer having high crystal quality can be obtained. The semiconductor layer includes a β-Ga2O3 substrate 1 made of a β-Ga2O3 single crystal, a GaN layer 2 formed by subjecting a surface of the β-Ga2O3 substate 1 to nitriding processing, and a GaN growth layer 3 formed on the GaN layer 2 through epitaxial growth by utilizing an MOCVD method. Since lattice constants of the GaN layer 2 and the GaN growth layer 3 match each other, and the GaN growth layer 3 grows so as to succeed to high crystalline of the GaN layer 2, the GaN growth layer 3 having high crystalline is obtained.

Bipolar transistor

SEMICONDUCTOR DEVICE

PURPOSE:To perform a high speed operation of a FET by utilizing a resonance tunnel effect. CONSTITUTION:A predetermined voltage is applied to a source S, and first and second drains D1, D2, and a predetermined voltage is applied to a gate G to move charge from a charge storage layer LS to quantum well channel layers LW1, LW2 by means of a resonance tunnel operation which penetrates the thicknesses of potential barrier layers LB1, LB2 under a gate electrode 1G. Accordingly, charge running times to the layers LW1, LW2, i.e., the first and second drains become very short for the charge required to substantially tunnel the extremely thin layers LB1, LB2. Thus, an ultrahigh speed operation can be achieved.

MANUFACTURE OF COMPOUND SEMICONDUCTOR SUBSTRATE AND TRANSISTOR USING THIS SUBSTRATE

PROBLEM TO BE SOLVED: To provide the manufacture of compound semiconductor substrates, by which the same property of objects can be manufactured as transistor units, and the same property of transistors using these substrates. SOLUTION: The layers where n or i-AlGaAs layers 1 and n-GaAs layers 2 are stacked alternately is dry-etched in order while measuring the current value between a source 21 and a drain 22 in process, using the substrate where the n or i-AlGaAs layers 1 and n-GaAs layers 2 are stacked alternately. Hereby, the fine adjustment of the current between the source and the drain becomes possible. COPYRIGHT: (C)1997,JPO ...

MANUFACTURE OF SEMICONDUCTOR DEVICE

PURPOSE: To form a semiconductor device whose element characteristics are not deteriorated by a method wherein, after an element forming region is formed in a mesa type by etching on a semiconductor substrate composed of In based compound semiconductor, an undoped semiconductor layer is grown on the whole surface, and the undoped semiconductor layer on the upper part of the mesa is eliminated. CONSTITUTION: On a semiconductor substrate whose operating layer is composed of InP based or InAsGs based semiconductor or layer structure of them, an element region is formed in a mesa type by etching using a mask. Undoped AlGaAs or undoped GaAs is grown on the whole surface. The mask is etched and eliminated, and only the undoped AlGaAs or the undoped GaAs formed on the mask is eliminated. Thereby an InP based or InGaAs based field effect transistor wherein parasitic leak current is reduced and sufficient breakdown voltage is obtained can be manufactured. COPYRIGHT: (C)1991,JPO&Japio ...

Halbleitermaterial und -vorrichtungen

Rauscharme AlGaPSb/GaInAs Leistungs-HEMT und pseudomorphische HEMT auf einem GaAs Substrat

Semiconductor circuit structure having dislocation-free substrate

An integrated circuit bulk substrate having a zinc blende or Wurtzite crystalline structure is alloyed with a material having atoms that replace atoms of the host semiconductor. The alloyed atoms have a bond length with the nearest neighboring host atoms that is less than the bond length of the host atoms. The number of bonded alloyed atoms is small compared to the number of host atoms so as not to substantially affect electronic conduction properties of the host material, but is large enough to virtually eliminate dislocations over a large surface area and volume of the host material on which active semiconductor devices are located.

INTEGRATED CIRCUIT HAVING DISLOCATION-FREE SUBSTRATE

An integrated circuit bulk substrate having a zinc blende or Wurtzite crystalline structure is alloyed with a material having atoms that replace atoms of the host semiconductor. The alloyed atoms have a bond length with the nearest neighboring host atoms that is less than the bond length of the host atoms. The number of bonded alloyed atoms is small compared to the number of host atoms so as not to substantially affect electronic conduction properties of the host material, but is large enough to virtually eliminate dislocations over a large surface area and volume of the host material on which active semiconductor devices are located.

High electron mobility epitaxial substrate

METHOD OF MANUFACTURING GAAS SEMICONDUCTOR DEVICE

A METHOD OF MANUFACTURING GaAs SEMICONDUCTOR DEVICE Amethod of manufacturing a GaAs semiconductor device of an E/D construction having a GaAs/AlGaAS heterojunction and utilizing two-dimensional electron gas, comprising the steps of forming a heterojunction semiconductor substrate and etching a portion of the substrate to provide a gate portion of a depletion-mode FET. When the substrate comprising a semi-insulating GaAs layer, an undoped GaAs, an N-type AlGaAs layer of an electron-supply layer, and a GaAs layer is formed, the GaAs layer is composed of a first GaAs layer, an etching stoppable AlGaAs layer, and a second GaAs layer, the first GaAs layer being formed on the N type GaAs layer. The etching for provision of the gate portion is carried out by a dry etching method using an etchant of CCl2F2 gas, so that the second GaAs layer can be etched but the AlGaAs layer cannot be etched. Thus, the thickness of the layers between a gate electrode of the depletion-mode FET and the GaAs/AlGaAs ...

HIGH SPEED FET EMPLOYING TERNARY AND QUARTERNARY III-V ACTIVE LAYERS

PATENT APPLICATION of LAWRENCE W. JAMES for HIGH SPEED FET EMPLOYING TERNARY AND QUARTERNARY III-V ACTIVE LAYERS A field effect transistor (FET) preferably employs an epitaxial layer of indium gallium arsenide as its active layer. On the surface of the active layer, ohmic source and drain contacts are spaced from respectively opposite sides of a Schottky barrier (rectifying) gate electrode. The active layer is grown over an epitaxial transition layer which is graded from gallium arsenide to indium gallium arsenide and is doped with chromium or oxygen to be semi-insulating. The transition layer is in turn formed over a bulk, intrinsic layer of gallium arsenide. High speed operation of the FET is obtainable because the active layer has excellent electron transport characteristics. Other materials suitable for the active layer are indium arsenide phosphide and indium gallium arsenide phosphide.

Stacked high-cutoff InGaAs semiconductor power diode

Semiconductor layer

TRANSISTOR III-V HAS HETEROJUNCTION, IN PARTICULAR FIELD-EFFECT TRANSISTOR BIPOLAR HEMTOU TRANSISTOR HAS HETEROJUNCTION

COMPOUND SEMICONDUCTOR EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING SAME

METHOD AND SYSTEM TO IDENTIFY A UNIT OF PROGRAM

HIGH ELECTRON MOBILITY TRANSISTOR HAVING A BORON NITRIDE ALLOY INTERLAYER AND METHOD OF PRODUCTION

A semiconductor device includes a III-nitride buffer layer and a III-nitride barrier layer. A boron nitride alloy interlayer interposed between the III-nitride buffer layer and the III-nitride barrier layer. A portion of the III-nitride buffer layer includes a two- dimensional electron gas (2DEG) channel that is on a side of the III-nitride buffer layer adjacent to the boron nitride alloy interlayer.

A METHOD FOR LOCALLY MODIFYING THE EFFECTIVE BANDGAP ENERGY IN INDIUM GALLIUM ARSENIDE PHOSPHIDE (InGaAsP) QUANTUM WELL STRUCTURES

A novel quantum well intermixing method for regionally modifying the bandgap properties of InGaAsP quantum well structures is disclosed. The method induces bandgap wavelength blue shifting and deep states for reducing carrier lifetime within InGaAsp quantum well structures. The novel quantum well intermixing technique is applied to the modulator section of an integrated DFB laser/electro-absorption modulator, wherein the modulator exhibits fast switching times with efficient optical coupling between the DFB laser and modulator region.

Scandium-Containing III-N Etch-Stop Layers for Selective Etching of III-Nitrides and Related Materials

A semiconductor device structure including a scandium (Sc)- or yttrium (Y)-containing material layer situated between a substrate and one or more overlying layers. The Sc- or Y-containing material layer serves as an etch-stop during fabrication of one or more devices from overlying layers situated above the Sc- or Y-containing material layer. The Sc- or Y-containing material layer can be grown within an epitaxial group III-nitride device structure for applications such as electronics, optoelectronics, and acoustoelectronics, and can improve the etch-depth accuracy, reproducibility and uniformity.

Method for locally modifying the effective bandgap energy in indium gallium arsenide phosphide (InGaAsP) quantum well structures

A novel quantum well intermixing method for regionally modifying the bandgap properties of InGaAsP quantum well structures is disclosed. The method induces bandgap wavelength blue shifting and deep states for reducing carrier lifetime within InGaAsP quantum well structures. The novel quantum well intermixing technique is applied to the modulator section of an integrated DFB laser/electro-absorption modulator, wherein the modulator exhibits fast switching times with efficient optical coupling between the DFB laser and modulator region.

III-Nitride device with solderable front metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

SEMICONDUCTOR DEVICE

In accordance with an embodiment, a semiconductor device includes a GaN layer and a first AlxGa1-xN layer (0≦X<1). The first AlxGa1-xN layer (0≦X<1) is located on the GaN layer. The first AlxGa1-xN layer (O≦X<1) is located in contact with the GaN layer. The first AlxGa1-xN layer (0≦X<1) includes carbon (C).

Compound semiconductor multilayer structure, hall device, and hall device manufacturing method

Hall device is provided by enabling stable provision of a quantum well compound semiconductor stacked structure. It has first and second compound semiconductor layers composed of Sb and at least two of five elements of Al, Ga, In, As and P, and an active layer composed of InxGa1-x,AsySb1-y (0.8<=x<=1.0, 0.8 Подробнее

LЕD аrrау, LЕD hеаd аnd imаgе rесоrding аppаrаtus

Аn LЕD аrrау inсludеs а sеmiсоnduсtоr substrаtе аnd а plurаlitу оf first LЕD pоrtiоns fоrmеd intеgrаllу оn а surfасе оf thе sеmiсоnduсtоr substrаtе. Тhе first LЕD pоrtiоns еmit light оf а prеdеtеrminеd соlоr. Тhе LЕD аrrау inсludеs а plurаlitу оf sесоnd LЕD pоrtiоns fiхеd tо thе sеmiсоnduсtоr substrаtе аnd аrе dispоsеd соrrеspоnding tо thе first LЕD pоrtiоns. Тhе sесоnd LЕD pоrtiоns еmit light whоsе соlоr is diffеrеnt frоm thе first LЕD pоrtiоns. Тhе sесоnd LЕD pоrtiоns аrе sо dispоsеd thаt асtivе lауеrs оf thе sесоnd LЕD pоrtiоns аrе substаntiаllу аt thе sаmе hеight аs асtivе lауеrs оf thе first LЕD pоrtiоns.

Devices having asymmetric delta-doping

Resonant tunelling barrier structure device

SEMICONDUCTOR EPITAXIAL WAFER AND FIELD EFFECT TRANSISTOR

PROBLEM TO BE SOLVED: To provide a semiconductor epitaxial wafer for realizing improved characteristics by preventing a highly conductive part (conductive layer) from being formed in a buffer layer due to the mixture of conductive impurities in the epitaxial layer, when manufacturing an electronic device, such as a field effect transistor and a hetero junction bipolar transistor including a high electron mobility transistor, on the semiconductor epitaxial wafer. SOLUTION: In the semiconductor epitaxial wafer having the buffer layer 2 on a substrate 1, an AlXGa1-XN buffer layer 23 (0≤X<1), an AlN buffer layer 22, and a GaN buffer layer 21 are formed successively in the buffer layer 2. COPYRIGHT: (C)2006,JPO&NCIPI ...

FIELD EFFECT SEMICONDUCTOR DEVICE

PURPOSE: To stably maintain excellent element characteristics such as high speed operability, low noise characteristic, high output, etc., by forming an electron running layer of compound semiconductor having a lattice constant larger than that of a substrate and forming an electron supply layer of compound semiconductor having a lattice constant smaller than that of the substrate. CONSTITUTION: An updoped GaAs buffer layer 2 is grown on a GaAs substrate 1, 4 InxGa1-xAs layers 3 to become electron running layers and 4 InyGa1-y layers 4 to become supply layers are then alternately sequentially laminated therein, and an N-type GaAs cap layer 5 is formed to be manufactured. In a field effect semiconductor device having such a structure, contraction distortion is generated on the basis of the lattice constant difference between the substrate 1 and the layer 2 in the layer 3, while a tensile distortion is generated in the layer 4. COPYRIGHT: (C)1990,JPO&Japio ...

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

PROBLEM TO BE SOLVED: To provide a semiconductor device, which is capable of decreasing the contact resistance at the interface between an InGaP layer and a semiconductor layer formed at the upper layer of the InGaP layer, and the manufacturing method thereof. SOLUTION: This semiconductor device is constituted of an InGaP layer 20, which is epitaxially grown on a semiconductor substrate 10, and wherein the natural superlattice is broken and the alignment of In and Ga in the surface of a III-group atom layer has become irregular, and a semiconductor layer 22 which has been epitaxially grown on the InGaP layer 20 and has the same conductivity type as the InGaP layer 20. With this constitution, the trap at the interface of the InGaP layer 20 and the semiconductor layer 22 can be decreased. Thus, the contact resistance between the InGaP layer 20 and the semiconductor layer 22 can be decreased. COPYRIGHT: (C)1999,JPO ...

SEMICONDUCTOR DEVICE

PURPOSE: To prevent a reduction in an electron transit time by a method wherein a collector barrier layer is formed by doping partially a one conductivity type impurity in its thickness direction from the side of a collector layer. CONSTITUTION: An n+ GaAs collector layer 2, a collector barrier layer 3 consisting of an n-type Al0.3Ga0.7As layer 3A and an Al0.3Ga0.7As layer 3B, an N-type GaAs base layer 4 and moreover, an Al0.3Ga0.7As barrier layer 5, a GaAs well layer 6, a quantum well layer consisting of an Al0.3Ga0.7As barrier layer 7 and an n+ GaAs emitter layer 8 are grown in order on a semi-insulative GaAs substrate 1 by an MBE method, for example. Then, AuGe/Au electrodes [an emitter electrode (a), a base electrode (b) and a collector electrode (c)] are respectively mounted on the layer 8, the layer 4 and the layer 2. In case a transistor is simply a HET, an emitter layer is formed instead of the quantum well layers 5∼7 and an Al0.3Ga0.7As layer is formed as the barrier layers. Moreover ...

p-TYPE III NITRIDE SEMICONDUCTOR, ITS PRODUCING METHOD AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a low resistance p-type III nitride semiconductor, and its producing method, in which a mother crystal can be doped efficiently and heavily with three atom complex dopant. SOLUTION: A low temperature GaN buffer layer 11 and a p-type GaN layer 12 are formed sequentially on a sapphire substrate 10. The p-type GaN layer 12 is doped with p-type impurities, i.e., Mg (magnesium) and O (oxygen), by about 1×1020 cm-3 and 3×1019 cm-3, respectively. COPYRIGHT: (C)2003,JPO ...

SUPER LATTICE SEMICONDUCTOR DEVICE

PURPOSE: To control resonant tunneling and to implement low power consumption, by forming quantum wells at an emitter, a base and a collector, and applying bias voltages across the emitter and the collector and across the emitter and the base. CONSTITUTION: A collector-side quantum well 15 is formed at an interface between a collector layer 13 and a base layer 17. An emitter-side quantum well 19 is formed at an interface between an emitter layer 21 and the base layer 17. Under the state voltages are not applied to an emitter electrode 28, base electrodes 29 and collector electrodes 30, a first quantum level 25 of the layer 17 is shallower than first quantum levels 23 and 26 of the wells 15 and 19. When bias voltages are applied across the electrodes 28∼30, the first quantum level 25 of the layer 17 can be aligned with the first quantum level 26 of the well 19 and the second quantum level 24 of the well 15. Therefore resonant tunneling is yielded. Thus the resonant tunneling can be controlled ...

SEMICONDUCTOR CRYSTAL

PURPOSE: To obtain a hetero structure having a boundary of excellent thermal stability by providing an AlxSb1-x layer or a GaAsySb1-y layer between an InaAlbGa1-a-bAs layer and an IncAldGa1-c-dAs layer. CONSTITUTION: At least one or more AlAsxSb1-x layer or a GaAsySb1-y layer is provided between an InaAlbGa1-a-bAs layer and an IncAldGa1-c-dAs layer. That is, an i-type In0.52Al0.48As layer 27 of a buffer layer is provided on a high resistance InP substrate 28, an i-type In0.53Al0.47As layer 26 an operating layer is provided thereon, an i-type GaAs0.5Sb0.5 layer 25, a n-type In0.52Ad0.48As layer 24 of an electron supply layer, and a contact n+ type In0.53Ga0.47As layer 23 are further provided thereon. Further, a gate metal 21 and an ohmic metal 22 are provided. Thus, a thermally stable hetero junction is obtained. COPYRIGHT: (C)1991,JPO&Japio ...

NITRIDE SEMICONDUCTOR AND MANUFACTURING METHOD THEREFOR

PROBLEM TO BE SOLVED: To provide a p-type nitride semiconductor, having a high positive hole concentration of at least 1×1018 cm-3 at room temperature. SOLUTION: An organic metal vapor-phase growth method is used with organic metal containing In, Ga, and Mg and ammonium gas as the material gas, while nitrogen gas is used as the carrier gas. Here, an AlN buffer layer 2 of 20 nm is grown on a sapphire substrate 1 at 550°C, and a GaN buffer layer 3 of 1,100 nm is grown on the AlN buffer layer 2 at 1,000°C. Furthermore, a Mg-doped InGaN layer 4 is grown on the GaN buffer layer 3 at 780°C while hydrogen atom taken into InGaN during growth under thermal treatment at 500°C or higher in a nitrogen atmosphere is taken out, thus providing a P-type nitride semiconductor. COPYRIGHT: (C)2001,JPO ...

SEMICONDUCTOR DEVICE PROVIDED WITH QUANTUM THIN WIRE AND ITS MANUFACTURE

PURPOSE: To easily form a sufficiently thin quantum thin wire with good controllability and to realize a high-speed operation by a method wherein a third semiconductor layer is formed on a sidewall of a first semiconductor thin film and a second semiconductor layer via a second semiconductor thin film and a quantum thin wire is formed in their interface. CONSTITUTION: GaAs thin films 6 and AlGaAs thin films 8 are laminated alternately on a substrate 2 via an AlGaAs layer 4 to form a GaAs-AlGaAs superlattice layer 10. A high-resistance i-type GaAs layer 14 is formed on one sidewall of the superlattice layer 10 via an AlGaAs thin film 12; an n+ type GaAs layer 16 is formed on the other sidewall. When a negative voltage is applied to the side of the i-type GaAS layer 14 and a positive voltage is applied to the n+ type GaAs layer 16, a potential which is changed at the same cycle as that of a superlattice is formed, electrons are accumulated in a potential well formed in positions adjacent ...

ヘテロ接合III-V族トランジスタ、特にHEMT電界効果トランジスタまたはヘテロ接合バイポーラ・トランジスタ

... 本発明は、広い禁制帯の物質および狭い禁制帯の物質を有するIII-V族半導体物質を備えたヘテロ接合トランジスタに関する。狭い禁制帯の物質は、III族元素の1つとしてガリウムを、V族元素としてヒ素および窒素の双方を含むIII-V族化合物であり、窒素の含有量は約5%未満であり、狭い禁制帯の物質は少なくとも1つの第4のIIIまたはV族の元素を備える。前記第4の元素を追加することによって、へテロ接合の禁制帯の幅、伝導帯の不連続性ΔEc、および価電子帯の不連続性ΔEvを調整することが可能となる。本発明は、低い禁制帯を有し、従って高ドレイン電流を有するHEMT電界効果トランジスタを生成するのに有用である。また、本発明は、低いVBEを有し、従って低供給電圧によって機能することができるヘテロ接合バイポーラ・トランジスタを生成するのに有用である。 ...

HEMT mit integrierter Diode mit niedriger Durchlassspannung

High-Electron-Mobility-Transistor (100), umfassend:Source (S), Gate (G) und Drain (D);ein erstes III-V-Halbleitergebiet (116) mit einem ersten zweidimensionalen Elektronengas (120), das einen ersten leitenden Kanal, der vom Gate (G) zwischen Source (S) und Drain (D) gesteuert werden kann, bereitstellt;ein zweites III-V-Halbleitergebiet (108) unter dem ersten III-V-Halbleitergebiet und mit einem zweiten zweidimensionalen Elektronengas (114) als zweiten leitenden Kanal, der entweder mit Source (S) oder mit Drain (D) verbunden ist und nicht vom Gate (G) gesteuert werden kann; undwobei das erste und zweite III-V-Halbleitergebiet (116, 108) voneinander durch ein Gebiet (110) des High-Electron-Mobility-Transistors (100) mit einem anderen Bandabstand als das erste und zweite III-V-Halbleitergebiet beabstandet sind.

Heteroübergangs-Bipolartransistor aus III-V Material

Halbleiterbauelement mit einer Puffer-Struktur, um Defekte der darauf gewachsenen Halbleiterschicht aufzuheben.

Nitridhalbleitereinrichtung

Nitridhalbleitereinrichtung mit:einer ersten Nitridhalbleiterschicht (16);einer zweiten Nitridhalbleiterschicht (18), die auf der ersten Nitridhalbleiterschicht (16) lokalisiert ist und eine Bandlücke hat, die größer als eine Bandlücke der ersten Nitridhalbleiterschicht (16) ist;eine Halbleiterschicht (34) des p-Typs, die auf der zweiten Nitridhalbleiterschicht (18) lokalisiert ist; undeine Gate-Elektrode (36), die auf der Halbleiterschicht (34) des p-Typs lokalisiert ist, wobeieine erste Grenzfläche (38a) und eine zweite Grenzfläche (37a, 35a) parallel zwischen der Gate-Elektrode (36) und der Halbleiterschicht (34) des p-Typs lokalisiert sind,die erste Grenzfläche (38a) eine erste Barriere mit Bezug auf Löcher hat, die sich in einer Richtung von der Halbleiterschicht (34) des p-Typs zu der Gate-Elektrode (36) bewegen,die zweite Grenzfläche (37a, 35a) eine zweite Barriere mit Bezug auf die Löcher, die sich in einer Richtung von der Halbleiterschicht (34) des p-Typs zu der Gate-Elektrode ...

INTEGRATED CIRCUIT

INTEGRATED CIRCUIT HAVING DISLOCATION-FREE SUBSTRATE

INGAAS FIELD EFFECT TRANSISTOR

InGaAs FIELD EFFECT TRANSISTOR InGaAs FETs using a silicon nitride layer, between the metal and the channel layer reduce the gate leakage current and yield desirable FET characteristics, particularly high transconductance.

HIGH SPEED FET EMPLOYING TERNARY AND QUARTERNARY III-V ACTIVE LAYERS

Semiconductor III-N structure and method for III-N forming the same

Semiconductors structures using group III-nitride quaternary material system with reduced phase separation and method of fabrication

Perovskite type function film GaN-based heteroepitaxy structure and preparation method thereof

DISPOSITIF SEMI-CONDUCTEUR DU GENRE TRANSISTOR A HETEROJONCTION(S)

LA PRESENTE INVENTION CONCERNE UN DISPOSITIF SEMI-CONDUCTEUR, DU GENRE TRANSISTOR A HETEROJONCTION(S), COMPRENANT UN EMPILEMENT DE COUCHES SEMI-CONDUCTRICES QUI, PAR COMBINAISON, FORMENT TROIS REGIONS DITES DE SOURCE, DE GRILLE ET DE DRAIN, ALORS QUE LE TRAJET DU COURANT QUI S'ETABLIT ENTRE LESDITES REGIONS DE SOURCE ET DE DRAIN EST SENSIBLEMENT PERPENDICULAIRE AUX DIVERSES JONCTIONS, REMARQUABLE EN CE QUE LA REGION DE GRILLE CONSTITUE UNE REGION D'ACCUMULATION D'ELECTRONS, SOUS LA FORME D'UN QUASI-GAZ DE FERMI A DEUX DIMENSIONS QUE L'ON PEUT PORTER AU POTENTIEL DE POLARISATION DESIRE AU MOYEN D'UNE ELECTRODE DE GRILLE, ALORS QUE LES ELECTRONS QUI FORMENT LE COURANT SOURCE-DRAIN TRAVERSENT CE NUAGE D'ELECTRONS SANS AVOIR BEAUCOUP D'INTERACTION AVEC LUI, SOUS UN REGIME BALISTIQUE OU QUASI BALISTIQUE. APPLICATION: DISPOSITIF SEMI-CONDUCTEUR.

Devices having asymmetric delta-doping

A SEMICONDUCTOR LAYER STRUCTURE

A III-nitride compound device which has a layer of AlInN (7) having a non-zero In content, for example acting as a current blocking layer, is described. The layer of AlInN (7) has at least aperture defined therein. The layer of AlInN (7) is grown with a small lattice-mismatch with an underlying layer, for example an underlying GaN layer, thus preventing added crystal strain in the device. By using optimised growth conditions the resistivity of the AlInN is made higher than 102ohm.cm thus preventing current flow when used as a current blocking layer in a multilayer semiconductor device with layers having smaller resistivity. As a consequence, when the AlInN layer has an opening and is placed in a laser diode device, the resistance of the device is lower resulting in a device with better performance.

THERMOELECTRIC MATERIALS BASED ON TETRAHEDRITE STRUCTURE FOR THERMOELECTRIC DEVICES

Thermoelectric materials based on tetrahedrite structures for thermoelectric devices and methods for producing thermoelectric materials and devices are disclosed.

BORON PHOSPHIDE-BASED SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

A boron phosphide-based semiconductor device includes a single crystal substrate having formed thereon a boron-phosphide (BP)-based semiconductor layer containing boron and phosphorus as constituent elements, where phosphorus (P) occupying the vacant lattice point (vacancy) of boron (B) and boron occupying the vacant lattice point (vacancy) of phosphorus are present in the boron-phosphide (BP)-based semiconductor layer. The boron phosphide-based semiconductor device includes a p-type boron phosphide-based semiconductor layer in which boron occupying the vacancy of phosphorus is contained in a higher atomic concentration than phosphorus occupying the vacancy of boron and a p-type impurity of Group II element or Group IV element is added.

COMPOUND SEMICONDUCTOR EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING SAME

A compound semiconductor epitaxial substrate which is used for pseudomorphic high-electron-mobility field-effect transistors and comprises an InGaAs layer serving as a channel layer (9) and AlGaAs layers containing n-type impurities serving as electron supply layers (6, 12) is disclosed. By setting the In proportion in the InGaAs layer formed as the channel layer (9) not less than 0.25 and optimizing the In proportion and the film thickness of the channel layer (9), the channel layer (9) has an electron mobility of 8,300 cm2/V·s or higher at room temperature. GaAs layers (8, 10) having a film thickness not less than 4 nm may be formed on both sides of the channel layer (9).

Disordered crystalline semiconductor

A semiconductor material having a disordered structure consists of a semiconductor material on which epitaxial growth is possible. The semiconductor material has an energy band structure constituted by one of the indirect band structure, the direct band structure, and a combination of the indirect and the direct band structures, and consists of a plurality of semiconductor layers. The semiconductor layer is orderly arranged along its surface and disorderly arranged along its thickness direction with respect to at least one of the followings the number of atomic or molecular layers constituting the semiconductor layer, a composition of a specific molecular layer of the molecular layers, and impurity doped to the semiconductor layer.

Compounds and infrared devices including In1-x Tlx Q, where Q is As1-y Py and 0≦y≦1

A semiconductor layer of In1-x Tlx Q carried on a substrate forms an infrared device, where Q is selected from the group consisting essentially of As1-y Py and 0 Подробнее

Binary superlattice tunneling device and method

A resonant tunneling diode (30) with anode (40) and cathode (32) separated by binary short-period superlattice tunneling barriers (34,38) with a quantum well (36) between is disclosed. Enhancement and depletion mode diodes are disclosed.

Semiconductor light emitting device, light emitting module, lighting apparatus, display element and manufacturing method of semiconductor light emitting device

An LED array chip (2), which is one type of a semiconductor light emitting device, includes an array of LEDs (6), a base substrate (4) supporting the array of the LEDs (6), and a phosphor film (48). The array of LEDs (6) is formed by dividing a multilayer epitaxial structure including a light emitting layer into a plurality of portions. The phosphor film (48) covers an upper surface of the array of the LEDs (6) and a part of every side surface of the array of LEDs (6). Here, the part extends from the upper surface to the light emitting layer.

Semiconductor Material Doping

A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).

HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF

A high electron mobility transistor is realized in the present invention by a gate recessed structure, a high permittivity oxide layer and a nitride-based interfacial passivation layer, featuring high threshold voltage, high transconductance, highly stable drain output current, and high reliability.

Fault tolerant design for large area nitride semiconductor devices

A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid ...

CURRENT APERTURE VERTICAL ELECTRON TRANSISTORS WITH AMMONIA MOLECULAR BEAM EPITAXY GROWN P-TYPE GALLIUM NITRIDE AS A CURRENT BLOCKING LAYER

A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

Compound semiconductor device and manufacturing method thereof

A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0≦x1<x2≦1” is found when a composition of the first AlGaN layer is represented by Al x1 Ga 1-x1 N, and a composition of the second AlGaN layer is represented by Al x2 Ga 1-x2 N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.

Ohmic contact to semiconductor device

Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).

SEMICONDUCTOR DEVICE, FABRICATION METHOD OF THE SEMICONDUCTOR DEVICES

In a semiconductor device, a YAG substrate is formed as a single-crystal substrate of any of surface orientations (100), (110), and (111). In the fabrication of the semiconductor device, a TMAl gas is first fed onto the YAG substrate so as to form a nucleation layer made of aluminum, which is a group-III element. Then, an NHgas is fed onto the nucleation layer. This turns the surface of the nucleation layer into a group-V element and then forms a group-III-V compound layer of AlN. Then, a mixed gas of TMAl gas and NHgas is fed onto the group-III-V compound layer so as to form another group-III-V compound layer. Finally, a group-III nitride semiconductor layer is crystal-grown on the group-III compound layer. 1. A method for fabricating a semiconductor device , the method comprising:{'sub': 3', '5', '12, 'forming a buffer layer, containing a group-III-V compound, on a substrate formed of YAlO; and'}forming a group-III nitride semiconductor layer on the buffer layer,wherein the forming the buffer layer includes forming a nucleation layer made of a group-III element in at least a part on the substrate,wherein the substrate is a single-crystal substrate of any of surface orientations (100) and (110).2. A method for fabricating a semiconductor device according to claim 1 , wherein the nucleation layer is formed by supplying a first gas containing a group-III element onto the substrate.3. A method for fabricating a semiconductor device according to claim 1 , wherein the forming a buffer layer further includes changing at least a part of the surface of the nucleation layer into a group-III-V compound by combining the at least a part of the surface of the nucleation layer with a group V element.4. A method for fabricating a semiconductor device according to claim 3 , wherein the at least a part of the surface of the nucleation layer is changed into a group-III-V compound by supplying a second gas containing a group-V element onto the nucleation layer.5. A method for ...

GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate. 1. A composite substrate for a semiconductor to grow thereon comprising:a silicon substrate comprising a first surface and a second surface opposite to the first surface, the first surface defining a plurality of grooves therein, the second surface being configured for growth of the semiconductor thereon; anda filler filled into the plurality of grooves on the first surface of the silicon substrate, a thermal expansion coefficient of the filler being bigger than that of the silicon substrate.2. The composite substrate as claimed in claim 1 , wherein the plurality of grooves are uniformly arranged in the first surface.3. The composite substrate as claimed in claim 1 , wherein the plurality of grooves have a same depth.4. The composite substrate as claimed in claim 1 , wherein the depth of the grooves is in a range from one third of a thickness of the silicon substrate to a half of the thickness of the silicon substrate.5. The composite substrate as claimed in claim 1 , wherein the filler is selected from the group consisting of AlO claim 1 , SiC claim 1 , AlN claim 1 , InN claim 1 , MgN claim 1 , ZnO claim 1 , GaAs claim 1 , GaP and Ge.6. A gallium nitride-based semiconductor device comprising: a silicon substrate comprising a first surface and a second surface opposite to the first surface, the first surface defining a plurality of grooves therein; and', 'a filler filled into ...

FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE

The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer a channel layer a barrier layer and a spacer layer is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer the lattice-relaxed channel layer and the barrier layer having a tensile strain, and the spacer layer are laminated on a substrate in this order. The gate insulating film is arranged on the spacer layer The gate electrode is arranged on the gate insulating film The source electrode and the drain electrode are electrically connected to the channel layer directly or via another component. 1. A field effect transistor comprising:a substrate;a buffer layer;a channel layer;a barrier layer;a spacer layer;a gate insulating film;a gate electrode;a source electrode; anda drain electrode, wherein{'sub': x', '1-x, 'the buffer layer is formed of lattice-relaxed AlGaN (0≦x<1),'}{'sub': x', '1-x, 'the channel layer is formed of AlGaN (0≦x<1) with the same composition as the buffer layer,'}{'sub': z', '1-z, 'the barrier layer is formed of AlGaN (x Подробнее

SEMICONDUCTOR DEVICES HAVING A RECESSED ELECTRODE STRUCTURE

An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance. 1. A field effect transistor , comprising:a source region;a drain region;a semiconductor region between the source region and the drain region, the semiconductor region having trenches extending along a direction that extends between the source region and the drain region;a conductive electrode having conductive regions formed in the trenches, the conductive electrode extending no more than a portion of a distance between the source region and the drain region; andan insulating region between the semiconductor region and the conductive electrode, the insulating region extending at least partially across an interface between the semiconductor region and the conductive electrode.2. The field effect transistor of claim 1 , wherein the first semiconductor region includes a III-N semiconductor material.3. The field effect transistor of claim 2 , wherein the III-N semiconductor material includes GaN.4. The field effect transistor of claim 1 , wherein the semiconductor region is a first semiconductor region claim 1 , and the field effect transistor further comprises a second semiconductor region between the first semiconductor region and the insulating region and/or conductive electrode.5. The field effect transistor of claim 4 , wherein the first semiconductor region includes a first III-N semiconductor material and the second semiconductor region includes a second III-N semiconductor material claim 4 , and wherein the first III-N semiconductor material has a different bandgap from that of the ...

FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE

The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer , a channel layer , a barrier layer , and a spacer layer is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer , the channel layer having a compressive strain, and the barrier layer having a tensile strain, and the spacer layer having a compressive strain are laminated on a substrate in this order. The gate insulating film is arranged on the spacer layer . The gate electrode is arranged on the gate insulating film . The source electrode and the drain electrode are electrically connected to the channel layer directly or via another component. 1. A field effect transistor comprising:a substrate;a buffer layer;a channel layer;a barrier layer;a spacer layer;a gate insulating film;a gate electrode;a source electrode; anda drain electrode, wherein{'sub': x', '1-x, 'the buffer layer is formed of lattice-relaxed AlGaN (0 Подробнее

Active Area Shaping for III-Nitride Devices

A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. 120-. (canceled)21. A III-nitride semiconductor device comprising:a first III-nitride body having one band gap, and a second III-nitride body having another band gap disposed over said first III-nitride body; 'a gate well having a first mouth defined in said first insulation body, and a second mouth defined in said second insulation body, said second mouth being wider than said first mouth;', 'a first insulation body situated over said second III-nitride body, and a second insulation body situated over said first insulation body;'}a gate arrangement disposed at least partially within said gate well, said gate arrangement including a gate dielectric formed along said first mouth and said second mouth in said gate well, and a gate electrode over said gate dielectric, said gate arrangement filling said gate well.22. The III-nitride semiconductor device of claim 21 , further comprising a drain electrode and a source electrode on respective sides of said gate arrangement.23. The III-nitride semiconductor device of claim 21 , wherein said first insulation body comprises silicon nitride.24. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises a nitride dielectric.25. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises silicon nitride.26. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises aluminum nitride.27. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises titanium nitride.28. The III-nitride semiconductor device of claim 21 , wherein said first III-nitride body comprises GaN and said second III-nitride body comprises AlGaN.29. A method of fabricating a III-nitride semiconductor device ...

DIODE

A diode includes: a semiconductor layer stack; cathode and anode electrodes formed on the semiconductor layer stack so as to be spaced apart from each other; and a protection film covering a region of an upper surface of the semiconductor layer stack. The semiconductor layer stack includes a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer, and has a channel. The anode electrode includes: a p-type third nitride semiconductor layer formed on the semiconductor layer stack; a first metal layer being in ohmic contact with the third nitride semiconductor layer; and a second metal layer being in contact with the first metal layer, and being in ohmic contact with the channel. 1. A diode comprising:a semiconductor layer stack formed on a principal surface of a substrate, including a first nitride semiconductor layer, and a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and has a larger band gap than the first nitride semiconductor layer, and having a channel through which electrons travel in a direction parallel to the principal surface of the substrate;cathode and anode electrodes formed on the semiconductor layer stack so as to be spaced apart from each other; anda protection film covering a region of an upper surface of the semiconductor layer stack between the cathode and anode electrodes, wherein a p-type third nitride semiconductor layer formed on the semiconductor layer stack;', 'a first metal layer formed on the third nitride semiconductor layer, and being in ohmic contact with the third nitride semiconductor layer; and', 'a second metal layer being in contact with the first metal layer, being opposite to the cathode electrode with respect to the third nitride semiconductor layer, and being in ohmic contact with the channel., 'the anode electrode includes2. The diode of claim 1 , whereinthe first nitride semiconductor layer ...

Gallium Nitride Devices with Compositionally-Graded Transition Layer

The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of o semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. 115-. (canceled)1635-. (canceled)36. A semiconductor device comprising:a transition layer;a III-nitride layer over said transition layer;wherein a composition of said transition layer at a top surface thereof substantially matches a composition of said III-nitride layer at a bottom surface thereof.37. The semiconductor device of claim 36 , wherein said transition layer is situated over a substrate.38. The semiconductor device of claim 37 , wherein said substrate comprises silicon.39. The semiconductor device of claim 37 , wherein said substrate consists of only silicon.40. The semiconductor device of claim 36 , wherein said III-nitride layer comprises gallium nitride.41. The semiconductor device of claim 36 , wherein said III-nitride layer consists of only gallium nitride.42. The semiconductor device of claim 36 , wherein said composition is graded continuously across said transition layer.43. The semiconductor device of claim 36 , wherein said transition layer comprises an alloy of gallium nitride selected from the group consisting of AlInGaN claim 36 , InGaN claim 36 , and AlGaN.44. The semiconductor device of claim 40 , ...

FIELD EFFECT TRANSISTOR

A first group III nitride semiconductor layer has a low carbon concentration region having a carbon concentration of less than 1×10cm, and located in a region under an edge of a gate electrode closer to a drain electrode, a thickness d of the low carbon concentration region satisfies 1. A field effect transistor , comprising:a substrate;a first group III nitride semiconductor layer formed on the substrate;a second group III nitride semiconductor layer formed on the first group III nitride semiconductor layer, and having a band gap wider than that of the first group III nitride semiconductor layer;a source electrode and a drain electrode formed on the second group III nitride semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode; anda field plate formed on the second group III nitride semiconductor layer to be connected to the gate electrode or the source electrode, and to cover an edge of the gate electrode closer to the drain electrode, wherein{'sup': 17', '−3, 'the first group III nitride semiconductor layer has a low carbon concentration region having a carbon concentration of less than 1×10cm, and located in at least a region under the edge of the gate electrode closer to the drain electrode,'}{'b': '2', 'claim-text': {'br': None, 'i': V', '·d', 'd', 'V', '·d, 'sub': m', 'm, '/(1101)≦2 Подробнее

NITRIDE-BASED HETEROJUCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACUTRING THE SAME

Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for manufacturing the same. The nitride-based heterojunction semiconductor device includes a first drain electrode, a conductive semiconductor layer including a nitride-based semiconductor disposed on the first drain electrode, a channel layer disposed on the conductive semiconductor layer, a barrier layer disposed on the channel layer, a source electrode and a second drain electrode spaced from each other on the barrier layer, and a gate electrode disposed between the source electrode and the second drain electrode. 1. A nitride-based heterojunction semiconductor device comprising:a first drain electrode;a conductive semiconductor layer comprising a nitride-based semiconductor disposed on the first drain electrode;a channel layer disposed on the conductive semiconductor layer;a barrier layer disposed on the channel layer;a source electrode and a second drain electrode spaced from each other on the barrier layer; anda gate electrode disposed between the source electrode and the second drain electrode.2. The nitride-based heterojunction semiconductor device according to claim 1 , further comprising:a current barrier layer disposed between the conductive semiconductor layer and the channel layer,wherein the current barrier layer has an opening at least at the side of the second drain electrode.3. The nitride-based heterojunction semiconductor device according to claim 2 , wherein the current barrier layer is disposed at least at a lower side of the gate electrode.4. The nitride-based heterojunction semiconductor device according to claim 2 , wherein the current barrier layer extends from a lower side of the source electrode to the lower side of the gate electrode.5. The nitride-based heterojunction semiconductor device according to claim 1 , wherein the current barrier layer comprises high-resistance gallium nitride.6. The nitride- ...

METHOD FOR TESTING GROUP III-NITRIDE WAFERS AND GROUP III-NITRIDE WAFERS WITH TEST DATA

The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control. 1. A certified Group III-nitride wafer comprising (i) a documentation of a value of a physical property in combination with (ii) a wafer from a first set of Group III-nitride substrates cut from an ingot formed using a seed material , wherein the value of the physical property is derived by a method comprisinga) selecting substrates from the first set of substrates to form a second set of substrates, the second set of substrates being a subset of the first set and therefore being a selection of substrates from the first set of substrates that does not include all members from the first set of substrates, the second set of substrates having at least one substrate selected from the substrates cut from a portion of the ingot located on one side of a seed used to form the ingot, and the second set of substrates having at least one substrate selected from the substrates cut from a second portion of the ingot located on the other side of the seed,b) analyzing samples taken from the substrates of the second set to assess values of a first property of each of the substrates of the second set, i) applying said correlation to substrates not in said second set of substrates to provide estimated values of said first property for said substrates; or', 'ii) comparing said correlation against a value of said property for ...

SELF-ALIGNED SIDEWALL GATE GaN HEMT

A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length. 127-. (canceled)28. A GaN HEMT comprising:a substrate;a buffer layer comprising a first epitaxial layer on the substrate;a channel comprising a second epitaxial layer on the buffer layer;a top barrier comprising a third epitaxial layer on the second epitaxial layer;a first sidewall dielectric spacer on the third epitaxial layer;a second sidewall dielectric spacer on the third epitaxial layer;a sidewall gate on the third epitaxial layer between the first sidewall dielectric spacer and the second sidewall dielectric spacer;a first ohmic contact for a source separated from the sidewall gate by the first sidewall dielectric spacer;a source contact on the first ohmic contact;a second ohmic contact for a drain separated from the sidewall gate by the second sidewall dielectric spacer;a drain contact on the second ohmic contact;a photoresist over the first ohmic contact, the source contact, the second ohmic contact, and the drain contact such that the first and second sidewall dielectric spacers and the sidewall gate protrude from the photoresist; anda gate head in contact with the sidewall gate, wherein a width of the gate head is wider than a width of the sidewall gate.29. The GaN HEMT of wherein:the first epitaxial layer comprises AlGaN;the second epitaxial layer comprises GaN; andthe third epitaxial layer comprises AlGaN or AlN; andthe substrate comprises sapphire, SiC, silicon, or GaN.30. The GaN HEMT of :wherein the sidewall gate is refractory gate material comprising W, TiW, Ta, Mo, or TaN.31 ...

DEVICE STRUCTURE INCLUDING HIGH-THERMAL-CONDUCTIVITY SUBSTRATE

Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside of the active layer faces away from the first substrate, forming a second substrate over the backside of the active layer, and removing the first substrate to expose the frontside of the active layer. Other embodiments are described and claimed. 1. A method comprising: a first substrate;', 'an etch stop layer including aluminum gallium arsenide or indium gallium phosphide formed over the first substrate;', 'an inverted epitaxial structure formed over etch stop layer in a manner such that the etch stop layer is between the first substrate and the inverted epitaxial structure and such that a frontside of the inverted epitaxial structure faces the etch stop layer and a backside of the inverted epitaxial structure faces away from the etch stop layer; and', 'a bonding layer formed over the backside of the inverted epitaxial structure;, 'providing an apparatus includingafter providing the apparatus, forming a second substrate over the bonding layer such that the bonding layer is between the backside and the second substrate; andafter said forming the second substrate, removing the first substrate and the etch stop layer to expose the frontside of the inverted epitaxial structure.2. The method of claim 1 , wherein said forming the second substrate comprises forming a high thermal conductivity material over the oxide layer.3. The method of claim 2 , wherein the high thermal conductivity material comprises a material selected from polycrystalline silicon carbide claim 2 , diamond claim 2 , or aluminum nitride.4. The method of claim 1 , wherein said forming of the second substrate over the oxide layer comprises wafer bonding the second substrate to the oxide ...

P-Type Amorphous GaNAs Alloy as Low Resistant Ohmic Contact to P-Type Group III-Nitride Semiconductors

A new composition of matter is described, amorphous GaNAs:Mg, wherein 0 Подробнее

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A nitride semiconductor layer formed from a nitride semiconductor is provided on at least one surface side of a semiconductor substrate. Impurity regions (a source region, a drain region, and the like) are provided on one surface side in the nitride semiconductor layer and contain an impurity of a first conductivity type. In addition, amorphous regions (a first amorphous region and a second amorphous region) are a part of the impurity regions and are located in a surface layer of the impurity regions. In addition, metallic layers (a source electrode and a drain electrode) come into contact with the amorphous regions (the first amorphous region and the second amorphous region). 1. A semiconductor device , comprising:a semiconductor substrate that includes a nitride semiconductor layer formed from a nitride semiconductor on at least one surface side;an impurity region that is provided on the one surface side in the nitride semiconductor layer and contains a first conductivity type impurity;an amorphous region that is a part of the impurity region and is located in a surface layer of the impurity region; anda metallic layer that comes into contact with the amorphous region.2. The semiconductor device according to claim 1 ,wherein the amorphous region includes a crystal defect that is formed by ion implantation of the impurity.3. The semiconductor device according to claim 1 ,wherein the amorphous region and the metallic layer come into ohmic contact with each other.4. The semiconductor device according to claim 1 ,wherein the amorphous region includes a microcrystalline region in which a grain size is equal to or less than 10 nm.5. The semiconductor device according to claim 1 , further comprising:a source region that is provided in the nitride semiconductor layer and is a first of the impurity region;a drain region that is provided in the nitride semiconductor layer to be spaced apart from the source region in a plan view and that is a second of the impurity region;a ...

Gallium Nitride Devices with Vias

Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. 127-. (canceled)2842-. (canceled)43. A transistor comprising a source electrode , a drain electrode and a gate electrode , said transistor further comprising:a substrate;a transition layer situated over said substrate;a gallium nitride layer situated over said transition layer;a via that extends through at least a portion of said substrate;a barrier layer along sidewalls of said via;an electrically conductive layer on a back surface of said substrate.44. The transistor of claim 43 , wherein said substrate comprises silicon.45. The transistor of claim 43 , wherein said electrically conductive layer comprises aluminum.46. The transistor of claim 43 , wherein said electrically conductive layer includes a first portion comprising gold and a second portion comprising aluminum.47. The transistor of further comprising a passivating layer situated over said gallium nitride layer.48. The transistor of claim 43 , wherein said gate electrode is defined by an electrode-defining layer comprising silicon nitride.49. The transistor of ...

III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME

Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. 1. An indium gallium nitride (InGaN) layer , comprising:a first InGaN sublayer; andat least a second InGaN sublayer disposed over the first InGaN sublayer;wherein a total thickness of the InGaN layer equals a sum of a thickness of the first InGaN sublayer and a thickness of the at least a second InGaN sublayer, the total thickness of the InGaN layer being greater than a critical thickness of the first InGaN sublayer and less than a critical thickness of the at least a second InGaN sublayer.2. The InGaN layer of claim 1 , wherein a concentration of indium in the first InGaN sublayer is at least substantially equal to a concentration of indium in the at least a second InGaN sublayer.3. The InGaN layer of claim 1 , wherein a concentration of indium in the InGaN layer is at least substantially constant across the total thickness of the InGaN layer.4. The InGaN layer of claim 1 , wherein the InGaN layer is at least substantially free of strain relaxation.5. The InGaN layer of claim 1 , wherein the InGaN layer has an indium concentration of at least about 5% and a total thickness of at least about 200 nm.6. The InGaN layer of claim 1 , wherein the InGaN layer has a concentration of indium of at least about 8% and a total thickness of at least about 150 nm.7. An indium gallium nitride (InGaN) layer claim 1 , comprising:a first InGaN sublayer having a thickness less than or equal to a critical thickness of ...

EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, PN JUNCTION DIODE, AND METHOD FOR MANUFACTURING AN EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT

Provided is an epitaxial substrate for use in a semiconductor element, having excellent characteristics and capable of suitably suppressing diffusion of elements from a cap layer. An epitaxial substrate for use in a semiconductor element, in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate, includes: a channel layer made of a first group-III nitride having a composition of InAlGaN (x1+y1+z1=1, z1>0); a barrier layer made of a second group-III nitride having a composition of InAlN (x2+y2=1, x2>0, y2>0); an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and a cap layer made of a third group-III nitride having a composition of InAlGaN (x3+y3+z3=1, z3>0). 1. An epitaxial substrate for use in a semiconductor element , in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of said group of group-III nitride layers is substantially in parallel with a substrate surface of said base substrate , said epitaxial substrate comprising:{'sub': x1', 'y1', 'z1, 'a channel layer made of a first group-III nitride having a composition of InAlGaN (x1+y1+z1=1, z1>0);'}{'sub': x2', 'y2, 'a barrier layer made of a second group-III nitride having a composition of InAlN (x2+y2=1, x2>0, y2>0);'}an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and{'sub': x3', 'y3', 'z3, 'a cap layer made of a third group-III nitride having a composition of InAlGaN (x3+y3+z3=1, z3>0).'}2. The epitaxial substrate according to claim 1 , whereina band gap of said second group-III nitride is larger than a band gap of said first group-III nitride.3. The epitaxial substrate according to claim 1 , wherein{'sub': x2', 'y2, 'said second group-III nitride is InAlN (x2+y2=1, 0.14≦x2≦0.24),'}{'sub': y3', 'z3, 'said third group-III nitride is ...

NITRIDE SEMICONDUCTOR DIODE

Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current. 1. A nitride semiconductor diode comprising:a substrate;a heterojunction stacked film on which a first nitride semiconductor layer formed on the substrate and a second nitride semiconductor layer greater in band gap energy than the first nitride semiconductor layer are stacked;a cathode electrode ohmically connected with the side face of the stacked film; andan anode electrode,wherein the stacked film is provided with a recessed portion which reaches the depth of a heterojunction surface being the interface of the first and second nitride semiconductor layers,wherein the recessed portion is provided with an region where at least one type of impurity selected from among a group of carbon (C), iron (Fe), zinc (Zn), and magnesium (Mg) is implanted, andwherein the anode electrode contacts the region and is Schottky connected with the stacked film.2. The nitride semiconductor diode according to claim 1 , wherein the region is formed by implanting the impurity into the stacked film itself or forming a film including the impurity.3. The nitride semiconductor diode according to claim 1 , wherein the region includes C or Fe with a density of 4×10cmor more or Mg with a density of 1×10cmor more.4. The nitride semiconductor diode according to claim 1 , wherein the density of the impurity in the region is higher than that of the impurity in the stacked film of the interface between the cathode ...

Formation of Devices by Epitaxial Layer Overgrowth

Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer. 1. A semiconductor structure comprising:a substrate;a first semiconductor layer over the substrate, the first semiconductor layer comprising a first p-n junction having a first band gap;a second semiconductor layer over the first semiconductor layer, the second semiconductor layer comprising a second p-n junction having a second band gap, the second band gap being greater than the first band gap; anda third semiconductor layer over the second semiconductor layer, the third semiconductor layer comprising a third p-n junction having a third band gap, the third band gap being greater than the second band gap.2. The semiconductor structure of claim 1 , wherein the first semiconductor layer is approximately 2 micrometers.3. The semiconductor structure of claim 1 , wherein the first semiconductor layer comprises InGaAs claim 1 , the second semiconductor layer comprises GaAs claim 1 , and the third semiconductor layer comprises InGaP.4. The semiconductor structure of further comprising a buffer layer between the first semiconductor layer and the second ...

GaN-based Semiconductor Element and Method of Manufacturing the Same

Provided is a GaN series semiconductor element, which is capable of obtaining an adequate normally-off characteristic, and a manufacturing method thereof. 1. A method for manufacturing a gallium nitride (GaN) series semiconductor element , comprising:forming an operating layer comprising a GaN series compound semiconductor layer that is stacked on a substrate via a buffer layer;forming a gate insulating film on the operating layer; andforming a gate electrode on the gate insulating film,{'sub': '2', 'wherein the forming the gate insulating film comprises forming a SiOfilm by an atmospheric pressure chemical vapor deposition (CVD) method.'}2. The method of claim 1 , wherein the forming the gate insulating film comprises forming the gate insulating film using at least silane as a raw material gas in a process of forming the SiOfilm by the atmospheric pressure CVD method.3. The method of claim 1 , wherein the forming the gate insulating film comprises forming the gate insulating film at a temperature of 400 degrees centigrade or approximately 400 degrees centigrade in a process of forming the SiOfilm by the atmospheric pressure CVD method.4. The method of claim 1 , wherein the forming the gate insulating film comprises forming the gate insulating film at a pressure higher than 450 hectopascals and lower than 1100 hectopascals in a process of forming the SiOfilm by the atmospheric pressure CVD method.5. The method of claim 1 , further comprising forming the buffer layer to comprise alternately stacked GaN layers and aluminum nitride (AIN) layers.6. The method of claim 1 , further comprising forming a channel layer comprising a p-GaN layer.7. The method of claim 6 , wherein the forming the operating layer comprises:forming an electron transit layer comprising undoped GaN; andforming an electron supply layer comprising a GaN series semiconductor, wherein the electron supply layer has a larger bandgap energy than the electron transit layer.8. The method of claim 7 , ...

Ingan ohmic source contacts for vertical power devices

A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

INTERNALLY REFORMED SUBSTRATE FOR EPITAXIAL GROWTH, INTERNALLY REFORMED SUBSTRATE WITH MULTILAYER FILM, SEMICONDUCTOR DEVICE, BULK SEMICONDUCTOR SUBSTRATE, AND MANUFACTURING METHODS THEREFOR

Provided are an internally reformed substrate for epitaxial growth having an arbitrary warpage shape and/or an arbitrary warpage amount, an internally reformed substrate with a multilayer film using the internally reformed substrate for epitaxial growth, a semiconductor device, a bulk semiconductor substrate, and manufacturing methods therefor. The internally reformed substrate for epitaxial growth includes: a single crystal substrate; and a heat-denatured layer formed in an internal portion of the single crystal substrate by laser irradiation to the single crystal substrate. 1. An internally reformed substrate for epitaxial growth , comprising:a single crystal substrate; anda heat-denatured layer formed in an internal portion of the single crystal substrate by laser irradiation to the single crystal substrate.2. An internally reformed substrate for epitaxial growth according to claim 1 , wherein the laser irradiation is performed so as to satisfy at least one of irradiation conditions A and B described below. laser wavelength: 200 nm to 400 nm', 'pulse width: order of nanoseconds, ''} laser wavelength: 400 nm to 5,000 nm', 'pulse width: order of femtoseconds to order of picoseconds, ''}3. An internally reformed substrate for epitaxial growth according to or claim 1 , wherein claim 1 , when a relative position of the heat-denatured layer in a thickness direction of the single crystal substrate is assumed to be 0% at one surface serving as a film formation surface and 100% at a surface opposite to the film formation surface claim 1 , the heat-denatured layer is provided in a range of 3% or more and 95% or less in the thickness direction of the single crystal substrate.4. An internally reformed substrate for epitaxial growth according to any one of to claim 1 , wherein claim 1 , in a planar direction of the single crystal substrate claim 1 , the heat-denatured layer is provided to have at least one pattern shape ...

NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A nitride based semiconductor device includes a first metallic junction layer, a Schottky junction layer on the first metallic junction layer, a first group III nitride semiconductor layer on the Schottky junction layer, a first insulating pattern layer on the first group III nitride semiconductor layer, the first insulating layer pattern including curved protrusions, a second group III nitride semiconductor layer laterally grown on the first group III nitride semiconductor layer, a first type group III nitride semiconductor layer on the second group III nitride semiconductor layer, the first type group III nitride semiconductor layer being simultaneously doped with aluminum (Al) and silicon (Si), an ohmic junction layer formed on the first type group III nitride semiconductor layer, a second metallic junction layer on the ohmic junction layer, and a metallic supporting substrate on the second metallic junction layer. 1. A nitride based semiconductor device , comprising:a first metallic junction layer;a Schottky junction layer on the first metallic junction layer;a first group III nitride semiconductor layer on the Schottky junction layer;a first insulating pattern layer on the first group III nitride semiconductor layer, the first insulating pattern layer including curved protrusions;a second group III nitride semiconductor layer laterally grown on the first group III nitride semiconductor layer that is exposed through the first insulating pattern layer;a first type group III nitride semiconductor layer on the second group III nitride semiconductor layer, the first type group III nitride semiconductor layer being simultaneously doped with aluminum (Al) and silicon (Si);an ohmic junction layer on the first type group III nitride semiconductor layer;a second metallic junction layer on the ohmic junction layer; anda metallic supporting substrate on the second metallic junction layer.2. The nitride based semiconductor device as claimed in claim 1 , wherein the second ...

POLYCRYSTALLINE ALUMINUM NITRIDE BASE MATERIAL FOR CRYSTAL GROWTH OF GaN-BASE SEMICONDUCTOR AND METHOD FOR MANUFACTURING GaN-BASE SEMICONDUCTOR USING THE SAME

There is provided a polycrystalline aluminum nitride substrate that is effective in growing a GaN crystal. The polycrystalline aluminum nitride base material for use as a substrate material for grain growth of GAN-base semiconductors, contains 1 to 10% by weight of a sintering aid component and has a thermal conductivity of not less than 150 W/m·K, the substrate having a surface free from recesses having a maximum diameter of more than 200 μm. 1. A polycrystalline aluminium nitride base material for use as a substrate material for grain growth of GaN-base semiconductors , the polycrystalline aluminium nitride base material containing 1 to 10% by weight of a sintering aid component and having a thermal conductivity of not less than 150 W/m·K , and the substrate having a surface free from recesses having a maximum diameter of more than 200 μm.2. The polycrystalline aluminum nitride base material according to claim 1 , wherein the sintering aid component comprises one or more materials selected from the group consisting of rare earth elements claim 1 , rare earth element oxides claim 1 , and rare earth element-aluminum oxides.3. The polycrystalline aluminum nitride substrate according to claim 1 , wherein the recesses are any one of pores claim 1 , traces after dropping of AlN crystal grains claim 1 , and traces after dropping of the sintering aid component.4. The polycrystalline aluminum nitride substrate according to claim 1 , wherein the maximum diameter of the recesses is not more than 50 μm.5. The polycrystalline aluminum nitride substrate according to claim 1 , which has a surface roughness (Ra) of not more than 0.1 μm.6. The polycrystalline aluminum nitride base material according to claim 1 , which comprises an aluminum nitride crystal and a grain boundary phase claim 1 , grains of the aluminum nitride crystal having a mean diameter of not more than 7 μm.7. The polycrystalline aluminum nitride base material according to claim 1 , wherein the substrate has a ...

PROTECTIVE-FILM-ATTACHED COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A protective-film-attached composite substrate includes a support substrate, an oxide film disposed on the support substrate, a semiconductor layer disposed on the oxide film, and a protective film protecting the oxide film by covering a portion that is a part of the oxide film and covered with none of the support substrate and the semiconductor layer. A method of manufacturing a semiconductor device includes the steps of: preparing the protective-film-attached composite substrate; and epitaxially growing, on the semiconductor layer of the protective-film-attached composite substrate, at least one functional semiconductor layer causing an essential function of a semiconductor device to be performed. Thus, there are provided a protective-film-attached composite substrate having a large effective region where a high-quality functional semiconductor layer can be epitaxially grown, and a method of manufacturing a semiconductor device in which the protective-film-attached composite substrate is used. 1. A protective-film-attached composite substrate comprising: a support substrate; an oxide film disposed on said support substrate; a semiconductor layer disposed on said oxide film; and a protective film protecting said oxide film by covering a portion that is a part of said oxide film and covered with none of said support substrate and said semiconductor layer.2. The protective-film-attached composite substrate according to claim 1 , wherein said oxide film is at least one selected from the group consisting of TiOfilm claim 1 , SrTiOfilm claim 1 , indium tin oxide film claim 1 , antimony tin oxide film claim 1 , ZnO film claim 1 , and GaOfilm.3. The protective-film-attached composite substrate according to claim 2 , wherein at least one of said support substrate and said semiconductor layer is formed of a group III nitride.4. The protective-film-attached composite substrate according to claim 1 , wherein at least one of said support substrate and said semiconductor layer ...

SEMICONDUCTOR-STACKED SUBSTRATE, SEMICONDUCTOR CHIP, AND METHOD FOR PRODUCING SEMICONDUCTOR-STACKED SUBSTRATE

Disclosed is a semiconductor-stacked substrate having a substrate, and a plurality of semiconductor layers which are different in thermal expansion coefficient from the substrate, and are formed in a plurality of regions of a surface of the substrate, respectively. Each semiconductor layer has a growth plane that is a nonpolar plane or a semi-polar plane, and has different thermal expansion coefficients between along a first axis and a second axis orthogonal to each other and parallel to the surface of the substrate. The following mathematical formula 1 is satisfied. D and ρ represent, respectively, the length and the curvature radius of the semiconductor layer in a direction which passes through a point where the deformation amount of the semiconductor layer is largest and is parallel to the first axis direction. D and ρ represent those of the second axis direction. 3. The semiconductor-stacked substrate according to claim 2 , wherein the stresses include distortion stress.41212. The semiconductor-stacked substrate according to claim 1 , wherein the lengths D and D are different from each other claim 1 , and radii ρ and ρ are different from each other.611. The semiconductor-stacked substrate according to claim 1 , wherein the length D is defined claim 1 , using the radius ρ and the maximum deformation amount Hof each of the semiconductor layers as the following mathematical formula 4:{'br': None, '[Math. 4]'}{'br': None, 'i': D', 'H, 'sub': 'max', '1≅√{square root over (8ρ1)}\u2003\u2003Mathematical formula 4'}722. The semiconductor-stacked substrate according to claim 1 , wherein the length D is defined claim 1 , using the radius ρ and the maximum deformation amount Hof the each of semiconductor layers as the following mathematical formula 5:{'br': None, '[Math. 5]'}{'br': None, 'i': D', 'H, 'sub': 'max', '2≅√{square root over (8ρ2)}\u2003\u2003Mathematical formula 5'}8. The semiconductor-stacked substrate according to claim 6 , wherein a center of each of the ...

Semiconductor wafer and insulated gate field effect transistor

Provided is a technique capable of realizing an insulated gate (MIS-type) P-HEMT structure with good transistor characteristics such as an improved carrier mobility of a channel layer and a reduced influence from interface states. A semiconductor wafer includes a base wafer, a first crystalline layer, and an insulating layer. The base wafer, the first crystalline layer, and the insulating layer are stacked in the order of the base wafer, the first crystalline layer, and the insulating layer. The first crystalline layer is made of In x Ga 1-x As (0.35≦x≦0.43) that can pseudo-lattice-match with GaAs or AlGaAs. The first crystalline layer is usable as a channel layer of a field effect transistor, and the insulating layer is usable as a gate insulating layer of the field effect transistor.

METHOD OF GROWING NITRIDE SEMICONDUCTOR LAYER

A method of growing a nitride semiconductor layer may include preparing a substrate in a reactor, growing a first nitride semiconductor on the substrate at a first temperature, the first nitride semiconductor having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate, and removing the substrate at a second temperature. 1. A method of growing a nitride semiconductor layer , the method comprising:preparing a substrate in a reactor;growing a first nitride semiconductor on the substrate at a first temperature, the first nitride semiconductor having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate; andremoving the substrate at a second temperature.2. The method of claim 1 , wherein the growing a first nitride semiconductor includes growing the first nitride semiconductor on the substrate at the first temperature equal to or higher than 950° C. claim 1 , and the removing the substrate includes removing the substrate at the second temperature equal to or higher than 400° C.3. The method of claim 1 , wherein the growing a first nitride semiconductor includes growing gallium nitride.4. The method of claim 1 , wherein the reactor is a hydride vapor phase epitaxy (HVPE) reactor claim 1 , the preparing a substrate includes preparing the substrate in the HVPE claim 1 , and the growing a first nitride semiconductor includes growing the first nitride semiconductor using HVPE.5. The method of claim 4 , wherein the growing a first nitride semiconductor includes growing the first nitride semiconductor on the substrate at the first temperature ranging from about 950° C. to about 1100° C.6. The method of claim 1 , further comprising:stacking a second nitride semiconductor on the first nitride semiconductor after the removing the substrate.7. The method of claim 6 , wherein the stacking a second nitride semiconductor includes stacking the second nitride semiconductor having a thickness equal to or ...

HIGH VOLTAGE SWITCHING DEVICES AND PROCESS FOR FORMING SAME

The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV). 1. A microelectronic device structure , comprising:{'sup': 6', '2, 'a first GaN layer having a top surface characterized by a dislocation defect density of not more than 5×10/cm;'}a second, conductive GaN layer overlying said first GaN layer;{'sup': 16', '3, 'a third GaN layer overlying said second, conductive GaN layer, said third GaN layer having a dopant concentration of not more than 1×10/cmand a thickness of at least 2.5 μm; and'}at least one metal contact over said third GaN layer, forming a metal-to-semiconductor junction therewith.2. The microelectronic device structure of claim 1 , having a breakdown voltage of at least 320V.3. The microelectronic device structure of claim 1 , further comprising a substrate claim 1 , wherein the first GaN layer is overlying the substrate.4. The microelectronic device structure of claim 3 , wherein the substrate comprises a foreign substrate claim 3 , and the microelectronic device structure further comprises a nucleation buffer layer disposed between the first GaN layer and the foreign substrate.5. The microelectronic device structure of claim 4 , wherein the foreign substrate comprises a material selected from the group consisting of sapphire claim 4 , Si claim 4 , and SiC.6. The microelectronic device structure of claim 1 , wherein the third GaN layer is less than 20 μm in thickness.7. The microelectronic device structure of claim 1 , wherein the third GaN layer is less than 50 μm in thickness.8. The microelectronic device structure of ...

NITRIDE BASED HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A nitride based heterojunction semiconductor device includes a GaN layer on a substrate, an Al-doped GaN layer on the GaN layer, an AlGaN layer on the Al-doped GaN layer, a source electrode, a gate electrode, and a drain electrode on the AlGaN layer, a first field plate on the AlGaN layer, the first field plate being in contact with the gate electrode, and a second field plate on the AlGaN layer, the second field plate being separated from the first field plate by a distance. 1. A nitride based heterojunction semiconductor device , comprising:a GaN layer on a substrate;an Al-doped GaN layer on the GaN layer;an AlGaN layer on the Al-doped GaN layer;a source electrode, a gate electrode, and a drain electrode on the AlGaN layer;a first field plate on the AlGaN layer, the first field plate being in contact with the gate electrode; anda second field plate on the AlGaN layer, the second field plate being separated from the first field plate by a distance.2. The semiconductor device as claimed in claim 1 , wherein the first field plate and the second field plate have a superlattice structure in which a p-type AlGaN layer and a p-type GaN layer are laminated alternately.3. The semiconductor device as claimed in claim 1 , wherein the AlGaN layer includes an etched area at a position in which the gate electrode is located.4. The semiconductor device as claimed in claim 3 , further comprising:a gate insulating layer between the etched area and the gate electrode.5. The semiconductor device as claimed in claim 3 , wherein a sidewall of the etched area and a sidewall of the first field plate are aligned.6. The semiconductor device as claimed in claim 1 , further comprising:a passivation layer on the AlGaN layer, the passivation layer exposing the source electrode, the gate electrode, and the drain electrode.7. The semiconductor device as claimed in claim 1 , wherein the GaN layer is a semi-insulating high-resistance GaN layer.8. The semiconductor device as claimed in claim 1 , ...

NITRIDE BASED HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A nitride based heterojunction semiconductor device includes a gallium nitride (GaN) layer disposed on a substrate, an aluminum (Al)-doped GaN layer disposed on the GaN layer, a Schottky electrode disposed in a first area on the Al-doped GaN layer, an AlGaN layer disposed in a second area on the Al-doped GaN layer, and an ohmic electrode disposed on the AlGaN layer. The first area is different from the second area. 1. A nitride based heterojunction semiconductor device , comprising:a gallium nitride (GaN) layer disposed on a substrate;an aluminum (Al)-doped GaN layer disposed on the GaN layer;a Schottky electrode disposed in a first area on the Al-doped GaN layer;an AlGaN layer formed in a second area on the Al-doped GaN layer, the second area being different from the first area; andan ohmic electrode disposed on the AlGaN layer.2. The semiconductor device of claim 1 , further comprising:an undoped GaN layer disposed on the Al-doped GaN layer.3. The semiconductor device of claim 1 , wherein a content of Al in the Al-doped GaN layer is in the range of 0.3% to 0.6%.4. The semiconductor device of claim 2 , wherein the Al-doped GaN layer and the undoped GaN layer have thicknesses in the range of 0.1 micrometers (μm) to 1.0 μm.5. A method of manufacturing a nitride based heterojunction semiconductor device claim 2 , the method comprising steps of:growing a gallium nitride (GaN) layer on a substrate;growing an aluminum (Al)-doped GaN layer on the GaN layer;forming an insulating layer in a first area on the Al-doped GaN layer;growing an AlGaN layer in a second area on the Al-doped GaN layer, the second area being different from the first area;removing the insulating layer to expose the first area on the Al-doped GaN layer;forming a Schottky electrode on the Al-doped GaN layer in an area that is exposed through the first area; andforming an ohmic electrode on the AlGaN layer.6. The method of claim 5 , further comprising the step of:growing an undoped GaN layer on the Al- ...

NITRIDE BASED HETEROJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A nitride based heterojunction semiconductor device includes a gallium nitride (GaN) layer disposed on a substrate, an aluminum (Al)-doped GaN layer disposed on the GaN layer, an AlGaN layer disposed on the Al-doped GaN layer, an ion-implanted layer disposed in an area on the AlGaN layer, excluding a first area and a second area. 1. A nitride based heterojunction semiconductor device , comprising:a gallium nitride (GaN) layer disposed on a substrate;an aluminum (Al)-doped GaN layer disposed on the GaN layer;an AlGaN layer disposed on the Al-doped GaN layer; andan ion-implanted layer disposed on an area of the AlGaN layer, excluding a first area and a second area.2. The semiconductor device of claim 1 , wherein the ion-implanted layer includes at least one ion selected from the group consisting of argon (Ar) claim 1 , carbon (C) claim 1 , hydrogen (H) claim 1 , and nitrogen (N).3. The semiconductor device of claim 1 , further comprising:a passivation layer disposed on the ion-implanted layer.4. The semiconductor device of claim 1 , further comprising:a Schottky electrode disposed in the first area; andan ohmic electrode disposed in the second area.5. The semiconductor device of claim 1 , wherein the ion-implanted layer is disposed in an area on the AlGaN layer claim 1 , excluding a third area that is separate from the first and second areas.6. The semiconductor device of claim 5 , further comprising:a source electrode disposed in the first area;a gate insulating layer disposed in the second area;a gate electrode disposed on the gate insulating layer; anda drain electrode disposed in the third area.7. The semiconductor device of claim 6 , wherein the AlGaN layer has an etched area in which the Al-doped GaN layer is exposed through the second area.8. The semiconductor device of claim 7 , wherein the gate insulating layer is disposed between the etched area and the gate electrode.9. A method of manufacturing a nitride based heterojunction semiconductor device claim 7 , ...

InGaN-Based Double Heterostructure Field Effect Transistor and Method of Forming the Same

A double heterojunction field effect transistor (DHFET) includes a substrate, a buffer layer consisting of GaN back-barrier buffer layer formed on the substrate, a channel layer consisting of an InGaN ternary alloy in one embodiment, and in another embodiment, InGaN/GaN superlattice (SL) formed on the GaN back-barrier buffer layer opposite to the substrate. A GaN spacer layer is formed on the InGaN or InGaN/GaN superlattice channel layer opposite to the GaN buffer layer and a carrier-supplying layer consisting of an AlInN ternary alloy is formed on the GaN spacer layer opposite to the channel layer. A preferred thickness of the GaN spacer layer is less than about 1.5 nm. The InGaN/GaN SL preferably includes 1 to 5 InGaN—GaN pairs and a preferred thickness of the InGaN layer in the InGaN/GaN SL is equal to or less than about 0.5 nm. A two-dimensional electron gas is formed at the interface between the InGaN or InGaN/GaN SL channel and GaN spacer layers. 1. A double-heterojunction field effect transistor , comprising:a) a substrate;b) a GaN back-barrier buffer layer on said substrate; [{'sub': x', '1-x, 'i) a InGaN channel layer on said GaN back-barrier buffer layer opposite said substrate, and'}, {'sub': x', '1-x, 'ii) a GaN spacer layer on said InGaN channel layer opposite said GaN back-barrier buffer layer, wherein a two-dimensional electron gas region is contained within the composite channel layer; and'}], 'c) a composite channel layer, the composite channel layer including,'}{'sub': x', '1-x, 'd) a carrier-supplying barrier layer on said GaN spacer layer opposite InGaN channel layer.'}2. The double-heterojunction field effect transistor of claim 1 , wherein the carrier-supplying barrier layer comprises AlInN.3. The double-heterojunction field effect transistor of claim 2 , wherein the carrier-supplying barrier layer comprises of AlGaN claim 2 , wherein 0.1≦z≦1.4. The double-heterojunction field effect transistor of claim 1 , wherein said GaN spacer layer is less ...

Power Device with Solderable Front Metal

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

METHOD FOR PRODUCING GALLIUM NITRIDE SUBSTRATES FOR ELECTRONIC AND OPTOELECTRONIC DEVICES

A method for separating a III-nitride layer from a substrate. This is done by fabricating a detachment porous region between the III-nitride layer and the substrate through etching. The porous region allows for easy detachment of the III-nitride layer from the substrate. Active layers for electronic and optoelectronic devices can then be grown on the III-nitride layer. 1. A method for separating at least one III-nitride layer from a substrate , comprising:fabricating a porous region between the III-nitride layer and the substrate through etching; andseparating the III-nitride layer from the substrate at the porous region.2. The method of claim 1 , wherein the substrate is a binary claim 1 , ternary claim 1 , or quaternary compound of the III-nitrides materials family.3. The method of claim 1 , wherein one or more active layers are grown on the III-nitride layer.4. The method of claim 1 , wherein the III-nitride layer is a single layer or is comprised of a plurality of sublayers.5. The method of claim 1 , wherein the fabricating step is performed by chemically etching the porous region in a vapor or liquid phase.6. The method of claim 1 , wherein the fabricating step is performed by electrochemically etching the porous region in a liquid phase.7. The method of claim 6 , wherein the chemically etching step is performed by photo-assisted electrochemically etching the porous region in a liquid phase.8. The method of claim 1 , wherein the fabricating step is performed by etching the porous region at a lower porosity.9. The method of claim 1 , wherein the fabricating step is performed by etching the porous region at a higher porosity after etching the etching the porous region at the lower porosity.10. The method of claim 9 , wherein the porous region includes two or more sublayers with different porosities.11. The method of claim 10 , wherein at least one of the sublayers has a higher porosity and is a preferred layer for being separated.12. The method of claim 10 , ...

Power Transistor Having Segmented Gate

There are disclosed herein various implementations of a transistor having a segmented gate region. Such a transistor may include at least one segmentation dielectric segment and two or more gate dielectric segments. The segmentation dielectric segment or segments are thicker than the gate dielectric segments, and is/are situated between the gate dielectric segments. The segmentation dielectric segment or segments cause an increase in the effective gate length so as to improve resistance to punch-through breakdown between a drain electrode and a source electrode of the transistor when the transistor is off.

Semiconductor Component and Method for Producing a Semiconductor Component

A semiconductor component has a semiconductor layer sequence made of a nitridic composite semiconductor material on a substrate. The substrate includes a silicon surface facing the semiconductor layer sequence. The semiconductor layer sequence includes an active region and at least one intermediate layer made of an oxygen-doped AN composite semiconductor material between the substrate and the active region. 115-. (canceled)16. A semiconductor component comprising:a semiconductor layer sequence composed of a nitridic compound semiconductor material on a substrate,wherein the substrate has a silicon surface facing the semiconductor layer sequence; andwherein the semiconductor layer sequence has an active region and an intermediate layer composed of an oxygen-doped AN compound semiconductor material between the substrate and the active region.17. The semiconductor component according to claim 16 , wherein the oxygen content of the intermediate layer is greater than or equal to 0.1% and less than or equal to 5%.18. The semiconductor component according to claim 16 , wherein the intermediate layer has a thickness of greater than or equal to 5 nm and less than or equal to 300 nm.19. The semiconductor component according to claim 16 , wherein the intermediate layer comprises a nucleation layer applied directly on the substrate.20. The semiconductor component according to claim 16 , wherein the intermediate layer comprises a transition layer or part of a transition layer between the active region and a nucleation layer.21. The semiconductor component according to claim 20 , wherein a plurality of intermediate layers are arranged between the active region and the nucleation layer as the transition layer or part of the transition layer.22. The semiconductor component according to claim 16 , wherein the intermediate layer is arranged between a transition layer and the active region.23. The semiconductor component according to claim 22 , wherein the intermediate layer has a ...

METHOD FOR TREATING A SUBSTRATE AND A SUBSTRATE

A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET. 1. A method for producing a crystalline oxide layer on an In-containing III-As , III-Sb or III-P compound semiconductor substrate , characterized in that in vacuum conditionssurface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides, andthe cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate.2. The method according to claim 1 , characterized in that the In-containing III-As claim 1 , III-Sb or III-P substrate is made of InAs claim 1 , InSb claim 1 , InP claim 1 , InGaAs or InGaSb.3. The method according to or claim 1 , characterized in that the substrate is cleaned by argon-ion sputtering and post heating in ultra-high-vacuum (UHV) conditions at least to 400° C. claim 1 , or by pure heating in UHV at around 400-550° C.4. The method according to any of the preceding claims claim 1 , characterized in that the cleaned substrate is covered by tin (Sn) layer.5. The method according to any of the preceding claims claim 1 , characterized in that the cleaned In-containing III-As substrate is heated to a temperature of about 340-400° C.6. The method according to to claim 1 , characterized in that the cleaned In-containing III-Sb substrate is heated to a temperature of about 340-450° C.7. The method according to to claim 1 , characterized in that the cleaned In-containing III-P substrate is heated to a temperature of about 450-500° C.8. The method according ...

COMPOUND SEMICONDUCTOR DEVICE

The compound semiconductor device comprises an i-GaN buffer layer formed on an SiC substrate ; an n-AlGaN electron supplying layer formed on the i-GaN buffer layer ; an n-GaN cap layer formed on the n-AlGaN electron supplying layer ; a source electrode and a drain electrode formed on the n-GaN cap layer ; a gate electrode formed on the n-GaN cap layer between the source electrode and the drain electrode ; a first protection layer formed on the n-GaN cap layer between the source electrode and the drain electrode ; and a second protection layer buried in an opening formed in the first protection layer between the gate electrode and the drain electrode down to the n-GaN cap layer and formed of an insulation film different from the first protection layer. 16-. (canceled)7. A compound semiconductor device comprising:a GaN active layer formed over a semiconductor substrate;an AlGaN carrier supplying layer formed over the GaN active layer;a GaN cap layer formed over the AlGaN carrier supplying layer;a source electrode and a drain electrode formed over the GaN cap layer;a first protection layer formed over the GaN cap layer between the source electrode and the drain electrode and having an opening reaching the GaN cap layer between the source electrode and the drain electrode, a width of the opening being gradually increased from a surface of the GaN cap layer toward a direction of a thickness of the first protection film; anda gate electrode formed in the opening.8. The compound semiconductor device according to claim 7 , whereinthe gate electrode is formed, extended over the first protection layer.9. The compound semiconductor device according to claim 7 , whereinthe surface of the GaN cap layer is formed with atomic layer steps.10. The compound semiconductor device according to claim 8 , whereinthe surface of the GaN cap layer is formed with atomic layer steps.11. The compound semiconductor device according to claim 7 , whereinthe first protection layer is a stacked film ...

METHOD FOR GROWING GROUP 13 NITRIDE CRYSTAL AND GROUP 13 NITRIDE CRYSTAL

To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface. 1a first crystal layer that includes, in a cross section of the first crystal layer, grain boundaries present in a direction that intersects with a direction in which defects in a seed-crystal substrate extend; and{'sup': 4', '2, 'a second crystal layer that overlies the first crystal layer, that includes, in a cross section of the second crystal layer, none of the grain boundaries or less of the grain boundaries than the first crystal layer, and that includes a region having an etch pit density of 10/cmor less.'}. A group 13 nitride crystal in which a content of an alkali metal is not higher than a lower limit of detection by SIMS, the group 13 nitride crystal comprising: This application is a division of U.S. application Ser. No. 13/208,944 filed Aug. 12, 2011, which in turn is a continuation of International Application No. PCT/JP2009/071605 filed Dec. 15, 2009, which designated the United States, the entireties of which are incorporated herein by reference, and claims the benefit under 35 USC §119(a)-(d) of Japanese Application No. 2009-032779 filed Feb. 16, 2009.The present invention relates to a method for growing a group 13 nitride crystal and a group 13 nitride crystal.In recent years, production of semiconductor ...

SEMICONDUCTOR DEVICE

A semiconductor device has a shield plate electrode connected to a source terminal electrode near a drain electrode. The source terminal electrode is arranged between an active region AA and a drain terminal electrode, and a shield plate electrode is connected to the source terminal electrode. 1. A semiconductor device , comprising:a substrate;a gate electrode which is arranged on a first surface of the substrate and has a plurality of gate finger electrodes;a source electrode which is arranged on the first surface of the substrate and has a plurality of source finger electrodes, and the source finger electrode is close to the gate electrode;a drain electrode which is arranged on the first surface of the substrate and has a plurality of drain finger electrodes, and the drain finger electrode faces the source finger electrode via the gate finger electrode;a gate terminal electrode which is arranged on the first surface of said substrate and is connected to a plurality of the gate finger electrodes;a source terminal electrode which is arranged on the first surface of said substrate and is connected to a plurality of the source finger electrode;a drain terminal electrode which is arranged on the first surface of said substrate and is connected to a plurality of the drain finger electrodes;an insulating layer which is arrange to cover the gate finger electrode, the substrate between the gate finger electrode and the source finger electrode, the substrate between the gate finger electrode and the drain finger electrode, and at least a part of the source finger electrode and at least a part of the drain finger electrode; anda shield plate electrode which is arranged via the insulating layer over the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other; ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a substrate; a gate electrode which is arranged on a first surface of the substrate and has a plurality of gate finger electrodes, a source electrode which is arranged on the first surface of the substrate and has a plurality of source finger electrodes, the source finger electrode is close to the gate finger electrode; a drain electrode which is arranged on the first surface of the substrate and has a plurality of drain finger electrodes, the drain finger electrode faces the source finger electrode via the gate finger electrode; and a shield plate electrode which is arranged on the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode via an insulating layer, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other. 1. A semiconductor device , comprising:a substrate;a gate electrode which is arranged on a first surface of the substrate and has a plurality of gate finger electrodes,a source electrode which is arranged on the first surface of the substrate and has a plurality of source finger electrodes, the source finger electrode is close to the gate finger electrode;a drain electrode which is arranged on the first surface of the substrate and has a plurality of drain finger electrodes, the drain finger electrode faces the source finger electrode via the gate finger electrode;an insulating layer which covers the gate finger electrode, the substrate between the gate finger electrode and the source finger electrode, the substrate between the gate finger electrode and the drain finger electrode, at least a part of the source finger electrode, and at least a part of the drain finger electrode; anda shield plate electrode which is arranged over the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode ...

SEMICONDUCTOR DEVICE

A semiconductor device has a shield plate electrode short-circuited to a source electrode near the drain electrode. The shield plate electrode is connected to the source terminal electrode which has a VIA hole via the first line of air-bridge structure or overlay structure. 1. A semiconductor device , comprising:a substrate;a gate electrode which is arranged on a first surface of the substrate and has a plurality of gate finger electrodes;a source electrode which is arranged on the first surface of the substrate and has a plurality of source finger electrodes, and the source finger electrode is close to the gate electrode;a drain electrode which is arranged on the first surface of the substrate and has a plurality of drain finger electrodes, and the drain finger electrode faces the source finger electrode via the gate finger electrode;a gate terminal electrode which is arranged on the first surface of the substrate and is connected to the gate electrode;a source terminal electrode which is arranged on the first surface of the substrate and is connected to the source electrode;a drain terminal electrode which is arranged on the first surface of the substrate and is connected to the drain electrode;an insulating layer which is arranged so as to cover the gate finger electrode, the substrate between the gate finger electrode and the source finger electrode, the substrate between the gate finger electrode and the drain finger electrode, at least a part of the source finger electrode, and at least a part of the drain finger electrode;a shield plate electrode which is arranged via the insulating layer over the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other; anda first line which connects the shield plate electrode and the source terminal ...

SEMICONDUCTOR DEVICE

A semiconductor device, comprising: a substrate; a plurality of gate finger electrodes which are arranged on the substrate; a plurality of source finger electrodes which are arranged on the substrate, each source finger electrode is close to the gate finger electrode; a plurality of drain finger electrodes which are arranged on the substrate, each drain finger electrode faces the source finger electrode via the gate finger electrode; a shield plate electrode which is arranged via an insulating layer over the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other; and a slot VIA hole which is formed in the substrate under the source finger electrode and is connected to the source finger electrode. 1. A semiconductor device , comprising:a substrate;a gate electrode which is arranged on a first surface of the substrate and has a plurality of gate finger electrodes;a source electrode which is arranged on the first surface of the substrate and has a plurality of source finger electrodes, the source finger electrode is close to the gate finger electrode;a drain electrode which is arranged on the first surface of the substrate and has a plurality of drain finger electrodes, the drain finger electrode faces the source finger electrode via the gate finger electrode;an insulating layer which covers the gate finger electrode, the substrate between the gate finger electrode and the source finger electrode, the substrate between the gate finger electrode and the drain finger electrode, at least a part of the source finger electrode, and at least a part of the drain finger electrode;a shield plate electrode which is arranged via the insulating layer over the drain finger electrode and the first surface of the substrate between the gate finger electrode and the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode. 1. A semiconductor device comprising:a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate having conductivity;a second semiconductor layer of a second conductivity type formed on the first semiconductor layer;a third semiconductor layer of the first conductivity type formed on the second semiconductor layer;an opening part formed by removing part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer;a gate insulating film formed so as to cover an inner wall of the opening part;a gate electrode formed inside the opening part via the gate insulating film;a source electrode formed on a surface of the third semiconductor layer;a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; anda fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.2. The semiconductor device according to claim 1 , whereinthe fourth electrode is formed on a back side insulating ...

Methods of forming semiconductor structures including iii-v semiconductor material using substrates comprising molybdenum, and structures formed by such methods

Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material such as GaN over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride.

NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR WAFER

According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of AlGaN (0 Подробнее

METHODS FOR FORMING GROUP III-NITRIDE MATERIALS AND STRUCTURES FORMED BY SUCH METHODS

Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer. 1. A method of forming a Group III-nitride material on a growth substrate , comprising: depositing a Group III-nitride layer comprising a plurality of wurtzite crystal structures on an upper surface of the non-native growth substrate using a halide vapor phase epitaxy (HVPE) process; and', 'thermally treating the Group III-nitride layer; and, 'forming a Group III-nitride nucleation layer over a surface of a non-native growth substrate, comprisingforming a further Group III-nitride layer over the nucleation layer.2. The method of claim 1 , wherein depositing a Group III-nitride layer comprising a plurality of wurtzite crystal structures on an upper surface of the non-native growth substrate comprises depositing the Group III-nitride layer comprising a plurality of wurtzite crystal structures adjacent to the upper surface of the non-native growth substrate.3. The method of claim 1 , wherein thermally treating the Group III-nitride layer comprises exposing the Group III-nitride layer to a temperature of less than about 900° C. to reduce a concentration of a chlorine species within the Group III-nitride nucleation layer.4. The method of claim 1 , wherein thermally treating the Group III-nitride layer comprises introducing the Group III-nitride layer to at least one getter for chlorine species to reduce a ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a first semiconductor layer formed over a substrate; a second semiconductor layer formed over the first semiconductor layer; electrodes formed over the second semiconductor layer; and a third semiconductor layer formed on the second semiconductor layer; wherein the third semiconductor layer is formed so as to surround each element, in which the electrodes are formed, and wherein the third semiconductor layer is a semiconductor layer of a conductivity type whose polarity is opposite to that of carriers produced in the first semiconductor layer. 1. A semiconductor device comprising:a first semiconductor layer formed over a substrate;a second semiconductor layer formed over the first semiconductor layer;electrodes formed over the second semiconductor layer; anda third semiconductor layer formed on the second semiconductor layer;wherein the third semiconductor layer is formed so as to surround each element, in which the electrodes are formed, andwherein the third semiconductor layer is a semiconductor layer of a conductivity type whose polarity is opposite to that of carriers produced in the first semiconductor layer.2. The semiconductor device according to claim 1 ,wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are nitride semiconductors.3. The semiconductor device according to claim 1 ,wherein electrons are produced in the first semiconductor layer near an interface between the first semiconductor layer and the second semiconductor layer, andwherein the third semiconductor layer is p-type.4. The semiconductor device according to claim 1 ,wherein the electrodes are a gate electrode, a source electrode, and a drain electrode, and are formed over the second semiconductor layer in a region surrounded by the third semiconductor layer.5. The semiconductor device according to claim 4 ,wherein the semiconductor device is a high electron mobility transistor.6. The semiconductor device ...

Group III-V and Group IV Composite Switch

In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source and a gate situated on a bottom side of the lower active die. The group III-V and group IV composite switch also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a drain of the group IV transistor using a through-semiconductor via (TSV) of the upper active die. 1. A composite switch comprising:a group IV transistor in a lower active die, a source and a gate of said group IV transistor being situated on a bottom side of said lower active die;a group III-V transistor in an upper active die stacked over said lower active die, a drain, a source, and a gate of said group III-V transistor being situated on a top side of said upper active die;said source of said group III-V transistor being electrically coupled to a drain of said group IV transistor using a through-semiconductor via (TSV) of said upper active die.2. The composite switch of claim 1 , wherein said group IV transistor is a vertical group IV transistor.3. The composite switch of claim 1 , wherein said TSV does not reach a bottom side of said upper active die.4. The composite switch of claim 3 , wherein said TSV reaches a highly conductive substrate in said upper active die claim 3 , said highly conductive substrate being in electrical contact with said drain of said group IV transistor.5. The composite switch of claim 1 , wherein said TSV reaches a bottom side of said upper active die.6. The composite switch of claim 1 , wherein said group III-V transistor is a normally ON transistor and said composite switch is configured to be normally OFF.7. The composite switch of claim 1 , wherein said group III-V transistor is a high-voltage ( ...

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

There is provided a semiconductor device or the like which includes a channel and a gate electrode in an opening and in which electric field concentration near a bottom portion of the opening can be reduced. The semiconductor device includes n-type GaN drift layer /p-type GaN barrier layer /n-type GaN contact layer. An opening extends from the top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer located in the opening, the regrown layer including an electron supply layer and an electron drift layer a source electrode S, a drain electrode D, a gate electrode G located on the regrown layer, and a semiconductor impurity adjustment region disposed in the bottom portion of the opening. The impurity adjustment region is a region that promotes a potential drop from the drain electrode side to the gate electrode side in a potential distribution in an off-state. 1. A vertical semiconductor device including a GaN-based stacked layer having an opening ,the GaN-based stacked layer including n-type GaN-based drift layer/p-type GaN-based barrier layer/n-type GaN-based contact layer in that order to the top layer side, the opening extending from a top layer and reaching the n-type GaN-based drift layer, the semiconductor device comprising:a regrown layer located so as to cover a wall surface of the opening, the regrown layer including an electron drift layer and an electron supply layer;a source electrode that is in contact with the n-type GaN-based contact layer and the regrown layer;a drain electrode located so as to face the source electrode with the GaN-based stacked layer sandwiched therebetween;a gate electrode located on the regrown layer; anda semiconductor impurity adjustment region disposed in a bottom portion of the opening,wherein the impurity adjustment region is a region that promotes a potential drop from the drain electrode side to the gate electrode side in a potential distribution in an off-state.2. The ...

GALLIUM NITRIDE SUBSTRATE AND EPITAXIAL WAFER

A gallium nitride substrate includes a plurality of physical level differences in a surface thereof. All the physical level differences existing in the surface have a dimension of not more than 4 μm. A relationship of (H−L)/H×100≦80 is satisfied in all the physical level differences, where H represents a higher value of cathodoluminescence emission intensities of a wavelength corresponding to a bandgap of the gallium nitride substrate, and L represents a lower value of the cathodoluminescence emission intensities, the cathodoluminescence emission intensities being measured in an upper step and a lower step of the physical level difference. 1. A gallium nitride substrate , comprising:a plurality of physical level differences in a surface thereof,wherein all the physical level differences existing in the surface have a dimension of not more than 4 μm, andwherein a relationship of (H−L)/H×100≦80 is satisfied in all the physical level differences, where H represents a higher value of cathodoluminescence emission intensities of a wavelength corresponding to a bandgap of the gallium nitride substrate, and L represents a lower value of the cathodoluminescence emission intensities, the cathodoluminescence emission intensities being measured in an upper step and a lower step of the physical level difference.2. The gallium nitride substrate according to claim 1 , wherein all the physical level differences have a dimension of not more than 3 μm.3. The gallium nitride substrate according to claim 2 , wherein all the physical level differences have a dimension of not more than 2 μm.4. An epitaxial wafer claim 2 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the gallium nitride substrate according to ;'}a buffer layer on the gallium nitride substrate; andan InGaN quantum well structure including an InGaN quantum well layer on the buffer layer. The present application is based on Japanese patent application No. 2012-069353 filed on Mar. 26, 2012, the entire ...

NUCLEATION OF III-N ON REO TEMPLATES

A method of fabricating a layer of single crystal III-N material on a silicon substrate includes epitaxially growing a REO template on a silicon substrate. The template includes a REO layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate and selected to protect the substrate from nitridation. Either a rare earth oxynitride or a rare earth nitride is formed adjacent the upper surface of the template and a layer of single crystal III-N material is epitaxially grown thereon. 1. A method of fabricating a layer of single crystal III-N material on a silicon substrate comprising:providing a single crystal silicon substrate with a crystal lattice spacing;epitaxially growing a REO template on the silicon substrate, the template including a rare earth oxide layer adjacent the substrate with a crystal lattice spacing substantially matching the crystal lattice spacing of the substrate, and selecting the rare earth oxide layer to protect the substrate from nitridation;forming one of a rare earth oxynitride or a rare earth nitride adjacent the upper surface of the template; andepitaxially growing a layer of single crystal III-N material on the one of the rare earth oxynitride or the rare earth nitride.2. A method as claimed in wherein the rare earth oxide layer includes a rare earth oxide that is one of a material that is converted to a rare earth oxynitride when exposed to nitride or a material that is substantially impervious to nitride and remains REO.3. A method as claimed in wherein the material that is converted includes erbium oxide.4. A method as claimed in wherein the material that is substantially impervious to nitride includes gadolinium oxide.5. A method as claimed in wherein the step of forming one of the rare earth oxynitride or the rare earth nitride adjacent the upper surface of the template includes exposing the surface of the rare earth oxide layer to a nitrogen plasma.6. A method as ...

NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. 1. A nitride semiconductor device comprising:a substrate;semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer;a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; anda gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode,the gate electrode having a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al being sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.2. The device according to claim 1 , wherein the carrier running layer includes a GaN layer claim 1 , and{'sub': x', '1-x', 'Y', '1-Y', 'x', '1-x', 'Y', '1-Y', 'x', '1-x', 'Y', '1-Y, 'the barrier layer is any one of a non-doped or n-type AlGaN layer (0 Подробнее

NITRIDE SEMICONDUCTOR DEVICE

According to one embodiment, a nitride semiconductor device includes semiconductor stacked layers provided on a substrate and including a nitride semiconductor; a source electrode and a drain electrode provided on the layers and being in contact with the layers; and a gate electrode provided on the layers and provided between the source electrode and the drain electrode. The layers have a first barrier layer, a second barrier layer, and a carrier running layer interposed between the first barrier layer and the second barrier layer. The second barrier layer and the carrier running layer are removed in a region in which the source electrode on the layers is provided. A part of the source electrode is in contact with the first barrier layer. And another part of the source electrode other than the part of the source electrode is in contact with the second barrier layer. 1. A nitride semiconductor device comprising:a substrate;semiconductor stacked layers provided on the substrate and including a nitride semiconductor;a source electrode and a drain electrode provided on the semiconductor stacked layers and being in contact with the semiconductor stacked layers; anda gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode,the semiconductor stacked layers having a first barrier layer, a second barrier layer, and a carrier running layer interposed between the first barrier layer and the second barrier layer,the second barrier layer and the carrier running layer are removed in a region in which the source electrode on the semiconductor stacked layers being provided,a part of the source electrode being in contact with the first barrier layer, andanother part of the source electrode other than the part of the source electrode being in contact with the second barrier layer.2. The nitride semiconductor device according to claim 1 , wherein the source electrode is in ohmic contact with a two-dimensional hole ...

COMPOUND SEMICONDUCTOR AND METHOD OF MANUFACTURING THE SAME

An embodiment of a compound semiconductor device includes: a substrate; an electron transport layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed over the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole canceling layer formed between the electron supply layer and the p-type semiconductor layer, the hole canceling layer containing a donor or a recombination center and canceling a hole. 1. A compound semiconductor device , comprising:a substrate;an electron transport layer and an electron supply layer formed over the substrate;a gate electrode, a source electrode and a drain electrode formed over the electron supply layer;a p-type semiconductor layer formed between the electron supply layer and the gate electrode; anda hole canceling layer formed between the electron supply layer and the p-type semiconductor layer, the hole canceling layer containing a donor or a recombination center and canceling a hole.2. The compound semiconductor device according to claim 1 , wherein the p-type semiconductor layer is a GaN layer which contains Mg.3. The compound semiconductor device according to claim 1 , wherein the hole canceling layer contains a p-type impurity.4. The compound semiconductor device according to claim 3 , wherein the hole canceling layer contains Mg as the p-type impurity.5. The compound semiconductor device according to claim 1 , wherein the hole canceling layer contains Si as the donor.6. The compound semiconductor device according to claim 1 , wherein the hole canceling layer contains at least one selected from the group Fe claim 1 , Cr claim 1 , Co claim 1 , Ni claim 1 , Ti claim 1 , V claim 1 , and Sc as the recombination center.7. The compound semiconductor device according to claim 1 , further comprising a hole barrier layer formed between the electron supply layer and the p-type semiconductor layer ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes: a first semiconductor layer formed over a substrate; a second semiconductor layer formed over the first semiconductor layer; an insulating film including a first insulating film formed over the second semiconductor layer, a second insulating film, and a third insulating film stacked sequentially over the first insulating film, and an electrode formed over the insulating film, wherein, in the first insulating film, a region containing halogen ions is formed under a region provided with the electrode, and the third insulating film contains a halogen. 1. A semiconductor device comprising:a first semiconductor layer formed over a substrate;a second semiconductor layer formed over the first semiconductor layer;an insulating film including a first insulating film formed over the second semiconductor layer, a second insulating film, and a third insulating film stacked sequentially over the first insulating film, andan electrode formed over the insulating film,wherein, in the first insulating film, a region containing halogen ions is formed under a region provided with the electrode, andthe third insulating film contains a halogen.2. The semiconductor device according to claim 1 , further comprising:a recess is formed in the third insulating film in the region, in which the electrode is provided, by removing part of the third insulating film.3. The semiconductor device according to claim 1 , whereinthe halogen is chlorine or fluorine.4. The semiconductor device according to claim 1 , whereinthe insulating film contains any one of an oxide, a nitride, and an oxynitride.5. The semiconductor device according to claim 1 ,{'sub': 2', '3', '2', '2', '2', '5', '2, 'wherein, the insulating film contains at least one material of AlO, SiO, HfO, TaO, ZrO, MgO, SiN, AlN, SiON, and AlON.'}6. The semiconductor device according to claim 1 , whereinthe insulating film contains aluminum oxide.7. The semiconductor device according to claim 1 , whereinthe ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE

A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component. 1. A semiconductor device comprising:a first semiconductor layer formed on a substrate;a second semiconductor layer formed on the first semiconductor layer;a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer;an opening formed in the second semiconductor layer;an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer;a gate electrode formed in the opening via the insulating film; anda protective film formed on the insulating film and including an amorphous film containing carbon as a major component.2. A semiconductor device comprising:a first semiconductor layer formed on a substrate;a second semiconductor layer formed on the first semiconductor layer;a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer;an insulating film formed above the second semiconductor layer;a gate electrode formed on the insulator; anda protective film formed on the insulating film and including an amorphous film containing carbon as a major component.3. The semiconductor device as claimed in claim 1 ,wherein the protective film includes the amorphous film and an insulating protective film,wherein the amorphous film is ...

SEMICONDUCTOR DEVICE, POWER-SUPPLY UNIT, AMPLIFIER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode. 16.-. (canceled)7. A semiconductor device , comprising:a semiconductor layer formed above a substrate;an electrode formed above the semiconductor layer; anda protective film formed above the semiconductor layer, whereinthe protective film has a membrane stress at a side near the semiconductor layer lower than a membrane stress at a side away from the semiconductor layer.8. The semiconductor device as claimed in claim 7 , whereinthe protective film includes a first protective film and a second protective film laminated on the first protective film, andthe first protective film has a membrane stress lower than a membrane stress of the second protective film.9. The semiconductor device as claimed in claim 7 , whereinthe protective film is formed by an amorphous film, wherein carbon is a chief ingredient of the amorphous film.10. The semiconductor device as claimed in claim 7 , whereinthe protective film is formed by an amorphous film, wherein carbon is a chief ingredient of the amorphous film, anda concentration of any one of nitrogen, oxygen, hydrogen and fluorine included in the protective film is higher at a side near the semiconductor layer than that at a side away from the semiconductor layer.11. The semiconductor device as claimed in claim 8 , whereinthe protective film is formed by an amorphous film, wherein carbon is a chief ingredient of the amorphous film, anda concentration of any one of nitrogen, oxygen, hydrogen and fluorine included in the first protective film is higher than the concentration included in the second protective film.12. The semiconductor device as claimed in claim 10 , whereina film density in the second protective film is ...

III-Nitride Heterojunction Device

A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof. 121-. (canceled)22. A III-nitride device comprising:a III-nitride heterojunction that includes a first III-nitride semiconductor body having one band gap, and a second III-nitride semiconductor body having another band gap disposed on said first III-nitride semiconductor body to generate a two dimensional electron gas;a first power electrode disposed over said III-nitride heterojunction and electrically coupled to said two dimensional electron gas;a second power electrode disposed over said III-nitride heterojunction and electrically coupled to said two dimensional electron gas;a gate arrangement disposed between said first power electrode and said second power electrode;spaced interrupted regions in said two-dimensional electron gas below said gate arrangement, wherein at least one of said spaced interrupted regions extends only partially under said gate arrangement.23. The III-nitride device of claim 22 , wherein said first and second power electrodes are ohmically coupled to said second III-nitride semiconductor body.24. The III-nitride device of claim 22 , wherein said gate arrangement includes an electrode that is schottky coupled to said second III-nitride semiconductor body.25. The III-nitride device of claim 22 , wherein said gate arrangement includes a gate electrode and a gate insulation body interposed between said gate electrode and said III-nitride heterojunction.26. The III-nitride device of claim 22 , wherein said first power electrode claim 22 , said second power electrode claim 22 , and said gate arrangement are parallel elongated bodies.27. The III-nitride device of claim 22 , wherein said spaced interrupted regions are disposed along said gate arrangement.28. The III-nitride device of claim 22 , wherein said interrupted regions are disposed below respective recesses in said second ...

Prepared and Stored GaN Substrate

A GaN substrate is stored within an atmosphere in which the oxygen concentration is not greater than 15 vol. % and the water-vapor concentration is not greater than 20 g/m. The GaN substrate () has a planar first principal face (), and in an arbitrary point (P) along the first principal face () and separated 3 mm or more from the outer edge thereof, the GaN substrate's plane orientation has an off-inclination angle Δα of −10° or more, 10° or less with respect to the plane orientation of an arbitrarily designated crystalline plane (1) that is inclined 50° or more, 90° or less with respect to a plane (1), being either the (0001) plane or the (000 ) plane, through the arbitrary point. This enables storing GaN substrates whose principal-face plane orientation is other than (0001) or (000 ), making available GaN substrates with which semiconductor devices of favorable properties can be manufactured. 1. A GaN substrate stored within an atmosphere in which the oxygen concentration is not greater than 15 vol. % and the water-vapor concentration is not greater than 20 g/m , the GaN substrate having opposite sides encompassed by a peripheral edge , one of said opposite sides being a planar first principal face and the other of said opposite sides being a second principal face , said first principal face having an average roughness Ra of not greater than 20 nm and being of plane orientation having , in an arbitrary point along the first principal face and separated at least 3 mm from said peripheral edge , an off-inclination angle of between −10° and 10° , inclusive , with respect to an arbitrarily designated crystalline plane , through said arbitrary point , of plane orientation inclined between 50° and 90° , inclusive , with respect to either the (0001) plane or the (000 ) plane , and said second principal face having an average roughness Ra of not greater than 20 μm.2. The GaN substrate set forth in claim 1 , wherein the average roughness Ra of said first principal face is ...

GROUP-III-NITRIDE BASED LAYER STRUCTURE AND SEMICONDUCTOR DEVICE

A group-III-nitride based layer sequence fabricated by means of an epitaxial process on a silicon substrate, the layer sequence comprising at least one doped first group-III-nitride layer () having a dopant concentration larger than 1×10cm, a second group-III-nitride layer () having a thickness of at least 50 nm and an n-type or p-type dopant concentration of less than 5×10cm, and an active region made of a group-III-nitride semiconductor material, wherein the first group-III-nitride layer comprises at least one n-type dopant selected from the group of elements formed by germanium, tin, lead, oxygen, sulphur, selenium and tellurium or a at least one p-type dopant, and wherein the active region has a volume density of either screw-type or edge type dislocations below 5×10mm. 1. A group-III-nitride based layer sequence fabricated by means of an epitaxial process on a silicon substrate , the layer sequence comprising:{'b': '105', 'sup': 18', '−3, 'at least one doped first group-III-nitride layer () having a dopant concentration larger than 1×10cm;'}{'b': '106', 'sup': 18', '−3, 'a second group-III-nitride layer () having a thickness of at least 50 nm and an n-type or p-type dopant concentration of less than 5×10cm; and'}{'b': '106', 'an active region () made of a group-III-nitride semiconductor material;'}wherein the first group-III-nitride layer comprises at least one n-type dopant selected from the group of elements formed by germanium, tin, lead, oxygen, sulphur, selenium and tellurium or a at least one p-type dopant; and wherein{'sup': 9', '−3, 'the active region has a volume density of either screw-type or edge type dislocations below 5×10cm.'}2. The layer sequence of claim 1 , wherein the second group-III-nitride layer is low-doped with an n-type or p-type dopant concentration of less than 5×10cm.3. The layer sequence of claim 2 , wherein the second group-III-nitride layer has a thickness of at least 500 nm.4. The layer sequence of claim 3 , wherein the second ...

COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A compound semiconductor device includes a substrate; a buffer layer formed on the substrate; an electron transit layer and an electron donating layer formed on the buffer layer; a gate electrode, a source electrode, and a drain electrode formed on the electron donating layer; and an embedded electrode to which a potential independent of the gate electrode, the source electrode, and the drain electrode is supplied to control a potential of the buffer layer. 1. A compound semiconductor device comprising:a substrate;a buffer layer formed on the substrate;an electron transit layer and an electron donating layer formed on the buffer layer;a gate electrode, a source electrode, and a drain electrode formed on the electron donating layer; andan embedded electrode to which a potential independent of the gate electrode, the source electrode, and the drain electrode is supplied to control a potential of the buffer layer.2. The compound semiconductor device according to claim 1 , further comprising:an insulating film that suppresses atomic diffusion from the embedded electrode.3. The compound semiconductor device according to claim 2 ,wherein the insulating film covers an entire surface of the embedded electrode.4. The compound semiconductor device according to claim 2 ,wherein the insulating film is formed entirely below a region where a two-dimensional electron gas is produced in the electron transit layer.5. The compound semiconductor device according to claim 1 ,wherein the embedded electrode is disposed between an upper surface and a lower surface of the buffer layer.6. The compound semiconductor device according to claim 1 ,wherein the embedded electrode is disposed between an upper surface and a lower surface of the electron transit layer.7. The compound semiconductor device according to claim 1 ,wherein the embedded electrode includes a conductive compound semiconductor layer.8. The compound semiconductor device according to claim 1 ,wherein the embedded electrode ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device, in which the generation of interface states in the interface region between a nitride semiconductor layer and an aluminum oxide layer is suppressed, includes a first nitride semiconductor layer and an aluminum oxide layer. The first nitride semiconductor layer includes Ga. The aluminum oxide layer directly contacts the upper surface of the first nitride semiconductor layer, and includes H (hydrogen) atoms at least within a defined region from the interface with the first nitride semiconductor layer. In addition, the peak value of an H atom concentration in the above region is in a range of 1×10cmto 5×10cm. 1. A semiconductor device comprising:a first nitride semiconductor layer including Ga; andan aluminum oxide layer that directly contacts the upper surface of the first nitride semiconductor layer, the aluminum oxide layer including H atoms at least within a defined region from the interface with the first nitride semiconductor layer,{'sup': 20', '−3', '21', '−3, 'wherein the peak value of an H atom concentration in the above region is in a range of 1×10cmto 5×10cm.'}2. The semiconductor device according to claim 1 , wherein the first nitride semiconductor layer is a GaN layer claim 1 , an AlGaN layer claim 1 , or an AlInGaN layer.3. The semiconductor device according to claim 1 , wherein the aluminum oxide layer comprises:an interface layer that directly contacts the first nitride semiconductor layer, and has the peak value of the H atom concentration; anda main body layer with which the interface layer is overlaid, and in which an H atom concentration is lower than that in the interface layer.4. The semiconductor device according to claim 3 , wherein the peak value of the H atom concentration in the interface layer is larger than double the peak value of the H atom concentration in the main body layer.5. The semiconductor device according to claim 1 , wherein the aluminum oxide layer includes amorphous states.6. The semiconductor device ...

N-POLAR III-NITRIDE TRANSISTORS

An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer. 1. An N-polar III-N transistor , comprising:a III-N buffer layer having a first lattice constant;a first III-N barrier layer having a second lattice constant on the III-N buffer layer;a III-N channel layer on the III-N buffer layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region, wherein a compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the plurality of access regions of the III-N channel layer;a source, a gate, and a drain; anda second III-N barrier layer between the gate and the III-N channel layer, the second III-N barrier layer having an N-face proximal to the gate and a group-III face opposite the N-face, the second III-N barrier layer having a larger bandgap than the III-N channel layer; whereinthe second lattice constant is within 0.5% of the first lattice constant.2. The transistor of claim 1 , wherein a thickness and aluminum fractional composition of a portion of the second III-N barrier over the gate region of the III-N channel layer are selected to cause the channel to be induced in ...

Lateral High Electron Mobility Transistor With Schottky Junction

A lateral HEMT includes a first semiconductor layer on a second semiconductor layer, a heterojunction at an interface between the first semiconductor layer and the second semiconductor layer, and a rectifying Schottky junction. The rectifying Schottky junction has a first terminal electrically coupled to a source electrode and a second terminal electrically coupled to the second semiconductor layer. 1. A lateral HEMT , comprising:a first semiconductor layer on a second semiconductor layer;a heterojunction at an interface between the first semiconductor layer and the second semiconductor layer; anda rectifying Schottky junction having a first terminal electrically coupled to a source electrode and a second terminal electrically coupled to the second semiconductor layer.2. The lateral HEMT of claim 1 , wherein the second semiconductor layer is at least part of the second terminal.3. The lateral HEMT of claim 1 , wherein the second terminal includes the second semiconductor layer and the first terminal includes a Schottky contact metal of at least one of Ni claim 1 , Pt claim 1 , W claim 1 , Mo claim 1 , TiSi claim 1 , WSi claim 1 , and CoSion the second semiconductor layer.4. The lateral HEMT of claim 1 , wherein a gate electrode of the lateral HEMT and a Schottky contact metal of the Schottky junction are separate parts of the same patterned metal layer.5. The lateral HEMT of claim 1 , wherein the rectifying Schottky junction includes at least one of p-type GaN and doped polysilicon.6. The lateral HEMT of claim 1 , wherein a shortest lateral distance between a gate electrode of the lateral HEMT and a drain electrode of the lateral HEMT is larger than the shortest lateral distance between the rectifying Schottky junction and the drain electrode.7. The lateral HEMT of claim 1 , wherein the first semiconductor layer comprises AlGaN and the second semiconductor layer comprises GaN.8. The lateral HEMT of claim 1 , wherein the first semiconductor layer comprises GaN and ...

HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS

Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed. 1. A method of integrating a Group III nitride material and silicon , said method comprising:providing a structure comprising, from bottom to top, a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer;forming an opening through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and partially within the (100) silicon layer, wherein a surface of the (100) silicon layer beneath the uppermost surface of the (100) silicon layer is exposed;forming a conformal dielectric material liner atop remaining portions of the blanket layer of dielectric material and within said opening;removing horizontal portions of the conformal dielectric material liner to provide template dielectric spacers partially covering said exposed surface of the (100) silicon layer;forming an epitaxial semiconductor material on a ...

As/Sb Compound Semiconductors Grown on Si or Ge Substrate

An As(arsenic)/Sb(antimony) compound semiconductor is grown on a Si(silicon) or Ge (germanium) substrate. With the present invention, island-like growth on the Si or Ge substrate owing to lattice constant mismatch is prevented. Bad electrical isolation owing to diffusion of Ge is also prohibited. The present invention could obtain a high quality metamorphic buffer which is suitable for integrating a Si or Ge substrate with an electronic or optoelectronic device of a III/V group semiconductor. 1. An As/Sb compound semiconductor grown on a Si substrate , comprisinga substrate;a nucleation layer, said nucleation layer being deposited on said substrate, said nucleation layer being a GaAs layer, said nucleation layer having a thickness smaller than 100 nanometer (nm); and at least one graded layer, said at least one graded layer being deposited on said nucleation layer, said graded layer being a GaAsSb graded layer, said at least one graded layer having a thickness between 5 nm and 2000 nm.2. The semiconductor according to claim 1 , wherein said nucleation layer is made of a material selected from a group consisting of AlGaAs claim 1 , AlGaP claim 1 , AlGaPAsand AlGaPSb; 0≦x≦1; 0 Подробнее

PVD BUFFER LAYERS FOR LED FABRICATION

Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma. 1. A method of fabricating a buffer layer above a substrate , the method comprising:pre-treating a surface of a substrate; and, subsequently,reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.2. The method of claim 1 , wherein the pre-treating is performed in the PVD chamber.3. The method of claim 2 , wherein the pre-treating comprises loading the substrate onto a pedestal of the PVD chamber and applying a bias to the pedestal to generate a plasma near the surface of the substrate.4. The method of claim 3 , wherein the plasma comprises a radical selected from the group consisting of a nitrogen radical claim 3 , and argon radical and a hydrogen radical.5. The method of claim 3 , wherein generating the plasma near the surface of the substrate comprises removing surface contamination or particles from the surface of the substrate and modifying the structure of the surface of the substrate.6. The method of claim 3 , wherein applying the bias to the pedestal comprises applying a bias approximately in the range of −5V to −1000V for a duration approximately in the range of 1 second to 15 minutes.7. The method of claim 3 , wherein the pre-treatment is performed while ...

GALLIUM NITRIDE SEMICONDUCTOR SUBSTRATE WITH SEMICONDUCTOR FILM FORMED THEREIN

A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a mirror polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface. 128-. (canceled)29. An epitaxial substrate comprising:a gallium nitride substrate of single crystal gallium nitride including a primary surface, the primary surface having a first area and a second area, an off-angle formed by a c-axis of the gallium nitride substrate with an axis perpendicular to the primary surface being greater than zero over the first and second areas, and a c-face of the single crystal gallium nitride of the gallium nitride substrate being concave or convex, a curvature radius R of a C-plane of the single crystal gallium nitride of the gallium nitride substrate being equal to or more than 1.5 meters; anda III nitride semiconductor film formed on the gallium nitride substrate, the III nitride semiconductor film including a primary surface, the primary surface of the III nitride semiconductor film including a surface morphology, and the surface morphology including no six-sided pyramid pattern. This application is a Continuation of U.S. application Ser. No. 13/434,437, filed on Mar. 29, 2012, which is a Continuation of U.S. application Ser. No. 12/980,923, filed on Dec. 29, 2010, now U.S. Pat. No. 8,168,516, which is a ...

WAFER LEVEL PACKAGED GAN POWER SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF

Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded. By this configuration, it is possible to reduce the process costs by forming the bump on the substrate based on the wafer level, rapidly emit the heat generated from an AlGaN HEMT device by forming the sub source contact pad and the sub drain contact pad of the substrate in the active region, and efficiently emit the heat generated from the AlGaN HEMT device by forming a via hole on the substrate and filling the via hole with the conductive metal. 1. A Power semiconductor device , comprising:a gallium nitride compound element formed by being grown on a wafer;a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element;a module substrate to which the nitride gallium compound element is flip-chip bonded;a bonding pad formed on the module substrate; anda bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded.2. The Power semiconductor device of claim 1 , wherein the bonding pad is disposed so as to have a vertical symmetrical structure or a horizontal symmetrical structure to the contact pad.3. The Power semiconductor device of claim 1 , wherein the source is further formed with a sub source contact pad and the drain is further formed with a sub drain contact pad.4. The Power semiconductor device of claim 3 , wherein the module substrate further includes a sub ...

Enhancement Mode III-Nitride Transistors with Single Gate Dielectric Structure

According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge. 120-. (canceled)21. A III-nitride transistor comprising:a conduction channel formed between first and second III-nitride bodies, said conduction channel including a two-dimensional electron gas;at least one silicon nitride layer having a charge confined within to cause an interrupted region in said conduction channel.22. The III-nitride transistor of wherein at least one gate electrode is operable to restore said interrupted region of said conduction channel.23. The III-nitride transistor of wherein said transistor is an enhancement mode transistor.24. The III-nitride transistor of wherein said at least one silicon nitride layer is ion implanted with said charge.25. The III-nitride transistor of wherein said at least one silicon nitride layer is grown with said charge.26. The III-nitride transistor of wherein said first III-nitride body comprises AlGaN.27. The III-nitride transistor of wherein said second III-nitride body comprises GaN.28. The III-nitride transistor of wherein said at least one silicon nitride layer is on said first III-nitride body.29. The III-nitride transistor of wherein said at least one silicon nitride layer is under said at least one gate electrode ...

NITRIDE SEMICONDUCTOR DEVICE

The present invention prevents breakage of a gate insulating film of a MOS device and provides a nitride semiconductor device having improved reliability. An SBD metal electrode provided between a drain electrode and a gate electrode is configured to form a Schottky junction with an AlGaN layer. Further, the SBD metal electrode and a source electrode are connected and electrically short-circuited. Consequently, when an off signal is inputted to the gate electrode, a MOSFET part is turned off and the drain-side voltage of the MOSFET part becomes close to the drain electrode voltage. When the drain electrode voltage increases, the SBD metal electrode voltage becomes lower than the drain-side voltage of the MOSFET part, thus the drain side of the MOSFET part and the drain electrode are electrically disconnected by the SBD metal electrode. 114-. (canceled)15. A nitride semiconductor device comprising:a substrate;a buffer layer that is formed on the substrate;an electron traveling layer that is formed on the buffer layer and is formed of a nitride compound;an electron supplying layer that is formed on the electron traveling layer, and whose band gap energy is different than the electron traveling layer, and that is formed from at least one layer;a recess portion that is formed in a region from a surface of the electron supplying layer at least to the electron supplying layer;a source electrode and a drain electrode that are formed on the electron supplying layer at positions opposing one another across the recess portion;a gate insulating film that is formed from the recess portion over a surface of the electron supplying layer, so as to cover the recess portion interior;a gate electrode that is formed on the gate insulating film that is within the recess portion; andan electrode for carrier transport that is formed between the gate electrode and the drain electrode, and is connected to the source electrode, and is for transporting carrier to the source electrode.16. The ...

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MODULE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Disclosed is a semiconductor device including first and second semiconductor elements, first and second external connection terminals and a sealing member. The first external connection terminal is provided at a first surface of the first semiconductor element. The second semiconductor element is provided at a second surface side, that is at a side opposite to the first surface, of the first semiconductor element. The second external connection terminal is connected to the second semiconductor element, and the second external connection terminal is configured to be, together with the first external connection terminal, connected to a wiring board. The sealing member seals the first and second semiconductor elements and exposes a portion, that is configured to be connected to the wiring board, of the first external connection terminal and a portion, that is configured to be connected to the wiring board, of the second external connection terminal. 1. A semiconductor device comprising:a first semiconductor element at which a first external connection terminal is provided at a first surface;a second semiconductor element provided at a second surface side, that is at a side opposite to the first surface, of the first semiconductor element;a second external connection terminal that is connected to the second semiconductor element, and is configured to be, together with the first external connection terminal, connected to a wiring board; anda sealing member that seals the first semiconductor element and the second semiconductor element, and that exposes a portion, that is configured to be connected to the wiring board, of the first external connection terminal and a portion, that is configured to be connected to the wiring board, of the second external connection terminal.2. The semiconductor device of claim 1 , wherein the first semiconductor element has a first electrode claim 1 , a second electrode claim 1 , and a control electrode that controls current flowing between ...

GROUP 13 NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF ITS MANUFACTURE

Disclosed is a semiconductor device comprising a substrate (); at least one semiconducting layer () comprising a nitride of a group 13 element on said substrate; and an ohmic contact () on the at least one semiconducting layer, said ohmic contact comprising a silicon-comprising portion () on the at least one semiconducting layer and a metal portion () adjacent to and extending over said silicon-comprising portion, the metal portion comprising titanium and a further metal. A method of manufacturing such a semiconductor device is also disclosed. 1. A semiconductor device comprising:a substrate;at least one semiconducting layer comprising a nitride of a group 13 element on said substrate; andan ohmic contact on the at least one semiconducting layer, said ohmic contact comprising a silicon-comprising portion on the at least one semiconducting layer and a metal portion adjacent to and extending over said silicon-comprising portion, the metal portion comprising titanium and a further metal, wherein the ohmic contact does not contain gold.2. The semiconductor device of claim 1 , wherein the silicon source of the silicon-comprising portion is selected from silicon claim 1 , silicon oxide and silicon nitride.3. The semiconductor device of claim 1 , wherein the metal portion comprises:a titanium layer on the at least one semiconducting layer and extending over the silicon-comprising portion; anda layer of the further metal over the titanium layer; and/oran alloy layer of said titanium and the further metal.4. The semiconductor device of any of claim 1 , wherein the semiconductor device comprises a first silicon-comprising portion and a second silicon-comprising portion laterally separated from the first silicon-comprising portion claim 1 , and wherein a part of the metal portion extends between the first silicon-comprising portion and the second silicon-comprising portion.5. (canceled)6. The semiconductor device of claim 4 , wherein the first silicon-comprising portion and ...

COMPOUND SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME

A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed. 1. (canceled)2. (canceled)3. (canceled)4. A compound semiconductor substrate comprising a first substrate and a second substrate made of single crystal gallium nitride , whereinin each of the first substrate and the second substrate, one surface is a (0001) Ga-face and an opposite surface is a (000-1) N-face, andthe first substrate and the second substrate are bonded to each other in a state where the (000-1) N-face of the first substrate and the (000-1) N-face of the second substrate face each other, and the (0001) Ga-face of the first substrate and the (0001) Ga-face of the second substrate are exposed.5. The compound semiconductor substrate according to claim 4 , wherein the first substrate and the second substrate are directly bonded to each other.6. The compound semiconductor substrate according to claim 4 , further comprising a conductive adhesive agent claim 4 , whereinthe first substrate and the second substrate are bonded to each other through the conductive adhesive agent.7. A manufacturing method of a compound semiconductor substrate claim 4 , comprising:preparing a first substrate and a second substrate made of single crystal silicon carbide, in each of the first substrate and the second substrate, one surface being a (000-1) C-face and an opposite surface being a (0001) Si-face;bonding the first substrate and the second substrate in a state where the (0001) Si-face of the first substrate and the (0001) Si- ...

NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER

According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type. 120-. (canceled)21: A nitride semiconductor device comprising:a foundation layer formed on an Al-containing nitride semiconductor layer, the foundation layer having a thickness not less than 1 micrometer and including GaN; anda functional layer provided on the foundation layer, the functional layer including a first semiconductor layer, the first semiconductor layer having an impurity concentration higher than an impurity concentration in the foundation layer and including GaN of a first conductivity type.22: The device according to claim 21 , wherein a thickness of the first semiconductor layer is not less than 1 micrometer.23: The device according to claim 22 , wherein the thickness of the first semiconductor layer is not more than 4 micrometers.24: The device according to claim 21 , wherein the impurity concentration in the foundation layer is not more than 1×10cm.25: The device according to claim 21 , wherein the thickness of the foundation layer is thinner than a thickness of the first semiconductor layer.26: The device according to claim 25 , wherein a thickness of the first semiconductor layer is not less than 1 micrometer.27: The device according to claim 21 , wherein the functional layer further includes:a light emitting part provided on the first semiconductor layer and including a plurality of barrier layers and a well layer provided between the barrier layers; anda second ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a semiconductor device that includes a substrate, a first buffer region formed over the substrate, a second buffer region formed on the first buffer region, an active layer formed on the second buffer region, and at least two electrodes formed on the active layer. The first buffer region includes at least one composite layer in which a first semiconductor layer and a second semiconductor layer are sequentially stacked. The second buffer region in includes at least one composite layer in which a third semiconductor layer, a fourth semiconductor layer, and a fifth semiconductor layer are sequentially stacked. The fourth lattice constant has a value between the third lattice constant and the fifth lattice constant. 1. A semiconductor device comprising:a substrate;a first buffer region formed over the substrate;a second buffer region formed on the first buffer region;an active layer formed on the second buffer region; andat least two electrodes formed on the active layer; whereinthe first buffer region includes at least one composite layer in which a first semiconductor layer having a first lattice constant and a second semiconductor layer having a second lattice constant that is different from the first lattice constant are sequentially stacked,the second buffer region includes at least one composite layer in which a third semiconductor layer having a third lattice constant that is substantially same as the first lattice constant, a fourth semiconductor layer having a fourth lattice constant, and a fifth semiconductor layer having a fifth lattice constant that is substantially same as the second lattice constant are sequentially stacked, andthe fourth lattice constant has a value between the third lattice constant and the fifth lattice constant.2. The semiconductor device according to claim 1 , whereincoefficients of thermal expansion of the first, second, third, fourth and fifth semiconductor layers are larger than a coefficient of thermal expansion of the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes. 1a substrate;a nitride based compound semiconductor layer arranged on the substrate;{'sub': x', '1-x, 'an active region arranged on the nitride based compound semiconductor layer and having an aluminum gallium nitride layer (AlGaN) (0.1≦x≦1);'}a gate electrode arranged on the active region;a source electrode arranged on the active region;a drain electrode arranged on the active region;a gate terminal electrode arranged on the nitride based compound semiconductor layer in an extension direction of the gate electrode, and being connected to the gate electrode;a source terminal electrode arranged on the nitride based compound semiconductor layer in an extension direction of the source electrode, and being connected to the source electrode;a drain terminal electrode arranged on the nitride based compound semiconductor layer in an extension direction of the drain electrode, and being connected to the drain electrode;an end face electrode arranged on an end face of the substrate in a source ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device. 16.-. (canceled)7. A method for producing a semiconductor device comprising:a step of preparing a GaN substrate having a GaN layer that is in ohmic contact with a supporting substrate;a step of forming an epitaxial layered body of first conductivity type GaN-based drift layer/second conductivity type GaN-based layer/first conductivity type GaN-based cap layer on the GaN substrate;a step of etching the epitaxial layered body on the GaN substrate in a first region to form a FET opening that reaches the first conductivity type GaN-based drift layer;a step of forming a channel-forming layer on an inside surface of the opening; anda step of etching the channel-forming layer and the epitaxial layered body in a second region by masking the first region with a resist film to form an SBD opening that reaches the first conductivity type GaN-based drift layer,wherein an electrode is formed so as to be in Schottky contact with the first conductivity type GaN-based drift layer in the SBD opening and contact the second conductivity type GaN-based layer in the opening.8. (canceled)91. The semiconductor device according to claim , wherein the electrode that is in Schottky contact is located so as to fill the opening in the first conductivity type drift layer and the second conductivity type layer and extend onto the second conductivity type layer in the periphery of the opening.10. The method for producing the semiconductor device according to claim 7 , in the step of forming the SBD opening and the step of forming the electrode claim 7 , a bigger opening than the opening formed in the first conductivity type GaN-based drift layer is formed in the second ...

COMPOUND SEMICONDUCTOR DEVICE

The compound semiconductor device comprises an i-GaN buffer layer formed on an SiC substrate ; an n-AlGaN electron supplying layer formed on the i-GaN buffer layer ; an n-GaN cap layer formed on the n-AlGaN electron supplying layer ; a source electrode and a drain electrode formed on the n-GaN cap layer ; a gate electrode formed on the n-GaN cap layer between the source electrode and the drain electrode ; a first protection layer formed on the n-GaN cap layer between the source electrode and the drain electrode ; and a second protection layer buried in an opening formed in the first protection layer between the gate electrode and the drain electrode down to the n-GaN cap layer and formed of an insulation film different from the first protection layer. 16-. (canceled)7. A compound semiconductor device comprising:a GaN active layer formed over a semiconductor substrate;an AlGaN carrier supplying layer formed over the GaN active layer;a GaN cap layer formed over the AlGaN carrier supplying layer;a source electrode and a drain electrode formed over the AlGaN carrier supplying layer;a first protection layer formed over the GaN cap layer between the source electrode and the drain electrode and having an opening reaching the GaN cap layer between the source electrode and the drain electrode, the opening exposing a surface of the GaN cap layer, a width of the opening being gradually increased from the surface of the GaN cap layer toward a surface of the first protection layer; anda gate electrode formed in the opening.8. The compound semiconductor device according to claim 7 , whereinthe gate electrode is formed, extended on the first protection layer.9. The compound semiconductor device according to claim 7 , whereinatomic layer steps are formed on the upper surface of the GaN cap layer.10. The compound semiconductor device according to claim 7 , whereinthe first protection layer is formed of SiN.11. The compound semiconductor device according to claim 7 , whereinthe first ...

METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR ELEMENT

A method for manufacturing a heterojunction field effect transistor comprises the steps of: epitaxially growing a drift layer on a support substrate ; epitaxially growing a current blocking layer which is a p-type semiconductor layer on the drift layer at a temperature equal to or higher than 1000° C. by using hydrogen gas as a carrier gas; and epitaxially growing a contact layer on the current blocking layer by using at least one gas selected from the group consisting of nitrogen gas, argon gas, helium gas, and neon gas as a carrier gas. 1. A method for manufacturing a nitride semiconductor device , comprising the steps of:epitaxially growing a first gallium nitride based semiconductor layer on a free-standing Group III nitride substrate;epitaxially growing a second gallium nitride based semiconductor layer which is a p-type semiconductor layer on the first gallium nitride based semiconductor layer at a temperature equal to or higher than 1000° C. by using hydrogen gas as a carrier gas; andepitaxially growing a third gallium nitride based semiconductor layer on the second gallium nitride based semiconductor layer by using at least one gas selected from the group consisting of nitrogen gas, argon gas, helium gas, and neon gas as a carrier gas.2. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein the third gallium nitride based semiconductor layer is an n-type semiconductor layer.3. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein the first gallium nitride based semiconductor layer is an n-type semiconductor layer.4. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein the second gallium nitride based semiconductor layer includes at least one element selected from the group consisting of magnesium and zinc as a dopant.5. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein a ratio of a hydrogen concentration to ...

Ohmic Contact to Semiconductor Layer

A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions. 1. A method comprising: forming a plurality of cavities in the semiconductor structure, wherein the plurality of cavities are separated from each other by a characteristic length scale, and wherein the characteristic length scale is selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer;', 'depositing the metal into the plurality of cavities and over an area of the semiconductor structure including the plurality of cavities; and', 'annealing the semiconductor structure and the metal using a set of conditions configured to ensure formation of a set of metal protrusions laterally penetrating the semiconductor layer from at least one of the plurality of cavities, wherein the set of metal protrusions are conducive to at least one of: field emission or field-enhanced thermionic emission., 'fabricating a perforating ohmic contact to a semiconductor layer in a semiconductor structure, the fabricating including2. The method of claim 1 , wherein a metal protrusion in the set of metal protrusions has one of: a pyramidal claim 1 , a prismatic claim 1 , or a conic shape.3. The method of claim 1 , wherein the set of metal protrusions have a characteristic lateral size claim 1 , wherein the characteristic ...

Method Of Manufacturing Gallium Nitride Substrate And Gallium Nitride Substrate Manufactured Thereby

A method of manufacturing a gallium nitride (GaN) substrate and a GaN substrate manufactured thereby. The method includes the steps of growing an aluminum nitride nucleation layer on a base substrate, growing a first gallium nitride film on the base substrate on which the aluminum nitride nucleation layer has been grown, the first gallium nitride film having a first content ratio of nitrogen to gallium, and growing a second gallium nitride film on the first gallium nitride film, the second gallium nitride film having a second content ratio of nitrogen to gallium which is lower than the first content ratio. Self-separation between the base substrate and the GaN substrate is possible during the growth process, thereby precluding mechanical separation, increasing a self-separation area, and minimizing the occurrence of warping. 1. A method of manufacturing a gallium nitride substrate , comprising:growing an aluminum nitride nucleation layer on a base substrate;growing a first gallium nitride film on the base substrate on which the aluminum nitride nucleation layer has been grown, the first gallium nitride film having a first content ratio of nitrogen to gallium; andgrowing a second gallium nitride film on the first gallium nitride film, the second gallium nitride film having a second content ratio of nitrogen to gallium which is lower than the first content ratio.2. The method of claim 1 , wherein the first content ratio ranges from 4:1 to 40:1 claim 1 , and the second content ratio ranges from 1:1 to 2:1.3. The method of claim 1 , wherein growing the second gallium nitride film comprises growing the second gallium nitride film at a slower growth rate than the first gallium nitride film.4. The method of claim 1 , wherein growing the second gallium nitride film comprises growing the second gallium nitride film at a higher temperature than the first gallium nitride film.5. The method of claim 3 , wherein growing the second gallium nitride film comprises growing the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided are a nitride-based semiconductor element with reduced leak current, and a manufacturing method thereof. The semiconductor element comprises a substrate; a buffer region that is formed above the substrate; an active layer that is formed on the buffer region; and at least two electrodes that are formed on the active layer. The buffer region includes a plurality of semiconductor layers having different lattice constants, and there is a substantially constant electrostatic capacitance between a bottom surface of the substrate and a top surface of the buffer region when a potential that is less than a potential of the bottom surface of the substrate is applied to the top surface of the buffer region and a voltage between the bottom surface of the substrate and the top surface of the buffer region is changed within a range corresponding to thickness of the buffer region. 1. A semiconductor element comprising:a substrate;a buffer region that is formed over the substrate;an active layer that is formed on the buffer region; andat least two electrodes that are formed on the active layer, whereinthe buffer region includes a plurality of semiconductor layers having different lattice constants, andthere is a substantially constant electrostatic capacitance between a bottom surface of the substrate and a top surface of the buffer region when an electric potential that is less than an electric potential of the bottom surface of the substrate is applied to the top surface of the buffer region and a voltage between the bottom surface of the substrate and the top surface of the buffer region is changed within a range corresponding to thickness of the buffer region.2. The semiconductor element according to claim 1 , whereinthe buffer region includes at least one composite layer, which is formed by layering a first semiconductor layer having a first lattice constant, a second semiconductor layer having a second lattice constant, and a third semiconductor layer having a third ...

SEMICONDUCTOR DEVICE, SUPERLATTICE LAYER USED IN THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a silicon substrate; a nitride nucleation layer disposed on the silicon substrate; at least one superlattice layer disposed on the nitride nucleation layer; and at least one gallium nitride-based semiconductor layer disposed on the superlattice layer. The at least one superlattice layer includes a stack of complex layers, each complex layer including a first layer and a second layer such that each of the complex layers has a plurality of nitride semiconductor layers having different compositions, at least one of the plurality of nitride semiconductor layers having a different thickness based on a location of the at least one nitride semiconductor layer within the stack, and at least one stress control layer having a thickness greater than a critical thickness for pseudomorphic growth. 1. A semiconductor device comprising:a silicon substrate;a nitride nucleation layer disposed on the silicon substrate;at least one superlattice layer disposed on the nitride nucleation layer; and a stack of complex layers, each complex layer including a first layer and a second layer such that each of the complex layers has a plurality of nitride semiconductor layers having different compositions, at least one of the plurality of nitride semiconductor layers having a different thickness based on a location of the at least one nitride semiconductor layer within the stack, and', 'at least one stress control layer having a thickness greater than a critical thickness for pseudomorphic growth, the at least one stress control layer being disposed between one of the plurality of nitride semiconductor layers and the complex layers., 'at least one gallium nitride-based semiconductor layer disposed on the superlattice layer, the at least one superlattice layer including,'}2. The semiconductor device of claim 1 , wherein the nitride nucleation layer comprises aluminum nitride (AlN).3. The semiconductor device of claim 1 , wherein each of the first layers comprises ...

SINGLE-CRYSTAL REO BUFFER ON AMORPHOUS SiOx

A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide. 19-. (canceled)10. A III-N on silicon wafer comprising:a crystalline silicon substrate;a layer of rare earth metal deposited on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C., the rare earth metal forming a layer of rare earth silicide on the substrate, the layer of rare earth silicide being transformed by annealing into a layer of amorphous silicon and an intermediate layer of rare earth oxide positioned between the substrate and the first layer of rare earth oxide; anda first layer of rare earth oxide deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate.11. A III-N on silicon wafer as claimed in further including a second layer of rare earth oxide with a structure and lattice constant substantially similar to the substrate claim 10 , the second layer of rare earth oxide positioned on the first layer of rare earth oxide to form a template for the subsequent deposition of a III-N semiconductor material.12. A III-N on silicon wafer as claimed in further including a layer of III-N semiconductor material positioned on the second layer of rare earth oxide claim ...

MULTILAYER SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A multilayer substrate structure comprises a substrate, a thermal matching layer formed on the substrate and a lattice matching layer above the thermal matching layer. The thermal matching layer includes at least one of molybdenum, molybdenum-copper, mullite, sapphire, graphite, aluminum-oxynitrides, silicon, silicon carbide, zinc oxides, and rare earth oxides. The lattice matching layer includes a first chemical element and a second chemical element to form an alloy. The first and second chemical element has similar crystal structures and chemical properties. The coefficient of thermal expansion of the thermal matching layer and the lattice parameter of the lattice matching layer are both approximately equal to that of a member of group III-V compound semiconductors. The lattice constant of the lattice matching layer is approximately equal to that of a member of group III-V compound semiconductor. 1. A multilayer substrate structure comprising:a substrate,a thermal matching layer formed on the substrate, the thermal matching layer including at least one of molybdenum, molybdenum-copper, mullite, sapphire, graphite, aluminum-oxynitrides, silicon, silicon carbide, zinc oxides, and rare earth oxides; anda lattice matching layer above the thermal matching layer, the lattice matching layer including a first chemical element and a second chemical element to form an alloy, the first and second chemical element having similar crystal structures and chemical properties,wherein the coefficient of thermal expansion of the thermal matching layer is approximately equal to that of a member of group III-V compound semiconductor,wherein the lattice constant of the lattice matching layer is approximately equal to that of a member of group III-V compound semiconductor.2. The multilayer substrate structure of further comprising an epitaxial layer epitaxially grown on the lattice matching layer claim 1 , the epitaxial layer including the member of group III-V compound semiconductor ...

JUNCTIONLESS ACCUMULATION-MODE DEVICES ON DECOUPLED PROMINENT ARCHITECTURES

A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy. 1. A junctionless accumulation mode (JAM) device comprising:a semiconductive first body including a channel region bounded by junctionless source and drain regions, wherein the semiconductive first body is located in a prominence that extends from a bulk semiconductive substrate, and wherein the semiconductive first body includes a first side, an edge, and a second side that is parallel-planar to the first side;a gate electrode that is wrapped around the prominence on each of the first side, the edge, and the second side;a semiconductive second body disposed opposite the edge and between the semiconductive first body and the bulk semiconductive substrate, wherein the semiconductive second body is differently doped from the semiconductive first body, and wherein the semiconductive second body causes a differential bias with the semiconductive first body; anda first semiconductive layer disposed between the bulk semiconductive substrate and the semiconductive second body.2. The device of claim 1 , wherein the first semiconductive layer comprises gallium arsenide.3. The device of further comprising a second semiconductive layer disposed between the first semiconductive layer and the semiconductive second body.4. The device of claim 3 , wherein the second semiconductive layer comprises aluminum indium antimonide.5. The device of claim 1 , wherein the semiconductive second body is also disposed within the prominence.6. The device of claim 1 , wherein the semiconductive second body is also disposed within the prominence claim 1 , and wherein a portion of the semiconductive second body has a form factor similar to the bulk semiconductive substrate.7. The device of claim 1 , wherein the semiconductive second body is also ...

MATERIALS, STRUCTURES, AND METHODS FOR OPTICAL AND ELECTRICAL III-NITRIDE SEMICONDUCTOR DEVICES

The present invention provides materials, structures, and methods for III-nitride-based devices, including epitaxial and non-epitaxial structures useful for III-nitride devices including light emitting devices, laser diodes, transistors, detectors, sensors, and the like. In some embodiments, the present invention provides metallo-semiconductor and/or metallo-dielectric devices, structures, materials and methods of forming metallo-semiconductor and/or metallo-dielectric material structures for use in semiconductor devices, and more particularly for use in III-nitride based semiconductor devices. In some embodiments, the present invention includes materials, structures, and methods for improving the crystal quality of epitaxial materials grown on non-native substrates. In some embodiments, the present invention provides materials, structures, devices, and methods for acoustic wave devices and technology, including epitaxial and non-epitaxial piezoelectric materials and structures useful for acoustic wave devices. In some embodiments, the present invention provides metal-base transistor devices, structures, materials and methods of forming metal-base transistor material structures for use in semiconductor devices. 1. A metallo-semiconductor structure comprising:a substrate having a top surface and a bottom surface; and wherein each of the one or more periods includes a first layer and a second layer,', 'wherein the first layer is a metal and the second layer is a semiconductor, and', 'wherein the first layer is substantially lattice matched to the second layer., 'one or more periods of a metallo-semiconductor on the top surface of the substrate,'}2. The structure of claim 1 , wherein the metal includes HfN and the semiconductor includes GaN.3. The structure of claim 1 , wherein the metal includes ZrN and the semiconductor includes GaN.4. The structure of claim 1 , wherein the metal includes HfN and the semiconductor includes AlN.5. The structure of claim 1 , wherein ...

NITRIDE-BASED COMPOUND SEMICONDUCTOR DEVICE

A nitride-based compound semiconductor device includes a substrate, a first nitride-based compound semiconductor layer that is formed above the substrate with a buffer layer interposed between them, a second nitride-based compound semiconductor layer that is formed on the first nitride-based compound semiconductor layer and that has a larger band gap than a band gap of the first nitride-based compound semiconductor layer, and an electrode that is formed on the second nitride-based compound semiconductor layer. The second nitride-based compound semiconductor layer has a region in which carbon is doped near a surface of the second nitride-based compound semiconductor layer. 1. A nitride-based compound semiconductor device comprising:a substrate;a first nitride-based compound semiconductor layer that is formed above the substrate with a buffer layer interposed therebetween;a second nitride-based compound semiconductor layer that is formed on the first nitride-based compound semiconductor layer and that has a larger band gap than a band gap of the first nitride-based compound semiconductor layer; andan electrode that is formed on the second nitride-based compound semiconductor layer, whereinthe second nitride-based compound semiconductor layer has a region in which carbon is doped near a surface of the second nitride-based compound semiconductor layer.2. The nitride-based compound semiconductor device according to claim 1 , wherein the region in which the carbon is doped has a depth of equal to or smaller than 10 nanometers from the surface of the second nitride-based compound semiconductor layer.3. The nitride-based compound semiconductor device according to claim 1 , wherein the carbon is doped using a resonant nuclear reaction with hydrogen.4. The nitride-based compound semiconductor device according to claim 2 , wherein the carbon is doped through ion implantation.5. The nitride-based compound semiconductor device according to claim 1 , wherein an irradiation defect ...

Integrated Composite Group III-V and Group IV Semiconductor Device

According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. 120-. (canceled)21. A monolithic integrated composite device comprising:a group IV semiconductor substrate supporting an overlying group III-V semiconductor body;a trench formed in said group III-V semiconductor body;a first buried layer having a first conductivity type formed in said trench over said group IV semiconductor substrate;a second buried layer having a second conductivity type opposite said first conductivity type formed over said first buried layer in said trench;a group IV semiconductor body formed in said trench over said second buried layer, said group IV semiconductor body including a defective region adjacent a sidewall of said trench.22. The monolithic integrated composite device of claim 21 , wherein said group IV semiconductor body comprises an epitaxial body grown in said trench.23. The monolithic integrated composite device of claim 21 , wherein said group IV semiconductor body comprises silicon.24. The monolithic integrated composite device of claim 21 , wherein said group III-V semiconductor body comprises a ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film in contact with the gate insulating film and including a channel formation region which overlaps with the gate electrode; a source electrode and a drain electrode over the oxide semiconductor film; and an oxide insulating film over the oxide semiconductor film, the source electrode, and the drain electrode. The source electrode and the drain electrode each include a first metal film having an end portion at the end of the channel formation region, a second metal film over the first metal film and containing copper, and a third metal film over the second metal film. The second metal film is formed on the inner side than the end portion of the first metal film. 1. A semiconductor device comprising:a gate electrode;a gate insulating film over the gate electrode;an oxide semiconductor film in contact with the gate insulating film, the oxide semiconductor film including a channel formation region overlapping with the gate electrode; anda source electrode and a drain electrode over the oxide semiconductor film;wherein the source electrode and the drain electrode each include a first metal film, a second metal film over the first metal film and containing copper, and a third metal film over the second metal film, andwherein an end portion of the second metal film is located on an inner side than an end portion of the first metal film on a side of the channel formation region.2. The semiconductor device according to claim 1 , wherein a thickness of the oxide semiconductor film in the channel formation region is smaller than a thickness of the oxide semiconductor film in a region in contact with the first metal film.3. The semiconductor device according to claim 1 , wherein the end portion of the second metal film is located on an inner side than an end portion of the third metal film on the side of the channel formation region.4. The semiconductor ...

Robust Fused Transistor

According to an exemplary implementation, a transistor includes a plurality of drain fingers interdigitated with a plurality of source fingers. The transistor further includes a gate configured to control current conduction between the plurality of drain fingers and the plurality of source fingers. Additionally, the transistor includes a plurality of drain fuses, each being configured to electrically disconnect a drain finger of the plurality of drain fingers from remaining ones of the plurality of drain fingers. At least one of the plurality of drain fuses can electrically couple the drain finger to a common drain pad. The transistor may further include a plurality of source fuses, each being configured to electrically disconnect a source finger of the plurality of source fingers from remaining ones of the plurality of source fingers. 1. A transistor comprising:a plurality of drain fingers interdigitated with a plurality of source fingers;a gate configured to control current conduction between said plurality of drain fingers and said plurality of source fingers;a plurality of drain fuses, each being configured to electrically disconnect a drain finger of said plurality of drain fingers from remaining ones of said plurality of drain fingers.2. The transistor of claim I , wherein at least one of said plurality of drain fuses electrically couples said drain finger to a common drain pad.3. The transistor of comprising a plurality of source fuses claim 1 , each being configured to electrically disconnect a source finger of said plurality of source fingers from remaining ones of said plurality of source fingers.4. The transistor of comprising a plurality of source fuses claim 1 , each electrically coupling a source finger of said plurality of source fingers to a common source pad.5. The transistor of claim 1 , wherein said transistor is a high-electron-mobility transistor (HEMT).6. The transistor of claim 1 , wherein said transistor is a gallium nitride (GaN) transistor. ...

Monolithic Integrated Group III-V and Group IV Device

According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT). 141-. (canceled)42. A monolithic vertically integrated composite device comprising:a semiconductor substrate having first and second sides;a group IV semiconductor layer formed over said first side and comprising at least one group IV semiconductor device;a group III-V semiconductor body formed over said second side and comprising at least one group III-V semiconductor device electrically coupled to said at least one group IV semiconductor device.43. The monolithic vertically integrated composite device of claim 42 , wherein said group IV semiconductor layer comprises an epitaxial layer grown over said first side.44. The monolithic vertically integrated composite device of claim 42 , further comprising a substrate via electrically coupling said at least one group III-V semiconductor device to said at least one group IV semiconductor device.45. The monolithic vertically integrated composite device of claim 42 , further comprising a through-wafer via electrically coupling said at least one group III-V semiconductor device to ...

COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0≦x1 Подробнее

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTORING THE SAME

A semiconductor device includes a first coalescent layer, a second coalescent layer, a nitride stacked structure on the second coalescent layer, and a third layer between the first and second coalescent layers. The first coalescent layer includes a plurality of formations that are partially merged, and the third layer is disposed on the formations to allow a first type of stress to be generated in an area which includes the first coalescent layer and a second type of stress to be generated in an area which includes the second coalescent layer. 1. A semiconductor device comprising:a first nitride semiconductor layer;a mask layer on the first nitride semiconductor layer;a first coalescent layer including a plurality of partially merged islands;a second coalescent layer on the first coalescent layer;an insertion layer between the first and second coalescent layers; anda nitride stacked structure on the second coalescent layer.2. The semiconductor device of claim 1 , wherein the mask layer comprises a silicon nitride material or a magnesium nitride material.3. The semiconductor device of claim 1 , wherein the first and second coalescent layers are formed of nitride semiconductor material.4. The semiconductor device of claim 3 , wherein each of the first and second coalescent layers are formed of at a material that includes at least one of a nitride or a metal.5. The semiconductor device of claim 1 , wherein at least one of the first coalescent layer or the second coalescent layer is made of a material that includes AlInGaN claim 1 , where 0≦x claim 1 , y≦1 and x+y<1.6. The semiconductor device of claim 1 , wherein the insertion layer is formed of at least one of AlInGaN (0≦x0 claim 1 , y0≦1 claim 1 , x0+y0≦1) claim 1 , step-grade AlInGaN (0≦x claim 1 , y≦1 claim 1 , x+y≦1) claim 1 , or AlInGaN/AlInGaN (0≦x1 claim 1 , x2 claim 1 , y1 claim 1 , y2≦1 claim 1 , x1≠x2 or y1≠y2) super lattice.7. The semiconductor device of claim 1 , wherein the insertion layer generates ...