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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 6330. Отображено 100.
10-05-2012 дата публикации

Method and system for manufacturing copper-based capacitor

Номер: US20120112315A1
Автор: LIN Huang, Yung Feng Lin, Zhen Chen
Принадлежит: Semiconductor Manufacturing International Shanghai Corp

Embodiments of the present invention provide a method and system for manufacturing copper-based capacitor on an integrated circuit. For example, the integrated circuit is associated with a channel length of less than 0.13 um. It is to be appreciated that, depending upon application, the present invention provides a more improved method for manufacturing capacitors and thus allow MIM capacitors to be manufactured at smaller dimensions. The method includes a step for providing a substrate. The method also includes a step for providing a layer of inter-metal dielectric overlaying the substrate. The method additionally includes a step for providing a bottom layer. The bottom layer includes a first portion and a second portion. The first portion can be characterized as electrically conductive. In addition, the method includes a step for providing a first insulating layer overlaying the bottom layer.

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Номер записи: 1
10-05-2012 дата публикации

Method of fabricating damascene structures

Номер: US20120115303A1
Автор: Anthony K. Stamper, Jeffrey P. Gambino, Peter J. Lindgren
Принадлежит: International Business Machines Corp

Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.

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Номер записи: 2
28-06-2012 дата публикации

Rectangular capacitors for dynamic random access memory (dram) and dual-pass lithography methods to form the same

Номер: US20120161215A1
Автор: Nick Lindert
Принадлежит: Intel Corp

A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective.

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Номер записи: 3
26-07-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120187535A1
Автор: Un Hee LEE
Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.

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Номер записи: 4
20-12-2012 дата публикации

Method of processing mim capacitors to reduce leakage current

Номер: US20120322220A1
Автор: Hanhong Chen, Hiroyuki Ode, Sandra Malhotra, Wim Deweerd, Xiangxin Rui
Принадлежит: Elpida Memory Inc, Intermolecular Inc

A method for processing dielectric materials and electrodes to decrease leakage current is disclosed. The method includes a post dielectric anneal treatment in an oxidizing atmosphere to reduce the concentration of oxygen vacancies in the dielectric material. The method further includes a post metallization anneal treatment in an oxidizing atmosphere to reduce the concentration of interface states at the electrode/dielectric interface and to further reduce the concentration of oxygen vacancies in the dielectric material.

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Номер записи: 5
21-03-2013 дата публикации

Memory cells, semiconductor devices, systems including such cells, and methods of fabrication

Номер: US20130069052A1
Автор: Gurtej S. Sandhu
Принадлежит: Micron Technology Inc

A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.

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Номер записи: 6
21-03-2013 дата публикации

Electrode Treatments for Enhanced DRAM Performance

Номер: US20130069202A1
Автор: Edward Haywood, Hanhong Chen, Kenichi Koyanagi, Naonori Fujiwara, Sandra G. Malhotra, Takakazu Kiyomura, Takashi Arao, Toshiyuki Hirota, Xiangxin Rui
Принадлежит: Elpida Memory Inc, Intermolecular Inc

A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO 2 ) on the first TiN electrode; depositing a dielectric material on the first layer of titanium dioxide; and depositing a second TiN electrode on the dielectric material.

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Номер записи: 7
04-04-2013 дата публикации

STACK PACKAGE

Номер: US20130082352A1
Автор: KIM Si Han, PARK Myung Geun
Принадлежит: SK HYNIX INC.

A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes. 1. A stack package comprising:a first semiconductor chip including a first surface having first pads and second pads disposed thereon, and a second surface facing away from the first surface;a second semiconductor chip including a third surface having third pads and fourth pads disposed thereon, and a fourth surface which facing away from the third surface, wherein the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip and the fourth pads are electrically connected with the second pads;connection members electrically connecting the first pads with the third pads and the second pads with the fourth pads;a substrate including a fifth surface attached to the fourth surface of the second semiconductor chip and having disposed thereon first connection pads and second connection pads, and a sixth surface facing away from the fifth surface and having third connection pads disposed thereon;capacitors including first electrodes electrically connected with the third pads, second electrodes electrically connected with the first connection. pads, and dielectrics interposed between the first electrodes and second electrodes; andconnection members connecting the fourth pads of the second semiconductor chip with the second connection pads of the substrate.2. The stack package according to claim 1 , further comprising:first ...

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Номер записи: 8
11-04-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130087888A1
Автор: KIKUCHI Hideaki, NAGAI Kouichi
Принадлежит:

There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective insulating film covering the metal wiring and the second insulating film, forming an insulating sidewall on a side of the metal wiring, forming a third insulating film on the insulating sidewall, forming a hole by etching the third insulating film under a condition that an etching rate of the insulating sidewall would be lower than that of the third insulating film, and forming a conductive plug inside the hole. 115-. (canceled)16. A semiconductor device comprising:a semiconductor substrate;a first insulating film formed over the semiconductor substrate;a capacitor formed over the first insulating film, the capacitor being constructed from a lower electrode, a capacitor dielectric film made of a ferroelectric material, and an upper electrode;a second insulating film formed over the capacitor;a metal wiring formed over the second insulating film;a first capacitor protective insulating film formed at least on a side surface of the metal wiring;an insulating sidewall formed on the first capacitor protective insulating film on beside the metal wiring;a third insulating film formed over the metal wiring and the insulating sidewall, the third insulating film having a hole over the metal wiring; anda conductive plug formed in the hole, the conductive plug being connected to the metal wiring.17. The semiconductor device according to claim 16 , wherein the insulating sidewall is made of any one of silicon nitride and silicon oxynitride claim 16 , and the third insulating film is made of silicon oxide.18. The semiconductor device according to claim 16 , wherein the first capacitor protective insulating film is formed on upper surfaces of the ...

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Номер записи: 9
11-04-2013 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20130089964A1
Автор: Kana Shimizu, Takamasa Itou, Takayuki Iwaki
Принадлежит: Renesas Electronics Corp

A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.

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Номер записи: 10
25-04-2013 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME

Номер: US20130102122A1
Автор: Chen Chien-Hua, Lee Teck-Chong
Принадлежит:

The present invention relates to a semiconductor package and a method for making the same. The method includes the steps of: (a) providing a base material; (b) forming a first metal layer on the base material, wherein the first metal layer comprises a first inductor and a first lower electrode; (c) forming a first dielectric layer and a first upper electrode on the first lower electrode, wherein the first dielectric layer is disposed between the first upper electrode and the first lower electrode, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor; and (d) forming a first protective layer, so as to encapsulate the first inductor and the first capacitor. 1. A method for making a semiconductor package , comprising the steps of(a) providing a base material, wherein the base material comprises at least one groove, at least one conductive via structure, a first surface and a second surface, the groove penetrates the first surface and the second surface of the base material, and the conductive via structure is disposed in the groove and exposed on the first surface and the second surface so as to form a through via structure;(b) forming a first metal layer on the first surface of the base material, wherein the first metal layer comprises a first inductor and a first lower electrode, and directly contacts the through via structure;(c) forming a first dielectric layer and a first upper electrode on the first lower electrode, wherein the first dielectric layer is disposed between the first upper electrode and the first lower electrode, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor; and(d) forming a first protective layer, so as to encapsulate the first inductor and the first capacitor.2. The method according to claim 1 , further comprising a step of forming a first insulation layer on the first surface of the base material after step (a) claim 1 , ...

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Номер записи: 11
02-05-2013 дата публикации

METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION

Номер: US20130105944A1
Автор: Buller James F., ZHU Jianhong
Принадлежит: GLOBALFOUNDRIES INC.

A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias. The design enables the spacing between metal lines to be maintained, the spacing between via to metal to be increased, and via connection to be maintained for both nets, thereby improving the conductivity and reliability of the capacitor and maintaining capacitance density. 1. A metal capacitor comprising:a first layer of alternating first and second substantially linear metal lines;a dielectric layer over the first layer;a second layer of alternating third and fourth substantially linear metal lines over the dielectric layer, wherein each first, second, third, and fourth metal line comprises alternating first and second segments, the first segments having a first width, the second segments having a second width, the first width being greater than the second width, and each first segment lies adjacent to a second segment of an adjacent metal line; andvias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein only the first segments of the metal lines overlap the vias.2. The capacitor according to claim 1 , wherein the first width is about 1.2 to about 3 times the second width.3. The capacitor according to claim 2 , wherein the first width is ...

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Номер записи: 12
09-05-2013 дата публикации

Semiconductor Package Having Passive Device and Method for Making the Same

Номер: US20130115749A1
Автор: Chen Chien-Hua, Lee Teck-Chong
Принадлежит:

The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced. 1. A method for making a semiconductor package , comprising the steps of:(a) providing a base material, wherein the base material comprises at least one groove and at least one conductive via structure;(b) forming a first capacitor on the base material, wherein the first capacitor comprises a first lower electrode, a first dielectric layer and a first upper electrode, the first lower electrode is disposed on the base material, the first dielectric layer is disposed on the first lower electrode, and the first upper electrode is disposed on the first dielectric layer;(c) forming a first protective layer, so as to encapsulate the first capacitor, wherein the first protective layer comprises a plurality of first openings, and the first openings expose the conductive via structure, part of the first lower electrode and part of the first upper electrode;(d) forming a first metal layer on the first protective layer, wherein the first metal layer comprises a first inductor, and directly contacts the conductive via structure, the first lower electrode and the first upper electrode; and(e) forming a second protective layer, so as to encapsulate the first inductor,2. The method according to claim 1 , further comprising a step of forming a first insulation layer ...

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Номер записи: 13
16-05-2013 дата публикации

Adsorption Site Blocking Method for Co-Doping ALD Films

Номер: US20130119513A1
Автор: Hanhong Chen, Hiroyuki Ode, Sandra Malhotra, Toshiyuki Hirota, Wim Deweerd
Принадлежит: Elpida Memory Inc, Intermolecular Inc

A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

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Номер записи: 14
16-05-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130122679A1
Автор: Wang Wensheng
Принадлежит: FUJITSU LIMITED

The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug buried in the insulation layer, a capacitor formed above the insulation layer and the conductor plug and including a lower electrode formed of the first conduction film and the second conduction film formed over the first conduction film and formed of Pt, Pt alloy, Pd or Pd alloy, a capacitor dielectric film formed of a ferroelectric or a high dielectric formed over the lower electrode and an upper electrode formed over the capacitor dielectric film, the capacitor dielectric film contains a first element of Pb or Bi, and the concentration peak of the first element diffused in the lower electrode from the capacitor dielectric film positioning in the interface between the first conduction film and the second conduction film. 1. A method for manufacturing a semiconductor device comprising a capacitor including a lower electrode , a capacitor dielectric film of a ferroelectric or a high dielectric formed over the lower electrode and an upper electrode formed over the capacitor dielectric film , comprising:forming a transistor over a semiconductor substrate;forming an insulation layer over the semiconductor substrate and over the transistor;burying a conductor plug in the insulation layer so that the conductor plug is electrically coupled to the transistor;forming over the insulation layer and the conductor plug, the lower electrode including the first conduction film and the second conduction film formed over the first conduction film;forming the capacitor dielectric film over the lower electrode, the capacitor dielectric film containing a first element of Pb or B, andforming the upper electrode over the capacitor dielectric film wherein the lower electrode prevents the diffusion of the first element at an interface between the first conduction film and the second conduction film.2. The method for manufacturing a semiconductor device according to claim 1 , whereinthe ...

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Номер записи: 15
16-05-2013 дата публикации

BLOCKING LAYERS FOR LEAKAGE CURRENT REDUCTION IN DRAM DEVICES

Номер: US20130122683A1
Автор: Chen Hanhong, Deweerd Wim Y., Malhotra Sandra G., Ode Hiroyuki
Принадлежит:

A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. 1. A method for forming a capacitor stack comprising:{'sub': '2', 'forming a MoOfirst electrode layer on a substrate;'}{'sub': 2', '2', '2, 'forming a TiOdielectric material on the first electrode layer wherein the TiOdielectric layer further contains a dopant and wherein the TiOdielectric material is more than about 30% crystalline after a subsequent annealing treatment;'}{'sub': 2', '3', '2', '2', '3', '2', '3, 'forming a LaOblocking layer on the TiOdielectric material wherein the LaOblocking layer further contains a dopant and wherein the LaOblocking layer is amorphous after a subsequent annealing treatment; and'}{'sub': 2', '3, 'forming a second electrode layer on the LaOblocking layer.'}2. The method of further comprising annealing the MoOfirst electrode layer before the forming of the TiOdielectric layer.3. The method of further comprising annealing the MoOfirst electrode layer claim 1 , the TiOdielectric material claim 1 , and the LaOblocking layer after the formation of the LaOblocking layer and before the forming of the second electrode layer.4. The method of wherein the MoOfirst electrode layer claim 1 , TiOdielectric material claim 1 , LaOblocking layer and second electrode layer are subjected to an annealing treatment after the formation of the second electrode layer.5. The method of wherein the dopant comprises one of Al claim 1 , Ce claim 1 , Co ...

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Номер записи: 16
16-05-2013 дата публикации

DOPING OF ZrO2 FOR DRAM APPLICATIONS

Номер: US20130122722A1
Автор: Cameron Thomas M., Cissell Julie, Hunks William, Peters David W., Xu Chongying
Принадлежит: ADVANCED TECHNOLOGY MATERIALS, INC.

A method of forming a dielectric material, comprising doping a zirconium oxide material, using a dopant precursor selected from the group consisting of Ti(NMe); Ti(NMeEt); Ti(NEt); TiCl; tBuN═Nb(NEt); tBuN═Nb(NMe); t-BuN═Nb(NEtMe); t-AmN═Nb(NEt); t-AmN═Nb(NEtMe); t-AmN═Nb(NMe); t-AmN═Nb(OBu-t); Nb-13; Nb(NEt); Nb(NEt); Nb(N(CH)); Nb(OC2H); Nb(thd)(OPr-i); SiH(OMe); SiCU; Si(NMe); (MeSi)NH; GeRx(OR)wherein x is from 0 to 4, each Ris independently selected from H or C-Calkyl and each Ris independently selected from C-Calkyl; GeCl; Ge(NR)wherein each Ris independently selected from H and C-Calkyl; and (RGe)NH wherein each Ris independently selected from C-Calkyl; bis(N,N′-diisopropyl-1,3-propanediamide) titanium; and tetrakis(isopropylmethylamido) titanium; wherein Me is methyl, Et is ethyl, Pr-i is isopropyl, t-Bu is tertiary butyl, t-Am is tertiary amyl, and thd is 2,2,6,6-tetramethyl-3,5-heptanedionate. Doped zirconium oxide materials of the present disclosure are usefully employed in ferroelectric capacitors and dynamic random access memory (DRAM) devices. 1. A method of forming a dielectric material , comprising doping a zirconium oxide material , using as a dopant precursor a precursor selected from the group consisting of Ti(NMe); Ti(NMeEt); Ti(NEt); TiCl; tBuN═Nb(NEt); tBuN═Nb(NMe); t-BuN═Nb(NEtMe); t-AmN═Nb(NEt); t-AmN═Nb(NEtMe); t-AmN═Nb(NMe); t-AmN═Nb(OBu-t); Nb-13; Nb(NEt); Nb(NEt); Nb(N(CH)); Nb(OCH); Nb(thd)(OPr-i); SiH(OMe); SiCl; Si(NMe); (MeSi)NH; GeR(OR)wherein x is from 0 to 4 , each Ris independently selected from H or C-Calkyl and each Ris independently selected from C-Calkyl; GeCl; Ge(NR)wherein each Ris independently selected from H and C-Calkyl; and (RGe)NH wherein each Ris independently selected from C-Calkyl; bis(N ,N′-diisopropyl-1 ,3-propanediamide) titanium; and tetrakis(isopropylmethylamido) titanium; wherein Me is methyl , Et is ethyl , Pr-i is isopropyl , t-Bu is tertiary butyl , t-Am is tertiary amyl , and thd is 2 ,2 ,6 ,6-tetramethyl- ...

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Номер записи: 17
23-05-2013 дата публикации

HERMETIC PACKAGING OF INTEGRATED CIRCUIT COMPONENTS

Номер: US20130127014A1
Автор: Chahal Premjeet, Morris Francis J.
Принадлежит: Raytheon Company

A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment. 1. A method for forming a hermetically-packaged integrated circuit , comprising:transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer;providing an integrated circuit device proximate an outer surface of the first substrate layer, the integrated circuit device operable to transmit or receive electrical signals through the conductive region; anddisposing a second substrate layer proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.2. The method of claim 1 , wherein transforming the portion of the first substrate layer comprises:forming a metal layer on the outer surface of the first substrate layer; andannealing the metal layer and first substrate layer to cause the metal layer to diffuse into the first substrate layer to form the conductive region.3. The method of claim 2 , wherein:the metal layer is selected from the group consisting of Cobalt (Co), Hafnium (Hf), Molybdenum (Mo), Niobium (Nb), Nickel (Ni), Palladium (Pd), Platinum (Pt), Tantalum (Ta), Tin (Ti), Vanadium (V), Tungsten (W), and Zirconium (Zr); and{'sub': 2', '2', '2', '2', '2', '2', '2', '2', '2', '2', '2, 'the conductive region comprises a silicide selected from the group consisting of CoSi, HfSi, MoSi, NbSi, NiSi, PdSi, PtSi, TaSi, TiSi, VSi, WSi, and ZrSi.'}4. The method of claim 1 , wherein transforming the portion of the first ...

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Номер записи: 18
23-05-2013 дата публикации

Band Gap Improvement In DRAM Capacitors

Номер: US20130127015A1
Автор: Hanhong Chen, Hiroyuki Ode, Sandra Malhotra, Wim Deweerd
Принадлежит: Intermolecular Inc

A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO 2 and ZrO 2 and further comprises a dopant of Al 2 O 3 . In some embodiments, the compound high k dielectric material comprises an admixture of TiO 2 and HfO 2 and further comprises a dopant of Al 2 O 3 .

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Номер записи: 19
30-05-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130134556A1
Автор: HIROTA Toshiyuki
Принадлежит: ELPIDA MEMORY, INC.

This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion. 1. A semiconductor device comprising a plurality of capacitors , each of the capacitors comprising:a cylindrical lower electrode having a top open edge, the cylindrical lower electrode being formed over a substrate,an upper electrode,a dielectric film between the cylindrical lower electrode and the upper electrode,a plate support extending over the substrate in a plate shape, the plate support being contacted on a side surface of the cylindrical lower electrodes at a contacting portion, and links to support the cylindrical lower electrodes, anda pore portion provided in the plate support, a part of the side surface of the cylindrical lower electrodes being exposed on the pore portion of the plate support,wherein a topmost open edge of the cylindrical lower electrode is located at an upper position than a top surface of the plate support.2. The semiconductor device according to claim 1 , wherein same plate support directly links at least more than three cylindrical lower electrodes.3. The semiconductor device according to claim 1 , wherein the pore portion is selectively formed in the plate support in a hole shape ...

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Номер записи: 20
06-06-2013 дата публикации

MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING

Номер: US20130140673A1
Автор: Goergens Lutz, Haeberlen Oliver, Krumrey Joachim, Paolucci Milko, Poelzl Martin, Rieger Walter, Schoiswohl Johannes, Vielemeyer Martin
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other. 1. A semiconductor device comprising:a semiconductor die having a first and a second side opposite each other, and comprising a first n-type channel FET and a second n-type channel FET;wherein a source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at the first side of the semiconductor die;wherein a drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and a gate of the second n-type channel FET are electrically coupled to contact areas at the second side of the one semiconductor die;wherein the contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other; andwherein the first FET is a lateral FET and the second FET is a trench FET and wherein an electrical connection from the contact area of the first FET at the first side to the source of the first FET includes a conductive plug.2. The semiconductor device of claim 1 , further comprising a Schottky diode connected in parallel to the source and the drain of the second n-type channel FET.3. A semiconductor device comprising:a ...

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Номер записи: 21
06-06-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130140674A1
Автор: FUJISAWA Hiroki, IWAKURA Ken, KATAGIRI Mitsuaki, SHINKAI Go, TAKEDA Hiromasa, Uematsu Yutaka
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line. 1. A semiconductor device comprising:first and second power lines that supply an operating voltage to a first circuit;third and fourth power lines that supply an operating voltage to a second circuit different from said first circuit; anda first capacitive element provided between said first power line and said third power line.2. The semiconductor device according to claim 1 , further comprising:a second capacitive element provided between said first power line and said second power line.3. The semiconductor device according to claim 1 , further comprising:a third capacitive element provided between said third power line and said fourth power line.4. The semiconductor device according to claim 1 , further comprising:a fourth capacitive element provided between said second power line and said fourth power line.5. The semiconductor device according to claim 1 , further comprising:a switching element connected in series with said first capacitive element between said first power line and said third power line.6. The semiconductor device according to claim 1 , wherein the first circuit is an output circuit.7. The semiconductor device according to claim 1 , further comprising:a substrate to which first to fourth power supply terminals and an output terminal are connected;first to fourth connecting lines that connect said first to fourth power lines to the first to fourth power supply terminals, respectively; andan output line that connects the output terminal to the first circuit. 1. Field of the InventionThe present invention relates to a semiconductor device.2. Description of Related ArtThe speed of handling signals has been increasing in recent semiconductor devices such as a DRAM (Dynamic ...

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Номер записи: 22
06-06-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

Номер: US20130140676A1
Автор: Wang Wensheng
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOxand whose actual composition is expressed as AOx; a second layer formed on the first layer and formed of an oxide whose stoichiometric composition is expressed as BOyand whose actual composition is expressed as BOy; and a metal layer formed on the second layer. The second layer is higher in ratio of oxidation than the first layer. The composition parameters x, x, y, and ysatisfy y/y>x/x, and the second layer includes an interface layer of the stoichiometric composition formed at an interface with the metal layer. The interface layer is higher in ratio of oxidation than the rest of the second layer. 1. A semiconductor device , comprising:a substrate; anda ferroelectric capacitor formed on the substrate, the ferroelectric capacitor includinga lower electrode;a ferroelectric film formed on the lower electrode;a first conductive oxide film formed on the ferroelectric film;a second conductive oxide film formed on the first conductive oxide film; anda metal layer formed on the second conductive oxide film,wherein the second conductive oxide film is crystallized, andthe second conductive oxide film includes a first region at an interface with the metal layer, anda second region between the first region and the first conductive oxide film, andthe second region is higher in ratio of oxidation than the first conductive oxide film, andan oxygen concentration of the second conductive oxide film is higher in the first region than in the second region.2. The semiconductor device as claimed in claim 1 , wherein a metal element of the first conductive oxide film is equal to a metal element of the second conductive oxide film.3. The semiconductor device as claimed in claim 1 , wherein the first and second conductive oxide ...

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Номер записи: 23
06-06-2013 дата публикации

CAPACITOR STRUCTURES FOR SEMICONDUCTOR DEVICE

Номер: US20130140677A1
Автор: Ang Yong Kheng, Chu Tsui Ping, Kho Evie Siaw Hei, Tia Swee Hua, YANG Peng
Принадлежит: X-Fab Semiconductor Foundries AG

A semiconductor device comprising a semiconductor substrate and a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials, wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other. This can minimize the voltage dependence of the capacitance of the composite capacitor structure. It is also possible to provide a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises at least a first and a second capacitor stack, each comprising a lower and an upper capacitor. The capacitors can be MIM capacitors. 1. A semiconductor device comprising:a semiconductor substrate;a composite capacitor structure on the semiconductor substrate,wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials,wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other.2. A semiconductor device according to claim 1 , wherein the first and second dielectric materials are different materials.3. A semiconductor device according to claim 1 , wherein the linear voltage coefficients of capacitance respectively of the first and second dielectric materials have opposite signs.4. A semiconductor device according to claim 1 , wherein the quadratic voltage coefficients of capacitance respectively of the first and second dielectric materials have opposite signs.5. A semiconductor device according to claim 1 , wherein one of the first and second dielectric materials comprises an oxide and the other comprises a nitride.6. A semiconductor device according to claim 1 , wherein the thickness of the first dielectric material is different ...

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Номер записи: 24
06-06-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

Номер: US20130143333A1
Автор: Wang Wensheng
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOxand whose actual composition is expressed as AOx; a second layer formed on the first layer and formed of an oxide whose stoichiometric composition is expressed as BOyand whose actual composition is expressed as BOy; and a metal layer formed on the second layer. The second layer is higher in ratio of oxidation than the first layer. The composition parameters x, x, y, and ysatisfy y/y>x/x, and the second layer includes an interface layer of the stoichiometric composition formed at an interface with the metal layer. The interface layer is higher in ratio of oxidation than the rest of the second layer. 1. A method of manufacturing a semiconductor device , the method including forming a ferroelectric capacitor , wherein: forming a lower electrode;', 'depositing a ferroelectric film on the lower electrode;', 'depositing a first conductive oxide film on the ferroelectric film;', 'crystallizing the first conductive oxide film in an oxidizing atmosphere;', 'depositing a second conductive oxide film in a microcrystalline state on the first conductive oxide film after said crystallizing;', 'crystallizing a surface of the second conductive oxide film in an oxidizing atmosphere; and', 'depositing a metal film on the second conductive oxide film after said crystallizing the surface thereof., 'said forming the ferroelectric capacitor includes'}2. The method as claimed in claim 1 , wherein each of said crystallizing the first conductive oxide film and said crystallizing the surface of the second conductive oxide film is performed with a rapid heat treatment process with a ratio of an oxidizing gas in the oxidizing atmosphere being less than or equal to 30%.3. The method as claimed in claim 2 , wherein the rapid heat ...

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Номер записи: 25
06-06-2013 дата публикации

HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR

Номер: US20130143384A1
Автор: Chen Hanhong, Deweerd Wim, Horikawa Mitsuhiro, Koyanagi Kenichi, Malhotra Sandra, Ode Hiroyuki, Rui Xiangxin
Принадлежит:

A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. 1. A method for forming a capacitor stack , the method comprising:forming a first electrode material above a substrate;forming a first dielectric material above the first electrode material, wherein the first dielectric material further contains a dopant;forming a second dielectric material above the first dielectric material, wherein the second dielectric material further contains a dopant and a doping level of the second dielectric material is less than a doping level of the first dielectric material;forming a second electrode material on the second dielectric material; andannealing the stack, wherein the first dielectric material is less than 30% crystalline after the annealing and the second dielectric material is equal to or greater than 30% crystalline after the annealing.2. The method of further comprising a post metallization anneal treatment after the forming of the second electrode material.3. The method of wherein the first electrode material is one of a metal claim 1 , conductive metal oxide claim 1 , conductive metal silicide claim 1 , conductive metal carbides claim 1 , conductive metal nitride claim 1 , or combinations thereof.4. The method of wherein the dopant comprises one of Al claim 1 , Zr claim 1 , Ge claim 1 , Hf claim 1 , Sn claim 1 , Sr claim 1 , Y claim 1 , Si claim 1 , Ti claim 1 , La claim 1 , Er claim 1 , Ga claim 1 , Gd claim 1 , Mg claim 1 , Co claim 1 , or combinations thereof.5. ...

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Номер записи: 26
13-06-2013 дата публикации

Integrated Capacitive Device Having a Thermally Variable Capacitive Value

Номер: US20130147004A1
Автор: Di-Giacomo Antonio, Fornara Pascal, Rivero Christian
Принадлежит: STMICROELECTRONICS (ROUSSET) SAS

An integrated circuit, comprising a capacitive device having a thermally variable capacitive value and comprising a thermally deformable assembly disposed within an enclosure, and comprising an electrically-conducting fixed body and a beam held at at least two different locations by at least two arms rigidly attached to edges of the enclosure, the beam and the arms being metal and disposed within the first metallization level. A part of the said thermally deformable assembly may form a first electrode of the capacitive device and a part of the said fixed body may form a second electrode of the capacitive device. The thermally deformable assembly has a plurality of configurations corresponding respectively to various temperatures of the said assembly and resulting in a plurality of distances separating the two electrodes and various capacitive values in the capacitive device corresponding to the plurality of distances. 1. An integrated circuit , comprising:a first metallization level disposed on a substrate and separated from a second metallization level by an insulating region; a thermally deformable assembly disposed within an enclosure, and comprising a beam held at at least two different locations by at least two arms rigidly attached to edges of the enclosure, the beam and the arms being metal and disposed within the first metallization level; and', 'an electrically-conducting fixed body;, 'a capacitive device having a thermally variable capacitive value and comprisingwherein a part of the said thermally deformable assembly forms a first electrode of the capacitive device;wherein a part of the said fixed body forms a second electrode of the capacitive device;wherein the said thermally deformable assembly has a plurality of configurations corresponding respectively to various temperatures of the said assembly and resulting in a plurality of distances separating the first electrode and second electrode and various capacitive values in the capacitive device ...

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Номер записи: 27
13-06-2013 дата публикации

Wafer Level Package Having Cylindrical Capacitor and Method Of Fabrication The Same

Номер: US20130147014A1
Автор: LEE Seung Seoup, YIM Soon Gyu
Принадлежит: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided. 1. A wafer level package having a cylindrical capacitor , comprising:a wafer chip including a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad;a redistribution layer connected to the bonding pad and extending to one side of the insulating layer;a cylindrical outer electrode connected to the redistribution layer and having a center opening therein;a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode;a dielectric layer formed between the outer electrode and the inner electrode; anda resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer,wherein a lower surface of the inner electrode is connected to a peripheral wiring layer which is formed on the insulating layer and which extends from outside the outer ...

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Номер записи: 28
13-06-2013 дата публикации

DEEP TRENCH DECOUPLING CAPACITOR AND METHODS OF FORMING

Номер: US20130147015A1
Автор: NAKOS James S., SPROGIS EDMUND J., Stamper Anthony K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a method of forming a semiconductor device includes: forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate; depositing a dielectric liner layer inside the trench; depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate; forming a silicide layer over a portion of the doped polysilicon layer; forming an intermediate contact layer within the inner trench; and forming a contact over a portion of the intermediate contact layer and a portion of the silicide layer. 1. A method of forming a semiconductor device , the method comprising:forming an outer trench in a silicon substrate, the forming exposing portions of the silicon substrate below an upper surface of the silicon substrate;depositing a dielectric liner layer inside the trench;depositing a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench in the silicon substrate;forming a silicide layer over a portion of the doped polysilicon layer;forming an intermediate contact layer within the inner trench; andforming a contact over a portion of the intermediate contact layer and a portion of the silicide layer.2. The method of claim 1 , wherein the dielectric liner layer substantially covers the exposed portions of the silicon substrate3. The method of claim 1 , further comprising forming at least one shallow trench isolation in the silicon substrate claim 1 , the at least one shallow trench isolation substantially filled with the dielectric liner layer and located below the upper surface of the silicon substrate4. The method of claim 1 , wherein the intermediate contact layer includes at least one of:silicon or tungsten polycide.5. The method of claim 1 , wherein the contact is partially ...

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Номер записи: 29
13-06-2013 дата публикации

DUAL NSD IMPLANTS FOR REDUCED RSD IN AN NMOS TRANSISTOR

Номер: US20130149829A1
Автор: Nandakumar Mahalingam
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks. 1. A method of forming a portion of an integrated circuit comprising:forming first and second source/drain regions in active areas of an NMOS region by implanting a first dose of phosphorous, a first dose of arsenic and a first dose of nitrogen;performing a first process thermal process that activates the formed first and second source/drain regions in the NMOS region;implanting the first source/drain region and a third source/drain region with a second dose of phosphorus.2. The method of wherein the second dose of phosphorous is equal to or larger than the first dose of phosphorous.3. The method of claim 1 , further comprising forming well regions and isolation regions in a semiconductor substrate of the NMOS region prior to implanting the first dose of phosphorous and a first dose of arsenic.4. The method of claim 3 , further comprising forming gate electrodes in the NMOS region prior to implanting the first dose of phosphorous and a first dose of arsenic.5. The method of claim 4 , further comprising forming first source/drain sidewall spacers prior to implanting the first dose of phosphorous and a first dose of arsenic.6. The method of claim 5 , further comprising performing an LDD implantation in the source/drain ...

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Номер записи: 30
13-06-2013 дата публикации

Methods of Manufacturing Semiconductor Devices

Номер: US20130149833A1
Автор: Choi Jae Hyoung, KANG Sang Yeol, KIM Joon, Kim Youn Soo, Kwon Ho Jun, PARK Ki Yeon, YOO Cha Young
Принадлежит:

A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes. 1. A method of manufacturing a semiconductor device , the method comprising:forming a plurality of bottom electrodes in a plurality of holes that pass through a mold layer and a support layer;exposing a surface of the plurality of bottom electrodes by removing a portion of the mold layer;removing a portion of ones of the plurality of bottom electrodes from the exposed surface of respective ones of the plurality of bottom electrodes; andsequentially forming a dielectric layer and a top electrode layer on the plurality of bottom electrodes.2. The method according to claim 1 , wherein exposing the portion of the plurality of bottom electrodes by removing the portion of the mold layer comprises performing partial removing operations a plurality of times.3. The method according to claim 1 , wherein removing the portion of the ones of the plurality of bottom electrodes comprises:oxidizing a portion of ones of the plurality of bottom electrodes from each exposed surface of the ones of the plurality of bottom electrodes; andremoving the oxidized portion of the ones of the plurality of bottom electrodes.4. The method according to claim 3 , wherein oxidizing the portion of the ones of the plurality of bottom electrodes is performed in an atmosphere of Oplasma claim 3 , Oplasma claim 3 , O claim 3 , O claim 3 , or HO (vapor) and/or in the air atmosphere.5. The method according to claim 3 ...

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Номер записи: 31
20-06-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130154056A1
Автор: TONARI Kazuaki
Принадлежит: ELPIDA MEMORY, INC.

In a semiconductor device including a capacitor which has an upper electrode, a polycrystalline silicon layer on the upper electrode, and a metallic member on the polycrystalline silicon layer, the polycrystalline silicon layer includes germanium so that an upper portion of the polycrystalline silicon layer is lower than a lower portion thereof in a concentration of germanium. 1. A semiconductor device comprising:a lower electrode formed over a semiconductor substrate;a dielectric film formed on the lower electrode;an upper electrode formed on the dielectric film;a polycrystalline silicon layer formed on the upper electrode; anda metallic member contacted with an upper surface of the polycrystalline silicon layer;wherein a concentration of germanium in an upper portion of the polycrystalline silicon layer is lower than that in a lower portion of the polycrystalline silicon layer.2. The semiconductor device as claimed in claim 1 , wherein the lower electrode has a cylindrical shape.3. The semiconductor device as claimed in claim 2 , wherein the polycrystalline silicon layer is filled within a concave portion of the upper electrode which is located within a concave portion of the lower electrode.4. The semiconductor device as claimed in claim 1 , wherein the polycrystalline silicon layer has a thickness which is 20 nm or more.5. The semiconductor device as claimed in claim 1 , wherein the polycrystalline silicon layer includes boron.6. The semiconductor device as claimed in claim 1 , wherein the upper electrode includes a metallic film.7. The semiconductor device as claimed in claim 1 , wherein the metallic member is a metallic contact plug which is located over the lower electrode.8. The semiconductor device as claimed in claim 1 , wherein the dielectric film includes a metal oxide film.9. The semiconductor device as claimed in claim 8 , wherein the metal oxide film includes at least one oxide film selected from a group consisting of a titanium oxide film claim 8 , a ...

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Номер записи: 32
20-06-2013 дата публикации

Method for Fabricating a DRAM Capacitor

Номер: US20130154057A1
Автор: Chen Hanhong, Deweerd Wim, Fuchigami Nobumichi, Ode Hiroyuki, Ramani Karthik
Принадлежит:

A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiOis used as the dielectric layer. The rutile-phase of TiOhas a higher k value than the other possible crystal structures of TiOresulting in improved performance of the DRAM capacitor. 1. A semiconductor layer stack comprising:a first electrode layer formed on a substrate, the first electrode layer comprising a conductive metal oxide;wherein the first electrode layer has been annealed in a reducing atmosphere;a dielectric layer formed on the first electrode layer; anda second electrode layer formed on the dielectric layer.2. The semiconductor layer stack of claim 1 , wherein the reducing atmosphere comprises one of hydrogen claim 1 , ammonia claim 1 , or mixtures thereof.3. The semiconductor layer stack of claim 2 , wherein the reducing atmosphere is about 1 to 10% hydrogen in nitrogen.4. The semiconductor layer stack of claim 1 , wherein the annealing is performed at a temperature between about 400 C to about 650 C.5. The semiconductor layer stack of claim 1 , wherein the annealing is performed using one of thermal energy claim 1 , plasma energy claim 1 , or rapid thermal annealing.6. The semiconductor layer stack of wherein the conductive metal oxide is molybdenum oxide claim 1 , wherein at least about 40% of the molybdenum oxide is present as crystalline MoO.7. The semiconductor ...

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Номер записи: 33
27-06-2013 дата публикации

Semiconductor Package Including Stacked Semiconductor Chips and a Redistribution Layer

Номер: US20130161788A1
Автор: An Sang-Ho, Chun Sung-Hoon, Kim Hye-jin, KIM Kyung-Man, LEE Seok-Chan
Принадлежит:

Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads. 1. A semiconductor package , comprising:a plurality of first semiconductor chips comprising an uppermost first semiconductor chip on a board, the plurality of first semiconductor chips including respective ones of a plurality of data pads and respective ones of a plurality of power pads, and the plurality of data pads comprising a first data pad in the uppermost first semiconductor chip;a wiring layer on the uppermost first semiconductor chip, the wiring layer including a redistribution pattern and a redistribution pad that is electrically connected to the redistribution pattern;a second semiconductor chip on the uppermost first semiconductor chip, the second semiconductor chip being electrically connected to the redistribution pattern;a plurality of first conductive connections between two of the plurality of data pads;a second conductive connection between the uppermost first semiconductor chip and the second semiconductor chip;a third conductive connection between the second semiconductor chip and the board,wherein one of the plurality of data pads is electrically connected to the board via the second conductive connection, the second semiconductor chip, the redistribution pattern, the redistribution pad and the third conductive connection.2. The semiconductor package of claim 1 , wherein the redistribution pad is one among a plurality of redistribution pads ...

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Номер записи: 34
27-06-2013 дата публикации

METHOD OF MANUFACTURING A FeRAM DEVICE

Номер: US20130161790A1
Автор: KIKUCHI Hideaki, NAGAI Kouichi
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a Pt film is formed as a cap layer on the upper electrode film. Then, a hard mask (a TiN film and an SiOfilm) of a predetermined pattern is formed on the Pt film, and the Pt film and the upper electrode film are etched. Then, an insulating protective film is formed on an entire surface, and a side surface of the upper electrode film is covered with the insulating protective film. Next, the ferroelectric film and the lower electrode film are etched, thus forming a ferroelectric capacitor. 16.-. (canceled)7. A method of manufacturing a semiconductor device comprising:forming an insulation film on a semiconductor substrate;forming a lower electrode film on the insulation film;forming a ferroelectric film on the lower electrode film;forming an upper electrode film on the ferroelectric film;forming a hard mask of a predetermined pattern on the upper electrode film;removing the upper electrode film on a portion uncovered with the hard mask;forming a first insulating protective film on an entire upper surface of the semiconductor substrate and covering a side surface of the remaining upper electrode film with the first insulating protective film;removing the ferroelectric film on the portion uncovered with the hard mask;forming a second insulating protective film on the entire upper surface of the semiconductor substrate and covering a side surface of the remaining ferroelectric film with the second insulating protective film;removing the lower electrode film on the portion uncovered with the hard mask; andremoving the hard mask.8. The method of manufacturing a semiconductor device according to claim 7 , wherein claim 7 , in the removing of the upper electrode film claim 7 , the ferroelectric film is etched halfway in a thickness direction.9. The method of manufacturing a semiconductor device ...

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Номер записи: 35
27-06-2013 дата публикации

3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY

Номер: US20130161791A1
Автор: Chen Fen, Li Baozhen, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided. 1. A capacitor , comprising:an insulating layer on a substrate, said insulating layer including a via having sidewalls and a bottom;a first electrode overlying said sidewalls and at least a portion of said bottom of said via;a first high-k dielectric material layer overlying said first electrode;a first conductive plate over said first high-k dielectric material layer;a second high-k dielectric material layer formed to overlie the first conductive plate and to leave a remaining portion of said via unfilled; anda second electrode formed in said remaining portion of said via, wherein said first conductive plate is substantially parallel to said first electrode and is not in contact with said first and second electrodes.2. The capacitor of claim 1 , further comprising a second conductive plate and a third high-k dielectric material layer between said second high-k dielectric material layer and said second electrode claim 1 , wherein said second conductive plate is substantially parallel to said first electrode and is not in contact with said first and second electrodes and said first conductive plate.3. The capacitor of claim 1 , further comprising:a lower ...

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Номер записи: 36
27-06-2013 дата публикации

3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY

Номер: US20130164905A1
Автор: Chen Fen, Li Baozhen, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided. 1. A method of forming a capacitor , comprising:providing a substrate having a lower interconnect level including a first dielectric layer having a first conductive feature embedded therein, a first dielectric capping layer on said lower interconnect level, an insulating layer on said first dielectric capping layer, and a patterned hardmask layer having a top surface on said insulating layer, wherein said insulating layer has a via that extends partially through said first dielectric capping layer, said via having sidewalls and a bottom;forming a first electrode layer over said sidewalls and said bottom of said via and said top surface of said hardmask layer;forming a first high-k dielectric material layer over said first electrode layer;forming a first conductive plate layer over said first high-k dielectric material layer;forming a via gouging at said bottom of said via by removing a portion of said first conductive plate layer, a portion of said first high-k dielectric material layer, a portion of said first electrode layer, a portion of said first dielectric capping layer and a portion of said first conductive feature, said via gouging having ...

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Номер записи: 37
27-06-2013 дата публикации

FILM DEPOSITION METHOD

Номер: US20130164936A1
Автор: KOAKUTSU Masato, OSHIMO Kentaro
Принадлежит: TOKYO ELECTRON LIMITED

A film deposition method includes a film depositing step of depositing titanium nitride on a substrate mounted on a substrate mounting portion of a turntable, which is rotatably provided in a vacuum chamber, by alternately exposing the substrate to a titanium containing gas and a nitrogen containing gas which is capable of reacting with the titanium containing gas while rotating the turntable; and an exposing step of exposing the substrate on which the titanium nitride is deposited to the nitrogen containing gas, the film depositing step and the exposing step being continuously repeated to deposit the titanium nitride of a desired thickness. 1. A film deposition method , comprising:a film depositing step of depositing titanium nitride on a substrate mounted on a substrate mounting portion of a turntable, which is rotatably provided in a vacuum chamber, by alternately exposing the substrate to a titanium containing gas and a nitrogen containing gas which is capable of reacting with the titanium containing gas while rotating the turntable; andan exposing step of exposing the substrate on which the titanium nitride is deposited to the nitrogen containing gas,the film depositing step and the exposing step being continuously repeated to deposit the titanium nitride of a desired thickness.2. The film deposition method according to claim 1 ,wherein in the film deposition step, the substrate is exposed to an inert gas between being exposed to the titanium containing gas and the nitrogen containing gas.3. The film deposition method according to claim 1 ,wherein in the exposing step, the substrate is exposed to the nitrogen containing gas and an inert gas in this order.4. The film deposition method according to claim 1 ,wherein the titanium containing gas is supplied from a first reaction gas supplying portion toward the turntable, andthe nitrogen containing gas is supplied from a second reaction gas supplying portion, which is provided to be apart from the first reaction gas ...

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Номер записи: 38
04-07-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

Номер: US20130168813A1
Автор: Sashida Naoya
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten. 1. A semiconductor device comprising:a semiconductor substrate;a first insulating film that is formed over the semiconductor substrate;a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode;a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; anda conductor plug that is formed in the hole and contains tungsten.2. The semiconductor device according to claim 1 ,wherein the center of gravity of the hole and the center of gravity of the upper electrode coincide with each other in plan view.3. The semiconductor device according to claim 1 ,wherein the shape of the hole is similar to the shape of the upper electrode in plan view.4. The semiconductor device according to claim 1 ,wherein the hole is larger than a lower surface of the upper electrode in plan view.5. The semiconductor device according to claim 1 ,wherein the conductor plug includes a tungsten film having a recess in an upper surface of the tungsten film, and a copper wiring is formed in the recess.6. The semiconductor device according to claim 5 , further comprising:a third insulating film that is formed over the second insulating film and has a wiring groove on the hole, the wiring groove being continuous to the recess,wherein the copper wiring is formed in the recess and the wiring groove.7. The semiconductor ...

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Номер записи: 39
04-07-2013 дата публикации

Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD)

Номер: US20130171800A1
Автор: Frye Robert C., Lin Yaojian
Принадлежит: STATS CHIPPAC, LTD.

A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first conductive layer over the substrate;forming a first insulating layer over the substrate and first conductive layer;forming a second insulating layer over the first insulating layer;forming a first opening through the second insulating layer to the first insulating layer; andforming a second conductive layer within the first opening over the first insulating layer and separated from the first conductive layer by the first insulating layer.2. The method of claim 1 , further including:forming a second opening through the first and second insulating layers; andforming a third conductive layer within the second opening.3. The method of claim 1 , wherein the second conductive layer claim 1 , first insulating layer claim 1 , and first conductive layer operate as a capacitor.4. The method of claim 1 , further including disposing a resistive layer between the first conductive layer and first insulating layer.5. The method of claim 1 , further including forming an interconnect structure over the second insulating layer.6. The ...

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Номер записи: 40
11-07-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING CAPACITOR INTEGRATED THEREIN

Номер: US20130175666A1
Автор: Barry Scott W., Ellul Joseph P., Ikeuchi Kiyoko, Srivastava Anuranjan, Tran Khanh
Принадлежит: MAXIM INTEGRATED PRODUCTS, INC.

Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes. 1. A semiconductor device comprising:a substrate having dopant material of a first conductivity type;a plurality of trenches disposed within the substrate;a diffusion region disposed proximate to the plurality of trenches, the diffusion region having dopant material of a second conductivity type; anda metal-insulator-metal (MIM) capacitor formed within each trench of the plurality of trenches.2. The semiconductor device as recited in claim 1 , wherein the metal-insulator-metal capacitor includes a seam for facilitating stress management.3. The semiconductor device as recited in claim 1 , wherein the metal-insulator-metal capacitor includes a low-stress conductive layer to fill and seal the plurality of trenches after formation of the metal-insulator-metal capacitor.4. The semiconductor device as recited in claim 1 , wherein the metal-insulator-metal capacitor includes a first electrode claim 1 , a second electrode claim 1 , and a dielectric layer disposed between the first electrode and the second electrode.5. The semiconductor device as recited in claim 4 , wherein at least one of the first electrode or the second electrode is titanium-nitride.6. The semiconductor device as recited in claim 4 , wherein the dielectric layer is a high-k material.7. The semiconductor device as recited in claim 1 , wherein the plurality of trenches have an ...

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Номер записи: 41
11-07-2013 дата публикации

Semiconductor Devices And Methods of Manufacturing The Same

Номер: US20130175667A1
Автор: Kim Hyung-Dong, Kwon Hyung-Shin
Принадлежит:

A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability. 1. A semiconductor device comprising:lower electrodes on a substrate, each of the lower electrodes having a taller side with a height that is greater than an opposing shorter side;a supporting layer pattern disposed between the lower electrodes to support the lower electrodes, the supporting layer pattern contacting the taller sides of the lower electrodes;a dielectric layer disposed on the lower electrodes and the supporting layer pattern;an upper electrode disposed on the dielectric layer;an inter-metal dielectric layer disposed on the upper electrode; anda metal contact penetrating through the inter-metal dielectric layer and contacting with the upper electrode, a bottom portion of the metal contact being aligned above the shorter sides of the lower electrodes.2. The semiconductor device of claim 1 , further comprising:a conductive line on the substrate, the conductive line contacting a bottom portion of the lower electrodes.3. The semiconductor device of claim 1 , wherein an upper surface of the shorter side of a lower electrode aligned with the bottom portion of the metal contact is lower than a bottom ...

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Номер записи: 42
11-07-2013 дата публикации

Semiconductor Device and Method of Making Integrated Passive Devices

Номер: US20130175668A1
Автор: Cao Haijing, Chen Kang, Fang Jianmin, Lin Yaojian, Zhang Qing
Принадлежит: STATS CHIPPAC, LTD.

A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization. 1. A semiconductor device , comprising:a first substrate;an integrated passive device disposed over the first substrate;a first insulating layer disposed over the integrated passive device and first substrate;a conductive layer formed over the first insulating layer;a second insulating layer formed over the first insulating layer and conductive layer; anda second substrate disposed over the second insulating layer.2. The semiconductor device of claim 1 , wherein the first substrate includes silicon material.3. The semiconductor device of claim 1 , wherein the first substrate includes non-silicon material.4. The semiconductor device of claim 1 , wherein the first substrate is made with a material selected from the group consisting of glass claim 1 , molding compound claim 1 , epoxy claim 1 , polymer claim 1 , and polymer composite.5. The semiconductor device of claim 1 , wherein a portion of the conductive layer is wound to exhibit an inductive property.6. The semiconductor device of claim 1 , wherein ...

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Номер записи: 43
18-07-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130181270A1
Автор: ISHITSUKA Takeshi, TASHIRO Hiroko
Принадлежит: FUJITSU LIMITED

A semiconductor device includes a capacitor, the capacitor includes: a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type disposed on the first semiconductor region, the second semiconductor region having a higher first-conductivity-type impurity concentration than the first semiconductor region; a third semiconductor region of the first conductivity type disposed on the second semiconductor region, the third semiconductor region including a contact region and having a higher first-conductivity-type impurity concentration than the second semiconductor region; a dielectric film disposed on the third semiconductor region; and an upper electrode disposed on the dielectric film beside the contact region. 1. A semiconductor device comprising a capacitor , the capacitor includes:a first semiconductor region of a first conductivity type;a second semiconductor region of the first conductivity type disposed on the first semiconductor region, the second semiconductor region having a higher first-conductivity-type impurity concentration than the first semiconductor region;a third semiconductor region of the first conductivity type disposed on the second semiconductor region, the third semiconductor region including a contact region and having a higher first-conductivity-type impurity concentration than the second semiconductor region;a dielectric film disposed on the third semiconductor region; andan upper electrode disposed on the dielectric film beside the contact region.2. The semiconductor device according to claim 1 , whereinthe third semiconductor region has a first peak in a depth direction; andthe second semiconductor region has a second peak lower than the first peak in a depth direction.3. The semiconductor device according to claim 1 , wherein the upper electrode includes a first-conductivity-type semiconductor material having a higher first-conductivity-type impurity concentration than the third ...

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Номер записи: 44
18-07-2013 дата публикации

HIGH CAPACITANCE TRENCH CAPACITOR

Номер: US20130183805A1
Автор: BOOTH, Divakaruni Ramachandra, JR. ROGER A., Wong Keith Kwong Hon
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers. 1. A method of forming a structure including a capacitor structure , said method comprising:forming a trench in a substrate;forming a first conductive layer contiguously contacting a bottom surface and sidewalls of said trench;forming a first node dielectric layer contiguously contacting sidewalls of said first conductive layer;forming a second conductive layer contiguously contacting sidewalls of said first node dielectric layer;forming a second node dielectric layer contiguously contacting sidewalls of said second conductive layer; andforming a third conductive layer contiguously contacting sidewalls of said second node dielectric layer;patterning a stack of said first conductive layer, said first node dielectric layer, said second conductive layer, said second node dielectric layer, and said third conductive layer, wherein remaining portions of said first conductive layer, said first node dielectric layer, said second conductive layer, said second node dielectric layer, and said third conductive layer collectively form a capacitor structure.2. The method of claim 1 , further ...

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Номер записи: 45
25-07-2013 дата публикации

Profile Engineered Thin Film Devices and Structures

Номер: US20130189823A1
Автор: CHANDRA Aditi, KAMATH Arvind, MOLESA Steven, SCHER Erik, Smith Patrick
Принадлежит:

The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch. 1. A method of making an electrically active device , comprising:a) printing a first ink composition comprising one or more first semiconductor and/or metal precursors onto a substrate, the first ink having one or more predetermined properties;b) curing the first precursor(s) to form a first electrically active layer having a smooth, dome-shaped profile; andc) forming a second electrically active layer conformally covering the first electrically active layer.2. The method of claim 1 , wherein the one or more first precursors are present in an amount of from 1 to 40% by weight of the first ink composition.3. The method of claim 2 , wherein the one or more first precursors are selected from the group consisting of (poly)silanes claim 2 , (poly)germanes claim 2 , (poly)germasilanes claim 2 , and nanoparticles of silicon and/or germanium.4. The method of claim 3 , wherein said (poly)silanes claim 3 , ( ...

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Номер записи: 46
01-08-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130193556A1
Автор: KIM Moo-Jin, Lee Jeong-Yun
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device includes a semiconductor substrate having a capacitor region and a resistor region. A capacitor dielectric material and a capacitor electrode are sequentially stacked on an active region in the capacitor region of the semiconductor substrate. A resistor is provided on the resistor region of the semiconductor substrate. A protection pattern is provided on a top surface of the capacitor electrode. The protection pattern is spaced apart from the capacitor electrode. The protection pattern and the resistor include the same material and have the same thickness in a direction vertical to a surface of the semiconductor substrate. 1. A semiconductor device comprising:a semiconductor substrate having a capacitor region and a resistor region;a capacitor dielectric material and a capacitor electrode sequentially stacked on an active region of the capacitor region of the semiconductor substrate;a resistor on the resistor region of the semiconductor substrate; anda protection pattern on a top surface of the capacitor electrode and spaced apart from the capacitor electrode,wherein the protection pattern and the resistor include a same material and have a same thickness in a direction vertical to a surface of the semiconductor substrate.2. The semiconductor device of claim 1 , further comprising:a lower insulating layer under the protection pattern and the resistor to cover the capacitor electrode; andan upper insulating layer on the lower insulating layer to cover the protection pattern and the resistor.3. The semiconductor device of claim 2 , wherein the lower insulating layer covers a bottom surface of the protection pattern claim 2 , and top and side surfaces covered with the upper insulating layer so that the protection pattern electrically floats.4. The semiconductor device of claim 2 , wherein the lower insulating layer includes a first insulating layer claim 2 , a second insulating layer claim 2 , and a third insulating layer stacked sequentially ...

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Номер записи: 47
08-08-2013 дата публикации

METHOD OF MANUFACTURING CAPACITOR, CAPACITOR AND METHOD OF FORMING DIELECTRIC FILM FOR USE IN CAPACITOR

Номер: US20130200491A1
Автор: AKIYAMA Koji, HARADA Katsushige, HISHIYA Shingo, WAMURA Yu
Принадлежит: TOKYO ELECTRON LIMITED

Provided are a method of manufacturing a capacitor capable of achieving a high dielectric constant property and a low leakage current, a capacitor, and a method of forming a dielectric film used in the capacitor. The capacitor is fabricated by forming a lower electrode layer on a substrate; forming a first TiOfilm having an interface control function on the lower electrode layer; forming a ZrO-based film on the first TiOfilm; performing an annealing process for crystallizing ZrOin the ZrO-based film, after forming the ZrO-based film; forming a second TiOfilm which serves as a capacity film on the ZrO-based film; and forming an upper electrode layer on the second TiOfilm. 1. A method of manufacturing a capacitor , the method comprising:forming a lower electrode layer on a substrate;{'sub': '2', 'forming a first TiOfilm having an interface control function on the lower electrode layer;'}{'sub': 2', '2, 'forming a ZrO-based film on the first TiOfilm;'}{'sub': 2', '2', '2, 'performing an annealing process for crystallizing ZrOin the ZrO-based film, after forming the ZrO-based film;'}{'sub': 2', '2, 'forming a second TiOfilm which serves as a capacity film, on the ZrO-based film; and'}{'sub': '2', 'forming an upper electrode layer on the second TiOfilm.'}2. The method of claim 1 , wherein the first TiOfilm has a film thickness of about 0.2 to 1.5 nm claim 1 , the ZrO-based film has a film thickness of about 1 to 10 nm claim 1 , and the second TiOfilm has a film thickness of about 1 to 20 nm.3. The method of claim 1 , wherein the annealing process is performed under a temperature of about 300° C. to 600° C.4. The method of claim 1 , wherein the first and second TiOfilms and the ZrO-based film are formed by supplying a Ti source gas formed of a Ti compound or a Zr source gas formed of a Zr compound claim 1 , and an oxidizing agent.5. The method of claim 4 , wherein the first and second TiOfilms are formed by supplying the Ti source gas formed of the Ti compound and the ...

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Номер записи: 48
08-08-2013 дата публикации

HIGHLY SCALABLE TRENCH CAPACITOR

Номер: US20130203234A1
Автор: Cheng Kangguo, Faltermeier Johnathan E., Kimball Anne Marie
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application. 113-. (canceled)14. A method for fabricating a trench structure comprising the steps of:forming spacers on trench sidewalls on a trench within a substrate;depositing a trench conductor within the trench, whereby the trench conductor is disposed between the spacers;removing a portion of the spacers; anddepositing a non-conformal material, thereby forming a collar, said collar comprising an inner wall and an outer wall, and wherein said collar comprises a cavity, said cavity disposed between the inner wall and outer wall of said collar; andremoving a portion of the non-conformal material.15. The method of claim 14 , further comprising the step of: forming an oxide liner on the trench conductor claim 14 , and the outer wall of said collar.16. The method of claim 14 , wherein the step of forming spacers on trench sidewalls comprises the steps of:depositing an oxide within the trench; andperforming a first etch of the oxide.17. The method of claim 14 , wherein the step of depositing a non-conformal material is performed via chemical vapor deposition.18. The method of claim 14 , further comprising the step of performing a thermal anneal at a temperature ranging from about 850 degrees Centigrade to about 1000 degrees Centigrade for a duration ranging from about 10 minutes to about 1 hour.19. The method ...

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Номер записи: 49
15-08-2013 дата публикации

DIELECTRIC FILM WITH NANOPARTICLES

Номер: US20130207231A1
Автор: "OBrien Stephen", Huang Limin, Liu Shuangyi
Принадлежит: The City University of New York

A dielectric film is produced by applying a fluid solvent to a layer of nanoparticles and then polymerizing the solvent between the nanoparticles, or by disposing dielectric nanoparticles in a carrier fluid including a polymerizable substance, applying the resulting fluid to a substrate, and polymerizing a polymerizable substance between the nanoparticles so that the polymerizable substance solidifies to form the dielectric film including the solidified polymerizable substance and the nanoparticles between which the solidified polymerizable substance is disposed. A dielectric film can include nanoparticles and polymer material between at least some of the nanoparticles. The film can have a capacitance change of within 0%-7% over the range 20° C.-125° C. and a dielectric constant between 17.5 and 25 for the range 100 Hz-1 MHz. 1. A method of producing a dielectric film , the method comprising:applying a layer of dielectric nanoparticles to a substrate;applying a fluid solvent in which the nanoparticles are soluble to the layer on the substrate, so that at least some of the solvent is disposed between at least some of the nanoparticles; andpolymerizing the solvent between the nanoparticles so that the solvent solidifies to form the dielectric film including the solidified solvent and the nanoparticles between which the solidified solvent is disposed.2. The method according to claim 1 , wherein the substrate includes an electrode to which the fluid solvent is applied claim 1 , the method further including applying an electrode to a side of the dielectric film opposite the substrate after the polymerizing step so that the dielectric film is a capacitor dielectric.3. The method according to claim 2 , further including repeating the applying-layer claim 2 , applying-fluid claim 2 , polymerizing claim 2 , and applying-electrode steps to provide a multilayer dielectric structure with embedded conductors.4. The method according to claim 2 , wherein the applying-electrode ...

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Номер записи: 50
15-08-2013 дата публикации

MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM

Номер: US20130210169A1
Автор: Matsuura Katsuyoshi
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma. 1. A manufacture method for a semiconductor device comprising:forming a ferroelectric capacitor over a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited;forming a first capacitor protective film of aluminum oxide, the first capacitor protective film covering the ferroelectric capacitor;forming a seventh insulating film of silicon oxide having a thickness equal to or thicker than 300 nm over the first capacitor protective film by plasma enhanced chemical vapor deposition using tetraethoxysilane-containing gas as source gas; andforming a first insulating film of silicon oxide over the seventh insulating film by chemical vapor deposition using high density plasma.2. The manufacture method for a semiconductor device according to claim 1 , further comprising:planarizing a surface of the first insulating film;forming a second capacitor protective film of aluminum oxide over the planarized first insulating film;forming a second insulating film of silicon oxide having a thickness equal to or thicker than 300 nm over the second capacitor protective film by plasma enhanced chemical vapor deposition using tetraethoxysilane-containing gas as source gas;forming a first wiring of conductive material over the second insulating film; andforming a third insulating film of silicon oxide over the second insulating film by chemical vapor deposition using high density plasma, the third insulating ...

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Номер записи: 51
22-08-2013 дата публикации

THIN FILM TRANSISTOR, DISPLAY DEVICE HAVING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130217191A1
Автор: Jinbo Yasuhiro, KAWAE Daisuke, KOBAYASHI Satoshi, KUROKAWA Yoshiyuki, Yamazaki Shunpei
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and methods for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a pair of buffer layers formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the pair of buffer layers, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes the impurity element which serves as a donor. 1. A manufacturing method of a semiconductor device comprising the steps of:forming a first conductive film over a substrate;forming a second conductive film over the substrate;forming a first insulating film over the first conductive film and the second conductive film;forming a second insulating film over the first insulating film;forming a first opening and a recessed portion in the second insulating film by using a multi-tone photomask, wherein the first opening exposes a part of the first insulating film;forming a second opening which exposes the second conductive film by etching the part of the first insulating film;forming a third opening by widening the first opening, and a fourth opening by widening the recessed portion, wherein the fourth opening exposes another part of the first insulating film over the first conductive film; andforming an electrode over the second insulating film,wherein the electrode is electrically connected to the second conductive film through the second opening and the third opening, andwherein the ...

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Номер записи: 52
22-08-2013 дата публикации

HIGH PERFORMANCE DIELECTRIC STACK FOR DRAM CAPACITOR

Номер: US20130217202A1
Автор: Chen Hanhong, Deweerd Wim Y., Horikawa Mitsuhiro, Koyanagi Kenichi, Malhotra Sandra G., Ode Hiroyuki, Rui Xiangxin
Принадлежит:

A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. 1. A method for forming a capacitor stack , the method comprising:forming a first electrode material above a substrate, wherein the first electrode material is a metal nitride;{'sub': 2', '2, 'forming a first ZrOmaterial above the first electrode material, wherein the first ZrOmaterial further contains a first dopant, wherein the first dopant is present at a concentration of less than 10 atomic %;'}{'sub': 2', '2', '2, 'forming a second ZrOmaterial above the first ZrOmaterial, wherein the second ZrOmaterial further contains a second dopant, wherein the second dopant is present at a concentration of greater than 15 atomic %;'}{'sub': '2', 'forming a second electrode material on the second ZrOmaterial, wherein the second electrode material is a metal nitride; and'}{'sub': 2', '2, 'annealing the capacitor stack, wherein the first ZrOmaterial is equal to or greater than 30% crystalline after the annealing and the second ZrOmaterial is less than 30% crystalline after the annealing.'}2. The method of claim 1 , wherein the annealing occurs at a temperature between 400 C and 550 C.3. The method of claim 1 , wherein the first electrode material comprises one of titanium nitride or tantalum nitride4. The method of claim 1 , wherein the first dopant comprises one of Al claim 1 , Ge claim 1 , Si claim 1 , Ti claim 1 , La claim 1 , or combinations thereof.5. The method of claim 4 , wherein the first dopant comprises Al.6. The ...

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Номер записи: 53
22-08-2013 дата публикации

CAPACITOR, METHOD OF FORMING A CAPACITOR, SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20130217203A1
Автор: CHO Kyu-ho, KIM Beom-Seok, KIM Wan-don, KWON Oh-Seong, TAK Yong-Suk
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A capacitor in a semiconductor memory device comprises a lower electrode on a substrate that is formed of a conductive metal oxide having a rutile crystalline structure, a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and includes impurities for reducing a leakage current, and an upper electrode on the titanium oxide dielectric layer. A method of forming a capacitor in a semiconductor device comprise steps of forming a lower electrode on a substrate that includes a conductive metal oxide having a rutile crystalline structure, forming a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and impurities for reducing a leakage current, and forming an upper electrode on the titanium oxide dielectric layer. 1. A method of forming a capacitor in a semiconductor device , comprising steps of:forming a lower electrode on a substrate, the lower electrode including a conductive metal oxide having a rutile crystalline structure;forming a titanium oxide dielectric layer on the lower electrode, the titanium oxide dielectric layer having a rutile crystalline structure and having impurities for reducing a leakage current; andforming an upper electrode on the titanium oxide dielectric layer.2. The method of claim 1 , wherein the lower electrode is formed using ruthenium oxide by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.3. The method of claim 2 , wherein the step of forming lower electrode is performed at a temperature in a range of about 200° C. to about 400° C.4. The method of claim 1 , wherein the step of forming the lower electrode includes steps of:forming a mold layer having an opening on the substrate;forming a conductive metal oxide layer to fill the opening;planarizing the metal oxide layer to form the lower electrode in the opening; andremoving the mold layer.5. The method of claim 1 , wherein the step of forming a titanium oxide ...

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Номер записи: 54
29-08-2013 дата публикации

Analog Floating-Gate Memory Manufacturing Process Implementing N-Channel and P-Channel MOS Transistors

Номер: US20130221418A1
Автор: Allan T. Mitchell, Imran Mahmood Khan, Michael A. Wu
Принадлежит: Texas Instruments Inc

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

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Номер записи: 55
29-08-2013 дата публикации

WIRING BOARDS AND SEMICONDUCTOR MODULES INCLUDING THE SAME

Номер: US20130221485A1
Автор: Kim Seung Hwan, Kim Yonghoon, Lee Heeseok
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A wiring board includes a metal core including a first surface and a second surface facing each other and a first portion and a second portion disposed on the first and second surfaces, respectively. The first and second portions each include a plurality of insulating layers and a plurality of wiring layers stacked in an alternating manner. At least one capacitor is disposed in at least one interior region. The at least one capacitor includes first and second electrodes. The at least one interior region exposes a portion of the metal core and a portion of at least one of the first and second portions adjacent to the metal core and at least one first via electrically connects one of the wiring layers of the first portion with the first and second electrodes. 1. A wiring board , comprising:a metal core including a first surface and a second surface facing each other;a first portion and a second portion disposed on the first and second surfaces, respectively, wherein each of the first and second portions comprises a plurality of insulating layers and a plurality of wiring layers stacked in an alternating manner;at least one capacitor disposed in at least one interior region, wherein the at least one capacitor comprises a first electrode and a second electrode thicker than the metal core, and wherein the at least one interior region exposes a portion of the metal core and a portion of at least one of the first and second portions adjacent to the metal core; andat least one first via electrically connecting one of the wiring layers of the first portion with the first and second electrodes,wherein a surface of the first and second electrodes is in contact with the at least one first via.2. The wiring board of claim 1 , wherein at least one of the insulating layers of the first and second portions comprises prepreg materials.3. The wiring board of claim 1 , further comprising:at least one second via electrically connecting one of the wiring layers of the second portion ...

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Номер записи: 56
29-08-2013 дата публикации

TRANSISTOR WITH MIM (METAL-INSULATOR-METAL) CAPACITOR

Номер: US20130221486A1
Автор: Fujiwara Tsuyoshi, Ishii Yukino, KATSUYAMA Kiyomi, Maeno Ryohei, Matsumoto Daichi, Otaguro Akira, SATO Hidenori, SATO Kiyohiko
Принадлежит: Hitachi, Ltd.

The orientation polarization (positive and negative) of the Si—N bonds and the Si—O bonds is canceled, thereby enabling to minimize the polarization in a capacitive insulating film. As a result, a silicon oxynitride film with a small voltage secondary coefficient is formed, and is applied as a capacitive insulating film for use in a MIM capacitor. Specifically, the refractive index of the silicon oxynitride film satisfies 1.47≦n≦1.53, for light with a wavelength of 633 nm. 1. A transistor with a MIM (Metal-Insulator-Metal) capacitor comprising:a lower electrode;an upper electrode, anda capacitive insulating film which is arranged between the lower electrode and the upper electrode,wherein the capacitive insulating film is a silicon oxynitride film whose composition ratios measured using an XPS (X-ray Photoemission Spectroscopy) technique are 0.024≦N/(Si ratio)≦0.22 and 1.74≦O/(Si ratio)≦2.1.2. The transistor according to claim 1 , wherein a first wiring layer is formed in a same layer as the lower electrode of the MIM capacitor.3. The semiconductor device according to claim 2 ,wherein the upper electrode of the MIM capacitor has a protective film and a laminated metal film,wherein a second wiring layer is formed in a same layer as the laminated metal film, andwherein the second wiring layer is positioned in an upper layer of the first wiring layer.4. The transistor according to claim 3 , wherein a trench reaching the lower electrode is formed in an interlayer insulating film which is formed between the first wiring layer and the second wiring layer.5. The transistor according to claim 3 , wherein the protective film and the laminated metal film are electrically connected with each other through a conductive plug.6. A transistor with a MIM (Metal-Insulator-Metal) capacitor comprising:a lower electrode;an upper electrode; anda capacitive insulating film which is arranged between the lower electrode and the upper electrode,wherein the capacitive insulating film is a ...

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Номер записи: 57
29-08-2013 дата публикации

HAFNIUM TANTALUM TITANIUM OXIDE FILMS

Номер: US20130224916A1
Автор: Ahn Kie Y., Forbes Leonard
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition. 1. A method for forming a transistor , the method comprising:forming a source region in a substrate;forming a drain region in the substrate;forming a dielectric on the substrate, with a reaction sequence atomic layer deposition process, the dielectric including a hafnium tantalum titanium oxide, a hafnium oxide, a tantalum oxide, and a titanium oxide as separate entities; andforming a gate above the dielectric.2. The transistor of claim 1 , wherein forming the dielectric includes a dielectric nitride.3. The transistor of claim 1 , wherein forming the dielectric includes forming an insulating metal oxide layer claim 1 , whose metal is different from hafnium claim 1 , tantalum and titanium.4. The transistor of claim 1 , further comprising forming an interfacial material between the substrate and the dielectric.5. The transistor of claim 4 , wherein forming the interfacial material comprises forming the interfacial layer to a thickness that is less than the dielectric.6. The transistor of claim 1 , wherein forming the dielectric comprises forming a tunnel oxide contacting a channel and a floating gate in the transistor.7. The transistor of claim 1 , wherein forming the dielectric comprises forming a floating gate dielectric contacting a floating gate and the gate in the transistor.8. A method for forming a transistor claim 1 , the method comprising:forming a source region in a substrate;forming a drain region in the substrate;forming a dielectric on the substrate with a reaction sequence atomic layer deposition process, the process including doping a hafnium tantalum titanium oxide with a metal or a compound of two or ...

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Номер записи: 58
05-09-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130228837A1
Автор: MATSUI Takayuki, SUKEKAWA MITSUNARI
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device according to this invention includes a support film that supports a lower electrode of a capacitor at an upper portion, and the support film includes a first insulating material having a stress within a range of +700 MPa to −700 MPa. Use of such a support film prevents a phenomenon in which the capacitor lower electrode is twisted. Preferably, the support film has a rate etched by hydrofluoric acid of 1.0 nm/sec or less and more preferably, the support film includes a silicon carbon nitride film. 1. A semiconductor device comprising:a capacitor; anda support film that supports the capacitor, the support film comprising a first insulating material having a stress within a range of +700 MPa to −700 MPa.2. The semiconductor device according to claim 1 , wherein the first insulating material has an etch rate relative to hydrofluoric acid of 1 nm/sec or less.3. The semiconductor device according to claim 1 , wherein the first insulating material comprises silicon carbon nitride.4. The semiconductor device according to claim 3 , wherein the capacitor is a cylindrical capacitor that includes a lower electrode having a cylindrical shape claim 3 , a capacitor dielectric film formed on inner and outer walls of the lower electrode claim 3 , and an upper electrode formed on the capacitor dielectric film claim 3 , and the support film is in contact with the outer wall of the lower electrode.5. The semiconductor device according to claim 4 , wherein the semiconductor device comprises a memory cell region in which a plurality of the capacitors is arranged in an array and a peripheral circuit region that is arranged around the memory cell region claim 4 , and the support film covers a whole of the memory cell region.6. The semiconductor device according to claim 5 , wherein the support film has openings near the peripheral circuit region.7. The semiconductor device according to claim 5 , wherein the lower electrode comprises a first titanium nitride film and ...

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Номер записи: 59
05-09-2013 дата публикации

PACKAGE SUBSTRATE AND SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE

Номер: US20130228895A1
Автор: IGUCHI Daisuke
Принадлежит: FUJI XEROX CO., LTD.

A semiconductor package includes a semiconductor element, a capacitor, and a package substrate. The capacitor supplies transient current to the semiconductor element. The semiconductor element and the capacitor are mounted on the package substrate. The semiconductor element includes an integrated circuit, a first connecting part, and a second connecting part. The capacitor includes a third connecting part and a fourth connecting part. The package substrate includes a first metallic layer, a second metallic layer, and a dielectric layer. The first metallic layer includes a first conductive region, a second conductive region, a third conductive region, and a fourth conductive region. The first conductive region is connected via a fifth connecting part to the second metallic layer. The third conductive region is connected via a sixth connecting part to the second metallic layer. The second and fourth conductive regions are connected to each other inside the first metallic layer. 1. A semiconductor package comprising:a semiconductor element;a capacitor that supplies transient current to the semiconductor element; anda package substrate on which the semiconductor element and the capacitor are mounted, an integrated circuit,', 'a first connecting part that connects the integrated circuit to one of an external power supply potential and an external reference potential, and', 'a second connecting part that connects the integrated circuit to the other one of the power supply potential and the reference potential,, 'wherein the semiconductor element includes'} a third connecting part that is connected to one of the power supply potential and the reference potential, and', 'a fourth connecting part that is connected to the other one of the power supply potential and the reference potential,, 'wherein the capacitor includes'} a first metallic layer,', 'a second metallic layer, and', 'a dielectric layer that is arranged between the first metallic layer and the second metallic ...

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Номер записи: 60
05-09-2013 дата публикации

Semiconductor memory devices and methods of forming the same

Номер: US20130230961A1
Автор: Byoung-Yong Gwak, Hyong-Soo Kim, Kukhan Yoon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes.

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Номер записи: 61
12-09-2013 дата публикации

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Номер: US20130234289A1
Автор: Hashimoto Takashi, Ishii Yasushi, Kawashima Yoshiyuki, Matsui Toshikazu, TOBA Koichi
Принадлежит: RENESAS ELECTRONICS CORPORATION

In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode. 119-. (canceled)20. A semiconductor device comprising:(a) a semiconductor substrate;(b) a capacitor element formed over the substrate,the capacitor element (b) including:(b1) a lower electrode formed over the substrate,(b2) a capacitor insulating film formed over the lower electrode, and(b3) an upper electrode formed over the capacitor insulating film,wherein the upper electrode has a first electrode portion, a second electrode portion and a third electrode portion,wherein the first electrode portion is formed so as to extend in a first direction along a surface of the semiconductor substrate,wherein the second electrode portion is formed so as to extend along a direction perpendicular to the surface of the semiconductor substrate, andwherein the third electrode portion is formed above the lower electrode and extends in the first direction;(c) a plurality of first metal silicide films formed over a surface of the upper electrode,wherein the plurality of first metal silicide films include a first silicide portion formed on the third electrode portion and a second silicide portion formed on ...

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Номер записи: 62
12-09-2013 дата публикации

METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY

Номер: US20130234290A1
Автор: Doyle Brian, Jong Lana, Keating Steven, Lindert Nick, RAHHAL-ORABI NADIA, Sha Lin, Sivakumar Swaminathan, Suri Satyarth
Принадлежит:

A method of patterning a metal () on a vertical sidewall () of an excavated feature () includes placing a material () in the excavated feature such that a portion () of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor () suitable for an eDRAM device. 1. An embedded memory device comprising:a first electrically conductive layer formed from a first metal;a first electrically insulating layer over the first electrically conductive layer;an excavated feature in the first electrically insulating layer that extends to the first electrically conductive layer; and a second electrically conductive layer located in the excavated feature adjacent to and electrically connected to the first electrically conductive layer;', 'a second electrically insulating layer located in the excavated feature interior to the second electrically conductive layer; and', 'a third electrically conductive layer located in the excavated feature interior to the second electrically insulating layer,, 'a MIM capacitor in the excavated feature, the MIM capacitor comprising the first electrically conductive layer acts as a floor of the excavated feature and the excavated feature further comprises sidewalls extending away from the floor;', 'the second electrically conductive layer covers the floor and a first portion of the sidewalls;', 'the second electrically insulating layer covers the second electrically conductive layer and a second portion of the sidewalls; and', 'the third electrically conductive layer is formed from the first metal., 'wherein2. The embedded memory device of wherein:the first metal is copper.3. The embedded memory device of wherein:the second electrically insulating layer is a conformal ...

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Номер записи: 63
12-09-2013 дата публикации

SEMICONDUCTOR CERAMIC AND METHOD FOR MANUFACTURING THE SAME, AND LAMINATED SEMICONDUCTOR CERAMIC CAPACITOR WITH VARISTOR FUNCTION AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130234293A1
Автор: Kawamoto Mitsutoshi
Принадлежит: MURATA MANUFACTURING CO., LTD.

A semiconductor ceramic contains a donor element solid-solved in crystal grains of a SrTiO-based compound, and an acceptor element in a grain boundary layer. The number of tetravalent acceptor elements is 1×10/g or more, as determined from an electron spin resonance absorption spectrum. A mixture of a calcined powder and an acceptor compound is pulverized to a specific surface area of 5.0 to 7.5 m/g before mixing with a binder. Semiconductor ceramic layers having a varistor function are formed by using the semiconductor ceramic forming a highly reliable capacitor which can suppress characteristics variations to stably obtain good electrical characteristics. 1. A semiconductor grain boundary insulated semiconductor ceramic comprising a principal component which is a SrTiO-based compound , a donor element solid-solved in crystal grains , and an acceptor element present in a grain boundary layer , and in which the number of tetravalent acceptor elements per unit weight (g) is 1×10/g or more.2. The semiconductor ceramic according to claim 1 , where the number of the tetravalent acceptor elements per unit weight (g) is 2.8×10/g or more.3. The semiconductor ceramic according to claim 1 , where the acceptor element is at least one element selected from the group consisting of Mn claim 1 , Co claim 1 , Ni claim 1 , and Cr.4. The semiconductor ceramic according to claim 3 , wherein compounding molar ratio m of Sr site to Ti site is 0.990≦m≦1.010 claim 3 , and the content of the acceptor element is greater than 0 mol to 0.7 mol or less with respect to 100 mol of the Ti element.5. The semiconductor ceramic according to claim 4 , wherein the acceptor element amount of 0.3 to 0.5 mol with respect to 100 mol of the Ti element.6. The semiconductor ceramic according to claim 5 , wherein the donor element is at least one element selected from the group consisting of La claim 5 , Nd claim 5 , Sm claim 5 , Dy claim 5 , Nb claim 5 , and Ta.7. The semiconductor ceramic according to ...

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Номер записи: 64
12-09-2013 дата публикации

METAL-INSULATOR-METAL (MIM) DEVICE AND METHOD OF FORMATION THEREOF

Номер: US20130237030A1
Автор: AVANZINO Steven, FANG Tzu-Ning, HADDAD Sameer, KAZA Swaroop, LIAO Dongxiang, Lo Wai, MARRIAN Christie
Принадлежит: SPANSION LLC

In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening. 1. A method of fabricating a metal-insulator-metal (MIM) device comprising:providing a first electrode;providing a protective layer on the first electrode;providing an opening through the protective layer to expose a portion of the first electrode;oxidizing a portion of the first electrode;providing an oxidizable layer on the oxidized portion of the first electrode;oxidizing the oxidizable layer; andproviding a second electrode in contact with the oxidized layer.2. The method of wherein the second electrode extends above the protective layer.3. The method of fabricating a metal-insulator-metal (MIM) device comprising:providing a first electrode;providing an oxide layer on the first electrode;providing a protective layer on the oxide layer;providing an opening through the protective layer to expose a portion of the oxide layer;oxidizing a portion of the first electrode underlying the exposed portion of the oxide layer; andproviding a second electrode in contact with the exposed portion of the oxide layer.4. The method of wherein the oxide layer is grown on the first electrode.5. The method of wherein the second electrode extends above the protective layer.6. The method of and further comprising the step of providing a spacer of insulating material on a wall of the opening in the protective layer prior to oxidizing a portion of the first ...

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Номер записи: 65
19-09-2013 дата публикации

Strained Channel Dynamic Random Access Memory Devices

Номер: US20130241035A1
Автор: Bulsara Mayank T., Currie Matthew T., Lochtefeld Anthony J.
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined. 1. A structure comprising:a substrate comprising a first region and a second region, the second region comprising a strained semiconductor material over a semiconductor substrate;a capacitor disposed in a trench in the first region of the substrate, the capacitor comprising a first conductive region along a sidewall of the trench, an insulator along the first conductive region, and a second conductive region along the insulator; anda device in the second region of the substrate, at least a portion of the device comprising a portion of the strained semiconductor material, the device being electrically coupled to the capacitor.2. The structure of claim 1 , wherein the second region comprises a relaxed semiconductor material disposed between the strained semiconductor material and the semiconductor substrate claim 1 , and wherein the first region of the substrate is free from the strained semiconductor material and is free from the relaxed semiconductor material.3. The structure of claim 2 , wherein the relaxed semiconductor material directly adjoins the semiconductor substrate.4. The structure of claim 2 , wherein the second region comprises a graded semiconductor material claim 2 , the graded semiconductor material being disposed between the relaxed semiconductor material and the semiconductor substrate.5. The structure of claim 2 , wherein the trench is disposed wholly in the semiconductor substrate in the first region of the substrate.6. The structure of claim 1 , wherein the first region comprises the strained semiconductor material over the semiconductor substrate claim 1 , and the first region and the second region comprise a relaxed semiconductor material disposed between the strained semiconductor material and the semiconductor substrate.7. The structure of claim 6 , wherein the relaxed semiconductor ...

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Номер записи: 66
26-09-2013 дата публикации

MEMORY DEVICES WITH VERTICAL STORAGE NODE BRACING AND METHODS OF FABRICATING THE SAME

Номер: US20130249053A1
Автор: LEE Junghwan
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A memory device includes a substrate and a plurality of vertical storage nodes linearly spaced apart on the substrate along a first direction. The device further includes at least one support pattern abutting sidewalls of the storage nodes, the at least one support pattern having portions that bridge first pairs of adjacent ones of the storage nodes and openings therein that separate second pairs of adjacent ones of the storage nodes. First distances between the storage nodes of the respective first pairs may be greater than second distances between the storage nodes of the respective second pairs. Methods of fabricating such devices are also described. 1. A memory device , comprising:a substrate;a plurality of vertical storage nodes linearly spaced apart on the substrate along a first direction; andat least one support pattern abutting sidewalls of the storage nodes, the at least one support pattern having portions that bridge first pairs of adjacent ones of the storage nodes and openings therein that separate second pairs of adjacent ones of the storage nodes.2. The device of claim 1 , wherein first distances between the storage nodes of the respective first pairs are greater than second distances between the storage nodes of the respective second pairs.3. The device of claim 1 , wherein the at least one support pattern comprises a plurality of parallel elongate strips extending along a second direction transverse to the first direction.4. The device of claim 1 , wherein the at least one support pattern comprises a mesh claim 1 , and wherein the openings comprise openings spaced apart along a second direction transverse to the first direction.5. The device of claim 1 , wherein the at least one support pattern comprises a first support pattern positioned at a first height above the substrate and a second support pattern positioned at a second height above the substrate.6. The device of claim 5 , wherein a top surface of the second support pattern is coplanar with ...

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Номер записи: 67
03-10-2013 дата публикации

CAPACITOR AND METHOD FOR FORMING THE SAME

Номер: US20130256837A1
Автор: Shin Dong Won
Принадлежит: Dongbu HiTek Co., Ltd.

A capacitor and a method of forming a capacitor including forming a first conductive layer, a dielectric film, a second conductive layer, and a hard mask on and/or over a substrate, forming a hard mask pattern and an upper electrode each having a sloped sidewall by etching the hard mask and the first conductive layer, forming a spacer on and/or over the sidewall of each of the hard mask pattern and the upper electrode, and forming a lower electrode by etching the dielectric film and the second conductive layer. 1. A method of forming a capacitor , the method comprising:forming a first conductive layer, a dielectric film, a second conductive layer, and a hard mask over a substrate;forming a hard mask pattern and an upper electrode each having a sloped sidewall by etching the hard mask and the second conductive layer;forming a spacer over the sidewall of each of the hard mask pattern and the upper electrode; andforming a lower electrode by etching the dielectric film and the first conductive layer.2. The method of claim 1 , wherein the sloped sidewall of each of the hard mask pattern claim 1 , and the upper electrode is sloped at an angle of 45°˜85°.3. The method of claim 1 , wherein forming the lower electrode by etching the dielectric film and the first conductive layer comprises:removing the dielectric film by using the hard mask pattern and the spacer as an etch mask to expose the first conductive layer, and forming the lower electrode by selectively removing the exposed first conductive layer.4. The method of claim 1 , wherein the forming the hard mask pattern and the upper electrode each having a sloped sidewall by etching the hard mask and the second conductive layer comprises:{'sub': 4', '4', '8', '5', '8, 'using CFgas added with CFgas or CFgas as etch gas in the formation of the hard mask pattern and the upper electrode each having the sloped sidewall.'}5. The method of claim 1 , wherein the forming the spacer comprises:forming an insulating film over the ...

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Номер записи: 68
03-10-2013 дата публикации

METHODS OF FORMING CAPACITORS AND SEMICONDUCTOR DEVICES INCLUDING A RUTILE TITANIUM DIOXIDE MATERIAL

Номер: US20130260529A1
Автор: Antonov Vassil, Bhat Vishwanath, CARLSON Chris, Hsieh Chun-I, Huang Tsai-Yu
Принадлежит: MICRON TECHNOLOGY, INC.

Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material. 1. A method of foiming a capacitor , comprising:forming at least one aperture in a support material;forming a titanium nitride material within the at least one aperture;forming a ruthenium material within the at least one aperture over the titanium nitride material;forming a first conductive material over the ruthenium material within the at least one aperture;removing the support material;oxidizing the titanium nitride material to form a titanium dioxide material; andforming a second conductive material over an outer surface of the titanium dioxide material.2. The method of claim 1 , wherein oxidizing the titanium nitride material to form a titanium dioxide material comprises forming a rutile titanium dioxide material.3. The method of claim 2 , wherein forming a rutile titanium dioxide material comprises oxidizing a portion of the ruthenium material to foim a ruthenium oxide material and forming the rutile titanium dioxide material on the ruthenium oxide material.4. The method of claim 1 , further comprising laterally supporting at least a portion of an open end of the titanium nitride material claim 1 , the ruthenium material and the first conductive material with a dielectric material.5. The method of claim 4 , wherein removing the support material comprises:forming at least one aperture in the dielectric material and exposing the support material through the at least one ...

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Номер записи: 69
03-10-2013 дата публикации

MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY

Номер: US20130260530A1
Автор: HSU Louis L., Ouyang Xu, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage. 1. A method of manufacturing a semiconductor structure , said method comprising:forming at least one switching device on a semiconductor substrate;forming at least one capacitor-side via structure contacting one node of said at least one switching device; andforming at least one capacitor, each of said at least one capacitor comprising at least three conductive plates and at least one node dielectric on said semiconductor substrate, wherein said at least three conductive plates vertically overlie or underlie one another and are separated from one another by said at least one node dielectric, and a laterally protruding portion of one of said at least three conductive plates contacts said at least one capacitor-side via structure, wherein said at least three conductive plates and at least one node dielectric are components of a capacitor module.2. The method of claim 1 , further comprising:forming at least one power-supply-side via structure contacting another node of said at least one switching device; andforming a power-supply-side plate contacting said at least one power-supply-side via structure.3. The method of claim 1 , further comprising:forming a first conductive plate over said semiconductor substrate;forming a ...

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Номер записи: 70
10-10-2013 дата публикации

COBALT TITANIUM OXIDE DIELECTRIC FILMS

Номер: US20130264625A1
Автор: Ahn Kie Y., Forbes Leonard
Принадлежит:

Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition. 120-. (canceled)21. A method comprising: pulsing a cobalt-containing precursor;', 'pulsing a titanium-containing precursor; and', 'performing a removal process between pulsing the cobalt-containing precursor and pulsing the titanium-containing precursor such that a gas containing cobalt is not present when pulsing the titanium-containing precursor and a gas containing titanium is not present when pulsing the cobalt-containing precursor., 'forming cobalt titanium oxide by a monolayer or partial monolayer sequencing process including22. The method of claim 21 , wherein forming the cobalt titanium oxide includes forming a dielectric stack including the cobalt titanium oxide.23. The method of claim 22 , wherein forming the dielectric stack includes forming an insulating nitride claim 22 , an insulating metal oxide claim 22 , or a combination of an insulating nitride and an insulating metal oxide.24. The method of claim 22 , wherein forming the dielectric stack includes forming silicon oxide.25. The method of claim 24 , wherein forming the silicon oxide includes arranging the silicon oxide in the dielectric stack such that the silicon oxide operatively provides a charge storage region.26. The method of claim 22 , wherein forming the dielectric stack includes forming the dielectric stack structured as a nanolaminate.27. The method of claim 21 , wherein the method includes doping the cobalt titanium oxide with an element or a compound other than cobalt claim 21 , titanium claim 21 , and oxygen.28. The method of claim 21 , wherein forming the cobalt titanium oxide includes forming the cobalt titanium oxide on a substrate with the ...

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Номер записи: 71
17-10-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130270672A1
Автор: HWANG Chan-Seung, Lim Jun-Hee
Принадлежит:

A semiconductor device is provided. The semiconductor device includes first and second storage electrodes formed to be spaced apart from each other on a substrate, an insulating continuous support pattern connected to top surfaces of the first and second storage electrodes, a storage dielectric layer formed to cover the first and second storage electrodes and the continuous support pattern, and a plate electrode formed on the storage dielectric layer. The continuous support pattern includes a first contact part connected to the top surface of the first storage electrode, a second contact part connected to the top surface of the second storage electrode, and a connection part connecting the first and second contact parts with each other. 1. A semiconductor device comprising:first and second storage electrodes formed to be spaced apart from each other on a substrate;an insulating continuous support pattern connected to top surfaces of the first and second storage electrodes;a storage dielectric layer formed on the first and second storage electrodes and the continuous support pattern; anda plate electrode formed on the storage dielectric layer,wherein the continuous support pattern includes a first contact part connected to the top surface of the first storage electrode, a second contact part connected to the top surface of the second storage electrode, and a connection part connecting the first and second contact parts with each other.2. The semiconductor device according to claim 1 , wherein at least one of the first contact part or the second contact part of the continuous support pattern has a vertical thickness greater than a horizontal width.3. The semiconductor device according to claim 1 , wherein the first contact part of the continuous support pattern includes an extension part which covers the top surface of the first storage electrode and extends to a side of the first storage electrode.4. The semiconductor device according to claim 3 , wherein the ...

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Номер записи: 72
17-10-2013 дата публикации

ON-CHIP CAPACITOR STRUCTURE

Номер: US20130270674A1
Автор: DARABI HOOMAN, Li Qiang, ZHANG BO
Принадлежит:

At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit. 123-. (canceled)24. An apparatus comprising:a first metal-oxide-semiconductor (MOS) capacitor formed on a semiconductor substrate and connected to a first differential node;a second MOS capacitor formed on the semiconductor substrate and connected to a second differential node; anda first metal-insulator-metal (MIM) capacitor connected between the first differential node and the second differential node and formed at least partially above the first MOS capacitor.25. The apparatus of claim 24 , wherein at least one layer of the first MOS capacitor comprises aluminum.26. The apparatus of claim 24 , wherein at least one layer of the first MOS capacitor comprises copper.27. The apparatus of claim 24 , wherein the first MOS capacitor comprises a first complementary metal-oxide semiconductor (CMOS) capacitor and the second MOS capacitor comprises a second CMOS capacitor.28. The apparatus of claim 24 , wherein the first and second MOS capacitors are formed within a well of the semiconductor substrate.29. The apparatus of claim 24 , wherein the first and second MOS capacitors are formed within an N-type well of the semiconductor substrate.30. The apparatus of claim 24 , wherein the first MIM capacitor ...

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Номер записи: 73
17-10-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130270677A1
Автор: Otsuka Keisuke, Tomoyama Tsuyoshi
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device includes a semiconductor substrate having a principal surface, a first conductor formed on the semiconductor substrate and including a conductive film having a first side wall portion and a first bottom surface portion both of which are continuously formed on a first trench having a first width in a direction parallel to the principal surface, and a second conductor formed on the semiconductor substrate and including a conductive film having a second side wall portion and a second bottom surface portion both of which are continuously formed on a second trench having a second width in a direction parallel to the principal surface, the second width being larger than the first width. 13-. (canceled)4. A semiconductor device comprising:a semiconductor substrate having a principal surface;a first conductor formed over the semiconductor substrate, the first conductor including first side wall portions in opposition to each other at a separation of a first distance in a horizontal direction and a first bottom portion continuously formed to connect between the first side wall portions;a second conductor formed over the semiconductor substrate, the second conductor including second side wall portions in opposition to each other at a separation of a second distance in a horizontal direction and a second bottom portion continuously formed to connect between the second side wall portions, the second distance being larger than the first distance;a third conductor formed at least over outer surfaces of both sides of the first side wall portions of the first conductor through a dielectric layer; anda fourth conductor formed at least over outer surfaces of both sides of the second side wall portions of the second conductor through a dielectric layer,wherein one of top ends of the first side wall portions is located at a position lower than the other of the top ends of the first side wall portions.5. The semiconductor device according to claim 4 , wherein the ...

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Номер записи: 74
24-10-2013 дата публикации

POWER SEMICONDUCTOR MODULE

Номер: US20130277800A1
Автор: HORI Motohito, IKEDA Yoshinari, YAMADA Takafumi
Принадлежит: FUJI ELECTRIC CO., LTD.

Embodiments of the invention provide a power semiconductor module wherein it is possible to reduce switching noise generated in a switching element, and at the same time, to reduce thermal resistance between a power semiconductor chip and an insulating substrate. In some embodiments, by a capacitor being installed between a printed substrate and an insulating substrate so as to be adjacent to a power semiconductor chip which is a switching element, it is possible to reduce switching noise generated in the switching element, and furthermore, it is possible to reduce thermal resistance between the power semiconductor chip and insulating substrate. 1. A power semiconductor module , comprising an upper substrate and a lower substrate on the top of which a power semiconductor chip is mounted , whereinthe power semiconductor chip and upper substrate are connected by conductors, and a capacitor connected in parallel circuit-wise to a power semiconductor corresponding to the power semiconductor chip connects the upper substrate and lower substrate.2. The power semiconductor module according to claim 1 , whereinthe capacitor is formed of a plurality of capacitors connected in parallel.3. The power semiconductor module according to claim 1 , whereinthe distance between the power semiconductor chip and capacitor is 0.3 mm or more and 10 mm or less.4. The power semiconductor module according to claim 1 , whereinthe thermal resistance of a path from the top of the power semiconductor chip via the conductors, upper substrate, and capacitor to the bottom of the lower substrate is 0.3° C./W or less.5. The power semiconductor module according to claim 1 , whereinthe capacitance of the capacitor is from 10 pF to 1 μF.6. The power semiconductor module according to claim 2 , whereinthe combined capacitance of the plurality of capacitors is from 10 pF to 1 μF.7. The power semiconductor module according to claim 1 , whereinthe upper substrate is a printed substrate, the lower substrate ...

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Номер записи: 75
24-10-2013 дата публикации

INTEGRATED CIRCUIT DEVICES WITH CAPACITOR AND METHODS OF MANUFACTURING THE SAME

Номер: US20130277802A1
Автор: Kang Mansug, KIM Hyongsoo, PARK Dongkyun, Park Sangjun, Yoon Kukhan
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An integrated circuit device with capacitors and methods of forming the integrated circuit device are provided. The methods may include forming a first lower capacitor electrode pattern on an inner surface of a hole in a mold layer. The first lower capacitor electrode pattern may have a hollow cylindrical shape and an opening in an upper surface. The method may further include forming a second lower capacitor electrode pattern plugging the opening and an upper surface of the second lower capacitor electrode pattern may be planar. The first and the second lower capacitor electrode patterns may comprise a lower capacitor electrode including a void. Additionally, the method may include removing the mold layer to expose the lower capacitor electrode, forming a dielectric layer on the lower capacitor electrode, and forming an upper capacitor electrode layer on the dielectric layer. 1. A semiconductor device , comprising:lower electrodes provided on a substrate to define a seam formed therein;a dielectric conformally covering the lower electrodes; andan upper electrode covering the dielectric,wherein a central portion of a top surface of the lower electrode is substantially coplanar with or higher than an edge portion thereof.2. The device of claim 1 , wherein each of the lower electrodes comprises a first lower electrode pattern defining a side surface of the seam a second lower electrode pattern defining a top surface of the seam claim 1 ,the first lower electrode pattern covers a side surface of the second lower electrode pattern, andtop surfaces of the first and second lower electrode patterns are in contact with the dielectric.3. The device of claim 1 , wherein each of the lower electrodes comprises a first lower electrode pattern having a hollow structure and a second lower electrode pattern provided in the first lower electrode pattern to define the seam claim 1 ,the first lower electrode pattern covers a side surface of the second lower electrode pattern, andtop ...

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Номер записи: 76
24-10-2013 дата публикации

CONNECTION STRUCTURE FOR AN INTEGRATED CIRCUIT WITH CAPACITIVE FUNCTION

Номер: US20130277803A1
Автор: PAGANI Alberto
Принадлежит: STMICROELECTRONICS S.R.L.

An embodiment, in a single structure, combines a pad including a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside of the chip itself and at least one capacitor. By combining a connection pad and a capacitor in a single structure, it may be possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the capacitor itself. In this way, the costs and size of the chip can be reduced. 110-. (canceled)11. A terminal structure , comprising:a pad forming an electrode of a first capacitor; anda first conductor disposed adjacent to the pad and forming another electrode of the capacitor.12. The terminal structure of wherein the first conductor is parallel to the pad.13. The terminal structure of claim 11 , further including:a second conductor electrically coupled to the pad and extending from the pad toward the first conductor; anda third conductor electrically coupled to the first conductor, extending from the first conductor toward the pad, and laterally adjacent to the second conductor.14. The terminal structure of claim 11 , further including:a second conductor electrically coupled to the pad and extending from the pad toward the first conductor;a third conductor electrically coupled to the first conductor, extending from the first conductor toward the pad, and laterally adjacent to the second conductor; anda fourth conductor electrically coupled to one of the pad and first conductors, extending from the one of the pad and first conductors to the other of the pad and first conductors, and laterally adjacent to at least one of the second and third conductors.15. The terminal structure of claim 11 , further including a second conductor electrically coupled to the pad claim 11 , disposed at a same level as the first conductor claim 11 , and galvanically isolated from the first conductor.16. The terminal structure of claim 11 , further including a ...

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Номер записи: 77
24-10-2013 дата публикации

ETCHSTOP LAYERS AND CAPACITORS

Номер: US20130279102A1
Автор: Brain Ruth A.
Принадлежит:

Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures. 1. A semiconductor device comprising ,a substrate having at least one dielectric layer disposed on the substrate surface.{'sup': '3', 'the dielectric layer having a first dielectric etchstop layer and a second etchstop layer disposed thereon, wherein the second etchstop layer has a density that is greater than the first etchstop layer and a density that is greater than 3 g/cm,'}a well formed through the first and second etchstop layers and in the at least one dielectric layer, wherein the well comprises sidewalls and a bottom, and a first layer of conducting material is disposed on the sidewalls and bottom of the well, an insulating layer disposed on the first layer of conducting material, and a second layer of conducting material disposed on the first layer of conducting material.2. The device of wherein the density of the second etchstop layer is in the range of 4 to 10 g/cm.3. The device of wherein the first layer of conducting material is recessed relative to the sidewalls of the well.4. The device of wherein the substrate comprises at least two dielectric layers claim 1 , the dielectric layers are separated by an etchstop layer claim 1 , and the second dielectric layer comprises a metal-filled trench or via that makes electrical contact claim 1 , with the first layer of conducting material.5. The device of wherein the metal-filled trench or via is in electrical contact with a transistor structure.6. The device of wherein the first dielectric etchstop layer is comprised of a dielectric material that is comprised of at least 95% silicon claim 1 , carbon claim 1 , nitrogen ...

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Номер записи: 78
24-10-2013 дата публикации

ENHANCED DEVICE RELIABILITY OF A SEMICONDUCTOR DEVICE BY PROVIDING SUPERIOR PROCESS CONDITIONS IN HIGH-K FILM GROWTH

Номер: US20130280873A1
Автор: Carter Richard, Erben Elke, Grass Carsten, Trentzsch Martin
Принадлежит: GLOBALFOUNDRIES INC.

When forming sophisticated circuit elements, such as transistors, capacitors and the like, using a combination of a conventional dielectric material and a high-k dielectric material, superior performance and reliability may be achieved by forming a hafnium oxide-based high-k dielectric material on a conventional dielectric layer with a preceding surface treatment, for instance using APM at room temperature. In this manner, sophisticated transistors of superior performance and with improved uniformity of threshold voltage characteristics may be obtained, while also premature failure due to dielectric breakdown, hot carrier injection and the like may be reduced. 1. A method , comprising:forming a first dielectric layer on a semiconductor region of a semiconductor device;performing a surface treatment on said first dielectric layer by using a mixture of ammonium hydroxide and hydrogen peroxide so as to prepare a surface of said first dielectric layer for a subsequent deposition of a second dielectric layer based on hafnium oxide; andforming said second dielectric layer on said prepared surface by applying a cyclic deposition process.2. The method of claim 1 , wherein forming said first dielectric layer comprises forming a silicon and oxygen-containing dielectric material on said semiconductor region.3. The method of claim 1 , wherein forming said second dielectric layer comprises performing said cyclic deposition process on the basis of substantially silicon-free precursor gases.4. The method of claim 1 , wherein performing said surface treatment comprises selecting a process temperature to be in the range of 10-40° C.5. The method of claim 4 , wherein said process temperature is selected to be in the range of 15-30° C.6. The method of claim 1 , wherein applying said cyclic deposition process comprises repeating a sequence of process steps including exposing said prepared surface to a hafnium-containing precursor and an oxidant-containing precursor with an intermediate ...

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Номер записи: 79
24-10-2013 дата публикации

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

Номер: US20130280881A1
Автор: KIM Weon-Hong, PARK Jung-Min, SONG Min-Woo
Принадлежит:

A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer. 17.-. (canceled)8. A method of fabricating a semiconductor device , the method comprising:providing a substrate;forming a bottom electrode on the substrate;forming a first dielectric layer on the bottom electrode such that the first dielectric layer includes a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb;forming a second dielectric layer on the first dielectric layer such that the second dielectric layer includes a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb and the first metal oxide and the second metal oxide include different materials;forming a third dielectric layer on the second dielectric layer such that the third dielectric layer includes a metal carbon oxynitride; andforming an upper electrode on the third dielectric layer.9. The method as claimed in claim 8 , wherein forming the third dielectric layer includes:providing a metal precursor to the substrate including the second dielectric layer such that the metal precursor is adsorbed on the second dielectric layer,supplying a first purge gas to remove un-adsorbed metal precursor,supplying an oxidation gas,supplying a second purge gas to remove un-reacted oxidation gas,performing a plasma treatment while nitridation gas is supplied, andsupplying a third purge gas to ...

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Номер записи: 80
31-10-2013 дата публикации

Semiconductor Module With a Semiconductor Chip and a Passive Component and Method for Producing the Same

Номер: US20130285132A1
Автор: Otremba Ralf
Принадлежит:

A semiconductor module includes a semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side one or more contacts, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the contacts. The electrode of the passive component is electrically connected with one of the contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the semiconductor chip or an electrode of a further semiconductor chip. 1. A semiconductor module comprising: a control electrode disposed on a portion of an external face of the semiconductor chip, and', 'a contact having a two-dimensional extent that substantially covers a remaining portion of the external face; and, 'a semiconductor chip including an electrode having a side that contacts the contact of the semiconductor chip such that the electrode is electrically connected to and fixed on the contact, and', 'a counter electrode electrically connected to the control electrode of the semiconductor chip., 'a passive discrete component arranged in a package and stacked on the contact, the passive discrete component comprising2. The semiconductor module according to claim 1 , wherein the passive discrete component comprises a coupling capacitor wired with the semiconductor chip as a stack of the semiconductor module as a high-pass filter or a low-pass filter.3. The semiconductor module according to claim 1 , wherein the passive discrete component further comprises a coupling capacitor wired with the semiconductor chip as a stack of the semiconductor module as a boot capacitor.4. The semiconductor module according to claim 3 , wherein:{'sub': 'B', 'the boot capacitor has a capacitance C; and'}{'sub': 'B', '5 nF≦C≦100 nF.'}5. The semiconductor module according to claim 1 , wherein:the ...

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Номер записи: 81
31-10-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130285202A1
Автор: Arao Takashi, Fujiwara Naonori, Koyanagi Kenichi, Uno Tomohiro
Принадлежит: ELPIDA MEMORY, INC.

To provide a semiconductor device including a capacitor which includes a cylindrical or columnar lower electrode, a support film in contact with the upper portion of the lower electrode for supporting the lower electrode, a dielectric film covering the lower electrode and the support film, and an upper electrode facing the lower electrode with the dielectric film interposed therebetween, wherein the dielectric film has a first thickness on the upper surface of the support film and a second thickness thinner than the first thickness on the side surface of the lower electrode, and thereby the mechanical strength of the support film is increased. 1. A semiconductor device provided with a capacitor comprising:a cylindrical or columnar lower electrode;a support film in contact with the upper portion of the lower electrode;a dielectric film covering the lower electrode and the support film; andan upper electrode facing the lower electrode with the dielectric film interposed therebetween,wherein the dielectric film has a first thickness on the upper surface of the support film and a second thickness thinner than the first thickness on the side surface of the lower electrode.2. The semiconductor device according to claim 1 , wherein the second thickness is a thickness of the dielectric film at a position lower than the position at which the lower electrode is in contact with the support film.3. The semiconductor device according to claim 2 , wherein in the dielectric film claim 2 , a ratio of dA/dB claim 2 , in which dA is the first thickness and dB is the second thickness claim 2 , is 1.25 or more.4. The semiconductor device according to claim 1 , wherein the support film is in contact with the upper side edge of the lower electrode.5. The semiconductor device according to claim 4 , wherein the first thickness is a maximum thickness of the dielectric film.6. The semiconductor device according to claim 1 , wherein the second thickness of the dielectric film is a thickness ...

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Номер записи: 82
31-10-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130285203A1
Автор: Hiroi Masayuki, SAKOH Takashi
Принадлежит: RENESAS ELECTRONICS CORPORATION

The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area. 1. A semiconductor integrated circuit device comprising:(a) a semiconductor substrate having a first main surface and a second main surface;(b) a memory array area and a non-memory array area provided over the first main surface;(c) a first embedded metal interconnection layer to an Nth embedded metal interconnection layer provided over the first main surface;(d) a low-dielectric constant interlayer insulating film provided to at least one of the first to Nth embedded metal interconnection layers;(e) a plurality of memory capacitors provided across at least from the first to Nth embedded metal interconnection layers; and(f) a memory-periphery metal seal ring provided between the memory array area and the non-memory array area so as to surround the memory array area and extending across the embedded metal interconnection layers including the low-dielectric constant interlayer insulating film.2. The semiconductor integrated circuit device according to claim 1 , whereinthe low-dielectric constant interlayer insulating film is a porous low-dielectric constant film.3. The semiconductor integrated circuit device according to claim 2 , whereinthe memory array area has a COB structure.4. The semiconductor integrated circuit device according to claim 3 , whereinthe memory capacitors have an upper electrode interconnecting the memory capacitors and lower electrodes provided to respective memory capacitors.5. The semiconductor integrated circuit ...

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Номер записи: 83
31-10-2013 дата публикации

COMPONENT-BUILT-IN WIRING BOARD

Номер: US20130285204A1
Автор: Hashimoto Hirohito, MIYAMOTO Shinya, Saita Kenichi, Suzuki Shinya, Yamashita Daisuke
Принадлежит: NGK SPARK PLUG CO., LTD.

Embodiments of the present invention provide a component-built-in wiring board capable of preventing a defect, such as a crack, resulting from stress concentration at a corner, when a component is accommodated in a housing portion of a core material with resin filler filled therebetween. The component-built-in wiring board can include a component accommodated in the housing portion of a core material, and a laminate portion in which insulating layers and conductor layers are laminated alternately on the core material. A gap between the housing portion of the core material and the component can be filled with a resin filler. In an inner circumferential portion of the housing portion of the core material a first straight chamfered portion is formed at each corner of a rectangle, and in an outer circumferential portion of the component a second straight chamfered portion is formed at each corner of a rectangle. 1. A component-built-in wiring board comprising:a core material having a housing portion extending through upper and lower surfaces of the core material;a component accommodated in the housing portion; anda laminate portion in which insulating layers and conductor layers are alternately laminated on at least one of the upper and lower surfaces of the core material, whereina gap between an inner circumferential portion of the housing portion and an outer circumferential portion of the component is filled with a resin filler,the inner circumferential portion of the housing portion has a cross-section where a first straight chamfered portion is formed at each corner of a rectangle in a plane direction,the outer circumferential portion of the component has a cross-section where a second straight chamfered portion is formed at each corner of a rectangle in the plane direction,at least the second chamfered portion has a chamfer length greater than a width of the gap between the first chamfered portion and the second chamfered portion, andthe outer circumferential ...

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Номер записи: 84
31-10-2013 дата публикации

Method for Producing MIM Capacitors with High K Dielectric Materials and Non-Noble Electrodes

Номер: US20130285205A1
Автор: Chen Hanhong, Kumar Pragati
Принадлежит:

A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor. 1. A semiconductor layer stack comprising:a first electrode deposited on a substrate;wherein the first electrode further comprises a dopant;a dielectric material deposited on the first electrode; anda second electrode deposited on the dielectric material,{'sub': 2', '2', '2, 'wherein the first electrode is a non-noble electrode and comprises one of MoO, MnO, TiN, or WO, and'}wherein the dopant comprises one of Co or Ni.2. The semiconductor layer stack of claim 1 , wherein the dopant in the first electrode preserves a rutile crystalline structure of the first electrode and increases a work function of the first electrode.3. The semiconductor layer stack of claim 2 , wherein a concentration of the dopant in the first electrode is less than 20 at %.4. The semiconductor layer stack of claim 3 , wherein the second electrode comprises one of MoO claim 3 , MnO claim 3 , TiN claim 3 , or WO.5. The semiconductor layer stack of claim 4 , wherein the second electrode further comprises a dopant claim 4 , and wherein the dopant comprises with one of Co or Ni claim 4 ,wherein the dopant in the second electrode preserves a rutile crystalline structure of the second electrode and increases a work function of the second electrode.6. The semiconductor layer stack of claim 5 , wherein a concentration of the dopant in the second electrode is less than ...

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Номер записи: 85
07-11-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130292740A1
Автор: TERASHIMA Tomohide, Yamashita Junichi
Принадлежит: Mitsubishi Electric Corporation

In a region located between a collector electrode and a semiconductor substrate, there are a portion where a hollow region is located and a portion where no hollow region is located. Between the collector electrode and the portion where no hollow region is located in the semiconductor substrate, a floating silicon layer electrically isolated by insulating films is formed. 1. A semiconductor device comprising:a semiconductor substrate having a main surface with a ground voltage applied to said semiconductor substrate;a first insulating film formed to cover said main surface of said semiconductor substrate;a semiconductor layer of a predetermined conductivity type formed to cover said first insulating film;a second insulating film formed to cover said semiconductor layer; anda first electrode formed to cover a predetermined region of said second insulating film with a predetermined voltage higher than said ground voltage applied to said first electrode, a region where a hollow is formed between said semiconductor substrate and said first insulating film; and', 'a region where no hollow is formed between said semiconductor substrate and said first insulating film,, 'in a region located between said first electrode and said semiconductor substrate, there being locatedin a portion of said semiconductor layer that is located directly above said region where said hollow is formed, an element-formed region being formed which is electrically connected to said first electrode and in which a predetermined semiconductor element is formed,between said first electrode and a portion of said semiconductor substrate that is located in said region where no hollow is formed, an electric field alleviation region being formed, andin said electric field alleviation region, a plurality of capacitors being formed that are connected in series between said predetermined voltage applied to said first electrode and said ground voltage applied to said semiconductor substrate.2. The ...

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Номер записи: 86
07-11-2013 дата публикации

SEMICONDUCTOR DEVICES INCLUDING CAPACITOR SUPPORT PADS

Номер: US20130292796A1
Автор: Cho Young-kyu, Choi Yong-hee, Im Ki-vin
Принадлежит:

A semiconductor device may include a semiconductor substrate and a plurality of first capacitor electrodes arranged in a plurality of parallel lines on the semiconductor substrate with each of the first capacitor electrodes extending away from the semiconductor substrate. A plurality of capacitor support pads may be provided with each capacitor support pad being connected to first capacitor electrodes of at least two adjacent parallel lines of the first capacitor electrodes and with adjacent capacitor support pads being spaced apart. A dielectric layer may be provided on each of the first capacitor electrodes, and a second capacitor electrode may be provided on the dielectric layer so that the dielectric layer is between the second capacitor electrode and each of the first capacitor electrodes. Related methods are also discussed. 122-. (canceled)22. A semiconductor device , comprising:a semiconductor substrate;a first capacitor on the semiconductor substrate, the first capacitor comprising a first tubular lower electrode extending away from the semiconductor substrate in a vertical direction, the first tubular lower electrode having an upper end that is open, a first capacitor dielectric on the first tubular lower electrode and a first upper electrode on the first capacitor dielectric;a second capacitor on the semiconductor substrate, the second capacitor comprising a second tubular lower electrode extending away from the semiconductor substrate in a vertical direction, the second tubular lower electrode having an upper end that is open, a second capacitor dielectric on the second tubular lower electrode and a second upper electrode on the second capacitor dielectric; anda first support structure comprised of an insulating material connecting an upper portion of the first tubular lower electrode with an upper portion of the second tubular lower electrode, the first support structure contacting a first side of the first tubular lower electrode and a first side of the ...

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Номер записи: 87
07-11-2013 дата публикации

DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE

Номер: US20130292798A1
Автор: KEMERER Timothy W., NAKOS James S., SHANK Steven M.
Принадлежит:

A resistor and capacitor are provided in respective shallow trench isolation structures. The method includes forming a first and second trench in a substrate and forming a first insulator layer within the first and second trench. The method includes forming a first electrode material within the first and second trench, on the first insulator layer, and forming a second insulator layer within the first and second trench and on the first electrode material. The method includes forming a second electrode material within the first and second trench, on the second insulator layer. The second electrode material pinches off the second trench. The method includes removing a portion of the second electrode material and the second insulator layer at a bottom portion of the first trench, and filling in the first trench with additional second electrode material. The additional second electrode material is in electrical contact with the first electrode material. 1. A method of forming a concentrically placed resistor and capacitor in a single trench structure , comprising:forming a deep trench through an STI structure and an underlying substrate;forming a first insulator material on a sidewall and bottom of the deep trench;forming a first electrode layer on the first insulator material, within the deep trench;forming a second insulator material on the first electrode layer;removing a portion of the second insulator material at a bottom of the deep trench to expose the first electrode layer;forming a second electrode layer in the deep trench on the second insulator material, and in electrical contact with the first electrode layer;forming a third insulator layer on the second electrode layer, in the deep trench; andforming a third electrode layer in the deep trench on the third electrical layer.2. The method of claim 1 , wherein the first electrode layer claim 1 , the second electrode layer and the third electrode layer are polysilicon.3. The method of claim 1 , wherein the first ...

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Номер записи: 88
14-11-2013 дата публикации

METHOD FOR MANUFACTURING THIN FILM CAPACITOR AND THIN FILM CAPACITOR OBTAINED BY THE SAME

Номер: US20130299943A1
Автор: Guegan Guillaume, Sakurai Hideaki, Soyama Nobuyuki, Watanabe Toshiaki
Принадлежит:

A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0. 14-. (canceled)61. An electronic device comprising a thin film capacitor obtained using the method for manufacturing according to claim . 1. Field of the InventionThe present invention relates to a method for manufacturing a thin film capacitor having superior leakage current characteristics and dielectric breakdown voltage characteristics. More particularly, the present invention relates to a method for manufacturing a thin film capacitor having the superior characteristics above in which formation of hillocks is suppressed during the manufacturing process of the thin film capacitor and which thereby prevents deterioration in dielectric breakdown voltage and increase in leakage current density caused by hillock generation.2. Description of Related ArtElectronic devices such as a dynamic random access memory (DRAM), a ferroelectric random access memory (FeRAM), an RF circuit or the like are provided with a capacitor. However the demand for higher integration and miniaturizing of devices in recent years has resulted in a ...

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Номер записи: 89
14-11-2013 дата публикации

METHOD FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH CAPACITOR AND RESISTOR AND METHOD FOR FORMING

Номер: US20130302965A1
Автор: HAIDER Asad M., KLAWINSKY James, MONTGOMERY Scott K., SUMMERFELT Scott R., WILLIAMS Byron L.
Принадлежит:

An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps. 1. A method of fabricating an integrated circuit , comprising;depositing a metallic material;depositing a conductive etch stop material on top of said metallic material;depositing a dielectric on top of said conductive etch stop material;depositing a top plate material on said dielectric;forming a first photoresist pattern over said top plate material to define a top plate of a capacitor;etching away portions of said top plate material and said dielectric exposed by said first photoresist pattern and stopping in said conductive etch stop material.forming a second photoresist pattern to define a bottom plate of said capacitor and to define a metallic device; andetching away portions exposed said etch stop material and said metallic material exposed by said second photoresist pattern to form said bottom plate of the capacitor and said metallic device.2. The method of wherein said metallic device is a resistor and said metallic material is selected from the group consisting of TiAl claim 1 , Ti claim 1 , TiN claim 1 , Ta claim 1 , TaN claim 1 , Ir/TiAlN claim 1 , Ir claim 1 , TiAlN claim 1 , SiCr claim 1 , NiCr claim 1 , and TiWN.3. The method of wherein said conductive etch stop material is selected from the group consisting of TiAlON claim 1 , TiAlN claim 1 , and TiAlO.4. The method of wherein said conductive etch stop material has a resistivity about 10 times greater than said metallic material.5. The method of where said metallic material is composed of TiAl with a Ti to Al atomic ratio between 80:20 and 50:50 and where conductive etch stop material is TiAlON where Ti to Al ratio in said TiAlON is within 20% of ...

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Номер записи: 90
21-11-2013 дата публикации

METHODS OF FORMING A RUTHENIUM MATERIAL, METHODS OF FORMING A CAPACITOR, AND RELATED ELECTRONIC SYSTEMS

Номер: US20130307120A1
Автор: Antonov Vassil, Bhat Vishwanath, Gealy Dan
Принадлежит: MICRON TECHNOLOGY, INC.

Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided. 1. A method of forming a ruthenium material on a substrate , comprising:forming a ruthenium silicide material on a substrate; andforming a ruthenium material on the ruthenium silicide material to have an exposed surface of the ruthenium material substantially free of silicon.2. The method of claim 1 , wherein forming a ruthenium silicide material on a substrate comprises exposing the substrate to a gaseous mixture of a silicon precursor gas and a ruthenium precursor gas.3. The method of claim 1 , wherein forming a ruthenium silicide material on a substrate comprises exposing the substrate to a silicon precursor gas comprising at least one of silane claim 1 , disilane claim 1 , trisilane claim 1 , dichlorosilane claim 1 , trichlorosilane claim 1 , hexachlorodisilane claim 1 , and a methylated silane.4. The method of claim 1 , wherein forming a ruthenium material on the ruthenium silicide material comprises forming the ruthenium material comprising a decreasing concentration of silicon between a surface of the ruthenium material adjacent the ruthenium silicide material to the exposed surface of the ruthenium material.5. The method of claim 1 , wherein forming a ruthenium material comprises forming a ruthenium material having the exposed surface with a silicon content of between 0 atomic percent and 0.01 atomic percent.6. The method of claim 1 , wherein forming a ruthenium material comprises exposing the ruthenium silicide to a hydrogen source gas and a ruthenium precursor gas.7. The method of claim 6 , wherein exposing the ruthenium silicide to a hydrogen source gas comprises exposing the ruthenium silicide to at least one of hydrogen and ammonia.8. The method of claim 1 , further comprising forming another ruthenium material over the ruthenium material and exhibiting a greater porosity than a porosity of the ruthenium material.9. A method of forming a ...

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Номер записи: 91
21-11-2013 дата публикации

Decoupling Composite Capacitor in a Semiconductor Wafer

Номер: US20130309833A1
Автор: Chen Xiangdong, Xia Wei
Принадлежит: BROADCOM CORPORATION

According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode. 1. A method for fabricating a decoupling composite capacitor , said method comprising:forming a through-wafer via opening in a substrate, and covering a sidewall and a bottom of said through-wafer via opening with a through-wafer via insulator;covering said through-wafer via insulator with a through-wafer via conductor;forming a substrate backside insulator;forming an opening in said substrate backside insulator to expose said through-wafer via conductor;forming a substrate backside conductor on said through-wafer via conductor, such that said substrate backside conductor extends over said substrate backside insulator, thereby forming said decoupling composite capacitor.2. The method of further comprising thinning said substrate prior to said forming said substrate backside insulator.3. The method of wherein said substrate forms a first electrode of said decoupling composite capacitor.4. The method of wherein said through-wafer via conductor and ...

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Номер записи: 92
21-11-2013 дата публикации

RETROGRADE SUBSTRATE FOR DEEP TRENCH CAPACITORS

Номер: US20130309835A1
Автор: Basker Veeraraghavan S., Haensch Wilfried E., Leobandung Effendi, Yamashita Tenko, Yeh Chun-chen
Принадлежит:

A method for forming a semiconductor device includes forming a deep trench in a substrate having a first doped portion to a first depth and a second doped portion below the first depth, the deep trench extending below the first depth. A region around the deep trench is doped to form a buried plate where the buried plate includes a dopant type forming an electrically conductive connection with the second doped portion of the substrate and being electrically insulated from the first doped portion. A deep trench capacitor is formed in the deep trench using the buried plate as one electrode of the capacitor. An access transistor is formed to charge or discharge the deep trench capacitor. A well is formed in the first doped portion. 1. A method for forming a semiconductor device , comprising:forming a deep trench in a retrograde substrate having a first doped portion to a first depth and a second doped portion below the first depth, the deep trench extending below the first depth;doping a region around the deep trench to form a buried plate where the buried plate includes a dopant type forming an electrically conductive connection with the second doped portion of the substrate and being electrically insulated from the first doped portion;forming a deep trench capacitor in the deep trench using the buried plate as one electrode of the capacitor;forming an access transistor to charge or discharge the deep trench capacitor; andforming a well in the first doped portion.2. The method as recited in claim 1 , wherein the first doped portion includes a p− doping and the second doped portion includes an n+ type doping and the step of doping a region around the deep trench to form a buried plate includes doping the region with an n+ doping.3. The method as recited in claim 1 , wherein the substrate includes a semiconductor-on-insulator substrate having semiconductor material formed on a buried dielectric layer over a bulk substrate claim 1 , and the step of forming an access ...

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Номер записи: 93
28-11-2013 дата публикации

HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS

Номер: US20130313680A1
Автор: Haba Belgacem, Mohammed Ilyas, Oganesian Vage, Savalia Piyush
Принадлежит: TESSERA, INC.

A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates. 1. A component having electrodes for electrical interconnection with a circuit component or microelectronic element , comprising:a substrate consisting essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C., the substrate having a first surface, a second surface opposite the first surface, and an opening extending between the first and second surfaces through a thickness of the substrate; and a first pair of electrically conductive plates being first and second plates and a second pair of electrically conductive plates being third and fourth plates, each plate extending along an inner surface of the opening, wherein the first plate overlies the inner surface, the third plate overlies the first plate and is separated therefrom by a first capacitor dielectric layer, the second plate overlies the third plate and is separated therefrom by a second dielectric layer, and the fourth plate overlies the second plate and is separated therefrom by a third capacitor dielectric layer; and', 'first and second electrodes, the first electrode exposed at the first surface at a first location and electrically ...

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Номер записи: 94
28-11-2013 дата публикации

CAPACITANCE STRUCTURE

Номер: US20130313681A1
Автор: GOEKCEN Mehmet, KRUPPA Jacek, Steinecke Thomas
Принадлежит:

A capacitance structure includes a first input terminal configured to input a first input signal, a first output terminal configured to output the first output signal, a second input terminal configured to input a second input signal, a second output terminal configured to output a second output signal, and a plurality of trench cells. Each of the plurality of trench cells includes a first electrode and a second electrode. The first electrodes of the plurality of trenches are interconnected to form a first electrode of the capacitor structure, the second electrodes of the plurality of trench cells are interconnected to form a second electrode of the capacitor structure, the first electrode of the capacitor structure is connected to the first input signal, and the second electrode of the capacitor structure is connected to the input second signal. 1. A capacitance structure comprising:a first input terminal configured to input a first input signal,a first output terminal configured to output the first output signal,a second input terminal configured to input a second input signal,a second output terminal configured to output a second output signal, anda plurality of trench cells,wherein each of the plurality of trench cells comprises a first electrode and a second electrode,wherein the first electrodes of the plurality of trenches are interconnected to form a first electrode of the capacitor structure,wherein the second electrodes of the plurality of trench cells are interconnected to form a second electrode of the capacitor structure,wherein the first electrode of the capacitor structure is connected to the first input signal, andwherein the second electrode of the capacitor structure is connected to the input second signal.2. The capacitance structure according to claim 1 , wherein the first input signal comprises a first supply voltage and said second input signal comprises a second supply voltage.3. The capacitance structure according to claim 1 , wherein the ...

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Номер записи: 95
28-11-2013 дата публикации

Semiconductor wire-array varactor structures

Номер: US20130313683A1
Автор: Amlan Majumdar, Katherine L. Saenger, Oki Gunawan
Принадлежит: International Business Machines Corp

Semiconductor variable capacitor (varactor) devices are provided, which are formed with an array of radial p-n junction structures to provide improved dynamic range and sensitivity. For example, a semiconductor varactor device includes a doped semiconductor substrate having first and second opposing surfaces and an array of pillar structures formed on the first surface of the doped semiconductor substrate. Each pillar structure includes a radial p-n junction structure. A first metallic contact layer is conformally formed over the array of pillar structures on the first surface of the doped semiconductor substrate. A second metallic contact layer formed on the second surface of the doped semiconductor substrate. An insulating layer is formed on the doped semiconductor substrate surrounding the array of pillar structures.

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Номер записи: 96
28-11-2013 дата публикации

SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES

Номер: US20130316512A1
Автор: Gunawan Oki, Majumdar Amlan, Saenger Katherine L.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Semiconductor variable capacitor (varactor) devices are provided, which are formed with an array of radial p-n junction structures to provide improved dynamic range and sensitivity. For example, a semiconductor varactor device includes a doped semiconductor substrate having first and second opposing surfaces and an array of pillar structures formed on the first surface of the doped semiconductor substrate. Each pillar structure includes a radial p-n junction structure. A first metallic contact layer is conformally formed over the array of pillar structures on the first surface of the doped semiconductor substrate. A second metallic contact layer formed on the second surface of the doped semiconductor substrate. An insulating layer is formed on the doped semiconductor substrate surrounding the array of pillar structures. 1. A method of fabricating a semiconductor varactor device , comprising:forming an array of pillar structures on a first surface of a doped semiconductor substrate, wherein each pillar structure comprises a radial p-n junction structure;conformally forming a first metallic contact layer over the array of pillar structures on the first surface of the doped semiconductor substrate;forming a second metallic contact layer on a second surface of the doped semiconductor substrate opposite the first surface; andforming an insulating layer on the doped semiconductor substrate surrounding the array of pillar structures.2. The method of claim 1 , wherein forming the array of pillar structures comprises forming a honeycomb lattice arrangement of pillar structures.3. The method of claim 1 , wherein forming the array of pillar structures comprises:forming an array of radial wires on the first surface of the doped semiconductor substrate;forming a conformal semiconductor layer on the array of radial wires and on regions of the first surface of the doped semiconductor substrate between the radial wires.4. The method of claim 3 , wherein the doped semiconductor ...

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Номер записи: 97
05-12-2013 дата публикации

Semiconductor Device Having Features to Prevent Reverse Engineering

Номер: US20130320491A1
Автор: Michael Clinton HOKE, Robert Francis TENCZAR, William Eli Thacker, III
Принадлежит: Static Control Components Inc

It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

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Номер записи: 98
05-12-2013 дата публикации

METAL FINGER CAPACITORS WITH HYBRID METAL FINGER ORIENTATIONS IN STACK WITH UNIDIRECTIONAL METAL LAYERS

Номер: US20130320494A1
Автор: CHIDAMBARAM PR, CHOI Jihong, Ge Lixin, YANG Bin, Zhu John J.
Принадлежит: QUALCOMM INCORPORATED

A semiconductor die having a plurality of metal layers, including a set of metal layers having a preferred direction for minimum feature size. The set of metal layers are such that adjacent metal layers have preferred directions orthogonal to one another. Finger capacitors formed in the set of metal layers are such that a finger capacitor formed in one metal layer has a finger direction parallel to the preferred direction of that metal layer. In bidirectional metal layers, capacitor fingers may be in either direction. 1. A semiconductor die comprising:a first unidirectional metal layer formed in the semiconductor die, the first unidirectional metal layer having a first preferred direction;a first capacitor fabricated in the first unidirectional metal layer, the first capacitor comprising interdigitated fingers having a direction parallel to the first preferred direction;a second unidirectional metal layer formed in the semiconductor die and adjacent to the first unidirectional metal layer, the second unidirectional metal layer having a second preferred direction orthogonal to the first preferred direction;a second capacitor fabricated in the second unidirectional metal layer, the second capacitor comprising interdigitated fingers having a direction parallel to the second preferred direction.2. The semiconductor die of claim 1 , further comprising:a third unidirectional metal layer formed in the semiconductor die and adjacent to the second unidirectional metal layer, the third unidirectional metal layer having a third preferred direction orthogonal to the second preferred direction;a third capacitor fabricated in the third unidirectional metal layer, the third capacitor comprising interdigitated fingers having a direction parallel to the third preferred direction.3. The semiconductor die of claim 2 , further comprising:a fourth bidirectional metal layer formed in the semiconductor die and adjacent to the first unidirectional metal layer;a fourth capacitor fabricated ...

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Номер записи: 99
05-12-2013 дата публикации

CAPACITIVE ELEMENT, MANUFACTURING METHOD OF THE SAME, SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS

Номер: US20130323901A1
Автор: Ebiko Yoshiki
Принадлежит: SONY CORPORATION

A capacitive element, includes: an active region parted by an element isolation region formed in a semiconductor substrate; a first electrode formed of a diffusion layer in the active region; an insulating layer formed on the first electrode; and a second electrode formed on a planar surface of the first electrode via the insulating layer, wherein the second electrode is formed within the active region and within the first electrode in a planar layout. 1. A method for manufacturing a capacitive element , the method comprising the steps of:forming in a semiconductor substrate an element isolation region that parts an active region;ion implanting impurities in the active region so as to form a first electrode formed of a diffusion layer;forming an insulating layer on the first electrode; andforming a second electrode above the insulating layer and on a planar surface of the first electrode, wherein the second electrode is formed within the active region and within the first electrode in a planar layout.2. A method for manufacturing a capacitive element , the method comprising the steps of:ion implanting impurities in a region of a semiconductor substrate to be an active region so as to form a first electrode formed of a diffusion layer;forming in the semiconductor substrate an element isolation trench that parts the active region;embedding an insulating film in the element isolation trench to form an element isolation region;forming an insulating layer on the first electrode; andforming a second electrode on the insulating layer,the element isolation trench being formed in part by removing a peripheral portion of the first electrode, and portions of the semiconductor substrate surrounding the peripheral portion of the first electrode.3. The method according to claim 2 , wherein the second electrode is formed within the active region and within the first electrode in a planar layout. The present application is a divisional of U.S. patent application Ser. No. 12/661,760 ...

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Номер записи: 100