КОНСТРУКТИВНЫЙ ЭЛЕМЕНТ

... 1. Конструктивный элемент, в частности полупроводниковый компонент, содержащий первую микросхему (10), размещенную на второй микросхеме (20), в котором первая и вторая микросхемы (10, 20) имеют соответственно на одной из своих основных поверхностей (13, 23) первую, соответственно, вторую металлизации (12, 22), которые обращены одна к другой, при этом первые участки металлизаций (12, 22) предусмотрены для выполнения электрического соединения между первой и второй микросхемами (10, 20), а вторые участки металлизации (12, 22) предусмотрены как дополнительная электрическая функциональная поверхность вне первой и второй микросхем (10, 20). 2. Конструктивный элемент по п. 1, отличающийся тем, что первая и/или вторая металлизация (12, 22) через контактные элементы (14, 24) соединены с контактными площадками (11, 21), расположенными в верхнем слое металлизации. 3. Конструктивный элемент по п.1 или 2, отличающийся тем, что первая или вторая микросхема (10, 20) в местах, в которых противолежащая ...

Dreidimensionale integrierte Schaltungsstruktur und Verfahren zu deren Herstellung

Es wird eine dreidimensionale integrierte Schaltungsstruktur bereitgestellt, die ein erstes Dia, eine Trägerschichtdurchkontaktierung und ein Verbindungselement enthält. Das erste Die ist an ein zweites Die mit einer ersten dielektrischen Schicht des ersten Dies und einer zweiten dielektrischen Schicht des zweiten Dies gebunden, wobei eine erste Passivierungsschicht zwischen der ersten dielektrischen Schicht und einer ersten Trägerschicht des ersten Dies liegt und ein erstes Testpad in der ersten Passivierungsschicht eingebettet ist. Die Trägerschichtdurchkontaktierung durchdringt das erste Die und ist elektrisch mit dem zweiten Die verbunden. Das Verbindungselement ist elektrisch mit dem ersten Die und dem zweiten Die durch die Trägerschichtdurchkontaktierung verbunden.

3DIC-STRUKTUR UND VERFAHREN ZUM HYBRID-BONDEN VON HALBLEITER-WAFERN

Verfahren zur Verbesserung von Hybrid-Bonderträgen für Halbleiterwafer beim Ausbilden von 3DIC-Vorrichtungen umfassen erste und zweite Wafer, die Dummy- und Hauptmetall aufweisen, das während der BEOL-Bearbeitung abgeschieden und strukturiert wird. Metall der Dummy-Metallstruktur besetzt zwischen etwa 40% und etwa 90% der Fläche jedes gegebenen Dummy-Metallstrukturbereichs. Eine hohe Dummy-Metalloberflächenabdeckung in Verbindung mit der Verwendung von geschlitzten leitfähigen Pads erlaubt eine verbesserte Planarisierung von Waferoberflächen, die für Hybrid-Bonden bereitgestellt werden. Planarisierte Wafer zeigen minimale topographische Abweichungen, die Stufenhöhenunterschieden von weniger als etwa 400 Å entsprechen. Die planarisierten ersten und zweiten Wafer werden ausgerichtet und anschließend mit Anwendung von Wärme und Druck Dielektrikum-zu-Dielektrikum und RDL-zu-RDL hybrid-gebondet. Lithographiesteuerung zum Erreichen einer WEE von etwa 0,5 mm bis etwa 1,5 mm kann auch verwendet ...

HYBRIDE BONDINSELSTRUKTUR

Die vorliegende Erfindung betrifft einen mehrdimensionalen integrierten Chip, der eine Umverdrahtungsschicht aufweist, die sich vertikal zwischen integrierten Chip-Dies erstreckt, die seitlich von einer rückwärtigen Bondinsel versetzt sind. Der mehrdimensionale integrierte Chip weist einen ersten integrierten Chip-Die mit ersten mehreren Metallverbindungsschichten auf, die innerhalb einer ersten dielektrischen Zwischenschicht angeordnet sind, die auf einer Vorderseite eines ersten Halbleitersubstrats angeordnet ist. Der mehrdimensionale integrierte Chip weist auch einen zweiten integrierten Chip-Die mit zweiten mehreren Metallverbindungsschichten auf, die innerhalb einer zweiten dielektrischen Zwischenschicht angeordnet sind, die an die erste ILD-Schicht anstößt. Eine Bondinsel ist innerhalb einer Aussparung angeordnet, die sich durch das zweite Halbleitersubstrat erstreckt. Eine Umverdrahtungsschicht erstreckt sich vertikal zwischen den ersten mehreren Metallverbindungsschichten und den ...

Backside dummy plugs for 3d integration

Improved metal to metal bonding for stacked (3D) integrated circuits

Semiconductor apparatus and equipment

Integrated circuit structure

METHOD FOR PRODUCING A CONDUCTIVE METAL DIRECT BONDING

Electronic component e.g. microelectromechanical system type component, for use in e.g. three-dimensional heterogeneous electronic device, has conductor via comprising hollow space that forms fluid circulation zone extending between ends

Composant électronique (100) comportant au moins un via conducteur (106) réalisé dans au moins un substrat (101), dans lequel le via conducteur s'étend entre une première extrémité (105) qui forme une ouverture débouchant au niveau d'une face (104) du substrat et une seconde extrémité (107), le via conducteur comportant en outre au moins une portion de matériau électriquement conducteur (110) s'étendant depuis la première extrémité jusqu'à la seconde extrémité et au moins un espace vide (114) apte à former une zone de circulation d'un fluide s'étendant depuis la première extrémité jusqu'à la seconde extrémité ...

PROCESS TO ALLOW ELECTRICAL AND MECHANICAL CONNECTION OF AN ELECTRICAL DEVICE WITH A FACE EQUIPPED WITH CONTACT PADS

A method of manufacturing an electrical device that is electrically and mechanically connectable to another electrical device, the electrical device having a face equipped with contact pads, the method being characterised in that it includes:- a layer-application step in which an adhesive layer is applied on the face equipped with contact pads, the adhesive layer being composed of a substance with adhesive properties; - an opening-creation step in which an opening is created through the adhesive layer at the level of a contact pad; - an opening-filing step in which the opening is filled with a conductive material so that the opening is substantially filled with the conductive material so as to form a conductive path the volume of which is defined by the opening. © KIPO & WIPO 2007 ...

Semiconductor device structure with stacked semiconductor dies

Semiconductor structure, 3dic structure and method of fabricating the same

Semiconductor device and method for manufacturing same

Disclosed herein is a semiconductor device including: a first laminate having a wiring layer formed on a substrate; a second laminate having a wiring layer formed on a substrate, a principal surface of the second laminate being bonded to a principal surface of the first laminate; a functional element disposed in at least one of the first laminate and the second laminate; and an air gap penetrating an interface between the first laminate and the second laminate, the air gap being disposed on an outside of a circuit formation region including the functional element in at least one of the first laminate and the second laminate as viewed from a direction perpendicular to the principal surfaces of the first laminate and the second laminate.

Chip package and method for forming the same

An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Methods for improving wafer planarity and bonded wafer assemblies made from the methods

A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.

Semiconductor package

A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer including second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer, a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor ...

Three dimensional memory device having embedded dynamic random access memory units

Embodiments of a three-dimensional (3D) memory device and a forming method thereof are disclosed. In an example, a 3D memory device comprises a first semiconductor structure, wherein the first semiconductor structure comprises peripheral circuits, an array of embedded dynamic random access memory (DRAM) units and a first bonding layer comprising a plurality of first bonding contacts. The 3D memory device further comprises a second semiconductor structure, wherein the second semiconductor structure comprises an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts. The 3D memory device further comprises a bonding interface located between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts in the bonding interface.

Integrated circuit package and method of forming the same

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

Package structure of semiconductor device

A package structure of semiconductor device includes a first substrate, a second substrate and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the first inner bonding pad pattern. A first bonding-pad density of the outer bonding pad pattern is larger than a second bonding-pad density of the inner bonding pad pattern.

Pad structure for enhanced bondability and method of forming the same

Pad structure for enhanced bondability

Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

Package

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.

Non-volatile memory device and manufacturing method thereof

A non-volatile memory device includes a first substrate, a second substrate, a memory array, a circuit structure, a bonding structure, and a shielding structure. A second front side of the second substrate faces a first front side of the first substrate. The memory array is disposed on the first substrate and disposed at the first front side of the first substrate. The circuit structure is disposed on the second substrate and disposed at the second front side of the second substrate. The bonding structure is disposed between the memory array and the circuit structure. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure is disposed between the memory array and the circuit structure and surrounds the bonding structure. The shielding structure is electrically connected to a voltage source.

Semiconductor memory

IMPROVED METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface 310 usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

Semiconductor packaging device comprising a shield structure

Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component ...

SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes a via provided above a substrate, a conductive layer provided on the via, and a via provided on the conductive layer. The via, the conductive layer, and the via are one continuous structure.

Semiconductor package

A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

NONVOLATILE MEMORY DEVICE, STORAGE DEVICE, AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE

Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly. 1. A nonvolatile memory device comprising:a memory cell array disposed on a substrate, wherein the memory cell array comprises a plurality of memory blocks;a row decoder connected to the memory cell array through word lines; anda page buffer connected to the memory cell array through bit lines,wherein each of the memory blocks comprises a pillar including a first portion disposed on the substrate and a second portion stacked on the first portion,wherein at least a portion of a width of the first portion increases as a distance from the substrate increases, and first conductive materials and first insulating layers surround the first portion and are stacked in turn on the substrate,wherein at least a portion of a width of the second portion increases as a distance from the substrate increases, and second conductive materials and second insulating layers surround the second portion and are stacked in turn on the substrate,wherein a first boundary is located between the first portion and the second portion,wherein the first conductive materials form first memory cells together with the first ...

NONVOLATILE MEMORY DEVICE INCLUDING ERASE TRANSISTORS

A nonvolatile memory device includes bitlines, a source line, cell channel structures, a gate electrode structure, erase channel structures and an erase selection line. The bitlines are disposed at a first end portion of a cell region, arranged in a first horizontal direction and extend in a second horizontal direction. The source line is disposed at a second end portion of the cell region and extend in the second horizontal direction. The cell channel structures are disposed in a cell string area of the cell region and are respectively connected between the bitlines and the source line. The erase channel structures are disposed in a contact area of the cell region and respectively connected between the bitlines and the source line. The erase channel structures include erase transistors. The erase selection line is disposed in the contact area to form a gate electrode of the erase transistors. 1. A nonvolatile memory device bitlines disposed at a first end portion of a cell region , arranged in a first horizontal direction and extending in a second horizontal direction;a source line disposed at a second end portion of the cell region and extending in the second horizontal direction;cell channel structures disposed in a cell string area of the cell region, wherein each one of the cell channel structures is connected between the bitlines and the source line and includes a string selection transistor, a ground selection transistor and memory cells;a gate electrode structure vertically stacked in the cell string area, wherein the gate electrode structure includes a string selection line, a ground selection transistor and wordlines;erase channel structures disposed in a contact area of the cell region, wherein each one of the erase channel structures is connected between the bitlines and the source line and includes erase transistors; andan erase selection line disposed in the contact area to form a gate electrode of the erase transistors.2. The nonvolatile memory device ...

Semiconductor package

A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may ...

Bonding structures and methods of forming the same

A package includes a package component and a second package component. A first elongated bond pad is at a surface of the first package component, wherein the first elongated bond pad has a first length in a first longitudinal direction, and a first width smaller than the first length. A second elongated bond pad is at a surface of the second package component. The second elongated bond pad is bonded to the first elongated bond pad. The second elongated bond pad has a second length in a second longitudinal direction, and a second width smaller than the second width. The second longitudinal direction is un-parallel to the first longitudinal direction.

INTERCONNECT LAYER CONTACT AND METHOD FOR IMPROVED PACKAGED INTEGRATED CIRCUIT RELIABILITY

Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder ...

SEMICONDUCTOR DEVICE AND SOLID-STATE IMAGING DEVICE

The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.

DIE STRUCTURE, DIE STACK STRUCTURE AND METHOD OF FABRICATING THE SAME

Provided is a die structure including a die, a bonding structure, and a protection structure. The die includes a substrate and a metal feature disposed over the substrate. The bonding structure is disposed over the die. The bonding structure includes a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer. The bonding metal layer is electrically connected to the metal feature of the die. The protection structure is disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer. A die stack structure and a method of fabricating the die structure are also provided.

SEMICONDUCTOR DEVICES

A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.

SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF DESIGNING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS

A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Device assembly structure and method of manufacturing the same

A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.

BOND ENHANCEMENT IN MICROELECTRONICS BY TRAPPING CONTAMINANTS AND ARRESTING CRACKS DURING DIRECT-BONDING PROCESSES

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule ...

Semiconductor package and manufacturing method thereof

A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A device includes a first semiconductor substrate and a second semiconductor substrate. A first insulating film is provided on a first face of the first semiconductor substrate. A first metal layer covers an inner surface of a first grove provided on the first insulating film. A first electrode is provided on the first metal layer and embedded in the first groove. The second semiconductor substrate has a second face facing the first face of the first semiconductor substrate. A second insulating film is provided on the second face of the second semiconductor substrate and is attached to the first insulating film. A second electrode is embedded in a second groove provided on the second insulating film and is connected to the first electrode. An end part of the first metal layer is recessed toward the first semiconductor substrate relative to a surface of the first insulating film.

MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY

The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Air trench in packages incorporating hybrid bonding

A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.

BONDED STRUCTURES

A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.

Bond Structures and the Methods of Forming the Same

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

METHOD FOR PRODUCING AN ELECTRONIC DEVICE

A method for producing an electronic device including in a stack at least a first structure and a second structure, the structures being obtained from a first substrate and a second substrate. Marks are obtained from a pattern made on one of the substrates. Furthermore, the same supporting members are used during the bonding phase for the preparation of the marks and for the bonding phase for the assembly of the structures.

Seal Ring in an Integrated Circuit Die

The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

THREE-DIMENSIONAL MEMORY DEVICE WITH LOGIC SIGNAL ROUTING THROUGH A MEMORY DIE AND METHODS OF MAKING THE SAME

A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.

BONDED ASSEMBLY CONTAINING SIDE BONDING STRUCTURES AND METHODS OF MANUFACTURING THE SAME

A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.

3D processor

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections ...

LIGHT-EMITTING DIODE DEVICE WITH DRIVING MECHANISM

A light-emitting diode device with a driving mechanism is provided. A first light-emitting diode chip, a second light-emitting diode chip and a third light-emitting diode chip are arranged on a driver circuit chip, and respectively configured to emit red light, green light and blue light. A first contact of the light-emitting diode chip, a first contact of the second light-emitting diode chip and a first contact of the third light-emitting diode chip are respectively in direct electrical contact with a first output contact, a second output contact and a third output contact of the driver circuit chip in a flip-chip manner. A second contact of the first light-emitting diode chip, a second contact of the second light-emitting diode chip and a second contact of the third light-emitting diode chip are in direct electrical contact with a common contact of the driver circuit chip.

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

Surface emitting light source with lateral variant refractive index profile

A micro-LED includes a light emitting device that emits a light beam surface—normally and a plurality of semiconductor layers that modify the light beam. Each semiconductor layer includes a first lateral region and a second lateral region, where the first lateral region and the second lateral region are characterized by different respective refractive indices. The first lateral regions of the plurality of semiconductor layers are arranged in two or more different lateral areas of the semiconductor light source. The second lateral region in each semiconductor layer of the plurality of semiconductor layers includes a semiconductor material with a different respective composition. The plurality of semiconductor layers form a planar optical component that is used to, for example, collimate, converge, diverge, or deflect the light beam emitted by the light emitting device.

Method of forming a dummy die of an integrated circuit having an embedded annular structure

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit ...

Three-dimensional memory devices

In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a plurality of channel structures each extending vertically through the memory stack, a conductive layer in contact with source ends of the plurality of channel structures, a first source contact electrically connected to the channel structures, and a second source contact electrically connected to the channel structures.

Solid-state imaging device and electronic apparatus

There is provided a solid-state imaging device including: a first substrate including a first semiconductor substrate and a first wiring layer, the first semiconductor substrate having a pixel unit with pixels; a second substrate including a second semiconductor substrate and a second wiring layer, the second semiconductor substrate having a circuit with a predetermined function; and a third substrate including a third semiconductor substrate and a third wiring layer, the third semiconductor substrate having a circuit with a predetermined function, the first, second, and third substrates being stacked in this order, the first substrate and the second substrate being bonded together with the first wiring layer and the second wiring layer opposed to each other, a first coupling structure on bonding surfaces of the first substrate and the second substrate, and including an electrode junction structure with electrodes formed on the respective bonding surfaces in direct contact with each other ...

Semiconductor memory device

A semiconductor memory device includes a first chip having a peripheral transistor and a first insulating layer, and includes a second chip having a stacked structure and a second insulating layer. The stacked structure includes conductive patterns and insulating patterns alternately stacked with each other, the first insulating layer includes a first bonding surface, the second insulating layer includes a second bonding surface contacting the first bonding surface, and the second chip further includes a protrusion protruding from the second bonding surface of the second insulating layer toward the first insulating layer.

Multi-metal contact structure

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate having a first active surface and a first inactive surface opposite to each other, a plurality of through electrodes penetrating the first semiconductor substrate, and a rear cover layer covering the first inactive surface, a second semiconductor chip stacked on the first semiconductor chip and including a second semiconductor substrate having a second active surface and a second inactive surface opposite to each other, and a front cover layer covering the second active surface, a plurality of signal pad structures penetrating the rear cover layer and the front cover layer to be electrically connected to the plurality of through electrodes, and a plurality of dummy pad structures apart from the plurality of signal pad structures in a horizontal direction, and penetrating the rear cover layer and the front cover layer.

SEMICONDUCTOR DEVICE

A semiconductor device includes a conductive substrate, first semiconductor elements and a first conductive member. The substrate includes an obverse surface facing in thickness direction. The first semiconductor elements, bonded to the obverse surface, have a switching function. The conductive member includes a first wiring extending in x direction orthogonal to thickness direction; a second wiring spaced from the first wiring in y direction orthogonal to thickness and x directions, extending in x direction; a third wiring connected to the first wiring and the second wiring, extending in y direction, and connected to the first semiconductor elements; a fourth wiring spaced from the third wiring in x direction, connected to the first wiring and the second wiring, and extending in y direction; and a fifth wiring between the first wiring and the second wiring in y direction and connected to the third wiring and the fourth wiring.

Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device

A chip stacked structure includes a first chip and a second chip. The first chip includes a first substrate, a first functional layer, and first through silicon vias. A diameter of the first through silicon via close to the first functional layer is greater than a diameter of the first through silicon via close to the first substrate. The second chip includes a second substrate and a second functional layer. The chip stacked structure further includes a first redistribution layer disposed on a side that is of the second functional layer and that is away from the second substrate, a first dielectric layer disposed between the first substrate and the first redistribution layer, and a plurality of first bonding metal blocks disposed in the first dielectric layer.

SEMICONDUCTOR DEVICE INCLUDING RESISTOR ELEMENT

A semiconductor device includes a first pad defined on one surface of a first chip; a second pad defined on one surface of a second chip which is stacked on the first chip, and bonded to the first pad; a first resistor element defined in the first chip, and coupled to the first pad; and a second resistor element defined in the second chip, and coupled to the second pad.

SEMICONDUCTOR PACKAGE HAVING REINFORCING STRUCTURE

A semiconductor package comprising a stack structure disposed on a package substrate and that includes a lower structure and an upper structure on the lower structure, the upper structure including a plurality of semiconductor chips offset from each other in a first horizontal direction and stacked in a cascade structure, a reinforcing structure on the upper structure and including a reinforcing chip and an interfacial layer covering an upper surface of the reinforcing chip, and an encapsulant covering the package substrate. The plurality of semiconductor chips include a first semiconductor chip disposed directly below the reinforcing structure and a second semiconductor chip disposed directly below the first semiconductor chip. The reinforcing structure covers an overhanging portion of the first semiconductor chip in which the first semiconductor chip does not overlap the second semiconductor chip in a vertical direction, and the interfacial layer and the encapsulant include the same material ...

STACKED-CHIP PACKAGES

A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.

INTEGRATED CIRCUIT ASSEMBLIES WITH STACKED COMPUTE LOGIC AND MEMORY DIES

Integrated circuit (IC) assemblies with stacked compute logic and memory dies, and associated systems and methods, are disclosed. One example IC assembly includes a compute logic die and a stack of memory dies provided above and coupled to the compute logic die, where one or more of the memory dies closest to the compute logic die include memory cells with transistors that are thin-film transistors (TFTs), while one or more of the memory dies further away from the compute logic die include memory cells with non-TFT transistors. Another example IC assembly includes a similar stack of compute logic die and memory dies where one or more of the memory dies closest to the compute logic die include static random-access memory (SRAM) cells, while one or more of the memory dies further away from the compute logic die include memory cells of other memory types.

MEMORY DEVICES AND METHODS OF FORMING MEMORY DEVICES

Apparatus for handling wafers aligned pairs

Eine für den industriellen Einsatz geeignete Vorrichtung und ein System zur Handhabung präzise aufeinander ausgerichteter und zentrierter Halbleiter-Waferpaare für Wafer-zu-Wafer- Ausrichtungs- und -Bondungsanwendungen weist einen Endeffektor mit einem Rahmenelement und einem schwimmenden Träger auf, der mit dem Rahmenelement, mit einem dazwischen ausgebildeten Spalt, verbunden ist, wobei der schwimmende Träger einen halbkreisförmigen Innenumfangsrand hat. Die zentrierten Halbleiter-Waferpaare sind unter Verwendung des Endeffektors unter robotischer Steuerung innerhalb eines Verarbeitungssystems positionierbar. Die zentrierten Halbleiter-Waferpaare werden ohne Gegenwart des Endeffektors in der Bondungsvorrichtung miteinander verbondet.

Method for handling wafers pairs aligned on top

Ein für den industriellen Einsatz geeignetes Verfahren zur Handhabung präzise aufeinander ausgerichteter und zentrierter Halbleiter-Waferpaare für Wafer-zu-Wafer- Ausrichtungs- und -Bondungsanwendungen weist einen Endeffektor mit einem Rahmenelement und einem schwimmenden Träger auf, der mit dem Rahmenelement, mit einem dazwischen ausgebildeten Spalt, verbunden ist, wobei der schwimmende Träger einen halbkreisförmigen Innenumfangsrand hat. Die zentrierten Halbleiter-Waferpaare sind unter Verwendung des Endeffektors unter robotischer Steuerung innerhalb eines Verarbeitungssystems positionierbar. Die zentrierten Halbleiter-Waferpaare werden ohne Gegenwart des Endeffektors in der Bondungsvorrichtung miteinander verbondet.

Vorrichtung zur Handhabung ausgerichteter Waferpaare

An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.

A process for bonding substrates

Die vorliegende Erfindung betrifft ein Verfahren zum Bonden eines ersten Substrats (4) mit einem zweiten Substrat (4'), dadurch gekennzeichnet, dass das erste Substrat ( 4) und/oder das zweite Substrat (4') vor dem Bonden gedünnt ist/wird.

IMPROVED METHOD OF ASSEMBLY BY DIRECT BONDING BETWEEN TWO ELEMENTS, EACH ELEMENT COMPRISING PORTIONS OF METAL AND DIELECTRIC MATERIALS

3D STACK ELECTRONIC CHIPS

3D STACK ELECTRONIC CHIPS

SYSTEM Of ASSEMBLY OF CHIPS

L'invention concerne un assemblage de puces/tranches semiconductrices dans lequel les faces accolées des deux puces/tranches (W1, W2) comprennent une couche isolante (20, 21) dans laquelle sont insérés des plots de cuivre en regard (Pi1, Pi2). La couche isolante est en un matériau choisi dans le groupe comprenant du nitrure de silicium et du nitro-carbure de silicium.

Device having interconnect structure and manufacturing method thereof

A device having an interconnect structure includes: an interconnect structure over a substrate, the interconnect structure including a first metal line and a second metal line, the first metal line longer than the second metal line; a surface dielectric layer over the interconnect structure; a plurality of first vias in the surface dielectric layer; a first bonding pad in the surface dielectric layer, where the first bonding pad is connected to a first end of the first metal line through the first vias; a plurality of second vias in the surface dielectric layer; a second bonding pad in the surface dielectric layer, the second bonding pad and the first bonding pad separate from each other, where the second bonding pad is connected to a second end of the first metal line through the second vias; and a third bonding pad in the surface dielectric layer, where the third bonding pad is connect to the second metal line through a third via.

Package structure

A package structure includes a chip, a selective-electroplating epoxy compound, a patterned circuit layer and a plurality of conductive vias. The chip includes a plurality of solder pads, an active surface and a back surface opposite to the active surface. The solder pads are disposed on the active surface. The selective-electroplating epoxy compound covers the chip and includes non-conductive metal complex. The patterned circuit layer is disposed directly on a surface of the selective-electroplating epoxy compound. The conductive vias are disposed directly at the selective-electroplating epoxy compound to electrically connect the solder pads and the patterned circuit layer.

System on integrated chips and methods of forming same

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Light emitting device

A light emitting device includes a carrier, at least one epitaxial structure, at least one buffer pad and at least one bonding pad. The epitaxial structure is disposed on the carrier. The buffer pad is disposed between the carrier and the epitaxial structure, wherein the epitaxial structure is temporarily bonded to the carrier by the buffer pad. The bonding pad is disposed on the epitaxial structure, wherein the epitaxial structure is electrically connected to a receiving substrate by the bonding pad.

Three-dimensional integrated circuit structures

Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

Integrated device with electromagnetic shield

Improve EM coupling for the wafer-bonding process from a first wafer to a second wafer by a shielding technique. Examples may include building an EM shield implemented by BEOL-stacks/routings, bonding contacts, and TSVs for a closed-loop shielding platform for the integrated device to minimize EM interference from active devices due to eddy currents. The shield may be implemented in the active device layer during a wafer-to-wafer bonding-process that uses two different device layers/wafers, an active device layer/wafer and a passive device layer/wafer. The shield may be designed by the patterned routings for both I/O ports and the GND contacts.

Integrated circuit package and manufacturing method thereof

Semiconductor package and method of forming same

Semiconductor device and manufacturing method thereof

A hybrid bond using a copper alloy for yield improvement

CHIP-ON-WAFER BONDING METHOD AND BONDING DEVICE, AND STRUCTURE COMPRISING CHIP AND WAFER

... [Problem] To provide a technique for efficiently bonding a chip to a wafer without leaving undesirable residue such as resin on the bonding interface, establishing electrical connections between the chip and wafer or among a plurality of layered chips, and increasing mechanical strength. [Solution] The method of the present invention for bonding a plurality of chips with chip-side bonding surfaces comprising metal regions to a substrate comprising a plurality of bonding sections is provided with the following steps: (S1) wherein the metal regions of the chip-side bonding surfaces are subjected to a surface activation treatment and a hydrophilization treatment; a step (S2) wherein the bonding sections of the substrate are subjected to a surface activation treatment and a hydrophilization treatment; a step (S3) wherein each of the plurality of chips, which have been subjected to the surface activation treatment and the hydrophilization treatment, is attached to the corresponding bonding section ...

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.

SEMICONDUCTOR APPARATUS AND EQUIPMENT

A semiconductor apparatus includes included first and second semiconductor components which are stacked on each other. The first component includes a first insulating layer and a first plurality of metal pads. The second component includes a second insulating layer and a second plurality of metal pads. Each of the first plurality of metal pads and each of the second plurality of metal pads are bonded to each other to form each of a plurality of bonding portions. First and second openings along an edge of the apparatus and passing through a bonding face between the first and second insulating layer are formed in the apparatus. A first bonding portion between the first opening and the second opening of the plurality of bonding portions is arranged in a distinctive location.

SEMICONDUCTOR PACKAGING DEVICE COMPRISING A SHIELD STRUCTURE

Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component if the semiconductor packaging device was flipped vertically.

SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.

NONVOLATILE MEMORY DEVICES

Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation. 1. A nonvolatile memory device comprising:a memory cell region including a first metal pad and a second metal pad;a peripheral circuit region including a third metal pad and a fourth metal pad, the peripheral circuit region being connected to the memory cell region by the first metal pad, the second metal pad, the third metal pad and the fourth metal pad;a memory cell array in the memory cell region, the memory cell array including a plurality of pages, each of the plurality of pages including a plurality of memory cells, each of the plurality of memory cells storing a plurality of data bits, each of the plurality of data bits being selectable by a different threshold voltage; sense data from selected memory cells among the plurality of memory cells through the plurality of bit-lines, the second metal pad and the fourth metal pad, and', 'perform a first read operation and a second read operation, each including two sequential sensing operations to determine one data state, and each of the plurality of page buffers including a latch, among a plurality of ...

SEMICONDUCTOR STRUCTURE, PACKAGE STRUCTURE, AND MANUFACTURING METHOD THEREOF

A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor.

NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array ...

Method for forming metal wiring

A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.

Bond structures and the methods of forming the same

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

System on Integrated Chips and Methods of Forming Same

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Trap Rich Layer for Semiconductor Devices

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

On-Chip Heat Spreader

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Interconnect Structure and Method of Forming Same

A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component. 1. A method comprising: the first semiconductor wafer comprises a first substrate, first inter-metal dielectric layers and first interconnect structures formed in the first inter-metal dielectric layers and over the first substrate; and', 'the second semiconductor wafer comprises a second substrate, second inter-metal dielectric layers and second interconnect structures formed in the second inter-metal dielectric layers and over the second substrate;, 'bonding a first semiconductor wafer on a second semiconductor wafer, whereinpatterning the first substrate to form a first opening and a second opening in the first substrate;depositing a liner to extend from within the first opening to within the second opening; the third opening is an extension of the first opening and formed partially through the first inter-metal dielectric layers; and', 'the fourth opening is an extension of the second opening and formed through the first inter-metal dielectric layers and partially through the second inter-metal dielectric layers; and, 'forming a third opening and a fourth opening using an etching process and using a first interconnect structure as a hard mask layer, whereinplating a conductive material in the first opening, the second opening, the third opening and the fourth ...

Stacked Semiconductor Device Assembly in Computer System

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device. 1. A stacked semiconductor device assembly , comprising: a master interface;', 'a channel master circuit coupled to the master interface;', 'a slave interface;', 'a channel slave circuit coupled to the slave interface;', 'a memory core coupled to the channel slave circuit; and', 'selection circuitry configured to determine whether the IC chip is to communicate data using the channel master circuit or the channel slave circuit., 'a plurality of stacked integrated circuit (IC) chips, each IC chip further comprising2. The stacked semiconductor device assembly of claim 1 , wherein for one of the plurality of stacked IC chips claim 1 , the selection circuitry receives an input claim 1 , and is configured to determine whether the one of the plurality of stacked IC chips is to communicate data using the channel master or slave circuit based on a voltage level of the input.3. The stacked semiconductor device assembly of claim 2 , wherein the one of the plurality of IC chips is physically offset from other IC chips in the stacked semiconductor device assembly.4. The stacked semiconductor device assembly of claim ...

ITERATIVE FORMATION OF DAMASCENE INTERCONNECTS

Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled. 1. A method of fabricating a plurality of interconnects , the method comprising:depositing a conformal layer of a plating base in each of a plurality of vias;depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias;depositing a plating metal over the plating base in each of the plurality of vias, wherein the depositing the plating metal results in each of the plurality of vias being completely filled or incompletely filled with the plating metal;performing a chemical mechanical planarization (CMP);performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal; andperforming a second iteration of the depositing the plating metal over the plating base in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.2. The method according to claim 1 , further comprising forming a plurality of intermediate structures corresponding to the plurality of interconnects by etching a ...

Integrated System and Method of Making the Integrated System

A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads. 1. A method for manufacturing an integrated device , the method comprising:forming a first reconstitution wafer comprising first components;forming a second reconstitution wafer comprising second components;dicing the second reconstitution wafer into second packaged components, the second packaged components comprising the second components;placing the second packaged components on a first main surface of the first reconstitution wafer; anddicing the first reconstitution wafer into integrated devices, each integrated device comprising a first packaged component and a second packaged component.2. The method of claim 1 , further comprising:placing an integrated device on a carrier;bonding the integrated device to the carrier; andencapsulating the integrated device.3. The method of claim 1 , further comprising disposing a first redistribution layer (RDL) on the first main surface of the first reconstitution wafer.4. The method of claim 3 , further comprising claim 3 , before dicing the second reconstitution wafer claim 3 , disposing a second RDL on a first main surface of the second reconstitution wafer claim 3 , wherein placing the second packaged components on the first main surface of the first reconstitution wafer comprises placing the second packaged components with second RDL regions facing ...

Semiconductor Device and Method of Manufacturing

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads. 1. A semiconductor device , comprising: a first passivation layer disposed over a first substrate; and', 'first bond pads disposed in the first passivation layer; and, 'a first die, comprising a second passivation layer, the second passivation layer being bonded to the first passivation layer; and', 'second bond pads disposed in the second passivation layer, each of the second bond pads being bonded to one of the first bond pads, the second bond pads comprising inner bond pads and outer bond pads, the outer bond pads having a greater diameter than the inner bond pads., 'a second die, comprising2. The semiconductor device of further comprising third bond pads disposed in the second passivation layer claim 1 , wherein the third bond pads are closer than the outer bond pads to an outer edge of the second passivation layer claim 1 , and wherein the third bond pads have a greater diameter than the outer bond pads.3. The semiconductor device of claim 1 , wherein:a center of one of the first bond pads is located a first distance from a center of the first passivation layer, the one of the first bond pads having a first diameter;a center of one of the second bond pads is located a second distance from a center of the second passivation layer, the one of the second bond pads being bonded to the one of the first bond pads, the one of the second bond pads having a second diameter; andthe second distance being ...

MEMORY DEVICES WITH THREE-DIMENSIONAL STRUCTURE

A memory device includes a peripheral circuit layer, a first memory layer provided on the peripheral circuit layer, an inter-metal layer provided on the first memory layer, and a second memory layer provided on the inter-metal layer. The peripheral circuit layer includes a first substrate and a peripheral circuit provided on the first substrate. The first memory layer includes a first memory structure electrically connected to the peripheral circuit through metal bonding pads. The inter-metal layer includes intermediate pads electrically connected to the peripheral circuit through metal bonding pads. The second memory layer includes a second memory structure electrically connected with the intermediate pads and a second substrate provided on the second memory structure. The peripheral circuit, the first memory structure, and the second structure are provided between the first substrate and the second substrate. 1. A memory device comprising: a first substrate;', 'a peripheral circuit provided on the first substrate;', 'first metal bonding pads; and', 'second metal bonding pads, 'a peripheral circuit layer including third metal bonding pads;', 'fourth metal bonding pads; and', 'a first memory structure electrically connected to the peripheral circuit through the first metal bonding pads and the third metal bonding pads;, 'a first memory layer provided on the peripheral circuit layer, the first memory layer includingan inter-metal layer provided on the first memory layer, the inter-metal layer including intermediate pads electrically connected to the peripheral circuit through the second metal bonding pads; and a second memory structure electrically connected with the intermediate pads; and', 'a second substrate provided on the second memory structure,, 'a second memory layer provided on the inter-metal layer, the second memory layer includingwherein the peripheral circuit, the first memory structure, and the second structure are provided between the first substrate ...

Process Control for Package Formation

A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

Imaging unit and electronic apparatus

An imaging unit that makes it possible to ensure high dimensional accuracy is provided. This solid-state imaging unit includes a stacked structure including a sensor substrate and a circuit board. The sensor board has an effective pixel region where an imaging device is disposed. The imaging device includes a plurality of pixels and is configured to receive external light in each of the pixels to generate a pixel signal. The circuit board includes a chip including a first portion and a second portion that are integrated with each other. The first portion includes a signal processing circuit that performs signal processing of the pixel signal. The second portion is disposed at a position different from a position of the first portion in an in-plane direction. Here, both the first portion and the second portion are disposed to overlap the effective pixel region in a stacking direction of the sensor board and the circuit board.

MANUFACTURING PROCESS FOR SEPARATING LOGIC AND MEMORY ARRAY

A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies. 1. An integrated memory module comprising:a first semiconductor die comprising a first group of bond pads and a second group of bond pads;a second semiconductor comprising a third group of bond pads flip-chip bonded to the first group of bond pads of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die;wherein the first and second coupled semiconductor dies together are configured as an integrated flash memory.2. The integrated memory module of claim 1 , wherein the first semiconductor die comprises a plurality of memory cells.3. The integrated memory module of claim 2 , wherein the second semiconductor die comprises a control circuit for controlling access to the plurality of memory cells.4. The integrated memory module of claim 3 , wherein the control circuit comprises a complementary metal-oxide-semiconductor integrated circuit.5. The integrated memory module of claim 1 , wherein the second group of bond pads on the first semiconductor die are configured to receive electrical connectors for electrically connecting the integrated memory module to a host device.6. The integrated memory module of claim 1 , wherein the second group of bond pads on the first semiconductor die are configured to receive wire bonds for electrically connecting the integrated memory module to a host device. ...

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first bonding layer on the surface of first substrate, the material of first bonding layer includes dielectrics such as Si, N and C, and the first bonding layer of semiconductor structure is provided with higher bonding force in wafer bonding. 1. A semiconductor structure , comprising:a first substrate; anda first bonding layer on a surface of said first substrate, wherein a material of said first bonding layer comprises dielectric materials of silicon, nitrogen and carbon.2. The semiconductor structure of claim 1 , wherein an atomic concentration of carbon in said first bonding layer is larger than 0% and smaller than 50%.3. The semiconductor structure of claim 1 , wherein an atomic concentration of carbon in said first bonding layer is uniform.4. The semiconductor structure of claim 1 , wherein said atomic concentration of carbon in said first bonding layer gradually changes along with the increase of thickness of said first bonding layer.5. The semiconductor structure of claim 1 , wherein a compactness of said first bonding layer gradually changes along with the increase of thickness of said first bonding layer.6. The semiconductor structure of claim 1 , wherein a thickness of said first bonding layer is larger than 100 Å.7. The semiconductor structure of claim 1 , further comprising a second substrate claim 1 , wherein a second bonding layer is formed on a surface of said second substrate claim 1 , and a surface of said second bonding layer is correspondingly bonded to a surface of said first bonding layer.8. The semiconductor structure of claim 7 , wherein said second bonding layer and said first bonding layer have the same material.9. The semiconductor structure of claim 7 , further comprising:a first bonding pad penetrating through said first bonding layer; anda second bonding pad penetrating through said second ...

Semiconductor structure and method of forming the same

The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first adhesive/bonding stack on the surface of first substrate, wherein the first adhesive/bonding stack includes at least one first adhesive layer and at least one first bonding layer. The material of first bonding layer includes dielectrics such as silicon, nitrogen and carbon, the material of first adhesive layer includes dielectrics such as silicon and nitrogen, and the first adhesive/bonding stack of semiconductor structure is provided with higher bonding force in bonding process.

Forming Metal Bonds with Recesses

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad. 1. A device comprising: a first dielectric layer; and', a diffusion barrier contacting the first dielectric layer; and', 'a metallic material between opposite portions of the diffusion barrier, wherein in a cross-sectional view of the first metal pad, an edge portion of the metallic material is recessed from a top edge of a nearest portion of the diffusion barrier to form an air gap; and, 'a first metal pad comprising], 'a first device die comprising a second dielectric layer bonded to the first dielectric layer; and', 'a second metal pad bonded to the first metal pad through metal-to-metal direct bonding., 'a second device die comprising2. The device of claim 1 , wherein the air gap further extends into the second metal pad.3. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second metal pad.4. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second dielectric layer.5. The device of claim 1 , wherein a surface of the metallic material in the first metal pad and facing the air gap is rounded.6. The device of claim 1 , wherein a surface of the second metal pad facing the air gap is rounded.7. The device of claim 1 , wherein the first device die further comprises a third metal pad comprising ...

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

METHOD OF FORMING SEMICONDUCTOR STRUCTURE

The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding. 1. A method of forming a semiconductor structure , comprising:providing a first substrate;{'sub': '3', 'forming a first bonding layer on a surface of the first substrate, wherein a material of the first bonding layer is a dielectric material containing element carbon (C) and a CHbond;'}providing a second substrate;{'sub': '3', 'forming a second bonding layer on a surface of the second substrate, wherein a material of the second bonding layer is a dielectric material containing element C and a CHbond;'}{'sub': '3', 'oxidizing a surface layer of the first bonding layer and a surface layer of the second bonding layer, wherein the CHbonds are oxidized to be OH bonds; and'}bonding the first bonding layer and the second bonding layer to each other correspondingly.2. The method of forming the semiconductor structure according to claim 1 , wherein C atomic concentration within the surface layer of the first bonding layer and C atomic concentration within the surface layer of the second bonding layer are higher than or equal to 35%.3. The method of forming the semiconductor structure according to claim 1 , wherein the first bonding layer is formed by a plasma-enhanced chemical vapor deposition process.4. The method of forming the semiconductor structure according to claim 3 , wherein a reactive gas used in the plasma-enhanced chemical vapor deposition process comprises NHand one of trimethylsilane or tetramethylsilane.5. The method ...

Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME

A manufacturing method of a semiconductor device according to an embodiment comprises, bonding a first semiconductor substrate and a second semiconductor substrate to form a stack, filling a first fill material having a first viscosity in a gap located between an outer peripheral portion of the first semiconductor substrate and an outer peripheral portion of the second semiconductor substrate, filling a second fill material having a second viscosity higher than the first viscosity in the gap so as to be adjacent to the first fill material after filling the first fill material in the gap and thinning the second semiconductor. 1. A semiconductor device manufacturing method , comprising:bonding a first semiconductor substrate and a second semiconductor substrate, to form a stack;filling a first fill material having a first viscosity in a gap located between an outer peripheral portion of the first semiconductor substrate and an outer peripheral portion of the second semiconductor substrate;filling a second fill material having a second viscosity higher than the first viscosity in the gap so as to be adjacent to the first fill material after filling the first fill material in the gap; andthinning the second semiconductor substrate.2. The semiconductor device manufacturing method according to claim 1 , wherein the first fill material includes an organic compound claim 1 , and the second fill material includes a glass material or an inorganic polymer.3. The semiconductor device manufacturing method according to claim 2 , wherein claim 2 , in the cross-sectional view of the stack claim 2 ,the gap is provided along a surface of the first semiconductor substrate and a surface of the second semiconductor substrate, and includes a first gap portion and a second gap portion,the first gap portion locates closer a center of the first semiconductor substrate and a center of the second semiconductor substrate than an end of the first semiconductor substrate and an end of the second ...

Wafer-to-wafer bonding structure

A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

THREE-DIMENSIONAL STACKING STRUCTURE

A three-dimensional stacking structure is described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die includes contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection. 1. A stacking structure , comprising:a first die, having a first bonding structure, wherein the first bonding structure comprises contact pads;a second die, having a second bonding structure, wherein the second die is stacked on the first die, and the second bonding structure is bonded with the first bonding structure;a spacer protective structure, disposed over the first die and surrounding the second die, wherein the spacer protective structure covers sidewalls of the second die; andan anti-bonding layer, disposed over the first die and located between the spacer protective structure and the first die.2. The structure of claim 1 , wherein the first bonding structure further comprises first bonding elements embedded in a first dielectric material claim 1 , and the second bonding structure comprises second bonding elements embedded in a second dielectric material.3. The structure of claim 2 , wherein the second bonding structure is bonded with the first bonding structure through the bonding of the first and second bonding elements and the bonding of the first and second dielectric materials.4. The structure of claim 2 , wherein the second bonding structure further comprises at least one seal ring structure embedded within the second dielectric material claim 2 , arranged along a ...

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods. 1. A method of forming a bonded semiconductor structure , comprising: providing a first semiconductor structure comprising at least one device structure;bonding a second semiconductor structure to the first semiconductor structure at a temperature or temperatures below about 400° C.;forming at least one through wafer interconnect through the second semiconductor structure and into the first semiconductor structure to the at least one device structure; andbonding the second semiconductor structure on a side thereof opposite the first semiconductor structure to a third semiconductor structure.2. The method of claim 1 , wherein bonding the second semiconductor structure to the first semiconductor structure comprises:bonding a relatively thicker semiconductor structure to the first semiconductor structure; andthinning the relatively thicker semiconductor structure to form the second ...

APPARATUS, SYSTEM, AND METHOD FOR HANDLING ALIGNED WAFER PAIRS

An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device. 1. A system for placing aligned wafer pairs into a processing device , the system comprising:an end effector having a frame member and a floating carrier for carrying wafers in spaced alignment, wherein the floating carrier is movably connected to the frame member;a robotic arm connected to the end effector; anda processing device having a processing chamber, wherein the frame member and floating carrier are positioned within the processing chamber, and wherein the floating carrier is decoupled from the frame member.2. The system of claim 1 , wherein a plurality of vacuum pads are connected to the floating carrier claim 1 , wherein each of the plurality of vacuum pads extend inward of the semi-circular interior perimeter of the floating carrier.3. The system of claim 1 , wherein the plurality of vacuum pads are movably connected to the floating carrier and radially adjustable along the semi-circular interior perimeter.4. The system of claim 2 , wherein the floating carrier is movably connected to the frame member and adjustable along an axis of the semi-circular interior perimeter claim 2 , wherein a size of a gap formed between the frame member and the floating carrier is adjustable.5. The system of claim 1 , wherein a plurality of limit features loosely couple the floating carrier to the frame member.6. The system of claim 1 , further comprising a ...

SEMICONDUCTOR STRUCTURE WITH HEAT DISSIPATION STRUCTURE AND METHOD OF FABRICATING THE SAME

A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region. 1. A semiconductor structure with a heat dissipation structure , comprising:a first device wafer comprising a front side and a back side; a first gate structure disposed on the front side;', 'two first source/drain doping regions embedded within the first device wafer at two side of the first gate structure;', 'a channel region disposed between the two first source/drain doping regions and embedded within the first device wafer; and, 'a first transistor disposed on the front side, wherein the first transistor comprisesa first dummy metal structure contacting the back side of the first device wafer, and overlapping the channel region.2. The semiconductor structure with the heat dissipation structure of claim 1 , further comprising a protective layer covering and contacting the back side and the first dummy metal structure.3. The semiconductor structure with the heat dissipation structure of claim 2 , wherein the first dummy metal structure comprises:a first dummy metal layer contacting the back side and overlapping the channel region;a first metal plug contacting the first dummy metal layer; anda second dummy metal layer contacting the first metal plug, wherein a top surface of the second dummy metal layer is exposed from the protective layer.4. The semiconductor structure with the heat dissipation structure of claim 2 , further comprising: a third dummy metal ...

METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES WITH SUPPORTING STRUCTURE FOR STAIRCASE REGION

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner. 1. A method for forming a three-dimensional (3D) memory device , comprising:sequentially forming a first semiconductor layer, a first block layer, and a sacrificial layer on a substrate;forming a block plug extending vertically through the sacrificial layer and the first block layer to divide the sacrificial layer into a supporting portion and a sacrificial portion;forming a dielectric stack above the sacrificial layer and having a staircase region, such that the supporting portion of the sacrificial layer is below and overlaps the staircase region of the dielectric stack;forming a channel structure extending vertically through the dielectric stack, the sacrificial portion of the sacrificial layer, and the first block layer, into the first semiconductor layer;forming an opening extending vertically through the dielectric stack to expose part of the sacrificial portion of the sacrificial layer; andreplacing, through the opening, the sacrificial portion of the sacrificial layer with a second semiconductor layer coplanar with the supporting portion of the sacrificial layer.2. The method of claim 1 , wherein replacing the sacrificial portion of the sacrificial layer with the second ...

EXTENDED SEAL RING STRUCTURE ON WAFER-STACKING

Embodiments include a wafer-on-wafer bonding where each wafer includes a seal ring structure around die areas defined in the wafer. Embodiments provide a further seal ring spanning the interface between the wafers. Embodiments may extend the existing seal rings of the wafers, provide an extended seal ring structure separate from the existing seal rings of the wafers, or combinations thereof. 1. A package device comprising: a first seal ring structure disposed around a periphery of the first die in a first interconnect of the first die,', 'a first dielectric layer over the first interconnect, and', 'a first seal ring extension disposed in the first dielectric layer, the first seal ring extension aligned with and physically coupled to the first seal ring structure, the first seal ring extension extending continuously around the periphery of the first die; and, 'a first die comprising a second dielectric layer disposed under a second interconnect, and', 'a second seal ring extension disposed in the second dielectric layer, the second seal ring extension aligned with and physically coupled to the first seal ring extension., 'a second die comprising2. The package device of claim 1 , wherein the first seal ring extension and the second seal ring extension are physically coupled by a direct metal-to-metal bond without a eutectic material formed there between.3. The package device of claim 1 , wherein an air gap between the first die and the second die is sealed by the coupled first seal ring extension and the second seal ring extension.4. The package device of claim 1 , wherein the first seal ring extension and the second seal ring extension are offset by a lateral distance.5. The package device of claim 1 , further comprising a third seal ring extension extending through the second die and into the first die claim 1 , the third seal ring surrounding first connectors of the first die and second connectors of the second die.6. The package device of claim 5 , wherein the ...

SEMICONDUCTOR PACKAGE FOR IMPROVING BONDING RELIABILITY

A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures. 1. A semiconductor package comprising:a first semiconductor chip;a second semiconductor chip arranged above the first semiconductor chip; andmain pad structures and dummy pad structures between the first semiconductor chip and the second semiconductor chip,wherein the main pad structures comprise first main pad structures apart from one another on the first semiconductor chip and second main pad structures apart from one another on the second semiconductor chip and bonded to the first main pad structures,wherein the dummy pad structures comprise first dummy pad structures comprising first dummy pads that are arranged apart from one another on the first semiconductor chip and first dummy capping layers arranged on the first dummy pads, and second dummy pad structures comprising second dummy pads that are arranged apart from one another on the second semiconductor chip and second dummy capping layers arranged on the second dummy pads, andwherein the first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the ...

VIAS IN COMPOSITE IC CHIP STRUCTURES

A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet. 1. A method for fabricating an IC device structure , the method comprising:forming a first metallization layer over first and second regions of a first device layer;bonding a chiplet over the first region of the first device layer, the chiplet comprising a second device layer and a second metallization layer, wherein said bonding positions the second device layer between the first device layer and the second metallization layer;forming one or more conductive vias through the second device layer or adjacent to an edge sidewall of the chiplet; andforming a top metallization layer over the chiplet and over the second region of the first device layer, wherein the top metallization layer comprises a plurality of first level interconnect (FLI) interfaces.2. The method of claim 1 , further comprising forming one or more second conductive vias that interconnect the first metallization layer to a backside of the second device layer.3. The method of claim 1 , further comprising bonding a second chiplet between the top metallization layer and the second region of the first device layer claim 1 , wherein the second chiplet comprises a third device layer and one or more third metallization layers interconnected to transistors of the ...

Semiconductor device with recessed pad layer and method for fabricating the same

The present application discloses a semiconductor device with a recessed pad layer and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a second die positioned on the first die, a pad layer positioned in the first die, a filler layer including an upper portion and a recessed portion, and a barrier layer positioned between the second die and the upper portion of the filler layer, between the first die and the upper portion of the filler layer, and between the pad layer and the recessed portion of the filler layer. The upper portion of the filler layer is positioned along the second die and the first die, and the recessed portion of the filler layer is extending from the upper portion and positioned in the pad layer.

THREE-DIMENSIONAL MEMORY DEVICES WITH SUPPORTING STRUCTURE FOR STAIRCASE REGION

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a first semiconductor layer, a supporting structure, a second semiconductor layer, and a plurality of channel structures. The memory stack includes vertically interleaved conductive layers and dielectric layers and has a core array region and a staircase region in a plan view. The first semiconductor layer is above and overlaps the core array region of the memory stack. The supporting structure is above and overlaps the staircase region of the memory stack. The supporting structure and the first semiconductor layer are coplanar. The second semiconductor layer is above and in contact with the first semiconductor layer and the supporting structure. Each channel structure extends vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer. 1. A three-dimensional (3D) memory device , comprising:a memory stack comprising interleaved conductive layers and dielectric layers and having a core array region and a staircase region in a plan view;a first semiconductor layer above and overlapping the core array region of the memory stack;a supporting structure above and overlapping the staircase region of the memory stack, wherein the supporting structure and the first semiconductor layer are coplanar;a second semiconductor layer above and in contact with the first semiconductor layer and the supporting structure; anda plurality of channel structures each extending vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer.2. The 3D memory device of claim 1 , wherein part of the supporting structure in contact with the first semiconductor layer comprises a material other than a material of the first semiconductor layer.3. The 3D memory device of claim 2 , wherein the part of the supporting structure ...

SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE

A wide dynamic range with single exposure is achieved. A solid-state imaging device according to an embodiment includes a first substrate including a photoelectric conversion element , and a second substrate including a capacitor positioned on a side opposite to a surface of incidence of light to the photoelectric conversion element in the first substrate, and configured to accumulate a charge transferred from the photoelectric conversion element. 1. A solid-state imaging device , comprising:a first substrate including a photoelectric conversion element; anda second substrate including a capacitor positioned on a side opposite to a surface of incidence of light to the photoelectric conversion element in the first substrate, and configured to accumulate a charge transferred from the photoelectric conversion element.2. The solid-state imaging device according to claim 1 , wherein the capacitor is a trench capacitor.3. The solid-state imaging device according to claim 1 , wherein:the first substrate includes a plurality of the photoelectric conversion elements; andthe capacitor is configured to accumulate a charge transferred from at least one of the photoelectric conversion elements.4. The solid-state imaging device according to claim 1 , wherein the capacitor includes a plurality of trench capacitors.5. The solid-state imaging device according to claim 4 , wherein the trench capacitors are connected to one another in parallel.6. The solid-state imaging device according to claim 1 , wherein the first substrate and the second substrate are bonded to each other by direct bonding.7. The solid-state imaging device according to claim 1 , wherein:the first substrate further includes a first copper electrode pad provided on a surface opposite to the surface of incidence;the second substrate further includes a second copper electrode pad provided on a surface opposed to the first substrate; andthe first substrate and the second substrate are bonded to each other through ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

A semiconductor device, which is configured as a backside illuminated solid-state imaging device, includes a stacked semiconductor chip which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit; a semiconductor-removed region in which a semiconductor section of a part of the first semiconductor chip unit is completely removed; and a plurality of connection wirings which is formed in the semiconductor-removed region and connects the first and second semiconductor chip units to each other. 119-. (canceled)20. A semiconductor device , comprising:a first substrate including a pixel array and first connection pads;a second substrate bonded to the first substrate, the second substrate including second connection pads and a logic circuit for driving the pixel array, wherein the first connection pads are located at a different level in the semiconductor device than the second connection pads; andconnection wirings that electrically connect the first connection pads to the second connection pads,wherein, in a plan view, pairs including one of the first connection pads and one of the second connection pads form a connection pad array, andwherein, in the plan view, at least one of the first connection pads partially overlaps at least one of the second connection pads.21. The semiconductor device of claim 20 , wherein claim 20 , in the plan view claim 20 , the first connection pads and the second connection pads have a same shape.22. The semiconductor device of claim 21 , wherein the same shape is an octagonal shape.23. The semiconductor device of claim 20 , wherein claim 20 , in the plan view claim 20 , each pair is a stage in which the first connection pad and the second connection pad are adjacent to one another in a horizontal direction claim 20 ...

System on integrated chips and methods of forming the same

A semiconductor device and methods of forming are provided. The method includes bonding a second die to a surface of a first die. The method includes encapsulating the second die in an isolation material, and forming a through via extending through the isolation material. The method also includes forming a first passive device in the isolation material.

HYBRID BOND USING A COPPER ALLOY FOR YIELD IMPROVEMENT

An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided. 19-. (canceled)10. A method for bonding a pair of semiconductor structures together , the method comprising:providing a pair of semiconductor structures comprising corresponding dielectric layers and corresponding metal features arranged in the dielectric layers, wherein the metal features comprise a copper alloy having copper and a secondary metal;bonding the semiconductor structures together to form a hybrid bond at an interface between the semiconductor structures, the hybrid bond comprising a first bond bonding the dielectric layers together and a second bond bonding the metal features together, and wherein the second bond comprises voids arranged between copper grains of the metal features; andperforming an anneal to the hybrid bond to form regions of the secondary metal along boundaries of the copper grains and to fill the voids with the secondary metal.11. The method according to claim 10 , wherein the metal features comprise a metal feature of the copper alloy claim 10 , wherein the hybrid bond further comprises a third bond bonding one of the dielectric layers to the metal feature claim 10 , and ...

4D DEVICE, PROCESS AND STRUCTURE

A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory. 161-. (canceled)62. An article of manufacture comprising a 4D device.63. The device of which includes a vertically stacked 3D component comprising at least one of a 2D-in-4D format claim 62 , 3D-in-4D format claim 62 , and 2D/3D-in-4D format claim 62 , connected to a horizontally stacked component comprising at least one of a 2D format and a 3D format.64. The device of wherein said horizontally stacked component comprises a 2D planar multicore logic device (2D).65. The device of wherein said horizontally stacked component comprises a 3D multi-stacked device with through-Si-vias (TSV) comprising at least one of TSV and 3D-TSV.66. The device of wherein said horizontally stacked component comprises at least one of a voltage regulating module (VRM) claim 63 , memory claim 63 , logic claim 63 , optoelectronics (O-E) claim 63 , III-V device claim 63 , micro-electro-mechanical (MEMS) stacks with TSV in the 3D stacks which comprises a 3D-TSV-combination.67. ...

Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device

A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers.

NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF

A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition. 1. A non-volatile memory device comprising:a memory cell array including memory cells respectively connected to bit lines; anda control logic unit configured to control a program operation with respect to the memory cells, wherein the control logic unit is further configured to:perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, andbased on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition,wherein the normal program verify condition comprises a normal program verify voltage, andthe initial program verify condition comprises an initial program verify voltage that is different from the normal program verify voltage.2. The non-volatile memory device of claim 1 , further comprising:a row decoder configured to drive a selected word line connected to the memory cells,wherein the row decoder is further configured to apply the normal program verify voltage to the selected word line during the normal program verify operation and to apply the initial program verify voltage to the selected word line during the initial program verify ...

MEMORY SYSTEM INCLUDING A NONVOLATILE MEMORY DEVICE, AND AN ERASING METHOD THEREOF

A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value. 1. A fail detecting method of a memory system comprising a nonvolatile memory device and a memory controller , the fail detecting method comprising:counting, by the memory controller, the number of erases of a word line connected to a pass transistor;issuing a first erase command, by the memory controller, when the number of erases reaches a reference value;applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value;detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; anddetermining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.2. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises increasing a source terminal voltage of the pass transistor.3. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises decreasing a gate terminal voltage of the pass transistor.4. The fail detecting method of claim 1 , ...

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING BUMP-CONTAINING BIT LINES AND METHODS FOR MANUFACTURING THE SAME

A semiconductor die can include an alternating stack of insulating layers and electrically conductive layers located on a substrate, memory stack structures extending through the alternating stack, drain regions located at a first end of a respective one of the vertical semiconductor channels of a memory stack structure, and bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions. At least of a subset of the bit lines includes bump-containing bit lines. Each of the bump-containing bit lines includes a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height. Bit line contact via structures overlie the bit lines and contact a bump portion of a respective one of the bump-containing bit lines. 1. A semiconductor structure comprising a first semiconductor die , wherein the first semiconductor die comprises:an alternating stack of insulating layers and electrically conductive layers located on a first substrate;memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film;drain regions located at a first end of a respective one of the vertical semiconductor channels;bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions by at least one conductive via structure, wherein at least a subset of the bit lines comprises bump-containing bit lines, and each of the bump-containing bit lines comprises a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height; andbit line contact via structures overlying the bit lines and contacting a bump portion of a respective one of the bump-containing bit lines.2. The semiconductor structure of claim 1 , wherein:the bit lines have a periodic pitch along a first horizontal direction and laterally ...

DEVICES, SYSTEMS, AND METHODS FOR STACKED DIE PACKAGES

A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view. 1. A package , comprising: a first chip including first bonding structures;', 'a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures; and', 'a first electrical contact on the second chip, wherein at least a portion of the first electrical contact does not overlap with the first chip in a plan view., 'a first chip stack including2. The package of claim 1 , wherein the first electrical contact is located at a first side of the second chip.3. The package of claim 2 , further comprising:a second electrical contact on the second chip and located at a second side of the second chip opposite the first side of the second chip.4. The package of claim 3 , wherein at least a portion of the second electrical contact does not overlap with the first chip in the plan view.5. The package of claim 1 , wherein claim 1 , in a cross sectional view claim 1 , a width of the first chip is less than a width of the second chip.6. The package of claim 1 , further comprising: a third chip including third bonding structures;', 'a fourth chip including fourth bonding structures facing the third bonding structures and bonded to the third bonding structures; and', 'a second electrical contact on the fourth chip, wherein at least a portion of the second electrical contact does not overlap with the third chip in the plan view; and, 'a second chip stack adhered to the first chip stack and includinga support substrate that supports the first chip stack and the second chip stack.7. The package of claim 6 , wherein claim 6 , in a ...

SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS OF THE SAME

A semiconductor device includes a first substrate structure and a second substrate structure. The first substrate structure includes a base substrate, circuit elements disposed on the base substrate, a first substrate disposed on the circuit elements, first memory cells disposed on the first substrate and electrically connected to the circuit elements, first bit lines disposed on the first memory cells and connected to the first memory cells, and first bonding pads disposed on the first bit lines to be connected to the first bit lines, respectively. The second substrate structure is connected to the first substrate structure on the first substrate structure, and includes a second substrate, second memory cells disposed on the second substrate, second bit lines disposed on the second memory cells and connected to the second memory cells, and second bonding pads disposed on the second bit lines to be connected to the second bit lines, respectively. The first substrate structure and the second substrate structure are connected to each other by bonding the first bonding pads to the second bonding pads, and the first bonding pads and second bonding pads are vertically between the first bit lines and the second bit lines, without the first substrate or second substrate disposed vertically between the first bit lines and the second bit lines. 1. A method for manufacturing a semiconductor device , comprising:forming a first substrate structure by forming first gate electrodes stacked and spaced apart from each other in a direction perpendicular to a first surface of a first substrate, first channels extending perpendicular to the first substrate while passing through the first gate electrodes, first bit lines connected to the first channels, and first bonding pads disposed on the first bit lines to be electrically connected to the first bit lines, respectively, on the first substrate;forming a second substrate structure by forming second gate electrodes stacked and spaced ...

A 3d semiconductor device and system

A 3D semiconductor device, the device including: a first crystalline silicon layer including a plurality of first transistors; a first metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of first logic gates; a first array of memory cells including second transistors; a second metal layer overlying the first and second transistors; a second crystalline silicon layer overlaying the second metal layer and the second crystalline silicon layer including a plurality of third transistors; a third metal layer interconnecting the third transistors, a portion of the third transistors forming a plurality of second logic gates; a second array of memory cells including fourth transistors and overlaying the second crystalline silicon layer; a fourth metal layer overlying the third and fourth transistors, where at least one of the fourth transistors is overlaying at least another one of the fourth transistors such that they are self-aligned, having been processed following the same lithography step, where the second array of memory cells include NAND flash type memory cells.

System on Integrated Chips and Methods of Forming Same

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die. 1. A package comprising:a first semiconductor die;a second semiconductor die bonded to the first semiconductor die, wherein a first dielectric layer of the first semiconductor die is directly bonded to a second dielectric layer of the second semiconductor die;a third semiconductor die bonded to the first semiconductor die, wherein the first dielectric layer of the first semiconductor die is directly bonded to a third dielectrics layer of the third semiconductor die;a first isolation material disposed around the second semiconductor die and the third semiconductor die, wherein the second semiconductor die is physically separated from the third semiconductor die by the first isolation material; anda redistribution structure electrically connected to the first semiconductor die, the second semiconductor die, and the third semiconductor die.2. The package of claim 1 , wherein the redistribution structure is disposed on an opposing side of the first semiconductor die as the second semiconductor die and the third semiconductor die.3. The package of claim 1 , wherein the redistribution structure is electrically connected to the second semiconductor die by a conductive via extending through a second isolation material claim 1 , and wherein the first semiconductor die is physically separated from the conductive via by the second isolation material.4. The package of claim 3 , wherein the second ...

Interconnect Chips

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die. 1. A package comprisinga first device die and a second device die;an interconnect die bonded to the first device die and the second device die, wherein the interconnect die electrically connects the first device die to the second device die;an encapsulating material encapsulating the interconnect die therein; anda through-via penetrating through the encapsulating material to connect to the first device die.2. The package of further comprising an integrated passive device bonded to one of the first device die or the second device die.3. The package of further comprising an underfill comprisinga first portion between the first device die and the interconnect die; anda second portion between the first device die and the second device die.4. The package of claim 1 , wherein a first surface of the encapsulating material is coplanar with a second surface of the interconnect die.5. The package of further comprising a die-attach film underlying and contact a bottom surface of the interconnect die claim 1 , wherein the die-attach film is in the encapsulating material.6. The package of further comprising:a dielectric layer; anda first redistribution line comprising a via portion extending into the dielectric layer, and a line portion over the dielectric layer, wherein the die-attach film is over and contacting the line portion.7. The package of further comprising:a second redistribution line extending into the dielectric layer, wherein the through-via overlies and contacts a top ...

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

A semiconductor device structure is provided. The semiconductor device structure includes a first polymer layer formed between a first substrate and a second substrate, and a first conductive layer formed over the first polymer. The semiconductor device includes a first through substrate via (TSV) formed over the first conductive layer, and the conductive layer is in direct contact with the first TSV and the first polymer. 1. A semiconductor device structure , comprising:a first polymer layer formed between a first substrate and a second substrate;a first conductive layer formed over the first polymer; anda first through substrate via (TSV) formed over the first conductive layer, wherein the conductive layer is in direct contact with the first TSV and the first polymer.2. The semiconductor device structure as claimed in claim 1 , further comprising:an interconnect structure formed over the first substrate, wherein the interconnect structure is in direct contact with the first TSV.3. The semiconductor device structure as claimed in claim 1 , further comprising:a first transistor formed in the first substrate; anda first contact plug formed below the first transistor, wherein a bottom surface of the first contact plug is level with a bottom surface of the first TSV.4. The semiconductor device structure as claimed in claim 3 , wherein a sidewall of the first contact plug is aligned with a sidewall of the first conductive layer.5. The semiconductor device structure as claimed in claim 1 , further comprising:a second TSV formed in the second substrate, wherein a first width of the first TSV is smaller than a second width of the second TSV.6. The semiconductor device structure as claimed in claim 5 , further comprising:a second polymer layer formed between the first substrate and the second substrate; anda second conductive layer formed below the second polymer layer, wherein the second conductive layer is in direct contact with the second polymer layer and the second TSV ...

NON-VOLATILE MEMORY DEVICE

A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines. 1. A non-volatile memory device comprising:a memory cell region including a first metal pad;a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region; anda control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines,wherein the control logic circuit is configured to:apply a program word line voltage with a voltage level changed stepwise to a selected word line connected to the plurality of memory cells, the program word line voltage including a first voltage level during a first time interval and a second voltage level different from the first voltage level during a subsequent second time interval;apply a program bit line voltage to a first bit line of the plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line;when the program bit line voltage has a program inhibit voltage level, inhibit the plurality of first ...

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

SEMICONDUCTOR PACKAGE INCLUDING AN IMAGE SENSOR CHIP AND A METHOD OF FABRICATING THE SAME

Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip. 1. A semiconductor package , comprising:a semiconductor chip structure;a transparent substrate disposed on the semiconductor chip structure;a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate; andan adhesive layer interposed between the dam and the semiconductor chip structure,wherein the semiconductor chip structure includes an image sensor chip and a logic chip, which are in contact with each other, wherein the image sensor chip is closer to the transparent substrate than the logic chip, andwherein widths of the image sensor chip and the logic chip are less than a width of the transparent substrate.2. The semiconductor package of claim 1 ,wherein the image sensor chip comprises a micro lens array, which is provided in a center region of the image sensor chip,wherein the logic chip comprises a through electrode, andwherein the through electrode overlaps the micro lens array.3. The semiconductor package of claim 1 , wherein a sidewall of the image sensor chip is aligned with a sidewall of the logic chip.4. The semiconductor package of claim 1 , wherein the adhesive layer is extended to be in contact with a sidewall of the dam and a surface of the transparent substrate.5. The semiconductor package of claim 1 ,wherein the image sensor chip ...

IMAGE SENSOR USING A BOOSTING CAPACITOR AND A NEGATIVE BIAS VOLTAGE

An image sensor includes a photodiode generating a charge in response to light, a transfer transistor connecting the photodiode and a floating diffusion, a reset transistor connected between the floating diffusion and a power node, a boosting capacitor connected to the floating diffusion, and adjusting a capacity of the floating diffusion in response to a boosting control signal, and a bias circuit having first and second current circuits for supplying different bias currents to an output node to which a voltage signal corresponding to a charge accumulated in the floating diffusion is output. The boosting control signal decreases from a high level to a low level after the transfer transistor is turned off, and the reset transistor is switched from a turned on state to a turned off state when the bias currents of the first and second current circuits are simultaneously provided to the output node. 1. An image sensor , comprising:a photodiode configured to generate a charge in response to light;a transfer transistor connecting the photodiode and a floating diffusion in response to a transmission control signal;a reset transistor connected between the floating diffusion and a power node;a boosting capacitor connected to the floating diffusion, and configured to adjust a capacity of the floating diffusion in response to a boosting control signal; anda bias circuit having a first current circuit and a second current circuit configured to supply different bias currents to an output node to which a voltage signal corresponding to a charge accumulated in the floating diffusion is output,wherein the boosting control signal decreases from a high level to a low level after the transfer transistor is turned off, andthe reset transistor is switched from a turned on state to a turned off state during a first time at which a first bias current of the first current circuit and a second bias current of the second current circuit are simultaneously provided to the output node.2. The ...

TRAP RICH LAYER FOR SEMICONDUCTOR DEVICES

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer. 130.-. (canceled)31. A method of fabricating an integrated circuit , comprising:forming a first active layer in a first semiconductor wafer, wherein the first active layer comprises a first active device layer and a first metallization layer;creating a trap rich layer in a second semiconductor wafer;bonding the second semiconductor wafer to the first semiconductor wafer to form a bonded structure;forming a second active layer in the second semiconductor wafer, wherein the second active layer comprises a second active device layer and a second metallization layer; andelectrically interconnecting the first and second metallization layers.32. The method of claim 31 , wherein the trap rich layer is between the first active device layer and the second active device layer in the bonded structure.33. The method of claim 31 , further comprising removing a portion of the second semiconductor wafer before the trap rich layer is created in the second semiconductor wafer.33. The method of claim 31 , wherein the forming of the second active layer is performed after the bonding.34. The method of claim 31 , wherein the forming of the second active layer is performed before the bonding.35. The method of claim 31 , wherein the forming comprises forming the first active device layer above an insulator layer in the first semiconductor wafer.36. The method of claim 31 , wherein the forming of the second active layer comprises forming the second active device layer above an insulator layer in the second semiconductor wafer.37. The method of claim 31 , further comprising providing a bonding layer on a bottom surface of the second ...

PAGE BUFFER CIRCUITS AND NONVOLATILE MEMORY DEVICES INCLUDING THE SAME

A nonvolatile memory device includes a memory cell array including memory cells and a page buffer circuit. The page buffer circuit includes page buffer units and cache latches. The cache latches are spaced apart from the page buffer units in a first horizontal direction, and correspond to respective ones of the plurality of page buffer units. Each of the page buffer units includes a pass transistor connected to each sensing node and driven in response to a pass control signal. The page buffer circuit being configured to perform a data transfer operation, based on performing a first data output operation to output data, provided from a first portion of page buffer units, from a first portion of cache latches to a data input/output (I/O) line, the data transfer operation configured to dump sensed data from a second portion of page buffer units to a second portion of cache latches. 1. A nonvolatile memory device comprising:a memory cell array including a plurality of memory cells; anda page buffer circuit including a plurality of page buffer units and a plurality of cache latches, the plurality of page buffer units in a first horizontal direction and connected to each of the memory cells through a plurality of bit-lines, the plurality of cache latches being spaced apart from the plurality of page buffer units in the first horizontal direction, the plurality of cache latches corresponding to respective ones of the plurality of page buffer units,each of the plurality of page buffer units including a pass transistor connected to each sensing node and driven in response to a pass control signal, andthe page buffer circuit being configured to perform a data transfer operation, based on performing a first data output operation to output data, provided from a first portion of page buffer units among the plurality of page buffer units, from a first portion of cache latches among the plurality of cache latches to a data input/output (I/O) line, the data transfer operation ...

Semiconductor Die Package and Method of Manufacture

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

SEMICONDUCTOR ELEMENT

A first semiconductor element according to one embodiment of the present disclosure includes: an element substrate including an element region in which a wiring layer and a first semiconductor layer including a compound semiconductor material are provided as a stack, and a peripheral region outside the element region; a readout circuit substrate opposed to the first semiconductor layer with the wiring layer interposed therebetween, and electrically coupled to the first semiconductor layer with the wiring layer interposed therebetween; a first electrode provided in the wiring layer and electrically coupled to the first semiconductor layer; a second electrode opposed to the first electrode with the first semiconductor layer interposed therebetween; and an insulating layer provided on the second electrode and having a non-reducing property. 1. A semiconductor element comprising:an element substrate including an element region in which a wiring layer and a first semiconductor layer including a compound semiconductor material are provided as a stack, and a peripheral region outside the element region;a readout circuit substrate opposed to the first semiconductor layer with the wiring layer interposed therebetween, and electrically coupled to the first semiconductor layer with the wiring layer interposed therebetween;a first electrode provided in the wiring layer and electrically coupled to the first semiconductor layer;a second electrode opposed to the first electrode with the first semiconductor layer interposed therebetween; andan insulating layer provided on the second electrode and having a non-reducing property.2. The semiconductor element according to claim 1 , wherein the insulating layer includes any one of an oxide (MO) claim 1 , a nitride (MN) claim 1 , and an oxynitride (MON)(M is any one of silicon (Si), titanium (Ti), hafnium (Hf), zirconium (Zr), and yttrium (Y); x, y, and z are integers of 1 or greater).3. The semiconductor element according to claim 1 , ...

Solid-state imaging element and imaging device

The signal quality of a solid-state imaging element configured to detect address events is enhanced. The solid-state imaging element has open pixels and light-blocked pixels arrayed therein. In the solid-state imaging element, the open pixels each detect whether or not an amount of change in incident light amount exceeds a predetermined threshold, and output a detection signal indicating a result of the detection. On the other hand, in the solid-state imaging element, the light-blocked pixels each output a correction signal based on an amount of noise generated in the open pixels each configured to detect whether or not an amount of change in incident light amount exceeds the predetermined threshold and to output a detection signal indicating a result of the detection.

Integrated circuit device structures and double-sided fabrication techniques

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

SEMICONDUCTOR DEVICE PRODUCTION METHOD

A semiconductor device production method includes forming a first recess portion in a first insulating film formed on a first substrate and a first conductive layer on the front surface of the first insulating film located inside and outside the first recess portion. In the first recess portion, a first pad is formed having a width of 3 μm or less and including the first conductive layer by performing a first polishing the first conductive layer at a first polishing rate and, after the first polishing, a second polishing the first conductive layer at a second polishing rate lower than the first polishing rate. The first pad of the first substrate and a second pad of a second substrate are joined together by annealing the first substrate and the second substrate. The selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4. 1. A semiconductor device production method comprising:forming a first recess portion in a first insulating film formed on a first substrate;forming a first conductive layer on a front surface of the first insulating film located both inside and outside the first recess portion;forming, in the first recess portion, a first pad having a width of 3 μm or less and including the first conductive layer by performing a first process of polishing the first conductive layer at a first polishing rate and, after the first process, a second process of polishing the first conductive layer at a second polishing rate which is lower than the first polishing rate, wherein the second process is performed such that a selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4; andjoining the first pad of the first substrate and a second pad of a second substrate together by annealing the first substrate and the second substrate.2. The semiconductor device production method according to claim 1 , wherein the first conductive layer contains copper.3. The semiconductor device production method according to ...

POST CMP PROCESSING FOR HYBRID BONDING

Devices and techniques include process steps for forming openings through stacked and bonded structures. The openings are formed by pre-etching through one or more layers of prepared dies after planarization of the bonding layer (by chemical-mechanical polishing (CMP) or the like) and prior to bonding. For instance, the openings are etched through one or more layers of dies to be bonded prior to bonding the dies to form an assembly. 1. A microelectronic assembly , comprising:a first substrate having a bonding surface, the bonding surface of the first substrate having a planarized topography;a first plurality of electrically conductive features at the bonding surface of the first substrate;a second substrate having a bonding surface, the bonding surface of the second substrate having a planarized topography and bonded to the bonding surface of the first substrate;a second plurality of electrically conductive features at the bonding surface of the second substrate and bonded to the first plurality of electrically conductive features; andone or more electrically conductive contact pads disposed within an insulating layer of the second substrate and below the bonding surface of the second substrate, the one or more electrically conductive contact pads disposed in an area different from the first plurality of electrically conductive features and the second plurality of electrically conductive features.2. The microelectronic assembly of claim 1 , further comprising one or more secondary openings in the insulating layer of the second substrate aligned to the one or more electrically conductive contact pads claim 1 , the one or more secondary openings extending from the bonding surface of the second substrate to the one or more electrically conductive contact pads claim 1 , providing access to the one or more electrically conductive contact pads.3. The microelectronic assembly of claim 2 , further comprising one or more primary openings in an insulating layer of the first ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor structure includes a first substrate, a first dielectric layer disposed over the first substrate, a plurality of first bonding pads disposed in the first dielectric layer, a plurality of second bonding pads disposed in the first dielectric layer, a second substrate, and a second dielectric layer disposed over the second substrate. The first bonding pads have a first width. The second bonding pads have a second width greater than the first width. The second bonding pads are arranged to form a frame pattern surrounding the first bonding pads. A portion of the second dielectric layer is in physical contact with the second bonding pads. The first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows. Two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row. 2. The conductor structure of claim 1 , wherein the second bonding pads are disposed adjacent to edges or a corner of the first substrate.3. The semiconductor structure of claim 1 , further comprising plurality of third bonding pads disposed in the second dielectric layer claim 1 , wherein the third bonding pads comprises a third width different from the first width of the first bonding pads.4. The semiconductor structure of claim 3 , wherein each of the third bonding pads is in physical contact with a portion of the one of the first bonding pads or a portion of the one of the second bonding pads.5. The semiconductor structure of claim 3 , wherein the second width is substantially greater than the third width.6. The semiconductor structure of claim 3 , wherein the third width of the third bonding pads is the same as the first width of the first bonding pads.7. The semiconductor structure of claim 3 , further comprising a plurality of fourth bonding pads disposed in the second dielectric layer claim 3 , wherein the fourth bonding pad comprises a fourth width greater than the third width.8. ...

HYBRID BONDING USING DUMMY BONDING CONTACTS

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface. 1. A method for forming a semiconductor device , comprising:forming a first interconnect layer comprising a plurality of first interconnects above a first substrate;forming a first bonding layer comprising a plurality of first bonding contacts above the first interconnect layer, such that each of the first interconnects is in contact with a respective one of the first bonding contacts;forming a second interconnect layer comprising a plurality of second interconnects above a second substrate;forming a second bonding layer comprising a plurality of second bonding contacts above the second interconnect layer, such that at least one of the second bonding contacts is in contact with a respective one of the second interconnects, and at least another one of the second bonding contacts is separated from the second interconnects; andbonding the first substrate and the second substrate in a face-to-face manner, such that each of the first bonding contacts is in contact with one of the ...

CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface. 1. A microelectronic device comprising:a dielectric-to-dielectric direct bond between a first die and a second die, the first die and the second die being direct-bonded together at a bonding interface;a metal-to-metal direct bond at the bonding interface forming a conductive interconnect between the first die and the second die; anda capacitive interconnect between the first die and the second die formed at the bonding interface,wherein the conductive interconnect comprises one of (i) a direct-bonded power interconnect or (ii) a direct-bonded ground interconnect, andwherein the capacitive interconnect comprises a signal line between the first die and the second die.2. The microelectronic device of claim 1 , wherein the capacitive interconnect comprises:a first layer of a first dielectric medium on a first metal of the first die; anda second layer of a second dielectric medium on a second metal of the second die.3. The microelectronic ...

BONDED THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MAKING THE SAME BY REPLACING CARRIER SUBSTRATE WITH SOURCE LAYER

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer. 1. A semiconductor structure comprising a memory die bonded to a logic die , the memory die comprising:an alternating stack of insulating layers and electrically conductive layers;memory openings extending through the alternating stack;memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film;a source layer having a front side electrically connected to first end portions of the vertical semiconductor channels that are distal from an interface between the logic die and the memory die;an electrically conductive layer connected to a back side of the source layer; andbackside bonding pads electrically connected to the electrically conductive layer.2. The semiconductor structure of claim 1 , wherein electrically conductive layer comprises a source power supply network.3. The semiconductor structure of claim 2 , wherein the source power supply network comprises backside metal interconnect structures embedded in a backside isolation dielectric layer and contacting the source layer at multiple locations.4. The semiconductor structure of claim 3 , wherein the source power supply network comprises:a network of metal lines; ...

SEMICONDUCTOR COOLING STRUCTURE AND METHOD IN A MIXED BONDING PROCESS

The invention provides a semiconductor cooling structure and method in a mixed bonding process, and comprises: providing two wafers which require to be treated by a mixed bonding process, each of the wafers being provided with several metallic device structure layers therein; a heat dissipation layer is set in at least one of the wafer, the heat dissipation layer is arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer; wherein material of each of the heat dissipation layers is good conductors of heat. The invention can make heat generated during bonding process transfer and distribute evenly. 1. A semiconductor cooling method in a mixed bonding process , comprising:providing two wafers which require to be treated by a mixed bonding process, each of the wafers being provided with several metallic device structure layers therein;a heat dissipation is arranged in at least one of the wafers, said heat dissipation layer is arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer;wherein, material of each of said heat dissipation layers is good conductors of heat.2. The semiconductor cooling method in a mixed bonding process as claimed in claim 1 , wherein the material of said heat dissipation layers is metal.3. The semiconductor cooling method in a mixed bonding process as claimed in claim 1 , wherein said heat dissipation layer claim 1 , through several holes claim 1 , connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer.4. The semiconductor cooling method in a mixed bonding process as claimed in claim 3 , wherein said several holes uniformly distribute in a ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes: a first substrate including a first surface layer that includes first and second electrodes; a second substrate including a second surface layer that includes third and fourth electrodes, and directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; and a functional film provided between the second and fourth electrodes. The first and third electrodes are bonded together so as to be in contact with each other, and the second electrode, the functional film, and the fourth electrode constitute a passive element. 1. A semiconductor device comprising:a first substrate including a first substrate body, and a first surface layer that is provided over a principal surface of the first substrate body, and includes a first surface film, a first electrode having a first surface exposed at an outermost surface of the first surface film, and a second electrode having a second surface exposed at the outermost surface of the first surface film;a second substrate including a second substrate body, and a second surface layer that is provided over a principal surface of the second substrate body, and includes a second surface film, a third electrode having a third surface exposed at an outermost surface of the second surface film, and a fourth electrode having a fourth surface exposed at the outermost surface of the second surface film, where the second substrate is directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; anda functional film provided between the second surface of the second electrode and the fourth surface of the fourth electrode, whereinthe first surface of the first electrode and the third surface of the third electrode are bonded together so as to be in contact with each other, andthe second electrode, the functional film, and the fourth electrode constitute a passive element.2. The semiconductor device of claim ...

PHOTOELECTRIC CONVERSION APPARATUS, PHOTOELECTRIC CONVERSION SYSTEM, AND MOVING BODY

A photoelectric conversion apparatus includes one or more first avalanche diodes, a first processing circuit configured to be connected to the first avalanche diode(s), one or more second avalanche diodes, and a second processing circuit configured to be connected to the second avalanche diode(s), wherein the first avalanche diode(s) is/are configured to be connected to the second processing circuit by a selection circuit. 1. A photoelectric conversion apparatus comprising:one or more first avalanche diodes;a first processing circuit configured to be connected to the first avalanche diode(s);one or more second avalanche diodes; anda second processing circuit configured to be connected to the second avalanche diode(s),wherein the first avalanche diode(s) is/are configured to be connected to the second processing circuit by a selection circuit, andwherein the second avalanche diode(s) is/are configured to be connected to the first processing circuit by the selection circuit.2. The photoelectric conversion apparatus according to claim 1 , wherein the first and second processing circuits each include a counting unit configured to count the signals from the first and second avalanche diodes.3. The photoelectric conversion apparatus according to claim 2 , wherein the selection circuit is configured to select which to input the signal from the first avalanche diode(s) to claim 2 , the first processing circuit or the second processing circuit claim 2 , and select which to input the signal from the second avalanche diode(s) to claim 2 , the first processing circuit or the second processing circuit.4. The photoelectric conversion apparatus according to claim 3 ,wherein the selection circuit includes a first switch and a second switch,wherein the first switch is configured to control connection and disconnection of the first avalanche diode(s) to/from the first processing circuit, andwherein the second switch is configured to control connection and disconnection of the first ...

BOND PAD STRUCTURE FOR LOW TEMPERATURE FLIP CHIP BONDING

Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads. 1. A device comprising:a first and a second semiconductor device having first and second bond pads, respectively, bonded together through the first and second bond pads, the first and second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having a configuration rotated with respect to a configuration of the metal segments of the second bond pad,wherein the metal segments of the first bond pad on the first semiconductor device comprise only columns of segments, the columns being staggered with respect to each other, and the metal segments of the second bond pad on the second semiconductor device comprise only rows of segments, the rows being staggered with respect to each other, wherein the columns of segments are perpendicular to the rows of segments.2. The device according to claim 1 , wherein the first bond pad on the first semiconductor device is larger than the second bond pad on the second semiconductor device.3. The device according to claim 1 , wherein the first and second bond pads each have plural copper segments.4. The device according to claim 1 , wherein the first configuration is rotated at a 45 degree to a 90 degree angle with respect to the second ...

SOLID-STATE IMAGING DEVICE AND IMAGING SYSTEM

A solid-state imaging device includes a first substrate, a second substrate, an electrode portion, a first substrate connecting portion, an electrostatic protection circuit, and a second substrate connecting portion. A photoelectric conversion element is disposed on the first substrate. A part of the peripheral circuit is arranged on the second substrate. The electrode portion has a connection surface. The first substrate connecting portion electrically connects the electrode portion and the second substrate. The electrostatic protection circuit is connected to a circuit between the first substrate connecting portion and the peripheral circuit. The second substrate connecting portion electrically connects the peripheral circuit and the photoelectric conversion element. The electrostatic protection circuit is disposed at a position such that the electrostatic protection circuit does not overlap any of the first substrate connecting portion and the second substrate connecting portion. 1. A solid-state imaging device comprising:a first substrate on which a photoelectric conversion element is arranged;a second substrate laminated and disposed on the first substrate, at least a part of a peripheral circuit being arranged on the second substrate, the peripheral circuit including a control circuit and a readout circuit configured to read a signal based on an electric charge of the photoelectric conversion element;an electrode portion provided on the first substrate and having a connection surface provided so as to be electrically connectable toward outside of the first substrate;a first substrate connecting portion disposed between the first substrate and the second substrate, the first substrate connecting portion electrically connecting the electrode portion and the second substrate;an electrostatic protection circuit provided on the second substrate, the electrostatic protection circuit being connected to a circuit between the first substrate connecting portion and the ...

Three-dimensional memory device with static random-access memory

Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In certain embodiments, the 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes an array of SRAM cells and a first bonding layer, and the second semiconductor structure includes an array of 3D NAND memory strings and a second bonding layer. The first semiconductor structure is attached with the second semiconductor structure through the first bonding layer and the second bonding layer. The array of 3D NAND memory strings and the array of SRAM cells are coupled through a plurality of bonding contacts in the first bonding layer and the second bonding layer and are arranged at opposite sides of the plurality of bonding contacts.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING HYBRID BONDING INTERFACE

The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases. 1. A method of manufacturing a semiconductor device , comprising:forming a dielectric layer on a substrate;etching the dielectric layer to create a plurality of openings in the dielectric layer;applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer;forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed;removing the sacrificial layer to form at least one air gap in the dielectric layer; andforming a plurality of protrusions on the bases.2. The method of claim 1 , wherein in a pair of openings claim 1 , only a portion of the dielectric layer is covered by the sacrificial layer.3. The method of claim 1 , wherein the first conductive feature and the bases are arranged in an interleaved configuration.4. The method of claim 1 , wherein the first conductive feature and the bases are formed using a plating process.5. The method of claim 4 , wherein the first conductive feature claim 4 , the bases and the protrusions have the same material.6. The method of claim 1 , wherein the formation of the protrusions comprises:applying a patterned mask comprising a plurality of through holes on the dielectric layer, the ...

Memory device including pass transistors

A memory device includes an active region with a drain; a plurality of memory blocks arranged in a first direction; and a plurality of pass transistors formed in the active region and sharing the drain, each one of the plurality of pass transistors configured to transfer an operating voltage from the drain to a corresponding one of the plurality of memory blocks in response to a block select signal. The plurality of pass transistors is divided into first pass transistors and second pass transistors. A channel length direction of the first pass transistors and a channel length direction of the second pass transistors are different from each other.

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes a first chip and a second chip. The first chip includes a semiconductor substrate, transistors, a first interconnect, and first bonding electrodes. The second chip includes a memory cell array and second bonding electrodes. The second bonding electrodes are bonded to the first bonding electrodes. The first chip or the second chip has bonding pad electrodes. The second bonding electrodes include third bonding electrodes and fourth bonding electrodes. The third and fourth bonding electrodes overlap the memory cell array. The third bonding electrodes are in a current pathway between the memory cell array and the transistors whereas the fourth bonding electrodes are not in such a current pathway. The first interconnect is electrically connected to a bonding pad electrode and a fourth bonding electrode directly, without a current path via any one of transistors. 1. A semiconductor storage device , comprising:a first chip including a semiconductor substrate, a plurality of transistors, a first interconnect, and a plurality of first bonding electrodes;a second chip including a memory cell array and a plurality of second bonding electrodes, the second bonding electrodes being bonded to the first bonding electrodes; anda plurality of bonding pad electrodes on the first chip or the second chip, the bonding pad electrodes being connectable to bonding wires, wherein{'claim-text': ['third bonding electrodes that overlap the memory cell array and are in a current pathway between the memory cell array and the transistors; and', 'fourth bonding electrodes that overlap the memory cell array but are not in a current pathway between the memory cell array and the transistors,'], '#text': 'the plurality of second bonding electrodes includes:'}the first interconnect is electrically connected to a bonding pad electrode in the plurality of bonding pad electrodes without via any of the transistors being in the electrical connection between the bonding ...

Interface structures and methods for forming same

A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.

Systems and methods for efficient transfer of semiconductor elements

Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.

Buffer layer(s) on a stacked structure having a via

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

IMAGE SENSOR

An image sensor is provided. The image sensor includes a first substrate; a plurality of photoelectric conversion units positioned in the first substrate; a first connection layer disposed on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; a plurality of second pixel pads respectively positioned on the plurality of first pixel pads; a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a pitch of the plurality of first pixel pads is substantially the same as a pitch of the plurality of pixel regions of the first substrate. 1. An image sensor comprising:a first substrate comprising a pixel array region comprising a plurality of pixel regions and a peripheral region around the pixel array region;a plurality of photoelectric conversion units respectively positioned in the plurality of pixel regions of the first substrate;a first connection layer disposed on the pixel array region and the peripheral region of the first substrate;a plurality of first pixel pads disposed on a portion of the first connection layer on the pixel array region of the first substrate;a plurality of first peripheral pads disposed on a portion of the first connection layer on the peripheral region of the first substrate;a plurality of second pixel pads respectively positioned on the plurality of first pixel pads;a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads;a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads;a device disposed on the second connection layer; anda ...

Apparatus And Method For Verification Of Bonding Alignment

Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node. 1. A device comprising:a common node disposed in a first wafer;a test node disposed in the first wafer and having a plurality of test pads exposed at a first surface of the first wafer, the test node further having a plurality of test node lines separated by a first spacing and exposed at a second surface of the first wafer and each connected to a respective one of the plurality of test pads; anda comb disposed in a second wafer and having a plurality of comb lines having a second spacing different from the first spacing, each of the comb lines having a first surface exposed at a first side of the second wafer.2. The device of claim 1 , wherein the common node includes a common node pad exposed at the first surface of the first wafer and further includes a plurality of common node lines exposed at the second surface of the first wafer claim 1 , the common node lines being separated by the first spacing.3. The device of claim 1 , wherein respective test node lines of the plurality of test node lines comprises substantially straight conductive line segments extending from the first surface of the first wafer to the second surface of the first wafer.4. The device of claim 1 , wherein at ...

COMPOSITE BOND STRUCTURE IN STACKED SEMICONDUCTOR STRUCTURE

A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer. 1. A semiconductor device , comprising:a substrate;a dielectric structure disposed on the substrate;a top metal layer disposed in the dielectric structure; anda bonding structure disposed on the dielectric structure and the top metal layer, and the bonding structure comprising:a silicon oxide layer disposed on the dielectric structure;a silicon oxy-nitride layer covering the silicon oxide layer and physically contacting the silicon oxide layer;a conductive bonding layer disposed in the silicon oxide layer and the silicon oxy-nitride layer; anda barrier layer covering a sidewall and a bottom of the conductive bonding layer.2. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation claim 1 , a top surface of the silicon oxy-nitride layer is at a second elevation claim 1 , and a result of the first elevation minus the second elevation ranges from substantially −50 angstroms to substantially 100 angstroms.3. The semiconductor device of claim 1 , wherein a top surface of the conductive bonding layer is at a first elevation claim 1 , a top surface of the silicon oxy-nitride layer is at a second elevation claim 1 , and a result of the first elevation minus the second ...

Semiconductor device and electronic apparatus

The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The, and the first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.

Interconnect Structure and Method of Forming Same

A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component. 1. A semiconductor device comprising:a first conductive plug, the first conductive plug having a first width adjacent to a semiconductor substrate and having a second width adjacent to a first metallization layer within a first die, the second width being smaller than the first width;a second conductive plug, the second conductive plug having a third width adjacent to the semiconductor substrate, a fourth width adjacent to the first metallization layer, and a fifth width adjacent to a second metallization layer of a second die; anda dielectric liner continuously extending to be in contact with both the first conductive plug and the second conductive plug, the dielectric liner remaining outside of the first metallization layer.2. The semiconductor device of claim 1 , wherein the first conductive plug is in physical contact with a conductive portion of the first metallization layer.3. The semiconductor device of claim 2 , wherein the first conductive plug extends into the conductive portion of the first metallization layer.4. The semiconductor device of claim 2 , wherein the conductive portion of the first metallization layer is adjacent to an interface between the semiconductor substrate and the first metallization layer.5. The semiconductor device of claim 2 , wherein ...

Memory device with improved program performance and method of operating the same

A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

MEMORY DEVICE

A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery. 1. A memory device comprising:a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit controlling the first memory cells and disposed below the first memory cell array;a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit controlling the second memory cells and disposed below the second memory cell array; anda pad area including a power wiring, wherein:the first memory area includes a first local lockout circuit determining whether to lock out during an operation of the first memory area,the second memory area includes a second local lockout circuit determining whether to lock out separately from the first memory area during an operation of the second memory area,the first memory area and the second memory area are included in a single semiconductor chip to share the pad area, andwhile the first memory area performs a first operation, the second memory area performs a second operation, and each of the first operation and the second operation ...

Method of fabricating a semiconductor device

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE POLYMER LINER AND METHOD FOR FORMING THE SAME

The present disclosure relates to a semiconductor device structure with a conductive polymer liner and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first metal layer disposed over a semiconductor substrate, and a second metal layer disposed over the first metal layer. The semiconductor device structure also includes a conductive structure disposed between the first metal layer and the second metal layer. The conductive structure includes a first conductive via and a first conductive polymer liner surrounding the first conductive via.

Integrated Circuit Package and Method

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device is provided. The semiconductor device includes a base layer having a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device includes a stack of alternating word line layers and insulating layers that is positioned over the first side of the base layer, where the stack includes a first region and a second region. A channel structure extends through the first region of the stack in a vertical direction and further extends into the base layer from the first side. A plurality of connection structures are formed over the second side of the base layer and include a first connection structure that is coupled to the channel structure. 1. A semiconductor device , comprising:a base layer having a first side for forming memory cells and a second side that is opposite to the first side;a stack of alternating word line layers and insulating layers positioned over the first side of the base layer, the stack including a first region and a second region;a channel structure extending through the first region of the stack along a vertical direction and further extending into the base layer from the first side; anda plurality of connection structures formed over the second side of the base layer and including a first connection structure that is coupled to the channel structure.2. The semiconductor device of claim 1 , further comprising:a doped region formed in the second side of the base layer and coupled to the channel structure; anda first dielectric layer formed over the second side of the base layer, the connection structures extending through the first dielectric layer so that the first connection structure of the connection structures is in direct contact with the doped region.3. The semiconductor device of claim 2 , further comprising:a second dielectric layer arranged in the base layer between the first side and the second side.a third dielectric layer formed over a first surface of the second ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a first substrate, a first insulating film provided on the first substrate, and a first plug provided in the first insulating film. The device further includes a first layer provided on the first insulating film and a first metal layer provided on the first plug in the first layer and electrically connected to the first plug. The device further includes a second metal layer including a first portion provided in the first layer and a second portion provided on the first layer and electrically connected to the first metal layer.

Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.

PAD-OUT STRUCTURE FOR XTACKING ARCHITECTURE

The present disclosure provides a method of fabricating a semiconductor device. The method can include bonding a first die and a second die face to face, the first die including a substrate, transistors formed on a face side of the first die over a semiconductor layer with an insulating layer between the substrate and the semiconductor layer, and a first contact structure on the face side of the first die extending through the insulating layer. The method can also include exposing the first contact structure from the back side of the first die, forming, from the back side of the first die, a contact hole in the insulating layer to expose the semiconductor layer, and forming, on the back side of the first die, a first pad-out structure connected with the first contact structure and a second pad-out structure, on the contact hole, conductively connected with the semiconductor layer.

3D PROCESSOR

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies. 120.-. (canceled)21. A three dimensional (3D) processor circuit , comprising:a first integrated circuit (IC) die comprising a first processor core; anda second IC die vertically mounted on the first IC die and comprising a first cache for the first processor core,wherein the first processor core on the first IC die overlaps with the first cache on the second IC die.22. The 3D processor circuit of claim 21 , further comprising a plurality of z-axis connections between the first processor core and the first cache.23. The 3D processor circuit of claim 22 , wherein the plurality of z-axis connections comprise a z-axis bus claim 22 , the z-axis bus being wholly defined within an x-y cross-section of the first processor core and the first cache.24. The 3D processor circuit of claim 22 , wherein at least two of the plurality of z-axis ...

THREE-DIMENSIONAL MEMORY DEVICE WITH VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF

A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

Bonded three-dimensional memory devices and methods for forming the same

Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.

Semiconductor storage device

A semiconductor storage device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a first semiconductor layer that extends in the first direction and faces the plurality of first conductive layers, a first gate insulating film that extends in the first direction and covers an outer peripheral surface of the first semiconductor layer, a first insulating layer that extends in the first direction and has an outer peripheral surface covered with the first semiconductor layer, and a second conductive layer that is farther from the substrate than the plurality of first conductive layers and is connected to one end in the first direction of the first semiconductor layer. The first semiconductor layer includes a first region facing the plurality of first conductive layers and a second region farther from the substrate than the first region. The second conductive layer is connected to an inner peripheral surface and an outer peripheral surface of the second region of the first semiconductor layer and is in contact with one end in the first direction of the first insulating layer.

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes first and second stacks, and first to fourth semiconductor layers. The first stack includes first conductive layers and first insulating layers alternately stacked in a first direction. The first semiconductor layer extends through the first stack. The second semiconductor layer extends in a second direction above the first stack and connected to the first semiconductor layer. The second stack includes second conductive layers and second insulating layers alternately stacked in the first direction. The first and second stacks are arranged in a third direction. The third semiconductor layer extends through the second stack. The fourth semiconductor layer extends in the second direction above the second stack and connected to the third semiconductor layer. A third conductive layer is in contact with upper surfaces of the second and fourth semiconductor layers. The second and fourth semiconductor layers are separated from each other in the third direction.

THREE-DIMENSIONAL MEMORY DEVICE WITH VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF

A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom electrode, a metal oxide semiconductor vertical transistor channel, a cylindrical gate dielectric, and a top electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

Semiconductor device and method for manufacturing the same

A semiconductor device includes: a plurality of first electrode films stacked in a state of being insulated from each other; a plurality of semiconductor members extending in a stacked direction of the plurality of first electrode films in a stacked body of the plurality of first electrode films; a plurality of charge storage members provided between the plurality of first electrode films and the plurality of semiconductor members; a first conductive film having a first surface, and commonly connected to the plurality of semiconductor members on the first surface; a first insulating film provided on a second surface of the first conductive film on the side opposite to the first surface; a contact provided in the first insulating film and connected to the first conductive film; and a second conductive film provided on the first insulating film and connected to the contact.

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together. 1. A method comprising:depositing a first protection layer on a first bonding surface of a first semiconductor wafer;removing the first protection layer from the first bonding surface of the first semiconductor wafer to expose the first bonding surface of the first semiconductor wafer;applying a plasma process to the first bonding surface of the first semiconductor wafer;performing a cleaning process on the first bonding surface of the first semiconductor wafer;coupling the first semiconductor wafer to a second semiconductor wafer; andannealing the first semiconductor wafer and the second semiconductor wafer to bond the first bonding surface of the first semiconductor wafer to a second bonding surface of the second semiconductor wafer, wherein bonding the first bonding surface of the first semiconductor wafer to the second bonding surface of the second semiconductor wafer comprises:forming a first bond between a first insulating layer of the first bonding surface and a second insulating layer of the second bonding surface; andforming a second bond between a first conductive pad of the first bonding ...