Semiconductor device

Devices and methods related to packaging of radio-frequency devices on ceramic substrates

Devices and methods related to packaging of radio-frequency (RF) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit and mounted on a surface of the ceramic substrate. The packaged electronic device can further include a conformal conductive coating implemented over the die to provide shielding functionality. The packaged electronic device can further include an electrical connection between the conformal conductive coating and the conductive layer.

Millimeter wave wafer level chip scale packaging (WLCSP) device and related method

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

SEMICONDUCTOR PACKAGE, PRINTED CIRCUIT BOARD SUBSTRATE AND SEMICONDUCTOR DEVICE

A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer. 1. A semiconductor package comprising:a semiconductor integrated circuit;an interlayer film disposed on the semiconductor integrated circuit;a rewiring layer disposed on the interlayer film;post electrodes disposed on the rewiring layer;a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; anda plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer,wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.2. The semiconductor package of claim 1 , wherein the protective layer is interposed between the rewiring layer and the ball non-connected to the rewiring layer.3. A semiconductor package comprising:a semiconductor integrated circuit;an interlayer film disposed on the semiconductor integrated circuit;a rewiring layer disposed on the interlayer film;post electrodes disposed on the rewiring layer;a protective layer which is disposed on the interlayer film and covers the rewiring layer and the ...

Coreless package structure and method for manufacturing the same

The present invention relates to a coreless package structure comprising a package substrate, a package colloid formed on the package substrate, a chip and a plurality of electrical contact pads. The package substrate comprises a dielectric layer near the package colloid and a first inner layer conductive circuit pattern embedded in the dielectric layer. The package colloid encloses the chip which is electrically connected with the package substrate. A plurality of electrical contact pads are exposed from the side, far from the package substrate, of the package colloid and are disposed around the chip. Each electrical contact pad is connected with the first inner layer conductive circuit pattern by a first conductive rod passing through the package colloid. The end, near the first inner layer conductive circuit pattern, of each first conductive rod is received in the dielectric layer, and the section, parallel to the package substrate, of each first conductive rod gradually enlarges from ...

SEMICONDUCTOR DEVICE

A semiconductor device (10) is provided with: an expanding semiconductor chip (20), which includes a first semiconductor chip (11), and an expanding section (21) that is provided to expand outward from the side surfaces of the first semiconductor chip; and a second semiconductor chip (12), which is connected to the expanding semiconductor chip via a plurality of bumps (14), and is electrically connected to the first semiconductor chip (11). The first semiconductor chip (11) is smaller than the second semiconductor chip (12). The expanding section (21) is provided with at least one external terminal.

Solid-state imaging device

A solid-state imaging device encompasses a detector substrate having a first main-surface, on which a plurality of first lands are arranged in a matrix, and a signal-circuit substrate having a second main-surface, on which plurality of second lands are arranged so as to face the arrangement of the first lands. A plurality of tubular bumps, each of which having a flattened plane pattern, and is provided between each of the first lands and each of the second lands. The tubular bumps respectively have major-axis directions to define inclined angles, and are arranged in the matrix such that the inclined angles differ depending on locations of the plurality of tubular bumps.

MULTI-FACED MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS

Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin.

Semiconductor device sealed in a resin section and method for manufacturing the same

A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of the first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.

Chip package and packaging method

A chip package and a packaging method are provided, which relates to the field of communications technologies, and is invented to implement high-frequency electromagnetic interference shielding and effectively improve chip performance. The package includes a package substrate and a metal cap covering the package substrate, where a silicon chip placement area is arranged on an upper surface of the package substrate, multiple first conductive parts are arranged in a peripheral area of the silicon chip placement area, and an edge of the metal cap is in contact with the package substrate and electrically connected to the multiple first conductive parts, where at least a portion of first conductive parts in the multiple first conductive parts are electrically connected to a grounding part by using the metal cap, and the grounding part is arranged on the package substrate, and configured to ground the package substrate.

Double-sided flip chip package

Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. 5 Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module. 110a 22110b 200b 20a100 130 { 130 VVVV VVu .VVV VVVVVV VVVVVV VV VVVV VVV 200bor 3 100 110b 1)3 130 110a 210a 200a 210c 200c 130 110a 130 o 0 0 0 0 0 0 o 0 0 120a 120c o 0 0 0 0 0 0 0 0 0 0 0 io o o lo o o 0 o 0~l 0 o00 01 lo o o o10 o oi o l o0 0 lo o o ol lo o o ol 0 o 10 0 0 01 10 0 0 o o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE AND RELATED METHOD

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Method of yield prejudgment and bump re-assignment and computer readable storage medium

A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.

Chip-stacked semiconductor package and method of manufacturing the same

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A first semiconductor chip has a first electrode pad, and a second semiconductor chip has a first through via and a second electrode pad joined to the via and aligned with the first electrode pad. A third semiconductor chip has a second through via, a third electrode pad joined to the via, wiring joined to the via, and a fourth electrode pad joined to the wiring and aligned with the second and third electrode pads. The semiconductor chips are stacked and electrically connected by joining the first to third electrode pads to one another, and gaps of the stacked body are filled with resin. The stacked body is secured to an adhesive material formed on a substrate and a solder bump formed on the substrate is joined to the fourth electrode. A molding resin encapsulates the stacked body and an adjacent surface of the substrate. 1. A method for manufacturing a semiconductor device , the method comprising:mounting at least one second semiconductor chip having a first through via and a second electrode pad joined to the first through via onto a first semiconductor chip having a first electrode pad on a first surface thereof, the second electrode pad and the first electrode pad being brought into alignment with one another;mounting a third semiconductor chip on the second semiconductor chip, the third semiconductor chip having a second through via, and on one surface thereof, a third electrode pad joined to the second through via and, on another surface thereof, a fourth electrode pad and a protective film having wiring therein, the fourth electrode pad formed so as to be joined to the wiring, the second electrode pad of the second semiconductor chip and the third electrode pad of the third semiconductor chip positioned in alignment with one another;joining the first to third electrode pads to one another and thereby electrically connecting the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip to one another;filling gaps in a stacked ...

SYSTEM FOR PERFORMING A MACHINE LEARNING OPERATION USING MICROBUMPS

A system including a machine learning processing device and a memory device with microbumps is disclosed. A machine learning processing device is for performing a machine learning operation, where the machine learning processing device includes a first set of microbumps. A memory device is for storing data for the machine learning operation, where the memory device includes a second set of microbumps. The first set of microbumps of the memory device are coupled with the second set of microbumps of the machine learning processing device. The first set of microbumps of the memory device and the second set of microbumps of the machine learning processing device are to transmit the data for the machine learning operation.

Chip package and chip packaging method

Package-on-package assembly with wire bonds to encapsulation surface

Package-on-package assembly with wire bonds to encapsulation surface

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Semiconductor device

MECHANISMS FOR FORMING PACKAGE STRUCTURE

Structures and formation methods of a package structure are provided. The package structure includes a semiconductor die and a substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween. The first bonding structure and the second bonding structure are next to each other and the second bonding structure is wider than the first bonding structure. The first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump thereon, and the second bonding structure has a second UBM structure and a second solder bump thereon. The second UBM structure has a maximum width larger than that of the first UBM structure, and the second solder bump has a maximum width larger than that of the first solder bump. 1. A package structure , comprising:a semiconductor die; anda substrate bonded to the semiconductor die through a first bonding structure and a second bonding structure therebetween, wherein:the first bonding structure and the second bonding structure are next to each other,the second bonding structure is wider than the first bonding structure,the first bonding structure has a first under bump metallurgy (UBM) structure and a first solder bump thereon,the second bonding structure has a second UBM structure and a second solder bump thereon, andthe second UBM structure has a maximum width larger than that of the first UBM structure, and the second solder bump has a maximum width larger than that of the first solder bump.2. The package structure as claimed in claim 1 , wherein the second solder bump has a volume larger than that of the first solder bump.3. The package structure as claimed in claim 1 , wherein the second solder bump has a height substantially equal to that of the first solder bump.4. The package structure as claimed in claim 1 , wherein the second solder bump is formed over a high stress region of the semiconductor die.5. The package structure as claimed in claim 4 , wherein ...

Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages

An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.

Millimeter wave wafer level chip scale packaging (WLCSP) device and related method

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

Package-on-package assembly with wire bonds to encapsulation surface

A microelectronic assembly includes a substrate having a first surface and a second surface remote from the first surface. A microelectronic element overlies the first surface and first electrically conductive elements are exposed at one of the first surface and the second surface. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer extends from the first surface and fills spaces between the wire bonds such that the wire bonds are separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

Method for manufacturing semiconductor device and semiconductor device

A first semiconductor chip has a first electrode pad, and a second semiconductor chip has a first through via and a second electrode pad joined to the via and aligned with the first electrode pad. A third semiconductor chip has a second through via, a third electrode pad joined to the via, wiring joined to the via, and a fourth electrode pad joined to the wiring and aligned with the second and third electrode pads. The semiconductor chips are stacked and electrically connected by joining the first to third electrode pads to one another, and gaps of the stacked body are filled with resin. The stacked body is secured to an adhesive material formed on a substrate and a solder bump formed on the substrate is joined to the fourth electrode. A molding resin encapsulates the stacked body and an adjacent surface of the substrate.

Flip-chip package structure and method for an integrated switching power supply

Disclosed are flip-chip package structures and methods for an integrated switching power supply. In one embodiment, a flip-chip package structure can include: (i) a die with an integrated switching power supply, where a first surface of the die includes first bumps with different polarities; (ii) a redistribution layer including redistribution layer units, each having a first surface to connect bumps with a same polarity from the first bumps, the redistribution layer having a second surface including second bumps to redistribute polarities; (iii) a lead frame having pins, where a first surface of the lead frame can connect bumps with a same polarity from the second bumps; and (iv) a flip-chip package configured to package the die, the redistribution layer, the first and second bumps, and the lead frame, where a second surface of the lead frame provides electrical connectivity between the integrated switching power supply and a PCB.

Forming the encapsulated structure mechanism

Semiconductor device

A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.

Chip package structure

A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface, and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the first conductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die. 1. A semiconductor device package , comprising:a substrate comprising a circuit layer, the substrate including a first surface and a second surface opposite to the first surface, at least one recess recessed from the second surface and partially exposing the circuit layer, and a bottom surface of the circuit layer in the recess is recessed from the second surface of the substrate;a first electronic component disposed above the first surface;a second electronic component stacked adjacent to the first electronic component;an encapsulation layer at least encapsulating the second electronic component and partially covering the second surface of the substrate; andan electrical conductor extending from the second surface of the substrate into the recess of the substrate, and contacting the bottom surface of the circuit layer.2. The package of claim 1 , wherein a space is defined between the encapsulation layer and the electrical conductor.3. The package of claim 2 , wherein in a cross section claim 2 , a width of the space between the encapsulation layer and the electrical conductor reduces in a direction toward the substrate.4. The package of claim 2 , wherein in a cross section claim 2 , an interface between the space and a sidewall of the ...

ELECTRONIC COMPONENT

An electronic component includes: four device chips having rectangular planar shapes and arranged on a substrate so that a corner of four corners constituting a rectangle of one device chip is adjacent to the corners of remaining three device chips; first pads located on surfaces of the four device chips and closest to the corner; one or more first bumps bonding the first pads to the substrate in the four device chips; second pads located on surfaces of the four device chips, the second pad being one of pads other than the first pad; and one or more second bumps bonding the second pads to the substrate in the four device chips, a sum of bonded areas between the one or more second bumps and the second pad being less than a sum of bonded areas between the first pad and the one or more first bumps. 1. An electronic component comprising:a substrate;four device chips each having a rectangular planar shape, the four device chips being arranged on the substrate so that a corner, which is one corner of four corners constituting a rectangle of one device chip of the four device chips, is adjacent to the corner of each of remaining three device chips of the four device chips;a first pad located on a surface at the substrate side of each of the four device chips and closest to the corner;one or more first bumps bonding the first pad to the substrate in each of the four device chips;a second pad located on the surface at the substrate side of each of the four device chips, the second pad being one of pads other than the first pad; andone or more second bumps bonding the second pad to the substrate in each of the four device chips, a sum of bonded areas between the second pad and the one or more second bumps being less than a sum of bonded areas between the first pad and the one or more first bumps.2. The electronic component according to claim 1 , whereinin one of the four device chips, the sum of the bonded areas between the second pad and the one or more second bumps is equal ...

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer. 1. A microelectronic package , comprising:a substrate having first contacts on an upper surface thereof;a microelectronic die having a lower surface attached to face the upper surface of the substrate, the microelectronic die having second contacts on an upper surface of the microelectronic die;wire bonds bonded to the first contacts at bases of the wire bonds;edge surfaces of the wire bonds extending from the bases and located between the bases and corresponding end surfaces of the wire bonds;wherein first ones of the wire bonds are interconnected between a first portion of the first contacts and the second contacts;a dielectric structure formed above the upper surface of the substrate and the microelectronic die and between the bases of the wire bonds;wherein the end surfaces of second ones of the wire bonds are located above the upper surface of the microelectronic die separated therefrom by a portion of the dielectric structure located above the upper surface of the microelectronic die; anda stack of microelectronic elements interconnected to the substrate via the second ones of ...

IC package with metal interconnect structure implemented between metal layers of die and interposer

An integrated circuit package includes a die having a first substrate implementing an integrated circuit comprising circuit elements. The die includes a first plurality of metal layers implementing a first portion of a metal interconnect structure for the integrated circuit. The die also includes a first plurality of pads at or overlying a top metal layer of the first plurality of metal layers. The integrated circuit package includes an interposer having a second plurality of metal layers implementing a second portion of the metal interconnect structure. The interposer includes a second plurality of pads at or overlying a top metal layer of the second plurality of metal layers. A plurality of solder structures couple the first and second pluralities of pads. The first and second portions of the metal interconnect structure together complete a signal path between two or more circuit blocks of the integrated circuit.

Flip-chip package device for integrated switching power supply and flip-chip packaging method

Ball grid array rework

Embodiments of the invention relates to a method for rework of a BGA package. Memory shape material is placed adjacent to a plurality of solder joints of the package. Stimulation is applied to the material, with the stimulation causing the material to change from a non-stimulated shape to a stimulated shape. This stimulation causes an expansion of the material. As the material expands, it exerts a tensile force on the BGA package and an adjacently positioned carrier, causing a separation of the two components, while mitigating collateral heat of adjacently positioned components.

Semiconductor device sealed in a resin section and method for manufacturing the same

A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.

Packaged semiconductor device

A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

Electronic device and semiconductor device

Electronic device and semiconductor device

DEVICES AND METHODS RELATED TO PACKAGING OF RADIO-FREQUENCY DEVICES ON CERAMIC SUBSTRATES

Devices and methods related to packaging of radio-frequency (RF) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit and mounted on a surface of the ceramic substrate. The packaged electronic device can further include a conformal conductive coating implemented over the die to provide shielding functionality. The packaged electronic device can further include an electrical connection between the conformal conductive coating and the conductive layer.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate comprising a top surface and a back surface, a semiconductor chip having a plurality of functions and mounted on the top surface of the substrate, and a plurality of balls formed on the back surface of the substrate to connect the substrate to an external substrate of the semiconductor package. The substrate further comprises a plurality of electrodes that correspond to the plurality of functions and are formed on the back surface of the substrate, and a subset of the plurality of electrodes corresponds to a subset of the plurality of functions, and each of the plurality of balls is respectively disposed on each of the electrodes in the subset. 1. A semiconductor package , comprising:a substrate comprising a top surface and a back surface;a semiconductor chip having a plurality of functions and mounted on the top surface of the substrate; anda plurality of balls formed on the back surface of the substrate to connect the substrate to an external substrate of the semiconductor package, wherein,the substrate further comprises a plurality of electrodes that correspond to the plurality of functions and are formed on the back surface of the substrate, anda subset of the plurality of electrodes corresponds to a subset of the plurality of functions, and each of the plurality of balls is respectively disposed on each of the electrodes in the subset.2. The semiconductor package according to claim 1 , whereinthe back surface of the substrate comprises a plurality of regions corresponding to the plurality of functions, andeach of the plurality of electrodes is respectively formed in the corresponding regions of the plurality of regions.3. The semiconductor package according to claim 1 , whereinthe electrodes in the subset that correspond to the subset of functions are disposed in a zigzag pattern, andthe electrodes not in the subset correspond to functions other than the functions in the subset and are disposed adjacent to the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a semiconductor device (SP) according to an embodiment, a solder resist film (first insulating layer, SR) which is in contact with the base material layer, and a resin body (second insulating layer, ) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (CR) of a wiring substrate and a semiconductor chip (). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved. 1. A semiconductor device comprising:a wiring substrate including a base material layer, a plurality of first terminals formed on a first surface of the base material layer, and a first insulating layer covering the first surface of the base material layer;a semiconductor chip including a front surface, aback surface opposite to the front surface, and a plurality of bonding pads formed on the front surface, and mounted over the first insulating layer; anda second insulating layer arranged between the wiring substrate and the semiconductor chip, and being in contact with each of the first insulating layer and the semiconductor chip,wherein each of the plurality of first terminals is exposed from a first opening formed in the first insulating layer,wherein each of the base material layer and the first insulating layer of the wiring substrate is comprised of resin containing a plurality of filler particles and a glass fiber,wherein a linear expansion coefficient of the first insulating layer ...

EPOXY RESIN COMPOSITION AND SEMICONDUCTOR APPARATUS PREPARED USING THE SAME

An epoxy resin composition includes an inorganic filler, an epoxy resin, and a curing agent. The inorganic filler has an average particle diameter D50 from about 2 μm to about 10 μm, an average particle diameter D10 of about 3 μm or less, and an average particle diameter D90 from about 6 μm to about 15 μm. Inorganic filler particles having a particle diameter of about 25 μm or more constitute about 0.1 wt % or less of the inorganic filler. 1. An epoxy resin composition , comprising:an inorganic filler;an epoxy resin; anda curing agent,wherein:the inorganic filler has an average particle diameter D50 from about 2 μm to about 10 μm, an average particle diameter D10 of about 3 μm or less, and an average particle diameter D90 from about 6 μm to about 15 μm, andin the inorganic filler, inorganic filler particles having a particle diameter of about 25 μm or more constitute about 0.1 wt % or less of the inorganic filler.2. The epoxy resin composition as claimed in claim 1 , wherein the inorganic filler has a particle diameter no greater than about 30 μm.3. The epoxy resin composition as claimed in claim 1 , wherein a particle diameter ratio of the average particle diameter D90 to the average particle diameter D50 ranges from about 1.2 to about 5.0.4. The epoxy resin composition as claimed in claim 1 , wherein a particle diameter ratio of the average particle diameter D90 to the average particle diameter D10 ranges from about 1.1 to about 150.5. The epoxy resin composition as claimed in claim 1 , wherein a particle diameter ratio of the average particle diameter D50 to the average particle diameter D10 ranges from about 1.1 to about 30.6. The epoxy resin composition as claimed in claim 1 , wherein inorganic filler particles having a particle diameter of about 20 μm or more constitute about 0.1 wt % or less of the inorganic filler.7. The epoxy resin composition as claimed in claim 1 , wherein a ratio of pore volume to total volume including pores and the inorganic filler ...

Millimeter wave wafer level chip scale packaging (WLCSP) device

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Semiconductor package, printed circuit board substrate and semiconductor device

A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.

Semiconductor device and manufacturing method thereof

In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

Package-on-package assembly with wire bonds to encapsulation surface

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

CHIP-STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other. 1. A method of manufacturing a chip-stacked semiconductor package , the method comprising:preparing a base wafer, the base wafer including a plurality of first chips, each of the plurality of first chips having a first front surface, a first back surface that is opposite to the first front surface, and a first connection member on the first front surface;preparing a plurality of second chips, each of the plurality of second chips having a second front surface, a second back surface that is opposite to the second front surface, and a second connection member on the second front surface;stacking the plurality of second chips on the plurality of first chips such that the second connection member is electrically connected to the first connection member between the first front surface and the second front surface;sealing the plurality of second chips by using a first sealing member;forming a first through-silicon via (TSV) that is electrically connected to the second connection member in each of the plurality of second chips;separating the plurality of first chips and the plurality of second chips, ...

MULTI-LAYER SHEET FOR MOLD UNDERFILL ENCAPSULATION, METHOD FOR MOLD UNDERFILL ENCAPSULATION, ELECTRONIC COMPONENT MOUNTING SUBSTRATE, AND PRODUCTION METHOD FOR ELECTRONIC COMPONENT

[Problem] To provide a multi-layer sheet for mold underfill encapsulation, which exhibits good infiltrability between electrodes. [Solution] In order to solve the aforementioned problem, the present invention provides a multi-layer sheet for mold underfill encapsulation, which is characterized by having provided as an outermost layer thereof an (A) layer that comprises a resin composition having a local maximum loss tangent (tan δ) value of 3 or more at a measurement temperature of 125° C. for a measurement time of 0-100 seconds. 1. A multi-layer sheet for mold underfill encapsulation , the multi-layer sheet comprising the following (A)-layer as an outermost layer:(A)-layer: a layer formed from a resin composition having a local maximum value of tan δ (loss tangent) of 3 or more at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds.2. The multi-layer sheet according to claim 1 , wherein the (A)-layer contains a filler claim 1 , and the maximum particle size of the filler is 20 μm or less.3. The multi-layer sheet according to claim 1 , wherein the (A)-layer contains a curing accelerator whose median diameter (D50) at a cumulative volume of 50% in the volume particle size distribution is 10 μm or less.4. The multi-layer sheet according to claim 1 , wherein the thickness of the (A)-layer is 10 to 500 μm.5. The multi-layer sheet according to claim 1 , further comprising the following (B)-layer:(B)-layer: a layer formed from a resin composition satisfying the following Formula (1), {'br': None, 'i': 'E′≤', '40000≤α×250000 [Pa/K]\u2003\u2003(1)'}, 'in the following Formula (1), “α” represents the coefficient of thermal expansion α [ppm/K] at 80° C. or lower of a thermoset product obtained after subjecting the resin composition to a thermosetting treatment at 175° C. for one hour; and “E′” represents the storage modulus E′ [GPa] at 25° C. of the thermoset product.'}6. The multi-layer sheet according to claim 5 , wherein the ratio (B/A) of the ...

반도체 장치 및 그 제조 방법

... 일 실시 형태에 의한 반도체 장치(SP1)는 배선 기판(2)의 기재층(2CR)과 반도체 칩(3)의 사이에, 기재층과 밀착되는 솔더 레지스트막(SR1: 제1 절연층), 솔더 레지스트막 및 반도체 칩과 밀착되는 수지체(4: 제2 절연층)가 적층되어 있다. 또한, 솔더 레지스트막의 선팽창 계수는 기재층의 선팽창 계수 이상이며, 솔더 레지스트막의 선팽창 계수는 수지체의 선팽창 계수 이하이며, 또한 기재층의 선팽창 계수는 수지체의 선팽창 계수보다도 작은 것이다. 상기 구성에 의해, 온도 사이클 부하에 기인하는 반도체 장치의 손상을 억제하여, 신뢰성을 향상시킬 수 있다.

ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE

An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line. Also, the second power line intersects the first substrate side of the second wiring substrate and extends from a side of the first substrate side of the second wiring substrate toward the second semiconductor chip when seen in a plan view.

Electronic component and method of manufacturing the same

An electronic component has a circuit board with a main surface, a chip having a sensor facing the main surface, bump electrodes disposed between the main surface and the chip so as to be placed inside of the edges of the chip in a plan view of the main surface, a dam provided between the main surface and the chip so as to extend at least from the edges of the chip to outer positions of the bump electrodes in a plan view of the main surface, and an under-fill material provided at least in a clearance between the dam and the chip. Between the main surface and the sensor, a space is formed in a region enclosed by the bump electrodes in a plan view of the main surface. The under-fill material is disposed outside of the space in a plan view of the main surface.

Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages

An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.

DOUBLE-SIDED FLIP CHIP PACKAGE

Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module.

Fine Pitch stud POP Structure and Method

A fine pitch stud POP structure and method is disclosed. The studs are made in bonding pads on the top surface of a lower substrate, which greatly increase the height of the interconnection such as solder balls. In addition, the lower substrate and the upper substrate are connected by reflowing two solder balls on them separately. The two features make the diameter of the bonding balls greatly reduce and further make the pitch between two bonding balls on the lower substrate or the upper substrate greatly reduce, and then the fine pitch POP is achieved.

Electronic device, component mounting substrate, and electronic apparatus

To provide an electronic device wherein warping of a substrate is suppressed, a component mounting substrate, and an electronic apparatus. According to one embodiment of the present art, an electronic device is provided with a first circuit board and a second circuit board. The first circuit board has a first main surface, a second main surface, and a plurality of external terminals. The external terminals include a first terminal group positioned at the outermost periphery, and are disposed in matrix on the first main surface. The second circuit board has a terminal surface facing the second main surface, and a plurality of connecting terminals. The connecting terminals are disposed on the terminal surface, include a second terminal group facing at least a part of the first terminal group, and are electrically connected to the second main surface.

Chip-stacked semiconductor package and method of manufacturing the same

A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.

Epoxy resin composition and semiconductor apparatus prepared using the same

An epoxy resin composition includes an inorganic filler, an epoxy resin, and a curing agent. The inorganic filler has an average particle diameter D50 from about 2 m to about 10 m, an average particle diameter D10 of about 3 m or less, and an average particle diameter D90 from about 6 m to about 15 m. Inorganic filler particles having a particle diameter of about 25 m or more constitute about 0.1 wt % or less of the inorganic filler.

MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

DOUBLE-SIDED FLIP CHIP PACKAGE

Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module.

DEVICES AND METHODS RELATED TO PACKAGING OF RADIO-FREQUENCY DEVICES ON CERAMIC SUBSTRATES

Devices and methods related to packaging of radio-frequency (RF) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit and mounted on a surface of the ceramic substrate. The packaged electronic device can further include a conformal conductive coating implemented over the die to provide shielding functionality. The packaged electronic device can further include an electrical connection between the conformal conductive coating and the conductive layer. 1. A method for fabricating a packaged radio-frequency (RF) module , the method comprising:forming or providing a ceramic substrate configured to receive one or more components, the ceramic substrate including a conductive layer in electrical contact with a ground plane;mounting a die on a surface of the ceramic substrate, the die including an integrated circuit; andforming a conformal conductive coating over the die and in electrical contact with the conductive layer to thereby provide shielding functionality for the die.2. The method of wherein the ceramic substrate includes a plurality of ceramic layers arranged in a stack having an array of units defined by a grid of lines along which a singulation process results in separation of the units into a plurality of individual units.3. The method of further comprising singulating the array of units prior to the forming of the conformal conductive coating.4. The method of wherein the mounting of the die is performed on each of the units prior to the singulating step.5. The method of wherein the conductive layer includes a conductive strip implemented along a corresponding one of the grid of lines claim 3 , such that the singulating step along the line results in two neighboring units to be ...

Devices and methods related to packaging of radio-frequency devices on ceramic substrates

Devices and methods related to packaging of radio-frequency (RF) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit and mounted on a surface of the ceramic substrate. The packaged electronic device can further include a conformal conductive coating implemented over the die to provide shielding functionality. The packaged electronic device can further include an electrical connection between the conformal conductive coating and the conductive layer.

Apparatus And Methods For High-Density Chip Connectivity

Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a pitch of 0.6 microns, compared to a pitch of 100 microns available with today's Ball Grid Array (BGA) technology. As a result, circuits in the mated chips can communicate via the pads with the same speed or clock frequency as if in a single chip. For example, clock rates between interconnected chips can be increased from 100 MHz to 4 GHz due to low capacitance of the interconnected pads. Because high-density arrays of pads can interconnect chips, chips can be made smaller, thereby reducing cost of chips by order(s) of magnitude. 1. An electronic chip , comprising:a substrate;an electronic circuit formed on the substrate; and{'b': '100', 'a plurality of conductive pads formed on the substrate and connected to the electronic circuit, the conductive pads having a pitch less than approximately microns.'}2. The electronic chip of claim 1 , further comprising at least one alignment structure formed on the substrate.3. The electronic chip of claim 2 , wherein the at least one alignment structure includes an indentation.4. The electronic chip of claim 3 , wherein the indentation includes tapering surfaces into the substrate.5. The electronic chip of claim 2 , wherein the at least one alignment structure includes a semi-hemispherical shape.6. The electronic chip of claim 2 , wherein the at least one alignment structure includes a circular post.7. The electronic chip of claim 1 , wherein the conductive pads have a maximum surface area less than approximately 10 square microns.8. The electronic chip of claim 7 , wherein the conductive pads have a maximum surface area less than approximately 0.5 square microns.9. The electronic chip of claim 1 , wherein the ...

Ball grid array rework

Embodiments relate to an apparatus for rework of a BGA package. Memory shape material is placed adjacent to a plurality of solder joints of the package. Stimulation is applied to the material, with the stimulation causing the material to change from a non-stimulated shape to a stimulated shape. This stimulation causes an expansion of the material. As the material expands, it exerts a tensile force on the BGA package and an adjacently positioned carrier, causing a separation of the two components, while mitigating collateral heat of adjacently positioned components.

FLIP-CHIP PACKAGE STRUCTURE AND METHOD FOR AN INTEGRATED SWITCHING POWER SUPPLY

Disclosed are flip-chip package structures and methods for an integrated switching power supply. In one embodiment, a flip-chip package structure can include: (i) a die with an integrated switching power supply, where a first surface of the die includes first bumps with different polarities; (ii) a redistribution layer including redistribution layer units, each having a first surface to connect bumps with a same polarity from the first bumps, the redistribution layer having a second surface including second bumps to redistribute polarities; (iii) a lead frame having pins, where a first surface of the lead frame can connect bumps with a same polarity from the second bumps; and (iv) a flip-chip package configured to package the die, the redistribution layer, the first and second bumps, and the lead frame, where a second surface of the lead frame provides electrical connectivity between the integrated switching power supply and a PCB.

PACKAGED SEMICONDUCTOR DEVICE

A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

반도체 패키지

... 본 발명의 실시예에 따른 반도체 패키지는 제 1 영역을 포함하는 패키지 기판, 상기 패키지 기판의 상기 제 1 영역을 관통하며, 상기 패키지 기판의 상부면 및 하부면에 노출된 열 기둥, 상기 패키지 기판 상에 배치된 반도체 칩, 및 제 1 방향으로 배열되고 상기 제 1 방향에 수직인 제 2 방향으로 나열되어 상기 패키지 기판과 상기 반도체 칩 사이에 개재되고, 상기 열 기둥과 접촉하는 제 1 범프들을 포함하는 범프들, 및 상기 제 1 방향으로 배열되고 상기 제 2 방향으로 나열되어 상기 패키지 기판의 하부면에 배치되고, 상기 열 기둥과 접촉하는 제 1 단자들을 포함하는 단자들을 포함하되, 상기 열 기둥은 전원 통로 및 접지 통로 중 어느 하나일 수 있다.

Package-on-package assembly with wire bonds to encapsulation surface

Flip-chip package structure and method for an integrated switching power supply

Disclosed are flip-chip package structures and methods for an integrated switching power supply. In one embodiment, a flip-chip package structure can include: (i) a die with an integrated switching power supply, where a first surface of the die includes first bumps with different polarities; (ii) a redistribution layer including redistribution layer units, each having a first surface to connect bumps with a same polarity from the first bumps, the redistribution layer having a second surface including second bumps to redistribute polarities; (iii) a lead frame having pins, where a first surface of the lead frame can connect bumps with a same polarity from the second bumps; and (iv) a flip-chip package configured to package the die, the redistribution layer, the first and second bumps, and the lead frame, where a second surface of the lead frame provides electrical connectivity between the integrated switching power supply and a PCB.

PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

There is provided a printed circuit board includes a substrate having product areas for mounting elements and dummy areas disposed between two neighboring product areas, external connection terminals disposed on the product areas, and a plurality of dummy bumps disposed on the dummy areas.

Semiconductor packages including thermal blocks

A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

Imaging device, endoscope system, and method for manufacturing imaging device

DOUBLE-SIDED FLIP CHIP PACKAGE CAPABLE OF IMPROVING THE DENSITY OF A CONNECTOR

PURPOSE: A double-sided flip chip package is provided to mount the same integrated circuit dies on a module PCB and to improve the degree of integration. CONSTITUTION: A module PCB(100) includes a first surface, a second surface and a first set of electrical conductors(130). The electrical conductors are electrically connected to an electronic device module. A first die is electrically connected to the module PCB through the flip chip interconnection of the first surface of the module PCB. A second die is electrically connected to the module PCB through a flip chip interconnection of the second surface of the module PCB. The first set of the electrical conductors electrically connects the electronic device module to a module including a SOC(system on a chip). COPYRIGHT KIPO 2013 ...

PACOTE FLIP CHIP DE DUPLA FACE

Semiconductor device having an inductor

A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

Semiconductor device and corresponding method

A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.

Semiconductor device and method of forming inverted pyramid cavity semiconductor package

SEMICONDUCTOR DEVICE HAVING AN INDUCTOR

A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor. 1. A semiconductor device , comprising a semiconductor chip having:a semiconductor substrate;a multilayered interconnect having a bottom surface contacting said semiconductor substrate and an uppermost surface opposite to the bottom surface, and including an inductor;a plurality of first pads respectively physically contacting external electrode terminals on said uppermost surface of said multilayered interconnect in a region around the inductor on at least three sides thereof in a plan view, the first pads being in direct physical contact with the respective external electrode terminals; anda circuit forming region provided right under said first pads,wherein an area of said uppermost surface of said multilayered interconnect overlapping said inductor does not include any pads for physically contacting external electrode terminals, andwherein an area of an upper side of said semiconductor substrate overlapping said inductor does not include any circuit elements.2. The semiconductor device according to claim 1 , wherein said first pads are provided in a plurality of regions closer than said inductor to side surfaces of said semiconductor chip in a plan view.3. The semiconductor device according to claim 1 , wherein said first pads are regularly arranged in a plan view claim 1 , except the area that overlaps said inductor.4. The semiconductor device according to claim 3 , wherein said first pads are arranged in a square pattern in a plan view claim 3 , in a region other than the area that overlaps ...

Semiconductor device sealed in a resin section and method for manufacturing the same

A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of the first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.

Chip-stacked semiconductor package and method of manufacturing the same

A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.

Method of yield prejudgment and bump re-assignment and computer readable storage medium

Method of yield prejudgment and bump re-assignment for a chip is provided. The chip includes a plurality of areas. Each area is electrically connected to a substrate via a corresponding bump. The successful connection probability of each area is prejudged. The chip is divided into a signal region and a short region according to the successful connection probabilities. The positions of the bumps are arranged such that signal bumps are disposed in the signal region and power bumps are disposed in the short region.

ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

An electronic component has a circuit board with a main surface, a chip having a sensor facing the main surface, bump electrodes disposed between the main surface and the chip so as to be placed inside of the edges of the chip in a plan view of the main surface, a dam provided between the main surface and the chip so as to extend at least from the edges of the chip to outer positions of the bump electrodes in a plan view of the main surface, and an under-fill material provided at least in a clearance between the dam and the chip. Between the main surface and the sensor, a space is formed in a region enclosed by the bump electrodes in a plan view of the main surface. The under-fill material is disposed outside of the space in a plan view of the main surface.

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer. 1. A method for forming a microelectronic package , comprising:obtaining a substrate having first contacts on an upper surface thereof;attaching a microelectronic die having a lower surface to face the upper surface of the substrate, the microelectronic die having second contacts on an upper surface of the microelectronic die;bonding wire bonds to the first contacts including forming bases of the wire bonds during the bonding, the wire bonds having edge surfaces between the bases and corresponding end surfaces;wherein a first portion of the wire bonds is interconnected between a first portion of the first contacts and the second contacts;wherein the end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die;forming a dielectric layer above the upper surface of the substrate and between the wire bonds; andbending uppermost portions of the second portion of the wire bonds over to be parallel with an upper surface of the dielectric layer.2. The method according to claim 1 , wherein the uppermost portions have corresponding sections of the ...

METHOD OF YIELD PREJUDGMENT AND BUMP RE-ASSIGNMENT AND COMPUTER READABLE STORAGE MEDIUM

A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.

SEMICONDUCTOR PACKAGE

According to an embodiment of the present invention, a semiconductor package comprises: a package substrate including a first region; a thermal pillar penetrating the first region of the package substrate and exposed to upper and lower surfaces of the package substrate; a semiconductor chip arranged on the package substrate; bumps arranged in a first direction and a second direction vertical to the first direction, and interposed between the package substrate and the semiconductor chip, and including first bumps contacting the thermal pillar; and terminals arranged in the first direction and the second direction to be arranged on a lower surface of the package substrate, and including first terminals contacting the thermal pillar. The thermal pillar can be one of a power route or a ground route. Therefore, the semiconductor package can improve a power feature. COPYRIGHT KIPO 2016 ...

DOUBLE-SIDED FLIP CHIP PACKAGE

Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module.

Semiconductor device having an inductor

A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

Chip stacked semiconductor package and manufacturing method thereof

MICROELECTRONIC PACKAGE WITH SOLDER ARRAY THERMAL INTERFACE MATERIAL (SA-TIM)

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.

CHIP-TO-CHIP INTERFACE OF A MULTI-CHIP MODULE (MCM)

Electronic component

An electronic component includes: four device chips having rectangular planar shapes and arranged on a substrate so that a corner of four corners constituting a rectangle of one device chip is adjacent to the corners of remaining three device chips; first pads located on surfaces of the four device chips and closest to the corner; one or more first bumps bonding the first pads to the substrate in the four device chips; second pads located on surfaces of the four device chips, the second pad being one of pads other than the first pad; and one or more second bumps bonding the second pads to the substrate in the four device chips, a sum of bonded areas between the one or more second bumps and the second pad being less than a sum of bonded areas between the first pad and the one or more first bumps.

SEMICONDUCTOR DEVICE SEALED IN A RESIN SECTION AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.

Mechanisms for forming package structure

Embodiments of mechanisms for forming a package structure are provided. A method for forming a package structure includes providing a semiconductor die and forming a first bump structure and a second bump structure over the semiconductor die. The second bump structure is thinner and wider than the first bump structure. The method also includes providing a substrate having a first contact pad and a second contact pad formed on the substrate. The method further includes forming a first solder paste structure and a second solder paste structure over the first contact pad and the second contact pad, respectively. The second solder paste structure is thicker than the first solder paste structure. In addition, the method includes reflowing the first bump structure and the second bump structure with the first solder paste structure and the second solder paste structure, respectively, to bond the semiconductor die to the substrate.

Double-sided flip chip package

Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

FILM TYPE SEMICONDUCTOR PACKAGE

A film type semiconductor package includes a film substrate; a metal pattern extending a first length in a first direction on the film substrate, having a first width in a second direction perpendicular to the first direction the first length being larger than the first width, and includes a plurality of through holes spaced apart from each other in the first direction; a semiconductor chip including a plurality of pads; and a plurality of bumps spaced apart from each other in the first direction, bonded with the metal pattern, and overlapping the plurality of through holes and connected to the pads of the semiconductor chip. 1. A film type semiconductor package comprising:a film substrate;a metal pattern extending a first length in a first direction on the film substrate, having a first width in a second direction perpendicular to the first direction, wherein the first length in the first direction is larger than the first width in the second direction, and comprising a plurality of through holes spaced apart from each other in the first direction;a semiconductor chip comprising a plurality of pads; anda plurality of bumps spaced apart from each other in the first direction, bonded with the metal pattern, and overlapping the plurality of through holes and connected to the pads of the semiconductor chip.2. The film type semiconductor package of claim 1 , wherein the plurality of bumps partially overlap the plurality of through holes.3. The film type semiconductor package of claim 1 , wherein the plurality of bumps completely overlap the plurality of through holes.4. The film type semiconductor package of claim 1 , wherein each through hole of the plurality of through holes comprises a first through hole and a second through hole spaced apart from each other in the second direction.5. The film type semiconductor package of claim 4 , wherein each bump of the plurality of bumps are bonded with the metal pattern through the first through hole and the second through hole ...

Bumped land grid array

A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of solderable surfaces formed on the first face of the substrate, a first solderable surface in the plurality of solderable surfaces having a pattern plating structure on an outward facing surface of the first solderable surface. There may also be an amount of solder bonded to the outward facing surface of the first solderable surface, where the pattern plating structure on the outward facing surface of the first solderable surface causes the amount of solder to have a first thickness at its ends, a second thickness at its center, and a discrete transition between the first thickness and the second thickness.

POWER MODULE

A power module includes a base plate, first, second, and third semiconductor chips. At least one of a third edge or fourth edge of the first semiconductor chip is disposed adjacent to a side end of the base plate. Among a half of a distance from a first edge of the first semiconductor chip to one edge of the second semiconductor chip, a half of a distance from a second edge of the first semiconductor chip to one edge of the third semiconductor chip, and a distance from the third edge or fourth edge of the first semiconductor chip disposed adjacent to the side end of the base plate to the side end of the base plate, a length of a solder fillet formed on the edge of the first semiconductor chip at the shortest distance is formed in the shortest length. 1. A power module comprising:a base plate;a first semiconductor chip having four edges;a second semiconductor chip having four edges, one of the four edges disposed adjacent to a first edge of the first semiconductor chip, the second semiconductor chip soldered to the base plate; anda third semiconductor chip having four edges, one of the four edges disposed adjacent to a second edge of the first semiconductor chip, the third semiconductor chip soldered to the base plate,wherein at least one of a third edge or a fourth edge of the first semiconductor chip is disposed adjacent to a side end of the base plate, andamong a half of a distance from the first edge of the first semiconductor chip to the one edge of the second semiconductor chip, a half of a distance from the second edge of the first semiconductor chip to the one edge of the third semiconductor chip, and a distance from the third edge or the fourth edge of the first semiconductor chip disposed adjacent to the side end of the base plate to the side end of the base plate, a length of a solder fillet formed on the edge of the first semiconductor chip at the shortest distance is formed in the shortest length.2. The power module according to claim 1 ,wherein a half ...

Chip package and manufacturing method thereof

A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

CORELESS PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME

A coreless package structure and a method for manufacturing same includes the steps of providing a supporting substrate comprising an etching resist layer and a copper foil. A groove is defined in the copper foil and a plurality of contact pads are formed on the surface of the copper foil. A chip including a plurality of electrode pads is received in the groove and a packaging layer is formed on a side of the copper foil. An insulating layer and a conductive pattern layer are formed on the packaging layer in that order, the conductive pattern layer being electrically connected to the contact pads and the electrode pads by a plurality of conductive bumps. Finally, the etching resist layer and the copper foil are removed to obtain a coreless package structure. 1. A method for manufacturing a coreless package structure comprising:providing a supporting substrate comprising a etching resist layer and a first copper foil;defining a groove in the first copper foil;forming a plurality of contact pads on the surface of the first copper foil;receiving a chip in the groove, the chip comprising a plurality of electrode pads1 on a side away from the etching resist layer;forming a packaging layer on a side of the copper foil, the packaging layer covering the chip, the contact pads, and the first copper foil exposed from the contact pads;forming an insulating layer, a plurality of first conductive bumps, and a conductive pattern layer, on the insulating layer adhered between the packaging layer and the conductive pattern layer, the conductive pattern layer electrically connected to the contact pads by the first conductive bumps, the conductive pattern layer electrically connected to the electrode pads by a plurality of second conductive bumps or wires; andremoving the etching resist layer and the first copper foil, thereby, obtaining a coreless package structure.2. The method of claim 1 , wherein the etching resist layer is made of nickel claim 1 , and the etching resist layer ...

Semiconductor device

A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.

SEMICONDUCTOR DEVICES INCLUDING POWER CONNECTION LINES

A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region. 1. A semiconductor chip , comprising:a first core region including a first core and a first power line configured to provide a first voltage to the first core;a second core region including a second core and a second power line configured to provide the first voltage to the second core;a cache region between the first core region and the second core region, the cache region including a cache and a third power line configured to provide a second voltage to the cache; anda first power connection line in the cache region, the first power connection line connecting the first power line to the second power line.2. The semiconductor chip of claim 1 , whereinthe cache region includes a plurality of line layers that are stacked, andthe first power connection line is on a first line layer that is different from a separate line layer on which the third power line is located.3. The semiconductor chip of claim 1 , whereinthe first core region, the second core region, and the cache region include a plurality of line layers that are stacked, andthe first power connection line is on a same line layer as a line layer on which the first power line and the second power line are located.4. The semiconductor chip of claim 1 , whereinthe first core region, the cache region, and the second core region are aligned in a first direction,the ...

MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad. 1. A wafer level chip scale package (WLCSP) structure comprising:a printed circuit board (PCB) trace connection including at least one ground connection connected with a PCB ground plane;a set of ground pillars each contacting the printed circuit board trace connection;a set of chip pads contacting each of the ground pillars in the set of ground pillars;a chip ground plane connecting the set of chip pads; and a signal trace connection electrically isolated from the PCB ground plane;', 'a signal pillar contacting the signal trace connection;', 'a chip pad contacting the signal pillar; and', 'a signal trace connection on a chip contacting the chip pad., 'a signal interconnect interposed between two of the set of ground pillars, the signal interconnect including2. The WLCSP structure of claim 1 , wherein each of the ground pillars includes:a pillar section contacting a corresponding chip pad in the set of chip pads; anda solder joint contacting the pillar section and the printed circuit board trace connection.3. The WLCSP structure of claim 1 , wherein the signal trace connection electrically ...

Fine Pitch stud POP Structure and Method

A fine pitch stud POP structure and method is disclosed. The studs are made in bonding pads on the top surface of a lower substrate, which greatly increase the height of the interconnection such as solder balls. In addition, the lower substrate and the upper substrate are connected by reflowing two solder balls on them separately. The two features make the diameter of the bonding balls greatly reduce and further make the pitch between two bonding balls on the lower substrate or the upper substrate greatly reduce, and then the fine pitch POP is achieved. 1. A fine pitch stud POP structure comprising a lower package body and an upper package body , wherein ,the lower package body comprises a lower substrate, at least one chip attached on a die pad of the top surface of the lower substrate and electrically connected with the lower substrate, studs made in bonding pads on the top surface of the lower substrate, solder balls mounted on the studs separately; wherein, the solder balls and the top surface of the lower substrate are pre-molded, and the top of the solder balls is exposed outside of the pre-molded material on the top surface of the lower substrate and is used to connected with the upper package body; wherein,the upper package body comprises an upper substrate, and solder balls mounted on bonding pads on the bottom surface of the upper substrate; wherein,the position and pitch of the solder balls on the bottom surface of the upper substrate match those of the solder balls on the top surface of the lower substrate, and the upper substrate is connected with the lower substrate by reflowing the solder balls on the bottom surface of the upper substrate and the solder balls on the top surface of the lower substrate separately.2. The structure of claim 1 , wherein claim 1 , the at least one chip is flip chip.3. The structure of claim 1 , wherein claim 1 , the lower package body further comprises: solder balls mounted on bonding pads of the bottom surface of the lower ...

SEMICONDUCTOR DEVICE SEALED IN A RESIN SECTION AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same. 19-. (canceled)10. A method for manufacturing a semiconductor device comprising:forming a groove on a semiconductor wafer having a pad electrode formed on an upper surface thereof;connecting the pad electrode and a lower surface of the groove by a bonding wire;forming on the semiconductor wafer a columnar electrode with a part of the bonding wire being embedded therein, and a resin section sealing a first semiconductor chip, the columnar electrode and the remaining part of the bonding wire, embedding the groove therein, and exposing the upper surface of the columnar electrode;forming the first semiconductor chip from the semiconductor wafer by grinding or polishing a lower surface of the semiconductor wafer so as to expose a lower surface of the columnar electrode; andseparating the first semiconductor chip by cutting the resin section along the groove.11. The method according to claim 10 , wherein a side surface of the columnar electrode is surrounded by the resin section.12. The method according to claim ...

Double-sided substrate with cavities for direct die-to-die interconnect

Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

SEMICONDUCTOR PACKAGES INCLUDING GAP IN INTERCONNECTION TERMINALS AND METHODS OF MANUFACTURING THE SAME

A semiconductor package includes a lower package comprising a lower semiconductor chip mounted on a lower package substrate, an upper package comprising an upper package substrate stacked on the lower package and an upper semiconductor chip mounted on the upper package substrate, interconnection terminals electrically connecting the lower package substrate with the upper package substrate, and a lower molding film molding the lower semiconductor chip between the lower package substrate and the upper package substrate. The lower package substrate comprises a chip region on which the lower semiconductor chip is mounted, an interconnection region enclosing a portion of the chip region, and a mold injection region defined by the chip region and the interconnection region. The interconnection terminals are disposed on the lower package substrate of the interconnection region but not disposed on the lower package substrate of the mold injection region. 1. A semiconductor package comprising:a lower package comprising a lower semiconductor chip on a lower package substrate;an upper package comprising an upper package substrate on the lower package and on the lower semiconductor chip opposite the lower package substrate, and an upper semiconductor chip on the upper package substrate opposite the lower semiconductor chip;interconnection terminals electrically connecting the lower package substrate with the upper package substrate; anda lower molding film molding the lower semiconductor chip between the lower package substrate and the upper package substrate,wherein the lower package substrate comprises a chip region between the lower semiconductor chip and the lower package substrate, an interconnection region outside of and enclosing a portion of the chip region, and a mold injection region defined by the chip region and the interconnection region, andthe interconnection terminals are on the lower package substrate of the interconnection region but not on the lower package ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate including a lower plate and an upper plate, a semiconductor chip mounted on a top surface of the substrate, and a mold layer surrounding a sidewall and a bottom surface of the semiconductor chip. The substrate has a mold path including an inner path extending between the lower and upper plates and a mold hole penetrating the upper plate. The mold hole is connected to the inner path. The mold layer extends into the mold path. 1. A semiconductor package comprising:a substrate comprising a lower plate and an upper plate, the substrate having a mold path, the mold path including an inner path extending between the lower and upper plates and a mold hole penetrating the upper plate, and the mold hole connected to the inner path;a semiconductor chip mounted on a top surface of the substrate; anda mold layer encapsulating the semiconductor chip, the mold layer further arranged in the mold path.2. The semiconductor package of claim 1 , wherein the mold layer extends into the inner path through the mold hole.3. The semiconductor package of claim 1 , wherein the inner path includes a first groove formed at a bottom surface of the upper plate.4. The semiconductor package of claim 3 , wherein the inner path further includes a second groove formed at a top surface of the lower plate claim 3 , andwherein the second groove is in communication with the first groove.5. The semiconductor package of claim 4 , wherein the first groove extends in one direction claim 4 , andwherein the second groove extends in another direction to cross the first groove.6. The semiconductor package of claim 4 , wherein the second groove includes a plurality of second grooves.7. The semiconductor package of claim 3 , wherein the mold hole is connected to the first groove.8. The semiconductor package of claim 1 , wherein the inner path includes a groove formed at a top surface of the lower plate.9. The semiconductor package of claim 1 , further comprising:bumps ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a semiconductor device (SP) according to an embodiment, a solder resist film (first insulating layer, SR) which is in contact with the base material layer, and a resin body (second insulating layer, ) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (CR) of a wiring substrate and a semiconductor chip (). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved. 1. A semiconductor device comprising:a wiring substrate including a base material layer, a terminal formed on a first surface of the base material layer, and an insulating layer formed on the first surface such that the insulating film covers a first portion of the terminal, and such that the insulating film exposes a second portion of the terminal;a semiconductor chip including a front surface, a bonding pad formed on the front surface, and a projecting electrode formed on the bonding pad, and mounted over the wiring substrate such that the front surface faces the first surface of the wiring substrate via the projecting electrode;a solder material located between the second portion of the terminal and the projecting electrode; anda resin body located between the wiring substrate and the semiconductor chip, and sealing a connection part between the projecting electrode and the terminal,wherein the insulating film has an opening in which the second portion of the terminal is exposed,wherein, ...

Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die

A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;providing a substrate;forming a plurality of conductive traces including a plurality of interconnect sites over the substrate arranged in a layout comprising signal sites located primarily in a perimeter region of the substrate; anddisposing an interconnect structure between the semiconductor die and substrate.2. The method of claim 1 , wherein the substrate is a four-metal layer substrate.3. The method of claim 1 , wherein the interconnect structure includes a fusible portion and non-fusible portion.4. The method of claim 1 , further including arranging the signal sites in a peripheral array generally parallel to an edge of the substrate.5. The method of claim 1 , further including arranging the signal sites in adjacent rows in a staggered arrangement or orthogonal arrangement.6. The method of claim 1 , further including depositing an encapsulant over the semiconductor die and substrate.7. A method of making a semiconductor device claim 1 , comprising:providing a substrate;forming a plurality of conductive traces including interconnect sites ...

SUBSTRATE COMPRISING INTERCONNECTS EMBEDDED IN A SOLDER RESIST LAYER

A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.

Structure and method for cooling three-dimensional integrated circuits

A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

CHIP PACKAGE STRUCTURE

A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface, and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the first conductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge. 1. A chip package structure , comprising:a chip package layer, comprising at least one chip and an encapsulant, wherein the at least one chip has an upper surface, and the encapsulant encapsulates the at least one chip and exposes the upper surface; andat least one conductive structure layer, comprising a plurality of first conductive pillars and a plurality of second conductive pillars, wherein the first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface, the second conductive pillars are located between an edge of the upper surface and the first conductive pillars, and a density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.2. The chip package structure as claimed in claim 1 , wherein the first conductive pillars constitute a first conductive pillar array claim 1 , the second conductive pillars are arranged along a column direction of the first conductive pillar array claim 1 , a first column of the first conductive pillar array is ...

REDUCTION OF SOLDER INTERCONNECT STRESS

A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto. 1. An interposer comprising:a matrix of contacts arranged in rows and columns, wherein the matrix of contacts comprise:a plurality of first contacts each comprising a major axis and a minor axis; anda plurality of second contacts each comprising diameter axes,wherein the major axis of the plurality of first contacts are aligned with a direction of expansion of the interposer.2. The interposer of claim 1 , wherein the plurality of first contacts are located within a power/ground region of the interposer and the plurality of second contacts are located within an input output region of the interposer.3. The interposer of claim 1 , wherein the plurality of first contacts are located within a quintain of the interposer and the plurality of second contacts are located within an perimeter region of the interposer that complexly surrounds the quintain.4. The interposer of claim 1 , wherein the plurality of first contacts comprise a diagonal contact nearest the interposer center.5. The interposer ...

REDUCTION OF SOLDER INTERCONNECT STRESS

An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto. 1. A method comprising:patterning a first contact trench and a second contact trench within a mask formed upon an electronic package structure, wherein the first contact trench and the second contact trench are patterned such that respective centers of the first contact trench and second contact trench are horizontally aligned, and wherein the first contact trench and the second contact trench are patterned such that the first contact trench is rotated relative to the second contact trench; andpatterning a third contact trench and a fourth contact trench within the mask, wherein the third contact trench and the fourth contact trench are patterned such that the third contact trench and the fourth contact trench are diagonally aligned.2. The method of claim 1 , further comprising:patterning a fifth contact trench and a sixth contact trench within the mask, wherein the fifth contact trench and the sixth contact trench are patterned such that respective centers of the fifth contact trench and sixth contact trench are vertically aligned, and wherein the fifth contact trench and the sixth contact trench are ...

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package. 1. An electronic package , comprising:a first substrate;a first electronic component disposed on the first substrate;a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer, wherein the first conductive elements are different in structure from the second conductive elements; anda first encapsulant formed between the first substrate and the second substrate and encapsulating the first electronic component, the first conductive elements and the second conductive elements.2. The electronic package of claim 1 , wherein a ratio of a number of the first conductive elements to a number of the second conductive elements is 1:0.5 to 1:1.5.3. The electronic package of claim 1 , wherein the first conductive elements are metal bumps.4. The electronic package of claim 1 , wherein the first conductive elements are metal bumps encapsulated by a conductive material.5. The electronic package of claim 1 , wherein the second conductive elements are solder bumps.6. The electronic package of claim 1 , wherein the bonding layer is made of a thin film or a heat ...

SEMICONDUCTOR PACKAGES

A semiconductor package is disclosed. The semiconductor package comprises a lower package including a first substrate and a semiconductor chip on the first substrate, a second substrate on the lower package, interconnect terminals between the first substrate and the second substrate, and an adhesive pattern between a top surface of the semiconductor chip and a bottom surface of the second substrate. The adhesive pattern extends along an edge of the semiconductor chip. The adhesive pattern exposes a top surface of a central zone of the semiconductor chip. 1. A semiconductor package , comprising:a lower package including a first substrate and a semiconductor chip on the first substrate;a second substrate on the lower package;interconnect terminals between the first substrate and the second substrate; and the adhesive pattern extending along an edge of the semiconductor chip, and', 'the adhesive pattern exposing a top surface of a central zone of the semiconductor chip., 'an adhesive pattern between a top surface of the semiconductor chip and a bottom surface of the second substrate,'}2. The semiconductor package of claim 1 , wherein the adhesive pattern has a closed-loop shape or a ring shape.3. The semiconductor package of claim 1 , whereinthe lower package further includes a molding layer contacting sidewalls of the semiconductor chip, andthe adhesive pattern contacts a top surface of the molding layer.4. The semiconductor package of claim 1 , further comprising:a heat dissipation structure on the top surface of the central zone of the semiconductor chip.5. The semiconductor package of claim 1 , further comprising:a second semiconductor chip on the second substrate.6. The semiconductor package of claim 5 , wherein the semiconductor chip is a semiconductor logic chip and the second semiconductor chip is a semiconductor memory chip.7. The semiconductor package of claim 1 , further comprising:an upper package on the second substrate, whereinthe upper package includes, ...

FLEXIBLE DISPLAY PANEL AND PREPARATION METHOD THEREOF, FLEXIBLE DISPLAY DEVICE

A flexible display panel, a preparation method thereof and a flexible display device are provided. The flexible display panel includes a flexible substrate; a back protective film arranged on a back surface of the flexible substrate; an adhesive layer arranged between the flexible substrate and the back protective film; and a support structure arranged in the adhesive layer between the flexible substrate and the back protective film and in a position corresponding to each of integrated circuit bumps, the support structure being configured to support the integrated circuit bumps in the adhesive layer. 1. A flexible display panel , comprising a flexible substrate;a back protective film arranged on a back surface of the flexible substrate;an adhesive layer between the flexible substrate and the back protective film;a support structure arranged in the adhesive layer between the flexible substrate and the back protective film and in a position corresponding to each of integrated circuit bumps, the support structure being configured to support the integrated circuit bump in the adhesive layer.2. The flexible display panel according to claim 1 , wherein the support structure is a supporting bar.3. The flexible display panel according to claim 2 , wherein a plurality of the supporting bars are arranged corresponding to each of the integrated circuit bumps claim 2 , the plurality of the supporting bars being arranged in parallel substantially.4. The flexible display panel according to claim 2 , wherein a plurality of the supporting bars are arranged corresponding to each of the integrated circuit bumps claim 2 , the plurality of the supporting bars being intersected with each other to form a grid structure.5. The flexible display panel according to claim 2 , wherein a plurality of the integrated circuit bumps are arranged along a pattern separately claim 2 , and the supporting bars are arranged along the pattern.6. The flexible display panel according to claim 5 , wherein ...

IMAGING DEVICE, ENDOSCOPE SYSTEM, AND METHOD OF MANUFACTURING IMAGING DEVICE

An imaging device includes: an image sensor including a light receiving unit, and sensor electrodes; a relay board including at least one rectangular substrate, one or more electronic components, a body part, substrate electrodes, cable electrodes, and pins standing on the substrate and configured to electrically connect the substrate electrodes and the cable electrodes, wherein the substrate electrodes are electrically and mechanically connected with the sensor electrodes; and a cable assembly including cables, and a cable fixing member, wherein cores of the cables exposed on an connection face of the cable fixing member are electrically and mechanically connected with the cable electrodes. A coefficient of thermal expansion of the image sensor, a coefficient of thermal expansion of the relay board, and a coefficient of thermal expansion of the cable assembly vary gradually in descending order or ascending order. 1. An imaging device comprising: a light receiving unit configured to perform photoelectric conversion on incident light to generate in electrical signal, and', 'a plurality of sensor electrodes formed on a rear face opposite to a face on which the light receiving unit is formed;, 'an image sensor including'} at least one rectangular substrate,', 'one or more electronic components mounted on the substrate,', 'a body part formed of encapsulating resin encapsulating the electronic components and formed in a quadrangular prism having a cross-section of a same shape as a projection area of the substrate,', 'substrate electrodes formed on a front face of the relay board,', 'cable electrodes formed on a rear face of the relay board, and', 'a plurality of pins standing on the substrate and configured to electrically connect the substrate electrodes and the cable electrodes,', 'wherein the substrate electrodes are electrically and mechanically connected with the sensor electrodes of the image sensor; and, 'a relay board including'} a plurality of cables, and', 'a ...

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby. 1. (canceled)2. A microelectronic package comprising:a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;at least one microelectronic element overlying the first surface within the first region;first electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the first conductive elements being electrically connected to the at least one microelectronic element;wire bonds having bases joined to respective ones of the first conductive elements, and end surfaces remote from the substrate and remote from the bases, each wire bond defining an edge surface extending between the base and the end surface thereof;a dielectric encapsulation layer extending from at least one of the first or second surfaces and filling spaces between the wire bonds such that the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions ...

SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME, METHODS OF MANUFACTURING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME

A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes penetrating the substrate and extending from the first surface to the second surface, front-side bumps disposed on the first surface and connected to odd-numbered through electrodes among the plurality of through electrodes, and backside bumps disposed on the second surface and connected to even-numbered through electrodes among the plurality of through electrodes. Related semiconductor packages, fabrication methods, electronic systems and memory cards are also provided. 1. A semiconductor package comprising:a first semiconductor chip including:a first substrate having a first surface and a second surface that are opposite to each other;a plurality of first through electrodes penetrating the first substrate and being spaced apart from each other;a plurality of first front-side bumps disposed on the first surface of the first substrate and connected to first odd-numbered through electrodes among the first through electrodes;a plurality of first backside bumps disposed on the second surface of the first substrate and connected to first even-numbered through electrodes among the first through electrodes; anda second semiconductor chip including:a second substrate having a first surface and a second surface that are opposite to each other;a plurality of second through electrodes penetrating the second substrate and being spaced apart from each other;a plurality of second front-side bumps disposed on the first surface of the second substrate and connected to second odd-numbered through electrodes among the second through electrodes; anda plurality of second backside bumps disposed on the second surface of the second substrate and connected to second even-numbered through electrodes among the second through electrodes,wherein the first and second semiconductor chips are combined with each other so that the first surface ...

Pad Structure Design in Fan-Out Package

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated. 1. A package comprising:a plurality of dielectric layers;a plurality of redistribution lines in the plurality of dielectric layers;a first device die over and electrically coupling to the plurality of redistribution lines; a first inner metal pad, wherein the first inner metal pad is elongated; and', 'a plurality of non-elongated metal pads surrounding the first inner metal pad; and, 'a plurality of metal pads underlying and electrically coupling to the plurality of redistribution lines, wherein the plurality of metal pads comprisesa plurality of solder regions contacting the plurality of metal pads.2. The package of claim 1 , wherein the plurality of metal pads form an array claim 1 , and the array includes four corner metal pads at four corners of the package claim 1 , and the first inner metal pad is in a sub-array of the array claim 1 , and wherein:all metal pads of the sub-array in all edge-rows and all edge-columns of the sub-array are non-elongated, and the first inner metal pad is an inner metal pad of the sub-array.3. The package of claim 1 , wherein the plurality of metal pads comprise a corner metal pad closest to a corner of the package than all of rest of the plurality of metal pads claim 1 , and wherein the corner metal pad is elongated.4. The package of claim 3 , wherein the plurality of metal pads comprises a non-elongated metal pad between the first inner metal pad and the corner metal pad.5. The package of claim 1 , wherein the first device ...

CHIP PACKAGE AND PACKAGING METHOD

A chip package and a packaging method are provided, which relates to the field of communications technologies, and is invented to implement high-frequency electromagnetic interference shielding and effectively improve chip performance. The package includes a package substrate and a metal cap covering the package substrate, where a silicon chip placement area is arranged on an upper surface of the package substrate, multiple first conductive parts are arranged in a peripheral area of the silicon chip placement area, and an edge of the metal cap is in contact with the package substrate and electrically connected to the multiple first conductive parts, where at least a portion of first conductive parts in the multiple first conductive parts are electrically connected to a grounding part by using the metal cap, and the grounding part is arranged on the package substrate, and configured to ground the package substrate. 1. A chip package , comprising:a package substrate and a metal cap covering the package substrate;a silicon chip placement area arranged on an upper surface of the package substrate;first conductive parts are arranged in a peripheral area of the silicon chip placement area;an edge of the metal cap contacting the package substrate and electrically connected to the first conductive parts; andwherein at least one first conductive part of the first conductive parts is electrically connected to a grounding part by using the metal cap, and the grounding part is arranged on the package substrate, and configured to ground the package substrate.2. The package according to claim 1 , wherein a first conductive part in the first conductive parts except the at least one first conductive part is directly and electrically connected to the grounding part claim 1 , and the at least one first conductive part of the first conductive parts is electrically connected claim 1 , by using the metal cap claim 1 , to the first conductive part that is directly and electrically ...

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE

Provided is a semiconductor device that includes: an integrated circuit (IC) chip including a terminal array that is a matrix of terminals arranged in at least seven rows and at least seven columns, the terminals including a reference terminal to which a reference voltage is applied; a capacitor electrically connected to the reference terminal; and a substrate including one main surface as a mounting surface on which the IC chip and the capacitor are mounted. The IC chip is an application specific integrated circuit (ASIC) chip or a field-programmable gate array (FPGA) chip. The reference terminal is disposed at a position within three rows or three columns from an outer edge of the terminal array. 1. A semiconductor device , comprising:an integrated circuit (IC) chip including a terminal array that is a matrix of terminals arranged in at least seven rows and at least seven columns, the terminals including a reference terminal to which a reference voltage is applied;a capacitor electrically connected to the reference terminal; anda substrate including one main surface as a mounting surface on which the IC chip and the capacitor are mounted,wherein the IC chip is an application specific integrated circuit (ASIC) chip or a field-programmable gate array (FPGA) chip, andthe reference terminal is disposed at a position within three rows or three columns from an outer edge of the terminal array.2. A semiconductor device , comprising:an integrated circuit (IC) chip including a terminal array that is a matrix of terminals arranged in at least seven rows and at least seven columns, the terminals including a reference terminal to which a reference voltage is applied;a capacitor electrically connected to the reference terminal; anda substrate including one main surface as a mounting surface on which the IC chip and the capacitor are mounted,wherein the IC chip is an application specific integrated circuit (ASIC) chip or a field-programmable gate array (FPGA) chip,the reference ...

SEMI-CONDUCTOR PACKAGE STRUCTURE

Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein. 1. A semiconductor package structure , comprising:a body enclosing a semiconductor chip and having a bottom surface;a plurality of first-layer electrical contacts disposed on the bottom surface and electrically connected to the semiconductor chip;a plurality of second-layer electrical contacts disposed on the bottom surface and electrically connected to the semiconductor chip;a plurality of third-layer electrical contacts disposed on the bottom surface and electrically connected to the semiconductor chip; anda plurality of fourth-layer electrical contacts disposed on the bottom surface and electrically connected to the semiconductor chip, the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts being arranged sequentially from outside to inside on the bottom surface in a matrix manner,wherein adjacent ones of the first-layer electrical contacts have two different spacings therebetween, and adjacent ones of the third-layer electrical contacts have the two different spacings therebetween, wherein said two different spacing comprise a first spacing and a second spacing greater than the first spacing.2. The semiconductor package structure of claim 1 , wherein the second spacing is twice the first spacing.3. The semiconductor package structure of claim 1 , wherein the first spacing is a minimum spacing between adjacent ones of the first-layer electrical contacts.4. The semiconductor package structure of claim 1 , wherein ...

BONDED SEMICONDUCTOR PACKAGE AND RELATED METHODS

Implementations of a semiconductor package may include: a first wafer having a first surface and a first set of blade interconnects, the first set of blade interconnects extending from the first surface. The package may include a second wafer having a first surface and a second set of blade interconnects, the second set of blade interconnects extending from the first surface and oriented substantially perpendicularly to a direction of orientation of the first set of blade interconnects. The first set of blade interconnects may be hybrid bonded to the second set of blade interconnects at a plurality of points of intersection between the first and second set of blade interconnects. The plurality of points of intersection may be located along a length of each blade interconnect of the first set of blade interconnects, and along the length of each blade interconnect of the second set of blade interconnects. 1. A semiconductor package comprising:a first wafer having a first surface;a first set of blade interconnects coupled to the first surface of the first wafer, the first set of blade interconnects extending from the first surface;a second wafer having a first surface; anda second set of blade interconnects coupled to the first surface of the second wafer, the second set of blade interconnects extending from the first surface and oriented substantially perpendicularly to a direction of orientation of the first set of blade interconnects;wherein the first set of blade interconnects is hybrid bonded to the second set of blade interconnects at a plurality of points of intersection between the first set and second set of blade interconnects; andwherein the plurality of points of intersection are located along a length of each blade interconnect of the first set of blade interconnects, and are located along the length of each blade interconnect of the second set of blade interconnects.2. The semiconductor package of claim 1 , wherein the first set of blade interconnects and ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the semiconductor body. The semiconductor package structure also includes an insulating layer surrounding the conductive structure. The semiconductor package structure further includes a redistribution layer structure coupled to the conductive structure. In addition, the semiconductor package structure includes a molding compound surrounding the semiconductor body. A portion of the molding compound extends between the redistribution layer structure and the semiconductor body. 1. A semiconductor package structure , comprising:a semiconductor body;a conductive structure disposed below the semiconductor body;an insulating layer surrounding the conductive structure;a redistribution layer structure coupled to the conductive structure; anda molding compound surrounding the semiconductor body, wherein a portion of the molding compound extends between the redistribution layer structure and the semiconductor body.2. The semiconductor package structure as claimed in claim 1 , wherein the semiconductor body has a surface facing the redistribution layer structure claim 1 , and the portion of the molding compound is in direct contact with the surface of the semiconductor body.3. The semiconductor package structure as claimed in claim 1 , further comprising a dielectric layer between the semiconductor body and the insulating layer claim 1 , wherein the dielectric layer surrounds a lower portion of the conductive structure and the insulating layer surrounds an upper portion of the conductive structure.4. The semiconductor package structure as claimed in claim 3 , wherein the portion of the molding compound is sandwiched between the redistribution layer structure and the dielectric layer.5. The semiconductor package structure as claimed in claim 1 , wherein the semiconductor body is wider than the insulating layer.6. The ...

SEMICONDUCTOR PACKAGE INCLUDING TEST BUMPS

Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump. 1. A semiconductor package , comprising:a first semiconductor chip;at least one second semiconductor chip stacked on the first semiconductor chip;a mold layer covering the first semiconductor chip and the second semiconductor chip,wherein the first semiconductor chip has a width greater than a width of the second semiconductor chip, a plurality of outer bumps on a bottom surface of the second semiconductor chip and being adjacent to an edge of the second semiconductor chip;', 'a plurality of inner bumps on the bottom surface of the second semiconductor chip and being adjacent to a center of the second semiconductor chip', 'a plurality of first through electrodes penetrating the second semiconductor chip and connected with the outer bumps; and', 'a plurality of second through electrodes penetrating the second semiconductor chin and connected with the inner bumps,, 'wherein the second semiconductor chip includeswherein a first interval between one of the outer bumps and one of the plurality of inner bumps that in moot adjacent to each other being greater than a second interval between the outer bumps, andwherein the outer bumps have a width equal to or ...

SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD

A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated. 1. A semiconductor device , comprising:a semiconductor die mounted at a die area of a package with an array of electrically-conductive balls providing electrical contact for the semiconductor die; anda power channel to convey a power supply current to the semiconductor die; at least one electrically-conductive connection plane layer extending in a longitudinal direction of the electrically-conductive connection plane layer between a distal end at the periphery of the package and a proximal end at the die area of the package; and', 'a distribution of electrically-conductive balls distributed along the longitudinal direction of the electrically conductive connection plane layer;', 'said electrically-conductive connection plane layer comprising subsequent portions in said longitudinal direction between adjacent electrically-conductive balls in said distribution;', 'wherein said subsequent portions have respective electrical resistance values, wherein said respective electrical resistance values decrease from said distal end to said proximal end of the electrically- ...

SEMI-CONDUCTOR PACKAGE STRUCTURE

Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein. 1. A semiconductor device , comprising:a semiconductor chip mounted to a package body;an array of locations on an external surface of the package body having a regular array spacing between locations in the array, the array spacing being substantially the same in an X and Y direction within a plane of the array,a plurality of contacts located at selected locations in the array, the plurality of contacts electrically connected to the semiconductor chip, the plurality of contacts including:a first layer, wherein the first layer includes contacts located at first array locations within the first layer, and one or more gaps located at second array locations within the first layer; anda second layer located inside the first layer, the second layer including contacts at all array locations within the second layer.2. The semiconductor device of claim 1 , wherein the first layer is located on a periphery of the package body.3. The semiconductor device of claim 1 , wherein the second layer is directly adjacent the first layer.4. The semiconductor device of claim 1 , wherein the second layer is spaced apart from the first layer by one or more intermediate layers.5. The semiconductor device of claim 1 , wherein the one or more gaps in the first layer includes multiple regularly spaced gaps.6. The semiconductor device of claim 1 , wherein a contact is located at a first two array locations at each corner of the first layer.7. The semiconductor device of claim 1 , ...

BUMP LAYOUT FOR COPLANARITY IMPROVEMENT

A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas. 1. A method comprising:receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area;grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, wherein a bump pattern density of the second region is lower than that of the first region;forming a second design by modifying the first design, wherein modifying the first design comprises modifying a cross-section area of the second group of conductive bumps in the second region; andforming the conductive bumps on the first surface of the interposer in accordance with the second design, wherein after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.2. The method of claim 1 , wherein a size of the first group of conductive bumps remain unchanged in the first design and the second design.3. The method of claim 1 , ...

THROUGH-SUBSTRATE UNDERFILL FORMATION FOR AN INTEGRATED CIRCUIT ASSEMBLY

An integrated circuit package may be fabricated by disposing an underfill material between an electronic substrate and an integrated circuit device through an opening in the electronic substrate. In one embodiment, an integrated circuit assembly may include an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one opening extending from the first surface to the second surface. The integrated circuit assembly may further include an integrated circuit device, wherein the integrated circuit device is electrically attached to the electronic substrate with at least one interconnect, and an underfill material may be disposed between the first surface of the electronic substrate and the integrated circuit device, wherein a portion of the underfill material extends into the opening in the electronic substrate. 1. An integrated circuit assembly comprising:an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one opening extending from the first surface to the second surface;an integrated circuit device, wherein the integrated circuit device is electrically attached to the electronic substrate with at least one interconnect; andan underfill material between the first surface of the electronic substrate and the integrated circuit device, wherein a portion of the underfill material extends into the opening in the electronic substrate.2. The integrated circuit assembly of claim 1 , wherein at least one of the integrated circuit device and the electronic substrate includes a trench formed therein claim 1 , wherein the trench is positioned proximate a gap between the integrated circuit and the electronic substrate.3. The integrated circuit assembly of claim 2 , wherein a portion of the underfill material resides within the trench.4. The integrated circuit assembly of claim 1 , wherein the underfill material substantially surrounds ...

THROUGH-SUBSTRATE VOID FILLING FOR AN INTEGRATED CIRCUIT ASSEMBLY

Integrated circuit assemblies may contain various mold, fill, and/or underfill materials. As these integrated circuit assemblies become ever smaller, it becomes challenging to prevent voids from forming within these materials, which may affect the reliability of the integrated circuit assemblies. Since integrated circuit assemblies are generally formed by electrically attaching integrated circuit dice on electronic substrates, the present description proposes injecting the mold, fill, and/or underfill materials through openings formed in the electronic substrate to fill voids that may form and/or to prevent the formation of the voids altogether. 1. An integrated circuit assembly , comprising:an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one inlet opening extending from the first surface to the second surface;at least one integrated circuit die attached to the electronic substrate;at least one void defined by the electronic substrate and the integrated circuit die; anda fill material within the at least one void, wherein a portion of the fill material extends into the opening in the electronic substrate.2. The integrated circuit assembly of claim 1 , further comprising a mold material on the electronic substrate and the at least one integrated circuit die.3. The integrated circuit assembly of claim 2 , wherein the at least one void is further defined by the mold material.4. An electronic system claim 2 , comprising:an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one inlet opening extending from the first surface to the second surface;at least two first level integrated circuit dice having a first surface and an opposing second surface, wherein the second surface of each at least two integrated first level integrated circuit attached to the electronic substrate;at least one second level integrated circuit ...

SEMICONDUCTOR DEVICE

A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction “X” and a plurality of sub-wiring units extending in a direction “Y”, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction “X” and a plurality of sub-wiring units extending in the direction “Y”, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction “X” between the main wiring units. To the end units, via wirings are coupled. 1. A semiconductor device comprising:a semiconductor chip which has a first surface, a first back surface on a side opposed to the first surface, and a plurality of electrodes arranged on the first surface; anda wiring substrate which has a first main surface on which the semiconductor chip is mounted, a second main surface on a side opposed to the first main surface, a first wiring layer which is formed between the first main surface and the second main surface, and a second wiring layer which is formed between the first wiring layer and the second main surface and adjacent to the first wiring layer in a cross sectional view in a direction crossing the first main surface, a first wiring having a first main wiring unit extending in a first direction in a cross sectional view and a plurality of first sub-wiring units, extending in a second direction crossing the first direction and crossing the first main wiring unit, and the first wiring being supplied with a first potential,', 'a second wiring having a second main wiring unit extending in the first direction in the cross sectional view and a plurality of second sub-wiring units, extending in the second direction ...

SEMI-CONDUCTOR PACKAGE STRUCTURE

Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein. 1. A semiconductor device , comprising:a semiconductor chip mounted to a package body;an array of locations on the package body having a regular array spacing between locations in the array, the array spacing being substantially the same in an X and Y direction within a plane of the array, a first layer of contacts located at locations in the array, wherein the first layer includes a series of regularly spaced gaps in the first layer of contacts, the regularly spaced gaps located at locations in the array;', 'a second layer of contacts located at locations in the array, the second layer located inside the first layer;', 'a third layer of contacts located at locations in the array, the third layer located inside the second layer; and', 'a fourth layer of contacts located at locations in the array, the fourth layer located inside the third layer., 'a plurality of contacts located at selected locations in the array, the plurality of contacts electrically connected to the semiconductor chip, the plurality of contacts including2. The semiconductor device of claim 1 , wherein the regular spaced gaps are at every third array location in the first layer.3. The semiconductor device of claim 1 , wherein the regular spaced gaps are continuous across at least one side of the package body.4. The semiconductor device of claim 1 , further including one or more gaps in the third layer of contacts claim 1 , the gaps located at locations in the array.5. The semiconductor ...

Method for bonding semiconductor components

A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies. The method allows to improve the throughput of the bonding process, as the heating step takes place only once for a plurality of dies and/or wafers.

SEMICONDUCTOR PACKAGES

A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path. 1. A semiconductor package comprising:a package substrate including a first region;a thermal block in the first region of the package substrate, the thermal block exposed at a top surface and at a bottom surface of the package substrate;a semiconductor chip on the package substrate;a plurality of bumps between the package substrate and the semiconductor chip, the plurality of bumps including first bumps in contact with the thermal block; anda plurality of terminals on the bottom surface of the package substrate, the plurality of terminals including first terminals in contact with the thermal block,wherein the thermal block is one of a power path and a ground path.2. The semiconductor package of claim 1 , wherein the package substrate further includes a second region spaced apart from the first region claim 1 , the semiconductor package further comprising:a second thermal block in the second region of the package substrate.3. The semiconductor package of claim 2 , wherein the plurality of bumps further include second bumps claim 2 ,wherein the plurality of terminals further include second terminals, andwherein the second bumps and the second terminals are in contact with the second thermal block.4. (canceled)5. The semiconductor package of claim 1 , wherein the first bumps include first edge bumps vertically overlapping with an outermost region of the first region claim 1 ,wherein the plurality of ...

REACTIVE BONDING OF A FLIP CHIP PACKAGE

An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process. 1. A structure for bonding substrates comprising a substrate having an array of bonding pads thereupon , wherein each of said bonding pads comprises at least one unit reactive-material-including stack that includes a set of reactive materials including a first material and a second material that , upon ignition , react spontaneously to form an alloy or a composite of said first material and said second material , wherein a magnetic material is present within each of said bonding pads as said first material , said second material , or an additional metal.2. The structure of claim 1 , further comprising another substrate bonded to an array of solder balls and overlying or underlying said substrate claim 1 , wherein said array of solder balls is oriented in a direction that faces said array of bonding pads.3. The structure of claim 2 , wherein said array of solder balls contacts said array of bonding pads.4. The structure of claim 2 , further comprising an apparatus for generating a time-varying magnetic field claim 2 , said apparatus oriented such that a magnetic field is applied to said array of bonding pads ...

Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages

An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure. 1. A method for testing a package structure comprising: first testing structures on a first substrate; and', 'first functional circuitry on the first substrate and independent from the first testing structures; and, 'electrically testing a first plurality of conductive connectors in a first package, wherein the first plurality of conductive connectors bonds a first package component to a second package component, and wherein the first package component comprises second testing structures on a second substrate and having a same circuit layout as the first testing structures, wherein a first electrical signal sent through the first testing structures during electrically testing the first plurality of conductive connectors is a same signal as a second electrical signal sent through the second testing structures during electrically testing the second plurality of conductive connectors; and', 'second functional circuitry on the second substrate and independent from the second testing structures, wherein the second functional circuitry has a different circuit layout as the first functional circuitry., 'electrically testing a second plurality of conductive connectors in a second package, wherein the second plurality of conductive connectors bonds a third package component to a fourth package component, and wherein the third package component comprises2. The method of claim 1 , wherein the second package component comprises a first probing pad electrically connected to the first testing structures claim 1 , wherein electrically testing the first plurality of conductive connectors ...

Semiconductor Device and Method of Forming Inverted Pyramid Cavity Semiconductor Package

A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die. 1. A semiconductor device , comprising:a first substrate including a first cavity formed through the first substrate;a conductive layer formed over a surface of the first substrate with the conductive layer exposed in the first cavity;a first semiconductor die disposed in the first cavity and on the conductive layer;a second substrate including a second cavity disposed over the first substrate with the second cavity larger than the first cavity; anda second semiconductor die disposed in the second cavity.2. The semiconductor device of claim 1 , wherein a portion of the first substrate is exposed within the second cavity.3. The semiconductor device of claim 2 , wherein the second semiconductor die is disposed over the portion of the first substrate exposed within the second cavity.4. The semiconductor device of claim 1 , further including a passive device disposed over the second substrate and second semiconductor die.5. The semiconductor device of claim 1 , further including an encapsulant ...

Transmission of data for a machine learning operation using different microbumps

A system includes a memory device with microbumps and a processing device. The processing device is operatively coupled with the memory device to perform operations. The operations include transmitting data for a machine learning operation based on a set of the microbumps of the memory device where the data is being stored at the memory device. In addition, the operations include determining a change in a condition of the machine learning operation. Furthermore, the operations include that, in response to determining the change in the condition of the machine learning operation, determining a new set of the microbumps of the memory device that are to transmit subsequent data for the machine learning operation. Moreover, the operations include transmitting the subsequent data using the new set of microbumps of the memory device.

Semiconductor device and method of manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate including a plurality of conductive traces and a semiconductor chip. The semiconductor chip comprises a surface facing the plurality of conductive traces and a plurality of conductive pads on the surface and correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.

DIE-DIE STACKING STRUCTURE AND METHOD FOR MAKING THE SAME

The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer. The structure and method of present invention at least provide more strength and stress buffer to resist die warpage and absorb thermal cycling stress, and then prevents the bump and dielectric materials in the die-die stacking structure from cracking caused by thermal stress or external mechanical stress. 1. A die assembly , comprising:a die having an upper surface and a bottom surface;an insulation layer covering at least one of the upper surface and the bottom surface of the die;a plurality of connection members which pass through the insulation layer to connect with the die;a protection material on the surface of the insulation layer;wherein the protection material bridges the plurality of connection members to form a mesh layout on the insulation layer.2. The die assembly of claim 1 , wherein each of the plurality of connection members comprises a first connecting element claim 1 , wherein an end of the first connecting element passes through the insulation layer to connect with the die.3. The die assembly of claim 1 , wherein each of the plurality of connection members comprises a first connecting element and a second connecting element claim 1 , wherein an end of the first connecting element passes through the insulation ...

CHIP CARRIER HAVING VARIABLY-SIZED PADS

Chip carriers having variably-sized solder pads, and integrated circuit packages incorporating such chip carriers are described. In an example, an integrated circuit package includes an integrated circuit electrically connected with a chip carrier having solder pads of different sizes. The integrated circuit may deliver high speed signals to smaller solder pads and low speed signals to larger solder pads. More particularly, the solder pads having smaller pad dimensions may better match impedance of a high speed signal line as compared to the solder pads having larger pad dimensions. 1. A chip carrier , comprising:a package substrate having a first surface and a second surface; a set of first solder pads, each first solder pad having a first pad dimension across a first pad surface, and', 'a set of second solder pads, each second solder pad having a second pad dimension across a second pad surface, wherein the second pad dimension is less than the first pad dimension; and, 'a plurality of solder pads mounted on the first surface in a pattern, wherein the plurality of solder pads includes'}a plurality of bonding pads mounted on the second surface and electrically connected to the plurality of solder pads through the package substrate.2. The chip carrier of claim 1 , wherein the pattern includes a grid pattern claim 1 , and wherein one or more of the second solder pads are between a pair of first solder pads in a row of the grid pattern.3. The chip carrier of claim 2 , wherein the set of second solder pads are arranged in a grid block claim 2 , and wherein the grid block is between the pair of first solder pads in the row of the grid pattern.4. The chip carrier of claim 3 , wherein the grid pattern includes an outer column of solder pads claim 3 , and wherein the grid block is one or more rows inward from the outer column.5. The chip carrier of claim 1 , wherein the first pad dimension is greater than 600 microns claim 1 , and wherein the second pad dimension is less ...

IC PACKAGE WITH METAL INTERCONNECT STRUCTURE IMPLEMENTED BETWEEN METAL LAYERS OF DIE AND INTERPOSER

An integrated circuit package includes a die having a first substrate implementing an integrated circuit comprising circuit elements. The die includes a first plurality of metal layers implementing a first portion of a metal interconnect structure for the integrated circuit. The die also includes a first plurality of pads at or overlying a top metal layer of the first plurality of metal layers. The integrated circuit package includes an interposer having a second plurality of metal layers implementing a second portion of the metal interconnect structure. The interposer includes a second plurality of pads at or overlying a top metal layer of the second plurality of metal layers. A plurality of solder structures couple the first and second pluralities of pads. The first and second portions of the metal interconnect structure together complete a signal path between two or more circuit blocks of the integrated circuit. 1. An integrated circuit package comprising: a first substrate implementing an integrated circuit comprising circuit elements at a surface of the first substrate;', 'a first plurality of metal layers disposed at the surface of the first substrate, the first plurality of metal layers implementing a first portion of a metal interconnect structure for the integrated circuit; and', 'a first plurality of pads at or overlying a top metal layer of the first plurality of metal layers;', 'wherein the first portion of the metal interconnect structure comprises a first metal interconnect path coupled between a first circuit block of the integrated circuit and a first pad of the first plurality of pads and comprises a second metal interconnect path coupled between a second circuit block of the integrated circuit and a second pad of the plurality of pads, wherein the second metal interconnect path does not connect to the first metal interconnect path within the first plurality of metal layers; and, 'a die comprising a second plurality of metal layers disposed at a ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding. 116-. (canceled)17. A semiconductor device comprising:a semiconductor chip having a first surface over which a plurality of electrode pads are disposed and a second surface opposite the first surface; anda wiring board having a first main surface over which a plurality of wirings and an insulating film are formed,wherein the semiconductor chip is mounted over the first main surface of the wiring board such that the first surface of the semiconductor chip faces the first main surface,wherein an opening is formed in the insulating film such that parts of a first wiring are exposed from the opening,wherein each of the parts of the first wiring exposed from the opening are coated with solder,wherein the first wiring has a first part which is an end portion thereof, a second part, and a third part located between the first and second parts,wherein, in a plan view, the first and second parts are exposed from the opening and the third part is covered with the insulating film,wherein, in the plan view, a wide-width portion of which a width is wider than a width of each of other portions in a direction perpendicular to a direction in which each of the plurality of wirings extends is formed at each of the first and second ...

Method for producing an integrated circuit package and apparatus produced thereby

A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via.

Protrusion Bump Pads for Bond-on-Trace Processing

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die. 1. An apparatus , comprising:a substrate;a plurality of conductive traces disposed on a side of the substrate;a plurality of conductive members each extending into the substrate from a corresponding one of the conductive traces; anda plurality of bump pads each protruding from one of a first subset of the conductive traces, wherein a second subset of the conductive traces are recessed within the side of the substrate.2. The apparatus of wherein the side is a first side claim 1 , and wherein ones of the plurality of conductive members are conductive pillars extending to corresponding conductive features disposed on a second side of the substrate.3. The apparatus of wherein the plurality of conductive traces are laterally offset from one another by a minimum trace pitch claim 1 , the plurality of bump pads are laterally offset from one another by a minimum bump pad pitch claim 1 , and the minimum bump pad pitch is substantially greater than the minimum trace pitch.4. The apparatus of wherein the plurality of conductive traces are laterally offset from one another by a minimum trace pitch claim 1 , the plurality of bump pads are laterally offset from one another by a minimum bump pad pitch claim 1 , and the minimum bump pad pitch is at least about twice the minimum trace pitch.5. The apparatus of wherein the plurality of conductive traces are laterally offset from one another by a minimum ...

Ball Grid Array Rework

Embodiments relate to a method and apparatus for rework of a BGA package. Memory shape material is placed adjacent to a plurality of solder joints of the package. Stimulation is applied to the material, with the stimulation causing the material to change from a non-stimulated shape to a stimulated shape. This stimulation causes an expansion of the material. As the material expands, it exerts a tensile force on the BGA package and an adjacently positioned carrier, causing a separation of the two components, while mitigating collateral heat of adjacently positioned components. 1. A method comprising:placing a material between a ball grid array (BGA) package and a printed circuit board; andstimulating the material, the stimulation expanding the material and increasing separation between the BGA package and the printed circuit board.2. The method of claim 1 , wherein the stimulation is by a thermal stimulus.3. The method of claim 1 , wherein the stimulation is by an electrical stimulus.4. The method of claim 1 , wherein the stimulation is by a chemical stimulus.5. The method of claim 1 , wherein the material is placed interstitially with respect to a matrix of solder joints between the BGA package and the printed circuit board.6. The method of claim 1 , wherein the material is placed around a perimeter of a matrix of solder joints between the BGA package and the printed circuit board.7. The method of claim 1 , wherein the material is selected from the group consisting of: a memory shape alloy and a high z-axis coefficient of thermal expansion material.8. The method of claim 1 , further comprising delivering heat to the solder joints concurrent with stimulation of the material.9. The method of claim 1 , further comprising the expansion elongating the solder joints.10. The method of claim 9 , further comprising the expansion separating the solder joints.11. An apparatus comprising:a ball grid array (BGA) package assembled on to a printed circuit board; anda material ...

SEMICONDUCTOR PACKAGE AND ELECTRONIC APPARATUS

According to one embodiment, a semiconductor package includes a package substrate, a controller chip, a semiconductor memory chip, a temperature sensor, a seal portion, and a plurality of solder balls. The controller chip and the semiconductor memory chip are provided on a first surface of the package substrate. The temperature sensor is provided at a position along an edge of the first surface, which is at a center portion separated away from corner portions. The plurality of solder balls is provided on a second surface that is at an opposite side of the first surface. 1. A semiconductor package comprising:a package substrate including a first surface;a controller chip provided on the first surface of the package substrate;a semiconductor memory chip provided on the first surface;a temperature sensor provided at a position along an edge of the first surface, which is at a center portion separated away from corner portions;a seal portion provided on the first surface and configured to cover the controller chip, the semiconductor memory chip, and the temperature sensor; anda plurality of solder balls provided on a second surface that is at an opposite side of the first surface.2. The semiconductor package according to claim 1 , wherein the semiconductor memory chip is stacked on the controller chip.3. The semiconductor package according to claim 2 , wherein the position where the temperature sensor is provided is a position that overlaps a region to which the controller chip is moved along one edge of the first surface.4. The semiconductor package according to claim 2 , wherein the temperature sensor is provided at the position along an edge among four edges of the first surface claim 2 , the edge being closest to the controller chip in a plan view.5. The semiconductor package according to claim 2 , further comprising an EEPROM provided in the vicinity of the corner portion of the first surface claim 2 ,wherein the seal portion covers the EEPROM.6. The semiconductor ...

Pad structure design in fan-out package

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.

Ball Grid Array Rework

Embodiments relate to an apparatus for rework of a BGA package. Memory shape material is placed adjacent to a plurality of solder joints of the package. Stimulation is applied to the material, with the stimulation causing the material to change from a non-stimulated shape to a stimulated shape. This stimulation causes an expansion of the material. As the material expands, it exerts a tensile force on the BGA package and an adjacently positioned carrier, causing a separation of the two components, while mitigating collateral heat of adjacently positioned components. 1. An apparatus comprising:a ball grid array (BGA) package assembled on to a printed circuit board; anda material placed between the BGA package and the printed circuit board, wherein exposure of the material to a stimulation changes a shape of the material.2. The apparatus of claim 1 , wherein the material is placed interstitially with respect to a matrix of solder joints between the BGA package and the printed circuit board.3. The apparatus of claim 1 , further comprising an applicator in communication with the material claim 1 , the applicator to apply a tensile force between the BGA package and the printed circuit board.4. The apparatus of claim 3 , wherein the tensile force is controlled by a regulator in communication with the applicator.5. The apparatus of claim 1 , wherein the material is placed around a perimeter of a matrix of solder joints between the BGA package and the printed circuit board.6. The apparatus of claim 1 , wherein the stimulation is by an electrical stimulus.7. The apparatus of claim 1 , wherein the stimulation is by a thermal stimulus.8. The apparatus of claim 1 , wherein the stimulation is by a chemical stimulus.9. The apparatus of claim 1 , further comprising the stimulation to elongate and separate the solder joints claim 1 , including a first part of the solder to remain in communication with the BGA package and a second part of the solder to remain in communication with ...

BALL GRID ARRAY PACKAGE WITH PROTECTIVE CIRCUITRY LAYOUT AND A SUBSTRATE UTILIZED IN THE PACKAGE

Disclosed is a BGA package with protective circuitry layouts to prevent cracks of the bottom circuit in the specific area of the substrate leading to package failure and to enhance packaging yield of BGA packages. A chip is disposed on the upper surface of the substrate. A chip projective area is defined inside the bottom surface of the substrate and is established by vertically projecting the edges of the chip on the upper surface to the bottom surface of the substrate. At least an external contact pad vulnerable to thermal stress is located within the chip projective area. A protective area and a wiring area are respectively defined in the chip projective area at two opposing sides of the external contact pad. A plurality of protective mini-pads are arranged in a dotted-line layout and disposed in the projective area to partially surround the external contact pad to avoid thermal stress concentrated on the protective area and to further prevent circuitry cracks in the package structure. 1. A semiconductor package comprising:a chip having an active surface and a plurality of edges around the active surface; anda substrate including:an upper surface on which the chip is disposed;a bottom surface opposing to the upper surface; the bottom surface having a chip projective area defined inside the substrate and a peripheral area surrounding the chip projective area, wherein the chip projective area is established by vertically projecting the edges of the chip to the upper surface and through the substrate and to the bottom surface of the substrate;a plurality of first contact pads disposed inside the chip projective area on the bottom surface, wherein the first contact pads include at least an external contact pad adjacent to the peripheral area, wherein a protective area and a wiring area are disposed in a periphery of the external contact pad on the chip projective area opposite to each other;a circuitry disposed inside the wiring area on the bottom surface; anda ...

METHOD FOR MAKING SUPPORT STRUCTURE FOR PROBING DEVICE

A method for making a support structure for a probing device includes a step of providing a substrate having first internal conductive lines, a carrier having second internal conductive lines and a thickness less than 2 mm for packaging an integrated circuit chip, solder balls, and photoresist support blocks made by lithography in a way that the solder balls and the photoresist support blocks are disposed between the substrate and the carrier, the photoresist support blocks separately arranged from each other, and at least one of the photoresist support blocks is disposed between two adjacent solder balls. The method further includes a step of electrically connecting the first internal conductive lines with the second internal conductive lines respectively by soldering the carrier and the substrate with the solder balls by reflow soldering. 1. A method for making a support structure for a probing device , comprising the steps of:a) providing a substrate having a plurality of first internal conductive lines, a carrier having a plurality of second internal conductive lines and a thickness less than 2 mm for packaging an integrated circuit chip, a plurality of photoresist support blocks made by lithography, and a plurality of solder balls in a way that the photoresist support blocks and the solder balls are disposed between the substrate and the carrier, the photoresist support blocks are separately arranged, and at least one of the photoresist support blocks is disposed between two adjacent said solder balls; andb) soldering the carrier and the substrate with the solder balls by reflow soldering to electrically connect the first internal conductive lines with the second internal conductive lines respectively.2. The method as claimed in claim 1 , wherein the at least one of the photoresist support blocks is disposed between two adjacent said solder balls in a way that the two adjacent said solder balls define therebetween an interval larger than 20 μm.3. The method as ...

PACKAGE ON PACKAGE ARRANGEMENT AND METHOD

A method of forming a package on package, semiconductor package arrangement is described. In one aspect, solder bumps on a lower surface of a first grid array package substrate are fused to corresponding unencapsulated solder bumps on an upper surface of a second grid array package substrate. The fused solder bumps form solder joints that electrically connect the first and second packages. The height of the resulting solder joints is greater than a height of a die that is flip chip mounted to the second substrate such that the first substrate does not contact any portion of the second package and an air gap is formed that separates the second die from the first package. Corresponding PoP packages structures are also described. 1. A method of packaging integrated circuits comprising:providing a first grid array package having a first substrate, a first die mounted on the first substrate and a multiplicity of first solder bumps on a lower surface of the first substrate, the multiplicity of first solder bumps being exposed at the lower surface of the first grid array package;providing a second grid array package having a second substrate, a second die flip chip mounted on a top surface of the second substrate, a multiplicity of second solder bumps on a lower surface of the second substrate, and a multiplicity of third solder bumps on the top surface of the second substrate, wherein the multiplicity of second solder bumps are exposed at a lower surface of the second grid array package, and wherein the multiplicity of third solder bumps are not surrounded by any molding material and have a spacing that matches a spacing of the first solder bumps;fusing the first solder bumps to corresponding ones of the third solder bumps to thereby form solder joints that electrically couple the first grid array package to the second grid array package and to thereby form a stacked package on package, wherein the respective sizes of the first and third solder balls are arranged such ...

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE STRUCTURE

A chip package structure and a method for forming a chip package are provided. The chip package structure includes a chip package over a printed circuit board and multiple conductive bumps between the chip package and the printed circuit board. The chip package structure also includes one or more thermal conductive elements between the chip package and the printed circuit board. The thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps. 1. A chip package structure , comprising:a chip package over a printed circuit board;a plurality of conductive bumps between the chip package and the printed circuit board; andat least one thermal conductive element between the chip package and the printed circuit board, wherein the thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps.2. The chip package structure as claimed in claim 1 , wherein the conductive bumps comprise solder bumps claim 1 , solder balls claim 1 , or a combination thereof3. The chip package structure as claimed in claim 1 , wherein the thermal conductive element comprises a metal foil.4. The chip package structure as claimed in claim 1 , wherein the thermal conductive element comprises a copper foil.5. The chip package structure as claimed in claim 1 , further comprising:a first bonding layer between the thermal conductive element and the chip package; anda second bonding layer between the thermal conductive element and the printed circuit board.6. The chip package structure as claimed in claim 5 , wherein the first bonding layer and the second bonding layer are made of a solder material.7. The chip package structure as claimed in claim 5 , wherein the first bonding layer and the second bonding layer are made of different solder materials.8. The chip package structure as claimed in claim 7 , wherein the first bonding layer has a melting point higher than that of the second ...

INTEGRATED CIRCUIT AND ELECTRONIC DEVICE COMPRISING A PLURALITY OF INTEGRATED CIRCUITS ELECTRICALLY COUPLED THROUGH A SYNCHRONIZATION SIGNAL

An electronic device has a plurality of integrated circuits fixed to a support between transmitting and receiving antennas. An integrated circuit generates a synchronization signal supplied to the other integrated circuits. Each integrated circuit is formed in a die integrating electronic components and overlaid by a connection region according to the Flip-Chip Ball-Grid-array or embedded Wafer Level BGA. A plurality of solder balls for each integrated circuit is electrically coupled to the electronic components and bonded between the respective integrated circuit and the support. The solder balls are arranged in an array, aligned along a plurality of lines parallel to a direction, wherein the plurality of lines comprises an empty line along which no solder balls are present. A conductive synchronization path is formed on the support and extends along the empty line of at least one integrated circuit, between the solder balls of the latter. 1. An integrated circuit package , comprising:a die including semiconductor material and integrated electronic components;a connection region overlying the die; anda plurality of solder balls, fixed to the connection region and electrically coupled to the electronic components, the solder balls being arranged in an array and being aligned along a plurality of lines parallel to a direction,wherein the plurality of lines includes an empty line along which no solder balls are present.2. The integrated circuit package according to claim 1 , wherein the first lines are arranged at a mutually uniform claim 1 , first distance and first adjacent lines belonging to the plurality of lines and directly adjacent the empty line claim 1 , are arranged at a mutual claim 1 , second distance claim 1 , the second distance being greater than the first distance.3. The integrated circuit package according to claim 2 , wherein the second distance is twice the first distance.4. The integrated circuit package according to claim 1 , wherein the ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, and a redistribution structure disposed on the first semiconductor die and the insulating encapsulation. The first semiconductor die includes a first contact region and a first non-contact region in proximity to the first contact region. The first semiconductor die includes a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, and the first electrical connector is electrically connected to a first integrated circuit (IC) component in the first semiconductor die. The first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure. 1. A semiconductor package , comprising:a first semiconductor die, comprising a first contact region and a first non-contact region in proximity to the first contact region, the first semiconductor die comprising a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, the first electrical connector being electrically connected to a first integrated circuit (IC) component in the first semiconductor die;an insulating encapsulation, laterally encapsulating the first semiconductor die; anda redistribution structure, disposed on the first semiconductor die and the insulating encapsulation, wherein the first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure.2. The semiconductor package of claim 1 , whereinat least two sides of the ...

Electronic control device

A control unit that controls a motor includes a semiconductor device, the semiconductor device includes a semiconductor package including a plurality of first electrodes, a wiring board including a plurality of second electrodes arranged so as to correspond to each of the plurality of first electrodes, and solder joints connecting the plurality of first electrodes and the plurality of second electrodes, and a tip end of a second electrode arranged at an outermost corner of the wiring board is located outside an outer peripheral end of the semiconductor package.

SEMI-CONDUCTOR PACKAGE STRUCTURE

Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein. 1. A semiconductor device , comprising:a semiconductor chip mounted to a package body;an array of locations on the package body having a regular array spacing between locations in the array, the array spacing being substantially the same in an X and Y direction within a plane of the array,a plurality of contacts located at selected locations in the array, the plurality of contacts electrically connected to the semiconductor chip, the plurality of contacts including:a first layer of contacts located at locations in the array, wherein the first layer includes contacts located at selected locations in the array, and one or more gaps located at locations in the array;a second layer of contacts located at locations in the array, the second layer located inside the first layer;a third layer of contacts located at locations in the array, the third layer located inside the second layer; anda fourth layer of contacts located at locations in the array, the fourth layer located inside the third layer.2. The semiconductor device of claim 1 , wherein the one or more gaps in the first layer includes multiple regularly spaced gaps.3. The semiconductor device of claim 1 , further including one or more gaps in the third layer of contacts claim 1 , the gaps located at locations in the array.4. The semiconductor device of claim 1 , further including one or more lateral conductors passing through at least one of the gaps in the first layer.5. The semiconductor device of ...

MULTILAYER SUBSTRATE, COMPONENT MOUNTED BOARD, AND METHOD FOR PRODUCING COMPONENT MOUNTED BOARD

A multilayer substrate includes a flexible element assembly including a principal surface, a first to an n-th external electrode disposed on the principal surface, and at least one first dummy conductor disposed inside the element assembly in a floating state. When the element assembly is viewed from a normal direction of the principal surface, a distance between an m-th external electrode and a nearest external electrode therefrom among the first to the n-th external electrodes is defined as a distance Dm, an average of distances D to Dn is defined as an average Dave, and an area within a circle having a center on the m-th external electrode and having a radius of Dm is defined as an area Am. The first dummy conductor is located in at least one area Am having a radius of Dm greater than the average Dave when viewed from the normal direction.

SEMICONDUCTOR PACKAGE, PRINTED CIRCUIT BOARD SUBSTRATE AND SEMICONDUCTOR DEVICE

A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.

CHIP ALIGNMENT UTILIZING SUPEROMNIPHOBIC SURFACE TREATMENT OF SILICON DIE

Certain embodiments of the present disclosure provide a method for soldering a chip onto a surface. The method generally includes forming a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material. The method may also include treating the dielectric material to render the dielectric material superomniphobic, and soldering the chip onto the bonding pad. 1. A method for soldering a chip onto a surface , comprising:forming a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material;treating the dielectric material to render the dielectric material superomniphobic; andsoldering the chip onto the bonding pad on the surface.2. The method of claim 1 , wherein the chip comprises a bonding pad claim 1 , and wherein soldering the chip onto the bonding pad on the surface comprises:applying solder onto the bonding pad of the chip;placing the chip on the bonding pad on the surface; andreflowing the solder to enable surface tension alignment of the bonding of the chip with the bonding pad on the surface.3. The method of claim 2 , further comprising:aligning the bonding pad of the chip with the bonding pad on the surface.4. The method of claim 3 , wherein the aligning is performed after placing the chip on the bonding pad.5. The method of claim 1 , wherein the dielectric material comprises silicon dioxide.6. The method of claim 1 , wherein the surface on which the chip is to be soldered is a surface of another chip or a substrate.7. The method of claim 1 , wherein treating the dielectric material changes a surface energy of the dielectric material such that a difference between the surface energy of the dielectric material and a surface energy of the bonding pad increases.819-. (canceled) Three-dimensional (3D) integrated circuits have proven to be the favored approach for improving the performance of ...

Semiconductor device

There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h 1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h 2 of the solder layer is measured from the upper surface of the resist layer. Thickness h 1 is greater than or equal to a half of thickness h 2 and is smaller than or equal to thickness h 2 .

SEMICONDUCTOR DEVICE HAVING AN INDUCTOR

A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor. 1. A semiconductor device , comprising: a semiconductor substrate;', 'an interconnect layer including an inductor provided on said semiconductor substrate; and', 'first conductive pads provided on said interconnect layer,, 'a semiconductor chip havingwherein a circuit forming region is provided ri under said first pads, and said first pads are provided in a region, which does not overlap said inductor in a plan view.2. The semiconductor device according to claim 1 , whereinsaid first pads are provided in a plurality of lines in at least one region of first, second, third, and fourth regions,where regions which are closer than said inductor to the first, second, third, and fourth side surfaces of said semiconductor chip in a plan view are defined as said first, second, third, and fourth regions, respectively.3. The semiconductor device according to claim 1 , whereinsaid first pads are provided in at least one of fifth and sixth regions and provided in at least one of seventh and eighth regions,where one pair of facing side surfaces among the first, second, third, and fourth side surfaces of said semiconductor chip are defined as first and second side surfaces and the other pair of facing surfaces are defined as third and fourth side surfaces, andthe regions obtained by extending the region of said inductor to said first and second side surfaces in the direction perpendicular to said first side surface are defined as fifth and sixth regions, respectively, and the regions obtained by extending the ...

SOLID-STATE IMAGING DEVICE

A solid-state imaging device encompasses a detector substrate having a first main-surface, on which a plurality of first lands are arranged in a matrix, and a signal-circuit substrate having a second main-surface, on which plurality of second lands are arranged so as to face the arrangement of the first lands. A plurality of tubular bumps, each of which having a flattened plane pattern, and is provided between each of the first lands and each of the second lands. The tubular bumps respectively have major-axis directions to define inclined angles, and are arranged in the matrix such that the inclined angles differ depending on locations of the plurality of tubular bumps. 1. A solid-state imaging device comprising:a detector substrate having a first main-surface, on which a plurality of first lands are arranged in a matrix;a signal-circuit substrate having a second main-surface, on which plurality of second lands are arranged so as to face the arrangement of the first lands; anda plurality of tubular bumps, each of which having a flattened plane pattern, and is provided between each of the plurality of first lands and each of the plurality of second lands, the plurality of tubular bumps respectively having major-axis directions to define inclined angles, being arranged in the matrix such that the inclined angles differ depending on locations of the plurality of tubular bumps.2. The solid-state imaging device of claim 1 , wherein the second main-surface shares a common center with the first main-surface in a plane pattern.3. The solid-state imaging device of claim 2 , wherein at least a part of the plurality of tubular bumps implement a linear arrangement such that the major-axis directions of the plurality of tubular bumps are respectively aligned with a specified line radiating from the center.4. The solid-state imaging device of claim 3 , wherein the detector substrate further has a plurality of solid-state detectors arranged in the matrix claim 3 ,and wherein the ...

SEMI-CONDUCTOR PACKAGE STRUCTURE

Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside, to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein. 1. A semiconductor device , comprising:a semiconductor chip mounted to a package body; a first layer, wherein the first layer includes contacts with a first spacing, and one or more gaps between contacts having a first layer gap spacing greater than the first spacing;', 'a second layer inside the first layer, wherein the second layer includes contacts with only the first spacing; and', 'a third layer inside the second layer, wherein the third layer includes contacts with the first spacing, and one or more gaps between contacts having a third layer gap spacing greater than the first spacing., 'a number of contacts located on the package body, the number of contacts electrically connected to the semiconductor chip, the number of contacts arranged in an array, array including2. The semiconductor device of claim 1 , wherein the first layer gap spacing is twice the first spacing.3. The semiconductor device of claim 1 , wherein the first layer gap spacing is greater than twice the first spacing.4. The semiconductor device of claim 1 , further including one or more la conductors passing through at least one of the gaps in the first layer.5. The semiconductor device of claim 1 , further including three lateral conductors passing through at least one of the gaps in the first layer.6. The semiconductor device of claim 4 , further including one or snore lateral conductors passing through at least one of the gaps in the third layer.7. The semiconductor device of ...

HIGH-FREQUENCY MODULE

A high-frequency module () includes a substrate (), a first electronic component () and a second electronic component () mounted on a main surface () of the substrate (). The substrate () has a protruding portion () projecting from the main surface (), the first electronic component () is mounted in a region of the main surface () different from a region in which the protruding portion () is provided, and the second electronic component () is mounted on the protruding portion (). 1. A high-frequency module , comprising:a substrate, anda first electronic component and a second electronic component mounted on a main surface of the substrate,wherein the substrate includes a protruding portion projecting from the main surface,the first electronic component is mounted on a region of the main surface different from a region in which the protruding portion is provided, andthe second electronic component is mounted on the protruding portion.2. The high-frequency module according to claim 1 ,wherein the first electronic component is connected to the substrate by a first bonding member, anda height of the protruding portion is higher than a height of the first bonding member.3. The high-frequency module according to claim 1 ,wherein the protrusion portion includes a plurality of columnar electrodes, and a ceramic portion covering side surfaces of the respective columnar electrodes, andthe second electronic component is connected to an end surface of each of the columnar electrodes by a second bonding member.4. The high-frequency module according to claim 3 ,wherein the substrate includes a substrate outer peripheral portion positioned outside of the region in which the protruding portion is provided, andwherein the protruding portion has a rectangular outer shape when the substrate is viewed from a thickness direction of the substrate, and projects in the thickness direction farther than the substrate outer peripheral portion.5. The high-frequency module according to claim 1 ...

Semiconductor device and manufacturing method of semiconductor device

Reliability of joining between semiconductor chips is improved by promoting filling of a sealing resin into a gap formed between the semiconductor chips. A semiconductor device includes: a first semiconductor chip, which has a plurality of first electrodes on a surface; a second semiconductor chip, which is disposed to be separated by a gap from the surface of the first semiconductor chip, and which includes an inner peripheral area that has a plurality of second electrodes connected to each of the first electrodes on a surface and an outer peripheral area that surrounds the inner peripheral area and has a thickness thinner than the thickness of the inner peripheral area; and a sealing resin, which is respectively filled between the surface of the first semiconductor chip and the inner peripheral area, and between the surface of the first semiconductor chip and the outer peripheral area.

Structure and Method for Cooling Three-Dimensional Integrated Circuits

A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules. 1. A method for cooling a three-dimension integrated circuit (3DIC) , the method comprising:measuring temperatures at a plurality of locations in the 3DIC to obtain measured temperatures;determining a location of a heat spot within the 3DIC based on the measured temperatures; andexecuting cooling activities near the location of the heat spot, wherein the cooling activities are executed by cooling elements that include a plurality of individually controllable cooling modules, and wherein certain of the individually controllable cooling modules near the location of the heat spot are turned on.2. The method of claim 1 , wherein the determining the location of the heat spot comprises accessing information on chip bumps.3. The method of claim 1 , wherein the determining the location of the heat spot comprises accessing a graphic data system layout of circuit elements.4. The method of claim 1 , wherein the determining the location of the heat spot comprises accessing information on locations of the plurality of individually controllable cooling modules.5. The method of claim 1 , wherein ...

MICROELECTRONIC ASSEMBLIES

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects. 1. A microelectronic assembly , comprising:a package substrate having a first surface and an opposing second surface;a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer and wherein the first surface of the first die is coupled to the second surface of the package substrate by first interconnects;a second die having a first surface and an opposing second surface, wherein the second die is embedded in a second dielectric layer and wherein the first surface of the second die is coupled to the second surface of the first die by second interconnects; anda third die having a first surface and an opposing second surface, wherein the third die is embedded in a third dielectric layer and wherein the first surface of the third die is coupled to the second surface of the second die by third interconnects.2. The microelectronic assembly of claim 1 , wherein the first surface of the second die is coupled to the second surface of the package substrate by fourth interconnects.3. The microelectronic assembly of claim 2 , wherein the ...

MICROELECTRONIC PACKAGE WITH SOLDER ARRAY THERMAL INTERFACE MATERIAL (SA-TIM)

Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed. 1. A microelectronic package that includes:a package substrate;a die coupled with the package substrate at a first face of the die;a plurality of solder thermal interface material (STIM) thermal interconnects coupled with the die at a second face of the die that is opposite the first face;an integrated heat spreader (IHS) coupled with the plurality of STIM thermal interconnects; anda thermal underfill material positioned between the IHS and the die, wherein the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects.2. The microelectronic package of claim 1 , further comprising a patterning layer positioned between a STIM thermal interconnect of the plurality of STIM thermal interconnects and the IHS.3. The microelectronic package of claim 1 , further comprising a solder resist layer coupled to the second face of the die and adjacent to claim 1 , and at least partially surrounding claim 1 , a STIM thermal interconnect of the plurality of STIM thermal interconnects.4. The microelectronic package of claim 1 , further comprising a solder resist layer coupled to the IHS and adjacent to claim 1 , and at least partially surrounding claim 1 , a STIM thermal interconnect of the plurality of STIM thermal interconnects.5. The microelectronic package of claim 1 , wherein a first STIM thermal interconnect of the plurality of STIM thermal interconnects has a different size or shape than a ...

Pad Structure Design in Fan-Out Package

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated. 1. A package comprising: a first device die; and', 'a first inner metal pad, wherein the first inner metal pad has an elongated top-view shape when viewed in a top view of the package, and wherein the first inner metal pad is at least partially overlapped by the first device die;', 'a plurality of metal pads underlying and electrically coupling to the first device die, wherein the plurality of metal pads comprise], 'a first package comprisinga plurality of solder regions underlying and contacting the plurality of metal pads; anda second package overlying and bonded to the first package.2. The package of claim 1 , wherein the plurality of metal pads further comprise a second inner metal pad overlapped by the first device die claim 1 , wherein the plurality of metal pads is non-elongated.3. The package of claim 1 , wherein the first package comprises:a package corner; anda corner metal pad closer to the package corner than all other metal pads in the first package, wherein the first inner metal pad is spaced apart from the package corner by the corner metal pad.4. The package of claim 3 , wherein the corner metal pad has an additional elongated top-view shape.5. The package of claim 1 , wherein the plurality of metal pads comprise a sub set of metal pads that encircle the first inner metal pad.6. The package of claim 1 , wherein the first device die comprises a die corner claim 1 , and wherein the first inner metal pad is closer to the die corner than all metal ...

电子设备

本公开涉及一种电子设备，具体为一种具有堆叠电子芯片的电子设备，包含：载体基板(2)；至少第一电子芯片(4)和第二芯片(15)；其中第一芯片(4)安装在载体基板(2)上，经由插入的电连接元件(14)将第一芯片的正面电连接网络(8)与载体基板的电连接网络(3)进行连接；第二芯片(15)安装在第一芯片上，经由插入的电连接元件(21)将第二芯片的正面电连接网络(19)与第一芯片的背面电连接网络(11)进行连接；并且电连接线(22)将第一芯片的背面电连接网络与载体基板的电连接网络进行连接。

Package-on-package assembly with wire bonds to encapsulation surface

PURPOSE: A package-on-package assembly with wire bonds on an encapsulation surface of encapsulation layer is provided to easily form a monolithic layer on a substrate by depositing a dielectric material on a first substrate and hardening a deposited dielectric material. CONSTITUTION: A substrate(12) has a first side(14) and a second side(16). The substrate is divided into a first area(18) and a second area(20). A microelectronic element(22) is mounted on a first side of the substrate in the first area. A conductive element(28) includes a contact or a pad(30) exposed to the first side of the substrate. A microelectronic assembly(10) includes a plurality of wire bonds(32) bonded on the pad having the conductive element.

柔性显示面板及其制备方法、柔性显示装置

本发明提供一种柔性显示面板，包括柔性基板；在所述柔性基板的背面形成有背面保护膜；在所述柔性基板和所述背面保护膜之间还设置有胶材；在所述柔性基板和所述背面保护膜之间且对应每个IC Bump位置处设置有支撑体；所述支撑体用于在所述胶材内支撑所述IC Bump。本发明还提供一种柔性显示面板的制备方法和柔性显示装置。本发明可以提高IC bonding后的平坦度，从而能够降低IC边缘处断线和压接不良等问题的产生。