Stack arrangement for FBGA memory module, has encapsulation at central region of each memory chip, constituting spacer between chips, and metallization connected to carrier substrate

A metallization (4) is arranged on an active side of each memory chip, and connected to the bond pad (3) of the memory hip. The metallizations of each individual component (1) is identical. The central regions of each memory chip are provided with an encapsulation (7) which is stacked on the carrier substrate with the same alignment to each other. The encapsulation constitutes a spacer between the chips. Each metallization is connected electrically to the carrier substrate.

Semiconductor device and production method

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENTS, MANUFACTURING METHODS AND COMPONENTS FOR THE SAME

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

MICROELECTRONIC ASSEMBLIES INCLUDING Z-AXIS CONDUCTIVE FILMS

An assembly of two or more microelectronic parts, wherein electrical and/or thermal interconnection between the parts is achieved by means of multiple, discrete, conductive nanoscopic fibrils (15) or tubules (15) fixed within the pores of an insulating film (16). Such a film is said to have anisotropic electrical conductivity, i.e., Z-axis conductivity, with little or no conductivity in the other directions.

半导体装置及其制造方法、电子设备及其制造方法

... 一种半导体装置，在载体基板(11)背面所设的连接盘(12a)上，形成熔点比突出电极(24)还低的突出电极(17)，通过在比突出电极(24)的熔点还低、比突出电极(17)的熔点还高的温度下进行回流焊处理，可以使突出电极(17)接合在母基板(31)的连接盘(32)上。这样，可以防止在载体基板的2次安装时突出电极的融解。 ...

Provided for the semiconductor chip are connected with each other intermediary substrate method and apparatus

半导体封装结构及其制造方法

... 一种半导体封装的结构及其制造方法，该结构包括：具有导体片的构架，每个导体片皆掩埋在通过该构架敞开且按一定间隔设置的数个小孔中的一个中；具有固定于夹具上并在四个方向上延伸的引线的TAB，每根引线用于电连接一个导体片。所说方法包括以下步骤：根据封装的形状提供构架；把引线贴装在夹具上，使之在四个方向上延伸，构成TAB；在构架上按一定间隔形成小孔；在每个小孔中掩埋一个导体片；回流TAB上的引线，电连接引线与各导体片，并把引线贴装到构架上。 ...

LSI electronic circuit support assembly

Assemblage de dispositifs électroniques comprenant un boîtier de support de bande (1) supportant un circuit LSI (2) et ayant des trous traversants (8) disposés bidimensionnellement dans un film et connectés électriquement au circuit LSI par un motif de câblage, et un substrat isolant (3) ayant des broches d'entrée/sortie (4) connectées à des pastilles (9) fournies sur un substrat de montage (6), s'étendant dans et en contact avec les trous (8). Le boîtier de support de bande peut être fabriqué de façon aussi peu coûteuse que le boîtier TBGA de l'état de l'art, à un coût inférieur à celui d'un câblage similaire utilisant un substrat stratifié céramique. La constante diélectrique et d'autres facteurs du matériau du substrat isolant (3) n'ont pas à être pris en compte, et on peut utiliser le matériau le moins coûteux.

반도체 패키지

... 본 발명의 일 실시예에 따른 반도체 패키지는 복수의 배선들이 형성된 기판, 상기 복수의 배선들 중 일부의 배선과 전기적으로 연결된 적어도 하나의 반도체 칩, 및 상기 기판에 실장되어 상기 적어도 하나의 반도체 칩을 둘러싸고, 상기 복수의 배선 중 적어도 하나의 배선과 전기적으로 연결되며, 연자성 물질을 포함하는 쉴딩 캔(shielding can)을 포함하여 전자기 간섭을 제거할 수 있다.

적층가능 마이크로전자 패키지 구조

... 마이크로전자 어셈블리(8)는 제 1 면(14) 및 제 2 면(16) 및 기판 콘택(24)이 있는 기판(12)을 가지는 제 1 마이크로전자 패키지(10A)를 포함한다. 제 1 패키지는 기판 콘택과 전기적으로 접속되고 제 1 면 상에서 서로로부터 이격되어 제 1 및 제 2 마이크로전자 소자 사이에 상호접속 영역을 제공하는 소자 콘택(24)을 가지는 제 1 및 제 2 마이크로전자 소자(40)를 더 포함한다. 제 2 면에서의 복수 개의 패키지 단자(26)는 패키지를 외부 컴포넌트와 접속시키기 위하여 기판 콘택과 상호접속된다. 복수 개의 스택 단자(58)는 패키지를 기판의 제 1 면에 상재하는 컴포넌트와 접속시키기 위하여 상호접속 영역 내의 제 1 면에서 노출된다. 어셈블리는 제 1 마이크로전자 패키지에 상재하며 제 1 마이크로전자 패키지의 스택 단자에 결합되는 단자(26)를 가지는 제 2 마이크로전자 패키지(10B)를 더 포함한다.

SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME

MULTI-LAYER WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE USING THE MULTI-LAYER WIRING SUBSTRATE

CHIP STACK PACKAGE INCLUDING A PACKAGE SUBSTRATE CONNECTED TO A SECOND CHIP VIA PLUGS PENETRATING AN INTERMEDIATE SUBSTRATE, AND A MANUFACTURING METHOD THEREOF

PURPOSE: A chip stack package and a manufacturing method thereof are provided to improve the yield of a first chip since it is not necessary to increase the size of the first chip form formation of plugs. CONSTITUTION: A chip stack package includes an intermediate substrate(110) having a recess(112), a first chip(130) mounted in the recess, and a second chip(140) disposed on the intermediate substrate, the second chip being electrically connected to the first chip. A package substrate(150) is disposed under the intermediate substrate, and plugs(120) penetrate the intermediate substrate to electrically connect the second chip with the package substrate. The recess is disposed at a lower portion of the intermediate substrate, and the first and second chips are electrically connected to each other through second plugs. © KIPO 2008 ...

리세싱된 엣지들을 갖는 반도체 디바이스 및 그 제조방법

... 패키지 엣지를 따라 리세싱된 영역들을 활용하는 디바이스 및 제조 방법이 제공된다. 예를 들어, 집적형 팬 아웃 패키지에 있어서, 단품화 이후 유전체층들이 다이의 엣지들로부터 리세싱 백(recessed back)되도록, 유전체층들, 예컨대 재분배층들의 폴리머층들은 스크라이브 라인을 따라 제거된다. 모서리 영역들은 더욱 리세싱될 수 있다. 리세싱된 영역들은 삼각형, 둥근형, 또는 이와 다른 형상일 수 있다. 몇몇의 실시예들에서, 하나 이상의 모서리 영역들은 남아있는 모서리 영역들에 비해 더욱 리세싱될 수 있다. 재분배층들은 전측면 재분배층들과 후측면 재분배층들 중 하나 또는 이 둘 모두를 따라 리세싱될 수 있다.

Small-form-factor wireless communication module and manufacturing method thereof

A small-form-factor wireless communication module includes two chips, a module substrate, and a supporting substrate. The module substrate includes a plurality of first solder pads arranged on the top and bottom surfaces, and a plurality of second solder pads arranged on the bottom surface. The two chips are respectively set on the first solder pads of the top and the bottom surfaces. The supporting substrate is set on the bottom surface of the module substrate and includes a chamber for containing the chip on the bottom surface of the module substrate. One of the two chips is utilized for communication circuits.

Two material high k thermal encapsulant system

Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

Device and method for an integrated ultra-high-density device

A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface.

Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

A groove is formed on a semiconductor substrate having integrated circuits and electrodes from a first surface. An insulating layer is formed on an inner surface of the groove. A conductive layer is formed on the insulating layer above the inner surface of the groove. A second surface of the semiconductor substrate opposite to the first surface is ground until the groove is exposed to divide the semiconductor substrate into a plurality of semiconductor chips in which the conductive layer is exposed on a side surface of each semiconductor chip. The semiconductor chips are then stacked. The conductive layer of one of the semiconductor chips is electrically connected to the conductive layer of another one of the semiconductor chips.

THIN PLANAR SEMICONDUCTOR DEVICE HAVING ELECTRODES ON BOTH SURFACES AND METHOD OF FABRICATING SAME

A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.

Semiconductor device and manufacturing method of the same

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

Components with posts and pads

A packaged microelectronic element includes connection component incorporating a dielectric layer ( 22 ) carrying traces ( 58 ) remote from an outer surface ( 26 ), posts ( 48 ) extending from the traces and projecting beyond the outer surface of the dielectric, and pads ( 30 ) exposed at the outer surface of the dielectric layer, the pads being connected to the posts by the traces. The dielectric element overlies the front surface of a microelectronic element, and contacts ( 74 ) exposed on the front surface of the microelectronic element are connected to the pads by elongated leads ( 76 ) such as wire bonds. Methods of making the connection component are also disclosed.

Microelectronic assemblies incorporating inductors

Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Modular integrated circuit chip carrier

An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

Stacked chip assembly

A semiconductor chip assembly, comprises a first semiconductor chip having a front surface, a rear surface and contacts on the front surface and a second semiconductor chip having a front surface, a rear surface and contacts on the front surface. The rear surface of the second semiconductor chip is juxtaposed with the front surface of the first semiconductor chip. The assembly includes a first backing element having electrically conductive first terminals. The first backing element is juxtaposed with the rear surface of the first semiconductor chip so that at least some of the terminals overlie the rear surface of the first semiconductor chip. At least some of the contacts on the first and the second semiconductor chips are electrically connected to at least some of the terminals. The assembly includes a substrate having contact pads thereon. The first terminals are connected to the contact pads of the substrate. The substrate is adapted to connect the assembly with other elements of a ...

Vertical surface mount package utilizing a back-to-back semiconductor device module

A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the device module. The device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. Solder reflow or a module-securing device can secure the device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate. Another module-securing device comprises a clip-on lead, where one end resiliently biases against a lead of at least one of the semiconductor devices, while the other end connects electrically to a carrier substrate terminal.

Stack package and method for manufacturing the same

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Semiconductor package having a redistribution line structure

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

Multi-chip stack package

A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and electrically connected to the first wiring substrate and the first chip has a first active surface. The second wiring substrate is disposed on the first active surface of the first chip and electrically connected to the first wiring substrate. The second chip is disposed on the second wiring substrate and electrically connected to the second wiring layer. The second active surface of the second chip faces the first active surface of the first chip.

METHOD AND MOLD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MOUNTING THE DEVICE

A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.

Semiconductor device carrier for fine pitch packaging miniaturization and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Microelectronic component and assembly having leads with offset portions

A microelectronic component comprising a dielectric layer having an opening and leads extending across the opening is disclosed. The leads have an offset portion. A method of making a microelectronic assembly comprises connecting each of the leads to a contact on a microelectronic element. A semiconductor chip assembly has a microelectronic component with an opening and leads extending across the opening. The leads are connected to contacts on a semiconductor chip and have at least one twisted portion.

Stacked microfeature devices and associated methods

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

Semiconductor device package and method of manufacturing the same

Various embodiments of the present disclosure relate to a semiconductor device package including a carrier, an electrical component, an antenna, a conductive pad and a conductive line. The carrier includes a top surface. The electrical component is disposed over the top surface of the carrier. The antenna is disposed over the top surface of the carrier and spaced away from the electrical component. The conductive pad is disposed over the top surface of the carrier and beneath the antenna, wherein the conductive pad includes a resonant structure. The conductive line is electrically connected to the electrical component and extends within the carrier. A part of the conductive line is beneath the antenna and the resonant structure of the conductive pad.

ELECTRONIC ASSEMBLY AND METHOD OF FORMING SAME

Various embodiments of an electronic assembly and a method of forming such assembly are disclosed. The electronic assembly includes a first integrated circuit package electrically connected to a second integrated circuit package. The first integrated circuit package includes a dielectric layer, a patterned conductive layer disposed within the dielectric layer, a device disposed on the first major surface of the dielectric layer and electrically connected to the patterned conductive layer, and an encapsulant layer disposed on the device and at least a portion of the first major surface of the dielectric layer. A conductive pillar of the second integrated circuit package is disposed within a trench of the first integrated circuit package such that the conductive pillar is electrically connected to a conductor disposed within the trench of the first integrated circuit package. The conductive pillar is electrically connected to a patterned conductive layer of the second integrated circuit package ...

Semiconductor device having wire studs as vertical interconnect in FO-WLP

A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

SEMICONDUCTOR PACKAGE STRUCTURE

A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.

MULTI-DIE MEMORY DEVICE

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor chip 2 is disposed within a device hole as formed in a tape base material 1a of a tape carrier 1, which chip is less in thickness than the tape base material 1a, while sealing by a seal resin 3 to permit both the principal surface and back surface of such semiconductor chip 2 to be coated therewith. And, let the position of the semiconductor chip 2 in a direction along the thickness of the tape base 1a be identical to a stress neutral plane of the TCP as a whole.

Porous alumina templates for electronic packages

Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

Semiconductor Package

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.

Packaged system of semiconductor chips having a semiconductor interposer

A semiconductor system ( 200 ) of one or more semiconductor interposers ( 201 ) with a certain dimension ( 210 ), conductive vias ( 212 ) extending from the first to the second surface, with terminals and attached non-reflow metal studs ( 215 ) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips ( 202, 203 ) have a dimension ( 220, 230 ) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs ( 224, 234 ). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate ( 204 ) has terminals and reflow bodies ( 242 ) to connect to the studs of the projecting interposer.

SEMICONDUCTOR CHIP ASSEMBLIES, METHODS OF MAKING SAME AND COMPONENTS FOR SAME

Semiconductor chip assemblies incorporating flexible, sheet-like elements (42) having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals (48) on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer (42) interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with test probe assembly so as to permit reliable engagement despite tolerances.

METHOD AND MOLD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MOUNTING THE DEVICE

A method for manufacturing semiconductor devices includes a resin sealing step of putting a substrate (16) on which bumps (12) and a plurality of semiconductor chips (11) are arranged in the cavity (28) of a mold (20) and supplying a resin (35) to the region where the bumps (12) are provided so as to coat the bumps (12) and form a resin layer (13), a protruded electrode exposing step of exposing at least the front end sections of the bumps (12) coated with the resin layer (13) from the layer (13), and a separating step of separating the semiconductor chips (11) into individual chips (11) by cutting the substrate (16) together with the layer (13).

ELECTRONIC COMPONENT FOR WIRING AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To simply and inexpensively manufacture an electronic device package by offline concentrating the process requiring a facility close to the previous process on components without requiring a penetration electrode technology. SOLUTION: A circuit element including a semiconductor chip is arranged and connected to its backside wiring pattern, and then mounted in the electronic device package connected to external electrodes positioned on the surface opposed to the wiring pattern via vertical wiring. The electronic component for wiring includes: a conductive supporting part of an electrocast matrix material; and a plurality of vertical wiring parts integrally coupled on the supporting part by the electrocast method. COPYRIGHT: (C)2010,JPO&INPIT ...

Electrical or electronic component e.g. integrated circuit, has metallic contact layer arranged on solid metallic socket and forming structure e.g. micro structure, including elevations and slots with height of specific value

The component (1) has a protective layer (4) arranged on a substrate (3) e.g. semiconductor wafer. A connector has a solid metallic socket (8) arranged on a contact surface (5), which is arranged on surface of the substrate. The layer covers an edge of the contact surface. The socket projects above a step, which is formed over the edge of the contact surface by the protective layer. A metallic contact layer is arranged on the socket and forms a structure (2) e.g. micro structure, including elevations and slots with height of 10 nanometer. The substrate is made of silicon or fiberglass resin. The substrate is formed of glass or ceramics. An independent claim is also included for a method for producing connection between electrical or electronic components.

Halbleiterbasisbauteil mit Verdrahtungssubstrat und Zwischenverdrahtungsplatte für einen Halbleiterbauteilstapel sowie Verfahren zu deren Herstellung

Die Erfindung betrifft ein Halbleiterbasisbauteil (1) mit Verdrahtungssubstrat (5) und Zwischenverdrahtungsplatte (6) für einen Halbleiterbauteilstapel. Zwischen der Zwischenverdrahtungsplatte (6) und dem Verdrahtungssubstrat (5) ist ein Halbleiterchip (7) angeordnet, der über das Verdrahtungssubstrat (5) einerseits mit Außenkontakten (24) auf der Unterseite (23) des Verdrahtungssubstrats (5) und andererseits mit Kontaktanschlussflächen (10) in den Randbereichen (8, 9) des Verdrahtungssubstrats (5) elektrisch verbunden ist. Die Zwischenverdrahtungsplatte (6) weist abgewinkelte Außenflachleiter (14; 15) auf, die in den Kontaktanschlussflächen (10) der Verdrahtungsplatte (5) elektrisch verbunden sind. Außerdem sind an der Oberseite (16) der Zwischenverdrahtungsplatte (6) Außenkontaktanschlussflächen (20) auf den freien Enden der Innenflachleiter (19) angeordnet, die in Größe und Anordnung Außenkontakten eines zu stapelnden Halbleiterbauteils entsprechen.

HALBLEITERVORRICHTUNG MIT AUSGESPARTEN RÄNDERN UND HERSTELLUNGSVERFAHREN

Eine Vorrichtung und ein Herstellungsverfahren werden bereitgestellt, die ausgesparte Regionen entlang eines Paketrandes verwenden. Bei einem integrierten Fan-Out-Paket werden beispielsweise die Dielektrikumschichten, wie z. B. die Polymerschichten, der Umverdrahtungsschichten entlang der Ritzlinie entfernt, sodass nach der Vereinzelung die Dielektrikumschichten von den Rändern der Chiplage weg ausgespart sind. Die Eckenregionen können weiter ausgespart werden. Die ausgesparten Regionen können dreieckig, gerundet oder von einer anderen Form sein. Bei einigen Ausführungsformen können eine oder mehrere von den Eckenregionen weiter relativ zu den verbleibenden Eckenregionen ausgespart werden. Die Umverdrahtungsschichten können entlang von einer oder von beiden der Vorderseitenumverdrahtungsschichten und der Rückseitenumverdrahtungsschichten ausgespart werden.

Die package with superposer substrate for passive components

A semiconductor die package 100 includes active circuitry 104 on a front side of a die 102, such as a system on chip (SoC) die or radio frequency (RF) die which includes a silicon substrate, and a separate component substrate 110 near a back side of the die to carry passive components 112 which may include high Q inductors, transformers, capacitors and resistors. The component substrate may be bump bonded to the back surface of the die. A conductive path, which may comprise a through silicon via (TSV) 116 connects passive components to the active circuitry on the die. A package substrate 106 may be positioned over the front side of the die and connected through a mold compound 108 to the die 102. A multi-die stack may include a second die on the opposite side of the component substrate to the first die (see Fig. 2; 222). The component substrate may extend laterally beyond the die allowing direct connection between the component substrate and package substrate by through mold vias (TMVs) ...

Testing semiconductor elements

SEMICONDUCTOR CHIP ARRANGEMENTS, MANUFACTURING METHODS AND COMPONENTS FOR THE SAME

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ARRANGEMENT AND PROCEDURE FOR YOUR PRODUCTION

SEMICONDUCTOR CHIP ASSEMBLIES, METHODS OF MAKING SAME AND COMPONENTS FOR SAME

SIGNAL DELIVERY IN STACKED DEVICE

... 일부 실시예들은 베이스, 제 1 다이, 제 1 다이 및 베이스와 함께 스택으로 배열된 제 2 다이, 및 스택으로 및 제 1 및 제 2 다이들 중 적어도 하나의 외부에 배치되고, 제 1 및 제 2 다이들 중 적어도 하나와 베이스 사이에서 신호들을 전송하도록 구성되는 구조를 구비한 장치, 시스템들 및 방법들을 포함한다.

3차원 수직 배선을 이용한 ＲＦ 적층 모듈 및 이의 배치 방법

... 3차원 수직 배선을 이용한 RF 적층 모듈의 구조 및 배치방법을 제공한다. , 3차원 수직 배선을 이용한 RF 적층 모듈에서 제1 웨이퍼는 적어도 하나의 제1 관통홀 및 제1 RF 소자를 포함한다. 제2 웨이퍼는 제2 RF 소자 및 상기 제1 관통홀과 대응되는 위치에 구비된 적어도 하나의 제2 관통홀을 포함한다. 수직 배선은 상기 제1 관통홀과 상기 제2 관통홀을 연결한다. 관통전극은 상기 제1 관통홀의 하면 또는 상기 제2 관통홀의 상면으로 외부 소자와 연결된다.

팬아웃 웨이퍼 레벨 패키지의 3D 집적화

... 팬아웃 웨이퍼 레벨 패키지(FOWLP) 및 형성 방법이 기술된다. 실시예에서, 패키지는 제1 라우팅 층, 제1 라우팅 층의 상부면 상의 제1 다이, 및 제1 라우팅 층 상에서 제1 다이를 캡슐화하는 제1 몰딩 화합물을 포함한다. 제1 복수의 전도성 필라가 제1 라우팅 층의 하부면으로부터 연장된다. 제2 다이가 제2 라우팅 층의 상부면 상에 있고, 제1 복수의 전도성 필라는 라우팅 층의 상부면 상에 있다. 제2 몰딩 화합물은 제2 라우팅 층 상에서 제1 몰딩 화합물, 제1 라우팅 층, 제1 복수의 전도성 필라, 및 제2 다이를 캡슐화한다. 일 실시예에서, 복수의 전도성 범프(예를 들어, 솔더 볼)가 제2 라우팅 층의 하부면으로부터 연장된다.

PACKAGED SEMICONDUCTOR DIE USING PREDETERMINED TESTS FOR IMPROVING CORRESPONDING CAPABILITY TO MULTI-CHIP PACKAGE AND ENHANCING DESIGN FLEXIBILITY AND MANUFACTURING METHOD THEREOF

PURPOSE: A packaged semiconductor die and its manufacturing method are provided to enhance a corresponding capability to a multi-chip package and to improve design flexibility by using a known good package performed with predetermined tests. CONSTITUTION: A die substrate(220) with an insulating base member(221) and metal line patterns(223,224) on the insulating base member is provided. A known good package that undergoes predetermined tests is mounted on the die substrate. At this time, the known good package is electrically connected with the metal line patterns of the die substrate. The resultant structure is selectively encapsulated by using a molding member(240). © KIPO 2006 ...

Semiconductor device with separated passivated passivation material and related systems and methods

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND PORTABLE INFORMATION TERMINAL

A low cost semiconductor device, a method of manufacturing an electronic device, electronic devices, and a portable information terminal; the semiconductor device, comprising projected electrodes located on one surface of a circuit board and having a specified height, semiconductor chips smaller than the height of the projected electrodes, and electronic parts larger than the thickness of the semiconductor chips located on the other surface of the circuit board so that the one surface side is bent in the direction thereof, whereby the rigidly of the device and a clearance between the semiconductor chips and a mounting substrate are assured; electronic devices and a portable information terminal, wherein the semiconductor device having a logic LSI installed on both surfaces of the circuit board is installed on a mounting substrate disposed in a cabinet through the projected electrodes having a specified height and formed so that the projected electrode side of the circuit board is bent in ...

Stack-type semiconductor package, method of forming the same and electronic system including the same

A method of forming a stack-type semiconductor package includes preparing a lower printed circuit board including a plurality of interconnections and a plurality of ball lands for connection on an upper surface thereof. One or more first chips, which are electrically connected to the plurality of interconnections and sequentially stacked, are mounted on the lower printed circuit board. A lower molded resin compound is formed on the lower printed circuit board to cover the first chips, and is formed to have via holes exposing the ball lands for connection. An upper chip package, under which solder balls are formed, is aligned so that the solder balls correspond to the via holes of the lower molded resin compound, respectively. The solder balls are reflown to form connection conductors filling the via holes. A stack-type semiconductor package structure and an electronic system including the same are also provided.

Stack package and methods of manufacturing the same

A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer.

Semiconductor devices method of connecting semiconductor devices and semiconductor device connectors

Semiconductor devices suited for high-density packaging, a method of connecting such semiconductor devices, and connectors for connecting such semiconductor devices. Each semiconductor device 10 includes a plurality of exposed terminals 13 arranged two-dimensionally on opposite surfaces thereof. Each connector 30 includes a plurality of connecting pins projecting from opposite surfaces thereof and arranged two-dimensionally in a corresponding relationship to the exposed terminals 13. Each end connector 33 includes connecting pins 34 likewise arranged two-dimensionally on an inward surface thereof. These connectors 30 and 33 are used to sandwich a plurality of semiconductor devices 10 to form a package. The exposed terminals 13 of the semiconductor devices 10 are electrically connected through the connecting pins of the connectors 30 and 33.

STACKED DIE PACKAGE

Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack.

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Wafer level stackable semiconductor package

A stackable semiconductor package includes a semiconductor die, and has a chip sized peripheral outline matching that of the die. In addition to the die, the package includes stacking pads and stacking contacts on opposing sides of the die, and conductive grooves on the edges of the die in electrical communication with the stacking pads and the stacking contacts. The conductive grooves function as interlevel conductors for the package and can also function as edge contacts for the package. The configuration of the stacking pads, of the stacking contacts and of the conductive grooves permit multiple packages to be stacked and electrically interconnected to form stacked assemblies. A method for fabricating the package is if performed at the wafer level on a substrate, such as a semiconductor wafer, containing multiple dice. In addition, multiple substrates can be stacked, bonded and singulated to form stacked assemblies that include multiple stacked packages.

Apparatus and method for stacking integrated circuit devices

An apparatus and method for stacking integrated circuit devices which combine flip-chip technology and soldering methods with laminated stack frames to provide a vertical stack array with minimal parasitic inductance. Each laminated stack frame has a central cavity and includes a plurality of vias extending through them. The vias have top surfaces and bottom surfaces, wherein the bottom surfaces each contain a solder bump. Each laminated stack frame also includes a plurality of solder bump pads extending into the cavity to contact corresponding solder bumps on a flip-chip integrated circuit chip, and a plurality of traces coupling each solder bump pad to a via. The bottom surfaces of the vias of a bottom laminated stack frame couple to contacts on a printed circuit board.

Stackable ball grid array package

A stackable fine ball grid array (FBGA) package is disclosed that allows the stacking of one array upon another. This stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements. Additionally, certain pins on the FBGA in the stack require an isolated connection to the PC board. Yet, ...

Integrated circuit device system with elevated configuration and method of manufacture thereof

A system and method of manufacture of an integrated circuit device system includes mounting a first elevated device on a first riser positioned adjacent to a base device. The first elevated device includes a first device overhang that extends over the base device. A second elevated device can be mounted on a second riser adjacent to the first riser to allow the attachment of a second elevated device mounted above the first elevated device to achieve higher component densities.

Stacked microelectronic assembly and method therefor

A method of making a stacked microelectronic assembly includes providing a flexible substrate having a plurality of attachment sites, test contacts and conductive terminals, and including a wiring layer with leads extending to the attachment sites. The method includes assembling a plurality of microelectronic elements to the attachment sites and electrically interconnecting the microelectronic elements and the leads. The flexible substrate is then folded so as to stack at least some of the microelectronic elements in substantially vertical alignment with one another to provide a stacked assembly with the conductive terminals exposed at the bottom end of the stack and the test contacts exposed at the top end of the stack.

Semiconductor die packages with recessed interconnecting structures

Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multidie assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface are employed to connect stacked assemblies.

Chip on package structure and method

A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Assembly jig and manufacturing method of multilayer semiconductor device

There are provided a base member 14, a position restriction mechanism 15, a height restriction mechanism 17, an evenness holding mechanism, and an alignment mechanism 20, 22. A plurality of semiconductor modules is serially layered on the base member. Each semiconductor module comprises a semiconductor chip 7 mounted on a printed-wiring board 6 and a bump 13 formed on an interlayer connection land 8. The position restriction mechanism 15 restricts respective positions of the semiconductor modules 2 to be layered on the base member 14. The height restriction mechanism 17 restricts the height of the entire layered semiconductor module unit 4 layered on the base member 14. The evenness holding mechanism maintains evenness of the semiconductor module 2. The alignment mechanism 20, 22 aligns a mother substrate 5 on which a multilayer semiconductor module unit 4 is mounted.

Recessed and embedded die coreless package

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

Anisotropic elastomeric interconnecting system

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Redistribution layers for microfeature workpieces, and associated systems and methods

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

Stack package and method for manufacturing the same

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Semiconductor device and semiconductor package including the same

Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

Process for assembling two parts of a circuit

A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Off-chip vias in stacked chips

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Power/ground layout for chips

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Semiconductor module

A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

Three-Dimensional Semiconductor Device

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

Dram device with built-in self-test circuitry

A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Multi-stack semiconductor integrated circuit device

The invention relates to a multi-stack semiconductor integrated circuit device where communication between semiconductor chips can be efficiently carried out by bypassing a number of chips. Each semiconductor chip that forms a multi-stack semiconductor integrated circuit device having a stack structure where four or more semiconductor chips having the same shape are stacked on top of each other is provided with: a first coil for transmission/reception for communication between chips over a long distance; and a second coil for transmission/reception for communication between chips over a short distance, of which the size is smaller than that of the above-described first coil for transmission/reception.

Three-dimensional system-in-a-package

A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Semiconductor packages and methods of forming the same

A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Stackable integrated circuit package system

A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Packaging identical chips in a stacked structure

Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.

Method and A System for Producing a Semi-Conductor Module

In a method for producing a semi-conductor module ( 10 ) comprising at least two semi-conductor chips ( 12, 14 ) and an interposer ( 20 ) which has electrically conductive structures ( 28 ) connecting the semi-conductor chips ( 12, 14 ) to one another, the interposer ( 20 ) is printed directly onto a first ( 12 ) of the semi-conductor chips. When the interposer ( 20 ) is printed on, the electrically conductive structures ( 28 ) are produced by means of electrically conductive ink ( 68 ). The second semi-conductor chip ( 14 ) is mounted on the interposer ( 20 ) such that the two semi-conductor chips ( 12, 14 ) are arranged one above the other and that the interposer ( 20 ) forms an intermediate layer between the two semi-conductor chips ( 12, 14 ).

Systems and methods for lowering interconnect capacitance

Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to pass a signal through at least a portion of the at least one integrated circuit. The apparatus may include a transmitter to operate at a first voltage and a second voltage, and to output to an end node of the interconnect a reduced swing signal ranging from the first voltage to a third voltage. The third voltage may be between the first and second voltages, and the reduced swing signal may operate to reduce a capacitance of the interconnect when compared to operating the transmitter at the second voltage. Additional apparatus and methods are disclosed.

Multi-chip semiconductor package and method of fabricating the same

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

Silicon based microchannel cooling and electrical package

A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip stack; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chip stacks. The chip package further includes a cooling lid disposed above the chip stack providing additional cooling.

Semiconductor device and fabrication method therefore

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

Semiconductor device

A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias.

Processes and structures for IC fabrication

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Integrated Circuit Die Stacks With Rotationally Symmetric VIAS

An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.

Power recovery circuit based on partial standing waves

A power recovery system includes a transmission line that is coupled to transfer an RF signal received via an antenna. The RF signal generates a partial standing wave in the transmission line and the transmission line has at least one standing wave anti-node. A power recovery circuit converts an anti-node signal from the at least one standing wave anti-node to a power signal.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Semiconductor chip module and semiconductor package having the same

A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure

A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

Methods and Apparatus for Package on Package Structures

A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.

Side Stack Interconnection for Integrated Circuits and The Like

In an illustrative embodiment, a plurality of integrated circuits are stacked one on top of the other in a block. A plurality of leads on each integrated circuit is made accessible on a first side of the block. An insulating layer is formed on the first side of the block; electrically conducting vias are formed in the insulating layer and coupled to the leads; a conducting layer is formed on the insulating layer and coupled to the conducting vias; and conducting paths are formed in the conducting layer. Additional layers of insulating layer, conducting vias and conducting layer may be formed on top of the first insulating layer and first conducting layer so as to form more complicated interconnection paths to the leads from the integrated circuits.

Reconfiguring through silicon vias in stacked multi-die packages

Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Stacked Semiconductor Device Assembly in Computer System

This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device. 1. A stacked semiconductor device assembly , comprising: a master interface;', 'a channel master circuit coupled to the master interface;', 'a slave interface;', 'a channel slave circuit coupled to the slave interface;', 'a memory core coupled to the channel slave circuit; and', 'selection circuitry configured to determine whether the IC chip is to communicate data using the channel master circuit or the channel slave circuit., 'a plurality of stacked integrated circuit (IC) chips, each IC chip further comprising2. The stacked semiconductor device assembly of claim 1 , wherein for one of the plurality of stacked IC chips claim 1 , the selection circuitry receives an input claim 1 , and is configured to determine whether the one of the plurality of stacked IC chips is to communicate data using the channel master or slave circuit based on a voltage level of the input.3. The stacked semiconductor device assembly of claim 2 , wherein the one of the plurality of IC chips is physically offset from other IC chips in the stacked semiconductor device assembly.4. The stacked semiconductor device assembly of claim ...

SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides. 125.-. (canceled)26. An integrated circuit (“IC”) package substrate , comprising a bottom surface comprising an array of contacts , the array of contacts comprising a plurality of data I/O contacts , wherein:a first subset of the plurality of data I/O contacts forms a first C-shaped layout arranged on a first portion of the bottom surface;a second subset of the plurality of data I/O contacts forms a second C-shaped layout arranged on a second portion of the bottom surface; andthe first portion and the second portion are reflectively symmetrical about a central axis.27. The IC package substrate of claim 26 , the array of contacts further comprising a plurality of ground (“GND”) contacts claim 26 , wherein at least one GND contact of the plurality of GND contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.28. The IC package substrate of claim 26 , the array of contacts further comprising a plurality of data queue stroke (“DQS”) contacts claim 26 , wherein at least one DQS contact of the plurality of DQS contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.29. The IC package substrate of claim 26 , wherein the first subset of the plurality of data I/O contacts comprises a first communications channel claim 26 , and the second subset of the plurality of data I/O contacts comprises a second communications channel.30. The IC package of claim 29 , the array of contacts further comprising a plurality of chip enable (“CE”) contacts claim ...

3DIC Stacking Device and Method of Manufacture

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position. 1. A semiconductor device comprising:a first semiconductor die encapsulated by a first encapsulant;at least one through substrate via extending through at least a portion of the first semiconductor die and being exposed on a first side of the first semiconductor die;first external connectors located on a second side of the first semiconductor die;a first redistribution layer in electrical connection with the first external connectors, the first redistribution layer extending over the first encapsulant; anda second semiconductor die in electrical connection with the at least one through substrate via, the second semiconductor die extending over the first encapsulant.2. The semiconductor device of claim 1 , further comprising;a third semiconductor die encapsulated by the first encapsulant; anda fourth semiconductor die in electrical connection with the third semiconductor die, the fourth semiconductor die extending over the first encapsulant.3. The semiconductor device of claim 2 , wherein the second semiconductor die and the fourth semiconductor die are encapsulated by a second encapsulant.4. The semiconductor device of claim 1 , further comprising a second redistribution layer in electrical connection with the at least one through substrate via claim 1 , the second redistribution layer extending over the first encapsulant.5. The semiconductor device of claim 1 , wherein the second semiconductor die is offset from the first semiconductor die.6. The semiconductor device of claim 5 , wherein the offset is between about 100 um and about 3 mm.7. ...

3D PACKAGE STRUCTURE AND METHODS OF FORMING SAME

An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias. 1. A method comprising:forming a first die package over a carrier substrate, the first die package comprising a first die;forming a first redistribution layer over and coupled to the first die, the first redistribution layer comprising one or more metal layers disposed in one or more dielectric layers;adhering a second die over the first redistribution layer;laminating a first dielectric material over the second die and the first redistribution layer;forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer; andforming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.2. The method of further comprising:forming a first set of conductive connectors over and coupled to the second redistribution layer.3. The method of further comprising:removing the carrier substrate; andcoupling a substrate to the first set of conductive connectors.4. The method of claim 1 , wherein the forming the first die package further comprises:encapsulating at least lateral edges of the first die with an encapsulant; andlaminating a second dielectric ...

Stacked Integrated Circuits with Redistribution Lines

An integrated circuit structure includes a first and a second semiconductor chip. The first semiconductor chip includes a first substrate and a first plurality of dielectric layers underlying the first substrate. The second semiconductor chip includes a second substrate and a second plurality of dielectric layers over the second substrate, wherein the first and the second plurality of dielectric layers are bonded to each other. A metal pad is in the second plurality of dielectric layers. A redistribution line is over the first substrate. A conductive plug is electrically coupled to the redistribution line. The conductive plug includes a first portion extending from a top surface of the first substrate to a bottom surface of the first substrate, and a second portion extending from the bottom surface of the first substrate to the metal pad. A bottom surface of the second portion contacts a top surface of the metal pad. 1. A method comprising:bonding a first wafer to a second wafer, wherein a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer are bonded between a firs substrate of the first wafer and a second substrate in the second wafer;forming a first opening in the first substrate;etching the first plurality of dielectric layers and the second wafer through the first opening to form a second opening, wherein a first metal pad in the second plurality of dielectric layers is exposed to the second opening;filling a conductive material to form a first conductive plug extending into the first opening and the second opening;forming a first dielectric layer over the first substrate; andforming a redistribution line comprising a portion over the dielectric layer, wherein the redistribution line is electrically coupled to the first conductive plug through a portion in the dielectric layer.2. The method of further comprising claim 1 , after the first opening is formed claim 1 , depositing a second ...

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die. 1. A memory device , comprising:a first semiconductor die; and second semiconductor dies laterally wrapped by an encapsulant; and', 'a redistribution structure disposed on the second semiconductor dies and the encapsulant, wherein the second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers, each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region. 1. A semiconductor package , comprising:a first package including a first package substrate on which a lower semiconductor chip is mounted; anda second package stacked on the first package, the second package including a second package substrate on which upper semiconductor chips are mounted, a chip region overlapped with the lower semiconductor chip to provide a region on which the upper semiconductor chips are mounted; and', 'a connection region provided around the chip region,, 'wherein the second package substrate compriseswherein the chip region comprises a first surface that faces the lower semiconductor chip and forms a first recess region and a second surface that is opposite to the first surface and forms a first protruding portion, andwherein the upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.2. The semiconductor package of claim 1 , wherein the lower semiconductor chip is provided in such a way that an upper or entire portion thereof is inserted into the first recess region.3. The semiconductor package of claim 1 , further comprising bonding wires connecting ...

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate. 1. A packaged microelectronic device , comprising:an interposer substrate having a first side with a plurality of interposer contacts and a second side opposite the first side, the second side including a plurality of interposer pads arranged in an array corresponding to a standard JEDEC pinout;a microelectronic die attached and electrically coupled to the interposer substrate;a casing covering the die and at least a portion of the interposer substrate, wherein the casing has a thickness and a top facing away from the interposer substrate; anda plurality of electrically conductive through-casing interconnects in contact with and projecting from corresponding interposer contacts, wherein the through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing, and wherein the through-casing interconnects are at least partially encapsulated in the casing,wherein the through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to ...

Package-on-package semiconductor device assemblies including one or more windows and related methods and packages

Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. Semiconductor devices may be supported on the upper surface of the substrate around a periphery of the array of electrically conductive elements. The semiconductor devices may be electrically connected to at least some of the electrically conductive elements of the array by routing elements extending from the semiconductor devices toward the window.

Methods of Forming Multi-Die Package Structures Including Redistribution Layers

A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate. 1. A semiconductor device , comprising:a first die disposed on a first surface of a redistribution structure;a second die disposed on the first surface of the redistribution structure;a molding material extending between the first die and the second die;a heat dissipation lid connected to the first surface of the redistribution structure, the first die and the second die being disposed in an inner cavity of the heat dissipation lid;a package connected to a second surface of the redistribution structure, the second surface of the redistribution structure being opposite to the first surface of the redistribution structure, the package comprising a plurality of package dies, and the package underlying each of the first die and the second die in part; anda plurality of first connectors connected to the second surface of the redistribution structure.2. The semiconductor device according to claim 1 , wherein a first connector of the plurality of first connectors has a first surface that is farthest from the redistribution structure claim 1 , the package has a first surface that is farthest from the redistribution structure ...

SEMICONDUCTOR STRUCTURE AND A MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess extending from the first surface towards the second surface, a first die at least partially disposed within the recess and including a first die substrate and a first bonding member disposed over the first die substrate, a second die disposed over the first die and including a second die substrate and a second bonding member disposed a second die substrate and the second die substrate, a redistribution layer (RDL) disposed over the second die, and a conductive bump disposed over the RDL, wherein the first bonding member is disposed opposite to and is bonded with the second bonding member. 2. The semiconductor structure of claim 1 , wherein the first die is bonded with a sidewall of the recess.3. The semiconductor structure of claim 1 , wherein a thickness of the first die is substantially greater than a depth of the recess.4. The semiconductor structure of claim 1 , wherein a portion of the first die is protruded from the recess.5. The semiconductor structure of claim 1 , wherein the first die is at least partially surrounded by the substrate.6. The semiconductor structure of claim 1 , wherein a distance between a sidewall of the first die and a sidewall of the recess is about 5 um to about 30 um.7. The semiconductor structure of claim 1 , wherein a depth of the recess is about 20 um to about 60 um.8. The semiconductor structure of claim 1 , wherein a thickness of the first die is about 30 um to about 70 um.9. The semiconductor structure of claim 1 , further comprising a dielectric material disposed within the recess and surrounding the first die or the second die.10. The semiconductor structure of claim 9 , wherein the dielectric material is disposed between the substrate and the RDL.11. The semiconductor structure of claim 9 , further comprising a via extending from the first bonding member towards the RDL and passing through a ...

SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed. 111-. (canceled)12. A method for fabricating an integrated circuit (IC) assembly , comprising:providing a package substrate having a first side and a second side disposed opposite to the first side;coupling an active side of a first die with the first side of the package substrate, the first die including an inactive side disposed opposite to the active side and one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; andforming a mold compound on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side;mounting ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package. The semiconductor package includes a first substrate, a first die, a plurality of first electrical contacts, a first encapsulant, a second substrate, a second die, a third die, a plurality of second electrical contacts, a second encapsulant and an adhesive layer. The first die is disposed on a first surface of the first substrate. The first electrical contacts are disposed on a second surface of the first substrate and are electrically connected to the first die. The first encapsulant is formed on the first surface of the first substrate to enclose the first die. The second and third dies are disposed on a first surface of the second substrate. The second electrical contacts are disposed on a second surface of the second substrate and are electrically connected to the second and third dies. The second encapsulant is formed on the first surface of the second substrate to enclose the second and third dies. The adhesive layer is disposed between the first and second encapsulants to attach the first encapsulant to the second encapsulant. The present disclosure further provides a method of manufacturing the above semiconductor package. 1. A semiconductor package , comprising:a first substrate having opposing first surface and second surface;a first die disposed on the first surface of the first substrate;a plurality of first electrical contacts disposed on the second surface of the first substrate and electrically connected to the first die, the first electrical contacts being configured to be electrically connected to a first external circuit;a first encapsulant formed on the first surface of the first substrate to enclose the first die, the first encapsulant having a bottom surface;a second substrate having opposing first surface and second surface;a second die and a third die both disposed on the first surface of the second substrate;a plurality of second electrical contacts disposed on the second surface of the ...

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Rotatable Architecture for Multi-Chip Package (MCP)

A multi-chip packaged device may include a first integrated circuit die with a first integrated circuit, such that the first integrated circuit may include a first plurality of ports disposed on a first side and a second plurality of ports disposed on a second side of the first integrated circuit die. The multi-chip packaged device may also include a second integrated circuit die, such that the second integrated circuit may include a third plurality of ports disposed on a third side of the second integrated circuit die. The first integrated circuit may communicate with the first side of the second integrated circuit when placed adjacent to the first side and communicate with the second side of the first integrated circuit die when placed adjacent to the second side. 1. A multi-chip packaged device , comprising: a first plurality of ports disposed on a first side of the first integrated circuit die; and', 'a second plurality of ports disposed on a second side of the first integrated circuit die; and, 'a first integrated circuit die comprisinga second integrated circuit die comprising a third plurality of ports disposed on a first side of the second integrated circuit die, wherein the second integrated circuit die is configured to communicate with the first integrated circuit via the third plurality of ports and the first plurality of ports when the first side of the first integrated circuit die is placed adjacent to the first side of the second integrated circuit die, and wherein the second integrated circuit die is configured to communicate with the first integrated circuit die via the third plurality of ports and the second plurality of ports when the second side of the first integrated circuit die is placed adjacent to the first side of the second integrated circuit die.2. The multi-chip packaged device of claim 1 , wherein the third plurality of ports is configured to enable the second integrated circuit die to communicate with either the first plurality of ports ...

Underfill Structure for Semiconductor Packages and Methods of Forming the Same

A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE. 1. A device comprising: an integrated circuit die;', 'an interposer bonded to the integrated circuit die by a plurality of die connectors; and', 'an encapsulant surrounding the integrated circuit die;, 'a package comprisinga package substrate bonded to the interposer by a plurality of conductive connectors;a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); anda second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.2. The device of claim 1 , wherein the first underfill tapers from the package toward the package substrate.3. The device of claim 2 , wherein the second underfill tapers from the package substrate toward the package.4. The device of claim 1 , wherein the first underfill and the second underfill taper from the package substrate toward the package.5. The device of claim 1 , wherein the first underfill is in contact with the interposer and spaced apart from the encapsulant.6. The device of claim 1 , wherein the second underfill is in contact with the package and spaced apart from the conductive connectors.7. The device of claim 1 , wherein the first underfill has a ...

Multi-Chip Structure and Method of Forming Same

A device includes a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction, a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction and a plurality of bumps between the first chip and the second chip. 1. A device comprising:a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction;a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction; anda plurality of bumps between the first chip and the second chip.2. The device of claim 1 , further comprising:a redistribution layer over the molding compound layer;a dielectric layer over the redistribution layer;an under bump metallization structure over the dielectric layer; anda solder ball over the under bump metallization structure.3. The device of claim 2 , wherein:the first chip comprises a plurality of logic circuits, wherein the first chip comprise a plurality of through vias connected to the redistribution layer; andthe second chip comprises a plurality of memory dies stacked together, wherein the second chip is electrically connected to the first chip through the plurality of bumps.4. The device of claim 2 , wherein:the redistribution layer extends beyond at least one outmost edge of the first chip.5. The device of claim 2 , wherein:the second chip and the redistribution layer are separated by the molding compound layer.6. The device of claim 1 , wherein:a top surface of the second chip is exposed outside the molding compound layer.7. The device of claim 1 , wherein:a first sidewall of the first chip is exposed outside the molding compound layer;a second sidewall of the first chip is covered by the molding compound layer and underneath the second chip;a first sidewall of the second ...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors. 1. A 3D semiconductor device , the device comprising: 'wherein said first metal layer comprises interconnecting said first transistors forming, at least in part a plurality of logic gates;', 'a first single crystal layer comprising a plurality of first transistors and a first metal layer,'}a plurality of second transistors overlaying, at least in part said first single crystal layer;a plurality of third transistors overlaying, at least in part said second transistors;a plurality of fourth transistors overlaying, at least in part said third transistors;a second metal layer overlaying, at least in part said fourth transistors;a plurality of vias, said plurality of vias providing connections from said second transistors to said second metal layer;a first power distribution grid structured to provide power to at least a portion of said first transistors; and wherein said fourth transistors are aligned with less than 100 nm misalignment to said first transistors,', 'wherein said first power distribution grid is isolated from said second power distribution grid,', 'wherein at least one of said plurality of vias has a radius ...

Stress Reduction Apparatus and Method

A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region. 1. A method comprising:depositing a polymer layer over a substrate of a first semiconductor die;forming an under bump metallization structure over the polymer layer;forming a connector over the under bump metallization structure; andforming a first dummy conductive plane over the polymer layer, wherein a topmost surface of the first dummy conductive plane is below a topmost surface of the connector, and wherein a long edge of the first dummy conductive plane is collinear with an edge of the first semiconductor die in a plan view.2. The method of claim 1 , further comprising forming a second dummy conductive plane over the polymer layer and in physical contact with the first dummy conductive plane claim 1 , wherein the first dummy conductive plane and the second dummy conductive plane form an L-shaped dummy region at a corner of the first semiconductor die.3. The method of claim 2 , further comprising forming a third dummy conductive plane between the first dummy conductive plane and the connector.4. The method of claim 1 , further comprising bonding a second semiconductor die to the first semiconductor die through a reflow process claim 1 , wherein the second semiconductor die is electrically coupled to the first semiconductor die through the connector.5. The method of claim 4 , further comprising forming an underfill layer between the first semiconductor die and the second semiconductor die claim 4 , wherein a topmost ...

SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME

A semiconductor package including at least one integrated circuit component, a glue material, an insulating encapsulation, and a redistribution circuit structure is provided. The glue material encapsulates the at least one integrated circuit component and has a first surface and a second surface opposite to the first surface, wherein the at least one integrated circuit component is exposed by the first surface of the glue material, and an area of the first surface is smaller than an area of the second surface. The insulating encapsulation encapsulates the glue material, wherein an interface is between the glue material and the insulating encapsulation. The redistribution circuit structure is disposed on the at last one integrated circuit component, the glue material and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the at least one integrated circuit component. 1. A semiconductor package , comprising:at least one integrated circuit component having an active surface;a glue material, encapsulating the at least one integrated circuit component and having a first surface and a second surface opposite to the first surface, wherein the at least one integrated circuit component is exposed by the first surface of the glue material, and an area of the first surface is smaller than an area of the second surface;an insulating encapsulation, encapsulating the glue material, wherein an interface is between the glue material and the insulating encapsulation; anda redistribution circuit structure disposed on the at least one integrated circuit component, the glue material and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the at least one integrated circuit component,wherein the active surface of the at least one integrated circuit component faces toward the first surface of the glue material.2. The semiconductor package as claimed in claim 1 , wherein an included ...

Semiconductor package and method for manufacturing a semiconductor package

A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. 1. A package comprising: a first device die;', 'a first molding compound extending along sidewalls of the first device die; and', 'a first through intervia (TIV) extending through the first molding compound;, 'a first fan-out tier comprisingone or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;one or more second fan-out RDLs on an opposing side of the first fan-out tier from the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; anda plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan ...

ELECTRONICS PACKAGE DEVICES WITH THROUGH-SUBSTRATE-VIAS HAVING PITCHES INDEPENDENT OF SUBSTRATE THICKNESS

An electronics package device having a through-substrate-via comprises a substrate having a cavity and at least one electronic component (e.g., stack of dies) supported in the cavity. The electronics package device comprises a through-substrate-via disposed through the substrate and that has a pitch-to-height ratio of less than 1.5 and a pitch value that is independent of a thickness value of the substrate. Thus, the pitch of the through-substrate-via is uniform or consistent along the length of the through-substrate-via regardless of the height of the substrate. A supplemental electronics package device can be stacked on the first package device and electrically coupled to an assembly circuit board by the through-substrate-vias. A method is provided of making the electronics package device that minimizes space required for vertical interconnects for PoP devices having the electronic package device. A method is provided that maximizing an amount of input/output contacts between an assembly circuit board and the electronics package device. 1. An electronics package device , comprising:a substrate having a first height region and a second height region, the first height region having a thickness value greater than a thickness value of the second height region;a cavity defined by the first and second height regions;a plurality of electronic components stacked in the cavity; anda plurality of through-substrate vias disposed through the first height region and having upper contact pads for electrically coupling a supplemental package device to an assembly circuit board supporting the substrate, each through-substrate-via having a pitch-to-height ratio of less than 1.5, wherein a pitch value of each through-substrate-via is independent of the thickness value of the first height region of the substrate.2. The electronics package device of claim 1 , wherein the pitch value is less than 0.4 mm.3. The electronics package device of claim 1 , wherein the thickness value of the ...

THREE-DIMENSIONAL INTEGRATED FAN-OUT WAFER LEVEL PACKAGE

An integrated fan-out wafer level package houses a semiconductor package having a first semiconductor die encapsulated by a dielectric compound. A plurality of redistribution layers are formed on a first side of the semiconductor package which are in electrical contact with contact pads of the first semiconductor die. A plurality of solder balls located on the first side of the semiconductor package is electrically connected to the contact pads of the semiconductor die via the redistribution layers. A second semiconductor die is further attached to the first side of the semiconductor package and is electrically connected to the contact pads of the first semiconductor die via the redistribution layers. 1. An integrated fan-out wafer level package comprising:a semiconductor package comprising a first semiconductor die encapsulated by a dielectric compound;a plurality of redistribution layers formed on a first side of the semiconductor package in electrical contact with contact pads of the first semiconductor die;a plurality of solder balls located on the first side of the semiconductor package and electrically connected to the contact pads of the semiconductor die via the redistribution layers; anda second semiconductor die attached to the first side of the semiconductor package and electrically connected to the contact pads of the first semiconductor die via the redistribution layers; anda plurality of wire bond pads formed on the redistribution layers on the first side of the semiconductor package and wire bonds directly connecting the second semiconductor die to the wire bond pads.2. The integrated fan-out wafer level package as claimed in claim 1 , wherein the plurality of solder balls is arranged for electrically mounting the integrated fan-out wafer level package onto a printed circuit board.3. The integrated fan-out wafer level package as claimed in claim 1 , wherein the first semiconductor die comprises an application processor chip.4. The integrated fan-out ...

SEMICONDUCTOR PACKAGES

A semiconductor package may include a first substrate, a second substrate facing the first substrate, a plurality of first electrical connections disposed between the first substrate and the second substrate, and a first material disposed between the first substrate and the second substrate. The plurality of first electrical connections may electrically couple the first substrate and the second substrate to each other. The first material may surround each of the plurality of first electrical connections, and a width of the first material proximal the first substrate may be smaller than a width of the first material proximal the second substrate. 1. A semiconductor package comprising: a first encapsulant formed over the first side of the first substrate; and', 'a first plurality of electrical features formed at the second side of the first substrate;, 'a first substrate having a first side and a second side opposite the first side, the first substrate comprisinga second substrate having a first side and a second side opposite the first side, the second substrate comprising a second plurality of electrical features formed on the first side of the second substrate;a plurality of first electrical connections coupled between the first plurality of electrical features and the second plurality of electrical features;a second encapsulant disposed over the first side of the second substrate, the second encapsulant positioned between each of the plurality of first electrical connections; anda first material disposed over the second encapsulant, the first material positioned between each of the plurality of first electrical connections, wherein the first material is separated from the second side of the first substrate.2. The semiconductor package of claim 1 , further comprising:a third encapsulant disposed between the second encapsulant and the second side of the first substrate.3. The semiconductor package of claim 2 , wherein the third encapsulant comprises a molding ...

Semiconductor devices and methods for manufacturing the same

A semiconductor device includes an interposer substrate and at least one die mounted on the interposer substrate. The interposer substrate includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, an interlayer insulating layer on the first surface of the semiconductor substrate, a capacitor in a hole penetrating the interlayer insulating layer, an interconnection layer on the interlayer insulating layer, and a through-via extending from the interconnection layer toward the second surface of the semiconductor substrate in a vertical direction that is perpendicular to the first surface of the semiconductor substrate. The capacitor includes a sequential stack of a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode. A bottom of the hole is distal from the second surface of the semiconductor substrate in relation to the first surface of the semiconductor substrate.

Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

Multi-chip package structure

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

Multichip package manufacturing process

Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

Integrated Fan-Out Structure with Openings in Buffer Layer

A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package. 1. A structure comprising: a through-via extending through a molding compound;', 'a device die encapsulated in the molding compound;', 'a buffer layer over the molding compound;', 'an opening disposed in the buffer layer and extending to the through-via, wherein the buffer layer comprises ripples around a circumference of the opening; and', 'a guiding trench encircling a portion of the buffer layer in a top-down view of the structure, wherein the portion of the buffer layer at least partially overlaps the device die., 'a first package comprising2. The structure of claim 1 , wherein the first package further comprises a laminating film contacting the buffer layer claim 1 , wherein the buffer layer is disposed between the laminating film and the molding compound claim 1 , and wherein the opening extends through the laminating film.3. The structure of claim 1 , wherein the ripples are in a periodic configuration around the circumference of the opening.4. The structure of further comprising a second package bonded to the first package by an electrical connector disposed in the opening.5. The structure of further comprising an underfill around the electrical connector and disposed between the first package and the second package claim 4 , wherein the underfill is partially disposed in the guiding trench.6. The structure of further comprising an additional guiding ring encircling the guiding ring in a top-down view of the structure.7. The structure of ...

Chip package and manufacturing method thereof

A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

STACKED SEMICONDUCTOR DEVICE

A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies. 1. A packaged semiconductor device comprising:multiple integrated circuit (IC) chips arranged as a stack, each chip including multiple input/output (I/O) pads, each I/O pad selectively coupled to an input/output (I/O ) circuit;wherein the I/O pads for each chip in the stack are vertically aligned with corresponding I/O pads in the other stacked chips to define vertically aligned sets of I/O pads;wherein a given vertically aligned set of I/O pads for the stacked chips is electrically coupled via a conductive path; andwherein less than all of the I/O circuits corresponding to a given vertically aligned set of I/O pads are electrically coupled to the conductive path.2. The packaged semiconductor device according to claim 1 , wherein the multiple IC chips comprise dynamic random access memory (DRAM) devices.3. The packaged semiconductor device according to claim 1 , wherein each path comprises through-silicon-vias formed through each chip.4. The packaged semiconductor device according to claim 1 , wherein each conductive path is coupled to no more than one I/O circuit.5. The packaged semiconductor device according to claim 1 , further comprising a programmable element to ...

Semiconductor package

A semiconductor package is provided. The semiconductor package includes a package substrate, a semiconductor chip, bonding wires, and a molding film. The package substrate includes a first surface having a recessed portion, a second surface opposed to the first surface, an opening extending from the recessed portion of the first surface to the second surface, and bonding pads provided on the first surface. The semiconductor chip is disposed on the second surface of the package substrate to cover the opening, and includes center pads exposed through the opening. Bonding wires electrically connect the center pads and the bonding pads through the opening. The molding film covers the bonding pads, the center pads, and the bonding wires. A depth of the recessed portion is greater than a distance between the recessed portion of the first surface and a lowermost surface of the molding film.

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods. 1. A method of forming a bonded semiconductor structure , comprising: providing a first semiconductor structure comprising at least one device structure;bonding a second semiconductor structure to the first semiconductor structure at a temperature or temperatures below about 400° C.;forming at least one through wafer interconnect through the second semiconductor structure and into the first semiconductor structure to the at least one device structure; andbonding the second semiconductor structure on a side thereof opposite the first semiconductor structure to a third semiconductor structure.2. The method of claim 1 , wherein bonding the second semiconductor structure to the first semiconductor structure comprises:bonding a relatively thicker semiconductor structure to the first semiconductor structure; andthinning the relatively thicker semiconductor structure to form the second ...

3DIC Interconnect Apparatus and Method

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

RECESSED AND EMBEDDED DIE CORELESS PACKAGE

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands. 16-. (canceled)7. A package structure , comprising:a dielectric material, wherein the dielectric material includes a first surface, a second surface that is spaced apart from the first surface, and a protruding portion that projects from the first surface and includes the second surface; anda die at least partially disposed in the dielectric material, and is at least partially embedded in the protruding portion of the dielectric material.8. The package structure of claim 7 , wherein the first surface is parallel the second surface.9. The package structure of claim 7 , wherein the die is attached to the dielectric material with an adhesive film.10. The package structure of claim 7 , wherein the package structure is a first package structure claim 7 , wherein the package structure includes a second package structure claim 7 , wherein the first and second package structures are coupled together in a package-on-package (PoP) configuration.11. The package structure of claim 10 , wherein the first package structure includes one or more interconnects comprising vias with contact pads claim 10 , to provide electric coupling with the second package structure.12. The package structure of claim 11 , wherein the one or more interconnects are first interconnects claim 11 , wherein the second package structure includes one or more second interconnects to couple with respective ones of the first interconnects.13. The package structure of claim 12 , further comprising one ...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the plurality of logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Serializer/Deserializer (“SerDes”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors. 1. A 3D semiconductor device , the device comprising: 'wherein said first metal layer comprises interconnecting said first transistors forming, at least in part a plurality of logic gates;', 'a first single crystal layer comprising a plurality of first transistors and a first metal layer,'}a plurality of second transistors overlaying, at least in part said first single crystal layer;a plurality of third transistors overlaying, at least in part said second transistors;a second metal layer overlaying, at least in part said third transistors;Input/Output pads to provide connection to external devices;a global power grid to distribute power to said device, said global power grid overlaying, at least in part said first metal layer; and wherein said third transistors are aligned to said first transistors with less than 40 nm misalignment,', 'wherein said first single crystal layer comprises an Serializer/Deserializer (“SerDes”) structure connected to at least one of said Input/Output pads,', 'wherein said global ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires. 1. A manufacturing method of a package structure , comprising:providing a carrier,disposing a semiconductor die and at least one sacrificial structure on the carrier;electrically connecting the semiconductor die to bonding pads on the sacrificial structure through a plurality of conductive wires;forming an encapsulant on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires;debonding the carrier,removing at least a portion of the sacrificial structure through a thinning process; andforming a redistribution layer on the semiconductor die and the encapsulant, the redistribution layer is electrically connected to the semiconductor die through the conductive wires.2. The manufacturing method of a package structure according to claim 1 , wherein the sacrificial structure is disposed on the carrier claim 1 , and the semiconductor die is disposed on the sacrificial structure.3. The manufacturing method of a package structure according to claim 2 , wherein a width of the sacrificial structure is greater than a width of the semiconductor die.4. The manufacturing method of a package structure according to claim 2 , wherein the redistribution layer is formed on the ...

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

PACKAGE ON ACTIVE SILICON SEMICONDUCTOR PACKAGES

Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds. 1. A package-on-silicon (PoS) semiconductor package , comprising: an upper surface;', 'a lower surface; and', a first portion of conductive structures disposed in a first pattern across the upper surface of the active silicon substrate; and', 'a second portion of conductive structures disposed in a second pattern across the upper surface of the active silicon substrate;, 'wherein the plurality of conductive structures includes, 'a plurality of conductive structures disposed across the upper surface;'}, 'wherein the plurality of conductive bumps communicably couple the first semiconductor package to the first portion of conductive structures disposed on the active silicon substrate; and', 'a first semiconductor package having an upper surface, a lower surface, and a plurality of conductive bumps disposed in the first pattern across the lower surface of the first semiconductor package;'}, the second semiconductor package disposed such that at least a portion of the first semiconductor package is ...

Selective die electrical insulation by additive process

Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.

INTERPOSER AND CIRCUIT SUBSTRATE

An interposer includes an insulating plate including insulating layers and having first, second, third and fourth surfaces such that the second surface is on the opposite side of the first surface, the third surface is perpendicular to the first surface, the fourth surface is on the opposite side of the third surface, and the insulating layers are laminated on the third surface, and conductor layers formed in the insulating plate such that each conductor layer is interposed between adjacent insulating layers and includes straight conductors having first electrodes exposed from the first surface and second electrodes exposed from the second surface, respectively. The insulating layers include second insulating layers each sandwiched by adjacent conductor layers such that each second insulating layer integrally has an inter-conductor-layer insulating layer portion formed between the adjacent conductor layers and inter-conductor insulating layer portions formed between adjacent straight conductors in a respective conductor layer. 1. An interposer , comprising:an insulating plate comprising a plurality of insulating layers and having a first surface, a second surface, a third surface and a fourth surface such that the second surface is on an opposite side of the first surface, the third surface is perpendicular to the first surface, the fourth surface is on an opposite side of the third surface, and the plurality of insulating layers is laminated on the third surface; anda plurality of conductor layers formed in the insulating plate such that each of the conductor layers is interposed between adjacent insulating layers and comprises a plurality of straight conductors having a plurality of first electrode portions exposed from the first surface at one ends and a plurality of second electrode portions exposed from the second surface at opposite ends, respectively,wherein the plurality of insulating layers includes a plurality of second insulating layers each sandwiched by ...

PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION CAPABILITY

Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors. 1a memory element that has an output and that has a power supply terminal at which a power supply voltage is provided;a pass transistor having a gate that is coupled to the output of the memory element; anda write assist circuit that applies a temporary adjustment to the power supply voltage, wherein the pass transistor receives the adjusted power supply voltage from the output of the memory element, and wherein the pass transistor exhibits a drive strength that is unaffected by the temporary adjustment in the power supply voltage.. An integrated circuit, comprising: This application is a continuation of U.S. patent application Ser. No. 14/737,246, filed Jun. 11, 2015. This application claims the benefit of and claims priority to U.S. patent application Ser. No. 14/737,246, filed Jun. 11, 2015, which is hereby incorporated by reference herein in its entirety.This relates to integrated circuits and more particularly, to programmable integrated circuits.Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first circuit board having a first chip and a second chip mounted on a first base, the second chip having a greater height from the first base than that of the first chip; and a second circuit board having a third chip and a fourth chip mounted on a second base, the fourth chip having a greater height from the second base than that of the third chip, the second circuit board being disposed overlapping with the first base such that the second base faces the first chip, and the second base not contacting the second chip. 1. A semiconductor device comprising:a first circuit board having a first chip and a second chip mounted on a first base, with the second chip having a greater height from the first base than that of the first chip; anda second circuit board having a third chip and a fourth chip mounted on a second base, the fourth chip having a greater height from the second base than that of the third chip, with the second circuit board disposed overlapping with the first circuit board such that the second base faces the first chip, and the second base not contacting the second chip.2. The semiconductor device of claim 1 , wherein the second base is narrower in width than the first base and does not contact the second chip.3. The semiconductor device of claim 2 , wherein:the first base further includes a protrusion protruding further toward an outer-side than the second base in plan view; andthe second chip is mounted on the protrusion.4. The semiconductor device of claim 1 , wherein:the second chip is housed in a housing hole that penetrates the second base such that the second base does not contact the second chip.5. The semiconductor device of claim 1 , further comprising a connecting member that is disposed between the first base and the second base claim 1 , and that electrically connects the first base and the second base.6. The semiconductor device of claim 5 , wherein the connecting member is disposed at a position ...

Interconnection structures and methods for making the same

The present disclosure provides a method for interconnecting components. First and second substrates are provided. First and second components are respectively provided on the first and second substrates, in which the second component is not in contact with the first component. Then, a joint component is formed between the first and second components by passing a flow of a fluid comprising ions of a conductive material between the first and second components and electrolessly plating the first and second components by the conductive material so that the joint component is electrically connected between the first and second components. The present disclosure also provides related interconnection structures and a fixture for forming a related microchannel structure.

Semiconductor Device and Method of Manufacture

A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode. 1. A semiconductor device comprising: a first unique identifier structure;', 'a first electrical input; and', 'a first comparator comprising a first input connected to the first unique identifier structure and comprising a second input connected to the first electrical input;, 'a first semiconductor device comprising a second unique identifier structure different from the first unique identifier structure;', 'a second electrical input electrically connected to the first electrical input; and', 'a second comparator comprising a third input connected to the second unique identifier structure and comprising a fourth input connected to the second electrical input., 'a second semiconductor device bonded to the first semiconductor device, the second semiconductor device comprising2. The semiconductor device of claim 1 , wherein the first unique identifier structure comprises:a first reference voltage line;a second reference voltage line; anda plurality of identification lines, each of the plurality of identification lines being electrically connected to one of the first reference voltage line or the second reference voltage line through one or more vias.3. The semiconductor device of claim 1 , wherein the first unique identifier structure comprises:a first reference voltage line;a second reference voltage line; anda plurality of identification lines, each of the plurality of identification lines being electrically connected or isolated to one of the first ...

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device includes a first die having a first surface and a second surface opposite to the first surface, and a first adhesive layer disposed on the first surface of the first die. The semiconductor package device further includes an encapsulant layer encapsulating the first die and the first adhesive layer, and a first conductive via disposed in the first adhesive layer and electrically connected to the first die. 1. A semiconductor package device , comprising:a first die, having a first surface and a second surface opposite to the first surface;a first adhesive layer disposed on the first surface of the first die;an encapsulant layer encapsulating the first die and the first adhesive layer; anda first conductive via disposed in the first adhesive layer and electrically connected to the first die.2. The semiconductor package device of claim 1 , further comprising a first conductive layer disposed on the second surface of the first die and covering substantially the entire second surface of the first die claim 1 , wherein the first conductive layer has a first surface and a second surface opposite to the first surface and exposed from the encapsulant layer claim 1 , the first surface of the first conductive layer directly contacts the second surface of the first die and the second surface of the first conductive layer is substantially coplanar with a first surface of the encapsulant layer.3. The semiconductor package device of claim 2 , further comprising a second conductive via disposed in the first die claim 2 , wherein the second conductive via is electrically connected to the first conductive layer and the first conductive via.4. The semiconductor package device of claim 1 , further comprising a first conductive layer disposed on the encapsulant layer claim 1 , wherein the conductive layer covers substantially an entire surface of the encapsulant layer.5. The semiconductor package device of claim 4 , further comprising:a patterned conductive ...

Semiconductor package device and method of manufacturing the same

A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

THROUGH SILICON VIA SHARING IN A 3D INTEGRATED CIRCUIT

The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies. 1. A structure comprising:a plurality of stacked dies each containing at least one macro device; anda layer structure positioned between the plurality of stacked dies which comprises a control structured to route signals between the at least one macro device of a first stacked die and the at least one macro device of a second stacked die of the plurality of stacked dies, wherein the control includes a control logic to selectively and dynamically route signals through a through silicon via (TSV) allocation which connects to the at least one macro device of a first die and a second die of the plurality of stacked dies, whereinthe control comprises at least one multiplexer and at least one demultiplexer which forward the signals throughout the layer structure,the control logic selectively enables and disables the at least one multiplexer and the at least one demultiplexer to dynamically route the signals through the TSV allocation,the control logic selectively routes the signals through different TSV allocations,the control logic includes at least one of history tables, priority queues, programmed priority, and controller application,the layer structure further comprises a content addressable memory (CAM) which stores the history tables, andthe history tables keep an accounting of requests from the at least one macro device to determine a frequency of the request.2. The structure of claim 1 , wherein the at ...

Bonded Semiconductor Structures

A method is disclosed that includes the steps outlined below. A first oxide layer is formed to divide a first semiconductor substrate into a first part and a second part. A second oxide layer is formed on the first part of the first semiconductor substrate. The first oxide layer is bonded to a third oxide layer of a second semiconductor substrate. The second part of first semiconductor substrate and the first oxide layer are removed to expose the first part of the first semiconductor substrate.

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors. 1. A 3D semiconductor device , the device comprising: 'wherein said first metal layer comprises interconnecting said first transistors forming, at least in part a plurality of logic gates;', 'a first single crystal layer comprising a plurality of first transistors and a first metal layer,'}a plurality of second transistors overlaying, at least in part said first single crystal layer;a plurality of third transistors overlaying, at least in part said second transistors;a second metal layer overlaying, at least in part said third transistors;Input/Output pads to provide connection to external devices;a global power grid to distribute power to said device, said global power grid overlaying, at least in part said first metal layer; and wherein said third transistors are aligned to said first transistors with less than 40 nm misalignment,', 'wherein said first single crystal layer comprises a Phase Lock Loop (“PLL”) structure connected to at least one of said Input/Output pads,', 'wherein said global power grid is connected to said local ...

Interconnect structure for stacked die in a microelectronic device

A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

Bonding Package Components Through Plating

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a substrate and an electronic component disposed on the substrate. The electronic component has an active surface facing away from the substrate. The substrate has a first conductive pad and a second conductive pad disposed thereon. The electronic component has a first electrical contact and a second electrical contact disposed on the active surface. The semiconductor device package further includes a first metal layer connecting the first electrical contact with the first conductive pad, a second metal layer connecting the second electrical contact with the second conductive pad, a first seed layer disposed below the first metal layer; and a first isolation layer disposed between the first metal layer and the second metal layer. A method of manufacturing a semiconductor device package is also disclosed.

HIGH BANDWIDTH DIE TO DIE INTERCONNECT WITH PACKAGE AREA REDUCTION

Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer. 1. A package structure comprising:a first wiring layer including a first side and a second side opposite the first side;a first die and a vertical interposer side-by-side on the first side of the first wiring layer, wherein the vertical interposer includes electrical interconnects from a first side of the vertical interposer coupled with the first side of the first wiring layer to a second side of the vertical interposer opposite the first side of the vertical interposer;a second die face down on and electrically connected with the second side of the vertical interposer; anda local interposer on the second side of the first wiring layer and in electrical connection with the first die and the vertical interposer;wherein first transistors of the first die are formed with a different processing node than second transistors of the second die.2. The package structure of claim 1 , wherein the first transistors of the first die are formed with a smaller processing node than second transistors of the second die.3. The package of claim 1 , wherein the first die comprises a first core selected from the group consisting of a central processing unit and a graphics processing unit.4. The package of claim 3 , wherein the second die comprises a memory core.5. The package of claim 3 , wherein the second die comprises an RF core.6. The package structure of claim 1 , wherein the first die and the second die comprise split logic.7. The package structure of claim 1 , wherein the local interposer includes a plurality of terminals on a first side of the local interposer that is coupled with the second side of the first wiring layer ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed. 1. A semiconductor structure , comprising:a semiconductor substrate including a front surface and a back surface, wherein the front surface includes a transistor formed thereon;a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, and at least a portion of the backside metallization layer forming an inductor structure; anda front side metallization layer formed over the semiconductor substrate, the front side metallization layer being closer to the front surface than to the back surface of the semiconductor substrate.2. The semiconductor structure of claim 1 , further comprising:an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate.3. The ...

System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack

A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

In a method for manufacturing a semiconductor device, a resin layer including an inorganic filler is molded on a surface of a substrate which includes semiconductor elements attached thereto by an adhesive, and terminals electrically connected to the semiconductor elements on another surface thereof. The molded substrate is cut so as to expose a conductive body electrically connected to an external terminal maintainable at ground potential. The surface of the resin layer of the substrate is sputter-etched in a vacuum environment, in a state where a plurality of the cut substrates is provided in a tray so that the surface of the substrate faces the tray. A metal layer is sputtered so as to be electrically connected to the conductive body on the surface and the cut surface in a state where the substrate is provided in the tray while maintaining the vacuum environment after sputter-etching. 1. A method for manufacturing a semiconductor device , comprising:molding a sealing resin layer, including an inorganic filler therein, on a surface of a substrate which includes a plurality of semiconductor elements attached thereto by an adhesive, the substrate further including external input and output terminals disposed on another surface thereof electrically connected to the semiconductor elements;cutting the molded substrate so as to expose a conductive body therein having a terminal portion electrically connectable to an external input and output terminal, the external input and output terminal configured to be connectable to a ground potential;positioning the cut molded substrates in a tray such that a surface of the sealing resin layer is exposed and an opposed surface of the cut molded substrate faces a surface of the tray;sputter-etching, in a sub-atmospheric pressure environment, the exposed surface of the sealing resin layer; andsputtering a metal layer over the sealing resin layer and the cut portion of the molded substrate in a sub-atmospheric pressure environment to ...

METHODS AND APPARATUS FOR PROVIDING AN INTERPOSER FOR INTERCONNECTING SEMICONDUCTOR CHIPS

Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate. 1. An interposer for interconnecting one or more semiconductor chips with a substrate in a semiconductor package , the interposer comprising:a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1);a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2);an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate; andat least one via extending from the first major surface of the first glass substrate to the second major surface of the second glass substrate,wherein CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the substrate.2. The interposer of claim 1 , wherein 1≦ ...

PROCESS FOR PRODUCING A STRUCTURE BY ASSEMBLING AT LEAST TWO ELEMENTS BY DIRECT ADHESIVE BONDING

A method for producing a structure by direct bonding of two elements, the method including: production of the elements to be assembled and assembly of the elements. The production of the elements to be assembled includes: deposition on a substrate of a TiN layer by physical vapor deposition, and deposition of a copper layer on the TiN layer. The assembly of the elements includes: polishing the surfaces of the copper layers intended to come into contact so that they have a roughness of less than 1 nm RMS and hydrophilic properties, bringing the surfaces into contact, and storing the structure at atmospheric pressure and at ambient temperature. 116-. (canceled)17. A production method for producing a structure by direct bonding of two elements comprising:production of the elements to be assembled and assembly of the elements; [{'sub': x', 'x, 'deposition on a substrate of at least one growth portion made from a material chosen from TiNand TaN, the growth portion being deposited by physical vapor deposition, and'}, 'deposition of at least one first portion of copper on all or part of the growth portion, conditions for depositing the growth portion by physical vapor deposition being such that the ratio between intensities of peaks is greater than or equal to 0.5, whereby the peaks are measured by X-Ray diffraction; and, 'wherein the production of the elements to be assembled comprises polishing surfaces of the first portions of copper intended to come into contact so that they have a roughness of less than 1 nm RMS and hydrophilic properties,', 'bringing the surfaces into contact,', 'storing the structure at a low temperature., 'wherein the assembly of the elements comprises18. A production method according to claim 17 , wherein the deposition of the growth portion by physical vapor deposition takes place at a temperature between 196° C. and 250° C.19. A production method according to claim 17 , wherein the deposition of the growth portion by physical vapor deposition ...

SOLID STATE DRIVE PACKAGE AND DATA STORAGE SYSTEM INCLUDING THE SAME

A solid state drive (SSD) package type has a lower package including a lower package substrate, a controller chip mounted on the lower package substrate, and a plurality of upper packages disposed on the lower package as spaced apart from each other. The plurality of upper packages includes at least one non-volatile memory and at least one first individual electronic component. The upper packages are electrically connected to the lower package such that the package type is a package-on-package (PoP) type. The height of the first individual electronic component is greater than the spacing between the lower package and each of the upper packages. 1. A solid state drive (SSD) package-on-package (PoP) , comprising:a lower package comprising a lower package substrate, a controller chip disposed on and mounted to the lower package substrate, and a lower mold layer on an upper surface of the lower package substrate and covering the controller chip; anda plurality of upper packages disposed on the lower package as spaced laterally apart from each other, and including a non-volatile memory package comprising a non-volatile memory and an individual component package comprising an individual electronic component, the non-volatile memory and the individual electronic component being electrically connected to the lower package,wherein the height of the first individual electronic component is greater than a thickness of the lower mold layer at the controller chip as measured from the upper surface of the lower package substrate.2. The SSD package-on-package of claim 1 , wherein the lower package further comprises a semiconductor memory chip mounted on the lower package substrate as laterally spaced apart from the controller chip claim 1 , and the non-volatile memory package spans the semiconductor memory chip as viewed in plan.3. The SSD package-on-package of claim 2 , wherein the semiconductor memory chip comprises a non-volatile memory.4. The SSD package-on-package of claim 1 ...

PACKAGING STRUCTURE

A packaging structure includes a first substrate including a first metal terminal and a second metal terminal whose height is lower than the height of the first metal terminal; and a second substrate including a third metal terminal and a fourth metal terminal whose height is lower than the height of the third metal terminal, the second substrate being provided on the first substrate, the first metal terminal and the third metal terminal being directly bonded with each other, and the second metal terminal and the fourth metal terminal being bonded via a connection portion. 1. A packaging structure comprising:a first substrate including a first metal terminal and a second metal terminal whose height is lower than the height of the first metal terminal, the first metal terminal and the second metal terminal being formed at a first surface of the first substrate; anda second substrate including a third metal terminal and a fourth metal terminal whose height is lower than the height of the third metal terminal, the third metal terminal and the fourth metal terminal being formed at a second surface of the second substrate, the third metal terminal being made of the same kind of metal as the first metal terminal,the second substrate being provided on the first substrate such that the second surface of the second substrate faces the first surface of the first substrate,the first metal terminal and the third metal terminal being directly bonded with each other, andthe second metal terminal and the fourth metal terminal being bonded via a connection portion.2. The packaging structure according to claim 1 , further comprising a plurality of the second metal terminals and a plurality of the fourth metal terminals claim 1 , wherein the plurality of second metal terminals and the plurality of fourth metal terminals are provided at an area that is an outer periphery side of an area at which the first metal terminal and the third metal terminal are provided claim 1 , in a plan ...

Backside Stacked Die In An Integrated Circuit (IC) Package

An integrated circuit (IC) device may include a substrate including a first mounting area and a ground ring, a first integrated circuit die attached to the first mounting area, a die attach paddle mounted onto the ground ring and extending above the first integrated circuit die, and a second integrated circuit die mounted on a second mounting area, wherein the die attach paddle defines the second mounting area above the first integrated circuit die. The second integrated circuit die may have a backside oriented toward the substrate and connected to ground. 1. An integrated circuit device comprising:a substrate including a first mounting area and a ground ring;a first integrated circuit die attached to the first mounting area;a die attach paddle mounted onto the ground ring and extending above the first integrated circuit die; anda second integrated circuit die mounted on a second mounting area;wherein the die attach paddle defines the second mounting area above the first integrated circuit die.2. An integrated circuit device according to claim 1 , wherein the second integrated circuit die includes a backside oriented toward the substrate and connected to ground.3. An integrated circuit device according to claim 1 , further comprising a conductive die attach material joining the die attach paddle to the substrate.4. An integrated circuit device according to claim 1 , wherein the first integrated circuit die and the second integrated circuit die have matching footprints.5. An integrated circuit device according to claim 1 , wherein the first integrated circuit die and the second integrated circuit die comprise identical devices.6. An integrated circuit device according to claim 1 , wherein the first integrated circuit die and the second integrated circuit die comprise 4-channel pulsers.7. An integrated circuit device according to claim 1 , wherein the first mounting area comprises an exposed die attach pad.8. An integrated circuit device according to claim 1 , wherein ...