Semiconductor device

Cross-referenced related application

4 March 2011 of the Japanese Patent application submitted 2011 - 48053 of all the disclosed content (including the specification, Figure and SUMMARY) in this by reference into this text.

Background Art

The invention relates to a semiconductor device, in particular when applied to the equipped with the such as SRAM memory semiconductor device such as the effective technology.

For example, Patent document 1 discloses a semiconductor memory device, the semiconductor storage device is assembled with a plurality of virtual unit virtual circuit to generate a sense amplifier enable signal. Patent document 2 discloses a single bit line system in the semiconductor memory device, the semiconductor memory device is configured to copy the bit line coupled to the copy of the memory cell transistor gate length of the memory cell transistor set up than the original length of the gate is longer, in the stated in a bit line system, reading the operation sequence of the bit line is by the operation of the copy of the decision. Patent document 3 discloses a semiconductor integrated circuit device, the semiconductor integrated circuit device assembled with a 1st and 2nd bit line copy of a copy of the bit line, the bit line copy of the 1st and the 2nd bit line coupled to the storage unit of the copy of the copy of the respectively, and the semiconductor integrated circuit device assembled with the 1st bit line copy of the input to the output signal of the bit line of the copy of the 2nd phase inverter circuit, and the semiconductor integrated circuit device through the use of separating the bit line of the copy generating the read amplifier enable signal.

(Patent document)

(Patent document 1) Japanese Patent 2004 - 95058 Bulletin

(Patent document 2) Japanese Patent 2006 - 31752 Bulletin

(Patent document 3) Japanese Patent 2010 - 165415 Bulletin

Content of the invention

In recent years, with the geometric dimensions of the semiconductor device become increasingly fine, the change between the MOS transistor has become an important subject. Therefore, for example, in the semiconductor device in include memory (typically an SRAM (static random access memory) assembly) in, taking into account the change in the SRAM memory cell performs a sequence design become important. Such as in Patent document 1 to Patent document 3 the disclosed, such sequence design method in the method is to read the use of the virtual storage unit (a copy of the storage unit) and the dummy bit line (the bit line copy) sets the read amplifier of the start of the sequence of the method.

However, in the use of such virtual storage unit and so on in the method, due to the virtual storage unit itself and the process fluctuations, may not be the starting timing of the sense amplifier to achieve the optimal. In other words, the majority of cases the virtual storage unit by the storage unit is the same as the original form of the size of the process, the original storage unit to very small sizes form; therefore, easy occurrence of such process fluctuations. For example, when the process fluctuations occur in the plurality of coupling to the dummy bit line virtual storing unit, driving the dummy bit line of the time sequence for each of the virtual storage unit is different. Therefore, the sense amplifier may occur too early or too late starting timing of the situation.

The invention according to the above situation, and an object of the present invention is equipped with the memory of the semiconductor device in the change of the operation sequence of the reduction. Through the description of the invention and the description of the Figure, the above-mentioned purpose and other purposes and new features will become clear.

The following briefly to explain the invention disclosed in this application in the profile of the typical mode of execution.

According to the semiconductor device of this invention comprises: 1st extending in the direction along the plurality of word lines; along the direction crossing the 1st 2nd extending in the direction of the plurality of bit lines; and the word lines arranged in the bit line of the intersection of the plurality of memory cells, the plurality of memory unit configuration including the 1st MIS transistor including the circuit.

According to the semiconductor device of this invention further comprises: a sense amplifier circuit, the sense amplifier circuit can respond to the enabling signal, via the plurality of bit lines of a bit line will be read out from the plurality of storage unit in a storage unit of the signal amplification; control circuit, said control circuit in response to the plurality of memory cell access instruction generating 1st signal; and, a timing adjustment circuit, wherein the timing adjustment circuit capable of receiving the input of the 1st signal, and by delaying the 1st signal to produce as the enable signal sources of 2nd signal.

Wherein the timing adjusting circuit includes: 1st wiring, the wiring and the 1st of the plurality of bit lines arranged side by side and forming at least one two-way wiring, and the 1st wiring can receive the transmission of the one end of the 1st signal and output from the other end of the 2nd signal; and the load circuit, the load circuit includes a plurality of coupling to the 1st 2nd MIS wiring of the transistor.

The 1st wiring includes a used as the external wiring of the 1st dummy bit line and is used as the return to the wiring of the 2nd dummy bit line, and the plurality of 2nd MIS transistor are respectively provided with 2nd 1st dummy bit line and dummy bit line.

The following briefly to explain the application discloses a typical embodiment of the present invention to obtain the effect. In other words, in the memory is set in the semiconductor device, the change of the operation sequence of the reduction is possible.

Description of drawings

Figure 1 is the block diagram of SUMMARY shown according to the embodiment of the invention 1 comprising in a semiconductor device memory configuration example;

Figure 2 is the wiring diagram of memory in each memory unit of the configuration example shown in Figure 1;

Figure 3 is the profile of SUMMARY graphical representation chart 1 memory operation of the shown embodiment;

Figure 4 is the block diagram of graphical representation according to the embodiment of the invention 1 outline of the whole of the semiconductor device structure embodiment;

Figure 5 is the wiring diagram of graphical representation chart 1 shown memory of the timing adjusting circuit (a column direction) configuration example;

Figure 6 is the wiring diagram of graphic through the improved Figure 5 shown by the timing adjustment circuit of a timing adjustment circuit (a column direction) configuration example;

Figure 7 is the top view of graphical representation chart 5 and Figure 6 is shown a timing adjustment circuit of the load circuit in the column direction of the specific layout configuration example;

Figure 8 (a) is shown basiscopic 7 shown A - A 'line sectional view of the structure of the embodiment, Figure 8 (b) is basiscopic 7 shown B - B' line sectional view of the structure of the embodiment;

Figure 9 is the illustrative comparison top view of graphical representation chart 1 shows the word and line by the driving circuit, the timing adjusting circuit (a column direction) and the portion of the memory array layout configuration example;

Figure 10 (a) and Figure 10 (b) is respectively graphical representation chart 5 and Figure 6 of the embodiment of the configuration of the timing adjustment circuit and the size of the memory array of the illustrative top view of the link;

Figure 11 (a) and Figure 11 (b) is graphical representation chart 5 shown the timing adjusting circuit and Figure 6 is shown a timing adjustment circuit of the significant difference of the embodiment of the interpretative with photos;

Figure 12 is the wiring diagram of graphic according to the embodiment of the invention 2 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration example;

Figure 13 is the wiring diagram of graphic according to the embodiment of the invention 2 comprising in a semiconductor device the timing adjusting circuit (column direction) of another configuration example;

Figure 14 (a), fig. 14 (b) and Figure 14 (c) is graphical representation chart 12 shows the row direction by the load in the load circuit capacitance supplementary with photos, wherein fig. 14 (a) and Figure 14 (b) is a representation of the position of the load capacitance of the schematic view, Figure 14 (c) to brief shows and Figure 14 (a) and Figure 14 (b) of the load capacitance corresponding to the waveform of the voltage of the of the embodiment of Figure;

Figure 15 (a), fig. 15 (b) and Figure 15 (c) is graphical representation chart 13 shows the row direction by the load in the load circuit capacitance supplementary with photos, wherein Figure 15 (a) and Figure 15 (b) is a representation of the position of the load capacitance of the schematic view, Figure 15 (c) is SUMMARY shows and Figure 15 (a) and Figure 15 (b) corresponding to the load capacitance of the voltage waveform of the embodiment of Figure;

Figure 16 (a) is a graphical representation according to the embodiment of the invention 3 comprising in a semiconductor device the timing adjusting circuit (column direction) of the embodiment of the configuration of the wiring diagram, Figure 16 (b) Figure 16 (a) complementary with photos;

Figure 17 (a) is a graphical representation according to the embodiment of the invention 3 comprising in a semiconductor device the timing adjusting circuit (column direction) of another configuration example of the wiring diagram, Figure 17 (b) Figure 17 (a) complementary with photos;

Figure 18 is the wiring diagram of graphic according to the embodiment of the invention 4 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration example;

Figure 19 (a) is a graphical representation according to the embodiment of the invention 5 in the semiconductor device, Figure 1 shown in the memory read/write control circuit of the peripheral configuration of the block diagram of the embodiment, Figure 19 (b) is graphical representation chart 19 (a) of the SZ/write delay control circuit wiring diagram of the concrete configuration of the embodiment;

Figure 20 (a) is graphical representation chart 19 at the time of reading in the operation of the embodiment of the profile, Figure 20 (b) is graphical representation chart 19 in the load in the operation of the embodiment of the profile;

Figure 21 is the wiring diagram of graphic according to the embodiment of the invention 6 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration example;

Figure 22 is the wiring diagram of graphic according to the embodiment of the invention 7 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration example;

Figure 23 is the wiring diagram of graphical representation chart 22 as shown in the wiring diagram of the improved embodiment;

Figure 24 is the top view of graphical representation chart 22 and Figure 23 shown in the column direction of the timing adjustment circuit of the load circuit configuration example of the specific pattern;

Figure 25 is the wiring diagram of graphic according to the embodiment of the invention 8 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration example;

Figure 26 is the top view of graphical representation chart 25 shown in the column direction of the timing adjustment circuit of the load circuit configuration example of the specific pattern;

Figure 27 is the wiring diagram of graphic according to the embodiment of the invention 9 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration example;

Figure 28 is the wiring diagram of graphic according to the embodiment of the invention 10 comprising in a semiconductor device the timing adjusting circuit (a row direction) configuration example;

Figure 29 is the top view of graphical representation chart 28 shown in the row direction of the timing adjustment circuit of the load circuit configuration example of the specific pattern;

Figure 30 (a), fig. 30 (b) and Figure 30 (c) is a graphical representation according to the embodiment of the invention 11 in the semiconductor device of the memory of the timing adjusting circuit (a column direction) each different layout of the schematic view of the embodiment;

Figure 31 (a), fig. 31 (b) and Figure 31 (c) for shows and Figure 30 (a), fig. 30 (b) and Figure 30 (c) different memory of the timing adjusting circuit (column direction) of each different layout of the schematic view of the embodiment;

Fig. 32 (a) and Figure 32 (b) is respectively graphical representation chart 30 and Figure 31 as shown in the timing adjustment circuit (a column direction) in the following cases of the flow signal of the interpretative with photos: in a word line driving circuit and a timing adjustment circuit is disposed on one side of the memory array under the circumstance of, and a word line driving circuit and a timing adjustment circuit arranged in the memory array of the two sides of the case.

Figure 33 (a), Figure 33 (b) and Figure 33 (c) is a graphical representation according to the embodiment of the invention 12 in the semiconductor device of the memory of the timing adjusting circuit (column direction) of each different layout of the schematic view of the embodiment;

Figure 34 (a) and Figure 34 (b) is shows and Figure 33 (a), Figure 33 (b) and Figure 33 (c) shown in different memory of the memory timing adjusting circuit (column direction) of each of the different layout schematic view of the embodiment; and

Figure 35 (a) and Figure 35 (b) is a graphical representation according to the embodiment of the invention 13 of the semiconductor device in the memory of the timing adjusting circuit (a row direction) of each different layout of the schematic view of the embodiment.

Mode of execution

For the sake of convenience, in the following embodiment when necessary, in order to separate the plurality of parts of the explanation or the embodiment. However, unless otherwise specified, the above-mentioned many parts or embodiments are not mutually related, the relationship between them is: one of some or all of the other of the improved embodiment, detailed or supplementary explanation. In the following embodiment, when referred to the number of components and the like (including number, numerical value, quantity, range and so on) when, the number is not limited to the specific number can be more than or less than the specific number, in addition to the number of designated or is clear from the principle clearly limited to a particular number of cases.

In addition, in the following embodiment, needless to say assembly (including the element steps etc.) is not necessary, in addition to the assembly is a clearly designated or from the principle that in the case of the assembly is necessary. Similarly, in the following embodiment, when the shape of the mentioned assembly and, when the position relations, should include the basic shape is close to or substantially similar to the shape, positional relationship and so on, in addition to the shape, position and so on is clearly designated or from the principle that the shape, position and the like obviously different case. The same applies to the value and range as described above.

Although not specifically limited, but the embodiment of the configuration of the various functional modules of the circuit component is well known by such as CMOS (complementary MOS) transistor such as similar integrated circuit technology in the single crystal silicon formed on the semiconductor substrate. In the embodiment, the MISFET (metal insulator semiconductor field effect transistor) (abbreviated as MIS transistor), MOSFET (metal oxide semiconductor field effect transistor) (abbreviated as MOS transistor) as an example. However, does not preclude the use non-oxide film as the gate insulating film. The following in the Figure, the circle symbols on the grid is added to distinguish the p - channel MOS transistor (PMOS transistor) and n - channel MOS transistor (NMOS transistor). In the Figure of not specifying the substrate potential of the MOS transistor coupling. However, as long as the MOS transistor can be normal operation, method of coupling is not affected by the specific constraints.

In the below, embodiments of the present invention will refer to the Figure a specific explanation. Used for explaining embodiments of the present invention all in a diagram, in general the same symbol corresponding to the same assembly, and omit the repeated explanation thereof.

Embodiment 1

"The whole memory of the outline structure"

Figure 1 is the block diagram of SUMMARY shown according to the embodiment of the invention 1 comprising the semiconductor device of the embodiment in the configuration of the memory. Figure 1 shown in the memory MEMU comprises: address control circuit ADRCTL, a word line driving circuit WD, the timing adjusting circuit (a column direction) TMCTLB, memory array MARY, column select circuit YSW, read/write control circuit RWCTL, write drive circuit WTD, sense amplifier circuit SA and the input/output buffer circuit IOB. The memory array includes MARY 1st extending along the direction of the m word line WL0 - WLm, along with said 1st 2nd intersecting in the direction extending in the direction of the n bit line pair (BL0, ZBL0) - (BLn, ZBLn), and disposed in the m n bits of word and the intersection of the line to the plurality of memory cell MC. Each bit line pair is configured with the transmission the complementary signal of the two bit line (for example, BL0 and ZBL0).

The address control circuit ADRCTL response as the trigger of the TDEC decoding activation signal, from the memory of the MEMU external address terminal input of the address signal A0 - Aj decode (or pre-encoding), and the line selection signal X0 - Xk and column selection signal Y0 - Yi. A word line driving circuit WD (activated) selected with the row select signal X0 - Xk corresponding to the word lines in a plurality m of a word line. Column select circuit YSW selection with the column selection signal Y0 - Yi n bit line corresponding to the one of the pair of the pair of bit lines. The timing adjusting circuit TMCTLB is the main feature of this embodiment in a, its detail will be described below. A timing adjustment circuit in TMCTLB receives the input of the decoding activation signal output the dummy bit line signal after the TDEC SDBL. Read/write control circuit RWCTL from the memory in response to an external control terminal MEMU every control signal (WEN, CLK, CEN) and the dummy bit line signal SDBL, generating decoding activation signal TDEC, internal write enable signal and the read amplifier enable signal WE SE. Control signal WEN a distinction is drawn between the read instruction and write instructions of the write enable signal. The control signal CLK is used as the read/write operation of the reference clock signal. The control signal for the control of the clock signal CEN whether effective clock enable signal.

The input/output buffer circuit input from the memory of the IOB MEMU external data terminal of the data input signal Di, and transmit it to the write drive circuit WTD. The input/output buffer circuit IOB also input from the output of the sense amplifier circuit SA signal, and as a data output signal Do output to the external data terminal. The write drive circuit in response to the write enable signal WTD WE, from an input/output buffer circuit of the IOB data different degree of amplification, and by the above column select circuit YSW transmit it to the predetermined bit line pair. In response to the sense amplifier circuit SA as the trigger of the sense amplifier enable signal SE, via the column select circuit YSW, from predetermined bit line to the transmitted signal to the different degree of amplification, and outputs it to the input/output buffer circuit IOB.

Figure 2 is the wiring diagram of graphical representation chart 1 shown in each memory cell in the memory configuration of the MC examples. Figure 2 shown in the memory cell MC for the SRAM memory cell, said SRAM storage unit assembly has four NMOS transistor MN1 - MN4 PMOS transistor MP1 and two and MP2. For the NMOS transistor MN3 purposes, is coupled to the gate to word and line WL, one of the source/drain is coupled to the positive electrode on the side of the bit line BL. For the NMOS transistor MN4 purposes, is coupled to the gate to word and line WL, and the source/drain coupled to one of the bit line to the negative side of the ZBL. Transistor MN1, MP1 and transistor MN2, MP2 are respectively provided with a power supply voltage of the power supply voltage VSS VCC and ground between the CMOS of the inverter circuit. The two CMOS inverter circuit through a side of the output coupling to the other side of the input configuration locked to the latch circuit. NMOS transistor MN4 source/drain of the other one of the CMOS inverter circuit is coupled to the (MN1, MP1) input (CMOS inverter circuit (MN2, MP2) output). NMOS transistor MN3 source/drain of the other one of the CMOS inverter circuit is coupled to the (MN2, MP2) input (CMOS inverter circuit (MN1, MP1) output).

"SUMMARY of the whole memory operation"

Figure 3 is the profile of SUMMARY graphical representation chart 1 the operation of the memory in the embodiment. In fig. 3 of the embodiment, the clock signal CLK occurs, the clock enable signal CEN is in the "low (L)" level and write-enabled signal WEN is in the "high (H)" level, to carry out the read cycle (T0), the clock enable signal CEN is in the "low" level and write-enabled signal WEN is in the "low" level, the implementation of the write cycle (T1). The clock signal CLK occurs, the clock enable signal CEN is in the "high" level, memory into the "non-operating cycle (T2)", not only to carry out the read operation also does not carry out the write operation.

In the read cycle (T0) in, first of all, the read/write control circuit in response to a clock signal CLK RWCTL emergence, the TDEC decoding activation signal from "low" to "high" level conversion level. The read/write control circuit RWCTL output a "low" level of the internal write enable signal WE. The address control circuit in response to the decoding activation signal ADRCTL TDEC to "high" level of conversion, generating with the address signal A0 - Aj the rows corresponding to the selection signal X0 - Xk and column selection signal Y0 - Yi (Figure 3 shown in the Y0). In fig. 3 of the embodiment, on the assumption that the word line WL0 by the row selection signal X0 - Xk selected, bit line pair (BL0, ZBL0) by the column selection signal Y0 - Yi selected. A word line driving circuit WD corresponding to the row select signal X0 - Xk, the word line WL0 is activated to "high" level. Therefore, the word line WL0 coupling of the memory cell MC of the memory data is read out to the corresponding bit line pair. In this, the read out signal outside of the bit line pair (BL0, ZBL0) in the reading signal via the column select circuit YSW is transferred to the sense amplifier circuit SA.

On the other hand, at the same time, a timing adjustment circuit in response to the decoding activation signal TMCTLB TDEC to "high" level of conversion, in the additional predetermined delay time (Tdly1) after the dummy bit line signal SDBL conversion to "high" level. Read/write control circuit in response to the dummy bit line signal RWCTL SDBL to "high" level of the conversion, the read amplifier enable signal SE to transition to the active state ("high" level). In response to the sense amplifier circuit SA as the trigger of the sense amplifier enable signal SE to "high" level of conversion, to as mentioned above by the column select circuit YSW sending of the pair of bit lines (BL0, ZBL0) of the read signal is amplified. The amplified signal as the data output signal via the input/Do output buffer circuit IOB output to the external terminal. In this example, the activation of the word line WL0 in response to the activation signal from the decoding TDEC "high" level to "low" level of conversion, to be de-activated.

Next, in the write cycle (T1) in, first of all, the read/write control circuit in response to a clock signal CLK RWCTL emergence, the TDEC decoding activation signal from "low" to "high" level conversion level. Read/write control circuit RWCTL outputs a "high" level of the internal write enable signal WE. The address control circuit in response to the decoding activation signal ADRCTL TDEC to "high" level of conversion, generates a row selection signal X0 - Xk and column selection signal Y0 - Yi, and a word line driving circuit WD activation with the row selection signal X0 - Xk corresponding word lines (in the in this example is the WL0). At the same time, on the other hand, from the external terminal of the data input signal via the input/Di output buffer circuit IOB input to write drive circuit WTD. The write drive circuit in response to the aforementioned WTD WE internal write enable signal to the "high" level of conversion, from an input/output buffer circuit amplifying the input signal of the IOB. Column select circuit YSW write drive circuit with the output of the WTD coupled to the column select signal Y0 - Yi a corresponding bit line to (in this example is BL0 and ZBL0). Therefore, the data input signal Di information is written to the selected memory cell MC. After, in this example, the activation of the word line WL0 in response to the activation signal from the decoding TDEC "high" level to "low" level of conversion, to be de-activated. Therefore, the selected memory cell MC storing data input signal Di information.

"The whole of the semiconductor device structure of the outline"

Figure 4 is the block diagram of graphical representation according to the embodiment of the invention 1 SUMMARY of the whole semiconductor device structure example. Figure 4 graphically shows the referred to as SOC (system-on-chip) and the like of the semiconductor device (LSI), wherein each logic circuit and a memory circuit formed on a semiconductor chip. Figure 4 is shown in the semiconductor device is used for the mobile telephone of the LSI, and, for example, comprises two processor unit CPU1 and CPU2, application unit APPU, memory MEMU, baseband unit BBU, and input/output unit IOU. Figure 1 configuration example shown can be applied to the memory MEMU in these cells.

The processor unit CPU1 and CPU2 based on program executes a predetermined algorithm processing. Application unit APPU implementation of the mobile telephone the required predetermined application processing. The baseband unit with wireless communication of the implementation of the BBU predetermined baseband processing. The input/output unit IOU as an external input/output interface function. The memory MEMU to deal with all the circuit modules of this way of handling the appropriate access. For example, in SOC such as such as in the semiconductor device, in many cases, the use of known as storage IP (Intellectual property) in the design data, such as through the automation of known as the memory compiler design tool implementing memory MEMU. Usually, because when the stored IP does not at the same time optimal operation sequence are also different, the need for each memory IP the new development of a timing adjustment circuit TMCTLB. However, from the perspective of improving the design efficiency, the ideal is to achieve a storage IP common available timing adjustment circuit.

"The timing adjusting circuit (column direction) of a specific circuit (1)"

Figure 5 is the wiring diagram of graphical representation chart 1 as shown in the timing adjustment circuit of the memory MEMU (column direction) of the configuration examples. Figure 5 as shown in the timing adjustment circuit TMCTLBn 1 includes a plurality of (here, 6 a) of the inverter circuit IV1 - IV6, dummy bit line DBL1 two and DBL2, a load circuit in the column direction and x CLBn - CLBn. Here, dummy bit line DBL1 and DBL2 are respectively provided with the memory array in the BL MARY each line is substantially equal to the length of, and along with the memory array MARY in the extending direction of the bit line BL (Y direction) in the same direction extending in parallel arrangement. The inverter circuit IV1 - IV6 is a CMOS inverter circuit, the inverter circuit configuration has a PMOS transistor and the NMOS transistor, each of the inverter circuit in the power supply voltage VCC and ground power supply coupled between the voltage VSS.

The inverter circuit IV1 and IV2 are respectively arranged in the dummy bit line DBL1 at input terminal of. The inverter circuit IV1 input the above-mentioned decoding activation signal TDEC, inverter circuit IV2 input inverter circuit IV1 the output signal of the inverse of the signal output to the dummy bit line DBL1 input terminal. The inverter circuit IV3 and IV4 are respectively arranged in the dummy bit line DBL1 of dummy bit line DBL2 output terminal and the input terminal. The inverter circuit IV3 dummy bit line DBL1 input from the output terminal of the signal, the inverter circuit IV4 IV3 input inverter circuit the output signal of the inverse of the signal output to the dummy bit line DBL2 input terminal. The inverter circuit IV5 and IV6 are respectively arranged in the dummy bit line DBL2 output terminal. The inverter circuit IV5 input from the dummy bit line DBL2 output terminal of the signal, the inverter circuit IV6 input inverter circuit IV5 output signal, and output the dummy bit line signal SDBL. In this manner, dummy bit line DBL1 and DBL2 in close to the memory array of a timing adjustment circuit arranged MARY TMCTLBn 1 formed in the region of the two-way wiring. For here in the case of bi-directional wiring, to the dummy bit line DBL1 external wiring is, return to the dummy wiring is a bit line DBL2.

The column direction load circuit CLBn - CLBn in each of the load circuit includes a plurality of (here, four) MNa1 - MNa4 NMOS transistor, the source electrode and the drain electrode sequentially coupled in series, the gate jointly coupled to the ground power supply voltage VSS. X in the column direction as a part of the load circuit (for example, half) of each of the column direction of the load circuit CLBn - CLBn in, NMOS transistor MNa2 and MNa3 source and the drain of the dummy bit line DBL1 coupled to, the NMOS transistor MNa1 and MNa4 one of the source/drain of the (not with the NMOS transistor MNa2 and MNa3 sharing a side) is disconnected. X in the column direction as a load circuit and another part (for example, the other half) of each of the column direction of the load circuit CLBn [q + 1] - CLBn in, NMOS transistor MNa2 and MNa3 of the source and drain is coupled to the dummy bit line DBL2, the NMOS transistor MNa1 and MNa4 one of the source/drain (not with the NMOS transistor MNa2 and MNa3 sharing a side) is disconnected.

Figure 6 is the wiring diagram of picture shows through to Figure 5 shown in the improvement of the timing adjustment circuit of the obtained timing adjustment circuit (a column direction) configuration examples. Figure 6 shown TMCTLBp 1 of a timing adjustment circuit configured to: the map 5 shown in the column direction of a load circuit x CLBn - CLBn replacement of Figure 6 shown in a load circuit in the column direction x CLBp - CLBp. The column direction load circuit CLBp - CLBp in each of the configured to: will include in each column direction load circuit CLBn - CLBn in a plurality of (here, four) NMOS transistor MNa1 - MNa4 is replaced with a plurality of (here, four) PMOS transistor MPa1 - MPa4. With the NMOS transistor MNa1 - MNa4 different, PMOS transistor MPa1 - MPa4 has jointly coupled to the power supply voltage to the gate of the VCC.

Figure 5 and Figure 6 shown in the column direction of the load circuit CLBn - CLBn and CLBp - CLBp play a dummy bit line DBL1 and DBL2 the load capacitance of the role. In particular, because each of the column direction of the load circuit in the NMOS transistor MNa1 - MNa4 (or PMOS transistor MPa1 - MPa4) is driven to the cut-off state, to form the NMOS transistor MNa2 and MNa3 (or PMOS transistor MPa2 and MPa3) of the source and drain diffusion layer of the dummy bit line DBL1 capacitance into and DBL2 the load capacitance of the. Therefore, inverter circuit IV2 output signals of the load circuit with the column direction CLBn - CLBn (or CLBp - CLBp) generated with the load capacitance of the dummy bit line DBL1 and parasitic resistance and parasitic capacitance corresponding to the transmission after a delay to the phase inverter circuit IV3. Similarly, the inverter circuit IV4 with the output signal of the column direction in the load circuit CLBn [q + 1] - CLBn (or CLBp [q + 1] - CLBp) generated by the load capacitance of the dummy bit line DBL2 and parasitic resistance and parasitic capacitance corresponding to the transmission after a delay to the phase inverter circuit IV5. Thus, through delay decoding activation signal to obtain a dummy bit line signal TDEC SDBL. More strictly speaking, comprising setting the inverter circuit IV1 - IV6 logic threshold, including the driving ability of the delay time of the impact.

"The timing adjusting circuit (column direction) of the specific layout configuration (1)"

Figure 7 is the top view of graphical representation chart 5 and Figure 6 is shown a timing adjustment circuit of the load circuit in the column direction of the specific layout configuration examples. Figure 8 (a) is shown basiscopic 7 shown A - A 'line of cutaway view of the embodiment of the structure, Figure 8 (b) is shown basiscopic 7 shown B - B' line of cutaway view of the embodiment of the structure. As shown in Figure 7 and Figure 8, the timing adjusting circuit TMCTLBn (TMCTLBp) comprises a trap WEL, in the trap WEL DF formed in the diffusion layer, in the trap WEL with is interposed is formed over the gate insulating film of the polycrystalline silicon layer GS PO, 1st are sequentially formed in the upper layer of the metal wiring layer M1 and 2nd the metal wiring layer M2, the interlayer insulating layer ISL2 set in the contact layer in the contact point of the CT, and the interlayer insulating layer ISL2 passes the level set up in the through hole of the V1. Contact established CT 1st the metal wiring layer M1 and the polycrystalline silicon layer between the PO coupling, and 1st the metal wiring layer M1 and diffusion between the DF coupling. passes the level V1 has established a 1st the metal wiring layer M1 and 2nd the metal wiring layer M2 of the coupling between the.

In fig. 7 in, by the 2nd the metal wiring layer M2 formed dummy bit line DBL1 two and DBL2 along the Y direction (the extending direction of the bit lines) and row extends. The polycrystalline silicon layer formed by the PO 8 gate wiring along the X direction (the extending direction of the word line) and row extends. The column direction CLBn load circuit (or CLBp) in the eight gate wiring device to the four dummy bit line DBL1 gate wiring and of the intersecting portion is formed. The column direction CLBn load circuit (or CLBp) also in the four gate wiring and the dummy bit line DBL2 of the intersecting portion is formed. The column direction CLBn load circuit (or CLBp) respectively in the remaining four gate wiring and the dummy bit line DBL1 of the intersecting portion and the four gate wiring and the dummy bit line DB2L of the intersecting portion is formed. In each of the column direction in the load circuit, the source or drain diffusion layer become DF arranged in the above-mentioned four gate wiring of each of the two sides. Through the use of diffusion layer DF, the NMOS transistor MNa1 - MNa4 (or PMOS transistor MPa1 - MPa4) in the Y direction are sequentially formed.

A column direction included in the load circuit comprising the other diffusion layer DF with a load circuit in the column direction of the space between the diffusion layer DF through Figure 8 (b) is shown separated from the insulating layer of the ISL. Therefore, Figure 5 and Figure 7 in the embodiment, each of the two ends of the load circuit in the column direction of the source electrode or the drain electrode (transistor MNa1 (or MPa1) and transistor MNa4 (or MPa4) of the source or drain) is kept off, so as to prevent the insulating layer from ISL reflect the dummy bit line to capacitance of the load capacitance of the in. By ISL through the insulating layer of the plurality of diffusion layers DF separated form the area is called as the element active region, and so on. Figure 7 shown in the configuration example, are respectively arranged in the column direction with the four load circuit corresponding to the four elements of the active area.

Here, used as the NMOS transistor MNa2 and MNa3 (or PMOS transistor MPa2 and MPa3) of the source and the drain of the plurality of diffusion layers DF first of all through the contact layer coupled to the CT are respectively arranged between each of the diffusion layer and the upper layer of the DF 1st the metal wiring layer M1 in the wiring, then through passes the level V1 coupled to the corresponding dummy bit line (DBL1 or DBL2). The polycrystalline silicon layer is formed by PO eight gate wiring via the contact layer by the 1st CT jointly coupled to the metal wiring layer M1 formed extending along the Y direction of the grid bias wiring VGL. When the timing adjustment circuit has by fig. 5 shown in a NMOS transistor in the column direction of the load circuit of a timing adjustment circuit CLBn when TMCTLBn, trap WEL is p-type, n-type diffusion layer is DF, to the gate bias voltage applied to the power supply wiring VGL ground voltage VSS. On the other hand, when the timing adjustment circuit has by fig. 6 shown in a PMOS transistor in the column direction of the load circuit of a timing adjustment circuit CLBp when TMCTLBp, trap WEL is n-type, the diffusion layer is DF p type, the gate bias voltage to the supply voltage is applied wiring VGL VCC.

Figure 9 is the top view of graphical representation chart 1 shows the word and line by the driving circuit, the timing adjusting circuit (a column direction) and a part of the memory array of the layout configuration of the embodiment of the SUMMARY comparison. For example, a word line driving circuit WD, a timing adjustment circuit MARY TMCTLB and memory array through the map 9 shown in the repeating unit of the equi-spaced, along the Y direction order of the repeating manner arranged for distribution. In this, in the timing adjustment circuit TMCTLB of the load circuit in the column direction, forms the above-mentioned MOS transistor of each of the gate wiring (polycrystalline silicon layer PO) gate length L2 than MARY forming memory arrays in each memory cell of each MOS transistor gate length of L3 long. Although not shown, for example, forming a timing adjustment circuit in the TMCTLB each inverter circuit (IV1 - IV6) of a gate length of the MOS transistor of each memory cell than a gate length of L3 long.

Moreover, although not specifically limited, the gate length L2 than forming a word line driving circuit WD of the gate length of the MOS transistor L1 long. Usually, a word line driving circuit of the MOS transistor need WD large drive capability in order to drive the word line; therefore, in many cases the coverage gate length is designed to be short. For example, the memory array of the MOS transistor in the MARY based on usually applied to the storage unit of the memory cell layout design rules. To form a word line driving circuit of the MOS transistor based on the WD for logic circuit (all as shown in Figure 4 the base band unit BBU and application unit such as APPU logic circuit) the design of the logic layout rules. In such a case, a timing adjustment circuit of the MOS transistor TMCTLB may also be based on the design of the logic layout rules.

Figure 10 (a) and Figure 10 (b) are respectively is the illustrative diagram of the 5 and Figure 6 in the configuration example of the timing adjustment circuit and the relationship between the top view of the memory size of the array. As mentioned above, the timing adjusting circuit TMCTLB in the length of the each dummy bit line is designed to be included in the memory array with a bit line in a MARY have substantially equal lengths. Therefore, as shown in Figure 10 (a) and Figure 10 (b) as shown in the, Y direction on the size of the timing adjustment circuit TMCTLB can also be included in the memory array with the MARY (Figure 10 (a) in the case of p line, and Figure 10 (b) in the case of the r (r<p) line) in a change in the number of word line WL.

Figure 11 (a) and Figure 11 (b) is graphical representation chart 5 shown the timing adjusting circuit and Figure 6 is shown a timing adjustment circuit of the significant difference of the embodiment of the interpretative with photos. Figure 11 (a) and Figure 11 (b) graphically shows the periphery of the memory array MARY SUMMARY layout configuration examples. In this embodiment, close to the memory array MARY as a reference, the timing adjusting circuit TMCTLB and a word line driving circuit WD in the X direction are arranged in the order, the input/output circuit module in the Y direction IOBK continuously arranged. The control circuit module CTLBK arranged along the Y direction in the timing adjustment circuit TMCTLB and a word line driving circuit WD adjacent along the X direction and the input/output circuit block in regions adjacent to the IOBK. For example, the input/output circuit module IOBK corresponding to Figure 1 as shown in the column select circuit YSW, write drive circuit WTD, sense amplifier circuit SA, input/output buffer circuit such as the IOB, control circuit module CTLBK corresponding to Figure 1 as shown in the address control circuit ADRCTL, read/write control circuit RWCTL and the like.

In fig. 11 (a) word line driving circuit shown in the WD, close to the timing adjustment circuit formed TMCTLB p-type trap WEL_P, deviate from the timing adjustment circuit to form n-type well WEL_N TMCTLB, the n-type well WEL_N clamp can absorb almost the p-type trap WEL_P. In the memory array in the MARY, close to the timing adjustment circuit to form n-type well WEL_N TMCTLB, deviate from the timing adjustment circuit formed TMCTLB WEL_P p-type well, the p-type trap WEL_P type trap with said n WEL_N. In such a case, regardless of the n-type well the WEL_N or p-type trap WEL_P in which one of the timing adjustment circuit as a trap of the TMCTLB, almost no difference in area efficiency. Therefore, in this case, Figure 5 configuration examples and shown in Figure 6 is shown in the configuration example will not produce the obvious differences.

On the other hand, in fig. 11 (b) word line driving circuit shown in the WD, close to the timing adjustment circuit formed TMCTLB p-type trap WEL_P, deviate from the timing adjustment circuit to form n-type well WEL_N TMCTLB, the n-type well with said WEL_N of WEL_P p-type trap. In the memory array in the MARY, close to the timing adjustment circuit formed TMCTLB p-type trap WEL_P, deviate from the timing adjustment circuit to form n-type well WEL_N TMCTLB, the n-type well with said WEL_N WEL_P p-type trap. In such a case, when adopting the p-type trap WEL_P as a timing adjustment circuit of the TMCTLB when pitfall, the WEL_P p-type trap can be connected with a word line driving circuit of the WD p-type trap WEL_P and memory array of MARY p-type trap WEL_P integrally formed. Therefore, with the n-type well WEL_N as compared with a case, can be realized with relatively small area. For the purposes of this point, uses the chart 5 shown (NMOS transistor) configuration examples than in Figure 6 is shown (PMOS transistor) configuration example of the variable more beneficial.

"Embodiment 1 of the main effect of the"

In this connection, the following effects (1) - (8) primarily by adopting according to the embodiment of the invention 1 by the configuration of the semiconductor device obtained. Independent understanding of various configurations are possible; therefore, preferably independent of adopting and producing the effect (1) - (8) every configuration, or by some combination of them.

(1) according to the embodiment of the invention 1 comprising the semiconductor device in the timing adjustment circuit of the transistor gate voltage clamp-in: by adopting the timing adjustment circuit, can reduce the sequential operation (usually the starting timing of the sense amplifier) of the change. One of the reasons is that: the amount of delay is through the use of the column direction of the load circuit is arranged to, rather than through the virtual method of storage unit is set, the virtual storage unit method employs the use of having a memory unit of the electrical performance of the electrical performance of the similar virtual memory unit. In virtual storage unit in the method of, for example, is configured to fixed information stored in the first plurality of virtual storage unit is coupled to the dummy bit line, and at least one virtual storage unit in response to the word line (or dummy word line) to the activation of the driving the dummy bit line. The starting timing of the sense amplifier by the virtual storage unit driven by the timing of the dummy bit line is provided. However, in the storage unit, with the geometric construction of the more fine or capacity increase, process variation (the voltage change and temperature change, according to the examples may be) more easily. Thus, each virtual memory unit also easy to process variations, the virtual storage unit reflect the memory unit of the configuration. When the virtual storage appeared in the process changes, the dummy bit line drive timing for each virtual memory unit is different for, thus, may in a sense amplifier of the start timing of the change.

On the other hand, in the adoption of the column direction in the method of the load circuit, the gate of the MOS transistor is not like the virtual storage unit as in the method of dynamic drive, instead of the MOS transistor keeps the gate at a fixed value of the cut-off level. Therefore, fixed in advance to the dummy bit line load capacitance adds to states, and the readout amplifier the starting timing of the main through the load capacitance of the order of determination. The load capacitance variation depends primarily on the Figure 7 shown in the total area of the diffusion layer DF change, and it is easy to do than the above-mentioned virtual storage unit of the dummy bit line driving timing variation (in other words, dummy memory cell the current drive capability of the variable quantity of) small. Therefore, the reduction of the driving timing of the sense amplifier changes become possible.

(2) according to the embodiment of the invention 1 comprising the semiconductor device in the timing adjustment circuit in the length of the gate electrode of the transistor: by adopting the timing adjustment circuit, reduce the amount of the operation sequence of the (usually the starting timing of the sense amplifier) of the change and become possible. Another reason is that: as shown in Figure 9, load circuit formed by the column direction of the gate length of the MOS transistor design than the storage unit in a MOS transistor of the long gate length. When the gate length of the relatively long design, the area of the source electrode and the drain to be designed to be relatively large. In the semiconductor production process, usually, the smaller the size of the process, the more easy to process changes. When the gate length is shortened, the size of the more easy to change. Therefore, the column direction generated by the load capacitance of the load circuit can be changed by the value of the grid to reduce the length of the longer design. In addition, for forming the timing adjustment circuit of the inverter circuit (Figure 5 shown IV1 - IV6 and the like) for the purposes, from the change of the threshold of reduction logic point of view, the ideal is to make the MOS transistor than a gate length of the MOS transistor in the memory cell gate length of all long.

(3) according to the embodiment of the invention 1 of the semiconductor device will be included in the load circuit to the outward direction of the distribution of the wiring and the return to the wiring arrangement in: by adopting the timing adjustment circuit, reduce the amount of the operation sequence of the (usually the starting timing of the sense amplifier) of the change and become possible. Another reason is that: the row direction of the arrangement of the distribution to the load circuit to the external wiring and the return in the wiring. For example, as shown in Figure 5, to dummy bit line is distributed to the outer wiring (DBL1) and return to the wiring (DBL2), and a plurality of the column direction of the load circuit is disposed on a dummy bit line DBL1 and DBL2 in.

If the column direction are arranged in the load circuit on to the outer wiring and return to one side of the wiring, so when the wiring on the other side of the structure of the transistor when a change occurs, the wiring side of the can will seriously affect the variability of the delay. In contrast, by the distribution of the load circuit to the column direction to the external wiring and the return to the wiring can reduce the wiring on one side of the impact of changes in.

(4) according to the embodiment of the invention 1 of the wiring of the semiconductor device in the column direction of the load circuit in the distributed arrangement of the: by adopting the timing adjustment circuit, reduce the amount of the operation sequence of the (usually the starting timing of the sense amplifier) of the change and become possible. Another reason is that: the load circuit in the column direction the distributed arrangement of the Y direction. For example, in fig. 5 in, when row direction of the load circuit when the length of the Y direction variable, especially since the memory array MARY increase when the capacity of the variable-length, process variations can be with the Y direction such as the position of the occurrence of the change. Therefore, in fig. 5 in, the dummy bit line DBL1 in dummy bit line DBL2 and in, a plurality of the column direction on the load circuit in the Y direction of the distributed arrangement. Specifically, the column direction load circuit configuration is in the Y direction of the plurality of MOS transistor distribution. Process changes and other by adopting the distributed arrangement can be averaged on the whole.

(5) according to the embodiment of the invention 1 of the inverter circuit of the semiconductor device in the arrangement: through the inverter circuit are respectively distributed arrangement of the dummy bit line DBL1 in input terminal, dummy bit line DBL1 output terminal (dummy bit line DBL2 input terminal) and the dummy bit line DBL2 in the output terminal, each of the inverter circuit and a logic threshold value of the variations can be averaged, as the above-mentioned effects (4).

(6) according to the embodiment of the invention 1 with the bit line of the semiconductor device corresponding to the length of the dummy bit line in the implementation of: by adopting the timing adjustment circuit, corresponding to the number of the word (bit line length) the optimal set the starting timing of the sense amplifier is possible. For example when the word line number (bit line length) with the storage capacity of a memory value changes, such as the parasitic capacitance of the bit line will be correspondingly change. Therefore, the read amplifier of the optimum starting sequence will also be different. Therefore, reference view 10 stated, the influence of the parasitic capacitance of the bit line by the word line in accordance with the number (bit line length) and change the length of the dummy bit line is reflected. Therefore, the number of to have different bit line (the bit line length) of the sense amplifier of the memory the optimum starting timing of set become possible.

(7) according to the embodiment of the invention 1 comprising in a semiconductor device of the timing adjustment circuit of the transistor layout: by adopting the timing adjustment circuit, so that when starting and sets the read amplifier of the priorities to easily perform timing adjustment is possible, but does not need to consider the type of the memory unit. For example, in the above-mentioned virtual storage unit in the method of, because when the storage unit types change virtual storage unit of the configuration will also change, the need for each storage unit of the new development of a timing adjustment circuit. On the other hand, Figure 5 is shown in the timing adjustment circuit or other timing adjusting circuit can be used together, but does not need to consider the type of the memory unit. Specifically, when the storage unit when the kind of the change, only the consideration of the worst situation (usually, is located on the word line of the end portion and the states the position line nose of the access time of the memory cell), only the proper adjustment of the column direction of the load circuit can be the load capacitance value of the capacitance. In this case, for example, does not need to change Figure 7 shown in the layout of its basic configuration, only the appropriate selection of whether to provide passes the level V1 (dummy bit line with the form of the column direction of the load circuit of each MOS transistor source and the drain of the coupling part between the). Therefore, adjustment is very simple.

(8) in the logic cloth drafting compass according to the embodiment of the invention 1 of the timing adjustment circuit of the semiconductor device in the application of the: by adopting the timing adjustment circuit, the arrangement of the layout in the elimination of restrictions become possible. For example, in the above-mentioned virtual storage unit in the method, the timing adjusting circuit through the memory cell layout rules design; therefore, it will be necessary for the timing adjustment circuit is disposed in the memory array (or in the vicinity of the memory array). On the other hand, Figure 5 is shown in the timing adjustment circuit or other timing adjustment circuit through the logic layout rules design. Therefore, does not have to be arranged in the timing adjustment circuit in the memory array (or in the vicinity of the memory array). Therefore, according to this example to make effective use of the area becomes possible, thereby realizing the small area of the semiconductor device.

"Embodiment 1 of various improved embodiment"

Embodiment 1 described in the various configurations of the embodiment are not limited to them, and can be within the range not to depart from the thrust of the natural to make various changes. For example, if the change is averaged from the above point of view, to allow an increase in the circuit area, so not only can be the dummy bit line is arranged as shown in Figure 5 two-way wiring, can also be provided with a plurality of bi-directional wiring. Figure 5 and the other in the Figure, in the column direction load circuit is arranged in the dummy bit line DBL1 two DBL2 and each of a plurality of dummy bit lines. However, according to the situation, the direction of the columns can also be arranged in the load circuit only a dummy bit line. However, from the above point of change is averaged, the ideal is to load circuit is arranged in the column direction of the two dummy bit lines, more ideal is the column direction of the load circuit are equally arranged in the two dummy bit lines. In addition, in fig. 5 and the other in the Figure, from the above changes in the angle of the average emulsion, inverter circuit IV3 and IV4 is set up in the turning point of the dummy bit line. However, according to the situation also may omit the inverter circuit. In Figure 5 and the other in the Figure, each of the inverter circuit is set up as a part of the two-stage configuration (for example, IV1 and IV2). However, it may also be appropriate to change the progression. In this case, the dummy bit line DBL1 from of the dummy bit line DBL2 delay time and the delay time is equal to the angle of as far as possible, the ideal is to make the dummy bit line DBL1 with the polarity of the signal of the dummy bit line DBL2 polarity of the signal of the same. However, according to the situation may also be provided in different polarity.

Embodiment 2

"The timing adjusting circuit (column direction) of the specific circuit (2)"

Figure 12 is the wiring diagram of graphic according to the embodiment of the invention 2 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration examples. Fig. 12 illustrated the timing adjusting circuit TMCTLBn 2 Figure 5 illustrated the timing adjusting circuit TMCTLBn 1 improved embodiment. Figure 12 shows the configuration of the embodiment with the Figure 5 shows the configuration of the embodiment is different in that: all the column direction contained in the load circuit CLBn - CLBn of the NMOS transistor in the MNa1 - MNa4 jointly coupled to the grid of the power supply voltage VCC.

Figure 13 is the wiring diagram of graphic according to the embodiment of the invention 2 comprising in a semiconductor device the timing adjusting circuit (a column direction) another configuration example. Figure 13 illustrated a timing adjustment circuit TMCTLBp 2 Figure 6 illustrated a timing adjustment circuit TMCTLBp 1 improved embodiment. Figure 13 shows the configuration of the embodiment and Figure 6 shows the configuration of the embodiment is different in that: all the column direction contained in the load circuit CLBp - CLBp in PMOS transistor MPa1 - MPa4 of gate common coupled to ground power supply voltage VSS.

When adopting the Figure 12 and Figure 13 shown in the column direction of the load circuit CLBn - CLBn and CLBp - CLBp when, with the above-mentioned Figure 5 and Figure 6 unlike in the case of, the gate insulating film capacitance of the dummy bit line DBL1 will serve as and DBL2 the load capacitance of the join. In other words, because the MOS transistor MNa1 - MNa4 (MPa1 - MPa4) drive to the on state, in the column direction of the load circuit MOS transistor MNa1 - MNa4 (MPa1 - MPa4) of the gate insulating film capacitance and a MOS transistor MNa2 and MNa3 (MPa2 and MPa3) a source and a drain diffusion layer of the capacitor is added to the dummy bit line DBL1 and DBL2. Usually, the gate insulating film the capacity of the capacitance value is less than the diffusion layer capacity value is large, for example, when the need for a relatively large load capacitance, or when it is desired that the number of the load circuit in the column direction to reduce to a certain degree, by adopting the above configuration examples become useful.

When adopting the Figure 12 and Figure 13 shown in the configuration example, can adopt the Figure 7 illustrated layout configuration examples. In fig. 12 of the case, the power supply voltage applied to the gate bias voltage wiring VGL VCC, Figure 13 of the case, the ground power supply voltage VSS is applied to the gate bias voltage wiring VGL. When the through the gate insulating film capacitance to adjust the dummy bit line to be joined in the load capacitance, only the appropriate selection of whether to set the contact layer for CT coupling chart 7 in grid bias wiring VGL and gate wiring (polycrystalline silicon layer PO). Here it can be easy to control. Can also adopt the Figure 12 (Figure 13) in the configuration of the embodiment and Figure 5 (Figure 6) in the examples of the configuration of the appropriate combination. In other words, for example, can be applied to the power supply voltage VCC to Figure 12 and Figure 5 in the column direction of the load circuit CLBn of the MOS transistor, and the ground power supply voltage VSS is applied to the load circuit in the column direction of the MOS transistor CLBn. In this case, in fig. 7 illustrated in the layout configuration examples, only needs to set up two grid bias wiring VGL (one for VCC, one for VSS) and only need via the contact CT to the grid bias wiring VGL these in a gate electrode of the bias wiring VGL is coupled to the gate wiring.

Figure 14 (a), fig. 14 (b) and Figure 14 (c) is graphical representation chart 12 shows the row direction by the load in the load circuit capacitance complementary with photos. Figure 14 (a) and Figure 14 (b) is a representation of the position of the load capacitance schematic view, Figure 14 (c) for shows and Figure 14 (a) and Figure 14 (b) corresponding to the load capacitance of the voltage waveform of the SUMMARY of the embodiment Figure. Figure 14 (a) and Figure 14 (b) graphically shows the load circuit in the column direction of the NMOS transistor MNa1 - MNa4 the profile structure of the embodiment. Figure 14 (a) and Figure 14 (b) in, the gate wiring in the GT p - type well formed on the WEL_P, wherein the gate insulating film, is used as a source electrode and a drain electrode of the n - type diffusion layer DF_N in p - type well WEL_P GT in the two sides of the gate wiring is formed.

Figure 14 (a) shows the ground power supply voltage VSS is applied to the gate wiring in the case of the GT, the embodiment corresponding to fig. 5 in the case of the shown. In this example, channel not in the NMOS transistor is formed below the gate, through the coupling to the diffusion layer is used as a source and the drain of the dummy bit line DF_N (here DBL1) it can be seen that in the diffusion layer DF_N and p - type well between the WEL_P diffusion layer capacitance (junction capacitance pn) Csb (or Cdb). Figure 14 (b) shows the power supply voltage applied to the gate wiring of the VCC GT situation, the embodiment corresponding to Figure 12 shown case. In this example, the channel of the NMOS transistor in the NCH formed below the gate. Therefore, for example, through the coupling to the diffusion layer is used as a source of the dummy bit line DBL1 DF_N of DF_N it can be seen that the diffusion layer (source) and p - type well diffusion layer capacitance between the WEL_P Csb, in addition, also it can be seen that the gate insulating film capacitance Cg, channel NCH and p - type well WEL_P pn junction capacitance between the DF_N Ccb and diffusion layer (drain) and p - type well diffusion layer capacitance between the WEL_P Cdb. The gate insulating film capacitance Cg as grid - source capacitance Csg and grid - the sum of the drain capacitance Cdg.

Therefore, when the dummy bit line DBL1 from "high" to "low" level conversion level, the kind of along with load capacitance change of as shown in Figure 14 (c) shows the delay (the change of the waveform of the pot). First, fig. 14 (a) of the cases, the dummy bit line DBL1 load capacitance value of the parasitic capacitance Cdbl1 diffusion layer capacity Csb (or Cdb) and obtained the of, referred to as "Cdbl1 + Csb (Cdb)". Therefore, as shown in Figure 14 (c) is shown, with only by the parasitic capacitance Cdbl1 obtained compared with a case where the load capacitance of the, dummy bit line DBL1 voltage waveform shown a more gentle change. Secondly, Figure 14 (b) of the cases, the load capacitor is the sum of the value of the derived of "Cdbl1 + Csb + Cdb + Ccb + Cg". Therefore, as shown in Figure 14 (c) is shown, and Figure 14 (a) as compared with a case, dummy bit line DBL1 voltage waveform shown much more gently changes. However, dummy bit line DBL1 voltage waveform than the Figure 14 (a) is close to a certain voltage level in the case of the shown much more gently change, because, in the dummy bit line DBL1 voltage conversion during the, channel NCH (is Cdb + Ccb + Cg) dummy bit line DBL1 is not in the voltage level close to a certain degree of "high" level during a.

Figure 15 (a), fig. 15 (b) and Figure 15 (c) is graphical representation chart 13 shows the row direction the load circuit of the load capacitance of the complementary with photos, wherein Figure 15 (a) and Figure 15 (b) is a representation of the schematic view of the position of the load capacitor, Figure 15 (c) is SUMMARY shows and Figure 15 (a) and Figure 15 (b) corresponding to the load capacitance of the voltage waveform of the example of the Figure. Figure 15 (a) and Figure 15 (b) graphically shows the load circuit in the column direction PMOS transistor MPa1 - MPa4 the profile structure of the embodiment. Figure 15 (a) and Figure 15 (b) in, the gate wiring GT in the n - type well formed on the WEL_N, wherein the gate insulating film, and is used as a source electrode and a drain electrode of the DF_P p - type diffusion layer in the n - type well WEL_N GT in the two sides of the gate wiring is formed.

Figure 15 (a) shows the power supply voltage applied to the gate wiring of the VCC GT situation, the embodiment corresponding to Figure 6 in the case of the shown. In this example, channel not in the PMOS transistor is formed below the gate, through the coupling to the diffusion layer is used as a source or drain of the dummy bit line DF_P (here DBL1) it can be seen that the diffusion layer in the n - type well WEL_N DF_P and diffusion layer between the capacitor (pn junction capacitance) Csb (or Cdb). Figure 15 (b) shows the ground power supply voltage VSS is applied to the gate wiring in the case of the GT, the embodiment corresponding to Figure 13 shown in the case of the. In this example, channel PCH in the gate of the PMOS transistor is formed. Therefore, for example, through the coupling to the diffusion layer is used as a source of the dummy bit line DBL1 DF_P of DF_P it can be seen that the diffusion layer (source) and n - type well diffusion layer capacitance between the WEL_N Csb, in addition, also it can be seen that the gate insulating film capacitance Cg, channel PCH and n - type well WEL_N pn junction capacitance between the DF_P Ccb and diffusion layer (drain) and n - type well diffusion layer capacitance between the WEL_N Cdb. The gate insulating film capacitance Cg as grid - source capacitance Csg and grid - the sum of the drain capacitance Cdg.

Therefore, when the dummy bit line DBL1 from "high" to "low" level conversion level, as shown in Figure 15 (c) shows the delay (waveform of the gentle change) along with the load capacitance of the types of temperature change. First of all, fig. 15 (a) of the cases, the dummy bit line DBL1 load capacitance value of the parasitic capacitance Cdbl1 diffusion layer capacity Csb (or Cdb) and obtained the of, referred to as "Cdbl1 + Csb (Cdb)". Therefore, as shown in Figure 15 (c) is shown, with only by the parasitic capacitance Cdbl1 obtained compared with a case where the load capacitance of the, dummy bit line DBL1 the voltage waveform of the more gentle change. Secondly, fig. 15 (b) of the cases, the load capacitor is the sum of the value of the derived of "Cdbl1 + Csb + Cdb + Ccb + Cg". Therefore, as shown in Figure 15 (c) is shown, and Figure 15 (a) as compared with a case, dummy bit line DBL1 voltage waveform shown much more gently changes. However, in close proximity to the specific voltage level condition, dummy bit line DBL1 show the voltage waveform from the very gentle change to Figure 15 (a) in the case of observation under less gentle change, because, in the dummy bit line DBL1 voltage conversion period, channel PCH (is Cdb + Ccb + Cg) in the dummy bit line DBL1 voltage level close to a certain degree of "low" level period of the disappeared.

In this way, when the load circuit in the column direction (the column direction load circuit using the gate insulating film capacitance as a load capacitor) when, how to see that the load capacitor with the dummy bit line DBL1 voltage level conversion direction and the column direction of the MOS transistor of the load circuit of a combination of different conductivity type. For example, the NMOS transistor, dummy bit line DBL1 from the voltage level of the "high" to "low" level conversion level, the gate insulating film capacitance at an early stage can not be seen, however, from "low" to "high" level conversion level, the gate insulating film capacitance can be seen at an early stage. On the contrary, the PMOS transistor, dummy bit line DBL1 voltage level from "high" to "low" level conversion level, the gate insulating film capacitance at an early stage can be seen, however, from "low" to "high" level conversion level, the gate insulating film capacitance can be seen at an early stage. Usually, more ideal is to adopt the wherein the gate insulating film capacitance in the conversion of the combination of the early can be seen.

As mentioned above, for example, through the use of the embodiment of the invention 2 of the semiconductor device, can be easy to support or even demand in the case of large load capacitance value. The embodiment of the invention 2 in, the PMOS transistor or the NMOS transistor in the column direction as any one of the load circuit. However, with the situation can also be configured to adopt the two. In other words, n - p - trap and trap are formed in the timing adjustment circuit, the load circuit in a row direction and a portion of the NMOS transistor is configured, the remaining part of the PMOS transistor is disposed. In this case, although the circuit area can be increased, but in the dummy bit line voltage level in the conversion process, on how to see the gate insulating film capacitance the extent of equalization is possible.

Embodiment 3

"The timing adjusting circuit (column direction) of the specific circuit (3)"

Figure 16 (a) is a graphical representation according to the embodiment of the invention 3 comprising in a semiconductor device the timing adjusting circuit (column direction) of the embodiment of the configuration of the wiring diagram, Figure 16 (b) Figure 16 (a) complementary with photos. Figure 16 (a) of a timing adjustment circuit shown TMCTLB 3 Figure 5 shown TMCTLBn 1 of a timing adjustment circuit of the improved embodiment. Figure 16 (a) of a timing adjustment circuit shown TMCTLB 3 with Figure 5 of a timing adjustment circuit shown TMCTLBn 1 the difference lies in that, in the load circuit changes the direction of the column direction into a variable load circuit VCLBn - VCLBn.

The variable column direction load circuit VCLBn - VCLBn is set as shown in Figure 5 as in the case of NMOS transistor MNa1 - MNa4; however, not privately 5 as in the case of in, NMOS transistor MNa1 - MNa4 of each gate voltage can be properly set. Therefore, Figure 16 (a) in, is also provided with a includes a latch circuit including LTa and LTb CLCTL the load capacitance of the setting circuit. In this configuration, the latch circuit latch LTa independent input load capacitance of the Sa to set up the signal, and to control the NMOS transistor MNa1 of the gate voltage, the latch circuit latch LTb independent input load capacitance of the setting signal Sb, and common control NMOS transistor MNa2 - MNa4 of the gate voltage.

In the present configuration example, as shown in Figure 16 (b) is shown, first, when the load capacitance setting signal (Sa, Sb) is set as ('1', '0') ('1: VCC level, ' 0': VSS level) when, NMOS transistor MNa1 respectively arranged as the conducting state, NMOS transistor MNa2 - MNa4 is set as the cut-off state. Therefore, the column direction of the dummy bit line DBL1 load circuit and DBL2 the load capacitance of the NMOS transistor MNa1 is mainly composed of the gate insulating film capacitance and the NMOS transistor MNa1 - MNa3 of the source and drain diffusion layer of the capacitor from the sum. Secondly, when the load capacitance setting signal (Sa, Sb) is set as ('0', '0') when, NMOS transistor MNa1 - MNa4 is set as the cut-off state. Therefore, the column direction of the dummy bit line DBL1 load circuit and DBL2 the load capacitance of the NMOS transistor by MNa2 and MNa3 of the source and drain diffusion layer of the capacitor from the sum. In this example, because the load capacitance setting signal (Sa, Sb)=('1', '0') of the case (defined as in the case of standard set) compared with the, load capacitance value becomes smaller, so the starting timing of the sense amplifier is set to be earlier.

Secondly, when the load capacitance setting signal (Sa, Sb) is set as ('0', '1') when, NMOS transistor MNa1 respectively is set to the stop state, NMOS transistor MNa2 - MNa4 is set as the conducting state. Therefore, the column direction of the dummy bit line DBL1 load circuit and DBL2 the load capacitance of the NMOS transistor by MNa2 - MNa4 gate insulating film capacitance of the NMOS transistor MNa2 - MNa4 and source and drain diffusion layer capacity of that sum. In this example, because the load capacitance value with the standard settings as compared with a case becomes larger, so the starting timing of the sense amplifier is set to be relatively late. Finally, when the load capacitance setting signal (Sa, Sb) is set as ('1', '1') when, NMOS transistor MNa1 - MNa4 is set as the conducting state. Therefore, the column direction of the dummy bit line DBL1 load circuit and DBL2 the load capacitance of the NMOS transistor by MNa1 - MNa4 gate insulating film capacitance of the NMOS transistor MNa1 - MNa4 and source and drain diffusion layer capacity of that sum. In this example, because the load capacitance value with the above-mentioned load capacitance setting signal (Sa, Sb)=('0', '1') as compared with a case is still relatively large, and therefore the starting timing of the sense amplifier is still relatively late.

When the semiconductor device is assembled with a non-volatile memory storage, the load capacitance setting signal Sa and Sb information can be pre-stored in the non-volatile memory, or the information can be through the fuse (fuse) manner in permanent set up, or, when the semiconductor device is assembled with a setting mode, the information can be via the semiconductor device in the various circuit unit or via the setting mode in which the dynamic change of the external terminal. For example, when the test such as when such as SRAM memory, the existence of the Provisional desired delay of the sense amplifier activation timing of the situation. In this case, it would be desirable to be dynamically changed configuration. Figure 16 (a) in, variable set up through a MOS transistor (MNa1) and three MOS transistor (MNa2 - MNa4) combining. However, it should be understood that, the combination is not limited to this case, but can be suitably changed. However, as shown in Figure 16 (a) is shown, through different number of MOS transistor allocated to each load capacitance setting signal, so as to make the several steps (the example for the four steps) variable is set become possible, among them the load capacitance of the value of the change through the full balance.

Figure 17 (a) is a graphical representation according to the embodiment of the invention 3 comprising in a semiconductor device the timing adjusting circuit (column direction) of another configuration example of the wiring diagram, Figure 17 (b) Figure 17 (a) complementary with photos. Figure 17 (a) is shown in the timing adjustment circuit TMCTLB 4 Figure 5 shown TMCTLBn 1 of a timing adjustment circuit of the improved embodiment. Figure 17 (a) is shown in the timing adjustment circuit TMCTLB 4 with Figure 5 of a timing adjustment circuit shown TMCTLBn 1 is different in that Figure 5 is shown in the inverter circuit IV2 and IV4 become variable inverter circuit VIV2 and VIV4.

In various variable inverter circuit VIV2 and VIV4 in the configuration, the pull-up PMOS transistor MP10 in power supply voltage VCC and coupled between the output node, the pull-down NMOS transistor MN10a, MN10b and MN10c inserted in parallel into the output node and the ground power supply voltage between the VSS. PMOS transistor MP10 MN10a NMOS transistor and, MN10b and MN10c jointly coupled to the respective gate at the input node. Here, NMOS transistor MN10a, MN10b and MN10c respectively through the NMOS transistor MN11a, MN11b and MN11c (every one among them is used as a switch) is coupled to the ground power supply voltage VSS. Therefore, the stated variable inverter circuit VIV driving capacity can be turned on and off the switch proper is arranged.

Therefore, Figure 17 (a) in, is also provided with a includes a latch circuit including LTc and LTd CLCTL the load capacitance of the setting circuit. In this configuration, the latch circuit latch LTc independent input load capacitance of the setting signal and to control the NMOS transistor MN11a Sc conduction/cut-off, the latch circuit latch LTd independent input load capacitance of the setting signal Sd and control NMOS transistor MN11b conduction/cut-off. NMOS transistor MN11c applied to its gate through the power supply voltage VCC fixed to the conducting state. Here, NMOS transistor MN11a, MN11b and MN11c (every one among them is used as a switch) of current driving capability is set to the same value. The subject NMOS transistor MN10b set than the current drive capability of NMOS transistor MN10a current drive capacity is large.

In this case, as shown in Figure 17 (b) is shown, first, when the load capacitance setting signal (Sc, Sd) is set as ('1', '0') ('1': VCC level, '0': VSS level) when, NMOS transistor MN10a and effectively used as a pull-down transistor is applied to the NMOS transistor MN10c in. Secondly, when the load capacitance setting signal (Sc, Sd) is set as ('0', '0') when, the effective pull-down transistor is only NMOS transistor MN10c. Therefore, variable inverter circuit VIV of current driving capability than the variable (defined as standard settings) load capacitance setting signal (Sc, Sd)=('1', '0') under the condition of the small. Therefore, the starting timing of the sense amplifier is set up more late.

Secondly, when the load capacitance setting signal (Sc, Sd) is set as ('0', '1') when, NMOS transistor MN10b as NMOS transistor is added to effectively pull-down NMOS transistor MN10c in. Therefore, variable inverter circuit VIV the current drive capability of the above-mentioned standard set becomes smaller than the case of the current drive capability of large. Therefore, the starting timing of the sense amplifier is set to be slightly earlier. Finally, when the load capacitance setting signal (Sc, Sd) is set as ('1', '1') when, NMOS transistor MN10a and MN10b as effective pull-down transistor is added to the NMOS transistor MN10c in. Therefore, the stated variable inverter circuit the current drive capability of VIV still become than the above-mentioned load capacitor setting signal (Sc, Sd)=('0', '1') under the condition of the current drive capability of large. Therefore, the starting timing of the sense amplifier will remain set up slightly earlier. In this example, the assumption that the starting timing of the sense amplifier through the dummy bit line DBL1 to and DBL2 from "high" to "low" level conversion level set of circumstances, the states pulls the side configuration will become variable. However, when adopting the from the "low" level to the "high" level when the new, the configuration of the states pulls the side become variable can be. Naturally, the current drive capability of the variable method is not limited to fig. 17 (a) the configuration of the shown example, but may be appropriately changed.

As mentioned above, by adopting the according to the embodiment of the invention 3 of the semiconductor, thereby realizing the following configuration is possible: in the configuration in the starting timing of the sense amplifier can be through various variable setting is adjusted. For example, as mentioned above, can help to test, and can realize the change corresponding to the improvement of production and the like. As shown in Figure 12 and the other is shown in the Figure, according to the situation, can be after the production load adjusting capacitance value, but do not need to adjust Figure 7 shown in CT of the contact layer of the presence or absence, the adjustment of the said contact layer according to the memory of the CT type and the like can be in the design and production stages.

Embodiment 4

"The timing adjusting circuit (column direction) of the specific circuit (4)"

Figure 18 is the wiring diagram of graphic according to the embodiment of the invention 4 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration examples. Figure 18 is shown in the timing adjustment circuit TMCTLBn 3 Figure 5 shown TMCTLBn 1 of a timing adjustment circuit of the improved embodiment. Figure 5 graphically shows the timing adjustment circuit TMCTLBn 1 of the wiring diagram, wherein the load circuit in the column direction CLBn - CLBn the load capacitance of the value is the same. However, the load capacitance value may be need not be the same. For example, as shown in Figure 18, can make the dummy bit line DBL1 are respectively located at the output of the dummy bit line DBL2 terminal and the input terminal of the load circuit in the column direction CLBn '[q] and CLBn' [q + 1] than the load capacitance value of the capacitance of the dummy bit line DBL1 are respectively located at the input of the dummy bit line DBL2 terminal and the output terminal of the column direction of the load circuit CLBn and the load capacitance of the CLBn value is small.

Figure 18 in, the load circuit in the column direction CLBn '[q] and CLBn' [q + 1] is configured with a plurality of (here, four) of the NMOS transistor in series MNb1 - MNb4, if row direction load circuit CLBn and as in the case of CLBn. However, unlike in a row direction and load circuit CLBn and as CLBn, NMOS transistor MNb2 and MNb3 only public coupling node (source or drain) is coupled to the corresponding dummy bit line (DBL1 or DBL2). Through this configuration can also be obtained with the embodiment 1 in the case of the effect of the same.

Embodiment 5

"Read/write control circuit details"

Figure 19 (a) is a graphical representation according to the embodiment of the invention 5 in the semiconductor device as shown in Figure 1 in the memory of the read/write control circuit of the peripheral configuration of the block diagram of the embodiment, Figure 19 (b) is graphical representation chart 19 (a) read/write shown in the concrete configuration of the delay control circuit of the embodiment of the wiring diagram. Figure 20 (a) is graphical representation chart 19 at the time of reading in the operation of the embodiment of the profile, Figure 20 (b) is graphical representation chart 19 write the time when the operation of the embodiment of the profile.

Figure 19 (a) indicated by the read/write control circuit is provided with a decoding RWCTL activation signal generating circuit TDECGEN and reading/writing the delay control circuit RWDLYCTL. As shown in Figure 20 (a) and Figure 20 (b) is shown, the decoding activation signal generating circuit in response to a clock signal CLK and the like TDECGEN, activate the decoding activation signal TDEC. A word line driving circuit WD decoding activation signal in response to the appearance of the TDEC, the activation of the predetermined word line WL. As mentioned above, the timing adjusting circuit TMCTLB through a predetermined delay time (Tdly1) is transmitted to the decoding activation signal to output the dummy bit line signal TDEC SDBL.

As shown in Figure 20 (a) is shown, when the internal write enable signal WE designated read operation when the (here WE='0'), the read/write delay control circuit in response to the dummy bit line signal RWDLYCTL SDBL, activation of the sense amplifier enable signal SE. A sense amplifier circuit in response to the activation of the SA sense amplifier enable signal SE, the implementation of the amplifying operation. In this case, positive-based line pair (BL, ZBL) the switching speed of the (from the pre-in the "high" level pre-charging state of the electric charge of the taken out speed) based on word line number (bit line length) change. Therefore, adopting the above-mentioned timing adjustment circuit TMCTLB become useful.

As shown in Figure 20 (b) is shown, when the internal write enable signal WE (here WE='1') when the designated write operation, the read/write delay control circuit in response to the dummy bit line signal RWDLYCTL SDBL, at a predetermined delay (Tdly2) is activated after the write mode word line pull-down signal BACKW. As shown in Figure 20 (a) is shown, when the internal write enable signal WE designated the read operation, decoding the activation signal generating circuit TDECGEN in a previously set after a predetermined period, the decipher TDEC to activation of the activation signal. As shown in Figure 20 (b) is shown, when the internal write enable signal WE designated write-in operation, decoding the activation signal generating circuit TDECGEN in response to the activation of word line pull-down signal BACKW write mode, the decipher TDEC to activation of the activation signal. As shown in Figure 20 (a) and Figure 20 (b) is shown, a word line driving circuit WD decoding activation signal in response to the decline of the TDEC, a predetermined word line WL deactivation.

As shown in Figure 20 (b) is shown, when the write memory cell MC in the opposite of the current storage information storing information in the, storage nodes in the memory cell MC (MEMT, MEML) at the speed of the inverse of the number of WL along with word and line change (bit line length). Therefore, the writing, preferably relative to the number of word line WL (bit line length) adjust a word line WL deactivation sequence. Therefore, the embodiment of the invention 5 in, through the timing adjustment circuit TMCTLB manner not only to adjust the sense amplifier activation timing but also regulate the write a of the word line WL deactivated time sequence.

For example, fig. 19 (b) is shown, read/write delay control circuit can be RWDLYCTL through two is equipped with a control switch of the inverter circuit CIV1 and CIV2 and configured with multi-stage inverter circuit of the delay circuit module IVBK realize. Is equipped with a control switch of each inverter circuit CIV1 and CIV2 included in the power supply voltage VCC and output node (i.e., on pulls the side) of the PMOS transistor coupled in series between the MP20 and MP21, and ground power supply voltage VSS and output node (i.e., next pulls the side) connected in series between the NMOS transistor of the MN20 and MN21. PMOS transistor MP20 and NMOS transistor MN20 forming CMOS inverter circuit, PMOS transistor MP21 NMOS transistor MN21 and as the role of the control switch, for controlling the CMOS inverter circuit activation and deactivation.

In the provided with a control switch of the inverter circuit CIV1 in, when the internal write enable signal WE (WE='0') designated the read operation, the control switch is set to on, CMOS inverter circuit input dummy bit line signal SDBL and make the dummy bit line signal SDBL inverting (this is at its inverted signal), and the sense amplifier enable signal SE output to the output node. The inverter circuit CIV1 in, when the internal write enable signal WE (WE='1') when the designated write operation, the control switch is set to off, an output node of the CMOS inverter circuit is set into the high impedance state. In this case, although not shown, the output node through the pull-down switch and the like driving to the ground power supply voltage VSS level.

On the other hand, provided with a control switch in the inverter circuit CIV2 in, when the internal write enable signal WE (WE='1') when the designated write operation, the control switch is set to on. In this case, dummy bit line signal SDBL (this is at its inverted signal) through the delay circuit module IVBK on-delay (fig. 20 (b) in the Tdly2) after the input to the CMOS inverter circuit. CMOS inverter circuit the input signal phase, and will write mode word line pull-down signal BACKW output to the output node. In the provided with a control switch of the inverter circuit CIV2 in, when the internal write enable signal WE (WE='0') designated the read operation, the control switch is set to off, the output node of the CMOS inverter circuit is set into the high impedance state. In this case, although not shown, the output node through the pull-down switch and the like driving to the ground power supply voltage VSS level.

As mentioned above, by adopting the according to the embodiment of the invention 5 of the semiconductor device, when the number of the write word line (bit line length) corresponding to the operation sequence (the word line pull-down sequence) can be optimized to be possible.

Embodiment 6

"The timing adjusting circuit (column direction) of the specific circuit (5)"

Figure 21 is the wiring diagram of graphic according to the embodiment of the invention 6 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration examples. Figure 21 as shown in the timing adjustment circuit TMCTLBn 4 for the above-mentioned Figure 5 as shown in the timing adjustment circuit TMCTLBn 1 improved embodiment. Figure 21 as shown in the timing adjustment circuit TMCTLBn 4 with Figure 5 as shown in the timing adjustment circuit TMCTLBn 1 is different in that the dummy bit line DBL1 'and DBL2' is about half the length of the, correspondingly, inverter circuit IV3 and IV4 arrangement are also different.

As noted above, because the timing adjustment circuit may be composed of memory array MARY independently form, even if the dummy bit line DBL1 'and DBL2' the length of the memory array is not necessarily the original MARY BL of the bit line of the same length, in a layout also will not appear is not convenient. However, in order to reflect the original bit line parasitic capacitance in the number based on the word line (the original bit line length) of the fluctuation component, the ideal is to maintain is the length of the dummy bit line-based with the ratio of the length of (the example in 2:1). The above-mentioned embodiment when applied to for example the dual-port SRAM isochronous useful. In other words, the dual-port SRAM in, sense amplifier circuit and the like generally along the Y direction in the clip in the middle of the two sides of the memory array MARY. In this case, in the example as shown in Figure 21 of the timing adjusting circuit TMCTLBn 4 in, the upper half-empty white region symmetrically on the X arrangement and in the lower half area of the circuit arrangement of the circuit can be the same, and through the use of the present two circuit system, to each of the two sides of the sense amplifier circuit provides the dummy bit line signal.

Embodiment 7

"The timing adjusting circuit (column direction) of the specific circuit (6)"

Figure 22 is the wiring diagram of graphic according to the embodiment of the invention 7 comprising in a semiconductor device the timing adjusting circuit (a column direction) configuration examples. Figure 22 shown TMCTLB 5 of a timing adjustment circuit for the above-mentioned Figure 5 shown TMCTLBn 1 of a timing adjustment circuit of the improved embodiment, and Figure 5 shown TMCTLBn 1 of a timing adjustment circuit to the state of the load circuit in the column direction CLB2 - CLB2 configuration. The load circuit in the column direction CLB2 - CLB2 sequentially arranged along the Y direction, and are respectively provided with a plurality of (here, four) NMOS transistor MNc1 - MNc4.

NMOS transistor MNc1 - MNc4 source/drain coupled to one of the dummy bit line common to DBL1, source/drain electrode common to the other end of the dummy bit line DBL2 is coupled to, the ground power supply voltage VSS is applied to the gate. When the configuration example, the column direction the dummy bit line DBL1 load circuit of the load capacitance of the load circuit by the column direction CLB2 - CLB2 of the NMOS transistor MNc1 - MNc4 drain/source electrode of one end of the capacitance from the diffusion layer, and listed in the direction of the load circuit of the dummy bit line DBL2 the load capacitance of the load circuit by the column direction CLB2 - CLB2 of the NMOS transistor MNc1 - MNc4 drain/source in the other end of the capacitance from the diffusion layer.

"The timing adjusting circuit (column direction) of the specific circuit (7)"

Figure 23 is the wiring diagram of graphical representation chart 22 improved embodiment. Figure 23 of a timing adjustment circuit shown TMCTLB 5' to be able to make the Figure 22 shown in the column direction of the load circuit CLB2 - CLB2 MNc1 - MNc4 NMOS transistor in the gate voltage of the variable configuration of the arrangement of the embodiment. Therefore, Figure 23 in, set up includes a latch circuit including LTe CLCTL the load capacitance of the setting circuit. Such as embodiment 3 and the other as in the case of, latch circuit LTe input load capacitance setting signal Se and collectively control the load circuit in the column direction CLB2 - CLB2 MNc1 - MNc4 NMOS transistor in the conduction/cut-off. For example, when the NMOS transistor MNc1 - MNc4 CLCTL through the load capacitance of the circuit is set into the cut-off state, obtained with the Figure 22 the same state. On the contrary, when the NMOS transistor MNc1 - MNc4 is set to the on state, through the NMOS transistor acts as a switch of the MNc1 - MNc4 in dummy bit line DBL1 and DBL2 is formed between the short-circuit. In this case, the starting timing of the sense amplifier and can be temporarily set up earlier.

"The timing adjusting circuit (column direction) of the specific layout configuration (2)"

Figure 24 is the top view of graphical representation chart 22 and Figure 23 shown in the direction of the timing adjustment circuit of the load circuit specific layout configuration examples. As shown in Figure 24, the timing adjusting circuit TMCTLB 5 (or the timing adjusting circuit TMCTLB 5') including the trap WEL, well diffusion layer formed in the WEL DF, via the gate insulating film in the trap WEL PO formed on the polycrystalline silicon layer, the upper layer sequentially formed 1st the metal wiring layer M1 and 2nd the metal wiring layer M2, contact passes the level CT and V1. Contact established CT 1st the metal wiring layer M1 and the polycrystalline silicon layer and 1st PO the coupling between the metal wiring layer M1 and diffusion between the DF coupling. passes the level V1 has established a 1st the metal wiring layer M1 and 2nd the metal wiring layer M2 of the coupling between the.

Figure 24 in, by the 2nd the metal wiring layer M2 formed dummy bit line DBL1 two and DBL2 along the Y direction (the extending direction of the bit lines) and row extends. The polycrystalline silicon layer is formed by PO eight gate wiring along the X direction (the extending direction of the word line) and row extends. The load circuit in the column direction CLB2 in eight gate wiring on the edge of the gate wiring with four of the dummy bit line DBL1 and DBL2 of the intersecting portion is formed. The other a column direction load circuit CLB2 also in the remaining four with the dummy bit line DBL1 gate wiring and DBL2 of the intersecting portion is formed. Each of the column direction in the load circuit, the source or drain diffusion layer become DF arranged in the above-mentioned four gate wiring of each gate wiring on both sides. The use of this arrangement, the NMOS transistor MNc1 - MNc4 along the Y direction are sequentially formed. A column direction included in the load circuit comprising the other diffusion layer DF with a load circuit in the column direction of the space between the diffusion layer DF through as shown in Figure 7 as in the embodiment of the insulating layer. Not privately 7 as the configuration of the shown embodiment, Figure 24 is shown in the configuration of the embodiment, two dummy bit line arranged in a MOS transistor on, and corresponding to the two in a row direction and load circuit is arranged two element active region.

Each of the column direction in the load circuit, used as the NMOS transistor MNc1 - MNc4 the source electrode and the drain electrode of the first DF each diffusion layer via the contact layer coupled to the CT are respectively arranged on each diffusion layer 1st DF upper layer of the metal wiring layer M1 in the wiring. In the two column direction in the load circuit in a load circuit, dummy bit line DBL1 via each of these diffusion layer above the DF passes the level V1 and 1st the metal wiring layer M1 of the NMOS transistor is coupled to the wiring MNc1 one of the source/drain (not with the NMOS transistor MNc2 share a side), NMOS transistor MNc2 and MNc3 common source electrode or drain electrode and NMOS transistor MNc4 one of the source/drain (not with the NMOS transistor MNc3 share a side). The dummy bit line DBL2 via each of these diffusion layer above the DF passes the level V1 and 1st the metal wiring layer M1 of the NMOS transistor is coupled to the wiring MNc1 and MNc2 share the source or the drain of the NMOS transistor and by MNc3 and MNc4 share source or drain. In order to Figure 22 shown in the column direction of the load circuit CLB2 for example, the layout configuration example is equivalent to the NMOS transistor MNc2 and MNc3 public coupling node is coupled to the dummy bit line DBL1, and the NMOS transistor MNc1 and MNc2 public coupling node and NMOS transistor MNc3 and MNc4 public coupling nodes are respectively coupled to the dummy bit line DBL2.

Two of the column direction of the load circuit in another load circuit configuration such that the one of the two in a row direction and load circuit in one of the dummy bit line DBL1 and DBL2 relations of the interchangeable. In other words, dummy bit line DBL2 via each of these diffusion layer above the DF passes the level V1 and 1st the metal wiring layer M1 of the NMOS transistor is coupled to the wiring MNc1 one of the source/drain (not with the NMOS transistor MNc2 share a side), NMOS transistor MNc2 and MNc3 share of MNc4 and NMOS transistor source or drain electrode of one of the source/drain (not with the NMOS transistor MNc3 share a side). The dummy bit line DBL1 via each of these diffusion layer above the DF passes the level V1 and 1st the metal wiring layer M1 of the NMOS transistor is coupled to the wiring MNc1 and MNc2 common source electrode or drain electrode and NMOS transistor MNc3 and MNc4 share source or drain. A polysilicon layer formed PO eight gate wiring through the contact layer coupled to the CT jointly by the 1st the metal wiring layer M1 formed extending along the Y direction of the grid bias wiring VGL. As Figure 7 as in the case of, can be through the passes the level V1 the presence or absence of the load capacitance amplitude adjustment.

When the fig. 24 shown in the layout of the configuration instance and the Figure 7 shown in the layout of the configuration examples do when compared, fig. 24 shown in the layout of the configuration examples can be adopting arranged on each element the two ends of the active region under the premise of the diffusion layer of a relatively small area. Figure 7 in, if each element active region of the two ends of the diffusion layer, the ten diffusion layer coupled to the dummy bit line capacitance will be DBL1 and DBL2 in each. On the other hand, Figure 24 in, five diffusion layer capacitance is coupled to the dummy bit line DBL1 and DBL2 in each, and, when the each diffusion layer area on the assumption that the Figure 7 of about two times the situation, dummy bit line DBL1 and DBL2 diffusion layer capacitance of the amplitude in fig. 24 of the circumstances and Figure 7 is similar to the case. Based on the above considerations, in fig. 7 in the case where, in the dummy bit line DBL1 formed at the lower side of the column direction of the load circuit and the dummy bit line DBL2 formed at the lower side of the column direction of the load circuit between the separated space (in particular, element-isolating insulating layer) is necessary, however, the space in fig. 24 of the cases is not necessary, resulting in a relatively small area. On the other hand, in each element active region does not adopt the two ends of the case of the diffusion layer, or in the gate insulating film capacitance as a load capacitance of the cases, a more ideal is uses the chart 7 shown in the example layout configuration.

As mentioned above, by adopting the according to the embodiment of the invention 7 semiconductor device obtained with the above-mentioned embodiment 1 the same effect is possible, in addition, according to this case, and can also achieve a relatively small area. In spite of the NMOS transistor in this example the configuration of the load circuit in the column direction, but in fact can also adopt the PMOS transistor.

Embodiment 8

"The timing adjusting circuit (column direction) of the specific circuit (8)"

Figure 25 is the wiring diagram of graphic according to the embodiment of the invention 8 comprising in a semiconductor device a timing adjustment circuit configuration example (column direction). Figure 25 of a timing adjustment circuit shown TMCTLB 6 Figure 12 is shown in the timing adjustment circuit TMCTLBn 2 or chart 22 of a timing adjustment circuit shown TMCTLB 5 improved embodiment, and with the Figure 22 compared with, the load circuit in the column direction CLB3 - CLB3 configuration different from a configuration. The load circuit in the column direction CLB3 - CLB3 sequentially arranged along the Y direction, and each of the column direction load circuit CLB3 - CLB3 disposes a plurality of (here, 12 a) NMOS transistor MNc1 - MNc4, MNc11 - MNc14 and MNc21 - MNc24.

NMOS transistor MNc11 - MNc14 in, one of the source/drain is coupled to the dummy bit line common to DBL1, source/drain the other one of the respectively coupled to the NMOS transistor MNc1 - MNc4 one of the source/drain of. NMOS transistor MNc21 - MNc24 in, one of the source/drain is coupled to the dummy bit line common to DBL2, source/drain the other one of the respectively coupled to the NMOS transistor MNc1 - MNc4 source/drain of another. The power supply voltage applied to the NMOS transistor VCC MNc11 - MNc14 and MNc21 - MNc24 grid, the ground power supply voltage VSS is applied to the NMOS transistor MNc1 - MNc4 gate.

When the configuration example, the column direction the dummy bit line DBL1 load circuit of the load capacitance of the gate insulating film is mainly composed of a capacitor and a NMOS transistor MNc11 - MNc14 source/drain of each diffusion layer capacitance and NMOS transistor MNc1 - MNc4 one of the source/drain diffusion layer of the capacitor from the combined capacitance. Similarly, the column direction the dummy bit line DBL2 load circuit of the load capacitance of the gate insulating film mainly composed of NMOS transistor capacitance and MNc21 - MNc24 source/gate of each diffusion layer capacitance and NMOS transistor MNc1 - MNc4 source/drain diffusion layer of the other one of the combined capacitance from the capacitance.

In this way, through the gate insulating film capacitance can be utilized as a load capacitor configuration, can be relatively large load capacitance value to meet the needs of the situation. Also appropriately carry out each NMOS transistor gate voltage variable is set, as in Figure 23 and the other as in the case of. For example, when the NMOS transistor MNc1 - MNc4 set up the grid voltage is the power supply voltage when the VCC, dummy bit line DBL1 and DBL2 can be formed between the short-circuit, as shown in Figure 23 as in the case of. Another case, when the NMOS transistor MNc11 - MNc14, MNc21 - MNc24 the gate voltage of the power supply voltage is set to the ground when the VSS, the column direction of the dummy bit line DBL1 load circuit and DBL2 the load capacitance of the NMOS transistor can be respectively by MNc11 - MNc14 and MNc21 - MNc24 source/drain diffusion layer from one of the capacitor. When the dummy bit line DBL1 does not need and DBL2 when a short-circuit between the, can remove the NMOS transistor MNc1 - MNc4 (in other words, NMOS transistor MNc11 - MNc14, MNc21 - MNc24 source/drain of another set up as to disconnect).

"The timing adjusting circuit (column direction) of the specific layout configuration (3)"

Figure 26 is the top view of graphical representation chart 25 shown a timing adjustment circuit of the load circuit in the column direction of the specific layout configuration examples. Figure 26 in, representatively shows a graph 25 shown in the load circuit of the column direction 12 a of the NMOS transistor in the 9 a NMOS transistor. As shown in Figure 26, the timing adjusting circuit TMCTLB 6 includes a trap WEL, trap WEL DF formed in the diffusion layer, through the gate insulating film in the trap WEL PO formed on the polycrystalline silicon layer, the upper layer sequentially formed 1st the metal wiring layer M1 and 2nd the metal wiring layer M2, contact passes the level CT and V1. Contact established CT 1st the metal wiring layer M1 and the polycrystalline silicon layer and 1st PO the coupling between the metal wiring layer M1 and diffusion between the DF coupling. passes the level V1 has established a 1st the metal wiring layer M1 and 2nd the metal wiring layer M2 of the coupling between the.

Figure 26 in, by the 2nd the metal wiring layer M2 formed dummy bit line DBL1 two and DBL2 along the Y direction (the extending direction of the bit lines) and row extends. The polycrystalline silicon layer is formed by PO nine gate wiring along the X direction (the extending direction of the word line) and row extends. In the nine grid and the wiring and the dummy bit line DBL1 and DBL2 of the intersecting portion, are respectively formed comprising the column direction load circuit CLB3 in nine of the NMOS transistor (along the Y direction according to the order of the MNc11, MNc1, MNc21, MNc22, MNc2, MNc12, MNc13, MNc3 and MNc23). Is used as a source or drain diffusion layer DF arranged in the above-mentioned nine gate wiring of each one of the two sides. The diffusion layer is adjacent to the NMOS transistor DF share, in addition to being arranged in one of the outside edge (in other words, in addition to the NMOS transistor MNc11 (and NMOS transistor MNc14 (not shown)) source/drain other than one). In the NMOS transistor MNc23 one end (not with the NMOS transistor MNc3 for one end of the of the total) of the diffusion layer DF is Figure 25 indicated by the NMOS transistor MNc24 shared (the plan for a total of not shown).

As the above nine NMOS transistor of the source and the drain of the first DF each diffusion layer via the contact layer coupled to the CT respectively disposed in each of said diffusion layer in an upper layer of the DF 1st the metal wiring layer M1 of the wiring. The dummy bit line DBL1 via each of these diffusion layer above the DF passes the level V1 and 1st metal wiring layer is coupled to the NMOS transistor MNc11 one of the source/drain (not with the NMOS transistor MNc1 share one side) and the NMOS transistor MNc12 one of the source/drain (with the NMOS transistor MNc13 share a side). The dummy bit line DBL2 via the above diffusion layer on the DF passes the level V1 and 1st the metal wiring layer M1 of the NMOS transistor is coupled to the wiring MNc21 one of the source/drain of (with the NMOS transistor MNc22 share one side) and the NMOS transistor MNc23 one of the source/drain of (with the NMOS transistor MNc24 (not shown) sharing a side). In order to Figure 25 shown in the column direction of the load circuit CLB3 for example, the pattern configuration examples of the dummy bit line DBL1 equivalent are respectively coupled to the NMOS transistor MNc11, NMOS transistor MNc12 and MNc13 public coupling node and NMOS transistor MNc14, and dummy bit line DBL2 are respectively coupled to the NMOS transistor MNc21 and MNc22 public coupling node and NMOS transistor MNc23 and MNc24 public coupling node.

The polycrystalline silicon layer is formed by PO nine gate wiring via the contact layer by the 1st CT appropriate coupling to the metal wiring layer M1 formed and along Y extending in the direction of the two gate bias wiring VGL1 and VGL2. The gate bias voltage wiring VGL1 CT via the contact layer coupled to the NMOS transistor MNc11 - MNc13 and MNc21 - MNc23 of each gate wiring. The gate bias voltage wiring VGL2 CT via the contact layer coupled to the NMOS transistor MNc1 - MNc3 of each gate wiring. As shown in Figure 7 as in the case of in, the amplitude of the load capacitance can be by the presence or absence of passes the level V1 is adjusted.

As mentioned above, by adopting the according to the embodiment of the invention 8 of the semiconductor device, with the above-mentioned embodiment can be obtained 2 the same effect. In spite of the NMOS transistor in this example the configuration of the load circuit in the column direction, the actual may also be employed on PMOS transistor.

Embodiment 9

"The timing adjusting circuit (column direction) of the specific circuit (9)"

Figure 27 is the wiring diagram of graphic according to the embodiment of the invention 9 comprising in a semiconductor device a timing adjustment circuit configuration example (column direction). Figure 27 of a timing adjustment circuit shown TMCTLBn 5 Figure 5 shown TMCTLBn 1 of a timing adjustment circuit of the improved embodiment. Figure 27 with the configuration example shown in Figure 5 is shown the configuration example is different in that Figure 5 in the direction of the load circuit shows the row CLBn - CLBn by fig. 27 in the direction of the load circuit shows the row CLB4 - CLB4 to replace.

The load circuit in the column direction CLB4 - CLB4 each of the load circuit in the column direction are disposed a plurality of (here, four) of which the source electrode and the drain electrode of the NMOS transistor in series MNe1 - MNe4. Located in the NMOS transistor MNe1 - MNe4 two end of the NMOS transistor MNe1 and MNe4 of the source electrode or the drain electrode is disconnected. Not privately 5 as in the case of, in the column direction load circuit CLB4 - CLB4 NMOS transistor in MNe1 - MNe4 jointly coupled to the grid of the corresponding dummy bit line DBL1 of and DBL2. Therefore, NMOS transistor MNe1 - MNe4 capacitor as a gate insulating film of each of the column direction of the load circuit is added to the dummy bit line DBL1 stray capacitance and DBL2 in.

For example, fig. 27 is shown by the configuration of the dummy bit line can be the embodiment DBL1 and DBL2 via passes the level V1 not only coupled to the diffusion layer DF but also is coupled to each gate wiring (polycrystalline silicon layer PO), in fig. 7 shown in the configuration example of the realization of the layout. In this case, by the presence or absence of the states passes the level V1 to carry out the timing adjustment. Figure 27 configuration embodiment, NMOS transistor MNe1 - MNe4 keep the two ends of the disconnect. However, for example, can also be applied to the one end of the ground power supply voltage VSS, while maintaining the other end disconnect.

Embodiment 10

"The timing adjusting circuit (a row direction) of the specific circuit"

Figure 28 is the wiring diagram of graphic according to the embodiment of the invention 10 comprising in a semiconductor device the timing adjusting circuit (a row direction) configuration examples. In the above embodiment, has to reflect the column direction (the direction of the bit line length) dependence of the timing adjusting circuit (a column direction) is described. However, in a similar manner, can also be reflecting the row direction (the length direction of the word line) dependence of the timing adjusting circuit (a row direction). Figure 28 is shown in the timing adjustment circuit for TMCTLW with Figure 5 is shown a timing adjustment circuit TMCTLBn 1 rotating 90 degrees a configuration corresponding to the examples.

Figure 28 is shown in the timing adjustment circuit (a row direction) TMCTLW includes a plurality of (here, six) of the inverter circuit IV1 - IV6, two dummy word line DWL1 and DWL2 and x line direction load circuit CLWn - CLWn. Here, dummy word line DWL1 and DWL2 respectively with the length of the memory array MARY word and line WL have substantially equal lengths, and their with the memory array along the extending direction of the MARY word and line WL (X direction) are arranged side by side in the same direction. The inverter circuit IV1 - IV6 is a CMOS inverter circuit, are provided respectively in the power supply voltage VCC and the ground power supply voltage VSS coupled between the PMOS transistor and the NMOS transistor.

The inverter circuit IV1 and IV2 are respectively arranged in the dummy word line DWL1 at input terminal of. The inverter circuit IV1 input the above-mentioned decoding activation signal TDEC, inverter circuit IV2 input inverter circuit IV1 and the output signal of the inverse of the signal output to the dummy word line DWL1 input terminal. The inverter circuit IV3 and IV4 are respectively arranged in the dummy word line DWL1 at the output terminal of the dummy word line DWL2 and at input terminal of. The inverter circuit IV3 DWL1 dummy word line input from the output terminal of the signal, the inverter circuit IV4 IV3 input inverter circuit the output signal of the inverse of the signal output to the dummy bit line DWL2 input terminal. The inverter circuit IV5 and IV6 DWL2 dummy word line are respectively arranged at the output terminal. The inverter circuit IV5 DWL2 dummy word line input from the output terminal of the signal, the inverter circuit IV6 input inverter circuit IV5 and output the output signal of the dummy bit line signal SDWL. In this way, dummy word line DWL1 and dummy word line DWL2 MARY arranged in close proximity to the memory array of a timing adjustment circuit TMCTLW (row direction) in the area of the two-way wiring.

Each row direction load circuit CLWn - CLWn includes a plurality of (here, four) its source and drain connected in series in sequence and the gate common couples to the ground power supply voltage VSS of the NMOS transistor MNd1 - MNd4. X line direction as a part of the load circuit (for example, half) of the load circuit line direction CLWn - CLWn in, NMOS transistor MNd2 and MNd3 source and the drain of the dummy word line is coupled to the DWL1, NMOS transistor MNd1 and MNd4 one of the source/drain (not with the NMOS transistor MNd2 and MNd3 share a side) is disconnected. X line direction as in other portions of the load circuit (for example, the remaining half) of each line in the direction of the load circuit CLWn [q + 1] - CLWn in, NMOS transistor MNd2 and MNd3 of the source and drain is coupled to the dummy bit line DBL2, NMOS transistor MNd1 and MNd4 one of the source/drain (not with the NMOS transistor MNd2 and MNd3 share a side) is disconnected.

Figure 28 is shown in the configuration example, as shown in Figure 5 as in the case of, NMOS transistor can be MNd2 and MNd3 of the source and drain diffusion layer capacitance adds to the line direction of the load circuit of the dummy word line DWL1 and DWL2. Therefore, in the decoding activation signal after a change of the dummy word line signal TDEC SDWL change properly setting delay time before. In this case, the bit line in the memory array MARY BL number (the length of the word line WL) can be with the storage units corresponding to the description of the change. Therefore, word line WL along with word and line WL the occurrence time of the change of the parasitic capacity or the like. Therefore, read and write the amount of time spent will correspondingly change. Therefore, uses the chart 28 when the configuration of the shown embodiment, as shown in Figure 5 as in the case of, dummy word line of the length of the length of the WL along with word and line change, therefore, the generation of the word line to reflect the influence of the parasitic capacity or the like of the operation sequence of the (dummy word line signal SDWL) become possible. For example, fig. 28 with the configuration example shown in Figure 5 and other configuration examples used in combination, and it is carrying out the following operation: to Figure 5 of a timing adjustment circuit shown TMCTLBn 1 input the dummy word line signal SDWL to replace the decoding activation signal TDEC.

"The timing adjusting circuit (a row direction) of the specific layout configuration"

Figure 29 is the top view of graphical representation chart 28 shown in the row direction of the timing adjustment circuit of the load circuit configuration examples of the specific layout. As shown in Figure 29, the timing adjusting circuit (a row direction) WEL TMCTLW including trap, trap WEL DF formed in the diffusion layer, the gate insulating film is interposed in the trap WEL PO formed on the polycrystalline silicon layer, are formed in the upper layer of the 1st the metal wiring layer M1 and 2nd the metal wiring layer M2, contact passes the level CT and V1. The contact layer CT to establish 1st the metal wiring layer M1 and the polycrystalline silicon layer and 1st PO the coupling between the metal wiring layer M1 and diffusion between the DF coupling. passes the level V1 to establish 1st the metal wiring layer M1 and 2nd the metal wiring layer M2 of the coupling between the.

Figure 29 in, by the 1st the metal wiring layer M2 forming two dummy word line DWL1 and DWL2 along the X direction (the extending direction of the word line) and row extends. In the dummy word line DWL1 on both sides, is formed by the polycrystalline silicon layer PO two gate wiring extending along the X direction and rows, in the dummy word line DWL2 on both sides, the polycrystalline silicon layer formed by the PO two gate wiring also extending along the X direction and rows. Forming NMOS transistor MNd1 and MNd2 component active area is disposed in the dummy word line DWL1 in the lower layer of, and along the X direction close to the dummy word line DWL1 arrangement forms the NMOS transistor MNd3 and MNd4 element active region. NMOS transistor MNd1 and MNd4 grid configuration with the dummy word line DWL1 located on both sides of the one of the two gate wiring. NMOS transistor MNd2 and MNd3 grid configured with two gate wirings in another.

In the NMOS transistor formed MNd1 and MNd2 element active region, is used as a source or drain diffusion layer DF arranged corresponding to the NMOS transistor MNd1 and MNd2 grid of two grid wiring on both sides. In these diffusion layer, arranged in two gate wiring between the diffusion layer of the NMOS transistor by DF MNd1 and MNd2 share. Similarly, in the NMOS transistor formed MNd3 and MNd4 element active region, is used as a source or drain diffusion layer DF arranged corresponding to the NMOS transistor MNd3 and MNd4 grid of two grid wiring on both sides. In these diffusion layer, arranged in two gate wiring between the diffusion layer of the NMOS transistor by DF MNd3 and MNd4 share. The dummy word line DWL1 CT via the contact layer are respectively coupled to the NMOS transistor MNd1 and MNd2 shared diffusion layer and NMOS transistor MNd3 and MNd4 shared diffusion layer. In the NMOS transistor MNd2 and MNd3 shared in the diffusion layer on different sides of each of the diffusion layer is formed on the DF along the X 1st extending in the direction of the metal wiring layer M1 of the wiring, and each diffusion layer via the contact CT are respectively coupled to the 1st the metal wiring layer M1 of the wiring. 1st the metal wiring layer M1 wiring extending along the Y direction via the 1st the metal wiring layer M1 of the dummy word line is coupled to the wiring further DWL1.

The dummy word line DWL2 there is and the lower part of the dummy word line DWL1 the lower part of the same configuration. Appropriate to form the above-mentioned element and the active area, and appropriately formed NMOS transistor MNd1 - MNd4 and make its appropriate dummy word line coupled to the DWL2. In the above-mentioned dummy word line arranged DWL1 and DWL2 a total of four of the two sides of the gate wiring (polycrystalline silicon layer PO) via the first contact is coupled to the CT corresponding to each gate wiring arranged 1st the metal wiring layer M1 of the wiring. Therefore, the four gate wiring also via the passes the level V1 jointly coupled to along Y extends in the direction of the grid bias voltage wiring VGL. The gate bias voltage wiring VGL by 2nd the metal wiring layer M2 is formed. In states the cloth in the Figure, can be through the NMOS transistor MNd1 - MNd4 DF in each diffusion layer contact the presence or absence of CT to the load capacitor of the amplitude control. In order to map 28 is shown in the row direction of the load circuit CLWn for example, the layout configuration example is equivalent to the NMOS transistor MNd2 one of the source/drain of the NMOS transistor MNd3 and of one of the source/drain diffusion layer formed by different, and they are respectively coupled to the from the dummy word line DWL1 in the 1st branch of the metal wiring layer.

As mentioned above, by adopting the according to the embodiment of the invention 10 of the semiconductor device, so that the generated number based on the bit line (word line length) the optimal operating sequence become possible. Of course, through the same layout configuration as shown in Figure 7 embodiment realizing Image 28 shown in the embodiment of configuration is also possible. However, in fig. 29 in, from the reflected angle of X direction-dependent relationship, in which the dummy word line and the gate wiring extending along the X direction of the layout configuration examples. Figure 28 configuration examples above row direction as if the load circuit as in the various embodiments can be properly improved, and if the embodiment 5 stated, Figure 28 configuration examples can also be set to activate the word line write sequence is used.

Embodiment 11

"The timing adjusting circuit (column direction) of the layout (1)"

Figure 30 (a), fig. 30 (b) and Figure 30 (c) is a graphical representation according to the embodiment of the invention 11 of the semiconductor device in the memory of the timing adjusting circuit (a column direction) each different configuration of the embodiment of the schematic view. Figure 30 (a) in, a word line driving circuit WD, a timing adjustment circuit MARY TMCTLB and memory array along the X direction (word line extending direction of the WL) arranged in sequence. Figure 30 (b) in, the timing adjusting circuit TMCTLB, a word line driving circuit WD and MARY along the X direction of the memory array are arranged in the order. Figure 30 (c) in, a word line driving circuit WD, memory array and a timing adjustment circuit MARY TMCTLB along the X direction are arranged in the order.

Figure 31 (a), fig. 31 (b) and Figure 31 (c) for shows and Figure 30 (a), Figure 30 (b) and Figure 30 (c) of the memory unit shown in different memory of the timing adjusting circuit (column direction) of each of the different arrangement of the embodiment of the schematic view. Not privately 30 (a) to Figure 30 (c) as, Figure 31 (a) to fig. 31 (c) in, set up a plurality of (here, two) memory array MARY1 and MARY2. Figure 31 (a) in, MARY1 1st memory array, a word line driving circuit WD, a timing adjustment circuit MARY2 TMCTLB and 2nd memory array along the X direction (word line extending direction of the WL) arranged in sequence. The memory array MARY1 and memory array MARY2 WL by word line arranged in the middle of the word line driving circuit WD drive. Fig. 31 (b) in, MARY1 1st memory array, a word line driving circuit WD, 2nd memory array MARY2 and a timing adjustment circuit sequentially arranged along the X direction TMCTLB. Fig. 31 (c) in, 1st memory array MARY1, WD1 1st a word line driving circuit, a timing adjustment circuit TMCTLB, 2nd word line driving circuit WD2 and 2nd memory array MARY2 sequentially arranged along the X direction. 1st memory array MARY1 WL 1st the word line by the word line driving circuit WD1 driving, and 2nd memory array MARY2 WL 2nd word line by the word line driving circuit WD2 driving.

As mentioned above, according to the embodiment of the timing adjustment circuit TMCTLB use logic layout rules to form non-storage unit layout rules. Therefore, as shown in Figure 30 (b) and Figure 31 (c) is shown, for example, does not have to be a timing adjustment circuit arranged in the vicinity of the TMCTLB memory array. Fig. 31 (c) in, through the word line driving circuit WD is divided into two to obtain symmetrical circuit arrangement. However, separate word line driving circuit WD is likely to increase the circuit area. For example, in the following circumstances produce Figure 32 (a) and Figure 32 (b) of the effect difference shown: as shown in Figure 30 (a), fig. 30 (b) and 31 (a) is shown, a word line driving circuit TMCTLB WD and a timing adjustment circuit arranged in the memory array near the side of the, and, as shown in Figure 30 (c) and Figure 31 (b) is shown in, a word line driving circuit WD and a timing adjustment circuit are arranged separately from the TMCTLB in the two sides of the memory array. Fig. 32 (a) and Figure 32 (b) is respectively shown in the case of signal flow the following explanatory with photos: as shown in Figure 30 (a) to Figure 30 (c) and Figure 31 (a) to fig. 31 (c) is shown, the timing adjusting circuit (a column direction) in the arrangement, a word line driving circuit and a timing adjustment circuit is disposed on one side of the memory array, and the word line drive circuit and a timing adjustment circuit in the memory array are arranged separately from the two sides.

First of all, fig. 32 (a) graphically shows the word line driving circuit in the WD and a timing adjustment circuit arranged in the memory array TMCTLB MARY case at one side of the arrangement of the whole memory configuration examples. In this case, comprising for example a sense amplifier circuit including the input/output circuit module IOBK along the Y direction in the vicinity of the memory array MARY, control circuit module CTLBK arranged along the Y direction in the adjacent word line driving circuit WD and the timing adjusting circuit TMCTLB along the X direction and adjacent to the input/output circuit module IOBK position. The control circuit module CTLBK TDEC decoding activation signal will be output to the timing adjustment circuit TMCTLB, and receiving from a timing adjustment circuit of the dummy bit line signal SDBL TMCTLB. The control circuit module according to the dummy bit line signal SDBL CTLBK generates the read amplifier enable signal, which is outputted to the input/output circuit module IOBK. In this way, because the signal flow in fig. 32 (a) of the case is simple, reduce the amount of accompanying the signal path timing change and become possible.

Secondly, fig. 32 (b) graphically shows the word line driving circuit in the WD and a timing adjustment circuit in the memory array are arranged separately from the TMCTLB MARY two side under the condition that the arrangement of the whole memory configuration examples. In this case, the input/output circuit module IOBK along the Y direction in the vicinity of the memory array MARY, for example, 1st control circuit module CTLBK 1 are arranged in the X direction along adjacent to the input/output circuit module IOBK and adjacent along the Y direction of the word line driving circuit position of the WD. 2nd control circuit module CTLBK 2 arranged along the Y direction in the adjacent position of the timing adjustment circuit TMCTLB. 1st control circuit module CTLBK 1 the decipher TDEC 2nd activation signal output to the control circuit module CTLBK2. 2nd control circuit module CTLBK 2 will be decoding activation signal output to the timing adjustment circuit TDEC TMCTLB, and receiving from a timing adjustment circuit of the dummy bit line signal SDBL TMCTLB. 2nd control circuit module CTLBK 2 according to the dummy bit line signal SDBL generates the read amplifier enable signal, which is outputted to the input/output circuit module IOBK.

In this way, in fig. 32 (b) of the cases, the implementation of the decipher TDEC 1st activation signal from the control circuit module CTLBK 1 transmission to 2nd control circuit module CTLBK 2 operation. Therefore, word line WL the length direction of the wiring delay can be reflected to a certain extent to the in the transmission process. Therefore, can produce the sense amplifier activation timing, this reflects the depend not only on the length direction of the bit line but on the length direction of the word line. When the with the embodiment 10 of the timing adjustment circuit (a row direction) similar timing adjustment circuit is arranged on the control circuit module CTLBK 1 from the 1st to 2nd control circuit module CTLBK 2 on the transmission path, will be more useful effect. Usually, a relatively wide space for the word line driving circuit can be arranged in the memory array not WD MARY obtained on one side of, the relatively wide space for the word line and the like with a terminal portion of processing related. Fig. 32 (b) in the arrangement shown, can effectively utilize such available space, thus, the area efficiency can be improved.

Embodiment 12

"The timing adjusting circuit (column direction) of the arrangement (2)"

Figure 33 (a), Figure 33 (b) and Figure 33 (c) is a graphical representation according to the embodiment of the invention 12 of the semiconductor device in the memory of the timing adjusting circuit (column direction) of each of the different arrangement of the embodiment of the schematic view. Figure 33 (a) in, a word line driving circuit WD, the timing adjusting circuit (for to the outer passageway) TMCTLB_FW, memory array MARY, the timing adjusting circuit (for return path) TMCTLB_RV along the X direction (word line extending direction of the WL) arranged in sequence. Figure 33 (b) in, the timing adjusting circuit (for to the outer passageway) TMCTLB_FW, a word line driving circuit WD, the timing adjusting circuit (for return path) TMCTLB_RV, MARY along the X direction of the memory array are arranged in the order. Figure 33 (c) in, the timing adjusting circuit (for to the outer passageway) TMCTLB_FW, a word line driving circuit WD, memory array MARY, the timing adjusting circuit (for return path) TMCTLB_RV along the X direction are arranged in the order.

Figure 34 (a) and Figure 34 (b) is shows and Figure 33 (a), Figure 33 (b) and Figure 33 (c) shown in different memory unit in the memory of the timing adjustment circuit (column direction) of each of the different configuration of the embodiment of the schematic view. Not privately 33 (a) to fig. 33 (c) as, Figure 34 (a) and Figure 34 (b) in, set up a plurality of (here, two) memory array MARY1 and MARY2. Figure 34 (a) in, 1st memory array MARY1, the timing adjusting circuit (for to the outer passageway) TMCTLB_FW, a word line driving circuit WD, the timing adjusting circuit (for return path) MARY2 TMCTLB_RV and 2nd memory array along the X direction (word line extending direction of the WL) arranged in sequence. The memory array MARY1 and memory array MARY2 WL disposed therein the word line by the word line driving circuit of the WD drive. Figure 34 (b) in, the timing adjusting circuit (for to the outer passageway) TMCTLB_FW, MARY1 1st memory array, a word line driving circuit WD, 2nd memory array MARY2 and timing adjustment circuit (for return path) TMCTLB_RV along the X direction are arranged in the order.

In this way, Figure 33 (a) to fig. 33 (c) and Figure 34 (a) and Figure 34 (b) represents the timing adjustment circuit is divided into two configuration examples. In order to Figure 5 as an example, the timing adjusting circuit (for to the outer passageway) TMCTLB_FW and inverter circuit IV1 and IV2 and the dummy bit line DBL1 corresponding, the timing adjusting circuit (for return path) TMCTLB_RV and inverter circuit IV5 and IV6 and dummy bit line DBL2 to should be. The inverter circuit IV3 and IV4 properly arranged in the timing adjusting circuit (for to the outer passageway) TMCTLB_FW and/or a timing adjustment circuit (for return path) in the TMCTLB_RV. Although not specifically limited, inverter circuit IV3 is arranged in the timing adjustment circuit (for to the outer passageway) in TMCTLB_FW, inverter circuit IV4 is arranged in the timing adjustment circuit (for return path) in the TMCTLB_RV.

For example, in fig. 34 (a) in, when using the configuration of the embodiment, because the occupied space of the timing adjustment circuit is divided into two, and the desired word line driving circuit WD and memory array MARY1 and MARY2 as close as possible to assign cases become useful. As shown in Figure 34 (a) is shown, also can be used in the timing adjustment circuit is divided into two to obtain a symmetrical layout. In addition, according to the circumstances, can adopt the Figure 5 shown as a timing adjustment circuit NMOS transistor (used for to the outer passageway) TMCTLB_FW in the column direction of the load circuit, can adopt the Figure 6 of the PMOS transistor as shown in the timing adjustment circuit (for return path) TMCTLB_RV in the column direction of the load circuit. In this case, as shown in Figure 11 of the explanation, each circuit module well of conduction type taken into account after, properly arranged the timing adjusting circuit (for to the outer passageway) TMCTLB_FW and timing adjustment circuit (for return path) TMCTLB_RV.

Embodiment 13

"The timing adjusting circuit (a row direction) of the arrangement of the"

Figure 35 (a) and Figure 35 (b) is a graphical representation according to the embodiment of the invention 13 of the semiconductor device in the memory of the timing adjusting circuit (a row direction) of each of the different configuration of the embodiment of the schematic view. Figure 35 (a) and Figure 35 (b) in, a word line driving circuit WD, the timing adjusting circuit (a column direction) MARY TMCTLB and memory array along the X direction (word line extending direction of the WL) arranged in sequence. Figure 35 (a) in, the input/output circuit module IOBK and a timing adjustment circuit TMCTLW (a row direction) along the Y direction are arranged in the order in MARY one side of the memory array. On the other hand, Figure 35 (b) in, the input/output circuit module IOBK and a timing adjustment circuit TMCTLW (a row direction) along the Y direction are respectively arranged at the two sides of the memory array MARY.

In this way, the timing adjusting circuit (a row direction) TMCTLW along the Y direction can be arranged in any of the memory array MARY on one side. However, from the need to improve the efficiency of the circuit area angle, ideally uses the chart 35 (b) show examples of the arrangement, in the arrangement in the embodiment arrangement area is relatively easy to obtain, from the perspective of the simplified signal streams, ideally uses the chart 35 (a) the arrangement of the embodiment shown. In other words, Figure 35 (a) of the cases, through the control circuit module is disposed in the timing adjustment circuit (a column direction) with the input/output circuit TMCTLB IOBK or a timing adjustment circuit module (a row direction) of the intersecting part of the TMCTLW (an example as shown in Figure 32), can use control circuit module with each of the timing adjustment circuit (a column direction) TMCTLB, the input/output circuit module IOBK and a timing adjustment circuit TMCTLW (a row direction) of each of the short circuit between the input/output.

As mentioned above, the inventor of the present invention has been achieved under the above-mentioned embodiment of this invention has a specific explanation. However, it should be emphasized that the invention is not limited to the above embodiment, and without departing from the substance of the range can be available in various changes.

For example, each embodiment to SRAM memory is explained as an example; however, in fact, each embodiment may be similarly applied to a DRAM (dynamic random access memory) for the representatives of the volatile memory, and flash memory as a representative of the non-volatile storage device. In the present application, to such as SOC (assembly of the storage unit) of the semiconductor device as an example illustrates; however, the invention also can be used from a single memory of a semiconductor memory device.

Figure 5 and the other is shown in the Figure of the dummy bit line is a single bi-directional wiring formation; however, dummy bit line can be composed of a plurality of bi-directional wiring are sequentially formed so as to adjust the amount of delay.

According to the embodiment of the invention semiconductor device especially effectively applied to such as is provided with a memory (e.g., SRAM) such as SOC of the LSI. However, according to the embodiment of the invention semiconductor device can be applied to have various volatile memory and/or various non-volatile memory of the LSI on a large scale.