Control method of memory system and related memory device

Replica bit line (RBL) control circuit

Clock and control signal generation for high performance memory devices

System and method of operating a memory device

A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.

A memory device and method of performing a write operation in a memory device

NONVOLATILE MEMORY AND METHOD WITH IMPROVED I/O INTERFACE

Each I/O channel between a controller and one or more memory dice of a memory device has a driver on one end and a receiver at the other end. The receiver is optionally terminated with a pseudo open-drain ("POD") termination instead of the conventional center-tapped ("CTT") termination to save energy. During a read operation, data is driven from the memory die to a POD terminated receiver circuit in the controller. With POD termination, the degradation in performance due to the more non-linear driver in the memory die, fabricated for example in the NAND technology processing, is alleviated by an adaptive reference voltage level adjustment in the receiver circuit of the controller. Optionally, the receiver circuit of a memory die is also provided with an adaptive reference level adjustment.

SEMICONDUCTOR INTEGRATED CIRCUIT

In a semiconductor integrated circuit having a multi-port register file, a first holding circuit (20A) is dedicated to a first function block having a first write port part (21AW) and two first read port parts (21AR1,21AR2). A second holding circuit (30B) is dedicated to a second function block having a second write port part (31AW) and a second read port part (31BR). When there occurs a need of reading the held data of the first holding circuit (20A) via, for example, the second read port part (31BR), the data of the second holding circuit (30B) is latched by a latch circuit (40), thereafter the data of the first holding circuit (20A) is transferred to the second holding circuit (30B), and then the data of the second holding circuit (30B) latched by the latch circuit (40) is transferred to the first holding circuit (20A), thereby exchanging the data. Accordingly, the area required for the register file can be significantly reduced.

Memory device with control circuitry for generating a reset signal in read and write modes of operation

A memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device has: memory blocks; and a local bus connected to the memory blocks. Each memory block has: switches respectively provided between bit line pairs and the local bus and each of which is turned ON in response to a selection signal; a dummy local bus; first and second control circuits. The local bus and the dummy local bus are precharged to a first potential before a read operation. In the read operation, the first control circuit outputs the selection signal to a selected switch to electrically connect a selected bit line pair and the local bus, while the second control circuit supplies a second potential lower than the first potential to the dummy local bus. The first control circuit stops outputting the selection signal when a potential of the dummy local bus is decreased to a predetermined set potential that is between the first and second potentials.

Semiconductor memory device

An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

Self-timed memory with adaptive voltage scaling

Various implementations described herein are directed to an integrated circuit that has memory circuitry with a memory structure and a reference path. The integrated circuit includes performance sensing circuitry having a logic structure that is adapted to detect variation of performance of the memory structure. The integrated circuit includes power management circuitry that is coupled to the memory circuitry and the performance sensing circuitry. The power management circuitry receives a feedback signal from the performance sensing circuitry and adaptively adjusts voltage provided to the memory circuitry based on the feedback signal to affect performance of the memory structure. The memory circuitry has a logic stage that reduces signal delay in the reference path for alignment with the adaptively adjusted voltage.

NONVOLATILE MEMORY AND METHOD WITH IMPROVED I/O INTERFACE

Each I/O channel between a controller and one or more memory dice of a memory device has a driver on one end and a receiver at the other end. The receiver is optionally terminated with a pseudo open-drain (“POD”) termination instead of the conventional center-tapped (“CTT”) termination to save energy. During a read operation, data is driven from the memory die to a POD terminated receiver circuit in the controller. With POD termination, the degradation in performance due to the more non-linear driver in the memory die, fabricated for example in the NAND technology processing, is alleviated by an adaptive reference voltage level adjustment in the receiver circuit of the controller. Optionally, the receiver circuit of a memory die is also provided with an adaptive reference level adjustment.

MEMORY

A memory including a memory cell array, a word line decoder, a first and a second reference bit line generators are provided. The memory cell array has first and last bit lines respectively disposed at two sides of the memory cell array. The word line decoder generates a pre-word line signal. The first and the second reference bit line generators respectively detect voltage level variations of the first and last bit lines according to the pre-word line signal, so as to generate a first and a second cut-back signals. The first reference bit line generator transmits the first cut-back signal to the second reference bit line generator, the second reference bit line generator transmits the first and the second cut-back signals to the word line decoder, and the word line decoder generates a word line signal according to the first and the second cut-back signals and the pre-word line signal.

MEMORY ARRAY RESET READ OPERATION

Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input. 1. (canceled)2. A method , comprising:initiating a reset read command that sets at least one portion of a memory array into a temporary state;applying, to all word lines associated with the at least one portion, a voltage that increases to a first voltage above a threshold voltage of memory cells of the at least one portion based at least in part on the initiating;applying, to at least one gate of at least one select gate device of the at least one portion, a voltage that increases to a second voltage above a second threshold voltage of the at least one select gate device based at least in part on the initiating; andsetting a node of the at least one portion to a third voltage based at least in part on the initiating.3. The method of claim 2 , wherein the reset read command that sets the at least one portion of the memory array into the temporary state comprises:initiating a transition of the at least one portion into the temporary state.4. The method of claim 2 , wherein the reset read command that sets the at least one portion of the memory array into the temporary state comprises:maintaining the at least one portion in the temporary state.5. The method of claim 2 , wherein the node comprises a source claim 2 , a drain claim 2 , a bit line claim 2 , or a combination thereof.6. The method of claim 2 , further comprising:decreasing the voltage applied to all word lines associated with the at least one portion from the first voltage to a fourth voltage based at least in part on achieving the first voltage; anddecreasing the ...

Semiconductor memory

A semiconductor memory includes a sense amplifier (SA) which operates in response to activation of a sense amplifier enable signal (SAE) and determines logic held in a nonvolatile memory cell (MC) according to a voltage of a bit line (BL), the voltage varying with a cell current flowing through a real cell transistor (MC), a replica cell transistor (RCT) coupled in series between a first node (N01) and a ground line, and a timing generation unit (TGEN). The timing generation unit (TGEN) activates the sense amplifier enable signal (SAE) when the first node (N01) coupled to the ground line via the replica cell transistor (RCT) changes from a high level to a low level. The replica cell transistor (RCT) includes a control gate receiving a constant voltage (VSA) and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier (SA) can be optimally set in accordance with the electric characteristic of the memory cell (MC).

SENSE AMPLIFIER TIMING CIRCUIT

PROBLEM TO BE SOLVED: To optimize timing performance of a dynamic sense amplifier by having a sense amplifier provided with first and second differential input, strobe input and output, first and second differential input coupling respectively with bit lines and bit bar lines, plural storage cells and word lines. SOLUTION: Differential input of a dynamic sense amplifier 300 are connected respectively to BIT and BIT bar lines pre-charged to VCC using a pre-charge circuit 302. Typical SRAM cells 304 are respectively connected to BIT and BIT bar lines. The SRAM cells 304 comprise a storage latch consisting of TR 306, 308, load devices 310, 312, memory cell access transistors 314, 316. Gate electrodes of the memory cell access transistors 314, 316 are connected to a word line WL. COPYRIGHT: (C)1998,JPO ...

Sensing margin varying circuit and method thereof

Semiconductor device

CLOCK AND CONTROL SIGNAL GENERATION FOR HIGH PERFORMANCE MEMORY DEVICES

SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY STRUCTURE IMPROVING BIT LINE PRECHARGE TIME AND IMPROVING METHOD THEREOF

PURPOSE: A semiconductor memory device is provided, which has a memory cell array structure improving a bit line precharge time(tRP). CONSTITUTION: A memory cell array structure(300) includes a number of memory cell blocks(MB0-MBN), the first sense amplifier blocks(BLSA1-BLSAN-1), the second sense amplifier blocks(BLSA0,BLSAN) and dummy capacitor regions(DCB0,DCB1). Sense amplifier parts(310) connected to bit line pair(BL,/BL) of the first memory cell block(MB0) are arranged in the second sense amplifier block(BLSA0). The sense amplifier part includes the first equalizer and precharge part(311), the first isolation transistor part(312), a bit line sense amplifier(313), the second isolation transistor part(314) and the second equalizer and precharge part(315). The first equalizer and precharge part precharges dummy bit line pair(DBL,/DBL) of the dummy capacitor region. The bit line sense amplifier senses data of memory cells(MC0,MC1) in the first memory cell block. The first dummy capacitor ...

Memory device with bi-directional tracking of timing constraints

A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the word line. The second bi-directional tracking circuit is configured to track a second timing constraint associated with turning on the bit line, turning off the bit line, or accessing the cell via the bit line.

SELF-TIMING FOR A MULTI-PORTED MEMORY SYSTEM

Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.

Efficient sense command generation

In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command; an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on corresponding access transistors to develop voltages on the bit lines; and a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell wherein the replica access transistor is switched on responsive to the clock edge such that the replica memory cell pulls the replica bit line to ground, the bit line replica ...

Clock and control signal generation for high performance memory devices

Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit. The first clock generator generates a first clock signal used for read and write operations. The second clock generator generates a second clock signal used for write operations. The reset circuit generates at least one reset signal for the first and second clock generators. The reset signal(s) may have timing determined based on loading due to dummy cells. The first control signal generator generates control signals used for read and write operations based on the first clock signal. The second control signal generator generates control signals used for write operations based on the second clock signal.

MEMORY INTERFACE CIRCUIT, MEMORY STORAGE DEVICE AND SIGNAL GENERATION METHOD

A memory interface circuit, a memory storage device and a signal generation method are provided. The memory interface circuit is configured to connect a volatile memory module and a memory controller. The memory interface circuit includes a clock generation circuit, a first interface circuit and a second interface circuit. The clock generation circuit is configured to provide a reference clock signal. The first interface circuit is configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal. The second interface circuit is configured to provide a command signal to the volatile memory module based on a second transition point of the reference clock signal. The first transition point is one of a rising edge and a falling edge of the reference clock signal. The second transition point is the other one of the rising edge and the falling edge of the reference clock signal. 1. A memory interface circuit , configured to connect a volatile memory module and a memory controller , and the memory interface circuit comprises:a clock generation circuit, configured to provide a reference clock signal;a first interface circuit, coupled to the memory controller and the clock generation circuit and configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal; anda second interface circuit, coupled to the memory controller and the clock generation circuit and configured to provide a command signal without the address signal to the volatile memory module based on a second transition point of the reference clock signal,wherein the first transition point is one of a rising edge and a falling edge of the reference clock signal, and the second transition point is the other one of the rising edge and the falling edge of the reference clock signal.2. The memory interface circuit according to claim 1 , wherein a transmission cycle of the address ...

Using a reference bit line in a memory

Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit line to reach a reference voltage. A memory cell that is coupled to the bit line may be selected after the precharge period, and a clamp voltage may be set based, at least in part, on the voltage of the reference bit line. If a voltage level of the bit line is less than the clamp voltage level during a sense period, charge may be drained from the sense node, and a state of the memory cell may be determined based, at least in part, on a voltage level of the sense node near an end of the sense period.

Location based timing scheme in memory design

A method and apparatus for improving the access time of a memory device is described. The location based timing scheme utilizes a subset of the address bits to adjust the timing of the sense amplifier enable in order to achieve a faster read of the information stored in the memory cell.

Skewed Corner Tracking for Memory Write Operations

A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

A memory device and method of performing access operations within such a memory device

Electronic equipment

Static random access memory with improved write time and reduced write power

SEMICONDUCTOR MEMORY DEVICE

METHOD AND APPARATUS FOR A DUMMY SRAM CELL

A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and second bit line output circuits. The dummy SRAM cell includes the same first and second subsets of transistors, with the first transistors configured as a dummy bit line output circuit having substantially the same electrical characteristics as the first bit line output circuit of the standard SRAM cell. Further, the second transistors, which are not otherwise needed for the dummy SRAM cell function, are reconfigured as a voltage tie circuit for the dummy bit line output. Using the second transistors for this purpose obviates the need to add additional transistors to form a voltage tie circuit for configuring the dummy bit line output circuit as a load or driver for the dummy bit line.

USING A REFERENCE BIT LINE IN A MEMORY

Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit line to reach a reference voltage. A memory cell that is coupled to the bit line may be selected after the precharge period, and a clamp voltage may be set based, at least in part, on the voltage of the reference bit line. If a voltage level of the bit line is less than the clamp voltage level during a sense period, charge may be drained from the sense node, and a state of the memory cell may be determined based, at least in part, on a voltage level of the sense node near an end of the sense period.

NOR-OR decoder

A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.

Memory array and method of operating the same

A memory array includes an array of memory cells. The memory array further includes at least two read tracking cells in a read tracking column. The memory array further includes a read tracking circuit coupled to the at least two read tracking cells, wherein the read tracking circuit is configured to generate a global tracking result signal based on outputs from the at least two read tracking cells. The memory array further includes memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal.

Apparatus and method for read time control in ECC-enabled flash memory

In a flash semiconductor memory, sense and contiguous ECC coding operations are carried out over a range of VCC values without wasted time by allocating a predetermined number of clocks to the combined operations rather than to the individual operations and operating at higher frequency for high VCC values, and lower frequency for low VCC values.

Tracking bit cell

A method includes determining a plurality of first current values of a first current to be sunk by a tracking cell of a tracking circuit in response to a plurality of first voltage values of a first voltage applied to the tracking cell. Each first current value of the plurality of first current values thereby corresponds to a first voltage value of the plurality of first voltage values. A second current value of a second current is determined. The second current value corresponds to a second voltage value of a second voltage of a memory cell of a plurality of memory cells. A third voltage value is selected based on the second current value, a first current value of the plurality of first current values, and a first voltage value corresponding to the first current value.

System and method of operating a memory device

A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.

Circuits and methods of a self-timed high speed SRAM

Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power.

Sense amplifier timing circuit

PROCEDURE AND DEVICE FOR A BLIND SRAMZELLE

Semiconductor integrated circuit

DURATION GENERATION CIRCUIT

CONTROL CIRCUIT OF A LINE OF A MEMORY ARRAY

L'invention concerne un circuit mémoire comprenant : un circuit de commande de ligne d'une matrice mémoire comprenant : un premier transistor (54) couplé entre des premier et deuxième nœuds (58, 56) et commandé par un signal de sélection de ligne (SDEC-n) comprenant un niveau haut (VDD) et un niveau bas ; un deuxième transistor (60) commandé par un premier signal (ENDN) et couplé entre le premier nœud (58) et un rail d'alimentation en tension d'une première tension d'alimentation (CVDD), cette première tension d'alimentation (CVDD) étant supérieure au niveau haut (VDD) du signal de sélection de ligne (SDEC-n), ledit premier nœud (58) étant relié à une ligne de la matrice mémoire, ledit deuxième nœud (56) recevant un signal de synchronisation (/CK) ; et un circuit de désactivation de ligne adapté à générer le premier signal (ENDN) et comprenant une cellule de référence et un dispositif à décalage de niveau de tension.

MEMORY DEVICE WITH DELAY TRACKING FOR IMPROVED TIMING MARGIN

메모리 디바이스 내의 감지 증폭기용 셀프 타이머

... 메모리 디바이스 내의 감지 증폭기용 셀프 타이머가 개시된다.

Semiconductor memory device

Semiconductor device

A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Command paths, apparatuses and methods for providing a command to a data block

Command paths, apparatuses, and methods for providing a command to a data block are described. In an example command path, a command receiver is configured to receive a command and a command buffer is coupled to the command receiver and configured to receive the command and provide a buffered command. A command block is coupled to the command buffer to receive the buffered command. The command block is configured to provide the buffered command responsive to a clock signal and is further configured to add a delay to the buffered command, the delay based at least in part on a shift count. A command tree is coupled to the command block to receive the buffered command and configured to distribute the buffered command to a data block.

ADJUSTABLE MEMORY SELF-TIMING CIRCUIT

A static Random Access Memory (RAM) has a sense enable circuit. A user-determinable number of timing cells produces a timing bit line output in response to a wordline enable input. A sense timing control circuit is triggered by the timing bit line output. The sense timing control circuit produces a sense enable signal for enabling a sensing amplifier to read the logic state of memory cells in communication with the sensing amplifier. A user can change the number of timing cells to optimize operation.

Delay calibration oscillators for a memory device

Methods, systems, and devices for delay calibration oscillators for a memory device are described. In some examples, a memory device may include a delay chain operable (e.g., for a calibration operation) in a ring oscillator configuration that includes a pulse generator. The pulse generator may be configured to output a pulse signal responsive to a transition of an input signal. By generating a pulse signal in a feedback loop of a ring oscillator, the ring oscillator may support a cycle that does not rely on both a first transition propagation pass (e.g., a rising edge propagation) and a responsive, opposite transition propagation pass (e.g., a falling edge propagation) through the delay chain, which may support a ring oscillator cycle time (e.g., period) that more closely represents aspects of the delay chain that are meant to be calibrated.

Memory circuit having tracking circuit including series-connected transistors

A memory circuit includes a plurality of memory cells and a tracking circuit. Each memory cell of the plurality of memory cells includes a cell transistor corresponding to a predetermined transistor configuration. The tracking circuit includes a first tracking bit line, a first tracking word line, a reference voltage node, and a first plurality of tracking cells. Each tracking cell of the first plurality of tracking cells includes a cell transistor corresponding to the predetermined transistor configuration. The cell transistors of the first plurality of tracking cells are electrically coupled in series between the first tracking bit line and the reference voltage node, and gate terminals of the cell transistors of the first plurality of tracking cells are electrically coupled with the first tracking word line.

Semiconductor memory read and write access

A semiconductor memory includes a sense amplifier which operates in response to activation of a sense amplifier enable signal and determines logic held in a nonvolatile memory cell according to a voltage of a bit line, the voltage varying with a cell current flowing through a real cell transistor, a replica cell transistor coupled in series between a first node and a ground line, and a timing generation unit. The timing generation unit activates the sense amplifier enable signal when the first node coupled to the ground line via the replica cell transistor changes from a high level to a low level. The replica cell transistor includes a control gate receiving a constant voltage and a floating gate coupled to the control gate. Thus, the activation timing of the sense amplifier can be optimally set in accordance with the electric characteristic of the memory cell.

Semiconductor memory device

SYSTEM AND METHOD FOR MODIFYING ACTIVATION OF A SENSE AMPLIFIER

A memory device and method of performing access operations within such a memory device

A memory device and associated method of accessing the device, the memory device , which may be a System-on-Chip, comprising an array of memory cells 200, 205 arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. The array operates in an array voltage domain with an array voltage supply (core voltage) Vddce. Access circuitry (130, 115, fig 1) is coupled to the plurality of word and bit lines (107, 109 fig 1) to perform memory cell access. At least a part of the access circuitry operates in a peripheral voltage domain with a peripheral voltage supply Vddpe. Control circuitry 250, 230,265 then controls operation of the access circuitry, the control circuitry including self-timed path (STP) delay circuitry 235, 240, 255, 260 which generates a delay indication indicative of an access timing delay associated with ...

Voltage mode sensing for low power flash memory

An electrically erasable flash memory has a memory array (50) comprising at least one row (24, 44) of memory cells (10, 30). Each memory cell has a data state. A voltage sensing circuit (54) is selectively coupled to individual ones of memory cells and configured to bias them with at least one of a bias current and a bias resistance in order to read the data states of the individual selected memory cells. A reference bit Nine (66) provides an indication to the sensing circuit (54) that data on a selected bit line (26) may be accurately read.

Synchronous memory device

동기식 메모리 장치가 제공된다. 동기식 메모리 장치는 독출 명령에 응답하여, 내부 독출 신호를 제공하는 독출 진입 발생 회로, 클럭 재생 회로로 피드백되는 피드백 클럭 신호와, 독출 진입 발생 회로가 내부 독출 신호를 제공하는 데 걸리는 시간과 실질적으로 동일한 시간만큼의 차이를 갖는 진입 트랜스퍼 신호를 제공하는 리플리커 회로, 및 내부 독출 신호를 수신하고, 내부 독출 신호와 진입 트랜스퍼 신호에 응답하여 카스 레이턴시에 대응하는 소정 시간만큼의 차이를 갖는 레이턴시 신호를 제공하는 레이턴시 회로를 포함한다. A synchronous memory device is provided. The synchronous memory device, in response to a read command, has a read entry generation circuit providing an internal read signal, a feedback clock signal fed back to the clock regeneration circuit, and a time substantially equal to the time taken for the read entry generation circuit to provide the internal read signal. A replicator circuit for providing an entry transfer signal having a difference by time, and receiving an internal read signal and providing a latency signal having a difference by a predetermined time corresponding to cas latency in response to the internal read signal and the entry transfer signal. Includes a latency circuit. 동기식 메모리 장치, 리플리커 회로, 레이턴시 회로 Synchronous Memory Devices, Replicator Circuits, Latency Circuits

USING A REFERENCE BIT LINE IN A MEMORY

... 방법, 메모리 및 시스템은 감지 노드(sense node)를 논리 하이 전압 레벨로 충전시키는 것, 및 참조 비트 라인(reference bit line)의 전압이 참조 전압(reference voltage)에 도달하는 시간에 적어도 부분적으로 기초하는 프리차지 기간 동안 비트 라인 및 참조 비트 라인에 전하를 공급하는 것을 포함할 수 있다. 프리차지 기간 후에 비트 라인에 결합되어 있는 메모리 셀이 선택될 수 있고, 클램프 전압은 참조 비트 라인의 전압에 적어도 부분적으로 기초하여 설정될 수 있다. 감지 기간 동안 비트 라인의 전압 레벨이 클램프 전압 레벨보다 작은 경우, 전하가 감지 노드로부터 배출될 수 있고, 감지 기간의 끝 부근에서 감지 노드의 전압 레벨에 적어도 부분적으로 기초하여 메모리 셀의 상태가 판정될 수 있다.

SENSE AMPLIFIER TIMING CIRCUIT, ESPECIALLY INCLUDING STROBE SIGNAL GENERATION CIRCUIT OUTPUTTING STROBE SIGNAL FOR CONTROLLING SENSE AMPLIFIER

PURPOSE: A sense amplifier timing circuit is provided to track process deviation closely in order to generate an optimum operation signal as to a sense amplifier. CONSTITUTION: A sense amplifier(300) has a first and a second differential inputs, a strobe input and a strobe output connected to a data line and a data bar line respectively. A plurality of latches are connected to the data line and the data bar line via a plurality of pass transistors. A control line is connected to the plurality of pass transistors. And a strobe signal generation circuit comprises a dummy control line having duplicated physical characteristics of the control line, and outputs a strobe signal controlling the sense amplifier, and controls delay of the strobe signal according to the variation of resistance of the control line. © KIPO 2006 ...

Semiconductor memory device

SEMICONDUCTOR MEMORY DEVICE, IN WHICH THE STAGE NUMBER OF REPLICA CELLS IS VARIED IN PROGRAMMABLE MANNER

PURPOSE: A semiconductor memory device is provided to supply an optimum start timing to a sense amplifier circuit without increasing layout area. CONSTITUTION: A memory array(100) includes a number of memory cells(106). A sense amplifier circuit(103) amplifies data read in a bit line from a memory cell selected by the memory array. A replica circuit(104A) has the same device as the memory cell, and includes a number of replica cells outputting a signal of a level according to the stage number to a common replica bit line. A sense amplifier control circuit(105) receives a signal of the replica bit line, and performs to control a timing of the signal starting the sense amplifier circuit. The replica circuit includes a switch(110) switching the stage number of an enabling replica cell. © KIPO 2005 ...

Memory apparatus and operating method thereof

PHASE CHANGE MEMORY DEVICE WITH DUMMY CELL ARRAY

A phase change memory device includes a cell array having a phase change resistance cell arranged at an intersection of a word line and a bit line and a dummy cell configured to discharge the bit line in response to a first bit line discharge signal. A column switching unit selectively controls a connection between the bit line and a global bit line in response to a column selecting signal. The dummy cell disconnects a discharging path in response to the first bit line discharge signal in a precharge mode, and discharges the bit line in response to the first bit line discharge signal in an active mode.

Semiconductor memory device having a delay circuit set according to the storage capacity of a memory macro

A delay circuit that delays a signal for controlling data read/write is composed of inverters, capacitors, and switches. The delay time that the delay circuit provides is set by selectively changing over the switches according to the storage capacity of a memory macro. Thus, the delay time most suitable for the storage capacity of the memory macro can be set, which allows the data read/write operation to be speeded up.

Memory timing circuit

A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.

SEMICONDUCTOR STORAGE

PROBLEM TO BE SOLVED: To provide a semiconductor storage which has a timing control circuit compensating signal delay of internal operation, is superior in stability with respect to manufacturing dispersion, and which can operate at high speed. SOLUTION: This semiconductor storage comprises a row detector selecting a row, word lines extending from the row decoder and connected to memory cells, dummy word lines extending from near a start point of the word line almost in parallel to the word line, turning back halfway in the total length, and returning in the vicinity of the start point, and a sense amplifier amplifying data read out from a memory cell selected by the word line in timing in accordance with a signal transmitting through the dummy word line. COPYRIGHT: (C)2002,JPO ...

SEMICONDUCTOR DEVICE

The present invention relates to a semiconductor device capable of controlling data setup/hold timing by each channel. The semiconductor device includes: a buffer unit generating a strobe signal by buffering an outer strobe signal input through a first pad and outputting the strobe signal to a first node of a first input and output line, wherein the buffer unit also generates data by buffering outer data which is input through a second pad and outputs the data to a second node of a second input and output line; a first channel installed in a first direction from the buffer unit and storing the data loaded on the second input and output line by being synchronized with the strobe signal loaded on the first input and output line; and a second channel installed in a second direction from the buffer unit and storing the data loaded on the second input and output line by being synchronized with the strobe signal loaded on the first input and output line. COPYRIGHT KIPO 2016 (31) First data input ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR READING INFOMATION THEREFROM

A memory device and method of performing a write operation in a memory device

The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry is used to assert a wordline signal to activate an addressed memory cell in the array. Write driver circuitry is used to perform a write operation to write a data value into the addressed memory cell, and is responsive to assertion of a write assist enable signal during the write operation to implement a write assist mechanism. Further, control circuitry is used to control timing of assertion of the wordline signal in dependence on timing of assertion of the write assist enable signal. By making the timing of assertion of the wordline signal dependent on the timing at which the write assist enable signal is asserted, it has been found that writeability of the memory cells is significantly improved.

Control device for semiconductor memory

SYSTEM AND METHOD OF OPERATING A MEMORY DEVICE

A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.

Read-Current and Word Line Delay Path Tracking for Sense Amplifier Enable Timing

A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal.

Tracking cell and method

A circuit includes a first power node that receives a first operational voltage having a first operational voltage level and a second power node that receives a second operational voltage having a second operational voltage level different from the first operational voltage level. A memory cell is coupled with the first power node, the memory cell configured to store a logic value, and a tracking cell is coupled with the second power node, the tracking cell configured to generate a signal having a timing responsive to the second operational voltage level. The circuit is configured to read the logic value of the memory cell based on the signal.

Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system

Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.

APPARATUSES AND METHODS FOR MEASURING AN ELECTRICAL CHARACTERISTIC OF A MODEL SIGNAL LINE AND PROVIDING MEASUREMENT INFORMATION

Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.

PULSE WIDTH CONTROL FOR READ AND WRITE ASSIST FOR SRAM CIRCUITS

A system and are described as to adjusting voltages in a memory device, while the device is in sleep mode, to prevent or minimize voltage or current leakage of the device.

VERFAHREN UND VORRICHTUNG FÜR SELBSTGETAKTETES SPEICHERSTEUERUNGSSYSTEM MIT NIEDRIGEM STROMVERBRAUCH

Memory device, has word line-driver that is provided for emitting word line-signal, if driver is activated by word line-trigger signal, and word line that is coupled for receiving and supplying word line signal to number of memory cells

The device (200) has a timing-controller (210) with an input coupled to receive a preload-output signal from a preload-circuit (230), and an output, where the controller is provided for supplying a word line-trigger signal based on the preload- output signal. A word line-driver has an input receiving a word line-trigger signal and an output, where the driver emits a word line-signal, if the driver is activated by the word line-trigger signal. A word line is coupled for receiving and supplying the word line signal to a number of memory cells (240). Independent claims are also included for the following: (1) a method for controlling timings of memory cell bit line preload functions and memory cell word line functions (2) a computer program product for providing executable instructions for controlling timings of bit line preload operations and word line operations within a memory device.

Having determined the time window of the memory device

For tracking the read current of the semiconductor memory of the programmable tracking circuit

CONTROL CIRCUIT OF A LINE OF A MEMORY ARRAY

L'invention concerne un circuit mémoire comprenant : un circuit de commande de ligne d'une matrice mémoire comprenant : un premier transistor (54) couplé entre des premier et deuxième nœuds (58, 56) et commandé par un signal de sélection de ligne (SDEC-n) comprenant un niveau haut (VDD) et un niveau bas ; un deuxième transistor (60) commandé par un premier signal (ENDN) et couplé entre le premier nœud (58) et un rail d'alimentation en tension d'une première tension d'alimentation (CVDD), cette première tension d'alimentation (CVDD) étant supérieure au niveau haut (VDD) du signal de sélection de ligne (SDEC-n), ledit premier nœud (58) étant relié à une ligne de la matrice mémoire, ledit deuxième nœud (56) recevant un signal de synchronisation (/CK) ; et un circuit de désactivation de ligne adapté à générer le premier signal (ENDN) et comprenant une cellule de référence et un dispositif à décalage de niveau de tension. The invention relates to a memory circuit comprising: a line control circuit of a memory array comprising: a first transistor (54) coupled between first and second nodes (58, 56) and controlled by a line selection signal ( SDEC-n) comprising a high level (VDD) and a low level; a second transistor (60) controlled by a first signal (ENDN) and coupled between the first node (58) and a voltage supply rail of a first supply voltage (CVDD), this first supply voltage ( CVDD) being greater than the high level (VDD) of the line selection signal (SDEC-n), said first node (58) being connected to a line of the memory array, said second node (56) receiving a synchronization signal ( / CK); and a line deactivation circuit adapted to generate the first signal (ENDN) and comprising a reference cell and a voltage level shifter.

Semiconductor Memory Apparatus

Memory array reset read operation

Apparatus for reducing write minimum supply voltage for memory

Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

Memory circuit

A memory circuit is disclosed. The circuit includes a plurality of memory cells, a first tracking word line driver, and a second tracking word line driver. The first tracking word line driver outputs a first signal in response to a first region of the plurality of memory cells being accessed, the first signal having a first pulse width. The second tracking word line driver outputs a second signal in response to a second region of the plurality of memory cells being accessed, the second signal having a second pulse width, the second pulse width being different from the first pulse width.

Nonvolatile memory system including nonvolatile memory device and memory controller and operating method of memory controller

A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is configured to count a clock to generate a current time, program dummy data at predetermined memory cells among the plurality of memory cells at a power-off state, detect a charge loss of the predetermined memory cells when a power-on state occurs after the power-off state, and restore the current time based on the detected charge loss.

Bit-Line Discharge Assistance in Memory Devices

One embodiment is an apparatus that has a memory array, a discharge device, and a discharge assistance controller. The memory array has memory cells arranged in at least one column that is coupled to a read bit line, and the discharge device is configured to provide discharge assistance to the read bit line. The discharge assistance controller is configured to modify duration of the discharge assistance in correlation with capacitance of the read bit line.

RESISTANCE CHANGE MEMORY

According to one embodiment, a resistance change memory includes the following structure. A memory cell includes a resistance change element and a transistor. A sense amplifier reads data stored in the memory cell. A control circuit controls the reading by the sense amplifier, and outputs a first signal to control the start of precharging of the bit line, a second signal to control a cell current running through the memory cell, and a third signal to control the start of the activation of the sense amplifier. A second word line has an interconnect structure similar to that of the first word line. A monitor circuit detects a first signal delay in the second word line, and outputs the first signal to the sense amplifier in accordance with the first signal delay.

SEMICONDUCTOR MEMORY DEVICE HAVING REPLICA CIRCUIT

A semiconductor memory device includes a memory cell array, word line, row decoder, bit line, sense amplifier, dummy cell array, dummy bit line, sense amplifier activation circuit, and signal interconnection. The word line is connected to memory cells arrayed in the column direction. The row decoder is connected to the word line. The bit line is connected to memory cells arrayed in the row direction. The sense amplifier is connected to the bit line. Dummy cells are arrayed in the row direction between the row decoder and the memory cell array. The dummy bit line is connected to the dummy cells. The sense amplifier activation circuit transmits a sense start signal for setting a sense start timing to the sense amplifier through the signal interconnection. In this arrangement, the signal delay of the word line is set to be equal to that of the signal interconnection.

SRAM restore tracking circuit and method

A novel and useful SRAM restore tracking circuit adapted to improve the tracking of SRAM cell behavior for different PVT corners. The SRAM array access path is mainly influenced by two stages: (1) the wordline (WL) delay and (2) the SRAM cell delay. These two stages are usually the most sensitive for process variation in the memory access path. The restore tracking circuit incorporates two novel topologies for enhanced tracking to SRAM cell behavior. The first topology is a circuit that functions to mimic the wordline load and delay characteristics. The WL stage is very sensitive to process variation due to the large load it must drive and the usually relatively poor slope (i.e. depending on the number of cells the WL). The second topology is a circuit that mimics the SRAM cell load and delay characteristics. The SRAM cell is very sensitive to process variation due to its very small device features and the high number of cells in the memory array.

DQS for data from a memory array

A memory comprises a first circuit, a second circuit, and a latch. The first circuit is configured to provide a first signal indicating an earliest time valid data is available from a memory array in response to a read command. The second circuit is configured to provide a second signal indicating a latest time valid data is available from the memory array in response to the read command. The latch is configured to be connected to a data line coupled to the memory array in response to the first signal and disconnected from the data line in response to the second signal to latch data read from the memory array.

PRE-CHARGE TRACKING OF GLOBAL READ LINES IN HIGH SPEED SRAM

In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle. A dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the SRAM forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle.

TRACKING CIRCUIT

A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal.

Method and Apparatus for a Dummy SRAM Cell

A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and second bit line output circuits. The dummy SRAM cell includes the same first and second subsets of transistors, with the first transistors configured as a dummy bit line output circuit having substantially the same electrical characteristics as the first bit line output circuit of the standard SRAM cell. Further, the second transistors, which are not otherwise needed for the dummy SRAM cell function, are reconfigured as a voltage tie circuit for the dummy bit line output. Using the second transistors for this purpose obviates the need to add additional transistors to form a voltage tie circuit for configuring the dummy bit line output circuit as a load or driver for the dummy bit line.

Semiconductor storage device

According to one embodiment, a dummy cell simulates an operation of a memory cell. A main dummy bit line transmits a signal read out from the dummy cell. An inverter makes a sense amplifier circuit to operate based on a potential of the main dummy bit line. n (n is a positive integer) number of auxiliary dummy bit lines are provided. A switching element connects at least one of the n number of auxiliary dummy bit lines to the main dummy bit line.

Semiconductor memory device

A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.

Semiconductor memory device

A row decoder is disposed on a side of a memory cell array in a column direction and supplies one of word lines with a first drive signal for selecting one of memory cells. A dummy word line is formed extending in the column direction. A dummy bit line is formed extending in a row direction. At least one of the dummy word line and the dummy bit line is disposed outside of the memory cell array. The row decoder outputs a second drive signal toward a sense amplifier circuit via the dummy bit line and the dummy word line.

Memory circuit and a tracking circuit thereof

Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell.

Memory device with robust write assist

A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.

Memory apparatus

A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The reference delay signal generator is configured to receive the input signal and to delay the input signal according to a plurality of reference delays, so as to generate a plurality of reference delay signals. The signal comparison controller is configured to receive the reference delay signals and the comparison signal. According to a time difference between the comparison signal and the reference delay signals, the signal comparison controller is configured to generate a selected signal and to generate a delay control signal according to the selected signal.

SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME

A device includes first memory blocks each including a first local bit line, first memory cells connected to the first local bit line and a first hierarchy switch connected between a first global bit line and the first local bit line, a dummy global bit line connected to the second node of a first sense amplifier, a dummy block including a dummy local bit line, dummy memory cells connected to the dummy local bit line and a dummy hierarchy switch connected between the dummy global bit line and the dummy local bit line, and a control circuit supplied with address information and configured to respond to the address information designating any one of the first memory blocks to turn ON each of the dummy hierarchy switch of the dummy block and the first hierarchy switch of one of the first memory blocks designated by the address information. 1. A device comprising:a first sense amplifier including first and second nodes;a first global bit line connected to the first node of the first sense amplifier;a plurality of first memory blocks each including a first local bit line, a plurality of first memory cells connected to the first local bit line and a first hierarchy switch connected between the first global bit line and the first local bit line;a dummy global bit line connected to the second node of the first sense amplifier;a dummy block including a dummy local bit line, a plurality of dummy memory cells connected to the dummy local bit line and a dummy hierarchy switch connected between the dummy global bit line and the dummy local bit line; anda control circuit supplied with address information and configured to respond to the address information designating any one of the first memory blocks to turn ON each of the dummy hierarchy switch of the dummy block and the first hierarchy switch of one of the first memory blocks designated by the address information.2. The device as claimed in claim 1 ,wherein the device further comprises a second sense amplifier including third ...

Write self timing circuitry for self-timed memory

A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.

Memory components and controllers that calibrate multiphase synchronous timing references

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

TRACKING SIGNALS IN MEMORY WRITE OR READ OPERATION

A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal. 1. A signal generating circuit comprising:a first circuit;a tracking circuit; anda delay circuit coupled with the first circuit and the tracking circuit, the first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal;', 'the tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal; and', 'the delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal., 'wherein'}2. The signal generating circuit of claim 1 , whereinthe delay circuit is configured to generate the output signal for use in deactivating a write signal of a memory cell.3. The signal generating circuit of claim 1 , whereinthe first circuit is configured to generate the second clock signal and the at least one first tracking signal in a similar manner.4. The signal generating circuit of claim 1 , whereinthe first circuit is configured to generate a rising edge of the second clock signal based on a rising edge of the first clock signal and to generate a falling edge of the second clock signal based on a falling edge of the output signal; andthe first circuit is configured to generate a rising edge of the at least one first tracking signal based ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal. 1. A semiconductor memory device comprising:a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region through data is input/output, respectively; anda second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.2. The semiconductor memory device of claim 1 , wherein the plurality of delay times includes delay times in which a data transmission line claim 1 , through which the data is input/output claim 1 , has been modeled corresponding to arrangement locations of a plurality of unit memory regions.3. The semiconductor ...

Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay

A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

TSV Check Circuit With Replica Path

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

MEMORY DEVICE HAVING COMMAND WINDOW GENERATOR

A memory device including a command window generator is provided. The command window generator is configured to generate a delay signal by converting a delay time between a clock signal input to a write path circuit and a clock signal output to a write path replica circuit into a number of cycles of an internal clock signal, by using the write path circuit and the write path replica circuit, and generate a command window to correspond to a data window using the delay signal. The delay window may correspond to a burst length of write data. 1. A command window generator configured to generate a command window for processing data associated with a command after a certain latency from receipt of the command , the command window generator comprising:a clock freezer circuit configured to receive a first clock signal divided from an input clock signal and generate a second clock signal from the first clock signal, where the second clock signal has a freezing section corresponding to a logic low section of a clock freezing signal;a first circuit configured to receive the second clock signal as an input, and output the second clock signal after a first delay time;a second circuit having the same structure as the first circuit and configured to receive an output of the first circuit as an input, and output a third clock signal after the first delay time; anda delay measure circuit configured to receive the second clock signal and the third clock signal as inputs, generate a delay signal by converting a delay time between the second clock signal and the third clock signal into a number of cycles of the input clock signal, and generate the command window to correspond to a data window of the data using the delay signal.2. The command window generator of claim 1 , wherein the delay measure circuit generates a latency control signal generated at a point in which the delay signal is subtracted from the latency claim 1 , andthe first circuit receives the latency control signal as ...

SEMICONDUCTOR DEVICE

A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier. 2. The semiconductor device according to claim 1 ,wherein a gate length of the second MIS transistor is longer than a gate length of the first MIS transistor.3. The semiconductor device according to further comprising:a word line driving circuit including a third MIS transistor and operable to drive the word line,wherein a gate length of the second MIS transistor is longer than a gate length of the third MIS transistor.4. The semiconductor device according to claim 1 ,wherein the first wiring forms at least one both-way wiring and includes a first dummy bit line used as an outward wiring and a second dummy bit line used as a homeward wiring. This application is a Continuation of U.S. application Ser. No. 15/367,829, filed Dec. 2, 2016, which is a Continuation of U.S. application Ser. No. 14/981,195, filed Dec. 28, 2015, now patented as U.S. Pat. No. 9,542,999, which is a Continuation of U.S. application Ser. No. 14/321,169, filed Jul. 1, 2014, now patented as U.S. Pat. No. 9,281,017, which is a Continuation of U.S. application Ser. No. 14/026,575, filed Sep. 13, 2013, now patented as U.S. Pat. No ...

MOBILE DEVICE AND A METHOD OF CONTROLLING THE MOBILE DEVICE

A mobile device including: a storage device; a system-on-chip (SOC) including a central processing unit (CPU) and a memory interface configured to access the storage device in response to a request of the CPU; and a working memory including an input/output (I/O) scheduler and a device driver, the I/O scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue, the device driver configured to adjust the performance of the mobile device based on the number of requests in the sync queue. 1. A mobile device , comprising:a storage device;a system-on-chip (SOC) including a central processing unit (CPU) and a memory interface configured to access the storage device in response to a request of the CPU; anda working memory including an input/output (I/O) scheduler and a device driver,the I/O scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue,the device driver configured to adjust the performance of the mobile device based on the number of requests in the sync queue.2. The mobile device of claim 1 , wherein when the sync queue and the async queue are empty a low power mode of the mobile device is entered.3. The mobile device of claim 1 , wherein the CPU is a heterogeneous multi-core CPU.4. The mobile device of claim 1 , wherein the working memory includes a dynamic random access memory (DRAM).5. The mobile device of claim 1 , wherein the storage device includes a nonvolatile memory device.6. The mobile device of claim 1 , wherein the synch queue includes a plurality of read requests.7. The mobile device of claim 1 , wherein the async queue includes a plurality of write requests.8. The mobile device of claim 1 , wherein the ...

SIGNAL CONTROL CIRCUIT, INFORMATION PROCESSING APPARATUS, AND DUTY RATIO CALCULATION METHOD

A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount. 1. A signal control circuit , comprising:a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; anda ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount.2. The signal control circuit according to claim 1 , wherein the delay acquisition circuit is configured to obtain the first delay amount such that rise of a delayed signal formed by adding the first delay amount to the input signal is located to be aligned with the fall or the rise of the reference signal and obtain the second delay amount such that fall of the delayed signal formed by adding the second delay amount to the input signal is located to be aligned with the fall or the rise of the reference signal.3. The signal control circuit according to claim 1 , wherein the delay acquisition circuit is configured to obtain the first delay amount by repeatedly adding a delay amount of a first predetermined phase difference unit to the input signal and the second delay amount by repeatedly adding a delay amount of a second predetermined phase ...

Internal signal monitoring circuit

Disclosed herein is an apparatus that includes a first circuit configured to measure a first time period from a first active edge of one of plurality of internal signals to a second active edge of one of the plurality of internal signals, and a second circuit configured to compare the first time period with a second time period to generate an alert signal.

Memory device with control circuitry for generating a reset signal in read and write modes of operation

A memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation.

CONTROLLER AND OPERATING METHOD THEREOF

A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period. 1. A controller that controls an operation of a semiconductor memory device including a plurality of memory blocks , the controller comprising:a temperature sensing unit configured to generate temperature information by sensing a temperature of the semiconductor memory device;a period storage unit configured to update an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information; anda command generating unit configured to generate the dummy read command, based on the output period.2. The controller of claim 1 , wherein the period storage unit includes a lookup table that includes an output period corresponding to each temperature range claim 1 ,wherein the period storage unit updates a currently applied output period with reference to the lookup table.3. The controller of claim 1 , wherein claim 1 , as the temperature measured by the temperature sensing unit increases claim 1 , the period storage unit updates a shorter period as the output period.4. The controller of claim 1 , wherein the command generating unit generates the dummy read command by comparing an output reference time with the output period claim 1 , where the output reference time indicates a period between a time when a preceding dummy read command was generated and a current time.5. The controller of ...

Sram read multiplexer including replica transistors

A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

MEMORY DEVICE, DRIVING METHOD THEREOF, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively. 1. (canceled)2. A semiconductor device comprising: a first transistor; and', 'a second transistor;, 'a memory cell comprisinga third transistor;a fourth transistor;a first line;a second line;a third line;a fourth line;a read circuit; anda sense amplifier,wherein one of a source and a drain of the first transistor is electrically connected to the first line,wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,wherein one of a source and a drain of the second transistor is electrically connected to the second line,wherein the other of the source and the drain of the second transistor is electrically connected to the third line,wherein one of a source and a drain of the third transistor is electrically connected to the fourth line,wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,wherein the other of the source and the drain of the fourth transistor is electrically connected to the third line,wherein a first input terminal of the read ...

PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY

Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances. 115-. (canceled)16. A method for introducing a programmable delay in a memory device comprising a plurality of conducting layers and at least one capacitor in a path of a signal to be delayed and being formed in a portion of the plurality of conducting layers , the method comprising:controlling the at least one capacitor being in the path of the signal to be delayed using at least one switch coupled to the at least one capacitor; andcontrolling a state of the at least one switch based upon a selection signal.17. The method according to claim 16 , wherein the memory device further comprises memory cell columns and a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is part of the memory cell columns.18. The method according to claim 16 , wherein the memory device further comprises a plurality of word line drivers adjacent a reference column; and wherein the portion of the conducting layers defining the at least one capacitor is over the plurality of word line drivers.19. The method according to claim 16 , wherein the memory device further comprises a word line driver in a word line decoder adjacent a reference column; and wherein the ...

MEMORY ARRAY RESET READ OPERATION

Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input. 1. A method , comprising:identifying a part of a read command for setting at least one portion of a memory array to a temporary state;identifying the at least one portion of the memory array based at least in part on the part of the read command; andexecuting the part of the read command on the at least one portion of the memory array based at least in part on identifying the at least one portion of the memory array.2. The method of claim 1 , wherein executing the part of the read command comprises:performing a read recovery part of a read operation, wherein the read operation comprises the read recovery part and a data sense part.3. The method of claim 1 , further comprising:increasing a voltage applied to all word lines associated with the at least one portion to a first voltage above a threshold voltage of memory cells of the at least one portion;increasing a voltage applied to at least one gate of at least one select gate device of the at least one portion to a second voltage above a second threshold voltage of the at least one select gate device; andsetting a voltage applied to a source, a drain, a bit line, or a combination thereof, of the at least one portion to a third voltage.4. The method of claim 3 , further comprising:decreasing the voltage applied to all word lines from the first voltage to a fourth voltage based at least in part on achieving the first voltage; anddecreasing the voltage applied to the at least one gate of the at least one select gate device from the second voltage to below the second threshold ...

SEMICONDUCTOR APPARATUS AND METHOD FOR CONTROLLING SEMICONDUCTOR APPARATUS

According to one embodiment, there is provided a semiconductor apparatus including a first chip and :a, second chip. The first chip is electrically connected to a terminal to which a signal from a host device is input. The second chip is electrically connected to the first chip. The second chip has a first duty adjustment circuit. The first chip has a second duty adjustment circuit. The first duty adjustment circuit performs first calibration operation in a first period. The second duty adjustment circuit performs second calibration operation in a second period. The first period and the second period have an overlapping period. 2. The semiconductor apparatus according to claim 1 , whereinthe second chip hasa data terminal,a strobe terminal,a first output cutoff circuit that may deactivate the data terminal, anda second output cutoff circuit that may deactivate the strobe terminal, andin a state in which the first output cutoff circuit deactivates the data terminal and the second output cutoff circuit deactivates the strobe terminal, the first duty adjustment circuit performs the first calibration operation, and the second duty adjustment circuit performs the second calibration operation.3. The semiconductor apparatus according to claim 2 , whereinthe second chip further has a read enable terminal, andin the state in which the first output cutoff circuit deactivates the data terminal and the second output cutoff circuit deactivates the strobe terminal, the first duty adjustment circuit performs the first calibration operation in the first period by means of a signal received via the read enable terminal.4. The semiconductor apparatus according to claim 2 , further comprising:a third chip electrically connected to the first chip,wherein the third chip hasa third duty adjustment circuit,a data terminal,a strobe terminal,a third output cutoff circuit that may deactivate the data terminal, anda fourth output cutoff circuit that may deactivate the strobe terminal,the ...

Adjustment method

Methods and devices for adjusting a read threshold voltage of bitlines are provided. One such method includes adjusting a read threshold voltage of bitlines coupled to memory points of a memory circuit. The read threshold voltage is initially set to a first value. First data are written in the memory points and second data are read from the memory points. The second data are compared to the first data, and the threshold voltage is decreased by a second value in response to a comparison error of one of the second data with the corresponding first data.

MEMORY DEVICE, DRIVING METHOD THEREOF, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively. 1. A memory device comprising:a first cell;a second cell;a read circuit;a first wordline;a second wordline;a third wordline;a first bitline;a second bitline;a third bitline;a sourceline; anda first wiring,wherein the first cell includes a first transistor and a second transistor,wherein a gate, a first terminal, and a second terminal of the first transistor are electrically connected to the third wordline, the third bitline, and a first terminal of the second transistor, respectively,wherein a gate and a second terminal of the second transistor are electrically connected to the first wiring and the sourceline, respectively,wherein the second cell includes a third transistor, a fourth transistor, and a capacitor,wherein a gate, a first terminal, and a second terminal of the third transistor are electrically connected to the first wordline, the first bitline, and a gate of the fourth transistor, respectively,wherein a first terminal and a second terminal of the capacitor are electrically connected to the gate of the fourth transistor and the second wordline, respectively,wherein a first terminal and a second ...

Non-volatile Memory Device With Stored Index Information

A memory device that includes a memory array having pluralities of non-volatile memory cells, a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, and a controller. The controller is configured to erase the pluralities of non-volatile memory cells, set each of the index memory cells to a first state, and program first data into the memory array by reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state, programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and setting the first one of the index memory cells to a second state different from the first state.

MULTIPLE DATA RATE MEMORY

There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch. The multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse. 1. A multiple data rate memory comprising:a clock splitting circuit; anda multiplexing address latch;wherein the clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch;wherein the multiplexer comprises a first enable switch that is activated by the first internal clock signal and a second enable switch that is activated by the second internal clock signal, and wherein each of the first and second enable switches connects an output of the multiplexer to ground via an address signal-dependent switch; andwherein the multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse.26.-. (canceled)7. The multiple data rate memory according to claim 16 , wherein both the first and second enable switches connect an output of the multiplexer to ground via a single address signal-dependent switch that is activated by a multiple data rate address signal comprising both the first address signal and the second address signal.8. The multiple data rate memory according to claim 7 , wherein the multiplexer is provided with an input through which both the first address signal and the second address signal are received as a multiple data rate ...

SEMICONDUCTOR DEVICE HAVING MODE REGISTER

Disclosed herein is an apparatus that includes a first circuit that activates first and second timing signals in response to a first command and activates the second timing signal in response to a second command, a second circuit that amplifies a first data read out from a first memory area in response to the first command in synchronization with the first timing signal, and a third circuit that outputs one of the first data output from the second circuit and a second data read out from a second memory area in response to the second command, in synchronization with the second timing signal. 1. An apparatus comprising:a memory cell array;a mode register storing a setting parameter;a command control circuit that activates a timing signal in response to a mode-register read command;a FIFO circuit that outputs the setting parameter read out from the mode register in response to the timing signal; anda signal line for transmitting the timing signal, a first line section having one end connected to the command control circuit, the first line section including a portion extending along the memory cell array; and', 'a second line section having one end connected to another end of the first line section and another end of the second line section connected to the FIFO circuit, the second line section including a portion extending along the first line section., 'wherein the signal line includes2. The apparatus of claim 1 , further comprising a delay circuit inserted into the signal line claim 1 , wherein the delay circuit delays the timing signal.3. The apparatus of claim 2 , wherein the delay circuit is connected to the another end of the first line section.4. The apparatus of claim 2 , wherein the delay circuit is inserted into the first line section.5. The apparatus of claim 1 , further comprising a read/write amplifier that outputs a read data read out from the memory cell army to the FIFO circuit in synchronization with the timing signal.6. The apparatus of claim 5 , ...

TSV CHECK CIRCUIT WITH REPLICA PATH

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path. 1. An apparatus comprising:a first semiconductor chip;first and second TSVs penetrating the first semiconductor chip;a first path including the first TSV;a second path including the second TSV;a first charge circuit configured to charge the first path;a second charge circuit configured to charge the second path;a first discharge circuit configured to discharge the first path;a second discharge circuit configured to discharge the second path; anda comparator circuit configured to compare a potential of the first path with a potential of the second path.2. The apparatus as claimed in claim 1 , wherein the first and second charge circuits are configured to charge the first and second paths simultaneously.3. The apparatus as claimed in claim 1 , wherein the first and second discharge circuits are configured to discharge the first and second paths simultaneously.4. The apparatus as claimed in claim 1 , further comprising a second semiconductor chip on which the first semiconductor chip is stacked claim 1 ,wherein the first and second discharge circuits are formed on the second semiconductor chip.5. The apparatus as claimed in claim 4 ,wherein the first semiconductor chip is a memory core chip, andwherein the second semiconductor chip is an interface chip.6. The apparatus as claimed in claim 5 , further comprising a third semiconductor chip stacked on the first and second semiconductor chips ...

Control method and controller of program suspending and resuming for memory

A memory system includes a memory cell array and a controller coupled to the memory cell array. The controller is configured to control applying a first program voltage to a word line to program memory cells in the memory cell array, the memory cells being coupled to the word line, and in response to receiving a suspend command, control applying a positive bias discharge voltage to the word line when the first program voltage ramps down.

INTEGRATED CIRCUIT

An integrated circuit includes: a delay circuit suitable for delaying one or more input signals; a toggle sensing circuit suitable for sensing whether or not the one or more input signals toggle; and a replica delay circuit suitable for delaying one or more clock signals in a section where no toggle of the one or more input signals is sensed by the toggle sensing circuit. 1. An integrated circuit , comprising:a delay circuit suitable for delaying one or more input signals;a toggle sensing circuit suitable for sensing whether or not the one or more input signals toggle; anda replica delay circuit suitable for delaying one or more clock signals in a section where no toggle of the one or more input signals is sensed by the toggle sensing circuit.2. The integrated circuit of claim 1 , wherein the one or more input signals include a strobe signal and a complementary strobe signal.3. The integrated circuit of claim 2 , wherein the one or more clock signals include a clock signal and a complementary clock signal.4. The integrated circuit of claim 3 , wherein the strobe signal and the complementary strobe signal are signals for strobing data received by the integrated circuit claim 3 , andwhen the strobe signal and the complementary strobe signal toggle, the strobe signal and the complementary strobe signal have the same frequency as a frequency of the clock signal and the complementary clock signal.5. The integrated circuit of claim 3 , wherein the delay circuit includes:a delay line suitable for delaying the strobe signal; anda complementary delay line suitable for delaying the complementary strobe signal.6. The integrated circuit of claim 5 , wherein the replica delay circuit includes:a replica delay line having the same configuration as the delay line; anda replica complementary delay line having the same configuration as the complementary delay line.7. The integrated circuit of claim 6 , further comprising:an input control circuit suitable for selectively transferring ...

MEMORY CIRCUIT INCLUDING TRACKING CIRCUIT

A memory circuit including: memory cells, each including a storage cell transistor; a first tracking bit line; and a tracking circuit, electrically coupled between a first tracking word line and a reference voltage node, including a first set of first tracking cells, each first tracking cell including a first cell transistor having a same transistor configuration as each storage cell transistor; and wherein: a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution that exhibits a weak bit current value; a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell statistical distribution that exhibits a first strong bit current value; and a first quantity of the first tracking cells is sufficient to cause the first strong bit current value to be equal to or less than the weak bit current value. 1. A memory circuit comprising:memory cells arranged in an array, each memory cell including a storage cell transistor corresponding to a predetermined transistor configuration;a first tracking bit line;a first tracking word line;a reference voltage node, a first terminal of the first tracking bit line being electrically coupled to the reference voltage node; and 'a first set of first tracking cells, each first tracking cell including a first cell transistor corresponding to the predetermined transistor configuration, gate terminals of the first cell transistors being electrically coupled with the first tracking word line; and', 'a tracking circuit electrically coupled between the first tracking word line and the reference voltage node, the tracking circuit including a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution under a predetermined operation setting which exhibits a weak bit current value;', 'a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell ...

READING FROM A MODE REGISTER HAVING DIFFERENT READ AND WRITE TIMING

A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register. 1. A memory device , comprising:a mode register to store configuration information to control operation of the memory device, wherein a write of configuration information directly to the mode register by a host takes less time than a read of the configuration information directly from the mode register by the host; anda communication register separate from the mode register to provide data for a read of the configuration information by the host from the mode register, wherein in response to a request by the host to read the mode register, the mode register to copy the configuration information from the mode register to the communication register, to enable the host to read the configuration information from the communication register instead of directly from the mode register.2. The memory device of claim 1 , wherein the mode register comprises a decision feedback equalization (DFE) configuration mode register.3. The memory device of claim 1 , wherein the memory device is to receive a polling request from the host after request by the host to read the mode register claim 1 , to determine if the communication ...

OFFSET CANCELLATION

Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel. 1. A method , comprising:determining that an active termination of a channel for communicating data with a controller is interrupted,communicating a calibration signal on the channel based at least in part on determining that the active termination is interrupted;detecting, at a receiver coupled with the channel and based at least in part on the calibration signal, an offset associated with a reference voltage for identifying signals received on the channel; andcalibrating the receiver to compensate for the offset based at least in part on the detecting.2. The method of claim 1 , further comprising:driving the reference voltage on the channel, wherein communicating the calibration signal is based at least in part on driving the reference voltage on the channel.3. The method of claim 2 , wherein the reference voltage driven on the channel is unmodified by the controller based at least in part on a termination of the controller at the channel.4. The method of claim 1 , further comprising:identifying a voltage level that corresponds to a transition from a first logic state to a second logic ...

OPERATING METHOD OF A MAGNETIC MEMORY DEVICE

An operating method of a magnetic memory device may include: a first step of retrieving write data to be written to a plurality of magnetic memory cells sharing a bit line according to a write request, the write data including more of a first type of data than a second type of data; a second step of writing the first type of data simultaneously to all cells of the plurality of magnetic memory cells; and a third step of writing the second type of data to a portion of the plurality of magnetic memory cells, the second type of data being different from the first type of data. 120-. (canceled)21. An operating method of a magnetic memory device , the method comprising:a first step of retrieving write data to be written to a plurality of magnetic memory cells sharing a bit line according to a write request, the write data including more of a first type of data than a second type of data;a second step of writing the first type of data simultaneously to all cells of the plurality of magnetic memory cells; anda third step of writing the second type of data to a portion of the plurality of magnetic memory cells, the second type of data being different from the first type of data.22. The operating method of claim 21 , wherein the second step comprises:blocking a current path passing through the plurality of magnetic memory cells; andapplying a current parallel to the memory cells through the bit line.23. The operating method of claim 21 , wherein the third step comprises:forming a current path passing through only one magnetic memory cell of the portion of the magnetic memory cells; andapplying a first current to the one magnetic memory cell; andapplying a second current parallel to the one magnetic memory cell.24. The operating method of claim 21 , wherein the magnetic memory device comprising:a bit line;a plurality of source lines;a plurality of normal cells coupled between the bit line and the plurality of source lines, each normal cell comprising a magnetic resistance ...

Margin free pvt tolerant fast self-timed sense amplifier reset circuit

In described embodiments, a circuit for providing a margin free PVT tolerant fast self-timed sense amplifier reset includes a sense amplifier coupled between a complementary pair of first and second bitlines in a memory cell, a first and second PMOS drivers connected to internal nodes of the sense amplifier, respectively, and outputting a first and second output signals, wherein the second output signal is inverted by an inverter to form an inverted output signal, a read detect block receiving the first and inverted output signals and generating a transition detect signal that is latched by a cross-coupled inverters and employed to generate a sense amplifier enable signal with a global sense amplifier enable signal, and a push-pull logic formed by a NMOS and a PMOS in series to generate an output of the circuit.

Offset cancellation

Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

Tracking cell and method

A circuit includes a first power node that receives a first operational voltage having a first operational voltage level and a second power node that receives a second operational voltage having a second operational voltage level different from the first operational voltage level. A memory cell is coupled with the first power node, the memory cell configured to store a logic value, and a tracking cell is coupled with the second power node, the tracking cell configured to generate a signal having a timing responsive to the second operational voltage level. The circuit is configured to read the logic value of the memory cell based on the signal.

Memory components and controllers that calibrate multiphase synchronous timing references

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

AREA-EFFICIENT PROCESS-AND-TEMPERATURE-ADAPTIVE SELF-TIME SCHEME FOR PERFORMANCE AND POWER IMPROVEMENT

In certain embodiments, a method and apparatus for adjusting the timing of a sense-amplifier read operation in an SRAM integrated memory circuit to overcome process-and-temperature variations are disclosed. A charge-injection pull-up transistor is provided to adjust the rate at which a signal line (e.g., a tracking bit line (TBL) and/or a clock signal (e.g., GCLKB)) transitions from one voltage level to another voltage level. A process-and-temperature-dependent bias circuit is provided to control the charge-injection pull-up transistor. The bias circuit causes the charge-injection pull-up transistor to adjust the discharge rate or transition rate of the signal line to compensate for timing delays caused by process or temperature variations. 1. A bias circuit for providing a process-or-temperature-dependent bias signal , the bias circuit comprising:a first transistor connected to a first supply-voltage source;a current source connected to the first transistor and an output node ; and (i) inversely related to the operating temperature of the bias circuit, and', '(ii) inversely related to a switching speed of at least the first transistor, wherein the switching speed is a function of a manufacturing process for manufacturing the bias circuit., 'one or more load cells connected to the output node and having a resistance that is at least one of2. The bias circuit of claim 1 , wherein the current source is a constant-current source.3. The bias circuit of claim 1 , wherein the current source comprises a second transistor comprising a drain terminal connected to the first transistor claim 1 , a gate terminal connected to its drain terminal claim 1 , and a source terminal connected to the output node.4. The bias circuit of claim 1 , wherein bias circuit is integrated on an integrated memory circuit claim 1 , and the one or more load cells have electrical characteristics that are similar to one or more memory cells that are also integrated on the integrated memory circuit ...

WRITE-TRACKING CIRCUITRY FOR MEMORY DEVICES

A write-tracking circuit for a writable memory array has one or more dummy memory cells and is configured to write different values to the one or more dummy memory cells. Durations of pulses applied to word lines of the memory array during write operations are controlled based on durations of writing the different values to the one or more dummy memory cells. In at least some embodiments, the write-tracking circuit is configured to write the different values to the one or more dummy memory cells during a single write operation. In at least some embodiments, the write-tracking circuit is configured to write the different values to at least one of the one or more dummy memory cells during different write operations. 1. An apparatus comprising:{'b': '102', 'a memory array (e.g., ) of memory cells arranged in at least one row;'}a word line (e.g., WL) configured to control access to the memory cells in the at least one row; and{'b': 114', '200', '208', '1', '208', '2, 'a write-tracking circuit (e.g., and ) comprising one or more dummy memory cells (e.g., () and ()), whereinthe write-tracking circuit is configured to write a first value and a second value, different from the first value, to the one or more dummy memory cells; anddurations of pulses applied to the word line during write operations of the memory array are controlled based on durations of writing the first and second values to the one or more dummy memory cells.2. The apparatus of claim 1 , wherein the write-tracking circuit is configured to write (i) the first value to a first dummy memory cell during a first write operation of the write-tracking circuit and (ii) the second value to the first dummy memory cell during a second write operation of the write-tracking circuit claim 1 , subsequent to the first write operation.3. The apparatus of claim 2 , further comprising reset-signal generation circuitry configured to control a reset signal based on durations of writing the first and second values to the first ...

Memory Device Having Variable Impedance Memory Cells and Time-To-Transition Sensing of Data Stored Therein

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

MULTI-CYCLE WRITE LEVELING

A memory controller includes logic to determine corresponding reference voltage values and delay values for one or more memory devices. The memory controller includes a command-address (CA) interface to send a command to a memory device to set a reference voltage value of the memory device to a test value, a data interface to write a data pattern to the memory device and read the data pattern from the memory device, and test reference voltage logic to perform a density check on at least a portion of the data pattern read from the memory device and determine whether the test value is a potential reference voltage value based on the density check. An operational reference voltage value selected from one or more potential reference voltage values may be used to determine a delay value. 1. A method comprising:setting a reference voltage value of a memory device to a test value;writing a first data pattern to the memory device;reading the first data pattern from the memory device;performing a density check on at least a portion of the first data pattern read from the memory device; anddetermining whether the test value is a potential receiver reference voltage value, for the memory device, based on the density check.2. The method of claim 1 , further comprising claim 1 , for each of one or more additional test values:setting the reference voltage value of the memory device to the additional test value;writing the first data pattern to the memory device;reading the first data pattern from the memory device;performing a density check on at least a portion of the first data pattern read from the memory device; anddetermining whether the additional test value is a potential reference voltage value based on the density check.3. The method of claim 2 , further comprising claim 2 , determining an operational reference voltage value based on the test values determined as potential reference voltage values.4. The method of claim 3 , further comprising:setting the reference ...

Tracking circuit

A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined.

NON-VOLATILE MEMORY DEVICE HAVING DUMMY CELLS AND MEMORY SYSTEM INCLUDING THE SAME

A non-volatile memory device includes a cell string, a ground select transistor, and at least one dummy cell. The cell string includes at least one memory cell. The at least one dummy cell is provided between the at least one memory cell and the ground select transistor and is connected to a bit line. A controller executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell to be lower than a threshold voltage of the at least one dummy cell in at least a part of a pre-charge period. 1. A non-volatile memory device , comprising:a cell string comprising at least one memory cell, a ground select transistor, and at least one dummy cell between the at least one memory cell and the ground select transistor and connected to a bit line; anda controller that executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell to be lower than a threshold voltage of the at least one dummy cell in at least a part of a pre-charge period.2. The non-volatile memory device according to claim 1 , further comprising:a page buffer connected to the bit line,wherein the page buffer applies a pre-charge voltage to the bit line in the pre-charge period.3. The non-volatile memory device according to claim 1 ,wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell to be lower than the threshold voltage of the at least one dummy cell before a start of the pre-charge period.4. The non-volatile memory device according to claim 1 ,wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell to switch between a turn on voltage and a turn off voltage of the at least one dummy cell at least once in the pre-charge period.5. The non-volatile memory device according to claim 1 ,wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell to be higher than the threshold voltage of the at least one dummy cell after an end of ...

Tracking circuit

A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal.

MEMORY CIRCUIT INCLUDING TRACKING CIRCUIT

A memory circuit includes: memory cells each including a storage transistor having a first configuration; and a tracking circuit including: a tracking bit line having first and second intermediary nodes; a tracking word line; a first finger circuit (coupled between the first intermediary node and a reference voltage node) including: a first set of first tracking cells, each including a first shadow transistor having the first configuration; and a second finger circuit (coupled between the second intermediary node and the reference voltage node) including: a second set of second tracking cells, each including a second shadow transistor having the first configuration; gate terminals of the first and second shadow transistors being coupled with the tracking word line; and a switch configured to selectively couple the first intermediary node with the second intermediary node and thereby selectively couple the first and second finger circuits in parallel. 1. A memory circuit comprising:memory cells arranged in an array, each memory cell including a storage transistor corresponding to a predetermined transistor configuration; and a tracking bit line;', a first finger circuit coupled between a first intermediary node of the tracking bit line and a reference voltage node, the first finger circuit including:', 'a first set of first tracking cells, each first tracking cell including a first shadow transistor corresponding to the predetermined transistor configuration, gate terminals of the first shadow transistors being coupled with the tracking word line; and, 'a tracking word line;'}, 'a second set of second tracking cells, each second tracking cell including a second shadow transistor corresponding to the predetermined transistor configuration, gate terminals of the second shadow transistors being coupled with the tracking word line; and', 'a second finger circuit coupled between a second intermediary node of the tracking bit line and the reference voltage node, the second ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM

Disclosed are a semiconductor device and a semiconductor system. The semiconductor device includes a command processing circuit for generating a write enable signal and a read enable signal in response to a command, a data strobe signal processing circuit for generating a data strobe signal in response to a clock and the read enable signal or for receiving the data strobe signal in response to the write enable signal and outputting a write data strobe signal, and a data processing circuit for converting analog data into digital data in response to the write data strobe signal and the write enable signal and converting the digital data into the analog data in response to the read enable signal. 1. A semiconductor device , comprising:a command processing circuit configured to generate a write enable signal and a read enable signal in response to a command;a data strobe signal processing circuit configured to generate a data strobe signal in response to a clock and the read enable signal or receive the data strobe signal in response to the write enable signal and outputting a write data strobe signal; anda data processing circuit configured to convert analog data into digital data in response to the write data strobe signal and the write enable signal and convert the digital data into the analog data in response to the read enable signal.2. The semiconductor device of claim 1 , wherein the command processing circuit is configured to enable one of the write enable signal and the read enable signal by decoding the command.3. The semiconductor device of claim 2 , wherein the command processing circuit comprises:a command decoder configured to generate one of a write command and a read command by decoding the command, anda latency circuit configured to delay the write command based on a latency value and output the delayed command as the write enable signal or to delay the read command based on the latency value and output the delayed command as the read enable signal.4. ...

MEMORY MACRO AND METHOD OF OPERATING THE SAME

A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal. 1. A memory macro comprising:a first memory cell array; a first set of memory cells configured as a first set of loading cells responsive to a first control signal;', 'a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, the second control signal being inverted from the first control signal, at least the first set of pull-down cells or the first set of loading cells being configured to track a memory cell of the first memory cell array; and', 'a first tracking bit line extending over the first tracking circuit, and being coupled to the first set of memory cells and the second set of memory cells;, 'a first tracking circuit comprisinga first transistor coupled to the first tracking bit line; anda second transistor coupled to the first tracking bit line, the second transistor and the first transistor being configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.2. The memory macro of claim 1 , wherein the first tracking bit line comprises:a first conductive line extending in a first direction, and being located ...

DUAL ASYNCHRONOUS AND SYNCHRONOUS MEMORY SYSTEM

Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains. 1. A system for dual asynchronous and synchronous memory operation , the system comprising:a memory controller; and a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain;', 'a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain, the at least one memory interface port operable to access at least one memory device; and', 'a boundary layer connected to the nest domain and the memory domain, the boundary layer configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains., 'a memory buffer chip coupled to the memory controller via a synchronous channel, the memory buffer chip comprising2. The system of claim 1 , further comprising:a plurality of additional memory buffer chips coupled to the memory controller via a plurality of additional synchronous channels, the plurality of additional memory buffer chips configurable to operate synchronously with the memory buffer chip and synchronously with respect to each other in the nest domain.3. ...

MEMORY INTERFACE OFFSET SIGNALING

A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths. 1. A memory interface method , comprising:applying an operating delay to only a first set of bits of a data channel of a memory interface waveform;transmitting the delayed first set of bits across a memory interface; andtransmitting a second set of bits of the data channel across the memory interface in which the first set of bits is interwoven with the second set of bits on the data channel.2. The memory interface method of claim 1 , further comprising:applying a strobe delay to a first strobe to generate a second strobe;transmitting the first strobe and the second strobe across the memory interface;sampling the first set of bits with the first strobe; andsampling the second set of bits with the second strobe.3. The memory interface method of claim 1 , in which the first set of bits comprises only odd bits of the data channel and the second set of bits comprises only even bits of the data channel.4. The memory interface method of claim 1 , further comprising:applying a first training delay value to only the first set of bits;applying a first training strobe delay value to a first strobe;applying a second training delay value to only the first set of bits;applying a second training strobe delay value to the first strobe; andsetting the operating delay equal to the first training delay value when a first signal integrity is greater than a second signal integrity.5. The memory interface method of claim 4 , further ...

Dummy Bitline Circuitry

Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal. 1. An integrated circuit , comprising:first dummy bitline circuitry having a first charge storage element;second dummy bitline circuitry coupled to the first dummy bitline circuitry, wherein the second dummy bitline circuitry has a second charge storage element; anddecoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element,wherein the decoupling circuitry operates to decouple the second charge storage element from the first charge storage element based on an enable signal.2. The integrated circuit of claim 1 , wherein the first charge storage element is a first bitline capacitor claim 1 , and wherein the second charge storage element is a second bitline capacitor.3. The integrated circuit of claim 1 , wherein the enable signal comprises multiple enable signals including a first enable signal and a second enable signal that is a complement of the first enable signal claim 1 , and wherein the decoupling circuitry operates to decouple the second charge storage element from the first charge storage element based on the first enable signal and the second enable signal.4. The integrated circuit of claim 3 , wherein the second dummy bitline circuitry comprises a first transistor that is ...

Address control circuit and semiconductor device including the same

An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

Method of operating tracking circuit

A method of operating a tracking circuit of a memory device includes charging a node of the tracking circuit to a first predetermined voltage level, the first node being electrically coupled with a first load device. A first plurality of tracking cell transistors are activated to discharge the first node toward a second predetermined voltage level. A reset signal is generated based on a signal at the first node. The reset signal may correspond to a waiting period for reading a memory cell of the memory device.

SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

The semiconductor memory device includes an internal flag signal generator and an active information generator. The internal flag signal generator generates a plurality of internal flag signals which are selectively enabled when combination signals of bank address signals and row address signals supplied are inputted from an external device at least a predetermined number of times. The active information generator outputs a flag signal enabled when at least one of the plurality of internal flag signals is enabled in response to a start signal for extracting information on a number of times that a word line is activated and outputs a plurality of bank information signals according to the plurality of internal flag signals. The active information generator generates internal bank address signals and internal row address signals according to the plurality of internal flag signals to refresh a bank. 1. A system comprising:a memory controller configured to output a start signal for extracting information on a number of times that a word line is activated and output a refresh signal for refreshing a bank in response to a flag signal which is enabled when the word line in the bank is activated by at least a predetermined number of times; anda semiconductor memory device configured to receive the start signal to output the flag signal and a plurality of bank information signals including information on the bank having the word line activated by at least the predetermined number of times and configured to receive the refresh signal to refresh the bank including the word line2. The system of claim 1 , wherein the semiconductor memory device includes:an internal flag signal generator configured to generate a plurality of internal flag signals which are selectively enabled when combination signals of bank address signals and row address signals supplied by an external device are inputted by at least the predetermined number of times; andan active information generator ...

SEMICONDUCTOR DEVICE

A semiconductor device may include a first internal command generation circuit configured to advance a phase of a first external command in accordance with a delay time of an on die termination (ODT) path and a first latency and generate the first delay command; and a second internal command generation circuit configured to advance a phase of a second external command in accordance with a delay time of a clock path and a second latency and to generate a second delay command. 1. A semiconductor device comprising:a first internal command generation circuit configured to advance a phase of a first external command in accordance with a delay time of an on die termination (ODT) path and a first latency and generate the first delay command; anda second internal command generation circuit configured to advance a phase of a second external command in accordance with a delay time of a clock path and a second latency and to generate a second delay command.2. The semiconductor device of claim 1 , wherein the first internal command generation circuit is configured to receive the first external command claim 1 , the first latency claim 1 , a first clock claim 1 , a first delay control signal claim 1 , and a second clock.3. The semiconductor device of claim 2 , wherein the first internal command generation circuit comprises:a buffer configured to buffer the first external command to generate a buffer signal;a variable delay circuit configured to determine a delay time in response to the first delay control signal and configured to delay the buffer signal by the determined delay time to generate a first delay signal;an on-die termination (ODT) replica configured to delay the first delay signal by a replica delay time of the first DLL circuit to output a second delay signal;a pulse generation circuit configured to generate a pulse in response to the buffer signal and the second delay signal;a counter configured to perform counting operations in response to the first clock during an ...

CONTROLLER AND OPERATING METHOD THEREOF

A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period. 1. A memory system comprising:a semiconductor memory device; anda controller configured to control the semiconductor memory device,wherein the controller generates, based on a temperature of the semiconductor memory device, a dummy read command for controlling the semiconductor memory device to perform a dummy read operation.2. The memory system of claim 1 , wherein the controller comprises:a temperature sensing unit configured to generate temperature information by sensing a temperature of the semiconductor memory device;a period storage unit configured to update an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information; anda command generating unit configured to generate the dummy read command, based on the output period.3. The memory system of claim 2 , wherein the period storage unit includes a lookup table that includes an output period corresponding to each temperature range claim 2 ,wherein the period storage unit updates a currently applied output period with reference to the lookup table.4. The memory system of claim 3 , wherein claim 3 , as the temperature measured by the temperature sensing unit increases claim 3 , the period storage unit updates a shorter period as the output period.5. The memory system of claim 2 , wherein the command generating unit ...

MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME

A memory device that includes an interface that receives a data signal and a strobe signal from an external device, the strobe signal corresponding to the data signal; a strobe buffer that receives the strobe signal from the interface; a phase detection unit that detects a phase difference between the data signal output from the interface and the strobe signal output from the strobe buffer; a phase adjust unit that adjusts a phase of the strobe signal output from the strobe buffer based on the phase difference; and a sampling unit that samples the data signal output from the interface based on the strobe signal output from the phase adjust unit. 1. A memory device comprising:an interface configured to receive a data signal and a strobe signal from an external device, the strobe signal corresponding to the data signal;a strobe buffer configured to receive the strobe signal from the interface;a phase detection unit configured to detect a phase difference between the data signal output from the interface and the strobe signal output from the strobe buffer;a phase adjust unit configured to adjust a phase of the strobe signal output from the strobe buffer based on the phase difference; anda sampling unit configured to sample the data signal output from the interface based on the strobe signal output from the phase adjust unit.2. The memory device of claim 1 , wherein the data signal and the strobe signal have the same phase claim 1 , as provided by the external device.3. The memory device of claim 2 , wherein the phase difference corresponds to a delay phase difference caused by the strobe buffer.4. The memory device of claim 2 , wherein the phase detection unit is configured to determine a compensation level of the strobe signal according to the phase difference.5. The memory device of claim 4 , wherein the phase adjust unit is configured to adjust the phase of the strobe signal by delaying the strobe signal according to the compensation level.6. The memory device of ...

MEMORY CIRCUIT INCLUDING TRACKING CIRCUIT

A memory circuit includes: memory cells each including a storage transistor corresponding to a predetermined configuration; and a tracking circuit configured to elapse a variable waiting period during which a voltage on a first node decreases from a first level to a second level, the tracking circuit including a first finger circuit coupled between a first node of a tracking bit line and a reference voltage node, the first finger circuit including a first set of first tracking cells, each first tracking cell including a first shadow transistor corresponding to the predetermined configuration, gate terminals of the first shadow transistors being coupled with a tracking word line; and a second finger circuit coupled between the first node and the reference voltage node; and a first switch configured to adjust the variable waiting period by selectively coupling the second finger circuit in parallel with the first finger circuit. 1. A memory circuit comprising:memory cells arranged in an array, each memory cell including a storage transistor corresponding to a predetermined configuration; and a tracking bit line;', 'a first finger circuit coupled to a tracking word line and between a first node of the tracking bit line and a reference voltage node, the first finger circuit including a first set of first tracking cells, each first tracking cell including a first shadow transistor corresponding to the predetermined configuration, gate terminals of the first shadow transistors being coupled with the tracking word line;', 'a second finger circuit coupled between the first node and the reference voltage node; and', 'a first switch configured to adjust the variable waiting period by selectively coupling the second finger circuit in parallel with the first finger circuit., 'a tracking circuit configured to elapse a variable waiting period during which a voltage on a first node decreases from a first level to a second level, the tracking circuit including2. The memory circuit ...

SEMICONDUCTOR DEVICE

A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier. 1. A semiconductor device comprising: a plurality of word lines;', 'a plurality of pair of bit lines;', 'a plurality of static type memory cells coupled to the word lines and the pair of bit lines so that one static type memory cell of the static type memory cells the is coupled to one word line of the word lines and one pair of bit lines of the pair of bit lines;, 'a memory array including'}a sense amplifier circuit which amplifies data read out to one pair of bit lines from one memory cell and is controlled by a first signal;a timing adjustment circuit which receives a second signal and provides a third signal generated by delaying the second signal; anda first control circuit which provides the first signal in response to the third signal, a first wiring for receiving the second signal;', 'a second wiring coupled to the first wiring and providing the third signal; and', 'a first MOS transistor having a source-drain path between the first wiring and the second wiring., 'wherein the timing adjustment circuit includes2. A semiconductor device according to claim 1 ,wherein the first MOS transistor ...

MEMORY MACRO AND METHOD OF OPERATING THE SAME

A memory macro includes a first memory cell array, first tracking circuit, first pre-charge circuit coupled to a first end of the first tracking bit line and a second pre-charge circuit coupled to a second end of the first tracking bit line. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line. The first set of pull-down cells and first set of loading cells are configured to track a memory cell of the first memory cell array. The first and second pre-charge circuit are configured to charge the first tracking bit line to a voltage level responsive to a third set of control signals. 1. A memory macro comprising:a first memory cell array; a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals;', 'a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, the first set of pull-down cells and the first set of loading cells being configured to track a memory cell of the first memory cell array, the first set of memory cells and the second set of memory cells being arranged in a column of the memory macro; and', 'a first tracking bit line extending over the column of the memory macro, and being coupled to the first set of memory cells and the second set of memory cells;, 'a first tracking circuit comprisinga first pre-charge circuit coupled to a first end of the first tracking bit line; anda second pre-charge circuit coupled to a second end of the first tracking bit line, the second pre-charge circuit and the first pre-charge circuit being configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.2. The memory macro of claim 1 , further ...

MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied. 120-. (canceled)21. A memory device , comprising:an interface;a register to receive a first timing adjustment value for a first internal timing reference signal, the first internal timing reference signal based on a first external timing reference signal, the first timing adjustment value not allowing full speed operation of the interface;a first circuit to receive the first external timing reference signal; and,a first sampler circuit, the first sampler circuit to resolve at least two signal values, a first signal value of the at least two signal values to be associated with a first transition of the first external timing reference signal, a second signal value of the at least two signal values to be associated with a second transition of the first external timing reference signal.22. The memory device of claim 21 , wherein the first timing adjustment value determines a duty cycle of the first internal timing reference signal.23. The memory device of claim 21 , wherein the first internal timing reference is to be used by a plurality of sampler circuits claim ...

Read time-out managers and memory systems including the read time-out managers

A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.

APPARATUSES AND METHODS FOR MEASURING AN ELECTRICAL CHARACTERISTIC OF A MODEL SIGNAL LINE AND PROVIDING MEASUREMENT INFORMATION

Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line. 1. An apparatus , comprising:a memory array including a plurality of signal lines;a signal line driver coupled to a signal line of the plurality of signal lines and configured to provide a voltage to the signal line of the plurality of signal lines; anda signal line model measurement circuit coupled to the signal line driver, the signal line model measurement circuit configured to measure an electrical characteristic of a model signal line and provide measurement information to the signal line driver, the signal line driver configured to provide the voltage to the signal line of the plurality of signal lines based at least in part on the measurement information.2. The apparatus of claim 1 , wherein the memory array includes a three-dimensional NAND memory array.3. The apparatus of claim 1 , wherein the plurality of signal lines of the memory array include a plurality of word lines.4. The apparatus of claim 1 , wherein the signal line model measurement circuit includes a signal line model including a plurality of model signal lines.5. The apparatus of claim 4 , wherein the memory array includes a memory structure and the signal line model is configured similarly to the memory structure of the memory array.6. The apparatus of claim 4 ...

MEMORY MACRO AND METHOD OF OPERATING THE SAME

A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells. 1. A memory macro comprising: 'a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage, the first voltage being different from the second voltage;', 'a first set of memory cells arranged in columns and rows, the columns of memory cells being arranged in a first direction, the rows of memory cells being arranged in a second direction different from the first direction, each memory cell of the first set of memory cells comprisinga second set of memory cells including a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode, the set of retention circuits being responsive to a set of control signals; anda set of conductive lines being coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells, the set of retention circuits is arranged in a first column in the first direction, and the set of conductive lines extend in the second direction, or', 'the set of retention circuits is arranged in a first row in the second direction, and the set of conductive lines extend in the first direction., 'wherein the set of retention ...

Apparatus and Method for Read Time Control in ECC-Enabled Flash Memory

In a flash semiconductor memory, sense and contiguous ECC coding operations are carried out over a range of V CC values without wasted time by allocating a predetermined number of clocks to the combined operations rather than to the individual operations and operating at higher frequency for high V CC values, and lower frequency for low V CC values.

SEMICONDUCTOR STORAGE DEVICE

According to one embodiment, there is provided a semiconductor storage device including a bit cell, a dummy cell, a word line, a dummy word line, a word line driver, a dummy word line driver, a first modulation circuit, and a second modulation circuit. The word line is electrically connected to the bit cell. The dummy word line is electrically connected to the dummy cell. The word line driver is electrically connected to the word line. The dummy word line driver is electrically connected to the dummy word line. The first modulation circuit is electrically connected to the word line driver. The second modulation circuit is electrically connected to the dummy word line driver.

Nonvolatile memory system including nonvolatile memory device and memory controller and operating method of memory controller

A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is configured to count a clock to generate a current time, program dummy data at predetermined memory cells among the plurality of memory cells at a power-off state, detect a charge loss of the predetermined memory cells when a power-on state occurs after the power-off state, and restore the current time based on the detected charge loss.

Tracking bit cell and method

A method includes generating a first edge of a first tracking signal for a tracking cell, generating a first edge of a second tracking signal for the tracking cell based on the first edge of the first tracking signal, generating a first edge of a cell signal for a memory cell, generating a second edge of the first tracking signal based on the first edge of the second tracking signal, and generating a second edge of the cell signal based on the second edge of the first tracking signal. A transistor in the tracking cell operates at a tracking voltage value and a transistor in the memory cell operates at a memory voltage value different from the tracking voltage value.

SEMICONDUCTOR DEVICE

A semiconductor device may include a first internal command generation circuit, a first DLL circuit, a second internal command generation circuit, and a second DLL circuit. The first internal command generation circuit may generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock. The first DLL circuit may generate the first delay control signal and the first second clock in response to the first clock. The second internal command to generation circuit may generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock. The second DLL circuit may generate the second delay control signal and the third clock in response to the first clock. 1. A semiconductor device comprising:a first internal command generation circuit configured to generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock;a first delay-locked loop (DLL) circuit configured to generate the first delay control signal and the second clock in response to the first clock;a second internal command generation circuit configured to generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock; anda second DLL circuit configured to generate the second delay control signal and the third clock in response to the first clock.2. The semiconductor device of claim 1 , wherein a replica delay time of the first DLL circuit is different from a replica delay time of the second DLL circuit.3. The semiconductor device of claim 1 , wherein the first internal command generation circuit comprises:a buffer configured to buffer the first external command to generate a buffer signal;a variable delay circuit configured to determine a delay time in response ...

APPARATUSES AND METHODS FOR MEASURING AN ELECTRICAL CHARACTERISTIC OF A MODEL SIGNAL LINE AND PROVIDING MEASUREMENT INFORMATION

Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line. 1. An apparatus , comprising:a memory array including a plurality of signal lines;a signal line driver coupled to a signal line of the plurality of signal lines and configured to provide a voltage to the signal line of the plurality of signal lines; anda signal line model measurement circuit coupled to the signal line driver, the signal line model measurement circuit configured to measure an electrical characteristic of a model signal line and provide measurement information to the signal line driver, the signal line driver configured to provide the voltage to the signal line of the plurality of signal lines based at least in part on the measurement information.2. The apparatus of claim 1 , wherein the memory array includes a three-dimensional LAND memory array.3. The apparatus of claim 1 , wherein the plurality of signal lines of the memory array include a plurality of word lines.4. The apparatus of claim 1 , wherein the signal line model measurement circuit includes a signal line model including a plurality of model signal lines.5. The apparatus of claim 4 , wherein the memory array includes a memory structure and the signal line model is configured similarly to the memory structure of the memory array.6. The apparatus of claim 4 ...

Address control circuit and semiconductor device including the same

An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

CIRCUITRY FOR TRACKING BIAS VOLTAGE BEHAVIOR

Various implementations described herein refer to an integrated circuit having dummy wordline driver circuitry coupled to a dummy wordline and dummy bitline pulldown circuitry coupled between a dummy bitline and the dummy wordline. The integrated circuit may include dummy wordline tracking circuitry coupled to the dummy wordline between the dummy wordline driver circuitry and the dummy bitline pulldown circuitry. The dummy wordline tracking circuitry may have one or more variable capacitors that are coupled between the dummy wordline and a variable voltage source.

半导体存储器设备与定时控制方法

本发明公开了一种半导体存储器设备(10)，用于适当地控制访问存储器单元(21)的数据的定时。半导体存储器设备包括存储器单元。连接到存储器单元的位线(BL、XBL)用于访问存储器单元中存储的数据。生成第一定时信号的第一路径包括用于存储数据的伪单元(22a)。连接到伪单元的伪位线(DBL、XDBL)用于访问伪单元中存储的数据。生成第二定时信号的第二路径(23)具有不同于第一路径的延迟特性的延迟特性。控制电路(18)使用第一定时信号和第二定时信号中的一个来控制用于访问存储器单元中存储的数据的定时。

Semiconductor memory device

본 발명은 내부 제어 신호의 적정한 타이밍 마진을 설정할 수 있고, 고속인 내부 제어 신호의 타이밍 생성을 가능하게 하는 반도체 기억 장치를 제공하는 것을 목적으로 한다. An object of the present invention is to provide a semiconductor memory device capable of setting an appropriate timing margin of an internal control signal and enabling timing generation of a high speed internal control signal. 메모리 셀 어레이에 대하여 디코더로부터 워드선 방향의 거리가 다른 지점에 추가된 적어도 2쌍의 더미 비트선과, 더미 비트선의 한쌍에 접속된 제1 더미 셀 어레이와, 더미 비트선의 다른쌍에 접속된 제2 더미 셀 어레이와, 디코더로부터 송출되어 제1 더미 셀 어레이를 통해 더미 비트선을 통과한 제1 신호 및 디코더로부터 송출되어 제2 더미 셀 어레이를 통해 더미 비트선을 통과한 제2 신호에 기초하여 입출력 래치 회로에 대한 내부 제어 신호의 타이밍을 생성하는 타이밍 제어 회로를 구성한다. At least two pairs of dummy bit lines added at different points in the word line direction from the decoder with respect to the memory cell array, a first dummy cell array connected to one pair of dummy bit lines, and a second connected to another pair of dummy bit lines Input / output based on the dummy cell array and the first signal sent from the decoder and passed through the dummy bit line through the first dummy cell array and the second signal sent from the decoder and passed through the dummy bit line through the second dummy cell array. Configure a timing control circuit that generates the timing of the internal control signal for the latch circuit.

비트라인 프리차아지 시간(ｔＲＰ)을 개선하는 메모리 셀어레이 구조를 갖는 반도체 메모리 장치 및 그 개선 방법

본 발명은 비트라인 프리차아지 시간(tRP)을 개선하는 메모리 셀 어레이 구조를 갖는 반도체 메모리 장치 및 그 개선 방법에 대하여 기술된다. 메모리 셀 어레이 구조는 공유 센스앰프 구조에 있어서 다수개의 메모리 셀 블락들과 제1 센스앰프부, 제2 센스앰프부 및 더미 커패시터 영역을 포함한다. 제1 센스앰프부는 인접한 메모리 셀 블락들 사이에 배치되어 메모리 셀 블락들에 공유되고 메모리 셀들의 데이터를 감지증폭한다. 제2 센스앰프부는 메모리 셀 블락들 중 에지쪽의 메모리 셀 블락과 연결되어 메모리 셀 데이터를 감지증폭한다. 더미 커패시터 영역은 제2 센스앰프부를 통하여 에지쪽 메모리 셀 블락의 비트라인 및 상보 비트라인과 각각 연결되는 더미 비트라인 및 상보 더미 비트라인 사이에 다수개의 커패시터들을 구비한다. 커패시터들은 비트라인의 라인 커패시턴스에 해당하는 값의 커패시턴스를 갖도록 설정되고 메모리 셀 커패시터로 구성될 수 있다.

Magnetic memory device and operating method thereof

A magnetic memory device according to the present technology includes a bit line, a plurality of source lines, a switching element connected between a bit line and a plurality of source lines, each of which is connected in series with a magnetoresistive element and the magnetoresistive element and switched by a word line signal. A plurality of general cells, including dummy cells connected to bit lines; And a spin hole effect material layer formed on an adjacent surface of the bit line and the magnetoresistive element, wherein the magnetoresistive element passes through the first current and the magnetoresistive element flowing through the dummy cell and flowing in a direction parallel to the magnetoresistive element. The data is recorded according to the second current flowing therethrough.

Using a reference bit line in a memory

方法、存储器和系统可以包括将感测节点充电至逻辑高电压电平，以及在至少部分地基于用于参考位线的电压达到参考电压的时间的预充电时段内向位线和参考位线供应电荷。在预充电时段之后可以选择耦合到位线的存储器单元，并且可以至少部分地基于参考位线的电压设置钳位电压。在感测时段期间如果位线的电压电平小于钳位电压电平则可以从感测节点排出电荷，并且可以至少部分地基于接近感测时段的结尾的感测节点的电压电平确定存储器单元的状态。

Semiconductor memory device

본 발명은 전원 투입시에 있어서, 모든 셀 커패시터의 전하 축적 노드에는 축적 전하가 존재하지 않는 상태로부터 액세스 동작으로 이행하는 경우에 있어서도, 셀 플레이트 전위가 변동하지 않는 반도체 기억 장치를 제공하는 것을 목적으로 한다. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device in which the cell plate potential does not change even when the power is turned on, even in the case where the charge accumulation nodes of all the cell capacitors do not have accumulated charges, and the transition to the access operation is performed. do. 기준 전압 발생 회로(104)로부터의 기준 전압(VPR, VCP)의 공급선인 VPR선, VCP선에 대해서, 각 셀 블록(B1 내지 Bk)마다 양 선을 접속하는 NMOS 트랜지스터(M1 내지 Mk)를 구비한다. NMOS 트랜지스터(M1 내지 Mk)의 게이트 단자는 공통으로 신호(φCPR)에 접속된다. 여기서, φCPR은 전원 투입후의 사전 결정된 시간에 플러스의 논리 레벨을 출력하는 신호이다. 각 셀 블록(B1 내지 Bk)마다 VPR선과 VCP선을 단락하는 NMOS 트랜지스터(M1 내지 Mk)를 구비함으로써, 전원 투입시에 양 배선이 각 셀 블록(B1 내지 Bk)마다 분로(shunt)된다. NMOS transistors M1 to Mk are connected to VPR lines and VCP lines, which are supply lines of the reference voltages VPR and VCP from the reference voltage generating circuit 104, for both cell blocks B1 to Bk. do. Gate terminals of the NMOS transistors M1 to Mk are commonly connected to the signal φ CPR. Here, φ CPR is a signal that outputs a positive logic level at a predetermined time after power-up. By providing the NMOS transistors M1 to Mk for shorting the VPR line and the VCP line for each cell block B1 to Bk, both wirings are shunted for each cell block B1 to Bk at power-on.

Input circuit and semiconductor integrated circuit having the input circuit

동기 DRAM에 있어서, 자체 재생 상태에 들어갔을 때에는 입력 회로를 비활성 상태로 하여 소비 전력의 감소를 도모하도록 되어 있지만, DLL 회로가 다시 로크온(lock-on)할 때까지 많은 더미 사이클을 필요로 하여 불필요한 시간이 걸린다. 입력되는 외부 제어 신호 CLK를 수신하여 내부 제어 신호 S1을 출력하는 입력 버퍼(210)와 상기 외부 제어 신호 CLK가 동작하는지의 여부를 검출하는 제어 신호 검출 회로(220)를 구비하고, 상기 입력 버퍼(210)는 상기 제어 신호 검출 회로(220)의 출력에 의해 상기 외부 제어 신호 CLK가 동작할 때 상기 내부 클럭 신호 S1을 출력하도록 구성된다.

Semiconductor memory device

【課題】回路素子の増大を抑制しつつ、高速化を実現し、あるいはメモリセルの特性バラツキに反映されたタイミング調整が可能な半導体記憶装置を提供する。 【解決手段】メモリアレイの相補ビット線に対応した第１ダミー線と第２ダミー線と、スタティック型メモリセルと同じ形態で形成され、書き込み電流経路が上記第１ダミー線と第２ダミー線との間に接続された複数の第１ダミーセルとで書き込みダミービットを構成する。上記書き込みダミービットは、上記スタティック型メモリセルへの書き込み信号入力に対応して駆動ＭＯＳＦＥＴにより一方のレベルが上記第１ダミー線に入力され、他方のレベルにプリチャージされた上記第２ダミー線の信号変化をセンスして出力させる。タイミング制御回路は、上記書き込みダミービットからの出力信号により選択されたワード線を非選択状態にする。 【選択図】図１

Differential static random access memory cell

The present invention discloses a static random access memory cell capable of differential operation. According to an embodiment of the present invention, a static random access memory cell includes a data node portion including four transistors constituting a first data node and a second data node, a data node portion including four transistors constituting a first data node and a second data node, A data control unit including first and second pass-gate transistors for controlling a read and a write, and a data driver connected to the data node unit through the two data nodes, And a control transistor controlled based on the driving voltage of the second word line having the opposite polarity to the word line.

Semiconductor device having active delay circuit and method therefor

본 발명은 PVT 변동에 따른 지연 변화를 조절할 수 있는 능동적 지연회로를 갖는 반도체 소자 및 이를 위한 방법을 제공하기 위한 것으로, 이를 위한 본 발명은 워드라인 구동신호를 소정시간 지연시켜 비트라인 감지증폭기 구동신호로 출력하는 지연회로를 갖는 반도체 소자에 있어서, 상기 지연회로는 직렬 연결된 복수개의 지연소자로 분할 구성되고, 내부클럭을 사용하여 상기 워드라인 구동신호가 활성화된 시점부터 서로 다른 지연값을 갖는 복수의 지연펄스신호를 생성하는 지연펄스신호 생성수단; 상기 비트라인 감지증폭기 구동신호의 활성화 시점을 검출하여 검출펄스신호를 생성하는 검출수단; 및 상기 검출펄스신호와 상기 복수의 지연펄스신호를 비교하여 상기 복수의 지연소자를 제어하기 위한 지연량 조절수단을 포함하는 반도체 소자를 제공한다. The present invention is to provide a semiconductor device having an active delay circuit that can adjust the delay change according to the PVT fluctuation, and a method therefor. The present invention is to delay the word line driving signal by a predetermined time for the bit line detection amplifier driving signal In a semiconductor device having a delay circuit for outputting the signal, the delay circuit is divided into a plurality of delay elements connected in series, and has a plurality of delay values different from the time when the word line driving signal is activated using an internal clock. Delay pulse signal generating means for generating a delay pulse signal; Detection means for detecting an activation time of the bit line detection amplifier driving signal to generate a detection pulse signal; And delay amount adjusting means for controlling the plurality of delay elements by comparing the detection pulse signal with the plurality of delay pulse signals. tRCD, 지연, 동작 주파수, Bin Portion, 자동 tRCD, delay, operating frequency, bin portion, auto

Memory device having latency control circuit for controlling data write and read latency

데이터 기입 및 독출 레이턴시를 제어하는 레이턴시 제어 회로를 갖는 메모리 장치가 개시된다. 메모리 장치는 클럭 신호에 응답하여 기입 커맨드에 따른 기입 레이턴시에 데이터 입력 경로 상의 지연 시간을 미리 보상하여 기입 레이턴시 제어 신호를 발생하는 레이턴시 제어 회로를 포함한다. 기입 레이턴시 제어 신호에 응답하여 데이터 버스로 입력되는 기입 데이터들이 바로 얼라인되고 래치되어 메모리 셀 어레이로 제공될 수 있다.

For providing commands to order path, the device and method of data block

本发明涉及用于将命令提供到数据块的命令路径、设备及方法。在实例性命令路径中，命令接收器经配置以接收命令，且命令缓冲器耦合到所述命令接收器且经配置以接收所述命令并提供经缓冲命令。命令块耦合到所述命令缓冲器以接收所述经缓冲命令。所述命令块经配置以响应于时钟信号而提供所述经缓冲命令且进一步经配置以将延迟添加到所述经缓冲命令，所述延迟至少部分地基于移位计数。命令树耦合到所述命令块以接收所述经缓冲命令且经配置以将所述经缓冲命令分配给数据块。

Nonvolatile memory device and operating method of nonvolatile memory device

본 발명의 실시 예에 따른 불휘발성 메모리 장치는, 메모리 셀들 및 더미 셀들을 포함하는 메모리 셀 어레이, 워드 라인들을 통해 메모리 셀들에 연결되는 행 디코더, 더미 워드 라인들을 통해 더미 셀들에 연결되는 더미 워드 라인 바이어스 회로, 비트 라인들을 통해 메모리 셀들에 연결되는 쓰기 드라이버 및 감지 증폭기 회로, 그리고 더미 비트 라인을 통해 더미 셀들에 연결되는 더미 비트 라인 바이어스 회로를 포함한다. A nonvolatile memory device according to an embodiment of the present invention includes a memory cell array including memory cells and dummy cells, a row decoder connected to the memory cells through word lines, and a dummy word line connected to the dummy cells through dummy word lines. a bias circuit, a write driver and sense amplifier circuit coupled to the memory cells via bit lines, and a dummy bit line bias circuit coupled to the dummy cells via a dummy bit line.

Circuit for varying sensing margin and semiconductor memory device comprising thereof

센싱마진 가변회로 및 이를 구비하는 반도체 메모리 장치가 개시된다. 본 발명의 실시예에 따른 반도체 메모리 장치는 더미 컬럼부, 제어부, 감지증폭부, 및 센싱마진 제어부를 구비한다. 더미 컬럼부는 데이터 판독시 인에이블되는 데이터인에이블신호 및 데이터제어신호에 응답하여 비트 셀 어레이로부터 출력되는 비트쌍을 감지될 때 까지의 센싱마진을 제어한다. 제어부는 상기 레디 신호에 응답하여 센싱인에이블신호를 출력한다. 감지증폭부는 상기 센싱인에이블신호에 응답하여 비트 셀 어레이로부터 출력되는 비트쌍을 감지한다. 상기 레디신호의 스큐를 조정함으로써 상기 비트쌍이 출력되어 감지될 때까지의 센싱마진을 제어한다. 본 발명의 실시예에 따른 센싱마진 가변회로는 미세공정 또는 고속 저전압 설계시의 변화요인으로 인해 SRAM의 센싱마진이 부족해지거나 속도가 늦어졌을 때 센싱마진 또는 속도를 조정할 수 있는 장점이 있다. 센싱마진, SRAM

Semiconductor devices

本发明提供一种具有存储器的半导体器件，所述存储器在操作时序上的变化减少。例如，所述半导体器件设置有与位线正本并排布置的虚设位线和顺序耦合至所述虚设位线的列方向负载电路。各列方向负载电路设置有固定在截止状态的多个NMOS晶体管，所述多个NMOS晶体管中的预先确定的一些NMOS晶体管使源极和漏极适当地耦合至所述虚设位线中的任一个虚设位线。将伴随预先确定的NMOS晶体管的扩散层电容的负载电容加至所述虚设位线，并且对应于所述负载电容，设置从译码激活信号至虚设位线信号的延迟时间。当设置读出放大器的启动时序时，采用所述虚设位线信号。

Determining optimal time instances to sense the output of a memory array

최적의 시간 인스턴스에서 감지 인에이블 신호를 발생시키는 메모리 장치에 있는 추적 회로가 개시된다. 추적 회로는 다수의 더미 셀(220, 230, 240)을 갖는 스케일러블 드라이버 블록을 포함하고, 각각은 메모리 어레이(120)에 있는 셀의 구동 강도와 동일한 구동 강도를 갖는다. 더미 셀은 턴 온되어 메모리 어레이에 있는 메모리 셀이 하듯이 컬럼을 구동한다. 결과적으로, 스케일러블 드라이버 블록은 적어도 로우의 수가 많을 때 컬럼(컬럼에 있는 다수의 로우)에 의해 유발되는 지연을 어림잡는다. 역 제어 로직은 로우의 수가 비교적 적은 경우의 지연을 에뮬레이션하고, 역 제어 로직과 스케일러블 드라이버 블록들 중 하나는 감지 동작을 트리거하기 위해 이용되는 펄스를 제공한다. A tracking circuit in a memory device that generates a sense enable signal at an optimal time instance is disclosed. The tracking circuit includes a scalable driver block having a plurality of dummy cells 220, 230, 240, each having a drive strength equal to the drive strength of the cells in the memory array 120. The dummy cell is turned on to drive the column as the memory cells in the memory array do. As a result, the scalable driver block approximates the delay caused by the column (multiple rows in the column) when at least the number of rows is large. Inverse control logic emulates a delay when the number of rows is relatively small, and one of the inverse control logic and scalable driver blocks provides a pulse that is used to trigger a sensing operation. 메모리, 지연, 에뮬레이션, 제어, 로직, 감지, 추적, 구동 Memory, Delay, Emulation, Control, Logic, Sense, Trace, Drive

Memory components and controllers that calibrate multiphase synchronous timing references

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Self-time scheme to reduce cycle time for memories

A self-time circuit and method are presented for reducing the write cycle time in semiconductor memory. A “dummy” memory cell having the same timing requirements as the functional cells, and associated write logic are added to the standard circuitry of the memory device. The dummy write cell receives the same control signals used to write data to the functional cells of the memory, and is configured to issue a completion signal when a write access is concluded, causing the write cycle to be terminated. The circuit and method disclosed herein thus permit write cycle time to be reduced to the lowest practical value, independently of the read cycle time. This potentially increases the overall operating speed of the memory device. The circuit and method disclosed herein are adaptable to the most common types of memory devices, such as SRAM, DRAM and CAM.

Control method and controller for program pause and resume of memory

一种用于存储器阵列的控制方法，该控制方法包括：在编程阶段中对存储器阵列的位单元进行编程；以及在放电阶段中对存储器阵列的位单元进行放电；其中，编程阶段包括：利用多个编程电压脉冲对存储器阵列的位单元进行编程；其中，放电阶段包括：隔离存储器阵列的位单元的选择线；以及生成对存储器阵列的位单元的编程电压脉冲；其中，编程阶段可以是在放电阶段之后通过暂停命令被暂停到暂停阶段的；其中，暂停命令是在多个编程电压脉冲中的一个编程电压脉冲期间接收的。