SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor memory device for improving speed, adjusting, timing in consideration of variation of characteristics of memory cells and suppressing increase in circuit elements.

SOLUTION: A write dummy bit is constituted of a first dummy line and a second dummy line corresponding to complementary bit lines of a memory array and a plurality of first dummy cells which are formed in the same form as a static type memory cell and a write current path is connected between the first dummy line and the second dummy line. In the write dummy bit, one of levels is inputted to the first dummy line by a drive MOSFET corresponding to a write signal input for the static type memory cell, signal change of the second dummy line pre-charged to the other level is sensed and output. A timing control circuit sets a word line selected by the output signal from the write dummy bit in a non-selection state.

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