Silica-based uniwafer optoelectronic integration receiving chip used for automatic electricity meter reading system

1. For automatic power meter reading system of a monolithic optoelectronic integrated receiving chip silicio, characterized in that is provided with a silicon-based photo-detector and the silicon photo-detector following amplifying integrated circuit;

Said silicon based photoelectric detector uses "N+ / N-Well/P-Sub" structure, silicon-based opto-electronic detector is sequentially from bottom to top of the vertical structure: 1st layer is a low-doped P-type silicon substrate; 2nd layer is well N; 3rd layer is N-type heavy doped silicon, P-type heavy doped silicon, metal aluminum; 4th layer to the 6th layer is a three-layer SiO₂ insulating dielectric layer; layer is the 7th Si₃ N₄ surface-passivation layer; said P-type silicon substrate, well N, N-type heavy doped silicon, P-type heavy doped silicon is provided with a silicon material, metal aluminum by a sputtering process is deposited on the surface of the silicon chip, from top to bottom according to preparation sequence three-layer SiO₂, the insulating dielectric layer by a deposition process of the silicon substrate to, Si₃ N₄ through the surface-passivation layer attached to the deposition process SiO₂ on the insulating medium; said silicon based photoelectric detector following amplifying integrated circuit is equipped with a transimpedance pre-amplifier, the limiting amplifier and the differential output buffer circuit, the input end of the transimpedance pre-amplifier of a silicon-based photo-detector, the output terminal of the transimpedance pre-amplifier input terminal of the limiting amplifier, the limiting amplifier output end of the input end of the differential output buffer circuit.

2. The means for automatic power meter reading system of a monolithic optoelectronic integrated receiving chip silicio according to Claim 1, characterized in that the silicon-based opto-electronic detector of all longitudinal dimension of the standard CMOS by specific decision process, the first implantation P-Substrate layer, such as layer P-Substrate injected into the space between the strip N well region 26 a, above each of the well N N-type heavy doped silicon, that is, 26 a-type heavy doped silicon region N, the transverse structure in order to is in the intermediate section 13, 14 in each distributed symmetrically N well as the center, wherein 13 each covered by the metal Al N trap, receiving the optical signal, to form the reference detector; the remaining 13 a is not metal Al N trap cover, as a practical detector, receiving the optical signal; the metal shielding the reference detector and not by the metal shielding of the actual detector are placed, and are respectively connected.

3. The means for automatic power meter reading system of a monolithic optoelectronic integrated receiving chip silicio according to Claim 1, is characterized in that the silicon based optoelectronic detector for the effective photosensitive area of the 200 the  m× 200  m, its overall transverse size is 200 the  m.

4. The means for automatic power meter reading system of a monolithic optoelectronic integrated receiving chip silicio according to Claim 1, is characterized in that the silicon based photoelectric detector each strip of the length of the trap N the 200  m; each N trap width for the 3.8  m, each strip N well interval is the 4.0  m; wherein the width of the shield metal is the lx=7.8  m, each of the strip-shaped shielding metal ly=7.8  m, detector area is 200 the the  m× 200  m, N N-type heavy doped silicon distance not less than the edge of the well of the 0.4  m, not less than the width of the 0.8  m, in 26 a N-type heavy doped silicon region P-Substrate on the periphery of the layer thickness is 2.1 the annular   m P-type heavy doped silicon, forming the protection ring, with other detector isolating the role of the CMOS device.

5. The means for automatic power meter reading system of a monolithic optoelectronic integrated receiving chip silicio according to Claim 1, is characterized in that the silicon based photoelectric detector utilize the CMOS process in the metal aluminum covered on the upper surface of the trap N N type heavily doped as a cathode of the detector, is not metal aluminum covered on the upper surface of the trap N N type heavily doped as a detector of another cathode, two cathode respectively as follow-up to two input differential circuit; peripheral annular P-type heavily doped silicon as an anode lead-out, and zero voltage; a P+ N well and a diode, said work diode D0, N well to the substrate to form a two-electrode tube, said shielding diode DS; a forward voltage N+ electrode, electrode P+, P+ protection ring and adds zero voltage on the substrate P, the diode D0 and shielding diode DS are reverse-bias; the deep part of the substrate is shielded photogenerated carriers absorbed by the depletion region of the diode, the diode can be spread to the work, without long distance work diode the proliferation of the photo-generated carriers, only short diffusion well N the carrier.